2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/blkdev.h>
22 #include <linux/errno.h>
24 #include <linux/genhd.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/pci.h>
35 #include <linux/poison.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/types.h>
39 #include <linux/version.h>
41 #define NVME_Q_DEPTH 1024
42 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
43 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
44 #define NVME_MINORS 64
45 #define IO_TIMEOUT (5 * HZ)
46 #define ADMIN_TIMEOUT (60 * HZ)
48 static int nvme_major;
49 module_param(nvme_major, int, 0);
51 static int use_threaded_interrupts;
52 module_param(use_threaded_interrupts, int, 0);
54 static DEFINE_SPINLOCK(dev_list_lock);
55 static LIST_HEAD(dev_list);
56 static struct task_struct *nvme_thread;
59 * Represents an NVM Express device. Each nvme_dev is a PCI function.
62 struct list_head node;
63 struct nvme_queue **queues;
65 struct pci_dev *pci_dev;
66 struct dma_pool *prp_page_pool;
67 struct dma_pool *prp_small_pool;
71 struct msix_entry *entry;
72 struct nvme_bar __iomem *bar;
73 struct list_head namespaces;
80 * An NVM Express namespace is equivalent to a SCSI LUN
83 struct list_head list;
86 struct request_queue *queue;
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
98 struct device *q_dmadev;
101 struct nvme_command *sq_cmds;
102 volatile struct nvme_completion *cqes;
103 dma_addr_t sq_dma_addr;
104 dma_addr_t cq_dma_addr;
105 wait_queue_head_t sq_full;
106 wait_queue_t sq_cong_wait;
107 struct bio_list sq_cong;
115 unsigned long cmdid_data[];
119 * Check we didin't inadvertently grow the command struct
121 static inline void _nvme_check_size(void)
123 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
124 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
125 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
130 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
131 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
134 struct nvme_cmd_info {
136 unsigned long timeout;
139 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
141 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
145 * alloc_cmdid() - Allocate a Command ID
146 * @nvmeq: The queue that will be used for this command
147 * @ctx: A pointer that will be passed to the handler
148 * @handler: The ID of the handler to call
150 * Allocate a Command ID for a queue. The data passed in will
151 * be passed to the completion handler. This is implemented by using
152 * the bottom two bits of the ctx pointer to store the handler ID.
153 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
154 * We can change this if it becomes a problem.
156 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
159 int depth = nvmeq->q_depth - 1;
160 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
163 BUG_ON((unsigned long)ctx & 3);
166 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
169 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
171 info[cmdid].ctx = (unsigned long)ctx | handler;
172 info[cmdid].timeout = jiffies + timeout;
176 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
177 int handler, unsigned timeout)
180 wait_event_killable(nvmeq->sq_full,
181 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
182 return (cmdid < 0) ? -EINTR : cmdid;
186 * If you need more than four handlers, you'll need to change how
187 * alloc_cmdid and nvme_process_cq work. Consider using a special
188 * CMD_CTX value instead, if that works for your situation.
191 sync_completion_id = 0,
195 /* Special values must be a multiple of 4, and less than 0x1000 */
196 #define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id)
197 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
198 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
199 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
200 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
202 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
205 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
207 if (cmdid >= nvmeq->q_depth)
208 return CMD_CTX_INVALID;
209 data = info[cmdid].ctx;
210 info[cmdid].ctx = CMD_CTX_COMPLETED;
211 clear_bit(cmdid, nvmeq->cmdid_data);
212 wake_up(&nvmeq->sq_full);
216 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
218 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
219 info[cmdid].ctx = CMD_CTX_CANCELLED;
222 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
224 int qid, cpu = get_cpu();
225 if (cpu < ns->dev->queue_count)
228 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
229 return ns->dev->queues[qid];
232 static void put_nvmeq(struct nvme_queue *nvmeq)
238 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
239 * @nvmeq: The queue to use
240 * @cmd: The command to send
242 * Safe to use from interrupt context
244 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
248 spin_lock_irqsave(&nvmeq->q_lock, flags);
249 tail = nvmeq->sq_tail;
250 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
251 if (++tail == nvmeq->q_depth)
253 writel(tail, nvmeq->q_db);
254 nvmeq->sq_tail = tail;
255 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
262 dma_addr_t first_dma;
266 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
268 const int last_prp = PAGE_SIZE / 8 - 1;
275 prp_dma = prps->first_dma;
277 if (prps->npages == 0)
278 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
279 for (i = 0; i < prps->npages; i++) {
280 __le64 *prp_list = prps->list[i];
281 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
282 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
283 prp_dma = next_prp_dma;
291 struct nvme_prps *prps;
292 struct scatterlist sg[0];
295 /* XXX: use a mempool */
296 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
298 return kzalloc(sizeof(struct nvme_bio) +
299 sizeof(struct scatterlist) * nseg, gfp);
302 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
304 nvme_free_prps(nvmeq->dev, nbio->prps);
308 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
309 struct nvme_completion *cqe)
311 struct nvme_bio *nbio = ctx;
312 struct bio *bio = nbio->bio;
313 u16 status = le16_to_cpup(&cqe->status) >> 1;
315 dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
316 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
317 free_nbio(nvmeq, nbio);
319 bio_endio(bio, -EIO);
320 if (bio->bi_vcnt > bio->bi_idx) {
321 bio_list_add(&nvmeq->sq_cong, bio);
322 wake_up_process(nvme_thread);
328 /* length is in bytes */
329 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
330 struct nvme_common_command *cmd,
331 struct scatterlist *sg, int length)
333 struct dma_pool *pool;
334 int dma_len = sg_dma_len(sg);
335 u64 dma_addr = sg_dma_address(sg);
336 int offset = offset_in_page(dma_addr);
339 int nprps, npages, i, prp_page;
340 struct nvme_prps *prps = NULL;
342 cmd->prp1 = cpu_to_le64(dma_addr);
343 length -= (PAGE_SIZE - offset);
347 dma_len -= (PAGE_SIZE - offset);
349 dma_addr += (PAGE_SIZE - offset);
352 dma_addr = sg_dma_address(sg);
353 dma_len = sg_dma_len(sg);
356 if (length <= PAGE_SIZE) {
357 cmd->prp2 = cpu_to_le64(dma_addr);
361 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
362 npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
363 prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
365 if (nprps <= (256 / 8)) {
366 pool = dev->prp_small_pool;
369 pool = dev->prp_page_pool;
370 prps->npages = npages;
373 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
374 prps->list[prp_page++] = prp_list;
375 prps->first_dma = prp_dma;
376 cmd->prp2 = cpu_to_le64(prp_dma);
379 if (i == PAGE_SIZE / 8) {
380 __le64 *old_prp_list = prp_list;
381 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
382 prps->list[prp_page++] = prp_list;
383 prp_list[0] = old_prp_list[i - 1];
384 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
387 prp_list[i++] = cpu_to_le64(dma_addr);
388 dma_len -= PAGE_SIZE;
389 dma_addr += PAGE_SIZE;
397 dma_addr = sg_dma_address(sg);
398 dma_len = sg_dma_len(sg);
404 /* NVMe scatterlists require no holes in the virtual address */
405 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
406 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
408 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
409 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
411 struct bio_vec *bvec, *bvprv = NULL;
412 struct scatterlist *sg = NULL;
413 int i, old_idx, length = 0, nsegs = 0;
415 sg_init_table(nbio->sg, psegs);
416 old_idx = bio->bi_idx;
417 bio_for_each_segment(bvec, bio, i) {
418 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
419 sg->length += bvec->bv_len;
421 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
423 sg = sg ? sg + 1 : nbio->sg;
424 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
428 length += bvec->bv_len;
434 if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
435 bio->bi_idx = old_idx;
441 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
444 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
446 memset(cmnd, 0, sizeof(*cmnd));
447 cmnd->common.opcode = nvme_cmd_flush;
448 cmnd->common.command_id = cmdid;
449 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
451 if (++nvmeq->sq_tail == nvmeq->q_depth)
453 writel(nvmeq->sq_tail, nvmeq->q_db);
458 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
460 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
461 sync_completion_id, IO_TIMEOUT);
462 if (unlikely(cmdid < 0))
465 return nvme_submit_flush(nvmeq, ns, cmdid);
468 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
471 struct nvme_command *cmnd;
472 struct nvme_bio *nbio;
473 enum dma_data_direction dma_dir;
474 int cmdid, length, result = -ENOMEM;
477 int psegs = bio_phys_segments(ns->queue, bio);
479 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
480 result = nvme_submit_flush_data(nvmeq, ns);
485 nbio = alloc_nbio(psegs, GFP_ATOMIC);
491 cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
492 if (unlikely(cmdid < 0))
495 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
496 return nvme_submit_flush(nvmeq, ns, cmdid);
499 if (bio->bi_rw & REQ_FUA)
500 control |= NVME_RW_FUA;
501 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
502 control |= NVME_RW_LR;
505 if (bio->bi_rw & REQ_RAHEAD)
506 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
508 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
510 memset(cmnd, 0, sizeof(*cmnd));
511 if (bio_data_dir(bio)) {
512 cmnd->rw.opcode = nvme_cmd_write;
513 dma_dir = DMA_TO_DEVICE;
515 cmnd->rw.opcode = nvme_cmd_read;
516 dma_dir = DMA_FROM_DEVICE;
519 result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
524 cmnd->rw.command_id = cmdid;
525 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
526 nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
528 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
529 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
530 cmnd->rw.control = cpu_to_le16(control);
531 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
533 bio->bi_sector += length >> 9;
535 if (++nvmeq->sq_tail == nvmeq->q_depth)
537 writel(nvmeq->sq_tail, nvmeq->q_db);
542 free_nbio(nvmeq, nbio);
548 * NB: return value of non-zero would mean that we were a stacking driver.
549 * make_request must always succeed.
551 static int nvme_make_request(struct request_queue *q, struct bio *bio)
553 struct nvme_ns *ns = q->queuedata;
554 struct nvme_queue *nvmeq = get_nvmeq(ns);
557 spin_lock_irq(&nvmeq->q_lock);
558 if (bio_list_empty(&nvmeq->sq_cong))
559 result = nvme_submit_bio_queue(nvmeq, ns, bio);
560 if (unlikely(result)) {
561 if (bio_list_empty(&nvmeq->sq_cong))
562 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
563 bio_list_add(&nvmeq->sq_cong, bio);
566 spin_unlock_irq(&nvmeq->q_lock);
572 struct sync_cmd_info {
573 struct task_struct *task;
578 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
579 struct nvme_completion *cqe)
581 struct sync_cmd_info *cmdinfo = ctx;
582 if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
584 if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
586 if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
587 dev_warn(nvmeq->q_dmadev,
588 "completed id %d twice on queue %d\n",
589 cqe->command_id, le16_to_cpup(&cqe->sq_id));
592 if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
593 dev_warn(nvmeq->q_dmadev,
594 "invalid id %d completed on queue %d\n",
595 cqe->command_id, le16_to_cpup(&cqe->sq_id));
598 cmdinfo->result = le32_to_cpup(&cqe->result);
599 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
600 wake_up_process(cmdinfo->task);
603 typedef void (*completion_fn)(struct nvme_queue *, void *,
604 struct nvme_completion *);
606 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
610 static const completion_fn completions[4] = {
611 [sync_completion_id] = sync_completion,
612 [bio_completion_id] = bio_completion,
615 head = nvmeq->cq_head;
616 phase = nvmeq->cq_phase;
621 unsigned char handler;
622 struct nvme_completion cqe = nvmeq->cqes[head];
623 if ((le16_to_cpu(cqe.status) & 1) != phase)
625 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
626 if (++head == nvmeq->q_depth) {
631 data = free_cmdid(nvmeq, cqe.command_id);
633 ptr = (void *)(data & ~3UL);
634 completions[handler](nvmeq, ptr, &cqe);
637 /* If the controller ignores the cq head doorbell and continuously
638 * writes to the queue, it is theoretically possible to wrap around
639 * the queue twice and mistakenly return IRQ_NONE. Linux only
640 * requires that 0.1% of your interrupts are handled, so this isn't
643 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
646 writel(head, nvmeq->q_db + 1);
647 nvmeq->cq_head = head;
648 nvmeq->cq_phase = phase;
653 static irqreturn_t nvme_irq(int irq, void *data)
656 struct nvme_queue *nvmeq = data;
657 spin_lock(&nvmeq->q_lock);
658 result = nvme_process_cq(nvmeq);
659 spin_unlock(&nvmeq->q_lock);
663 static irqreturn_t nvme_irq_check(int irq, void *data)
665 struct nvme_queue *nvmeq = data;
666 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
667 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
669 return IRQ_WAKE_THREAD;
672 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
674 spin_lock_irq(&nvmeq->q_lock);
675 cancel_cmdid_data(nvmeq, cmdid);
676 spin_unlock_irq(&nvmeq->q_lock);
680 * Returns 0 on success. If the result is negative, it's a Linux error code;
681 * if the result is positive, it's an NVM Express status code
683 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
684 struct nvme_command *cmd, u32 *result, unsigned timeout)
687 struct sync_cmd_info cmdinfo;
689 cmdinfo.task = current;
690 cmdinfo.status = -EINTR;
692 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
696 cmd->common.command_id = cmdid;
698 set_current_state(TASK_KILLABLE);
699 nvme_submit_cmd(nvmeq, cmd);
702 if (cmdinfo.status == -EINTR) {
703 nvme_abort_command(nvmeq, cmdid);
708 *result = cmdinfo.result;
710 return cmdinfo.status;
713 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
716 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
719 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
722 struct nvme_command c;
724 memset(&c, 0, sizeof(c));
725 c.delete_queue.opcode = opcode;
726 c.delete_queue.qid = cpu_to_le16(id);
728 status = nvme_submit_admin_cmd(dev, &c, NULL);
734 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
735 struct nvme_queue *nvmeq)
738 struct nvme_command c;
739 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
741 memset(&c, 0, sizeof(c));
742 c.create_cq.opcode = nvme_admin_create_cq;
743 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
744 c.create_cq.cqid = cpu_to_le16(qid);
745 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
746 c.create_cq.cq_flags = cpu_to_le16(flags);
747 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
749 status = nvme_submit_admin_cmd(dev, &c, NULL);
755 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
756 struct nvme_queue *nvmeq)
759 struct nvme_command c;
760 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
762 memset(&c, 0, sizeof(c));
763 c.create_sq.opcode = nvme_admin_create_sq;
764 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
765 c.create_sq.sqid = cpu_to_le16(qid);
766 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
767 c.create_sq.sq_flags = cpu_to_le16(flags);
768 c.create_sq.cqid = cpu_to_le16(qid);
770 status = nvme_submit_admin_cmd(dev, &c, NULL);
776 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
778 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
781 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
783 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
786 static void nvme_free_queue(struct nvme_dev *dev, int qid)
788 struct nvme_queue *nvmeq = dev->queues[qid];
790 free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
792 /* Don't tell the adapter to delete the admin queue */
794 adapter_delete_sq(dev, qid);
795 adapter_delete_cq(dev, qid);
798 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
799 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
800 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
801 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
805 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
806 int depth, int vector)
808 struct device *dmadev = &dev->pci_dev->dev;
809 unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
810 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
814 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
815 &nvmeq->cq_dma_addr, GFP_KERNEL);
818 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
820 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
821 &nvmeq->sq_dma_addr, GFP_KERNEL);
825 nvmeq->q_dmadev = dmadev;
827 spin_lock_init(&nvmeq->q_lock);
830 init_waitqueue_head(&nvmeq->sq_full);
831 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
832 bio_list_init(&nvmeq->sq_cong);
833 nvmeq->q_db = &dev->dbs[qid * 2];
834 nvmeq->q_depth = depth;
835 nvmeq->cq_vector = vector;
840 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
847 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
850 if (use_threaded_interrupts)
851 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
852 nvme_irq_check, nvme_irq,
853 IRQF_DISABLED | IRQF_SHARED,
855 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
856 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
859 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
860 int qid, int cq_size, int vector)
863 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
868 result = adapter_alloc_cq(dev, qid, nvmeq);
872 result = adapter_alloc_sq(dev, qid, nvmeq);
876 result = queue_request_irq(dev, nvmeq, "nvme");
883 adapter_delete_sq(dev, qid);
885 adapter_delete_cq(dev, qid);
887 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
888 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
889 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
890 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
895 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
899 struct nvme_queue *nvmeq;
901 dev->dbs = ((void __iomem *)dev->bar) + 4096;
903 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
907 aqa = nvmeq->q_depth - 1;
910 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
911 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
912 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
914 writel(0, &dev->bar->cc);
915 writel(aqa, &dev->bar->aqa);
916 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
917 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
918 writel(dev->ctrl_config, &dev->bar->cc);
920 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
922 if (fatal_signal_pending(current))
926 result = queue_request_irq(dev, nvmeq, "nvme admin");
927 dev->queues[0] = nvmeq;
931 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
932 unsigned long addr, unsigned length,
933 struct scatterlist **sgp)
935 int i, err, count, nents, offset;
936 struct scatterlist *sg;
944 offset = offset_in_page(addr);
945 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
946 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
948 err = get_user_pages_fast(addr, count, 1, pages);
955 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
956 sg_init_table(sg, count);
957 sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
958 length -= (PAGE_SIZE - offset);
959 for (i = 1; i < count; i++) {
960 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
965 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
966 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
975 for (i = 0; i < count; i++)
981 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
982 unsigned long addr, int length,
983 struct scatterlist *sg, int nents)
987 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
988 dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
990 for (i = 0; i < count; i++)
991 put_page(sg_page(&sg[i]));
994 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
995 unsigned long addr, unsigned length,
996 struct nvme_command *cmd)
999 struct scatterlist *sg;
1000 struct nvme_prps *prps;
1002 nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
1005 prps = nvme_setup_prps(dev, &cmd->common, sg, length);
1006 err = nvme_submit_admin_cmd(dev, cmd, NULL);
1007 nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
1008 nvme_free_prps(dev, prps);
1009 return err ? -EIO : 0;
1012 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
1014 struct nvme_command c;
1016 memset(&c, 0, sizeof(c));
1017 c.identify.opcode = nvme_admin_identify;
1018 c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
1019 c.identify.cns = cpu_to_le32(cns);
1021 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1024 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
1026 struct nvme_command c;
1028 memset(&c, 0, sizeof(c));
1029 c.features.opcode = nvme_admin_get_features;
1030 c.features.nsid = cpu_to_le32(ns->ns_id);
1031 c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1033 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1036 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1038 struct nvme_dev *dev = ns->dev;
1039 struct nvme_queue *nvmeq;
1040 struct nvme_user_io io;
1041 struct nvme_command c;
1045 struct scatterlist *sg;
1046 struct nvme_prps *prps;
1048 if (copy_from_user(&io, uio, sizeof(io)))
1050 length = io.nblocks << io.block_shift;
1051 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
1055 memset(&c, 0, sizeof(c));
1056 c.rw.opcode = io.opcode;
1057 c.rw.flags = io.flags;
1058 c.rw.nsid = cpu_to_le32(io.nsid);
1059 c.rw.slba = cpu_to_le64(io.slba);
1060 c.rw.length = cpu_to_le16(io.nblocks - 1);
1061 c.rw.control = cpu_to_le16(io.control);
1062 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1063 c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */
1064 c.rw.apptag = cpu_to_le16(io.apptag);
1065 c.rw.appmask = cpu_to_le16(io.appmask);
1067 prps = nvme_setup_prps(dev, &c.common, sg, length);
1069 nvmeq = get_nvmeq(ns);
1071 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1072 * disabled. We may be preempted at any point, and be rescheduled
1073 * to a different CPU. That will cause cacheline bouncing, but no
1074 * additional races since q_lock already protects against other CPUs.
1077 status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
1079 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1080 nvme_free_prps(dev, prps);
1081 put_user(result, &uio->result);
1085 static int nvme_download_firmware(struct nvme_ns *ns,
1086 struct nvme_dlfw __user *udlfw)
1088 struct nvme_dev *dev = ns->dev;
1089 struct nvme_dlfw dlfw;
1090 struct nvme_command c;
1092 struct scatterlist *sg;
1093 struct nvme_prps *prps;
1095 if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1097 if (dlfw.length >= (1 << 30))
1100 nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1104 memset(&c, 0, sizeof(c));
1105 c.dlfw.opcode = nvme_admin_download_fw;
1106 c.dlfw.numd = cpu_to_le32(dlfw.length);
1107 c.dlfw.offset = cpu_to_le32(dlfw.offset);
1108 prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1110 status = nvme_submit_admin_cmd(dev, &c, NULL);
1111 nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1112 nvme_free_prps(dev, prps);
1116 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1118 struct nvme_dev *dev = ns->dev;
1119 struct nvme_command c;
1121 memset(&c, 0, sizeof(c));
1122 c.common.opcode = nvme_admin_activate_fw;
1123 c.common.rsvd10[0] = cpu_to_le32(arg);
1125 return nvme_submit_admin_cmd(dev, &c, NULL);
1128 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1131 struct nvme_ns *ns = bdev->bd_disk->private_data;
1134 case NVME_IOCTL_IDENTIFY_NS:
1135 return nvme_identify(ns, arg, 0);
1136 case NVME_IOCTL_IDENTIFY_CTRL:
1137 return nvme_identify(ns, arg, 1);
1138 case NVME_IOCTL_GET_RANGE_TYPE:
1139 return nvme_get_range_type(ns, arg);
1140 case NVME_IOCTL_SUBMIT_IO:
1141 return nvme_submit_io(ns, (void __user *)arg);
1142 case NVME_IOCTL_DOWNLOAD_FW:
1143 return nvme_download_firmware(ns, (void __user *)arg);
1144 case NVME_IOCTL_ACTIVATE_FW:
1145 return nvme_activate_firmware(ns, arg);
1151 static const struct block_device_operations nvme_fops = {
1152 .owner = THIS_MODULE,
1153 .ioctl = nvme_ioctl,
1156 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1158 while (bio_list_peek(&nvmeq->sq_cong)) {
1159 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1160 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1161 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1162 bio_list_add_head(&nvmeq->sq_cong, bio);
1165 if (bio_list_empty(&nvmeq->sq_cong))
1166 remove_wait_queue(&nvmeq->sq_full,
1167 &nvmeq->sq_cong_wait);
1171 static int nvme_kthread(void *data)
1173 struct nvme_dev *dev;
1175 while (!kthread_should_stop()) {
1176 __set_current_state(TASK_RUNNING);
1177 spin_lock(&dev_list_lock);
1178 list_for_each_entry(dev, &dev_list, node) {
1180 for (i = 0; i < dev->queue_count; i++) {
1181 struct nvme_queue *nvmeq = dev->queues[i];
1184 spin_lock_irq(&nvmeq->q_lock);
1185 if (nvme_process_cq(nvmeq))
1186 printk("process_cq did something\n");
1187 nvme_resubmit_bios(nvmeq);
1188 spin_unlock_irq(&nvmeq->q_lock);
1191 spin_unlock(&dev_list_lock);
1192 set_current_state(TASK_INTERRUPTIBLE);
1193 schedule_timeout(HZ);
1198 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1199 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1202 struct gendisk *disk;
1205 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1208 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1211 ns->queue = blk_alloc_queue(GFP_KERNEL);
1214 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1215 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1216 blk_queue_make_request(ns->queue, nvme_make_request);
1218 ns->queue->queuedata = ns;
1220 disk = alloc_disk(NVME_MINORS);
1222 goto out_free_queue;
1225 lbaf = id->flbas & 0xf;
1226 ns->lba_shift = id->lbaf[lbaf].ds;
1228 disk->major = nvme_major;
1229 disk->minors = NVME_MINORS;
1230 disk->first_minor = NVME_MINORS * index;
1231 disk->fops = &nvme_fops;
1232 disk->private_data = ns;
1233 disk->queue = ns->queue;
1234 disk->driverfs_dev = &dev->pci_dev->dev;
1235 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1236 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1241 blk_cleanup_queue(ns->queue);
1247 static void nvme_ns_free(struct nvme_ns *ns)
1250 blk_cleanup_queue(ns->queue);
1254 static int set_queue_count(struct nvme_dev *dev, int count)
1258 struct nvme_command c;
1259 u32 q_count = (count - 1) | ((count - 1) << 16);
1261 memset(&c, 0, sizeof(c));
1262 c.features.opcode = nvme_admin_get_features;
1263 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1264 c.features.dword11 = cpu_to_le32(q_count);
1266 status = nvme_submit_admin_cmd(dev, &c, &result);
1269 return min(result & 0xffff, result >> 16) + 1;
1272 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1274 int result, cpu, i, nr_io_queues;
1276 nr_io_queues = num_online_cpus();
1277 result = set_queue_count(dev, nr_io_queues);
1280 if (result < nr_io_queues)
1281 nr_io_queues = result;
1283 /* Deregister the admin queue's interrupt */
1284 free_irq(dev->entry[0].vector, dev->queues[0]);
1286 for (i = 0; i < nr_io_queues; i++)
1287 dev->entry[i].entry = i;
1289 result = pci_enable_msix(dev->pci_dev, dev->entry,
1293 } else if (result > 0) {
1294 nr_io_queues = result;
1302 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1303 /* XXX: handle failure here */
1305 cpu = cpumask_first(cpu_online_mask);
1306 for (i = 0; i < nr_io_queues; i++) {
1307 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1308 cpu = cpumask_next(cpu, cpu_online_mask);
1311 for (i = 0; i < nr_io_queues; i++) {
1312 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1314 if (!dev->queues[i + 1])
1322 static void nvme_free_queues(struct nvme_dev *dev)
1326 for (i = dev->queue_count - 1; i >= 0; i--)
1327 nvme_free_queue(dev, i);
1330 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1333 struct nvme_ns *ns, *next;
1334 struct nvme_id_ctrl *ctrl;
1336 dma_addr_t dma_addr;
1337 struct nvme_command cid, crt;
1339 res = nvme_setup_io_queues(dev);
1343 /* XXX: Switch to a SG list once prp2 works */
1344 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1347 memset(&cid, 0, sizeof(cid));
1348 cid.identify.opcode = nvme_admin_identify;
1349 cid.identify.nsid = 0;
1350 cid.identify.prp1 = cpu_to_le64(dma_addr);
1351 cid.identify.cns = cpu_to_le32(1);
1353 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1360 nn = le32_to_cpup(&ctrl->nn);
1361 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1362 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1363 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1365 cid.identify.cns = 0;
1366 memset(&crt, 0, sizeof(crt));
1367 crt.features.opcode = nvme_admin_get_features;
1368 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1369 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1371 for (i = 0; i <= nn; i++) {
1372 cid.identify.nsid = cpu_to_le32(i);
1373 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1377 if (((struct nvme_id_ns *)id)->ncap == 0)
1380 crt.features.nsid = cpu_to_le32(i);
1381 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1385 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1387 list_add_tail(&ns->list, &dev->namespaces);
1389 list_for_each_entry(ns, &dev->namespaces, list)
1392 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1396 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1397 list_del(&ns->list);
1401 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1405 static int nvme_dev_remove(struct nvme_dev *dev)
1407 struct nvme_ns *ns, *next;
1409 spin_lock(&dev_list_lock);
1410 list_del(&dev->node);
1411 spin_unlock(&dev_list_lock);
1413 /* TODO: wait all I/O finished or cancel them */
1415 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1416 list_del(&ns->list);
1417 del_gendisk(ns->disk);
1421 nvme_free_queues(dev);
1426 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1428 struct device *dmadev = &dev->pci_dev->dev;
1429 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1430 PAGE_SIZE, PAGE_SIZE, 0);
1431 if (!dev->prp_page_pool)
1434 /* Optimisation for I/Os between 4k and 128k */
1435 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1437 if (!dev->prp_small_pool) {
1438 dma_pool_destroy(dev->prp_page_pool);
1444 static void nvme_release_prp_pools(struct nvme_dev *dev)
1446 dma_pool_destroy(dev->prp_page_pool);
1447 dma_pool_destroy(dev->prp_small_pool);
1450 /* XXX: Use an ida or something to let remove / add work correctly */
1451 static void nvme_set_instance(struct nvme_dev *dev)
1453 static int instance;
1454 dev->instance = instance++;
1457 static void nvme_release_instance(struct nvme_dev *dev)
1461 static int __devinit nvme_probe(struct pci_dev *pdev,
1462 const struct pci_device_id *id)
1464 int bars, result = -ENOMEM;
1465 struct nvme_dev *dev;
1467 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1470 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1474 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1479 if (pci_enable_device_mem(pdev))
1481 pci_set_master(pdev);
1482 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1483 if (pci_request_selected_regions(pdev, bars, "nvme"))
1486 INIT_LIST_HEAD(&dev->namespaces);
1487 dev->pci_dev = pdev;
1488 pci_set_drvdata(pdev, dev);
1489 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1490 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1491 nvme_set_instance(dev);
1492 dev->entry[0].vector = pdev->irq;
1494 result = nvme_setup_prp_pools(dev);
1498 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1504 result = nvme_configure_admin_queue(dev);
1509 spin_lock(&dev_list_lock);
1510 list_add(&dev->node, &dev_list);
1511 spin_unlock(&dev_list_lock);
1513 result = nvme_dev_add(dev);
1520 spin_lock(&dev_list_lock);
1521 list_del(&dev->node);
1522 spin_unlock(&dev_list_lock);
1524 nvme_free_queues(dev);
1528 pci_disable_msix(pdev);
1529 nvme_release_instance(dev);
1530 nvme_release_prp_pools(dev);
1532 pci_disable_device(pdev);
1533 pci_release_regions(pdev);
1541 static void __devexit nvme_remove(struct pci_dev *pdev)
1543 struct nvme_dev *dev = pci_get_drvdata(pdev);
1544 nvme_dev_remove(dev);
1545 pci_disable_msix(pdev);
1547 nvme_release_instance(dev);
1548 nvme_release_prp_pools(dev);
1549 pci_disable_device(pdev);
1550 pci_release_regions(pdev);
1556 /* These functions are yet to be implemented */
1557 #define nvme_error_detected NULL
1558 #define nvme_dump_registers NULL
1559 #define nvme_link_reset NULL
1560 #define nvme_slot_reset NULL
1561 #define nvme_error_resume NULL
1562 #define nvme_suspend NULL
1563 #define nvme_resume NULL
1565 static struct pci_error_handlers nvme_err_handler = {
1566 .error_detected = nvme_error_detected,
1567 .mmio_enabled = nvme_dump_registers,
1568 .link_reset = nvme_link_reset,
1569 .slot_reset = nvme_slot_reset,
1570 .resume = nvme_error_resume,
1573 /* Move to pci_ids.h later */
1574 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1576 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1577 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1580 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1582 static struct pci_driver nvme_driver = {
1584 .id_table = nvme_id_table,
1585 .probe = nvme_probe,
1586 .remove = __devexit_p(nvme_remove),
1587 .suspend = nvme_suspend,
1588 .resume = nvme_resume,
1589 .err_handler = &nvme_err_handler,
1592 static int __init nvme_init(void)
1594 int result = -EBUSY;
1596 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1597 if (IS_ERR(nvme_thread))
1598 return PTR_ERR(nvme_thread);
1600 nvme_major = register_blkdev(nvme_major, "nvme");
1601 if (nvme_major <= 0)
1604 result = pci_register_driver(&nvme_driver);
1606 goto unregister_blkdev;
1610 unregister_blkdev(nvme_major, "nvme");
1612 kthread_stop(nvme_thread);
1616 static void __exit nvme_exit(void)
1618 pci_unregister_driver(&nvme_driver);
1619 unregister_blkdev(nvme_major, "nvme");
1620 kthread_stop(nvme_thread);
1623 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1624 MODULE_LICENSE("GPL");
1625 MODULE_VERSION("0.4");
1626 module_init(nvme_init);
1627 module_exit(nvme_exit);