drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kernel.h>
  30 #include <linux/mm.h>
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/poison.h>
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/types.h>
  38 #include <linux/version.h>
  39
  40 #define NVME_Q_DEPTH 1024
  41 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  42 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  43 #define NVME_MINORS 64
  44 #define IO_TIMEOUT      (5 * HZ)
  45 #define ADMIN_TIMEOUT   (60 * HZ)
  46
  47 static int nvme_major;
  48 module_param(nvme_major, int, 0);
  49
  50 static int use_threaded_interrupts;
  51 module_param(use_threaded_interrupts, int, 0);
  52
  53 /*
  54  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  55  */
  56 struct nvme_dev {
  57         struct nvme_queue **queues;
  58         u32 __iomem *dbs;
  59         struct pci_dev *pci_dev;
  60         struct dma_pool *prp_page_pool;
  61         struct dma_pool *prp_small_pool;
  62         int instance;
  63         int queue_count;
  64         u32 ctrl_config;
  65         struct msix_entry *entry;
  66         struct nvme_bar __iomem *bar;
  67         struct list_head namespaces;
  68         char serial[20];
  69         char model[40];
  70         char firmware_rev[8];
  71 };
  72
  73 /*
  74  * An NVM Express namespace is equivalent to a SCSI LUN
  75  */
  76 struct nvme_ns {
  77         struct list_head list;
  78
  79         struct nvme_dev *dev;
  80         struct request_queue *queue;
  81         struct gendisk *disk;
  82
  83         int ns_id;
  84         int lba_shift;
  85 };
  86
  87 /*
  88  * An NVM Express queue.  Each device has at least two (one for admin
  89  * commands and one for I/O commands).
  90  */
  91 struct nvme_queue {
  92         struct device *q_dmadev;
  93         struct nvme_dev *dev;
  94         spinlock_t q_lock;
  95         struct nvme_command *sq_cmds;
  96         volatile struct nvme_completion *cqes;
  97         dma_addr_t sq_dma_addr;
  98         dma_addr_t cq_dma_addr;
  99         wait_queue_head_t sq_full;
 100         struct bio_list sq_cong;
 101         u32 __iomem *q_db;
 102         u16 q_depth;
 103         u16 cq_vector;
 104         u16 sq_head;
 105         u16 sq_tail;
 106         u16 cq_head;
 107         u16 cq_phase;
 108         unsigned long cmdid_data[];
 109 };
 110
 111 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio);
 112
 113 /*
 114  * Check we didin't inadvertently grow the command struct
 115  */
 116 static inline void _nvme_check_size(void)
 117 {
 118         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 119         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 120         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 121         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 122         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 123         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 124         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 125         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 126         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 127 }
 128
 129 struct nvme_cmd_info {
 130         unsigned long ctx;
 131         unsigned long timeout;
 132 };
 133
 134 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 135 {
 136         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 137 }
 138
 139 /**
 140  * alloc_cmdid - Allocate a Command ID
 141  * @param nvmeq The queue that will be used for this command
 142  * @param ctx A pointer that will be passed to the handler
 143  * @param handler The ID of the handler to call
 144  *
 145  * Allocate a Command ID for a queue.  The data passed in will
 146  * be passed to the completion handler.  This is implemented by using
 147  * the bottom two bits of the ctx pointer to store the handler ID.
 148  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 149  * We can change this if it becomes a problem.
 150  */
 151 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 152                                                         unsigned timeout)
 153 {
 154         int depth = nvmeq->q_depth;
 155         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 156         int cmdid;
 157
 158         BUG_ON((unsigned long)ctx & 3);
 159
 160         do {
 161                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 162                 if (cmdid >= depth)
 163                         return -EBUSY;
 164         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 165
 166         info[cmdid].ctx = (unsigned long)ctx | handler;
 167         info[cmdid].timeout = jiffies + timeout;
 168         return cmdid;
 169 }
 170
 171 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 172                                                 int handler, unsigned timeout)
 173 {
 174         int cmdid;
 175         wait_event_killable(nvmeq->sq_full,
 176                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 177         return (cmdid < 0) ? -EINTR : cmdid;
 178 }
 179
 180 /* If you need more than four handlers, you'll need to change how
 181  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 182  * CMD_CTX value instead, if that works for your situation.
 183  */
 184 enum {
 185         sync_completion_id = 0,
 186         bio_completion_id,
 187 };
 188
 189 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 190 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 191 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 192 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 193
 194 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 195 {
 196         unsigned long data;
 197         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 198
 199         if (cmdid >= nvmeq->q_depth)
 200                 return CMD_CTX_INVALID;
 201         data = info[cmdid].ctx;
 202         info[cmdid].ctx = CMD_CTX_COMPLETED;
 203         clear_bit(cmdid, nvmeq->cmdid_data);
 204         wake_up(&nvmeq->sq_full);
 205         return data;
 206 }
 207
 208 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 209 {
 210         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 211         info[cmdid].ctx = CMD_CTX_CANCELLED;
 212 }
 213
 214 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 215 {
 216         int qid, cpu = get_cpu();
 217         if (cpu < ns->dev->queue_count)
 218                 qid = cpu + 1;
 219         else
 220                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 221         return ns->dev->queues[qid];
 222 }
 223
 224 static void put_nvmeq(struct nvme_queue *nvmeq)
 225 {
 226         put_cpu();
 227 }
 228
 229 /**
 230  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 231  * @nvmeq: The queue to use
 232  * @cmd: The command to send
 233  *
 234  * Safe to use from interrupt context
 235  */
 236 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 237 {
 238         unsigned long flags;
 239         u16 tail;
 240         /* XXX: Need to check tail isn't going to overrun head */
 241         spin_lock_irqsave(&nvmeq->q_lock, flags);
 242         tail = nvmeq->sq_tail;
 243         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 244         writel(tail, nvmeq->q_db);
 245         if (++tail == nvmeq->q_depth)
 246                 tail = 0;
 247         nvmeq->sq_tail = tail;
 248         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 249
 250         return 0;
 251 }
 252
 253 struct nvme_prps {
 254         int npages;
 255         dma_addr_t first_dma;
 256         __le64 *list[0];
 257 };
 258
 259 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
 260 {
 261         const int last_prp = PAGE_SIZE / 8 - 1;
 262         int i;
 263         dma_addr_t prp_dma;
 264
 265         if (!prps)
 266                 return;
 267
 268         prp_dma = prps->first_dma;
 269
 270         if (prps->npages == 0)
 271                 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
 272         for (i = 0; i < prps->npages; i++) {
 273                 __le64 *prp_list = prps->list[i];
 274                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 275                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 276                 prp_dma = next_prp_dma;
 277         }
 278         kfree(prps);
 279 }
 280
 281 struct nvme_bio {
 282         struct bio *bio;
 283         int nents;
 284         struct nvme_prps *prps;
 285         struct scatterlist sg[0];
 286 };
 287
 288 /* XXX: use a mempool */
 289 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 290 {
 291         return kzalloc(sizeof(struct nvme_bio) +
 292                         sizeof(struct scatterlist) * nseg, gfp);
 293 }
 294
 295 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 296 {
 297         nvme_free_prps(nvmeq->dev, nbio->prps);
 298         kfree(nbio);
 299 }
 300
 301 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 302                                                 struct nvme_completion *cqe)
 303 {
 304         struct nvme_bio *nbio = ctx;
 305         struct bio *bio = nbio->bio;
 306         u16 status = le16_to_cpup(&cqe->status) >> 1;
 307
 308         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 309                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 310         free_nbio(nvmeq, nbio);
 311         bio_endio(bio, status ? -EIO : 0);
 312         bio = bio_list_pop(&nvmeq->sq_cong);
 313         if (bio)
 314                 nvme_resubmit_bio(nvmeq, bio);
 315 }
 316
 317 /* length is in bytes */
 318 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
 319                                         struct nvme_common_command *cmd,
 320                                         struct scatterlist *sg, int length)
 321 {
 322         struct dma_pool *pool;
 323         int dma_len = sg_dma_len(sg);
 324         u64 dma_addr = sg_dma_address(sg);
 325         int offset = offset_in_page(dma_addr);
 326         __le64 *prp_list;
 327         dma_addr_t prp_dma;
 328         int nprps, npages, i, prp_page;
 329         struct nvme_prps *prps = NULL;
 330
 331         cmd->prp1 = cpu_to_le64(dma_addr);
 332         length -= (PAGE_SIZE - offset);
 333         if (length <= 0)
 334                 return prps;
 335
 336         dma_len -= (PAGE_SIZE - offset);
 337         if (dma_len) {
 338                 dma_addr += (PAGE_SIZE - offset);
 339         } else {
 340                 sg = sg_next(sg);
 341                 dma_addr = sg_dma_address(sg);
 342                 dma_len = sg_dma_len(sg);
 343         }
 344
 345         if (length <= PAGE_SIZE) {
 346                 cmd->prp2 = cpu_to_le64(dma_addr);
 347                 return prps;
 348         }
 349
 350         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 351         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
 352         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
 353         prp_page = 0;
 354         if (nprps <= (256 / 8)) {
 355                 pool = dev->prp_small_pool;
 356                 prps->npages = 0;
 357         } else {
 358                 pool = dev->prp_page_pool;
 359                 prps->npages = npages;
 360         }
 361
 362         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 363         prps->list[prp_page++] = prp_list;
 364         prps->first_dma = prp_dma;
 365         cmd->prp2 = cpu_to_le64(prp_dma);
 366         i = 0;
 367         for (;;) {
 368                 if (i == PAGE_SIZE / 8 - 1) {
 369                         __le64 *old_prp_list = prp_list;
 370                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 371                         prps->list[prp_page++] = prp_list;
 372                         old_prp_list[i] = cpu_to_le64(prp_dma);
 373                         i = 0;
 374                 }
 375                 prp_list[i++] = cpu_to_le64(dma_addr);
 376                 dma_len -= PAGE_SIZE;
 377                 dma_addr += PAGE_SIZE;
 378                 length -= PAGE_SIZE;
 379                 if (length <= 0)
 380                         break;
 381                 if (dma_len > 0)
 382                         continue;
 383                 BUG_ON(dma_len < 0);
 384                 sg = sg_next(sg);
 385                 dma_addr = sg_dma_address(sg);
 386                 dma_len = sg_dma_len(sg);
 387         }
 388
 389         return prps;
 390 }
 391
 392 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 393                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 394 {
 395         struct bio_vec *bvec;
 396         struct scatterlist *sg = nbio->sg;
 397         int i, nsegs;
 398
 399         sg_init_table(sg, psegs);
 400         bio_for_each_segment(bvec, bio, i) {
 401                 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
 402                 sg++;
 403                 /* XXX: handle non-mergable here */
 404                 nsegs++;
 405         }
 406         nbio->nents = nsegs;
 407
 408         return dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir);
 409 }
 410
 411 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 412                                                                 struct bio *bio)
 413 {
 414         struct nvme_command *cmnd;
 415         struct nvme_bio *nbio;
 416         enum dma_data_direction dma_dir;
 417         int cmdid;
 418         u16 control;
 419         u32 dsmgmt;
 420         unsigned long flags;
 421         int psegs = bio_phys_segments(ns->queue, bio);
 422
 423         nbio = alloc_nbio(psegs, GFP_NOIO);
 424         if (!nbio)
 425                 goto congestion;
 426         nbio->bio = bio;
 427
 428         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 429         if (unlikely(cmdid < 0))
 430                 goto free_nbio;
 431
 432         control = 0;
 433         if (bio->bi_rw & REQ_FUA)
 434                 control |= NVME_RW_FUA;
 435         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 436                 control |= NVME_RW_LR;
 437
 438         dsmgmt = 0;
 439         if (bio->bi_rw & REQ_RAHEAD)
 440                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 441
 442         spin_lock_irqsave(&nvmeq->q_lock, flags);
 443         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 444
 445         memset(cmnd, 0, sizeof(*cmnd));
 446         if (bio_data_dir(bio)) {
 447                 cmnd->rw.opcode = nvme_cmd_write;
 448                 dma_dir = DMA_TO_DEVICE;
 449         } else {
 450                 cmnd->rw.opcode = nvme_cmd_read;
 451                 dma_dir = DMA_FROM_DEVICE;
 452         }
 453
 454         if (nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs) == 0)
 455                 goto mapping_failed;
 456
 457         cmnd->rw.flags = 1;
 458         cmnd->rw.command_id = cmdid;
 459         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 460         nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
 461                                                                 bio->bi_size);
 462         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 463         cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
 464         cmnd->rw.control = cpu_to_le16(control);
 465         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 466
 467         writel(nvmeq->sq_tail, nvmeq->q_db);
 468         if (++nvmeq->sq_tail == nvmeq->q_depth)
 469                 nvmeq->sq_tail = 0;
 470
 471         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 472
 473         return 0;
 474
 475  mapping_failed:
 476         free_nbio(nvmeq, nbio);
 477         bio_endio(bio, -ENOMEM);
 478         return 0;
 479
 480  free_nbio:
 481         free_nbio(nvmeq, nbio);
 482  congestion:
 483         return -EBUSY;
 484 }
 485
 486 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio)
 487 {
 488         struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
 489         if (nvme_submit_bio_queue(nvmeq, ns, bio))
 490                 bio_list_add_head(&nvmeq->sq_cong, bio);
 491         else if (bio_list_empty(&nvmeq->sq_cong))
 492                 blk_clear_queue_congested(ns->queue, rw_is_sync(bio->bi_rw));
 493         /* XXX: Need to duplicate the logic from __freed_request here */
 494 }
 495
 496 /*
 497  * NB: return value of non-zero would mean that we were a stacking driver.
 498  * make_request must always succeed.
 499  */
 500 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 501 {
 502         struct nvme_ns *ns = q->queuedata;
 503         struct nvme_queue *nvmeq = get_nvmeq(ns);
 504
 505         if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
 506                 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
 507                 spin_lock_irq(&nvmeq->q_lock);
 508                 bio_list_add(&nvmeq->sq_cong, bio);
 509                 spin_unlock_irq(&nvmeq->q_lock);
 510         }
 511         put_nvmeq(nvmeq);
 512
 513         return 0;
 514 }
 515
 516 struct sync_cmd_info {
 517         struct task_struct *task;
 518         u32 result;
 519         int status;
 520 };
 521
 522 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 523                                                 struct nvme_completion *cqe)
 524 {
 525         struct sync_cmd_info *cmdinfo = ctx;
 526         if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
 527                 return;
 528         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 529                 dev_warn(nvmeq->q_dmadev,
 530                                 "completed id %d twice on queue %d\n",
 531                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 532                 return;
 533         }
 534         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 535                 dev_warn(nvmeq->q_dmadev,
 536                                 "invalid id %d completed on queue %d\n",
 537                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 538                 return;
 539         }
 540         cmdinfo->result = le32_to_cpup(&cqe->result);
 541         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 542         wake_up_process(cmdinfo->task);
 543 }
 544
 545 typedef void (*completion_fn)(struct nvme_queue *, void *,
 546                                                 struct nvme_completion *);
 547
 548 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 549 {
 550         u16 head, phase;
 551
 552         static const completion_fn completions[4] = {
 553                 [sync_completion_id] = sync_completion,
 554                 [bio_completion_id]  = bio_completion,
 555         };
 556
 557         head = nvmeq->cq_head;
 558         phase = nvmeq->cq_phase;
 559
 560         for (;;) {
 561                 unsigned long data;
 562                 void *ptr;
 563                 unsigned char handler;
 564                 struct nvme_completion cqe = nvmeq->cqes[head];
 565                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 566                         break;
 567                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 568                 if (++head == nvmeq->q_depth) {
 569                         head = 0;
 570                         phase = !phase;
 571                 }
 572
 573                 data = free_cmdid(nvmeq, cqe.command_id);
 574                 handler = data & 3;
 575                 ptr = (void *)(data & ~3UL);
 576                 completions[handler](nvmeq, ptr, &cqe);
 577         }
 578
 579         /* If the controller ignores the cq head doorbell and continuously
 580          * writes to the queue, it is theoretically possible to wrap around
 581          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 582          * requires that 0.1% of your interrupts are handled, so this isn't
 583          * a big problem.
 584          */
 585         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 586                 return IRQ_NONE;
 587
 588         writel(head, nvmeq->q_db + 1);
 589         nvmeq->cq_head = head;
 590         nvmeq->cq_phase = phase;
 591
 592         return IRQ_HANDLED;
 593 }
 594
 595 static irqreturn_t nvme_irq(int irq, void *data)
 596 {
 597         irqreturn_t result;
 598         struct nvme_queue *nvmeq = data;
 599         spin_lock(&nvmeq->q_lock);
 600         result = nvme_process_cq(nvmeq);
 601         spin_unlock(&nvmeq->q_lock);
 602         return result;
 603 }
 604
 605 static irqreturn_t nvme_irq_check(int irq, void *data)
 606 {
 607         struct nvme_queue *nvmeq = data;
 608         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 609         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 610                 return IRQ_NONE;
 611         return IRQ_WAKE_THREAD;
 612 }
 613
 614 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 615 {
 616         spin_lock_irq(&nvmeq->q_lock);
 617         cancel_cmdid_data(nvmeq, cmdid);
 618         spin_unlock_irq(&nvmeq->q_lock);
 619 }
 620
 621 /*
 622  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 623  * if the result is positive, it's an NVM Express status code
 624  */
 625 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 626                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 627 {
 628         int cmdid;
 629         struct sync_cmd_info cmdinfo;
 630
 631         cmdinfo.task = current;
 632         cmdinfo.status = -EINTR;
 633
 634         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 635                                                                 timeout);
 636         if (cmdid < 0)
 637                 return cmdid;
 638         cmd->common.command_id = cmdid;
 639
 640         set_current_state(TASK_KILLABLE);
 641         nvme_submit_cmd(nvmeq, cmd);
 642         schedule();
 643
 644         if (cmdinfo.status == -EINTR) {
 645                 nvme_abort_command(nvmeq, cmdid);
 646                 return -EINTR;
 647         }
 648
 649         if (result)
 650                 *result = cmdinfo.result;
 651
 652         return cmdinfo.status;
 653 }
 654
 655 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 656                                                                 u32 *result)
 657 {
 658         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 659 }
 660
 661 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 662 {
 663         int status;
 664         struct nvme_command c;
 665
 666         memset(&c, 0, sizeof(c));
 667         c.delete_queue.opcode = opcode;
 668         c.delete_queue.qid = cpu_to_le16(id);
 669
 670         status = nvme_submit_admin_cmd(dev, &c, NULL);
 671         if (status)
 672                 return -EIO;
 673         return 0;
 674 }
 675
 676 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 677                                                 struct nvme_queue *nvmeq)
 678 {
 679         int status;
 680         struct nvme_command c;
 681         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 682
 683         memset(&c, 0, sizeof(c));
 684         c.create_cq.opcode = nvme_admin_create_cq;
 685         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 686         c.create_cq.cqid = cpu_to_le16(qid);
 687         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 688         c.create_cq.cq_flags = cpu_to_le16(flags);
 689         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 690
 691         status = nvme_submit_admin_cmd(dev, &c, NULL);
 692         if (status)
 693                 return -EIO;
 694         return 0;
 695 }
 696
 697 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 698                                                 struct nvme_queue *nvmeq)
 699 {
 700         int status;
 701         struct nvme_command c;
 702         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 703
 704         memset(&c, 0, sizeof(c));
 705         c.create_sq.opcode = nvme_admin_create_sq;
 706         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 707         c.create_sq.sqid = cpu_to_le16(qid);
 708         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 709         c.create_sq.sq_flags = cpu_to_le16(flags);
 710         c.create_sq.cqid = cpu_to_le16(qid);
 711
 712         status = nvme_submit_admin_cmd(dev, &c, NULL);
 713         if (status)
 714                 return -EIO;
 715         return 0;
 716 }
 717
 718 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 719 {
 720         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 721 }
 722
 723 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 724 {
 725         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 726 }
 727
 728 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 729 {
 730         struct nvme_queue *nvmeq = dev->queues[qid];
 731
 732         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 733
 734         /* Don't tell the adapter to delete the admin queue */
 735         if (qid) {
 736                 adapter_delete_sq(dev, qid);
 737                 adapter_delete_cq(dev, qid);
 738         }
 739
 740         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 741                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 742         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 743                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 744         kfree(nvmeq);
 745 }
 746
 747 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 748                                                         int depth, int vector)
 749 {
 750         struct device *dmadev = &dev->pci_dev->dev;
 751         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 752         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 753         if (!nvmeq)
 754                 return NULL;
 755
 756         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 757                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 758         if (!nvmeq->cqes)
 759                 goto free_nvmeq;
 760         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 761
 762         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 763                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 764         if (!nvmeq->sq_cmds)
 765                 goto free_cqdma;
 766
 767         nvmeq->q_dmadev = dmadev;
 768         nvmeq->dev = dev;
 769         spin_lock_init(&nvmeq->q_lock);
 770         nvmeq->cq_head = 0;
 771         nvmeq->cq_phase = 1;
 772         init_waitqueue_head(&nvmeq->sq_full);
 773         bio_list_init(&nvmeq->sq_cong);
 774         nvmeq->q_db = &dev->dbs[qid * 2];
 775         nvmeq->q_depth = depth;
 776         nvmeq->cq_vector = vector;
 777
 778         return nvmeq;
 779
 780  free_cqdma:
 781         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 782                                                         nvmeq->cq_dma_addr);
 783  free_nvmeq:
 784         kfree(nvmeq);
 785         return NULL;
 786 }
 787
 788 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 789                                                         const char *name)
 790 {
 791         if (use_threaded_interrupts)
 792                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 793                                         nvme_irq_check, nvme_irq,
 794                                         IRQF_DISABLED | IRQF_SHARED,
 795                                         name, nvmeq);
 796         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 797                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 798 }
 799
 800 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 801                                         int qid, int cq_size, int vector)
 802 {
 803         int result;
 804         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 805
 806         if (!nvmeq)
 807                 return NULL;
 808
 809         result = adapter_alloc_cq(dev, qid, nvmeq);
 810         if (result < 0)
 811                 goto free_nvmeq;
 812
 813         result = adapter_alloc_sq(dev, qid, nvmeq);
 814         if (result < 0)
 815                 goto release_cq;
 816
 817         result = queue_request_irq(dev, nvmeq, "nvme");
 818         if (result < 0)
 819                 goto release_sq;
 820
 821         return nvmeq;
 822
 823  release_sq:
 824         adapter_delete_sq(dev, qid);
 825  release_cq:
 826         adapter_delete_cq(dev, qid);
 827  free_nvmeq:
 828         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 829                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 830         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 831                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 832         kfree(nvmeq);
 833         return NULL;
 834 }
 835
 836 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 837 {
 838         int result;
 839         u32 aqa;
 840         struct nvme_queue *nvmeq;
 841
 842         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 843
 844         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 845         if (!nvmeq)
 846                 return -ENOMEM;
 847
 848         aqa = nvmeq->q_depth - 1;
 849         aqa |= aqa << 16;
 850
 851         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 852         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 853         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 854
 855         writel(0, &dev->bar->cc);
 856         writel(aqa, &dev->bar->aqa);
 857         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 858         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 859         writel(dev->ctrl_config, &dev->bar->cc);
 860
 861         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 862                 msleep(100);
 863                 if (fatal_signal_pending(current))
 864                         return -EINTR;
 865         }
 866
 867         result = queue_request_irq(dev, nvmeq, "nvme admin");
 868         dev->queues[0] = nvmeq;
 869         return result;
 870 }
 871
 872 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 873                                 unsigned long addr, unsigned length,
 874                                 struct scatterlist **sgp)
 875 {
 876         int i, err, count, nents, offset;
 877         struct scatterlist *sg;
 878         struct page **pages;
 879
 880         if (addr & 3)
 881                 return -EINVAL;
 882         if (!length)
 883                 return -EINVAL;
 884
 885         offset = offset_in_page(addr);
 886         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 887         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 888
 889         err = get_user_pages_fast(addr, count, 1, pages);
 890         if (err < count) {
 891                 count = err;
 892                 err = -EFAULT;
 893                 goto put_pages;
 894         }
 895
 896         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 897         sg_init_table(sg, count);
 898         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 899         length -= (PAGE_SIZE - offset);
 900         for (i = 1; i < count; i++) {
 901                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 902                 length -= PAGE_SIZE;
 903         }
 904
 905         err = -ENOMEM;
 906         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 907                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 908         if (!nents)
 909                 goto put_pages;
 910
 911         kfree(pages);
 912         *sgp = sg;
 913         return nents;
 914
 915  put_pages:
 916         for (i = 0; i < count; i++)
 917                 put_page(pages[i]);
 918         kfree(pages);
 919         return err;
 920 }
 921
 922 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 923                                 unsigned long addr, int length,
 924                                 struct scatterlist *sg, int nents)
 925 {
 926         int i, count;
 927
 928         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 929         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 930
 931         for (i = 0; i < count; i++)
 932                 put_page(sg_page(&sg[i]));
 933 }
 934
 935 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 936                                         unsigned long addr, unsigned length,
 937                                         struct nvme_command *cmd)
 938 {
 939         int err, nents;
 940         struct scatterlist *sg;
 941         struct nvme_prps *prps;
 942
 943         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 944         if (nents < 0)
 945                 return nents;
 946         prps = nvme_setup_prps(dev, &cmd->common, sg, length);
 947         err = nvme_submit_admin_cmd(dev, cmd, NULL);
 948         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
 949         nvme_free_prps(dev, prps);
 950         return err ? -EIO : 0;
 951 }
 952
 953 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
 954 {
 955         struct nvme_command c;
 956
 957         memset(&c, 0, sizeof(c));
 958         c.identify.opcode = nvme_admin_identify;
 959         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
 960         c.identify.cns = cpu_to_le32(cns);
 961
 962         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 963 }
 964
 965 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
 966 {
 967         struct nvme_command c;
 968
 969         memset(&c, 0, sizeof(c));
 970         c.features.opcode = nvme_admin_get_features;
 971         c.features.nsid = cpu_to_le32(ns->ns_id);
 972         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
 973
 974         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 975 }
 976
 977 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
 978 {
 979         struct nvme_dev *dev = ns->dev;
 980         struct nvme_queue *nvmeq;
 981         struct nvme_user_io io;
 982         struct nvme_command c;
 983         unsigned length;
 984         u32 result;
 985         int nents, status;
 986         struct scatterlist *sg;
 987         struct nvme_prps *prps;
 988
 989         if (copy_from_user(&io, uio, sizeof(io)))
 990                 return -EFAULT;
 991         length = io.nblocks << io.block_shift;
 992         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
 993         if (nents < 0)
 994                 return nents;
 995
 996         memset(&c, 0, sizeof(c));
 997         c.rw.opcode = io.opcode;
 998         c.rw.flags = io.flags;
 999         c.rw.nsid = cpu_to_le32(io.nsid);
1000         c.rw.slba = cpu_to_le64(io.slba);
1001         c.rw.length = cpu_to_le16(io.nblocks - 1);
1002         c.rw.control = cpu_to_le16(io.control);
1003         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1004         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
1005         c.rw.apptag = cpu_to_le16(io.apptag);
1006         c.rw.appmask = cpu_to_le16(io.appmask);
1007         /* XXX: metadata */
1008         prps = nvme_setup_prps(dev, &c.common, sg, length);
1009
1010         nvmeq = get_nvmeq(ns);
1011         /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1012          * disabled.  We may be preempted at any point, and be rescheduled
1013          * to a different CPU.  That will cause cacheline bouncing, but no
1014          * additional races since q_lock already protects against other CPUs.
1015          */
1016         put_nvmeq(nvmeq);
1017         status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
1018
1019         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1020         nvme_free_prps(dev, prps);
1021         put_user(result, &uio->result);
1022         return status;
1023 }
1024
1025 static int nvme_download_firmware(struct nvme_ns *ns,
1026                                                 struct nvme_dlfw __user *udlfw)
1027 {
1028         struct nvme_dev *dev = ns->dev;
1029         struct nvme_dlfw dlfw;
1030         struct nvme_command c;
1031         int nents, status;
1032         struct scatterlist *sg;
1033         struct nvme_prps *prps;
1034
1035         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1036                 return -EFAULT;
1037         if (dlfw.length >= (1 << 30))
1038                 return -EINVAL;
1039
1040         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1041         if (nents < 0)
1042                 return nents;
1043
1044         memset(&c, 0, sizeof(c));
1045         c.dlfw.opcode = nvme_admin_download_fw;
1046         c.dlfw.numd = cpu_to_le32(dlfw.length);
1047         c.dlfw.offset = cpu_to_le32(dlfw.offset);
1048         prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1049
1050         status = nvme_submit_admin_cmd(dev, &c, NULL);
1051         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1052         nvme_free_prps(dev, prps);
1053         return status;
1054 }
1055
1056 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1057 {
1058         struct nvme_dev *dev = ns->dev;
1059         struct nvme_command c;
1060
1061         memset(&c, 0, sizeof(c));
1062         c.common.opcode = nvme_admin_activate_fw;
1063         c.common.rsvd10[0] = cpu_to_le32(arg);
1064
1065         return nvme_submit_admin_cmd(dev, &c, NULL);
1066 }
1067
1068 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1069                                                         unsigned long arg)
1070 {
1071         struct nvme_ns *ns = bdev->bd_disk->private_data;
1072
1073         switch (cmd) {
1074         case NVME_IOCTL_IDENTIFY_NS:
1075                 return nvme_identify(ns, arg, 0);
1076         case NVME_IOCTL_IDENTIFY_CTRL:
1077                 return nvme_identify(ns, arg, 1);
1078         case NVME_IOCTL_GET_RANGE_TYPE:
1079                 return nvme_get_range_type(ns, arg);
1080         case NVME_IOCTL_SUBMIT_IO:
1081                 return nvme_submit_io(ns, (void __user *)arg);
1082         case NVME_IOCTL_DOWNLOAD_FW:
1083                 return nvme_download_firmware(ns, (void __user *)arg);
1084         case NVME_IOCTL_ACTIVATE_FW:
1085                 return nvme_activate_firmware(ns, arg);
1086         default:
1087                 return -ENOTTY;
1088         }
1089 }
1090
1091 static const struct block_device_operations nvme_fops = {
1092         .owner          = THIS_MODULE,
1093         .ioctl          = nvme_ioctl,
1094 };
1095
1096 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1097                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1098 {
1099         struct nvme_ns *ns;
1100         struct gendisk *disk;
1101         int lbaf;
1102
1103         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1104                 return NULL;
1105
1106         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1107         if (!ns)
1108                 return NULL;
1109         ns->queue = blk_alloc_queue(GFP_KERNEL);
1110         if (!ns->queue)
1111                 goto out_free_ns;
1112         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1113                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1114         blk_queue_make_request(ns->queue, nvme_make_request);
1115         ns->dev = dev;
1116         ns->queue->queuedata = ns;
1117
1118         disk = alloc_disk(NVME_MINORS);
1119         if (!disk)
1120                 goto out_free_queue;
1121         ns->ns_id = index;
1122         ns->disk = disk;
1123         lbaf = id->flbas & 0xf;
1124         ns->lba_shift = id->lbaf[lbaf].ds;
1125
1126         disk->major = nvme_major;
1127         disk->minors = NVME_MINORS;
1128         disk->first_minor = NVME_MINORS * index;
1129         disk->fops = &nvme_fops;
1130         disk->private_data = ns;
1131         disk->queue = ns->queue;
1132         disk->driverfs_dev = &dev->pci_dev->dev;
1133         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1134         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1135
1136         return ns;
1137
1138  out_free_queue:
1139         blk_cleanup_queue(ns->queue);
1140  out_free_ns:
1141         kfree(ns);
1142         return NULL;
1143 }
1144
1145 static void nvme_ns_free(struct nvme_ns *ns)
1146 {
1147         put_disk(ns->disk);
1148         blk_cleanup_queue(ns->queue);
1149         kfree(ns);
1150 }
1151
1152 static int set_queue_count(struct nvme_dev *dev, int count)
1153 {
1154         int status;
1155         u32 result;
1156         struct nvme_command c;
1157         u32 q_count = (count - 1) | ((count - 1) << 16);
1158
1159         memset(&c, 0, sizeof(c));
1160         c.features.opcode = nvme_admin_get_features;
1161         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1162         c.features.dword11 = cpu_to_le32(q_count);
1163
1164         status = nvme_submit_admin_cmd(dev, &c, &result);
1165         if (status)
1166                 return -EIO;
1167         return min(result & 0xffff, result >> 16) + 1;
1168 }
1169
1170 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1171 {
1172         int result, cpu, i, nr_queues;
1173
1174         nr_queues = num_online_cpus();
1175         result = set_queue_count(dev, nr_queues);
1176         if (result < 0)
1177                 return result;
1178         if (result < nr_queues)
1179                 nr_queues = result;
1180
1181         /* Deregister the admin queue's interrupt */
1182         free_irq(dev->entry[0].vector, dev->queues[0]);
1183
1184         for (i = 0; i < nr_queues; i++)
1185                 dev->entry[i].entry = i;
1186         for (;;) {
1187                 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1188                 if (result == 0) {
1189                         break;
1190                 } else if (result > 0) {
1191                         nr_queues = result;
1192                         continue;
1193                 } else {
1194                         nr_queues = 1;
1195                         break;
1196                 }
1197         }
1198
1199         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1200         /* XXX: handle failure here */
1201
1202         cpu = cpumask_first(cpu_online_mask);
1203         for (i = 0; i < nr_queues; i++) {
1204                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1205                 cpu = cpumask_next(cpu, cpu_online_mask);
1206         }
1207
1208         for (i = 0; i < nr_queues; i++) {
1209                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1210                                                         NVME_Q_DEPTH, i);
1211                 if (!dev->queues[i + 1])
1212                         return -ENOMEM;
1213                 dev->queue_count++;
1214         }
1215
1216         return 0;
1217 }
1218
1219 static void nvme_free_queues(struct nvme_dev *dev)
1220 {
1221         int i;
1222
1223         for (i = dev->queue_count - 1; i >= 0; i--)
1224                 nvme_free_queue(dev, i);
1225 }
1226
1227 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1228 {
1229         int res, nn, i;
1230         struct nvme_ns *ns, *next;
1231         struct nvme_id_ctrl *ctrl;
1232         void *id;
1233         dma_addr_t dma_addr;
1234         struct nvme_command cid, crt;
1235
1236         res = nvme_setup_io_queues(dev);
1237         if (res)
1238                 return res;
1239
1240         /* XXX: Switch to a SG list once prp2 works */
1241         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1242                                                                 GFP_KERNEL);
1243
1244         memset(&cid, 0, sizeof(cid));
1245         cid.identify.opcode = nvme_admin_identify;
1246         cid.identify.nsid = 0;
1247         cid.identify.prp1 = cpu_to_le64(dma_addr);
1248         cid.identify.cns = cpu_to_le32(1);
1249
1250         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1251         if (res) {
1252                 res = -EIO;
1253                 goto out_free;
1254         }
1255
1256         ctrl = id;
1257         nn = le32_to_cpup(&ctrl->nn);
1258         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1259         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1260         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1261
1262         cid.identify.cns = 0;
1263         memset(&crt, 0, sizeof(crt));
1264         crt.features.opcode = nvme_admin_get_features;
1265         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1266         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1267
1268         for (i = 0; i < nn; i++) {
1269                 cid.identify.nsid = cpu_to_le32(i);
1270                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1271                 if (res)
1272                         continue;
1273
1274                 if (((struct nvme_id_ns *)id)->ncap == 0)
1275                         continue;
1276
1277                 crt.features.nsid = cpu_to_le32(i);
1278                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1279                 if (res)
1280                         continue;
1281
1282                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1283                 if (ns)
1284                         list_add_tail(&ns->list, &dev->namespaces);
1285         }
1286         list_for_each_entry(ns, &dev->namespaces, list)
1287                 add_disk(ns->disk);
1288
1289         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1290         return 0;
1291
1292  out_free:
1293         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1294                 list_del(&ns->list);
1295                 nvme_ns_free(ns);
1296         }
1297
1298         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1299         return res;
1300 }
1301
1302 static int nvme_dev_remove(struct nvme_dev *dev)
1303 {
1304         struct nvme_ns *ns, *next;
1305
1306         /* TODO: wait all I/O finished or cancel them */
1307
1308         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1309                 list_del(&ns->list);
1310                 del_gendisk(ns->disk);
1311                 nvme_ns_free(ns);
1312         }
1313
1314         nvme_free_queues(dev);
1315
1316         return 0;
1317 }
1318
1319 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1320 {
1321         struct device *dmadev = &dev->pci_dev->dev;
1322         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1323                                                 PAGE_SIZE, PAGE_SIZE, 0);
1324         if (!dev->prp_page_pool)
1325                 return -ENOMEM;
1326
1327         /* Optimisation for I/Os between 4k and 128k */
1328         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1329                                                 256, 256, 0);
1330         if (!dev->prp_small_pool) {
1331                 dma_pool_destroy(dev->prp_page_pool);
1332                 return -ENOMEM;
1333         }
1334         return 0;
1335 }
1336
1337 static void nvme_release_prp_pools(struct nvme_dev *dev)
1338 {
1339         dma_pool_destroy(dev->prp_page_pool);
1340         dma_pool_destroy(dev->prp_small_pool);
1341 }
1342
1343 /* XXX: Use an ida or something to let remove / add work correctly */
1344 static void nvme_set_instance(struct nvme_dev *dev)
1345 {
1346         static int instance;
1347         dev->instance = instance++;
1348 }
1349
1350 static void nvme_release_instance(struct nvme_dev *dev)
1351 {
1352 }
1353
1354 static int __devinit nvme_probe(struct pci_dev *pdev,
1355                                                 const struct pci_device_id *id)
1356 {
1357         int bars, result = -ENOMEM;
1358         struct nvme_dev *dev;
1359
1360         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1361         if (!dev)
1362                 return -ENOMEM;
1363         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1364                                                                 GFP_KERNEL);
1365         if (!dev->entry)
1366                 goto free;
1367         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1368                                                                 GFP_KERNEL);
1369         if (!dev->queues)
1370                 goto free;
1371
1372         if (pci_enable_device_mem(pdev))
1373                 goto free;
1374         pci_set_master(pdev);
1375         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1376         if (pci_request_selected_regions(pdev, bars, "nvme"))
1377                 goto disable;
1378
1379         INIT_LIST_HEAD(&dev->namespaces);
1380         dev->pci_dev = pdev;
1381         pci_set_drvdata(pdev, dev);
1382         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1383         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1384         nvme_set_instance(dev);
1385         dev->entry[0].vector = pdev->irq;
1386
1387         result = nvme_setup_prp_pools(dev);
1388         if (result)
1389                 goto disable_msix;
1390
1391         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1392         if (!dev->bar) {
1393                 result = -ENOMEM;
1394                 goto disable_msix;
1395         }
1396
1397         result = nvme_configure_admin_queue(dev);
1398         if (result)
1399                 goto unmap;
1400         dev->queue_count++;
1401
1402         result = nvme_dev_add(dev);
1403         if (result)
1404                 goto delete;
1405         return 0;
1406
1407  delete:
1408         nvme_free_queues(dev);
1409  unmap:
1410         iounmap(dev->bar);
1411  disable_msix:
1412         pci_disable_msix(pdev);
1413         nvme_release_instance(dev);
1414         nvme_release_prp_pools(dev);
1415  disable:
1416         pci_disable_device(pdev);
1417         pci_release_regions(pdev);
1418  free:
1419         kfree(dev->queues);
1420         kfree(dev->entry);
1421         kfree(dev);
1422         return result;
1423 }
1424
1425 static void __devexit nvme_remove(struct pci_dev *pdev)
1426 {
1427         struct nvme_dev *dev = pci_get_drvdata(pdev);
1428         nvme_dev_remove(dev);
1429         pci_disable_msix(pdev);
1430         iounmap(dev->bar);
1431         nvme_release_instance(dev);
1432         nvme_release_prp_pools(dev);
1433         pci_disable_device(pdev);
1434         pci_release_regions(pdev);
1435         kfree(dev->queues);
1436         kfree(dev->entry);
1437         kfree(dev);
1438 }
1439
1440 /* These functions are yet to be implemented */
1441 #define nvme_error_detected NULL
1442 #define nvme_dump_registers NULL
1443 #define nvme_link_reset NULL
1444 #define nvme_slot_reset NULL
1445 #define nvme_error_resume NULL
1446 #define nvme_suspend NULL
1447 #define nvme_resume NULL
1448
1449 static struct pci_error_handlers nvme_err_handler = {
1450         .error_detected = nvme_error_detected,
1451         .mmio_enabled   = nvme_dump_registers,
1452         .link_reset     = nvme_link_reset,
1453         .slot_reset     = nvme_slot_reset,
1454         .resume         = nvme_error_resume,
1455 };
1456
1457 /* Move to pci_ids.h later */
1458 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1459
1460 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1461         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1462         { 0, }
1463 };
1464 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1465
1466 static struct pci_driver nvme_driver = {
1467         .name           = "nvme",
1468         .id_table       = nvme_id_table,
1469         .probe          = nvme_probe,
1470         .remove         = __devexit_p(nvme_remove),
1471         .suspend        = nvme_suspend,
1472         .resume         = nvme_resume,
1473         .err_handler    = &nvme_err_handler,
1474 };
1475
1476 static int __init nvme_init(void)
1477 {
1478         int result;
1479
1480         nvme_major = register_blkdev(nvme_major, "nvme");
1481         if (nvme_major <= 0)
1482                 return -EBUSY;
1483
1484         result = pci_register_driver(&nvme_driver);
1485         if (!result)
1486                 return 0;
1487
1488         unregister_blkdev(nvme_major, "nvme");
1489         return result;
1490 }
1491
1492 static void __exit nvme_exit(void)
1493 {
1494         pci_unregister_driver(&nvme_driver);
1495         unregister_blkdev(nvme_major, "nvme");
1496 }
1497
1498 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1499 MODULE_LICENSE("GPL");
1500 MODULE_VERSION("0.2");
1501 module_init(nvme_init);
1502 module_exit(nvme_exit);