2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/blkdev.h>
22 #include <linux/errno.h>
24 #include <linux/genhd.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/moduleparam.h>
33 #include <linux/pci.h>
34 #include <linux/poison.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/types.h>
38 #include <linux/version.h>
40 #define NVME_Q_DEPTH 1024
41 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
42 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
43 #define NVME_MINORS 64
44 #define IO_TIMEOUT (5 * HZ)
45 #define ADMIN_TIMEOUT (60 * HZ)
47 static int nvme_major;
48 module_param(nvme_major, int, 0);
50 static int use_threaded_interrupts;
51 module_param(use_threaded_interrupts, int, 0);
54 * Represents an NVM Express device. Each nvme_dev is a PCI function.
57 struct nvme_queue **queues;
59 struct pci_dev *pci_dev;
63 struct msix_entry *entry;
64 struct nvme_bar __iomem *bar;
65 struct list_head namespaces;
72 * An NVM Express namespace is equivalent to a SCSI LUN
75 struct list_head list;
78 struct request_queue *queue;
86 * An NVM Express queue. Each device has at least two (one for admin
87 * commands and one for I/O commands).
90 struct device *q_dmadev;
92 struct nvme_command *sq_cmds;
93 volatile struct nvme_completion *cqes;
94 dma_addr_t sq_dma_addr;
95 dma_addr_t cq_dma_addr;
96 wait_queue_head_t sq_full;
97 struct bio_list sq_cong;
105 unsigned long cmdid_data[];
108 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio);
111 * Check we didin't inadvertently grow the command struct
113 static inline void _nvme_check_size(void)
115 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
116 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
117 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
118 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
119 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
120 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
121 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
122 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
123 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
126 struct nvme_cmd_info {
128 unsigned long timeout;
131 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
133 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
137 * alloc_cmdid - Allocate a Command ID
138 * @param nvmeq The queue that will be used for this command
139 * @param ctx A pointer that will be passed to the handler
140 * @param handler The ID of the handler to call
142 * Allocate a Command ID for a queue. The data passed in will
143 * be passed to the completion handler. This is implemented by using
144 * the bottom two bits of the ctx pointer to store the handler ID.
145 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
146 * We can change this if it becomes a problem.
148 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
151 int depth = nvmeq->q_depth;
152 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
155 BUG_ON((unsigned long)ctx & 3);
158 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
161 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
163 info[cmdid].ctx = (unsigned long)ctx | handler;
164 info[cmdid].timeout = jiffies + timeout;
168 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
169 int handler, unsigned timeout)
172 wait_event_killable(nvmeq->sq_full,
173 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
174 return (cmdid < 0) ? -EINTR : cmdid;
177 /* If you need more than four handlers, you'll need to change how
178 * alloc_cmdid and nvme_process_cq work. Consider using a special
179 * CMD_CTX value instead, if that works for your situation.
182 sync_completion_id = 0,
186 #define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id)
187 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
188 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
189 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
191 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
194 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
196 if (cmdid >= nvmeq->q_depth)
197 return CMD_CTX_INVALID;
198 data = info[cmdid].ctx;
199 info[cmdid].ctx = CMD_CTX_COMPLETED;
200 clear_bit(cmdid, nvmeq->cmdid_data);
201 wake_up(&nvmeq->sq_full);
205 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
207 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
208 info[cmdid].ctx = CMD_CTX_CANCELLED;
211 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
213 int qid, cpu = get_cpu();
214 if (cpu < ns->dev->queue_count)
217 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
218 return ns->dev->queues[qid];
221 static void put_nvmeq(struct nvme_queue *nvmeq)
227 * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
228 * @nvmeq: The queue to use
229 * @cmd: The command to send
231 * Safe to use from interrupt context
233 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
237 /* XXX: Need to check tail isn't going to overrun head */
238 spin_lock_irqsave(&nvmeq->q_lock, flags);
239 tail = nvmeq->sq_tail;
240 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
241 writel(tail, nvmeq->q_db);
242 if (++tail == nvmeq->q_depth)
244 nvmeq->sq_tail = tail;
245 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
250 static __le64 *alloc_prp_list(struct nvme_queue *nvmeq, int length,
253 return dma_alloc_coherent(nvmeq->q_dmadev, PAGE_SIZE, addr, GFP_ATOMIC);
258 dma_addr_t first_dma;
262 static void nvme_free_prps(struct nvme_queue *nvmeq, struct nvme_prps *prps)
264 const int last_prp = PAGE_SIZE / 8 - 1;
271 prp_dma = prps->first_dma;
272 for (i = 0; i < prps->npages; i++) {
273 __le64 *prp_list = prps->list[i];
274 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
275 dma_free_coherent(nvmeq->q_dmadev, PAGE_SIZE, prp_list,
277 prp_dma = next_prp_dma;
282 struct nvme_req_info {
285 struct nvme_prps *prps;
286 struct scatterlist sg[0];
289 /* XXX: use a mempool */
290 static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp)
292 return kzalloc(sizeof(struct nvme_req_info) +
293 sizeof(struct scatterlist) * nseg, gfp);
296 static void free_info(struct nvme_queue *nvmeq, struct nvme_req_info *info)
298 nvme_free_prps(nvmeq, info->prps);
302 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
303 struct nvme_completion *cqe)
305 struct nvme_req_info *info = ctx;
306 struct bio *bio = info->bio;
307 u16 status = le16_to_cpup(&cqe->status) >> 1;
309 dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents,
310 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
311 free_info(nvmeq, info);
312 bio_endio(bio, status ? -EIO : 0);
313 bio = bio_list_pop(&nvmeq->sq_cong);
315 nvme_resubmit_bio(nvmeq, bio);
318 /* length is in bytes */
319 static struct nvme_prps *nvme_setup_prps(struct nvme_queue *nvmeq,
320 struct nvme_common_command *cmd,
321 struct scatterlist *sg, int length)
323 int dma_len = sg_dma_len(sg);
324 u64 dma_addr = sg_dma_address(sg);
325 int offset = offset_in_page(dma_addr);
328 int nprps, npages, i, prp_page;
329 struct nvme_prps *prps = NULL;
331 cmd->prp1 = cpu_to_le64(dma_addr);
332 length -= (PAGE_SIZE - offset);
336 dma_len -= (PAGE_SIZE - offset);
338 dma_addr += (PAGE_SIZE - offset);
341 dma_addr = sg_dma_address(sg);
342 dma_len = sg_dma_len(sg);
345 if (length <= PAGE_SIZE) {
346 cmd->prp2 = cpu_to_le64(dma_addr);
350 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
351 npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
352 prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
353 prps->npages = npages;
355 prp_list = alloc_prp_list(nvmeq, length, &prp_dma);
356 prps->list[prp_page++] = prp_list;
357 prps->first_dma = prp_dma;
358 cmd->prp2 = cpu_to_le64(prp_dma);
361 if (i == PAGE_SIZE / 8 - 1) {
362 __le64 *old_prp_list = prp_list;
363 prp_list = alloc_prp_list(nvmeq, length, &prp_dma);
364 prps->list[prp_page++] = prp_list;
365 old_prp_list[i] = cpu_to_le64(prp_dma);
368 prp_list[i++] = cpu_to_le64(dma_addr);
369 dma_len -= PAGE_SIZE;
370 dma_addr += PAGE_SIZE;
378 dma_addr = sg_dma_address(sg);
379 dma_len = sg_dma_len(sg);
385 static int nvme_map_bio(struct device *dev, struct nvme_req_info *info,
386 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
388 struct bio_vec *bvec;
389 struct scatterlist *sg = info->sg;
392 sg_init_table(sg, psegs);
393 bio_for_each_segment(bvec, bio, i) {
394 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
396 /* XXX: handle non-mergable here */
401 return dma_map_sg(dev, info->sg, info->nents, dma_dir);
404 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
407 struct nvme_command *cmnd;
408 struct nvme_req_info *info;
409 enum dma_data_direction dma_dir;
414 int psegs = bio_phys_segments(ns->queue, bio);
416 info = alloc_info(psegs, GFP_NOIO);
421 cmdid = alloc_cmdid(nvmeq, info, bio_completion_id, IO_TIMEOUT);
422 if (unlikely(cmdid < 0))
426 if (bio->bi_rw & REQ_FUA)
427 control |= NVME_RW_FUA;
428 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
429 control |= NVME_RW_LR;
432 if (bio->bi_rw & REQ_RAHEAD)
433 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
435 spin_lock_irqsave(&nvmeq->q_lock, flags);
436 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
438 memset(cmnd, 0, sizeof(*cmnd));
439 if (bio_data_dir(bio)) {
440 cmnd->rw.opcode = nvme_cmd_write;
441 dma_dir = DMA_TO_DEVICE;
443 cmnd->rw.opcode = nvme_cmd_read;
444 dma_dir = DMA_FROM_DEVICE;
447 nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs);
450 cmnd->rw.command_id = cmdid;
451 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
452 info->prps = nvme_setup_prps(nvmeq, &cmnd->common, info->sg,
454 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
455 cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
456 cmnd->rw.control = cpu_to_le16(control);
457 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
459 writel(nvmeq->sq_tail, nvmeq->q_db);
460 if (++nvmeq->sq_tail == nvmeq->q_depth)
463 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
468 free_info(nvmeq, info);
473 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio)
475 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
476 if (nvme_submit_bio_queue(nvmeq, ns, bio))
477 bio_list_add_head(&nvmeq->sq_cong, bio);
478 else if (bio_list_empty(&nvmeq->sq_cong))
479 blk_clear_queue_congested(ns->queue, rw_is_sync(bio->bi_rw));
480 /* XXX: Need to duplicate the logic from __freed_request here */
484 * NB: return value of non-zero would mean that we were a stacking driver.
485 * make_request must always succeed.
487 static int nvme_make_request(struct request_queue *q, struct bio *bio)
489 struct nvme_ns *ns = q->queuedata;
490 struct nvme_queue *nvmeq = get_nvmeq(ns);
492 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
493 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
494 spin_lock_irq(&nvmeq->q_lock);
495 bio_list_add(&nvmeq->sq_cong, bio);
496 spin_unlock_irq(&nvmeq->q_lock);
503 struct sync_cmd_info {
504 struct task_struct *task;
509 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
510 struct nvme_completion *cqe)
512 struct sync_cmd_info *cmdinfo = ctx;
513 if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
515 if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
516 dev_warn(nvmeq->q_dmadev,
517 "completed id %d twice on queue %d\n",
518 cqe->command_id, le16_to_cpup(&cqe->sq_id));
521 if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
522 dev_warn(nvmeq->q_dmadev,
523 "invalid id %d completed on queue %d\n",
524 cqe->command_id, le16_to_cpup(&cqe->sq_id));
527 cmdinfo->result = le32_to_cpup(&cqe->result);
528 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
529 wake_up_process(cmdinfo->task);
532 typedef void (*completion_fn)(struct nvme_queue *, void *,
533 struct nvme_completion *);
535 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
539 static const completion_fn completions[4] = {
540 [sync_completion_id] = sync_completion,
541 [bio_completion_id] = bio_completion,
544 head = nvmeq->cq_head;
545 phase = nvmeq->cq_phase;
550 unsigned char handler;
551 struct nvme_completion cqe = nvmeq->cqes[head];
552 if ((le16_to_cpu(cqe.status) & 1) != phase)
554 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
555 if (++head == nvmeq->q_depth) {
560 data = free_cmdid(nvmeq, cqe.command_id);
562 ptr = (void *)(data & ~3UL);
563 completions[handler](nvmeq, ptr, &cqe);
566 /* If the controller ignores the cq head doorbell and continuously
567 * writes to the queue, it is theoretically possible to wrap around
568 * the queue twice and mistakenly return IRQ_NONE. Linux only
569 * requires that 0.1% of your interrupts are handled, so this isn't
572 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
575 writel(head, nvmeq->q_db + 1);
576 nvmeq->cq_head = head;
577 nvmeq->cq_phase = phase;
582 static irqreturn_t nvme_irq(int irq, void *data)
585 struct nvme_queue *nvmeq = data;
586 spin_lock(&nvmeq->q_lock);
587 result = nvme_process_cq(nvmeq);
588 spin_unlock(&nvmeq->q_lock);
592 static irqreturn_t nvme_irq_check(int irq, void *data)
594 struct nvme_queue *nvmeq = data;
595 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
596 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
598 return IRQ_WAKE_THREAD;
601 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
603 spin_lock_irq(&nvmeq->q_lock);
604 cancel_cmdid_data(nvmeq, cmdid);
605 spin_unlock_irq(&nvmeq->q_lock);
609 * Returns 0 on success. If the result is negative, it's a Linux error code;
610 * if the result is positive, it's an NVM Express status code
612 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
613 struct nvme_command *cmd, u32 *result, unsigned timeout)
616 struct sync_cmd_info cmdinfo;
618 cmdinfo.task = current;
619 cmdinfo.status = -EINTR;
621 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
625 cmd->common.command_id = cmdid;
627 set_current_state(TASK_KILLABLE);
628 nvme_submit_cmd(nvmeq, cmd);
631 if (cmdinfo.status == -EINTR) {
632 nvme_abort_command(nvmeq, cmdid);
637 *result = cmdinfo.result;
639 return cmdinfo.status;
642 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
645 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
648 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
651 struct nvme_command c;
653 memset(&c, 0, sizeof(c));
654 c.delete_queue.opcode = opcode;
655 c.delete_queue.qid = cpu_to_le16(id);
657 status = nvme_submit_admin_cmd(dev, &c, NULL);
663 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
664 struct nvme_queue *nvmeq)
667 struct nvme_command c;
668 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
670 memset(&c, 0, sizeof(c));
671 c.create_cq.opcode = nvme_admin_create_cq;
672 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
673 c.create_cq.cqid = cpu_to_le16(qid);
674 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
675 c.create_cq.cq_flags = cpu_to_le16(flags);
676 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
678 status = nvme_submit_admin_cmd(dev, &c, NULL);
684 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
685 struct nvme_queue *nvmeq)
688 struct nvme_command c;
689 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
691 memset(&c, 0, sizeof(c));
692 c.create_sq.opcode = nvme_admin_create_sq;
693 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
694 c.create_sq.sqid = cpu_to_le16(qid);
695 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
696 c.create_sq.sq_flags = cpu_to_le16(flags);
697 c.create_sq.cqid = cpu_to_le16(qid);
699 status = nvme_submit_admin_cmd(dev, &c, NULL);
705 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
707 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
710 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
712 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
715 static void nvme_free_queue(struct nvme_dev *dev, int qid)
717 struct nvme_queue *nvmeq = dev->queues[qid];
719 free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
721 /* Don't tell the adapter to delete the admin queue */
723 adapter_delete_sq(dev, qid);
724 adapter_delete_cq(dev, qid);
727 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
728 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
729 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
730 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
734 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
735 int depth, int vector)
737 struct device *dmadev = &dev->pci_dev->dev;
738 unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
739 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
743 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
744 &nvmeq->cq_dma_addr, GFP_KERNEL);
747 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
749 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
750 &nvmeq->sq_dma_addr, GFP_KERNEL);
754 nvmeq->q_dmadev = dmadev;
755 spin_lock_init(&nvmeq->q_lock);
758 init_waitqueue_head(&nvmeq->sq_full);
759 bio_list_init(&nvmeq->sq_cong);
760 nvmeq->q_db = &dev->dbs[qid * 2];
761 nvmeq->q_depth = depth;
762 nvmeq->cq_vector = vector;
767 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
774 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
777 if (use_threaded_interrupts)
778 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
779 nvme_irq_check, nvme_irq,
780 IRQF_DISABLED | IRQF_SHARED,
782 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
783 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
786 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
787 int qid, int cq_size, int vector)
790 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
795 result = adapter_alloc_cq(dev, qid, nvmeq);
799 result = adapter_alloc_sq(dev, qid, nvmeq);
803 result = queue_request_irq(dev, nvmeq, "nvme");
810 adapter_delete_sq(dev, qid);
812 adapter_delete_cq(dev, qid);
814 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
815 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
816 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
817 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
822 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
826 struct nvme_queue *nvmeq;
828 dev->dbs = ((void __iomem *)dev->bar) + 4096;
830 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
834 aqa = nvmeq->q_depth - 1;
837 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
838 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
839 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
841 writel(0, &dev->bar->cc);
842 writel(aqa, &dev->bar->aqa);
843 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
844 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
845 writel(dev->ctrl_config, &dev->bar->cc);
847 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
849 if (fatal_signal_pending(current))
853 result = queue_request_irq(dev, nvmeq, "nvme admin");
854 dev->queues[0] = nvmeq;
858 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
859 unsigned long addr, unsigned length,
860 struct scatterlist **sgp)
862 int i, err, count, nents, offset;
863 struct scatterlist *sg;
871 offset = offset_in_page(addr);
872 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
873 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
875 err = get_user_pages_fast(addr, count, 1, pages);
882 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
883 sg_init_table(sg, count);
884 sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
885 length -= (PAGE_SIZE - offset);
886 for (i = 1; i < count; i++) {
887 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
892 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
893 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
902 for (i = 0; i < count; i++)
908 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
909 unsigned long addr, int length,
910 struct scatterlist *sg, int nents)
914 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
915 dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
917 for (i = 0; i < count; i++)
918 put_page(sg_page(&sg[i]));
921 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
922 unsigned long addr, unsigned length,
923 struct nvme_command *cmd)
926 struct scatterlist *sg;
927 struct nvme_prps *prps;
929 nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
932 prps = nvme_setup_prps(dev->queues[0], &cmd->common, sg, length);
933 err = nvme_submit_admin_cmd(dev, cmd, NULL);
934 nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
935 nvme_free_prps(dev->queues[0], prps);
936 return err ? -EIO : 0;
939 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
941 struct nvme_command c;
943 memset(&c, 0, sizeof(c));
944 c.identify.opcode = nvme_admin_identify;
945 c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
946 c.identify.cns = cpu_to_le32(cns);
948 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
951 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
953 struct nvme_command c;
955 memset(&c, 0, sizeof(c));
956 c.features.opcode = nvme_admin_get_features;
957 c.features.nsid = cpu_to_le32(ns->ns_id);
958 c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
960 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
963 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
965 struct nvme_dev *dev = ns->dev;
966 struct nvme_queue *nvmeq;
967 struct nvme_user_io io;
968 struct nvme_command c;
972 struct scatterlist *sg;
973 struct nvme_prps *prps;
975 if (copy_from_user(&io, uio, sizeof(io)))
977 length = io.nblocks << io.block_shift;
978 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
982 memset(&c, 0, sizeof(c));
983 c.rw.opcode = io.opcode;
984 c.rw.flags = io.flags;
985 c.rw.nsid = cpu_to_le32(io.nsid);
986 c.rw.slba = cpu_to_le64(io.slba);
987 c.rw.length = cpu_to_le16(io.nblocks - 1);
988 c.rw.control = cpu_to_le16(io.control);
989 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
990 c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */
991 c.rw.apptag = cpu_to_le16(io.apptag);
992 c.rw.appmask = cpu_to_le16(io.appmask);
993 nvmeq = get_nvmeq(ns);
995 prps = nvme_setup_prps(nvmeq, &c.common, sg, length);
997 /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
998 * disabled. We may be preempted at any point, and be rescheduled
999 * to a different CPU. That will cause cacheline bouncing, but no
1000 * additional races since q_lock already protects against other CPUs.
1003 status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
1005 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1006 nvme_free_prps(nvmeq, prps);
1007 put_user(result, &uio->result);
1011 static int nvme_download_firmware(struct nvme_ns *ns,
1012 struct nvme_dlfw __user *udlfw)
1014 struct nvme_dev *dev = ns->dev;
1015 struct nvme_dlfw dlfw;
1016 struct nvme_command c;
1018 struct scatterlist *sg;
1019 struct nvme_prps *prps;
1021 if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1023 if (dlfw.length >= (1 << 30))
1026 nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1030 memset(&c, 0, sizeof(c));
1031 c.dlfw.opcode = nvme_admin_download_fw;
1032 c.dlfw.numd = cpu_to_le32(dlfw.length);
1033 c.dlfw.offset = cpu_to_le32(dlfw.offset);
1034 prps = nvme_setup_prps(dev->queues[0], &c.common, sg, dlfw.length * 4);
1036 status = nvme_submit_admin_cmd(dev, &c, NULL);
1037 nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1038 nvme_free_prps(dev->queues[0], prps);
1042 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1044 struct nvme_dev *dev = ns->dev;
1045 struct nvme_command c;
1047 memset(&c, 0, sizeof(c));
1048 c.common.opcode = nvme_admin_activate_fw;
1049 c.common.rsvd10[0] = cpu_to_le32(arg);
1051 return nvme_submit_admin_cmd(dev, &c, NULL);
1054 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1057 struct nvme_ns *ns = bdev->bd_disk->private_data;
1060 case NVME_IOCTL_IDENTIFY_NS:
1061 return nvme_identify(ns, arg, 0);
1062 case NVME_IOCTL_IDENTIFY_CTRL:
1063 return nvme_identify(ns, arg, 1);
1064 case NVME_IOCTL_GET_RANGE_TYPE:
1065 return nvme_get_range_type(ns, arg);
1066 case NVME_IOCTL_SUBMIT_IO:
1067 return nvme_submit_io(ns, (void __user *)arg);
1068 case NVME_IOCTL_DOWNLOAD_FW:
1069 return nvme_download_firmware(ns, (void __user *)arg);
1070 case NVME_IOCTL_ACTIVATE_FW:
1071 return nvme_activate_firmware(ns, arg);
1077 static const struct block_device_operations nvme_fops = {
1078 .owner = THIS_MODULE,
1079 .ioctl = nvme_ioctl,
1082 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1083 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1086 struct gendisk *disk;
1089 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1092 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1095 ns->queue = blk_alloc_queue(GFP_KERNEL);
1098 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1099 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1100 blk_queue_make_request(ns->queue, nvme_make_request);
1102 ns->queue->queuedata = ns;
1104 disk = alloc_disk(NVME_MINORS);
1106 goto out_free_queue;
1109 lbaf = id->flbas & 0xf;
1110 ns->lba_shift = id->lbaf[lbaf].ds;
1112 disk->major = nvme_major;
1113 disk->minors = NVME_MINORS;
1114 disk->first_minor = NVME_MINORS * index;
1115 disk->fops = &nvme_fops;
1116 disk->private_data = ns;
1117 disk->queue = ns->queue;
1118 disk->driverfs_dev = &dev->pci_dev->dev;
1119 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1120 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1125 blk_cleanup_queue(ns->queue);
1131 static void nvme_ns_free(struct nvme_ns *ns)
1134 blk_cleanup_queue(ns->queue);
1138 static int set_queue_count(struct nvme_dev *dev, int count)
1142 struct nvme_command c;
1143 u32 q_count = (count - 1) | ((count - 1) << 16);
1145 memset(&c, 0, sizeof(c));
1146 c.features.opcode = nvme_admin_get_features;
1147 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1148 c.features.dword11 = cpu_to_le32(q_count);
1150 status = nvme_submit_admin_cmd(dev, &c, &result);
1153 return min(result & 0xffff, result >> 16) + 1;
1156 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1158 int result, cpu, i, nr_queues;
1160 nr_queues = num_online_cpus();
1161 result = set_queue_count(dev, nr_queues);
1164 if (result < nr_queues)
1167 /* Deregister the admin queue's interrupt */
1168 free_irq(dev->entry[0].vector, dev->queues[0]);
1170 for (i = 0; i < nr_queues; i++)
1171 dev->entry[i].entry = i;
1173 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1176 } else if (result > 0) {
1185 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1186 /* XXX: handle failure here */
1188 cpu = cpumask_first(cpu_online_mask);
1189 for (i = 0; i < nr_queues; i++) {
1190 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1191 cpu = cpumask_next(cpu, cpu_online_mask);
1194 for (i = 0; i < nr_queues; i++) {
1195 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1197 if (!dev->queues[i + 1])
1205 static void nvme_free_queues(struct nvme_dev *dev)
1209 for (i = dev->queue_count - 1; i >= 0; i--)
1210 nvme_free_queue(dev, i);
1213 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1216 struct nvme_ns *ns, *next;
1217 struct nvme_id_ctrl *ctrl;
1219 dma_addr_t dma_addr;
1220 struct nvme_command cid, crt;
1222 res = nvme_setup_io_queues(dev);
1226 /* XXX: Switch to a SG list once prp2 works */
1227 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1230 memset(&cid, 0, sizeof(cid));
1231 cid.identify.opcode = nvme_admin_identify;
1232 cid.identify.nsid = 0;
1233 cid.identify.prp1 = cpu_to_le64(dma_addr);
1234 cid.identify.cns = cpu_to_le32(1);
1236 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1243 nn = le32_to_cpup(&ctrl->nn);
1244 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1245 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1246 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1248 cid.identify.cns = 0;
1249 memset(&crt, 0, sizeof(crt));
1250 crt.features.opcode = nvme_admin_get_features;
1251 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1252 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1254 for (i = 0; i < nn; i++) {
1255 cid.identify.nsid = cpu_to_le32(i);
1256 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1260 if (((struct nvme_id_ns *)id)->ncap == 0)
1263 crt.features.nsid = cpu_to_le32(i);
1264 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1268 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1270 list_add_tail(&ns->list, &dev->namespaces);
1272 list_for_each_entry(ns, &dev->namespaces, list)
1275 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1279 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1280 list_del(&ns->list);
1284 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1288 static int nvme_dev_remove(struct nvme_dev *dev)
1290 struct nvme_ns *ns, *next;
1292 /* TODO: wait all I/O finished or cancel them */
1294 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1295 list_del(&ns->list);
1296 del_gendisk(ns->disk);
1300 nvme_free_queues(dev);
1305 /* XXX: Use an ida or something to let remove / add work correctly */
1306 static void nvme_set_instance(struct nvme_dev *dev)
1308 static int instance;
1309 dev->instance = instance++;
1312 static void nvme_release_instance(struct nvme_dev *dev)
1316 static int __devinit nvme_probe(struct pci_dev *pdev,
1317 const struct pci_device_id *id)
1319 int bars, result = -ENOMEM;
1320 struct nvme_dev *dev;
1322 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1325 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1329 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1334 if (pci_enable_device_mem(pdev))
1336 pci_set_master(pdev);
1337 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1338 if (pci_request_selected_regions(pdev, bars, "nvme"))
1341 INIT_LIST_HEAD(&dev->namespaces);
1342 dev->pci_dev = pdev;
1343 pci_set_drvdata(pdev, dev);
1344 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1345 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1346 nvme_set_instance(dev);
1347 dev->entry[0].vector = pdev->irq;
1349 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1355 result = nvme_configure_admin_queue(dev);
1360 result = nvme_dev_add(dev);
1366 nvme_free_queues(dev);
1370 pci_disable_msix(pdev);
1371 nvme_release_instance(dev);
1373 pci_disable_device(pdev);
1374 pci_release_regions(pdev);
1382 static void __devexit nvme_remove(struct pci_dev *pdev)
1384 struct nvme_dev *dev = pci_get_drvdata(pdev);
1385 nvme_dev_remove(dev);
1386 pci_disable_msix(pdev);
1388 nvme_release_instance(dev);
1389 pci_disable_device(pdev);
1390 pci_release_regions(pdev);
1396 /* These functions are yet to be implemented */
1397 #define nvme_error_detected NULL
1398 #define nvme_dump_registers NULL
1399 #define nvme_link_reset NULL
1400 #define nvme_slot_reset NULL
1401 #define nvme_error_resume NULL
1402 #define nvme_suspend NULL
1403 #define nvme_resume NULL
1405 static struct pci_error_handlers nvme_err_handler = {
1406 .error_detected = nvme_error_detected,
1407 .mmio_enabled = nvme_dump_registers,
1408 .link_reset = nvme_link_reset,
1409 .slot_reset = nvme_slot_reset,
1410 .resume = nvme_error_resume,
1413 /* Move to pci_ids.h later */
1414 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1416 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1417 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1420 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1422 static struct pci_driver nvme_driver = {
1424 .id_table = nvme_id_table,
1425 .probe = nvme_probe,
1426 .remove = __devexit_p(nvme_remove),
1427 .suspend = nvme_suspend,
1428 .resume = nvme_resume,
1429 .err_handler = &nvme_err_handler,
1432 static int __init nvme_init(void)
1436 nvme_major = register_blkdev(nvme_major, "nvme");
1437 if (nvme_major <= 0)
1440 result = pci_register_driver(&nvme_driver);
1444 unregister_blkdev(nvme_major, "nvme");
1448 static void __exit nvme_exit(void)
1450 pci_unregister_driver(&nvme_driver);
1451 unregister_blkdev(nvme_major, "nvme");
1454 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1455 MODULE_LICENSE("GPL");
1456 MODULE_VERSION("0.2");
1457 module_init(nvme_init);
1458 module_exit(nvme_exit);