drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kernel.h>
  30 #include <linux/mm.h>
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/poison.h>
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/types.h>
  38 #include <linux/version.h>
  39
  40 #define NVME_Q_DEPTH 1024
  41 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  42 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  43 #define NVME_MINORS 64
  44 #define IO_TIMEOUT      (5 * HZ)
  45 #define ADMIN_TIMEOUT   (60 * HZ)
  46
  47 static int nvme_major;
  48 module_param(nvme_major, int, 0);
  49
  50 static int use_threaded_interrupts;
  51 module_param(use_threaded_interrupts, int, 0);
  52
  53 /*
  54  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  55  */
  56 struct nvme_dev {
  57         struct nvme_queue **queues;
  58         u32 __iomem *dbs;
  59         struct pci_dev *pci_dev;
  60         int instance;
  61         int queue_count;
  62         u32 ctrl_config;
  63         struct msix_entry *entry;
  64         struct nvme_bar __iomem *bar;
  65         struct list_head namespaces;
  66         char serial[20];
  67         char model[40];
  68         char firmware_rev[8];
  69 };
  70
  71 /*
  72  * An NVM Express namespace is equivalent to a SCSI LUN
  73  */
  74 struct nvme_ns {
  75         struct list_head list;
  76
  77         struct nvme_dev *dev;
  78         struct request_queue *queue;
  79         struct gendisk *disk;
  80
  81         int ns_id;
  82         int lba_shift;
  83 };
  84
  85 /*
  86  * An NVM Express queue.  Each device has at least two (one for admin
  87  * commands and one for I/O commands).
  88  */
  89 struct nvme_queue {
  90         struct device *q_dmadev;
  91         spinlock_t q_lock;
  92         struct nvme_command *sq_cmds;
  93         volatile struct nvme_completion *cqes;
  94         dma_addr_t sq_dma_addr;
  95         dma_addr_t cq_dma_addr;
  96         wait_queue_head_t sq_full;
  97         struct bio_list sq_cong;
  98         u32 __iomem *q_db;
  99         u16 q_depth;
 100         u16 cq_vector;
 101         u16 sq_head;
 102         u16 sq_tail;
 103         u16 cq_head;
 104         u16 cq_phase;
 105         unsigned long cmdid_data[];
 106 };
 107
 108 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio);
 109
 110 /*
 111  * Check we didin't inadvertently grow the command struct
 112  */
 113 static inline void _nvme_check_size(void)
 114 {
 115         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 116         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 117         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 118         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 119         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 120         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 121         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 122         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 123         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 124 }
 125
 126 struct nvme_cmd_info {
 127         unsigned long ctx;
 128         unsigned long timeout;
 129 };
 130
 131 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 132 {
 133         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 134 }
 135
 136 /**
 137  * alloc_cmdid - Allocate a Command ID
 138  * @param nvmeq The queue that will be used for this command
 139  * @param ctx A pointer that will be passed to the handler
 140  * @param handler The ID of the handler to call
 141  *
 142  * Allocate a Command ID for a queue.  The data passed in will
 143  * be passed to the completion handler.  This is implemented by using
 144  * the bottom two bits of the ctx pointer to store the handler ID.
 145  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 146  * We can change this if it becomes a problem.
 147  */
 148 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 149                                                         unsigned timeout)
 150 {
 151         int depth = nvmeq->q_depth;
 152         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 153         int cmdid;
 154
 155         BUG_ON((unsigned long)ctx & 3);
 156
 157         do {
 158                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 159                 if (cmdid >= depth)
 160                         return -EBUSY;
 161         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 162
 163         info[cmdid].ctx = (unsigned long)ctx | handler;
 164         info[cmdid].timeout = jiffies + timeout;
 165         return cmdid;
 166 }
 167
 168 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 169                                                 int handler, unsigned timeout)
 170 {
 171         int cmdid;
 172         wait_event_killable(nvmeq->sq_full,
 173                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 174         return (cmdid < 0) ? -EINTR : cmdid;
 175 }
 176
 177 /* If you need more than four handlers, you'll need to change how
 178  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 179  * CMD_CTX value instead, if that works for your situation.
 180  */
 181 enum {
 182         sync_completion_id = 0,
 183         bio_completion_id,
 184 };
 185
 186 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 187 #define CMD_CTX_CANCELLED       (0x2008 + CMD_CTX_BASE)
 188 #define CMD_CTX_COMPLETED       (0x2010 + CMD_CTX_BASE)
 189 #define CMD_CTX_INVALID         (0x2014 + CMD_CTX_BASE)
 190
 191 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 192 {
 193         unsigned long data;
 194         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 195
 196         if (cmdid >= nvmeq->q_depth)
 197                 return CMD_CTX_INVALID;
 198         data = info[cmdid].ctx;
 199         info[cmdid].ctx = CMD_CTX_COMPLETED;
 200         clear_bit(cmdid, nvmeq->cmdid_data);
 201         wake_up(&nvmeq->sq_full);
 202         return data;
 203 }
 204
 205 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 206 {
 207         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 208         info[cmdid].ctx = CMD_CTX_CANCELLED;
 209 }
 210
 211 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 212 {
 213         int qid, cpu = get_cpu();
 214         if (cpu < ns->dev->queue_count)
 215                 qid = cpu + 1;
 216         else
 217                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 218         return ns->dev->queues[qid];
 219 }
 220
 221 static void put_nvmeq(struct nvme_queue *nvmeq)
 222 {
 223         put_cpu();
 224 }
 225
 226 /**
 227  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 228  * @nvmeq: The queue to use
 229  * @cmd: The command to send
 230  *
 231  * Safe to use from interrupt context
 232  */
 233 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 234 {
 235         unsigned long flags;
 236         u16 tail;
 237         /* XXX: Need to check tail isn't going to overrun head */
 238         spin_lock_irqsave(&nvmeq->q_lock, flags);
 239         tail = nvmeq->sq_tail;
 240         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 241         writel(tail, nvmeq->q_db);
 242         if (++tail == nvmeq->q_depth)
 243                 tail = 0;
 244         nvmeq->sq_tail = tail;
 245         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 246
 247         return 0;
 248 }
 249
 250 struct nvme_req_info {
 251         struct bio *bio;
 252         int nents;
 253         struct scatterlist sg[0];
 254 };
 255
 256 /* XXX: use a mempool */
 257 static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp)
 258 {
 259         return kmalloc(sizeof(struct nvme_req_info) +
 260                         sizeof(struct scatterlist) * nseg, gfp);
 261 }
 262
 263 static void free_info(struct nvme_req_info *info)
 264 {
 265         kfree(info);
 266 }
 267
 268 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 269                                                 struct nvme_completion *cqe)
 270 {
 271         struct nvme_req_info *info = ctx;
 272         struct bio *bio = info->bio;
 273         u16 status = le16_to_cpup(&cqe->status) >> 1;
 274
 275         dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents,
 276                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 277         free_info(info);
 278         bio_endio(bio, status ? -EIO : 0);
 279         bio = bio_list_pop(&nvmeq->sq_cong);
 280         if (bio)
 281                 nvme_resubmit_bio(nvmeq, bio);
 282 }
 283
 284 /* length is in bytes */
 285 static void nvme_setup_prps(struct nvme_common_command *cmd,
 286                                         struct scatterlist *sg, int length)
 287 {
 288         int dma_len = sg_dma_len(sg);
 289         u64 dma_addr = sg_dma_address(sg);
 290         int offset = offset_in_page(dma_addr);
 291
 292         cmd->prp1 = cpu_to_le64(dma_addr);
 293         length -= (PAGE_SIZE - offset);
 294         if (length <= 0)
 295                 return;
 296
 297         dma_len -= (PAGE_SIZE - offset);
 298         if (dma_len) {
 299                 dma_addr += (PAGE_SIZE - offset);
 300         } else {
 301                 sg = sg_next(sg);
 302                 dma_addr = sg_dma_address(sg);
 303                 dma_len = sg_dma_len(sg);
 304         }
 305
 306         if (length <= PAGE_SIZE) {
 307                 cmd->prp2 = cpu_to_le64(dma_addr);
 308                 return;
 309         }
 310
 311         /* XXX: support PRP lists */
 312 }
 313
 314 static int nvme_map_bio(struct device *dev, struct nvme_req_info *info,
 315                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 316 {
 317         struct bio_vec *bvec;
 318         struct scatterlist *sg = info->sg;
 319         int i, nsegs;
 320
 321         sg_init_table(sg, psegs);
 322         bio_for_each_segment(bvec, bio, i) {
 323                 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
 324                 /* XXX: handle non-mergable here */
 325                 nsegs++;
 326         }
 327         info->nents = nsegs;
 328
 329         return dma_map_sg(dev, info->sg, info->nents, dma_dir);
 330 }
 331
 332 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 333                                                                 struct bio *bio)
 334 {
 335         struct nvme_command *cmnd;
 336         struct nvme_req_info *info;
 337         enum dma_data_direction dma_dir;
 338         int cmdid;
 339         u16 control;
 340         u32 dsmgmt;
 341         unsigned long flags;
 342         int psegs = bio_phys_segments(ns->queue, bio);
 343
 344         info = alloc_info(psegs, GFP_NOIO);
 345         if (!info)
 346                 goto congestion;
 347         info->bio = bio;
 348
 349         cmdid = alloc_cmdid(nvmeq, info, bio_completion_id, IO_TIMEOUT);
 350         if (unlikely(cmdid < 0))
 351                 goto free_info;
 352
 353         control = 0;
 354         if (bio->bi_rw & REQ_FUA)
 355                 control |= NVME_RW_FUA;
 356         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 357                 control |= NVME_RW_LR;
 358
 359         dsmgmt = 0;
 360         if (bio->bi_rw & REQ_RAHEAD)
 361                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 362
 363         spin_lock_irqsave(&nvmeq->q_lock, flags);
 364         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 365
 366         memset(cmnd, 0, sizeof(*cmnd));
 367         if (bio_data_dir(bio)) {
 368                 cmnd->rw.opcode = nvme_cmd_write;
 369                 dma_dir = DMA_TO_DEVICE;
 370         } else {
 371                 cmnd->rw.opcode = nvme_cmd_read;
 372                 dma_dir = DMA_FROM_DEVICE;
 373         }
 374
 375         nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs);
 376
 377         cmnd->rw.flags = 1;
 378         cmnd->rw.command_id = cmdid;
 379         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 380         nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size);
 381         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 382         cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
 383         cmnd->rw.control = cpu_to_le16(control);
 384         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 385
 386         writel(nvmeq->sq_tail, nvmeq->q_db);
 387         if (++nvmeq->sq_tail == nvmeq->q_depth)
 388                 nvmeq->sq_tail = 0;
 389
 390         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 391
 392         return 0;
 393
 394  free_info:
 395         free_info(info);
 396  congestion:
 397         return -EBUSY;
 398 }
 399
 400 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio)
 401 {
 402         struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
 403         if (nvme_submit_bio_queue(nvmeq, ns, bio))
 404                 bio_list_add_head(&nvmeq->sq_cong, bio);
 405         else if (bio_list_empty(&nvmeq->sq_cong))
 406                 blk_clear_queue_congested(ns->queue, rw_is_sync(bio->bi_rw));
 407         /* XXX: Need to duplicate the logic from __freed_request here */
 408 }
 409
 410 /*
 411  * NB: return value of non-zero would mean that we were a stacking driver.
 412  * make_request must always succeed.
 413  */
 414 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 415 {
 416         struct nvme_ns *ns = q->queuedata;
 417         struct nvme_queue *nvmeq = get_nvmeq(ns);
 418
 419         if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
 420                 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
 421                 spin_lock_irq(&nvmeq->q_lock);
 422                 bio_list_add(&nvmeq->sq_cong, bio);
 423                 spin_unlock_irq(&nvmeq->q_lock);
 424         }
 425         put_nvmeq(nvmeq);
 426
 427         return 0;
 428 }
 429
 430 struct sync_cmd_info {
 431         struct task_struct *task;
 432         u32 result;
 433         int status;
 434 };
 435
 436 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 437                                                 struct nvme_completion *cqe)
 438 {
 439         struct sync_cmd_info *cmdinfo = ctx;
 440         if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
 441                 return;
 442         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 443                 dev_warn(nvmeq->q_dmadev,
 444                                 "completed id %d twice on queue %d\n",
 445                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 446                 return;
 447         }
 448         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 449                 dev_warn(nvmeq->q_dmadev,
 450                                 "invalid id %d completed on queue %d\n",
 451                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 452                 return;
 453         }
 454         cmdinfo->result = le32_to_cpup(&cqe->result);
 455         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 456         wake_up_process(cmdinfo->task);
 457 }
 458
 459 typedef void (*completion_fn)(struct nvme_queue *, void *,
 460                                                 struct nvme_completion *);
 461
 462 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 463 {
 464         u16 head, phase;
 465
 466         static const completion_fn completions[4] = {
 467                 [sync_completion_id] = sync_completion,
 468                 [bio_completion_id]  = bio_completion,
 469         };
 470
 471         head = nvmeq->cq_head;
 472         phase = nvmeq->cq_phase;
 473
 474         for (;;) {
 475                 unsigned long data;
 476                 void *ptr;
 477                 unsigned char handler;
 478                 struct nvme_completion cqe = nvmeq->cqes[head];
 479                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 480                         break;
 481                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 482                 if (++head == nvmeq->q_depth) {
 483                         head = 0;
 484                         phase = !phase;
 485                 }
 486
 487                 data = free_cmdid(nvmeq, cqe.command_id);
 488                 handler = data & 3;
 489                 ptr = (void *)(data & ~3UL);
 490                 completions[handler](nvmeq, ptr, &cqe);
 491         }
 492
 493         /* If the controller ignores the cq head doorbell and continuously
 494          * writes to the queue, it is theoretically possible to wrap around
 495          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 496          * requires that 0.1% of your interrupts are handled, so this isn't
 497          * a big problem.
 498          */
 499         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 500                 return IRQ_NONE;
 501
 502         writel(head, nvmeq->q_db + 1);
 503         nvmeq->cq_head = head;
 504         nvmeq->cq_phase = phase;
 505
 506         return IRQ_HANDLED;
 507 }
 508
 509 static irqreturn_t nvme_irq(int irq, void *data)
 510 {
 511         irqreturn_t result;
 512         struct nvme_queue *nvmeq = data;
 513         spin_lock(&nvmeq->q_lock);
 514         result = nvme_process_cq(nvmeq);
 515         spin_unlock(&nvmeq->q_lock);
 516         return result;
 517 }
 518
 519 static irqreturn_t nvme_irq_check(int irq, void *data)
 520 {
 521         struct nvme_queue *nvmeq = data;
 522         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 523         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 524                 return IRQ_NONE;
 525         return IRQ_WAKE_THREAD;
 526 }
 527
 528 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 529 {
 530         spin_lock_irq(&nvmeq->q_lock);
 531         cancel_cmdid_data(nvmeq, cmdid);
 532         spin_unlock_irq(&nvmeq->q_lock);
 533 }
 534
 535 /*
 536  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 537  * if the result is positive, it's an NVM Express status code
 538  */
 539 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 540                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 541 {
 542         int cmdid;
 543         struct sync_cmd_info cmdinfo;
 544
 545         cmdinfo.task = current;
 546         cmdinfo.status = -EINTR;
 547
 548         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 549                                                                 timeout);
 550         if (cmdid < 0)
 551                 return cmdid;
 552         cmd->common.command_id = cmdid;
 553
 554         set_current_state(TASK_KILLABLE);
 555         nvme_submit_cmd(nvmeq, cmd);
 556         schedule();
 557
 558         if (cmdinfo.status == -EINTR) {
 559                 nvme_abort_command(nvmeq, cmdid);
 560                 return -EINTR;
 561         }
 562
 563         if (result)
 564                 *result = cmdinfo.result;
 565
 566         return cmdinfo.status;
 567 }
 568
 569 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 570                                                                 u32 *result)
 571 {
 572         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 573 }
 574
 575 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 576 {
 577         int status;
 578         struct nvme_command c;
 579
 580         memset(&c, 0, sizeof(c));
 581         c.delete_queue.opcode = opcode;
 582         c.delete_queue.qid = cpu_to_le16(id);
 583
 584         status = nvme_submit_admin_cmd(dev, &c, NULL);
 585         if (status)
 586                 return -EIO;
 587         return 0;
 588 }
 589
 590 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 591                                                 struct nvme_queue *nvmeq)
 592 {
 593         int status;
 594         struct nvme_command c;
 595         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 596
 597         memset(&c, 0, sizeof(c));
 598         c.create_cq.opcode = nvme_admin_create_cq;
 599         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 600         c.create_cq.cqid = cpu_to_le16(qid);
 601         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 602         c.create_cq.cq_flags = cpu_to_le16(flags);
 603         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 604
 605         status = nvme_submit_admin_cmd(dev, &c, NULL);
 606         if (status)
 607                 return -EIO;
 608         return 0;
 609 }
 610
 611 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 612                                                 struct nvme_queue *nvmeq)
 613 {
 614         int status;
 615         struct nvme_command c;
 616         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 617
 618         memset(&c, 0, sizeof(c));
 619         c.create_sq.opcode = nvme_admin_create_sq;
 620         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 621         c.create_sq.sqid = cpu_to_le16(qid);
 622         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 623         c.create_sq.sq_flags = cpu_to_le16(flags);
 624         c.create_sq.cqid = cpu_to_le16(qid);
 625
 626         status = nvme_submit_admin_cmd(dev, &c, NULL);
 627         if (status)
 628                 return -EIO;
 629         return 0;
 630 }
 631
 632 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 633 {
 634         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 635 }
 636
 637 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 638 {
 639         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 640 }
 641
 642 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 643 {
 644         struct nvme_queue *nvmeq = dev->queues[qid];
 645
 646         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 647
 648         /* Don't tell the adapter to delete the admin queue */
 649         if (qid) {
 650                 adapter_delete_sq(dev, qid);
 651                 adapter_delete_cq(dev, qid);
 652         }
 653
 654         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 655                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 656         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 657                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 658         kfree(nvmeq);
 659 }
 660
 661 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 662                                                         int depth, int vector)
 663 {
 664         struct device *dmadev = &dev->pci_dev->dev;
 665         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 666         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 667         if (!nvmeq)
 668                 return NULL;
 669
 670         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 671                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 672         if (!nvmeq->cqes)
 673                 goto free_nvmeq;
 674         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 675
 676         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 677                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 678         if (!nvmeq->sq_cmds)
 679                 goto free_cqdma;
 680
 681         nvmeq->q_dmadev = dmadev;
 682         spin_lock_init(&nvmeq->q_lock);
 683         nvmeq->cq_head = 0;
 684         nvmeq->cq_phase = 1;
 685         init_waitqueue_head(&nvmeq->sq_full);
 686         bio_list_init(&nvmeq->sq_cong);
 687         nvmeq->q_db = &dev->dbs[qid * 2];
 688         nvmeq->q_depth = depth;
 689         nvmeq->cq_vector = vector;
 690
 691         return nvmeq;
 692
 693  free_cqdma:
 694         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 695                                                         nvmeq->cq_dma_addr);
 696  free_nvmeq:
 697         kfree(nvmeq);
 698         return NULL;
 699 }
 700
 701 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 702                                                         const char *name)
 703 {
 704         if (use_threaded_interrupts)
 705                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 706                                         nvme_irq_check, nvme_irq,
 707                                         IRQF_DISABLED | IRQF_SHARED,
 708                                         name, nvmeq);
 709         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 710                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 711 }
 712
 713 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 714                                         int qid, int cq_size, int vector)
 715 {
 716         int result;
 717         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 718
 719         if (!nvmeq)
 720                 return NULL;
 721
 722         result = adapter_alloc_cq(dev, qid, nvmeq);
 723         if (result < 0)
 724                 goto free_nvmeq;
 725
 726         result = adapter_alloc_sq(dev, qid, nvmeq);
 727         if (result < 0)
 728                 goto release_cq;
 729
 730         result = queue_request_irq(dev, nvmeq, "nvme");
 731         if (result < 0)
 732                 goto release_sq;
 733
 734         return nvmeq;
 735
 736  release_sq:
 737         adapter_delete_sq(dev, qid);
 738  release_cq:
 739         adapter_delete_cq(dev, qid);
 740  free_nvmeq:
 741         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 742                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 743         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 744                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 745         kfree(nvmeq);
 746         return NULL;
 747 }
 748
 749 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 750 {
 751         int result;
 752         u32 aqa;
 753         struct nvme_queue *nvmeq;
 754
 755         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 756
 757         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 758         if (!nvmeq)
 759                 return -ENOMEM;
 760
 761         aqa = nvmeq->q_depth - 1;
 762         aqa |= aqa << 16;
 763
 764         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 765         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 766         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 767
 768         writel(0, &dev->bar->cc);
 769         writel(aqa, &dev->bar->aqa);
 770         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 771         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 772         writel(dev->ctrl_config, &dev->bar->cc);
 773
 774         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 775                 msleep(100);
 776                 if (fatal_signal_pending(current))
 777                         return -EINTR;
 778         }
 779
 780         result = queue_request_irq(dev, nvmeq, "nvme admin");
 781         dev->queues[0] = nvmeq;
 782         return result;
 783 }
 784
 785 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 786                                 unsigned long addr, unsigned length,
 787                                 struct scatterlist **sgp)
 788 {
 789         int i, err, count, nents, offset;
 790         struct scatterlist *sg;
 791         struct page **pages;
 792
 793         if (addr & 3)
 794                 return -EINVAL;
 795         if (!length)
 796                 return -EINVAL;
 797
 798         offset = offset_in_page(addr);
 799         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 800         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 801
 802         err = get_user_pages_fast(addr, count, 1, pages);
 803         if (err < count) {
 804                 count = err;
 805                 err = -EFAULT;
 806                 goto put_pages;
 807         }
 808
 809         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 810         sg_init_table(sg, count);
 811         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 812         length -= (PAGE_SIZE - offset);
 813         for (i = 1; i < count; i++) {
 814                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 815                 length -= PAGE_SIZE;
 816         }
 817
 818         err = -ENOMEM;
 819         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 820                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 821         if (!nents)
 822                 goto put_pages;
 823
 824         kfree(pages);
 825         *sgp = sg;
 826         return nents;
 827
 828  put_pages:
 829         for (i = 0; i < count; i++)
 830                 put_page(pages[i]);
 831         kfree(pages);
 832         return err;
 833 }
 834
 835 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 836                                 unsigned long addr, int length,
 837                                 struct scatterlist *sg, int nents)
 838 {
 839         int i, count;
 840
 841         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 842         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 843
 844         for (i = 0; i < count; i++)
 845                 put_page(sg_page(&sg[i]));
 846 }
 847
 848 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 849                                         unsigned long addr, unsigned length,
 850                                         struct nvme_command *cmd)
 851 {
 852         int err, nents;
 853         struct scatterlist *sg;
 854
 855         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 856         if (nents < 0)
 857                 return nents;
 858         nvme_setup_prps(&cmd->common, sg, length);
 859         err = nvme_submit_admin_cmd(dev, cmd, NULL);
 860         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
 861         return err ? -EIO : 0;
 862 }
 863
 864 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
 865 {
 866         struct nvme_command c;
 867
 868         memset(&c, 0, sizeof(c));
 869         c.identify.opcode = nvme_admin_identify;
 870         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
 871         c.identify.cns = cpu_to_le32(cns);
 872
 873         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 874 }
 875
 876 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
 877 {
 878         struct nvme_command c;
 879
 880         memset(&c, 0, sizeof(c));
 881         c.features.opcode = nvme_admin_get_features;
 882         c.features.nsid = cpu_to_le32(ns->ns_id);
 883         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
 884
 885         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 886 }
 887
 888 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
 889 {
 890         struct nvme_dev *dev = ns->dev;
 891         struct nvme_queue *nvmeq;
 892         struct nvme_user_io io;
 893         struct nvme_command c;
 894         unsigned length;
 895         u32 result;
 896         int nents, status;
 897         struct scatterlist *sg;
 898
 899         if (copy_from_user(&io, uio, sizeof(io)))
 900                 return -EFAULT;
 901         length = io.nblocks << io.block_shift;
 902         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
 903         if (nents < 0)
 904                 return nents;
 905
 906         memset(&c, 0, sizeof(c));
 907         c.rw.opcode = io.opcode;
 908         c.rw.flags = io.flags;
 909         c.rw.nsid = cpu_to_le32(io.nsid);
 910         c.rw.slba = cpu_to_le64(io.slba);
 911         c.rw.length = cpu_to_le16(io.nblocks - 1);
 912         c.rw.control = cpu_to_le16(io.control);
 913         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
 914         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
 915         c.rw.apptag = cpu_to_le16(io.apptag);
 916         c.rw.appmask = cpu_to_le16(io.appmask);
 917         /* XXX: metadata */
 918         nvme_setup_prps(&c.common, sg, length);
 919
 920         nvmeq = get_nvmeq(ns);
 921         /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
 922          * disabled.  We may be preempted at any point, and be rescheduled
 923          * to a different CPU.  That will cause cacheline bouncing, but no
 924          * additional races since q_lock already protects against other CPUs.
 925          */
 926         put_nvmeq(nvmeq);
 927         status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
 928
 929         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
 930         put_user(result, &uio->result);
 931         return status;
 932 }
 933
 934 static int nvme_download_firmware(struct nvme_ns *ns,
 935                                                 struct nvme_dlfw __user *udlfw)
 936 {
 937         struct nvme_dev *dev = ns->dev;
 938         struct nvme_dlfw dlfw;
 939         struct nvme_command c;
 940         int nents, status;
 941         struct scatterlist *sg;
 942
 943         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
 944                 return -EFAULT;
 945         if (dlfw.length >= (1 << 30))
 946                 return -EINVAL;
 947
 948         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
 949         if (nents < 0)
 950                 return nents;
 951
 952         memset(&c, 0, sizeof(c));
 953         c.dlfw.opcode = nvme_admin_download_fw;
 954         c.dlfw.numd = cpu_to_le32(dlfw.length);
 955         c.dlfw.offset = cpu_to_le32(dlfw.offset);
 956         nvme_setup_prps(&c.common, sg, dlfw.length * 4);
 957
 958         status = nvme_submit_admin_cmd(dev, &c, NULL);
 959         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
 960         return status;
 961 }
 962
 963 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
 964 {
 965         struct nvme_dev *dev = ns->dev;
 966         struct nvme_command c;
 967
 968         memset(&c, 0, sizeof(c));
 969         c.common.opcode = nvme_admin_activate_fw;
 970         c.common.rsvd10[0] = cpu_to_le32(arg);
 971
 972         return nvme_submit_admin_cmd(dev, &c, NULL);
 973 }
 974
 975 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
 976                                                         unsigned long arg)
 977 {
 978         struct nvme_ns *ns = bdev->bd_disk->private_data;
 979
 980         switch (cmd) {
 981         case NVME_IOCTL_IDENTIFY_NS:
 982                 return nvme_identify(ns, arg, 0);
 983         case NVME_IOCTL_IDENTIFY_CTRL:
 984                 return nvme_identify(ns, arg, 1);
 985         case NVME_IOCTL_GET_RANGE_TYPE:
 986                 return nvme_get_range_type(ns, arg);
 987         case NVME_IOCTL_SUBMIT_IO:
 988                 return nvme_submit_io(ns, (void __user *)arg);
 989         case NVME_IOCTL_DOWNLOAD_FW:
 990                 return nvme_download_firmware(ns, (void __user *)arg);
 991         case NVME_IOCTL_ACTIVATE_FW:
 992                 return nvme_activate_firmware(ns, arg);
 993         default:
 994                 return -ENOTTY;
 995         }
 996 }
 997
 998 static const struct block_device_operations nvme_fops = {
 999         .owner          = THIS_MODULE,
1000         .ioctl          = nvme_ioctl,
1001 };
1002
1003 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1004                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1005 {
1006         struct nvme_ns *ns;
1007         struct gendisk *disk;
1008         int lbaf;
1009
1010         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1011                 return NULL;
1012
1013         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1014         if (!ns)
1015                 return NULL;
1016         ns->queue = blk_alloc_queue(GFP_KERNEL);
1017         if (!ns->queue)
1018                 goto out_free_ns;
1019         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1020                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1021         blk_queue_make_request(ns->queue, nvme_make_request);
1022         ns->dev = dev;
1023         ns->queue->queuedata = ns;
1024
1025         disk = alloc_disk(NVME_MINORS);
1026         if (!disk)
1027                 goto out_free_queue;
1028         ns->ns_id = index;
1029         ns->disk = disk;
1030         lbaf = id->flbas & 0xf;
1031         ns->lba_shift = id->lbaf[lbaf].ds;
1032
1033         disk->major = nvme_major;
1034         disk->minors = NVME_MINORS;
1035         disk->first_minor = NVME_MINORS * index;
1036         disk->fops = &nvme_fops;
1037         disk->private_data = ns;
1038         disk->queue = ns->queue;
1039         disk->driverfs_dev = &dev->pci_dev->dev;
1040         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1041         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1042
1043         return ns;
1044
1045  out_free_queue:
1046         blk_cleanup_queue(ns->queue);
1047  out_free_ns:
1048         kfree(ns);
1049         return NULL;
1050 }
1051
1052 static void nvme_ns_free(struct nvme_ns *ns)
1053 {
1054         put_disk(ns->disk);
1055         blk_cleanup_queue(ns->queue);
1056         kfree(ns);
1057 }
1058
1059 static int set_queue_count(struct nvme_dev *dev, int count)
1060 {
1061         int status;
1062         u32 result;
1063         struct nvme_command c;
1064         u32 q_count = (count - 1) | ((count - 1) << 16);
1065
1066         memset(&c, 0, sizeof(c));
1067         c.features.opcode = nvme_admin_get_features;
1068         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1069         c.features.dword11 = cpu_to_le32(q_count);
1070
1071         status = nvme_submit_admin_cmd(dev, &c, &result);
1072         if (status)
1073                 return -EIO;
1074         return min(result & 0xffff, result >> 16) + 1;
1075 }
1076
1077 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1078 {
1079         int result, cpu, i, nr_queues;
1080
1081         nr_queues = num_online_cpus();
1082         result = set_queue_count(dev, nr_queues);
1083         if (result < 0)
1084                 return result;
1085         if (result < nr_queues)
1086                 nr_queues = result;
1087
1088         /* Deregister the admin queue's interrupt */
1089         free_irq(dev->entry[0].vector, dev->queues[0]);
1090
1091         for (i = 0; i < nr_queues; i++)
1092                 dev->entry[i].entry = i;
1093         for (;;) {
1094                 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1095                 if (result == 0) {
1096                         break;
1097                 } else if (result > 0) {
1098                         nr_queues = result;
1099                         continue;
1100                 } else {
1101                         nr_queues = 1;
1102                         break;
1103                 }
1104         }
1105
1106         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1107         /* XXX: handle failure here */
1108
1109         cpu = cpumask_first(cpu_online_mask);
1110         for (i = 0; i < nr_queues; i++) {
1111                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1112                 cpu = cpumask_next(cpu, cpu_online_mask);
1113         }
1114
1115         for (i = 0; i < nr_queues; i++) {
1116                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1117                                                         NVME_Q_DEPTH, i);
1118                 if (!dev->queues[i + 1])
1119                         return -ENOMEM;
1120                 dev->queue_count++;
1121         }
1122
1123         return 0;
1124 }
1125
1126 static void nvme_free_queues(struct nvme_dev *dev)
1127 {
1128         int i;
1129
1130         for (i = dev->queue_count - 1; i >= 0; i--)
1131                 nvme_free_queue(dev, i);
1132 }
1133
1134 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1135 {
1136         int res, nn, i;
1137         struct nvme_ns *ns, *next;
1138         struct nvme_id_ctrl *ctrl;
1139         void *id;
1140         dma_addr_t dma_addr;
1141         struct nvme_command cid, crt;
1142
1143         res = nvme_setup_io_queues(dev);
1144         if (res)
1145                 return res;
1146
1147         /* XXX: Switch to a SG list once prp2 works */
1148         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1149                                                                 GFP_KERNEL);
1150
1151         memset(&cid, 0, sizeof(cid));
1152         cid.identify.opcode = nvme_admin_identify;
1153         cid.identify.nsid = 0;
1154         cid.identify.prp1 = cpu_to_le64(dma_addr);
1155         cid.identify.cns = cpu_to_le32(1);
1156
1157         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1158         if (res) {
1159                 res = -EIO;
1160                 goto out_free;
1161         }
1162
1163         ctrl = id;
1164         nn = le32_to_cpup(&ctrl->nn);
1165         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1166         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1167         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1168
1169         cid.identify.cns = 0;
1170         memset(&crt, 0, sizeof(crt));
1171         crt.features.opcode = nvme_admin_get_features;
1172         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1173         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1174
1175         for (i = 0; i < nn; i++) {
1176                 cid.identify.nsid = cpu_to_le32(i);
1177                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1178                 if (res)
1179                         continue;
1180
1181                 if (((struct nvme_id_ns *)id)->ncap == 0)
1182                         continue;
1183
1184                 crt.features.nsid = cpu_to_le32(i);
1185                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1186                 if (res)
1187                         continue;
1188
1189                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1190                 if (ns)
1191                         list_add_tail(&ns->list, &dev->namespaces);
1192         }
1193         list_for_each_entry(ns, &dev->namespaces, list)
1194                 add_disk(ns->disk);
1195
1196         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1197         return 0;
1198
1199  out_free:
1200         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1201                 list_del(&ns->list);
1202                 nvme_ns_free(ns);
1203         }
1204
1205         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1206         return res;
1207 }
1208
1209 static int nvme_dev_remove(struct nvme_dev *dev)
1210 {
1211         struct nvme_ns *ns, *next;
1212
1213         /* TODO: wait all I/O finished or cancel them */
1214
1215         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1216                 list_del(&ns->list);
1217                 del_gendisk(ns->disk);
1218                 nvme_ns_free(ns);
1219         }
1220
1221         nvme_free_queues(dev);
1222
1223         return 0;
1224 }
1225
1226 /* XXX: Use an ida or something to let remove / add work correctly */
1227 static void nvme_set_instance(struct nvme_dev *dev)
1228 {
1229         static int instance;
1230         dev->instance = instance++;
1231 }
1232
1233 static void nvme_release_instance(struct nvme_dev *dev)
1234 {
1235 }
1236
1237 static int __devinit nvme_probe(struct pci_dev *pdev,
1238                                                 const struct pci_device_id *id)
1239 {
1240         int bars, result = -ENOMEM;
1241         struct nvme_dev *dev;
1242
1243         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1244         if (!dev)
1245                 return -ENOMEM;
1246         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1247                                                                 GFP_KERNEL);
1248         if (!dev->entry)
1249                 goto free;
1250         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1251                                                                 GFP_KERNEL);
1252         if (!dev->queues)
1253                 goto free;
1254
1255         if (pci_enable_device_mem(pdev))
1256                 goto free;
1257         pci_set_master(pdev);
1258         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1259         if (pci_request_selected_regions(pdev, bars, "nvme"))
1260                 goto disable;
1261
1262         INIT_LIST_HEAD(&dev->namespaces);
1263         dev->pci_dev = pdev;
1264         pci_set_drvdata(pdev, dev);
1265         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1266         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1267         nvme_set_instance(dev);
1268         dev->entry[0].vector = pdev->irq;
1269
1270         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1271         if (!dev->bar) {
1272                 result = -ENOMEM;
1273                 goto disable_msix;
1274         }
1275
1276         result = nvme_configure_admin_queue(dev);
1277         if (result)
1278                 goto unmap;
1279         dev->queue_count++;
1280
1281         result = nvme_dev_add(dev);
1282         if (result)
1283                 goto delete;
1284         return 0;
1285
1286  delete:
1287         nvme_free_queues(dev);
1288  unmap:
1289         iounmap(dev->bar);
1290  disable_msix:
1291         pci_disable_msix(pdev);
1292         nvme_release_instance(dev);
1293  disable:
1294         pci_disable_device(pdev);
1295         pci_release_regions(pdev);
1296  free:
1297         kfree(dev->queues);
1298         kfree(dev->entry);
1299         kfree(dev);
1300         return result;
1301 }
1302
1303 static void __devexit nvme_remove(struct pci_dev *pdev)
1304 {
1305         struct nvme_dev *dev = pci_get_drvdata(pdev);
1306         nvme_dev_remove(dev);
1307         pci_disable_msix(pdev);
1308         iounmap(dev->bar);
1309         nvme_release_instance(dev);
1310         pci_disable_device(pdev);
1311         pci_release_regions(pdev);
1312         kfree(dev->queues);
1313         kfree(dev->entry);
1314         kfree(dev);
1315 }
1316
1317 /* These functions are yet to be implemented */
1318 #define nvme_error_detected NULL
1319 #define nvme_dump_registers NULL
1320 #define nvme_link_reset NULL
1321 #define nvme_slot_reset NULL
1322 #define nvme_error_resume NULL
1323 #define nvme_suspend NULL
1324 #define nvme_resume NULL
1325
1326 static struct pci_error_handlers nvme_err_handler = {
1327         .error_detected = nvme_error_detected,
1328         .mmio_enabled   = nvme_dump_registers,
1329         .link_reset     = nvme_link_reset,
1330         .slot_reset     = nvme_slot_reset,
1331         .resume         = nvme_error_resume,
1332 };
1333
1334 /* Move to pci_ids.h later */
1335 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1336
1337 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1338         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1339         { 0, }
1340 };
1341 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1342
1343 static struct pci_driver nvme_driver = {
1344         .name           = "nvme",
1345         .id_table       = nvme_id_table,
1346         .probe          = nvme_probe,
1347         .remove         = __devexit_p(nvme_remove),
1348         .suspend        = nvme_suspend,
1349         .resume         = nvme_resume,
1350         .err_handler    = &nvme_err_handler,
1351 };
1352
1353 static int __init nvme_init(void)
1354 {
1355         int result;
1356
1357         nvme_major = register_blkdev(nvme_major, "nvme");
1358         if (nvme_major <= 0)
1359                 return -EBUSY;
1360
1361         result = pci_register_driver(&nvme_driver);
1362         if (!result)
1363                 return 0;
1364
1365         unregister_blkdev(nvme_major, "nvme");
1366         return result;
1367 }
1368
1369 static void __exit nvme_exit(void)
1370 {
1371         pci_unregister_driver(&nvme_driver);
1372         unregister_blkdev(nvme_major, "nvme");
1373 }
1374
1375 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1376 MODULE_LICENSE("GPL");
1377 MODULE_VERSION("0.2");
1378 module_init(nvme_init);
1379 module_exit(nvme_exit);