drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kernel.h>
  30 #include <linux/mm.h>
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/sched.h>
  35 #include <linux/slab.h>
  36 #include <linux/types.h>
  37 #include <linux/version.h>
  38
  39 #define NVME_Q_DEPTH 1024
  40 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  41 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  42 #define NVME_MINORS 64
  43
  44 static int nvme_major;
  45 module_param(nvme_major, int, 0);
  46
  47 /*
  48  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  49  */
  50 struct nvme_dev {
  51         struct list_head node;
  52         struct nvme_queue **queues;
  53         u32 __iomem *dbs;
  54         struct pci_dev *pci_dev;
  55         int instance;
  56         int queue_count;
  57         u32 ctrl_config;
  58         struct msix_entry *entry;
  59         struct nvme_bar __iomem *bar;
  60         struct list_head namespaces;
  61 };
  62
  63 /*
  64  * An NVM Express namespace is equivalent to a SCSI LUN
  65  */
  66 struct nvme_ns {
  67         struct list_head list;
  68
  69         struct nvme_dev *dev;
  70         struct request_queue *queue;
  71         struct gendisk *disk;
  72
  73         int ns_id;
  74         int lba_shift;
  75 };
  76
  77 /*
  78  * An NVM Express queue.  Each device has at least two (one for admin
  79  * commands and one for I/O commands).
  80  */
  81 struct nvme_queue {
  82         struct device *q_dmadev;
  83         spinlock_t q_lock;
  84         struct nvme_command *sq_cmds;
  85         volatile struct nvme_completion *cqes;
  86         dma_addr_t sq_dma_addr;
  87         dma_addr_t cq_dma_addr;
  88         wait_queue_head_t sq_full;
  89         struct bio_list sq_cong;
  90         u32 __iomem *q_db;
  91         u16 q_depth;
  92         u16 cq_vector;
  93         u16 sq_head;
  94         u16 sq_tail;
  95         u16 cq_head;
  96         u16 cq_phase;
  97         unsigned long cmdid_data[];
  98 };
  99
 100 /*
 101  * Check we didin't inadvertently grow the command struct
 102  */
 103 static inline void _nvme_check_size(void)
 104 {
 105         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 106         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 107         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 108         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 109         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 110         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 111         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 112         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 113         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 114 }
 115
 116 /**
 117  * alloc_cmdid - Allocate a Command ID
 118  * @param nvmeq The queue that will be used for this command
 119  * @param ctx A pointer that will be passed to the handler
 120  * @param handler The ID of the handler to call
 121  *
 122  * Allocate a Command ID for a queue.  The data passed in will
 123  * be passed to the completion handler.  This is implemented by using
 124  * the bottom two bits of the ctx pointer to store the handler ID.
 125  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 126  * We can change this if it becomes a problem.
 127  */
 128 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler)
 129 {
 130         int depth = nvmeq->q_depth;
 131         unsigned long data = (unsigned long)ctx | handler;
 132         int cmdid;
 133
 134         BUG_ON((unsigned long)ctx & 3);
 135
 136         do {
 137                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 138                 if (cmdid >= depth)
 139                         return -EBUSY;
 140         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 141
 142         nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(depth)] = data;
 143         return cmdid;
 144 }
 145
 146 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 147                                                                 int handler)
 148 {
 149         int cmdid;
 150         wait_event_killable(nvmeq->sq_full,
 151                         (cmdid = alloc_cmdid(nvmeq, ctx, handler)) >= 0);
 152         return (cmdid < 0) ? -EINTR : cmdid;
 153 }
 154
 155 /* If you need more than four handlers, you'll need to change how
 156  * alloc_cmdid and nvme_process_cq work
 157  */
 158 enum {
 159         sync_completion_id = 0,
 160         bio_completion_id,
 161 };
 162
 163 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 164 {
 165         unsigned long data;
 166
 167         data = nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(nvmeq->q_depth)];
 168         clear_bit(cmdid, nvmeq->cmdid_data);
 169         wake_up(&nvmeq->sq_full);
 170         return data;
 171 }
 172
 173 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 174 {
 175         int qid, cpu = get_cpu();
 176         if (cpu < ns->dev->queue_count)
 177                 qid = cpu + 1;
 178         else
 179                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 180         return ns->dev->queues[qid];
 181 }
 182
 183 static void put_nvmeq(struct nvme_queue *nvmeq)
 184 {
 185         put_cpu();
 186 }
 187
 188 /**
 189  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 190  * @nvmeq: The queue to use
 191  * @cmd: The command to send
 192  *
 193  * Safe to use from interrupt context
 194  */
 195 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 196 {
 197         unsigned long flags;
 198         u16 tail;
 199         /* XXX: Need to check tail isn't going to overrun head */
 200         spin_lock_irqsave(&nvmeq->q_lock, flags);
 201         tail = nvmeq->sq_tail;
 202         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 203         writel(tail, nvmeq->q_db);
 204         if (++tail == nvmeq->q_depth)
 205                 tail = 0;
 206         nvmeq->sq_tail = tail;
 207         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 208
 209         return 0;
 210 }
 211
 212 struct nvme_req_info {
 213         struct bio *bio;
 214         int nents;
 215         struct scatterlist sg[0];
 216 };
 217
 218 /* XXX: use a mempool */
 219 static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp)
 220 {
 221         return kmalloc(sizeof(struct nvme_req_info) +
 222                         sizeof(struct scatterlist) * nseg, gfp);
 223 }
 224
 225 static void free_info(struct nvme_req_info *info)
 226 {
 227         kfree(info);
 228 }
 229
 230 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 231                                                 struct nvme_completion *cqe)
 232 {
 233         struct nvme_req_info *info = ctx;
 234         struct bio *bio = info->bio;
 235         u16 status = le16_to_cpup(&cqe->status) >> 1;
 236
 237         dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents,
 238                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 239         free_info(info);
 240         bio_endio(bio, status ? -EIO : 0);
 241 }
 242
 243 /* length is in bytes */
 244 static void nvme_setup_prps(struct nvme_common_command *cmd,
 245                                         struct scatterlist *sg, int length)
 246 {
 247         int dma_len = sg_dma_len(sg);
 248         u64 dma_addr = sg_dma_address(sg);
 249         int offset = offset_in_page(dma_addr);
 250
 251         cmd->prp1 = cpu_to_le64(dma_addr);
 252         length -= (PAGE_SIZE - offset);
 253         if (length <= 0)
 254                 return;
 255
 256         dma_len -= (PAGE_SIZE - offset);
 257         if (dma_len) {
 258                 dma_addr += (PAGE_SIZE - offset);
 259         } else {
 260                 sg = sg_next(sg);
 261                 dma_addr = sg_dma_address(sg);
 262                 dma_len = sg_dma_len(sg);
 263         }
 264
 265         if (length <= PAGE_SIZE) {
 266                 cmd->prp2 = cpu_to_le64(dma_addr);
 267                 return;
 268         }
 269
 270         /* XXX: support PRP lists */
 271 }
 272
 273 static int nvme_map_bio(struct device *dev, struct nvme_req_info *info,
 274                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 275 {
 276         struct bio_vec *bvec;
 277         struct scatterlist *sg = info->sg;
 278         int i, nsegs;
 279
 280         sg_init_table(sg, psegs);
 281         bio_for_each_segment(bvec, bio, i) {
 282                 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
 283                 /* XXX: handle non-mergable here */
 284                 nsegs++;
 285         }
 286         info->nents = nsegs;
 287
 288         return dma_map_sg(dev, info->sg, info->nents, dma_dir);
 289 }
 290
 291 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 292                                                                 struct bio *bio)
 293 {
 294         struct nvme_command *cmnd;
 295         struct nvme_req_info *info;
 296         enum dma_data_direction dma_dir;
 297         int cmdid;
 298         u16 control;
 299         u32 dsmgmt;
 300         unsigned long flags;
 301         int psegs = bio_phys_segments(ns->queue, bio);
 302
 303         info = alloc_info(psegs, GFP_NOIO);
 304         if (!info)
 305                 goto congestion;
 306         info->bio = bio;
 307
 308         cmdid = alloc_cmdid(nvmeq, info, bio_completion_id);
 309         if (unlikely(cmdid < 0))
 310                 goto free_info;
 311
 312         control = 0;
 313         if (bio->bi_rw & REQ_FUA)
 314                 control |= NVME_RW_FUA;
 315         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 316                 control |= NVME_RW_LR;
 317
 318         dsmgmt = 0;
 319         if (bio->bi_rw & REQ_RAHEAD)
 320                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 321
 322         spin_lock_irqsave(&nvmeq->q_lock, flags);
 323         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 324
 325         memset(cmnd, 0, sizeof(*cmnd));
 326         if (bio_data_dir(bio)) {
 327                 cmnd->rw.opcode = nvme_cmd_write;
 328                 dma_dir = DMA_TO_DEVICE;
 329         } else {
 330                 cmnd->rw.opcode = nvme_cmd_read;
 331                 dma_dir = DMA_FROM_DEVICE;
 332         }
 333
 334         nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs);
 335
 336         cmnd->rw.flags = 1;
 337         cmnd->rw.command_id = cmdid;
 338         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 339         nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size);
 340         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 341         cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
 342         cmnd->rw.control = cpu_to_le16(control);
 343         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 344
 345         writel(nvmeq->sq_tail, nvmeq->q_db);
 346         if (++nvmeq->sq_tail == nvmeq->q_depth)
 347                 nvmeq->sq_tail = 0;
 348
 349         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 350
 351         return 0;
 352
 353  free_info:
 354         free_info(info);
 355  congestion:
 356         return -EBUSY;
 357 }
 358
 359 /*
 360  * NB: return value of non-zero would mean that we were a stacking driver.
 361  * make_request must always succeed.
 362  */
 363 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 364 {
 365         struct nvme_ns *ns = q->queuedata;
 366         struct nvme_queue *nvmeq = get_nvmeq(ns);
 367
 368         if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
 369                 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
 370                 bio_list_add(&nvmeq->sq_cong, bio);
 371         }
 372         put_nvmeq(nvmeq);
 373
 374         return 0;
 375 }
 376
 377 struct sync_cmd_info {
 378         struct task_struct *task;
 379         u32 result;
 380         int status;
 381 };
 382
 383 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 384                                                 struct nvme_completion *cqe)
 385 {
 386         struct sync_cmd_info *cmdinfo = ctx;
 387         cmdinfo->result = le32_to_cpup(&cqe->result);
 388         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 389         wake_up_process(cmdinfo->task);
 390 }
 391
 392 typedef void (*completion_fn)(struct nvme_queue *, void *,
 393                                                 struct nvme_completion *);
 394
 395 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 396 {
 397         u16 head, phase;
 398
 399         static const completion_fn completions[4] = {
 400                 [sync_completion_id] = sync_completion,
 401                 [bio_completion_id]  = bio_completion,
 402         };
 403
 404         head = nvmeq->cq_head;
 405         phase = nvmeq->cq_phase;
 406
 407         for (;;) {
 408                 unsigned long data;
 409                 void *ptr;
 410                 unsigned char handler;
 411                 struct nvme_completion cqe = nvmeq->cqes[head];
 412                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 413                         break;
 414                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 415                 if (++head == nvmeq->q_depth) {
 416                         head = 0;
 417                         phase = !phase;
 418                 }
 419
 420                 data = free_cmdid(nvmeq, cqe.command_id);
 421                 handler = data & 3;
 422                 ptr = (void *)(data & ~3UL);
 423                 completions[handler](nvmeq, ptr, &cqe);
 424         }
 425
 426         /* If the controller ignores the cq head doorbell and continuously
 427          * writes to the queue, it is theoretically possible to wrap around
 428          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 429          * requires that 0.1% of your interrupts are handled, so this isn't
 430          * a big problem.
 431          */
 432         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 433                 return IRQ_NONE;
 434
 435         writel(head, nvmeq->q_db + 1);
 436         nvmeq->cq_head = head;
 437         nvmeq->cq_phase = phase;
 438
 439         return IRQ_HANDLED;
 440 }
 441
 442 static irqreturn_t nvme_irq(int irq, void *data)
 443 {
 444         return nvme_process_cq(data);
 445 }
 446
 447 /*
 448  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 449  * if the result is positive, it's an NVM Express status code
 450  */
 451 static int nvme_submit_sync_cmd(struct nvme_queue *q, struct nvme_command *cmd,
 452                                                                 u32 *result)
 453 {
 454         int cmdid;
 455         struct sync_cmd_info cmdinfo;
 456
 457         cmdinfo.task = current;
 458         cmdinfo.status = -EINTR;
 459
 460         cmdid = alloc_cmdid_killable(q, &cmdinfo, sync_completion_id);
 461         if (cmdid < 0)
 462                 return cmdid;
 463         cmd->common.command_id = cmdid;
 464
 465         set_current_state(TASK_UNINTERRUPTIBLE);
 466         nvme_submit_cmd(q, cmd);
 467         schedule();
 468
 469         if (result)
 470                 *result = cmdinfo.result;
 471
 472         return cmdinfo.status;
 473 }
 474
 475 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 476                                                                 u32 *result)
 477 {
 478         return nvme_submit_sync_cmd(dev->queues[0], cmd, result);
 479 }
 480
 481 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 482 {
 483         int status;
 484         struct nvme_command c;
 485
 486         memset(&c, 0, sizeof(c));
 487         c.delete_queue.opcode = opcode;
 488         c.delete_queue.qid = cpu_to_le16(id);
 489
 490         status = nvme_submit_admin_cmd(dev, &c, NULL);
 491         if (status)
 492                 return -EIO;
 493         return 0;
 494 }
 495
 496 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 497                                                 struct nvme_queue *nvmeq)
 498 {
 499         int status;
 500         struct nvme_command c;
 501         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 502
 503         memset(&c, 0, sizeof(c));
 504         c.create_cq.opcode = nvme_admin_create_cq;
 505         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 506         c.create_cq.cqid = cpu_to_le16(qid);
 507         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 508         c.create_cq.cq_flags = cpu_to_le16(flags);
 509         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 510
 511         status = nvme_submit_admin_cmd(dev, &c, NULL);
 512         if (status)
 513                 return -EIO;
 514         return 0;
 515 }
 516
 517 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 518                                                 struct nvme_queue *nvmeq)
 519 {
 520         int status;
 521         struct nvme_command c;
 522         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 523
 524         memset(&c, 0, sizeof(c));
 525         c.create_sq.opcode = nvme_admin_create_sq;
 526         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 527         c.create_sq.sqid = cpu_to_le16(qid);
 528         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 529         c.create_sq.sq_flags = cpu_to_le16(flags);
 530         c.create_sq.cqid = cpu_to_le16(qid);
 531
 532         status = nvme_submit_admin_cmd(dev, &c, NULL);
 533         if (status)
 534                 return -EIO;
 535         return 0;
 536 }
 537
 538 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 539 {
 540         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 541 }
 542
 543 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 544 {
 545         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 546 }
 547
 548 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 549 {
 550         struct nvme_queue *nvmeq = dev->queues[qid];
 551
 552         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 553
 554         /* Don't tell the adapter to delete the admin queue */
 555         if (qid) {
 556                 adapter_delete_sq(dev, qid);
 557                 adapter_delete_cq(dev, qid);
 558         }
 559
 560         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 561                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 562         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 563                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 564         kfree(nvmeq);
 565 }
 566
 567 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 568                                                         int depth, int vector)
 569 {
 570         struct device *dmadev = &dev->pci_dev->dev;
 571         unsigned extra = (depth + BITS_TO_LONGS(depth)) * sizeof(long);
 572         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 573         if (!nvmeq)
 574                 return NULL;
 575
 576         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 577                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 578         if (!nvmeq->cqes)
 579                 goto free_nvmeq;
 580         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 581
 582         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 583                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 584         if (!nvmeq->sq_cmds)
 585                 goto free_cqdma;
 586
 587         nvmeq->q_dmadev = dmadev;
 588         spin_lock_init(&nvmeq->q_lock);
 589         nvmeq->cq_head = 0;
 590         nvmeq->cq_phase = 1;
 591         init_waitqueue_head(&nvmeq->sq_full);
 592         bio_list_init(&nvmeq->sq_cong);
 593         nvmeq->q_db = &dev->dbs[qid * 2];
 594         nvmeq->q_depth = depth;
 595         nvmeq->cq_vector = vector;
 596
 597         return nvmeq;
 598
 599  free_cqdma:
 600         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 601                                                         nvmeq->cq_dma_addr);
 602  free_nvmeq:
 603         kfree(nvmeq);
 604         return NULL;
 605 }
 606
 607 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 608                                                         const char *name)
 609 {
 610         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 611                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 612 }
 613
 614 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 615                                         int qid, int cq_size, int vector)
 616 {
 617         int result;
 618         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 619
 620         result = adapter_alloc_cq(dev, qid, nvmeq);
 621         if (result < 0)
 622                 goto free_nvmeq;
 623
 624         result = adapter_alloc_sq(dev, qid, nvmeq);
 625         if (result < 0)
 626                 goto release_cq;
 627
 628         result = queue_request_irq(dev, nvmeq, "nvme");
 629         if (result < 0)
 630                 goto release_sq;
 631
 632         return nvmeq;
 633
 634  release_sq:
 635         adapter_delete_sq(dev, qid);
 636  release_cq:
 637         adapter_delete_cq(dev, qid);
 638  free_nvmeq:
 639         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 640                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 641         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 642                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 643         kfree(nvmeq);
 644         return NULL;
 645 }
 646
 647 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 648 {
 649         int result;
 650         u32 aqa;
 651         struct nvme_queue *nvmeq;
 652
 653         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 654
 655         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 656
 657         aqa = nvmeq->q_depth - 1;
 658         aqa |= aqa << 16;
 659
 660         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 661         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 662         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 663
 664         writel(aqa, &dev->bar->aqa);
 665         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 666         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 667         writel(dev->ctrl_config, &dev->bar->cc);
 668
 669         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 670                 msleep(100);
 671                 if (fatal_signal_pending(current))
 672                         return -EINTR;
 673         }
 674
 675         result = queue_request_irq(dev, nvmeq, "nvme admin");
 676         dev->queues[0] = nvmeq;
 677         return result;
 678 }
 679
 680 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
 681 {
 682         struct nvme_dev *dev = ns->dev;
 683         int i, err, count, nents, offset;
 684         struct nvme_command c;
 685         struct scatterlist sg[2];
 686         struct page *pages[2];
 687
 688         if (addr & 3)
 689                 return -EINVAL;
 690         offset = offset_in_page(addr);
 691         count = offset ? 2 : 1;
 692
 693         err = get_user_pages_fast(addr, count, 1, pages);
 694         if (err < count) {
 695                 count = err;
 696                 err = -EFAULT;
 697                 goto put_pages;
 698         }
 699         sg_init_table(sg, count);
 700         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 701         if (count > 1)
 702                 sg_set_page(&sg[1], pages[1], offset, 0);
 703         nents = dma_map_sg(&dev->pci_dev->dev, sg, count, DMA_FROM_DEVICE);
 704         if (!nents)
 705                 goto put_pages;
 706
 707         memset(&c, 0, sizeof(c));
 708         c.identify.opcode = nvme_admin_identify;
 709         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
 710         nvme_setup_prps(&c.common, sg, 4096);
 711         c.identify.cns = cpu_to_le32(cns);
 712
 713         err = nvme_submit_admin_cmd(dev, &c, NULL);
 714
 715         if (err)
 716                 err = -EIO;
 717
 718         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 719  put_pages:
 720         for (i = 0; i < count; i++)
 721                 put_page(pages[i]);
 722
 723         return err;
 724 }
 725
 726 static int nvme_get_range_type(struct nvme_ns *ns, void __user *addr)
 727 {
 728         struct nvme_dev *dev = ns->dev;
 729         int status;
 730         struct nvme_command c;
 731         void *page;
 732         dma_addr_t dma_addr;
 733
 734         page = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
 735                                                                 GFP_KERNEL);
 736
 737         memset(&c, 0, sizeof(c));
 738         c.features.opcode = nvme_admin_get_features;
 739         c.features.nsid = cpu_to_le32(ns->ns_id);
 740         c.features.prp1 = cpu_to_le64(dma_addr);
 741         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
 742
 743         status = nvme_submit_admin_cmd(dev, &c, NULL);
 744
 745         /* XXX: Assuming first range for now */
 746         if (status)
 747                 status = -EIO;
 748         else if (copy_to_user(addr, page, 64))
 749                 status = -EFAULT;
 750
 751         dma_free_coherent(&dev->pci_dev->dev, 4096, page, dma_addr);
 752
 753         return status;
 754 }
 755
 756 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
 757                                                         unsigned long arg)
 758 {
 759         struct nvme_ns *ns = bdev->bd_disk->private_data;
 760
 761         switch (cmd) {
 762         case NVME_IOCTL_IDENTIFY_NS:
 763                 return nvme_identify(ns, arg, 0);
 764         case NVME_IOCTL_IDENTIFY_CTRL:
 765                 return nvme_identify(ns, arg, 1);
 766         case NVME_IOCTL_GET_RANGE_TYPE:
 767                 return nvme_get_range_type(ns, (void __user *)arg);
 768         default:
 769                 return -ENOTTY;
 770         }
 771 }
 772
 773 static const struct block_device_operations nvme_fops = {
 774         .owner          = THIS_MODULE,
 775         .ioctl          = nvme_ioctl,
 776 };
 777
 778 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
 779                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
 780 {
 781         struct nvme_ns *ns;
 782         struct gendisk *disk;
 783         int lbaf;
 784
 785         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
 786                 return NULL;
 787
 788         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
 789         if (!ns)
 790                 return NULL;
 791         ns->queue = blk_alloc_queue(GFP_KERNEL);
 792         if (!ns->queue)
 793                 goto out_free_ns;
 794         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
 795                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
 796         blk_queue_make_request(ns->queue, nvme_make_request);
 797         ns->dev = dev;
 798         ns->queue->queuedata = ns;
 799
 800         disk = alloc_disk(NVME_MINORS);
 801         if (!disk)
 802                 goto out_free_queue;
 803         ns->ns_id = index;
 804         ns->disk = disk;
 805         lbaf = id->flbas & 0xf;
 806         ns->lba_shift = id->lbaf[lbaf].ds;
 807
 808         disk->major = nvme_major;
 809         disk->minors = NVME_MINORS;
 810         disk->first_minor = NVME_MINORS * index;
 811         disk->fops = &nvme_fops;
 812         disk->private_data = ns;
 813         disk->queue = ns->queue;
 814         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
 815         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
 816
 817         return ns;
 818
 819  out_free_queue:
 820         blk_cleanup_queue(ns->queue);
 821  out_free_ns:
 822         kfree(ns);
 823         return NULL;
 824 }
 825
 826 static void nvme_ns_free(struct nvme_ns *ns)
 827 {
 828         put_disk(ns->disk);
 829         blk_cleanup_queue(ns->queue);
 830         kfree(ns);
 831 }
 832
 833 static int set_queue_count(struct nvme_dev *dev, int count)
 834 {
 835         int status;
 836         u32 result;
 837         struct nvme_command c;
 838         u32 q_count = (count - 1) | ((count - 1) << 16);
 839
 840         memset(&c, 0, sizeof(c));
 841         c.features.opcode = nvme_admin_get_features;
 842         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
 843         c.features.dword11 = cpu_to_le32(q_count);
 844
 845         status = nvme_submit_admin_cmd(dev, &c, &result);
 846         if (status)
 847                 return -EIO;
 848         return min(result & 0xffff, result >> 16) + 1;
 849 }
 850
 851 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
 852 {
 853         int result, cpu, i, nr_queues;
 854
 855         nr_queues = num_online_cpus();
 856         result = set_queue_count(dev, nr_queues);
 857         if (result < 0)
 858                 return result;
 859         if (result < nr_queues)
 860                 nr_queues = result;
 861
 862         /* Deregister the admin queue's interrupt */
 863         free_irq(dev->entry[0].vector, dev->queues[0]);
 864
 865         for (i = 0; i < nr_queues; i++)
 866                 dev->entry[i].entry = i;
 867         for (;;) {
 868                 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
 869                 if (result == 0) {
 870                         break;
 871                 } else if (result > 0) {
 872                         nr_queues = result;
 873                         continue;
 874                 } else {
 875                         nr_queues = 1;
 876                         break;
 877                 }
 878         }
 879
 880         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
 881         /* XXX: handle failure here */
 882
 883         cpu = cpumask_first(cpu_online_mask);
 884         for (i = 0; i < nr_queues; i++) {
 885                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
 886                 cpu = cpumask_next(cpu, cpu_online_mask);
 887         }
 888
 889         for (i = 0; i < nr_queues; i++) {
 890                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
 891                                                         NVME_Q_DEPTH, i);
 892                 if (!dev->queues[i + 1])
 893                         return -ENOMEM;
 894                 dev->queue_count++;
 895         }
 896
 897         return 0;
 898 }
 899
 900 static void nvme_free_queues(struct nvme_dev *dev)
 901 {
 902         int i;
 903
 904         for (i = dev->queue_count - 1; i >= 0; i--)
 905                 nvme_free_queue(dev, i);
 906 }
 907
 908 static int __devinit nvme_dev_add(struct nvme_dev *dev)
 909 {
 910         int res, nn, i;
 911         struct nvme_ns *ns, *next;
 912         void *id;
 913         dma_addr_t dma_addr;
 914         struct nvme_command cid, crt;
 915
 916         res = nvme_setup_io_queues(dev);
 917         if (res)
 918                 return res;
 919
 920         /* XXX: Switch to a SG list once prp2 works */
 921         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
 922                                                                 GFP_KERNEL);
 923
 924         memset(&cid, 0, sizeof(cid));
 925         cid.identify.opcode = nvme_admin_identify;
 926         cid.identify.nsid = 0;
 927         cid.identify.prp1 = cpu_to_le64(dma_addr);
 928         cid.identify.cns = cpu_to_le32(1);
 929
 930         res = nvme_submit_admin_cmd(dev, &cid, NULL);
 931         if (res) {
 932                 res = -EIO;
 933                 goto out_free;
 934         }
 935
 936         nn = le32_to_cpup(&((struct nvme_id_ctrl *)id)->nn);
 937
 938         cid.identify.cns = 0;
 939         memset(&crt, 0, sizeof(crt));
 940         crt.features.opcode = nvme_admin_get_features;
 941         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
 942         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
 943
 944         for (i = 0; i < nn; i++) {
 945                 cid.identify.nsid = cpu_to_le32(i);
 946                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
 947                 if (res)
 948                         continue;
 949
 950                 if (((struct nvme_id_ns *)id)->ncap == 0)
 951                         continue;
 952
 953                 crt.features.nsid = cpu_to_le32(i);
 954                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
 955                 if (res)
 956                         continue;
 957
 958                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
 959                 if (ns)
 960                         list_add_tail(&ns->list, &dev->namespaces);
 961         }
 962         list_for_each_entry(ns, &dev->namespaces, list)
 963                 add_disk(ns->disk);
 964
 965         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
 966         return 0;
 967
 968  out_free:
 969         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
 970                 list_del(&ns->list);
 971                 nvme_ns_free(ns);
 972         }
 973
 974         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
 975         return res;
 976 }
 977
 978 static int nvme_dev_remove(struct nvme_dev *dev)
 979 {
 980         struct nvme_ns *ns, *next;
 981
 982         /* TODO: wait all I/O finished or cancel them */
 983
 984         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
 985                 list_del(&ns->list);
 986                 del_gendisk(ns->disk);
 987                 nvme_ns_free(ns);
 988         }
 989
 990         nvme_free_queues(dev);
 991
 992         return 0;
 993 }
 994
 995 /* XXX: Use an ida or something to let remove / add work correctly */
 996 static void nvme_set_instance(struct nvme_dev *dev)
 997 {
 998         static int instance;
 999         dev->instance = instance++;
1000 }
1001
1002 static void nvme_release_instance(struct nvme_dev *dev)
1003 {
1004 }
1005
1006 static int __devinit nvme_probe(struct pci_dev *pdev,
1007                                                 const struct pci_device_id *id)
1008 {
1009         int result = -ENOMEM;
1010         struct nvme_dev *dev;
1011
1012         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1013         if (!dev)
1014                 return -ENOMEM;
1015         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1016                                                                 GFP_KERNEL);
1017         if (!dev->entry)
1018                 goto free;
1019         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1020                                                                 GFP_KERNEL);
1021         if (!dev->queues)
1022                 goto free;
1023
1024         INIT_LIST_HEAD(&dev->namespaces);
1025         dev->pci_dev = pdev;
1026         pci_set_drvdata(pdev, dev);
1027         dma_set_mask(&dev->pci_dev->dev, DMA_BIT_MASK(64));
1028         nvme_set_instance(dev);
1029         dev->entry[0].vector = pdev->irq;
1030
1031         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1032         if (!dev->bar) {
1033                 result = -ENOMEM;
1034                 goto disable;
1035         }
1036
1037         result = nvme_configure_admin_queue(dev);
1038         if (result)
1039                 goto unmap;
1040         dev->queue_count++;
1041
1042         result = nvme_dev_add(dev);
1043         if (result)
1044                 goto delete;
1045         return 0;
1046
1047  delete:
1048         nvme_free_queues(dev);
1049  unmap:
1050         iounmap(dev->bar);
1051  disable:
1052         pci_disable_msix(pdev);
1053         nvme_release_instance(dev);
1054  free:
1055         kfree(dev->queues);
1056         kfree(dev->entry);
1057         kfree(dev);
1058         return result;
1059 }
1060
1061 static void __devexit nvme_remove(struct pci_dev *pdev)
1062 {
1063         struct nvme_dev *dev = pci_get_drvdata(pdev);
1064         nvme_dev_remove(dev);
1065         pci_disable_msix(pdev);
1066         iounmap(dev->bar);
1067         nvme_release_instance(dev);
1068         kfree(dev->queues);
1069         kfree(dev->entry);
1070         kfree(dev);
1071 }
1072
1073 /* These functions are yet to be implemented */
1074 #define nvme_error_detected NULL
1075 #define nvme_dump_registers NULL
1076 #define nvme_link_reset NULL
1077 #define nvme_slot_reset NULL
1078 #define nvme_error_resume NULL
1079 #define nvme_suspend NULL
1080 #define nvme_resume NULL
1081
1082 static struct pci_error_handlers nvme_err_handler = {
1083         .error_detected = nvme_error_detected,
1084         .mmio_enabled   = nvme_dump_registers,
1085         .link_reset     = nvme_link_reset,
1086         .slot_reset     = nvme_slot_reset,
1087         .resume         = nvme_error_resume,
1088 };
1089
1090 /* Move to pci_ids.h later */
1091 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1092
1093 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1094         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1095         { 0, }
1096 };
1097 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1098
1099 static struct pci_driver nvme_driver = {
1100         .name           = "nvme",
1101         .id_table       = nvme_id_table,
1102         .probe          = nvme_probe,
1103         .remove         = __devexit_p(nvme_remove),
1104         .suspend        = nvme_suspend,
1105         .resume         = nvme_resume,
1106         .err_handler    = &nvme_err_handler,
1107 };
1108
1109 static int __init nvme_init(void)
1110 {
1111         int result;
1112
1113         nvme_major = register_blkdev(nvme_major, "nvme");
1114         if (nvme_major <= 0)
1115                 return -EBUSY;
1116
1117         result = pci_register_driver(&nvme_driver);
1118         if (!result)
1119                 return 0;
1120
1121         unregister_blkdev(nvme_major, "nvme");
1122         return result;
1123 }
1124
1125 static void __exit nvme_exit(void)
1126 {
1127         pci_unregister_driver(&nvme_driver);
1128         unregister_blkdev(nvme_major, "nvme");
1129 }
1130
1131 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1132 MODULE_LICENSE("GPL");
1133 MODULE_VERSION("0.1");
1134 module_init(nvme_init);
1135 module_exit(nvme_exit);