drivers/block/nvme-core.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/nvme.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <linux/fs.h>
  23 #include <linux/genhd.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/idr.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kdev_t.h>
  30 #include <linux/kthread.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/pci.h>
  36 #include <linux/poison.h>
  37 #include <linux/ptrace.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/t10-pi.h>
  41 #include <linux/types.h>
  42 #include <scsi/sg.h>
  43 #include <asm-generic/io-64-nonatomic-lo-hi.h>
  44
  45 #define NVME_MINORS             (1U << MINORBITS)
  46 #define NVME_Q_DEPTH            1024
  47 #define NVME_AQ_DEPTH           64
  48 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  49 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  50 #define ADMIN_TIMEOUT           (admin_timeout * HZ)
  51 #define SHUTDOWN_TIMEOUT        (shutdown_timeout * HZ)
  52
  53 static unsigned char admin_timeout = 60;
  54 module_param(admin_timeout, byte, 0644);
  55 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
  56
  57 unsigned char nvme_io_timeout = 30;
  58 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
  59 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
  60
  61 static unsigned char shutdown_timeout = 5;
  62 module_param(shutdown_timeout, byte, 0644);
  63 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
  64
  65 static int nvme_major;
  66 module_param(nvme_major, int, 0);
  67
  68 static int nvme_char_major;
  69 module_param(nvme_char_major, int, 0);
  70
  71 static int use_threaded_interrupts;
  72 module_param(use_threaded_interrupts, int, 0);
  73
  74 static DEFINE_SPINLOCK(dev_list_lock);
  75 static LIST_HEAD(dev_list);
  76 static struct task_struct *nvme_thread;
  77 static struct workqueue_struct *nvme_workq;
  78 static wait_queue_head_t nvme_kthread_wait;
  79
  80 static struct class *nvme_class;
  81
  82 static void nvme_reset_failed_dev(struct work_struct *ws);
  83 static int nvme_process_cq(struct nvme_queue *nvmeq);
  84
  85 struct async_cmd_info {
  86         struct kthread_work work;
  87         struct kthread_worker *worker;
  88         struct request *req;
  89         u32 result;
  90         int status;
  91         void *ctx;
  92 };
  93
  94 /*
  95  * An NVM Express queue.  Each device has at least two (one for admin
  96  * commands and one for I/O commands).
  97  */
  98 struct nvme_queue {
  99         struct device *q_dmadev;
 100         struct nvme_dev *dev;
 101         char irqname[24];       /* nvme4294967295-65535\0 */
 102         spinlock_t q_lock;
 103         struct nvme_command *sq_cmds;
 104         volatile struct nvme_completion *cqes;
 105         dma_addr_t sq_dma_addr;
 106         dma_addr_t cq_dma_addr;
 107         u32 __iomem *q_db;
 108         u16 q_depth;
 109         s16 cq_vector;
 110         u16 sq_head;
 111         u16 sq_tail;
 112         u16 cq_head;
 113         u16 qid;
 114         u8 cq_phase;
 115         u8 cqe_seen;
 116         struct async_cmd_info cmdinfo;
 117         struct blk_mq_hw_ctx *hctx;
 118 };
 119
 120 /*
 121  * Check we didin't inadvertently grow the command struct
 122  */
 123 static inline void _nvme_check_size(void)
 124 {
 125         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 126         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 127         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 128         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 129         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 130         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 131         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 132         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 133         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 134         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 135         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 136         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 137 }
 138
 139 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
 140                                                 struct nvme_completion *);
 141
 142 struct nvme_cmd_info {
 143         nvme_completion_fn fn;
 144         void *ctx;
 145         int aborted;
 146         struct nvme_queue *nvmeq;
 147         struct nvme_iod iod[0];
 148 };
 149
 150 /*
 151  * Max size of iod being embedded in the request payload
 152  */
 153 #define NVME_INT_PAGES          2
 154 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->page_size)
 155 #define NVME_INT_MASK           0x01
 156
 157 /*
 158  * Will slightly overestimate the number of pages needed.  This is OK
 159  * as it only leads to a small amount of wasted memory for the lifetime of
 160  * the I/O.
 161  */
 162 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 163 {
 164         unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
 165         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 166 }
 167
 168 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 169 {
 170         unsigned int ret = sizeof(struct nvme_cmd_info);
 171
 172         ret += sizeof(struct nvme_iod);
 173         ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
 174         ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
 175
 176         return ret;
 177 }
 178
 179 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 180                                 unsigned int hctx_idx)
 181 {
 182         struct nvme_dev *dev = data;
 183         struct nvme_queue *nvmeq = dev->queues[0];
 184
 185         WARN_ON(nvmeq->hctx);
 186         nvmeq->hctx = hctx;
 187         hctx->driver_data = nvmeq;
 188         return 0;
 189 }
 190
 191 static int nvme_admin_init_request(void *data, struct request *req,
 192                                 unsigned int hctx_idx, unsigned int rq_idx,
 193                                 unsigned int numa_node)
 194 {
 195         struct nvme_dev *dev = data;
 196         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 197         struct nvme_queue *nvmeq = dev->queues[0];
 198
 199         BUG_ON(!nvmeq);
 200         cmd->nvmeq = nvmeq;
 201         return 0;
 202 }
 203
 204 static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 205 {
 206         struct nvme_queue *nvmeq = hctx->driver_data;
 207
 208         nvmeq->hctx = NULL;
 209 }
 210
 211 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 212                           unsigned int hctx_idx)
 213 {
 214         struct nvme_dev *dev = data;
 215         struct nvme_queue *nvmeq = dev->queues[
 216                                         (hctx_idx % dev->queue_count) + 1];
 217
 218         if (!nvmeq->hctx)
 219                 nvmeq->hctx = hctx;
 220
 221         /* nvmeq queues are shared between namespaces. We assume here that
 222          * blk-mq map the tags so they match up with the nvme queue tags. */
 223         WARN_ON(nvmeq->hctx->tags != hctx->tags);
 224
 225         hctx->driver_data = nvmeq;
 226         return 0;
 227 }
 228
 229 static int nvme_init_request(void *data, struct request *req,
 230                                 unsigned int hctx_idx, unsigned int rq_idx,
 231                                 unsigned int numa_node)
 232 {
 233         struct nvme_dev *dev = data;
 234         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 235         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 236
 237         BUG_ON(!nvmeq);
 238         cmd->nvmeq = nvmeq;
 239         return 0;
 240 }
 241
 242 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
 243                                 nvme_completion_fn handler)
 244 {
 245         cmd->fn = handler;
 246         cmd->ctx = ctx;
 247         cmd->aborted = 0;
 248         blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
 249 }
 250
 251 static void *iod_get_private(struct nvme_iod *iod)
 252 {
 253         return (void *) (iod->private & ~0x1UL);
 254 }
 255
 256 /*
 257  * If bit 0 is set, the iod is embedded in the request payload.
 258  */
 259 static bool iod_should_kfree(struct nvme_iod *iod)
 260 {
 261         return (iod->private & NVME_INT_MASK) == 0;
 262 }
 263
 264 /* Special values must be less than 0x1000 */
 265 #define CMD_CTX_BASE            ((void *)POISON_POINTER_DELTA)
 266 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 267 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 268 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 269
 270 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
 271                                                 struct nvme_completion *cqe)
 272 {
 273         if (ctx == CMD_CTX_CANCELLED)
 274                 return;
 275         if (ctx == CMD_CTX_COMPLETED) {
 276                 dev_warn(nvmeq->q_dmadev,
 277                                 "completed id %d twice on queue %d\n",
 278                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 279                 return;
 280         }
 281         if (ctx == CMD_CTX_INVALID) {
 282                 dev_warn(nvmeq->q_dmadev,
 283                                 "invalid id %d completed on queue %d\n",
 284                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 285                 return;
 286         }
 287         dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
 288 }
 289
 290 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
 291 {
 292         void *ctx;
 293
 294         if (fn)
 295                 *fn = cmd->fn;
 296         ctx = cmd->ctx;
 297         cmd->fn = special_completion;
 298         cmd->ctx = CMD_CTX_CANCELLED;
 299         return ctx;
 300 }
 301
 302 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
 303                                                 struct nvme_completion *cqe)
 304 {
 305         struct request *req = ctx;
 306
 307         u32 result = le32_to_cpup(&cqe->result);
 308         u16 status = le16_to_cpup(&cqe->status) >> 1;
 309
 310         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
 311                 ++nvmeq->dev->event_limit;
 312         if (status == NVME_SC_SUCCESS)
 313                 dev_warn(nvmeq->q_dmadev,
 314                         "async event result %08x\n", result);
 315
 316         blk_mq_free_hctx_request(nvmeq->hctx, req);
 317 }
 318
 319 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
 320                                                 struct nvme_completion *cqe)
 321 {
 322         struct request *req = ctx;
 323
 324         u16 status = le16_to_cpup(&cqe->status) >> 1;
 325         u32 result = le32_to_cpup(&cqe->result);
 326
 327         blk_mq_free_hctx_request(nvmeq->hctx, req);
 328
 329         dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
 330         ++nvmeq->dev->abort_limit;
 331 }
 332
 333 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
 334                                                 struct nvme_completion *cqe)
 335 {
 336         struct async_cmd_info *cmdinfo = ctx;
 337         cmdinfo->result = le32_to_cpup(&cqe->result);
 338         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 339         queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
 340         blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
 341 }
 342
 343 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
 344                                   unsigned int tag)
 345 {
 346         struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
 347         struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
 348
 349         return blk_mq_rq_to_pdu(req);
 350 }
 351
 352 /*
 353  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 354  */
 355 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
 356                                                 nvme_completion_fn *fn)
 357 {
 358         struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
 359         void *ctx;
 360         if (tag >= nvmeq->q_depth) {
 361                 *fn = special_completion;
 362                 return CMD_CTX_INVALID;
 363         }
 364         if (fn)
 365                 *fn = cmd->fn;
 366         ctx = cmd->ctx;
 367         cmd->fn = special_completion;
 368         cmd->ctx = CMD_CTX_COMPLETED;
 369         return ctx;
 370 }
 371
 372 /**
 373  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 374  * @nvmeq: The queue to use
 375  * @cmd: The command to send
 376  *
 377  * Safe to use from interrupt context
 378  */
 379 static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 380 {
 381         u16 tail = nvmeq->sq_tail;
 382
 383         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 384         if (++tail == nvmeq->q_depth)
 385                 tail = 0;
 386         writel(tail, nvmeq->q_db);
 387         nvmeq->sq_tail = tail;
 388
 389         return 0;
 390 }
 391
 392 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 393 {
 394         unsigned long flags;
 395         int ret;
 396         spin_lock_irqsave(&nvmeq->q_lock, flags);
 397         ret = __nvme_submit_cmd(nvmeq, cmd);
 398         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 399         return ret;
 400 }
 401
 402 static __le64 **iod_list(struct nvme_iod *iod)
 403 {
 404         return ((void *)iod) + iod->offset;
 405 }
 406
 407 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
 408                             unsigned nseg, unsigned long private)
 409 {
 410         iod->private = private;
 411         iod->offset = offsetof(struct nvme_iod, sg[nseg]);
 412         iod->npages = -1;
 413         iod->length = nbytes;
 414         iod->nents = 0;
 415 }
 416
 417 static struct nvme_iod *
 418 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
 419                  unsigned long priv, gfp_t gfp)
 420 {
 421         struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
 422                                 sizeof(__le64 *) * nvme_npages(bytes, dev) +
 423                                 sizeof(struct scatterlist) * nseg, gfp);
 424
 425         if (iod)
 426                 iod_init(iod, bytes, nseg, priv);
 427
 428         return iod;
 429 }
 430
 431 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
 432                                        gfp_t gfp)
 433 {
 434         unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
 435                                                 sizeof(struct nvme_dsm_range);
 436         struct nvme_iod *iod;
 437
 438         if (rq->nr_phys_segments <= NVME_INT_PAGES &&
 439             size <= NVME_INT_BYTES(dev)) {
 440                 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
 441
 442                 iod = cmd->iod;
 443                 iod_init(iod, size, rq->nr_phys_segments,
 444                                 (unsigned long) rq | NVME_INT_MASK);
 445                 return iod;
 446         }
 447
 448         return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
 449                                 (unsigned long) rq, gfp);
 450 }
 451
 452 void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
 453 {
 454         const int last_prp = dev->page_size / 8 - 1;
 455         int i;
 456         __le64 **list = iod_list(iod);
 457         dma_addr_t prp_dma = iod->first_dma;
 458
 459         if (iod->npages == 0)
 460                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 461         for (i = 0; i < iod->npages; i++) {
 462                 __le64 *prp_list = list[i];
 463                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 464                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 465                 prp_dma = next_prp_dma;
 466         }
 467
 468         if (iod_should_kfree(iod))
 469                 kfree(iod);
 470 }
 471
 472 static int nvme_error_status(u16 status)
 473 {
 474         switch (status & 0x7ff) {
 475         case NVME_SC_SUCCESS:
 476                 return 0;
 477         case NVME_SC_CAP_EXCEEDED:
 478                 return -ENOSPC;
 479         default:
 480                 return -EIO;
 481         }
 482 }
 483
 484 #ifdef CONFIG_BLK_DEV_INTEGRITY
 485 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 486 {
 487         if (be32_to_cpu(pi->ref_tag) == v)
 488                 pi->ref_tag = cpu_to_be32(p);
 489 }
 490
 491 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 492 {
 493         if (be32_to_cpu(pi->ref_tag) == p)
 494                 pi->ref_tag = cpu_to_be32(v);
 495 }
 496
 497 /**
 498  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 499  *
 500  * The virtual start sector is the one that was originally submitted by the
 501  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 502  * start sector may be different. Remap protection information to match the
 503  * physical LBA on writes, and back to the original seed on reads.
 504  *
 505  * Type 0 and 3 do not have a ref tag, so no remapping required.
 506  */
 507 static void nvme_dif_remap(struct request *req,
 508                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 509 {
 510         struct nvme_ns *ns = req->rq_disk->private_data;
 511         struct bio_integrity_payload *bip;
 512         struct t10_pi_tuple *pi;
 513         void *p, *pmap;
 514         u32 i, nlb, ts, phys, virt;
 515
 516         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 517                 return;
 518
 519         bip = bio_integrity(req->bio);
 520         if (!bip)
 521                 return;
 522
 523         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 524         if (!pmap)
 525                 return;
 526
 527         p = pmap;
 528         virt = bip_get_seed(bip);
 529         phys = nvme_block_nr(ns, blk_rq_pos(req));
 530         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 531         ts = ns->disk->integrity->tuple_size;
 532
 533         for (i = 0; i < nlb; i++, virt++, phys++) {
 534                 pi = (struct t10_pi_tuple *)p;
 535                 dif_swap(phys, virt, pi);
 536                 p += ts;
 537         }
 538         kunmap_atomic(pmap);
 539 }
 540
 541 static int nvme_noop_verify(struct blk_integrity_iter *iter)
 542 {
 543         return 0;
 544 }
 545
 546 static int nvme_noop_generate(struct blk_integrity_iter *iter)
 547 {
 548         return 0;
 549 }
 550
 551 struct blk_integrity nvme_meta_noop = {
 552         .name                   = "NVME_META_NOOP",
 553         .generate_fn            = nvme_noop_generate,
 554         .verify_fn              = nvme_noop_verify,
 555 };
 556
 557 static void nvme_init_integrity(struct nvme_ns *ns)
 558 {
 559         struct blk_integrity integrity;
 560
 561         switch (ns->pi_type) {
 562         case NVME_NS_DPS_PI_TYPE3:
 563                 integrity = t10_pi_type3_crc;
 564                 break;
 565         case NVME_NS_DPS_PI_TYPE1:
 566         case NVME_NS_DPS_PI_TYPE2:
 567                 integrity = t10_pi_type1_crc;
 568                 break;
 569         default:
 570                 integrity = nvme_meta_noop;
 571                 break;
 572         }
 573         integrity.tuple_size = ns->ms;
 574         blk_integrity_register(ns->disk, &integrity);
 575         blk_queue_max_integrity_segments(ns->queue, 1);
 576 }
 577 #else /* CONFIG_BLK_DEV_INTEGRITY */
 578 static void nvme_dif_remap(struct request *req,
 579                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 580 {
 581 }
 582 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 583 {
 584 }
 585 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 586 {
 587 }
 588 static void nvme_init_integrity(struct nvme_ns *ns)
 589 {
 590 }
 591 #endif
 592
 593 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
 594                                                 struct nvme_completion *cqe)
 595 {
 596         struct nvme_iod *iod = ctx;
 597         struct request *req = iod_get_private(iod);
 598         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
 599
 600         u16 status = le16_to_cpup(&cqe->status) >> 1;
 601
 602         if (unlikely(status)) {
 603                 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
 604                     && (jiffies - req->start_time) < req->timeout) {
 605                         unsigned long flags;
 606
 607                         blk_mq_requeue_request(req);
 608                         spin_lock_irqsave(req->q->queue_lock, flags);
 609                         if (!blk_queue_stopped(req->q))
 610                                 blk_mq_kick_requeue_list(req->q);
 611                         spin_unlock_irqrestore(req->q->queue_lock, flags);
 612                         return;
 613                 }
 614                 req->errors = nvme_error_status(status);
 615         } else
 616                 req->errors = 0;
 617
 618         if (cmd_rq->aborted)
 619                 dev_warn(&nvmeq->dev->pci_dev->dev,
 620                         "completing aborted command with status:%04x\n",
 621                         status);
 622
 623         if (iod->nents) {
 624                 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
 625                         rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 626                 if (blk_integrity_rq(req)) {
 627                         if (!rq_data_dir(req))
 628                                 nvme_dif_remap(req, nvme_dif_complete);
 629                         dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->meta_sg, 1,
 630                                 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 631                 }
 632         }
 633         nvme_free_iod(nvmeq->dev, iod);
 634
 635         blk_mq_complete_request(req);
 636 }
 637
 638 /* length is in bytes.  gfp flags indicates whether we may sleep. */
 639 int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
 640                                                                 gfp_t gfp)
 641 {
 642         struct dma_pool *pool;
 643         int length = total_len;
 644         struct scatterlist *sg = iod->sg;
 645         int dma_len = sg_dma_len(sg);
 646         u64 dma_addr = sg_dma_address(sg);
 647         int offset = offset_in_page(dma_addr);
 648         __le64 *prp_list;
 649         __le64 **list = iod_list(iod);
 650         dma_addr_t prp_dma;
 651         int nprps, i;
 652         u32 page_size = dev->page_size;
 653
 654         length -= (page_size - offset);
 655         if (length <= 0)
 656                 return total_len;
 657
 658         dma_len -= (page_size - offset);
 659         if (dma_len) {
 660                 dma_addr += (page_size - offset);
 661         } else {
 662                 sg = sg_next(sg);
 663                 dma_addr = sg_dma_address(sg);
 664                 dma_len = sg_dma_len(sg);
 665         }
 666
 667         if (length <= page_size) {
 668                 iod->first_dma = dma_addr;
 669                 return total_len;
 670         }
 671
 672         nprps = DIV_ROUND_UP(length, page_size);
 673         if (nprps <= (256 / 8)) {
 674                 pool = dev->prp_small_pool;
 675                 iod->npages = 0;
 676         } else {
 677                 pool = dev->prp_page_pool;
 678                 iod->npages = 1;
 679         }
 680
 681         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 682         if (!prp_list) {
 683                 iod->first_dma = dma_addr;
 684                 iod->npages = -1;
 685                 return (total_len - length) + page_size;
 686         }
 687         list[0] = prp_list;
 688         iod->first_dma = prp_dma;
 689         i = 0;
 690         for (;;) {
 691                 if (i == page_size >> 3) {
 692                         __le64 *old_prp_list = prp_list;
 693                         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 694                         if (!prp_list)
 695                                 return total_len - length;
 696                         list[iod->npages++] = prp_list;
 697                         prp_list[0] = old_prp_list[i - 1];
 698                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 699                         i = 1;
 700                 }
 701                 prp_list[i++] = cpu_to_le64(dma_addr);
 702                 dma_len -= page_size;
 703                 dma_addr += page_size;
 704                 length -= page_size;
 705                 if (length <= 0)
 706                         break;
 707                 if (dma_len > 0)
 708                         continue;
 709                 BUG_ON(dma_len < 0);
 710                 sg = sg_next(sg);
 711                 dma_addr = sg_dma_address(sg);
 712                 dma_len = sg_dma_len(sg);
 713         }
 714
 715         return total_len;
 716 }
 717
 718 /*
 719  * We reuse the small pool to allocate the 16-byte range here as it is not
 720  * worth having a special pool for these or additional cases to handle freeing
 721  * the iod.
 722  */
 723 static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 724                 struct request *req, struct nvme_iod *iod)
 725 {
 726         struct nvme_dsm_range *range =
 727                                 (struct nvme_dsm_range *)iod_list(iod)[0];
 728         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 729
 730         range->cattr = cpu_to_le32(0);
 731         range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
 732         range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
 733
 734         memset(cmnd, 0, sizeof(*cmnd));
 735         cmnd->dsm.opcode = nvme_cmd_dsm;
 736         cmnd->dsm.command_id = req->tag;
 737         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
 738         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
 739         cmnd->dsm.nr = 0;
 740         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
 741
 742         if (++nvmeq->sq_tail == nvmeq->q_depth)
 743                 nvmeq->sq_tail = 0;
 744         writel(nvmeq->sq_tail, nvmeq->q_db);
 745 }
 746
 747 static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 748                                                                 int cmdid)
 749 {
 750         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 751
 752         memset(cmnd, 0, sizeof(*cmnd));
 753         cmnd->common.opcode = nvme_cmd_flush;
 754         cmnd->common.command_id = cmdid;
 755         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
 756
 757         if (++nvmeq->sq_tail == nvmeq->q_depth)
 758                 nvmeq->sq_tail = 0;
 759         writel(nvmeq->sq_tail, nvmeq->q_db);
 760 }
 761
 762 static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
 763                                                         struct nvme_ns *ns)
 764 {
 765         struct request *req = iod_get_private(iod);
 766         struct nvme_command *cmnd;
 767         u16 control = 0;
 768         u32 dsmgmt = 0;
 769
 770         if (req->cmd_flags & REQ_FUA)
 771                 control |= NVME_RW_FUA;
 772         if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 773                 control |= NVME_RW_LR;
 774
 775         if (req->cmd_flags & REQ_RAHEAD)
 776                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 777
 778         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 779         memset(cmnd, 0, sizeof(*cmnd));
 780
 781         cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
 782         cmnd->rw.command_id = req->tag;
 783         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 784         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 785         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 786         cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
 787         cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
 788
 789         if (blk_integrity_rq(req)) {
 790                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
 791                 switch (ns->pi_type) {
 792                 case NVME_NS_DPS_PI_TYPE3:
 793                         control |= NVME_RW_PRINFO_PRCHK_GUARD;
 794                         break;
 795                 case NVME_NS_DPS_PI_TYPE1:
 796                 case NVME_NS_DPS_PI_TYPE2:
 797                         control |= NVME_RW_PRINFO_PRCHK_GUARD |
 798                                         NVME_RW_PRINFO_PRCHK_REF;
 799                         cmnd->rw.reftag = cpu_to_le32(
 800                                         nvme_block_nr(ns, blk_rq_pos(req)));
 801                         break;
 802                 }
 803         } else if (ns->ms)
 804                 control |= NVME_RW_PRINFO_PRACT;
 805
 806         cmnd->rw.control = cpu_to_le16(control);
 807         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 808
 809         if (++nvmeq->sq_tail == nvmeq->q_depth)
 810                 nvmeq->sq_tail = 0;
 811         writel(nvmeq->sq_tail, nvmeq->q_db);
 812
 813         return 0;
 814 }
 815
 816 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 817                          const struct blk_mq_queue_data *bd)
 818 {
 819         struct nvme_ns *ns = hctx->queue->queuedata;
 820         struct nvme_queue *nvmeq = hctx->driver_data;
 821         struct request *req = bd->rq;
 822         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 823         struct nvme_iod *iod;
 824         enum dma_data_direction dma_dir;
 825
 826         /*
 827          * If formated with metadata, require the block layer provide a buffer
 828          * unless this namespace is formated such that the metadata can be
 829          * stripped/generated by the controller with PRACT=1.
 830          */
 831         if (ns->ms && !blk_integrity_rq(req)) {
 832                 if (!(ns->pi_type && ns->ms == 8)) {
 833                         req->errors = -EFAULT;
 834                         blk_mq_complete_request(req);
 835                         return BLK_MQ_RQ_QUEUE_OK;
 836                 }
 837         }
 838
 839         iod = nvme_alloc_iod(req, ns->dev, GFP_ATOMIC);
 840         if (!iod)
 841                 return BLK_MQ_RQ_QUEUE_BUSY;
 842
 843         if (req->cmd_flags & REQ_DISCARD) {
 844                 void *range;
 845                 /*
 846                  * We reuse the small pool to allocate the 16-byte range here
 847                  * as it is not worth having a special pool for these or
 848                  * additional cases to handle freeing the iod.
 849                  */
 850                 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
 851                                                 GFP_ATOMIC,
 852                                                 &iod->first_dma);
 853                 if (!range)
 854                         goto retry_cmd;
 855                 iod_list(iod)[0] = (__le64 *)range;
 856                 iod->npages = 0;
 857         } else if (req->nr_phys_segments) {
 858                 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
 859
 860                 sg_init_table(iod->sg, req->nr_phys_segments);
 861                 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
 862                 if (!iod->nents)
 863                         goto error_cmd;
 864
 865                 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
 866                         goto retry_cmd;
 867
 868                 if (blk_rq_bytes(req) !=
 869                     nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
 870                         dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
 871                                         iod->nents, dma_dir);
 872                         goto retry_cmd;
 873                 }
 874                 if (blk_integrity_rq(req)) {
 875                         if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
 876                                 goto error_cmd;
 877
 878                         sg_init_table(iod->meta_sg, 1);
 879                         if (blk_rq_map_integrity_sg(
 880                                         req->q, req->bio, iod->meta_sg) != 1)
 881                                 goto error_cmd;
 882
 883                         if (rq_data_dir(req))
 884                                 nvme_dif_remap(req, nvme_dif_prep);
 885
 886                         if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
 887                                 goto error_cmd;
 888                 }
 889         }
 890
 891         nvme_set_info(cmd, iod, req_completion);
 892         spin_lock_irq(&nvmeq->q_lock);
 893         if (req->cmd_flags & REQ_DISCARD)
 894                 nvme_submit_discard(nvmeq, ns, req, iod);
 895         else if (req->cmd_flags & REQ_FLUSH)
 896                 nvme_submit_flush(nvmeq, ns, req->tag);
 897         else
 898                 nvme_submit_iod(nvmeq, iod, ns);
 899
 900         nvme_process_cq(nvmeq);
 901         spin_unlock_irq(&nvmeq->q_lock);
 902         return BLK_MQ_RQ_QUEUE_OK;
 903
 904  error_cmd:
 905         nvme_free_iod(nvmeq->dev, iod);
 906         return BLK_MQ_RQ_QUEUE_ERROR;
 907  retry_cmd:
 908         nvme_free_iod(nvmeq->dev, iod);
 909         return BLK_MQ_RQ_QUEUE_BUSY;
 910 }
 911
 912 static int nvme_process_cq(struct nvme_queue *nvmeq)
 913 {
 914         u16 head, phase;
 915
 916         head = nvmeq->cq_head;
 917         phase = nvmeq->cq_phase;
 918
 919         for (;;) {
 920                 void *ctx;
 921                 nvme_completion_fn fn;
 922                 struct nvme_completion cqe = nvmeq->cqes[head];
 923                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 924                         break;
 925                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 926                 if (++head == nvmeq->q_depth) {
 927                         head = 0;
 928                         phase = !phase;
 929                 }
 930                 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
 931                 fn(nvmeq, ctx, &cqe);
 932         }
 933
 934         /* If the controller ignores the cq head doorbell and continuously
 935          * writes to the queue, it is theoretically possible to wrap around
 936          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 937          * requires that 0.1% of your interrupts are handled, so this isn't
 938          * a big problem.
 939          */
 940         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 941                 return 0;
 942
 943         writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 944         nvmeq->cq_head = head;
 945         nvmeq->cq_phase = phase;
 946
 947         nvmeq->cqe_seen = 1;
 948         return 1;
 949 }
 950
 951 /* Admin queue isn't initialized as a request queue. If at some point this
 952  * happens anyway, make sure to notify the user */
 953 static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
 954                                const struct blk_mq_queue_data *bd)
 955 {
 956         WARN_ON_ONCE(1);
 957         return BLK_MQ_RQ_QUEUE_ERROR;
 958 }
 959
 960 static irqreturn_t nvme_irq(int irq, void *data)
 961 {
 962         irqreturn_t result;
 963         struct nvme_queue *nvmeq = data;
 964         spin_lock(&nvmeq->q_lock);
 965         nvme_process_cq(nvmeq);
 966         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 967         nvmeq->cqe_seen = 0;
 968         spin_unlock(&nvmeq->q_lock);
 969         return result;
 970 }
 971
 972 static irqreturn_t nvme_irq_check(int irq, void *data)
 973 {
 974         struct nvme_queue *nvmeq = data;
 975         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 976         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 977                 return IRQ_NONE;
 978         return IRQ_WAKE_THREAD;
 979 }
 980
 981 struct sync_cmd_info {
 982         struct task_struct *task;
 983         u32 result;
 984         int status;
 985 };
 986
 987 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 988                                                 struct nvme_completion *cqe)
 989 {
 990         struct sync_cmd_info *cmdinfo = ctx;
 991         cmdinfo->result = le32_to_cpup(&cqe->result);
 992         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 993         wake_up_process(cmdinfo->task);
 994 }
 995
 996 /*
 997  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 998  * if the result is positive, it's an NVM Express status code
 999  */
1000 static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
1001                                                 u32 *result, unsigned timeout)
1002 {
1003         struct sync_cmd_info cmdinfo;
1004         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1005         struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1006
1007         cmdinfo.task = current;
1008         cmdinfo.status = -EINTR;
1009
1010         cmd->common.command_id = req->tag;
1011
1012         nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
1013
1014         set_current_state(TASK_UNINTERRUPTIBLE);
1015         nvme_submit_cmd(nvmeq, cmd);
1016         schedule();
1017
1018         if (result)
1019                 *result = cmdinfo.result;
1020         return cmdinfo.status;
1021 }
1022
1023 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1024 {
1025         struct nvme_queue *nvmeq = dev->queues[0];
1026         struct nvme_command c;
1027         struct nvme_cmd_info *cmd_info;
1028         struct request *req;
1029
1030         req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false);
1031         if (IS_ERR(req))
1032                 return PTR_ERR(req);
1033
1034         req->cmd_flags |= REQ_NO_TIMEOUT;
1035         cmd_info = blk_mq_rq_to_pdu(req);
1036         nvme_set_info(cmd_info, req, async_req_completion);
1037
1038         memset(&c, 0, sizeof(c));
1039         c.common.opcode = nvme_admin_async_event;
1040         c.common.command_id = req->tag;
1041
1042         return __nvme_submit_cmd(nvmeq, &c);
1043 }
1044
1045 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
1046                         struct nvme_command *cmd,
1047                         struct async_cmd_info *cmdinfo, unsigned timeout)
1048 {
1049         struct nvme_queue *nvmeq = dev->queues[0];
1050         struct request *req;
1051         struct nvme_cmd_info *cmd_rq;
1052
1053         req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
1054         if (IS_ERR(req))
1055                 return PTR_ERR(req);
1056
1057         req->timeout = timeout;
1058         cmd_rq = blk_mq_rq_to_pdu(req);
1059         cmdinfo->req = req;
1060         nvme_set_info(cmd_rq, cmdinfo, async_completion);
1061         cmdinfo->status = -EINTR;
1062
1063         cmd->common.command_id = req->tag;
1064
1065         return nvme_submit_cmd(nvmeq, cmd);
1066 }
1067
1068 static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
1069                                                 u32 *result, unsigned timeout)
1070 {
1071         int res;
1072         struct request *req;
1073
1074         req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
1075         if (IS_ERR(req))
1076                 return PTR_ERR(req);
1077         res = nvme_submit_sync_cmd(req, cmd, result, timeout);
1078         blk_mq_free_request(req);
1079         return res;
1080 }
1081
1082 int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
1083                                                                 u32 *result)
1084 {
1085         return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
1086 }
1087
1088 int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1089                                         struct nvme_command *cmd, u32 *result)
1090 {
1091         int res;
1092         struct request *req;
1093
1094         req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
1095                                                                         false);
1096         if (IS_ERR(req))
1097                 return PTR_ERR(req);
1098         res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
1099         blk_mq_free_request(req);
1100         return res;
1101 }
1102
1103 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1104 {
1105         struct nvme_command c;
1106
1107         memset(&c, 0, sizeof(c));
1108         c.delete_queue.opcode = opcode;
1109         c.delete_queue.qid = cpu_to_le16(id);
1110
1111         return nvme_submit_admin_cmd(dev, &c, NULL);
1112 }
1113
1114 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1115                                                 struct nvme_queue *nvmeq)
1116 {
1117         struct nvme_command c;
1118         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1119
1120         memset(&c, 0, sizeof(c));
1121         c.create_cq.opcode = nvme_admin_create_cq;
1122         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1123         c.create_cq.cqid = cpu_to_le16(qid);
1124         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1125         c.create_cq.cq_flags = cpu_to_le16(flags);
1126         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1127
1128         return nvme_submit_admin_cmd(dev, &c, NULL);
1129 }
1130
1131 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1132                                                 struct nvme_queue *nvmeq)
1133 {
1134         struct nvme_command c;
1135         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1136
1137         memset(&c, 0, sizeof(c));
1138         c.create_sq.opcode = nvme_admin_create_sq;
1139         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1140         c.create_sq.sqid = cpu_to_le16(qid);
1141         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1142         c.create_sq.sq_flags = cpu_to_le16(flags);
1143         c.create_sq.cqid = cpu_to_le16(qid);
1144
1145         return nvme_submit_admin_cmd(dev, &c, NULL);
1146 }
1147
1148 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1149 {
1150         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1151 }
1152
1153 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1154 {
1155         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1156 }
1157
1158 int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
1159                                                         dma_addr_t dma_addr)
1160 {
1161         struct nvme_command c;
1162
1163         memset(&c, 0, sizeof(c));
1164         c.identify.opcode = nvme_admin_identify;
1165         c.identify.nsid = cpu_to_le32(nsid);
1166         c.identify.prp1 = cpu_to_le64(dma_addr);
1167         c.identify.cns = cpu_to_le32(cns);
1168
1169         return nvme_submit_admin_cmd(dev, &c, NULL);
1170 }
1171
1172 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
1173                                         dma_addr_t dma_addr, u32 *result)
1174 {
1175         struct nvme_command c;
1176
1177         memset(&c, 0, sizeof(c));
1178         c.features.opcode = nvme_admin_get_features;
1179         c.features.nsid = cpu_to_le32(nsid);
1180         c.features.prp1 = cpu_to_le64(dma_addr);
1181         c.features.fid = cpu_to_le32(fid);
1182
1183         return nvme_submit_admin_cmd(dev, &c, result);
1184 }
1185
1186 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1187                                         dma_addr_t dma_addr, u32 *result)
1188 {
1189         struct nvme_command c;
1190
1191         memset(&c, 0, sizeof(c));
1192         c.features.opcode = nvme_admin_set_features;
1193         c.features.prp1 = cpu_to_le64(dma_addr);
1194         c.features.fid = cpu_to_le32(fid);
1195         c.features.dword11 = cpu_to_le32(dword11);
1196
1197         return nvme_submit_admin_cmd(dev, &c, result);
1198 }
1199
1200 /**
1201  * nvme_abort_req - Attempt aborting a request
1202  *
1203  * Schedule controller reset if the command was already aborted once before and
1204  * still hasn't been returned to the driver, or if this is the admin queue.
1205  */
1206 static void nvme_abort_req(struct request *req)
1207 {
1208         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1209         struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1210         struct nvme_dev *dev = nvmeq->dev;
1211         struct request *abort_req;
1212         struct nvme_cmd_info *abort_cmd;
1213         struct nvme_command cmd;
1214
1215         if (!nvmeq->qid || cmd_rq->aborted) {
1216                 unsigned long flags;
1217
1218                 spin_lock_irqsave(&dev_list_lock, flags);
1219                 if (work_busy(&dev->reset_work))
1220                         goto out;
1221                 list_del_init(&dev->node);
1222                 dev_warn(&dev->pci_dev->dev,
1223                         "I/O %d QID %d timeout, reset controller\n",
1224                                                         req->tag, nvmeq->qid);
1225                 dev->reset_workfn = nvme_reset_failed_dev;
1226                 queue_work(nvme_workq, &dev->reset_work);
1227  out:
1228                 spin_unlock_irqrestore(&dev_list_lock, flags);
1229                 return;
1230         }
1231
1232         if (!dev->abort_limit)
1233                 return;
1234
1235         abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1236                                                                         false);
1237         if (IS_ERR(abort_req))
1238                 return;
1239
1240         abort_cmd = blk_mq_rq_to_pdu(abort_req);
1241         nvme_set_info(abort_cmd, abort_req, abort_completion);
1242
1243         memset(&cmd, 0, sizeof(cmd));
1244         cmd.abort.opcode = nvme_admin_abort_cmd;
1245         cmd.abort.cid = req->tag;
1246         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1247         cmd.abort.command_id = abort_req->tag;
1248
1249         --dev->abort_limit;
1250         cmd_rq->aborted = 1;
1251
1252         dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
1253                                                         nvmeq->qid);
1254         if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1255                 dev_warn(nvmeq->q_dmadev,
1256                                 "Could not abort I/O %d QID %d",
1257                                 req->tag, nvmeq->qid);
1258                 blk_mq_free_request(abort_req);
1259         }
1260 }
1261
1262 static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1263                                 struct request *req, void *data, bool reserved)
1264 {
1265         struct nvme_queue *nvmeq = data;
1266         void *ctx;
1267         nvme_completion_fn fn;
1268         struct nvme_cmd_info *cmd;
1269         struct nvme_completion cqe;
1270
1271         if (!blk_mq_request_started(req))
1272                 return;
1273
1274         cmd = blk_mq_rq_to_pdu(req);
1275
1276         if (cmd->ctx == CMD_CTX_CANCELLED)
1277                 return;
1278
1279         if (blk_queue_dying(req->q))
1280                 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1281         else
1282                 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1283
1284
1285         dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1286                                                 req->tag, nvmeq->qid);
1287         ctx = cancel_cmd_info(cmd, &fn);
1288         fn(nvmeq, ctx, &cqe);
1289 }
1290
1291 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1292 {
1293         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1294         struct nvme_queue *nvmeq = cmd->nvmeq;
1295
1296         dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1297                                                         nvmeq->qid);
1298         spin_lock_irq(&nvmeq->q_lock);
1299         nvme_abort_req(req);
1300         spin_unlock_irq(&nvmeq->q_lock);
1301
1302         /*
1303          * The aborted req will be completed on receiving the abort req.
1304          * We enable the timer again. If hit twice, it'll cause a device reset,
1305          * as the device then is in a faulty state.
1306          */
1307         return BLK_EH_RESET_TIMER;
1308 }
1309
1310 static void nvme_free_queue(struct nvme_queue *nvmeq)
1311 {
1312         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1313                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1314         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1315                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1316         kfree(nvmeq);
1317 }
1318
1319 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1320 {
1321         int i;
1322
1323         for (i = dev->queue_count - 1; i >= lowest; i--) {
1324                 struct nvme_queue *nvmeq = dev->queues[i];
1325                 dev->queue_count--;
1326                 dev->queues[i] = NULL;
1327                 nvme_free_queue(nvmeq);
1328         }
1329 }
1330
1331 /**
1332  * nvme_suspend_queue - put queue into suspended state
1333  * @nvmeq - queue to suspend
1334  */
1335 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1336 {
1337         int vector;
1338
1339         spin_lock_irq(&nvmeq->q_lock);
1340         if (nvmeq->cq_vector == -1) {
1341                 spin_unlock_irq(&nvmeq->q_lock);
1342                 return 1;
1343         }
1344         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1345         nvmeq->dev->online_queues--;
1346         nvmeq->cq_vector = -1;
1347         spin_unlock_irq(&nvmeq->q_lock);
1348
1349         if (!nvmeq->qid && nvmeq->dev->admin_q)
1350                 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1351
1352         irq_set_affinity_hint(vector, NULL);
1353         free_irq(vector, nvmeq);
1354
1355         return 0;
1356 }
1357
1358 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1359 {
1360         struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1361
1362         spin_lock_irq(&nvmeq->q_lock);
1363         if (hctx && hctx->tags)
1364                 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
1365         spin_unlock_irq(&nvmeq->q_lock);
1366 }
1367
1368 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1369 {
1370         struct nvme_queue *nvmeq = dev->queues[qid];
1371
1372         if (!nvmeq)
1373                 return;
1374         if (nvme_suspend_queue(nvmeq))
1375                 return;
1376
1377         /* Don't tell the adapter to delete the admin queue.
1378          * Don't tell a removed adapter to delete IO queues. */
1379         if (qid && readl(&dev->bar->csts) != -1) {
1380                 adapter_delete_sq(dev, qid);
1381                 adapter_delete_cq(dev, qid);
1382         }
1383
1384         spin_lock_irq(&nvmeq->q_lock);
1385         nvme_process_cq(nvmeq);
1386         spin_unlock_irq(&nvmeq->q_lock);
1387 }
1388
1389 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1390                                                         int depth)
1391 {
1392         struct device *dmadev = &dev->pci_dev->dev;
1393         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1394         if (!nvmeq)
1395                 return NULL;
1396
1397         nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1398                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1399         if (!nvmeq->cqes)
1400                 goto free_nvmeq;
1401
1402         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1403                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1404         if (!nvmeq->sq_cmds)
1405                 goto free_cqdma;
1406
1407         nvmeq->q_dmadev = dmadev;
1408         nvmeq->dev = dev;
1409         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1410                         dev->instance, qid);
1411         spin_lock_init(&nvmeq->q_lock);
1412         nvmeq->cq_head = 0;
1413         nvmeq->cq_phase = 1;
1414         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1415         nvmeq->q_depth = depth;
1416         nvmeq->qid = qid;
1417         dev->queue_count++;
1418         dev->queues[qid] = nvmeq;
1419
1420         return nvmeq;
1421
1422  free_cqdma:
1423         dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1424                                                         nvmeq->cq_dma_addr);
1425  free_nvmeq:
1426         kfree(nvmeq);
1427         return NULL;
1428 }
1429
1430 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1431                                                         const char *name)
1432 {
1433         if (use_threaded_interrupts)
1434                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1435                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1436                                         name, nvmeq);
1437         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1438                                 IRQF_SHARED, name, nvmeq);
1439 }
1440
1441 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1442 {
1443         struct nvme_dev *dev = nvmeq->dev;
1444
1445         spin_lock_irq(&nvmeq->q_lock);
1446         nvmeq->sq_tail = 0;
1447         nvmeq->cq_head = 0;
1448         nvmeq->cq_phase = 1;
1449         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1450         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1451         dev->online_queues++;
1452         spin_unlock_irq(&nvmeq->q_lock);
1453 }
1454
1455 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1456 {
1457         struct nvme_dev *dev = nvmeq->dev;
1458         int result;
1459
1460         nvmeq->cq_vector = qid - 1;
1461         result = adapter_alloc_cq(dev, qid, nvmeq);
1462         if (result < 0)
1463                 return result;
1464
1465         result = adapter_alloc_sq(dev, qid, nvmeq);
1466         if (result < 0)
1467                 goto release_cq;
1468
1469         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1470         if (result < 0)
1471                 goto release_sq;
1472
1473         nvme_init_queue(nvmeq, qid);
1474         return result;
1475
1476  release_sq:
1477         adapter_delete_sq(dev, qid);
1478  release_cq:
1479         adapter_delete_cq(dev, qid);
1480         return result;
1481 }
1482
1483 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1484 {
1485         unsigned long timeout;
1486         u32 bit = enabled ? NVME_CSTS_RDY : 0;
1487
1488         timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1489
1490         while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1491                 msleep(100);
1492                 if (fatal_signal_pending(current))
1493                         return -EINTR;
1494                 if (time_after(jiffies, timeout)) {
1495                         dev_err(&dev->pci_dev->dev,
1496                                 "Device not ready; aborting %s\n", enabled ?
1497                                                 "initialisation" : "reset");
1498                         return -ENODEV;
1499                 }
1500         }
1501
1502         return 0;
1503 }
1504
1505 /*
1506  * If the device has been passed off to us in an enabled state, just clear
1507  * the enabled bit.  The spec says we should set the 'shutdown notification
1508  * bits', but doing so may cause the device to complete commands to the
1509  * admin queue ... and we don't know what memory that might be pointing at!
1510  */
1511 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1512 {
1513         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1514         dev->ctrl_config &= ~NVME_CC_ENABLE;
1515         writel(dev->ctrl_config, &dev->bar->cc);
1516
1517         return nvme_wait_ready(dev, cap, false);
1518 }
1519
1520 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1521 {
1522         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1523         dev->ctrl_config |= NVME_CC_ENABLE;
1524         writel(dev->ctrl_config, &dev->bar->cc);
1525
1526         return nvme_wait_ready(dev, cap, true);
1527 }
1528
1529 static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1530 {
1531         unsigned long timeout;
1532
1533         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1534         dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1535
1536         writel(dev->ctrl_config, &dev->bar->cc);
1537
1538         timeout = SHUTDOWN_TIMEOUT + jiffies;
1539         while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1540                                                         NVME_CSTS_SHST_CMPLT) {
1541                 msleep(100);
1542                 if (fatal_signal_pending(current))
1543                         return -EINTR;
1544                 if (time_after(jiffies, timeout)) {
1545                         dev_err(&dev->pci_dev->dev,
1546                                 "Device shutdown incomplete; abort shutdown\n");
1547                         return -ENODEV;
1548                 }
1549         }
1550
1551         return 0;
1552 }
1553
1554 static struct blk_mq_ops nvme_mq_admin_ops = {
1555         .queue_rq       = nvme_admin_queue_rq,
1556         .map_queue      = blk_mq_map_queue,
1557         .init_hctx      = nvme_admin_init_hctx,
1558         .exit_hctx      = nvme_exit_hctx,
1559         .init_request   = nvme_admin_init_request,
1560         .timeout        = nvme_timeout,
1561 };
1562
1563 static struct blk_mq_ops nvme_mq_ops = {
1564         .queue_rq       = nvme_queue_rq,
1565         .map_queue      = blk_mq_map_queue,
1566         .init_hctx      = nvme_init_hctx,
1567         .exit_hctx      = nvme_exit_hctx,
1568         .init_request   = nvme_init_request,
1569         .timeout        = nvme_timeout,
1570 };
1571
1572 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1573 {
1574         if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1575                 blk_cleanup_queue(dev->admin_q);
1576                 blk_mq_free_tag_set(&dev->admin_tagset);
1577         }
1578 }
1579
1580 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1581 {
1582         if (!dev->admin_q) {
1583                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1584                 dev->admin_tagset.nr_hw_queues = 1;
1585                 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1586                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1587                 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
1588                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1589                 dev->admin_tagset.driver_data = dev;
1590
1591                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1592                         return -ENOMEM;
1593
1594                 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1595                 if (IS_ERR(dev->admin_q)) {
1596                         blk_mq_free_tag_set(&dev->admin_tagset);
1597                         return -ENOMEM;
1598                 }
1599                 if (!blk_get_queue(dev->admin_q)) {
1600                         nvme_dev_remove_admin(dev);
1601                         return -ENODEV;
1602                 }
1603         } else
1604                 blk_mq_unfreeze_queue(dev->admin_q);
1605
1606         return 0;
1607 }
1608
1609 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1610 {
1611         int result;
1612         u32 aqa;
1613         u64 cap = readq(&dev->bar->cap);
1614         struct nvme_queue *nvmeq;
1615         unsigned page_shift = PAGE_SHIFT;
1616         unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1617         unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1618
1619         if (page_shift < dev_page_min) {
1620                 dev_err(&dev->pci_dev->dev,
1621                                 "Minimum device page size (%u) too large for "
1622                                 "host (%u)\n", 1 << dev_page_min,
1623                                 1 << page_shift);
1624                 return -ENODEV;
1625         }
1626         if (page_shift > dev_page_max) {
1627                 dev_info(&dev->pci_dev->dev,
1628                                 "Device maximum page size (%u) smaller than "
1629                                 "host (%u); enabling work-around\n",
1630                                 1 << dev_page_max, 1 << page_shift);
1631                 page_shift = dev_page_max;
1632         }
1633
1634         result = nvme_disable_ctrl(dev, cap);
1635         if (result < 0)
1636                 return result;
1637
1638         nvmeq = dev->queues[0];
1639         if (!nvmeq) {
1640                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1641                 if (!nvmeq)
1642                         return -ENOMEM;
1643         }
1644
1645         aqa = nvmeq->q_depth - 1;
1646         aqa |= aqa << 16;
1647
1648         dev->page_size = 1 << page_shift;
1649
1650         dev->ctrl_config = NVME_CC_CSS_NVM;
1651         dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1652         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1653         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1654
1655         writel(aqa, &dev->bar->aqa);
1656         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1657         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1658
1659         result = nvme_enable_ctrl(dev, cap);
1660         if (result)
1661                 goto free_nvmeq;
1662
1663         nvmeq->cq_vector = 0;
1664         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1665         if (result)
1666                 goto free_nvmeq;
1667
1668         return result;
1669
1670  free_nvmeq:
1671         nvme_free_queues(dev, 0);
1672         return result;
1673 }
1674
1675 struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1676                                 unsigned long addr, unsigned length)
1677 {
1678         int i, err, count, nents, offset;
1679         struct scatterlist *sg;
1680         struct page **pages;
1681         struct nvme_iod *iod;
1682
1683         if (addr & 3)
1684                 return ERR_PTR(-EINVAL);
1685         if (!length || length > INT_MAX - PAGE_SIZE)
1686                 return ERR_PTR(-EINVAL);
1687
1688         offset = offset_in_page(addr);
1689         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1690         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1691         if (!pages)
1692                 return ERR_PTR(-ENOMEM);
1693
1694         err = get_user_pages_fast(addr, count, 1, pages);
1695         if (err < count) {
1696                 count = err;
1697                 err = -EFAULT;
1698                 goto put_pages;
1699         }
1700
1701         err = -ENOMEM;
1702         iod = __nvme_alloc_iod(count, length, dev, 0, GFP_KERNEL);
1703         if (!iod)
1704                 goto put_pages;
1705
1706         sg = iod->sg;
1707         sg_init_table(sg, count);
1708         for (i = 0; i < count; i++) {
1709                 sg_set_page(&sg[i], pages[i],
1710                             min_t(unsigned, length, PAGE_SIZE - offset),
1711                             offset);
1712                 length -= (PAGE_SIZE - offset);
1713                 offset = 0;
1714         }
1715         sg_mark_end(&sg[i - 1]);
1716         iod->nents = count;
1717
1718         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1719                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1720         if (!nents)
1721                 goto free_iod;
1722
1723         kfree(pages);
1724         return iod;
1725
1726  free_iod:
1727         kfree(iod);
1728  put_pages:
1729         for (i = 0; i < count; i++)
1730                 put_page(pages[i]);
1731         kfree(pages);
1732         return ERR_PTR(err);
1733 }
1734
1735 void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1736                         struct nvme_iod *iod)
1737 {
1738         int i;
1739
1740         dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1741                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1742
1743         for (i = 0; i < iod->nents; i++)
1744                 put_page(sg_page(&iod->sg[i]));
1745 }
1746
1747 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1748 {
1749         struct nvme_dev *dev = ns->dev;
1750         struct nvme_user_io io;
1751         struct nvme_command c;
1752         unsigned length, meta_len;
1753         int status, i;
1754         struct nvme_iod *iod, *meta_iod = NULL;
1755         dma_addr_t meta_dma_addr;
1756         void *meta, *uninitialized_var(meta_mem);
1757
1758         if (copy_from_user(&io, uio, sizeof(io)))
1759                 return -EFAULT;
1760         length = (io.nblocks + 1) << ns->lba_shift;
1761         meta_len = (io.nblocks + 1) * ns->ms;
1762
1763         if (meta_len && ((io.metadata & 3) || !io.metadata))
1764                 return -EINVAL;
1765
1766         switch (io.opcode) {
1767         case nvme_cmd_write:
1768         case nvme_cmd_read:
1769         case nvme_cmd_compare:
1770                 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
1771                 break;
1772         default:
1773                 return -EINVAL;
1774         }
1775
1776         if (IS_ERR(iod))
1777                 return PTR_ERR(iod);
1778
1779         memset(&c, 0, sizeof(c));
1780         c.rw.opcode = io.opcode;
1781         c.rw.flags = io.flags;
1782         c.rw.nsid = cpu_to_le32(ns->ns_id);
1783         c.rw.slba = cpu_to_le64(io.slba);
1784         c.rw.length = cpu_to_le16(io.nblocks);
1785         c.rw.control = cpu_to_le16(io.control);
1786         c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1787         c.rw.reftag = cpu_to_le32(io.reftag);
1788         c.rw.apptag = cpu_to_le16(io.apptag);
1789         c.rw.appmask = cpu_to_le16(io.appmask);
1790
1791         if (meta_len) {
1792                 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1793                                                                 meta_len);
1794                 if (IS_ERR(meta_iod)) {
1795                         status = PTR_ERR(meta_iod);
1796                         meta_iod = NULL;
1797                         goto unmap;
1798                 }
1799
1800                 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1801                                                 &meta_dma_addr, GFP_KERNEL);
1802                 if (!meta_mem) {
1803                         status = -ENOMEM;
1804                         goto unmap;
1805                 }
1806
1807                 if (io.opcode & 1) {
1808                         int meta_offset = 0;
1809
1810                         for (i = 0; i < meta_iod->nents; i++) {
1811                                 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1812                                                 meta_iod->sg[i].offset;
1813                                 memcpy(meta_mem + meta_offset, meta,
1814                                                 meta_iod->sg[i].length);
1815                                 kunmap_atomic(meta);
1816                                 meta_offset += meta_iod->sg[i].length;
1817                         }
1818                 }
1819
1820                 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1821         }
1822
1823         length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1824         c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1825         c.rw.prp2 = cpu_to_le64(iod->first_dma);
1826
1827         if (length != (io.nblocks + 1) << ns->lba_shift)
1828                 status = -ENOMEM;
1829         else
1830                 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
1831
1832         if (meta_len) {
1833                 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1834                         int meta_offset = 0;
1835
1836                         for (i = 0; i < meta_iod->nents; i++) {
1837                                 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1838                                                 meta_iod->sg[i].offset;
1839                                 memcpy(meta, meta_mem + meta_offset,
1840                                                 meta_iod->sg[i].length);
1841                                 kunmap_atomic(meta);
1842                                 meta_offset += meta_iod->sg[i].length;
1843                         }
1844                 }
1845
1846                 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1847                                                                 meta_dma_addr);
1848         }
1849
1850  unmap:
1851         nvme_unmap_user_pages(dev, io.opcode & 1, iod);
1852         nvme_free_iod(dev, iod);
1853
1854         if (meta_iod) {
1855                 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1856                 nvme_free_iod(dev, meta_iod);
1857         }
1858
1859         return status;
1860 }
1861
1862 static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1863                         struct nvme_passthru_cmd __user *ucmd)
1864 {
1865         struct nvme_passthru_cmd cmd;
1866         struct nvme_command c;
1867         int status, length;
1868         struct nvme_iod *uninitialized_var(iod);
1869         unsigned timeout;
1870
1871         if (!capable(CAP_SYS_ADMIN))
1872                 return -EACCES;
1873         if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1874                 return -EFAULT;
1875
1876         memset(&c, 0, sizeof(c));
1877         c.common.opcode = cmd.opcode;
1878         c.common.flags = cmd.flags;
1879         c.common.nsid = cpu_to_le32(cmd.nsid);
1880         c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1881         c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1882         c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1883         c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1884         c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1885         c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1886         c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1887         c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1888
1889         length = cmd.data_len;
1890         if (cmd.data_len) {
1891                 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1892                                                                 length);
1893                 if (IS_ERR(iod))
1894                         return PTR_ERR(iod);
1895                 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1896                 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1897                 c.common.prp2 = cpu_to_le64(iod->first_dma);
1898         }
1899
1900         timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1901                                                                 ADMIN_TIMEOUT;
1902
1903         if (length != cmd.data_len)
1904                 status = -ENOMEM;
1905         else if (ns) {
1906                 struct request *req;
1907
1908                 req = blk_mq_alloc_request(ns->queue, WRITE,
1909                                                 (GFP_KERNEL|__GFP_WAIT), false);
1910                 if (IS_ERR(req))
1911                         status = PTR_ERR(req);
1912                 else {
1913                         status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1914                                                                 timeout);
1915                         blk_mq_free_request(req);
1916                 }
1917         } else
1918                 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
1919
1920         if (cmd.data_len) {
1921                 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1922                 nvme_free_iod(dev, iod);
1923         }
1924
1925         if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
1926                                                         sizeof(cmd.result)))
1927                 status = -EFAULT;
1928
1929         return status;
1930 }
1931
1932 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1933                                                         unsigned long arg)
1934 {
1935         struct nvme_ns *ns = bdev->bd_disk->private_data;
1936
1937         switch (cmd) {
1938         case NVME_IOCTL_ID:
1939                 force_successful_syscall_return();
1940                 return ns->ns_id;
1941         case NVME_IOCTL_ADMIN_CMD:
1942                 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
1943         case NVME_IOCTL_IO_CMD:
1944                 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
1945         case NVME_IOCTL_SUBMIT_IO:
1946                 return nvme_submit_io(ns, (void __user *)arg);
1947         case SG_GET_VERSION_NUM:
1948                 return nvme_sg_get_version_num((void __user *)arg);
1949         case SG_IO:
1950                 return nvme_sg_io(ns, (void __user *)arg);
1951         default:
1952                 return -ENOTTY;
1953         }
1954 }
1955
1956 #ifdef CONFIG_COMPAT
1957 static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1958                                         unsigned int cmd, unsigned long arg)
1959 {
1960         switch (cmd) {
1961         case SG_IO:
1962                 return -ENOIOCTLCMD;
1963         }
1964         return nvme_ioctl(bdev, mode, cmd, arg);
1965 }
1966 #else
1967 #define nvme_compat_ioctl       NULL
1968 #endif
1969
1970 static int nvme_open(struct block_device *bdev, fmode_t mode)
1971 {
1972         int ret = 0;
1973         struct nvme_ns *ns;
1974
1975         spin_lock(&dev_list_lock);
1976         ns = bdev->bd_disk->private_data;
1977         if (!ns)
1978                 ret = -ENXIO;
1979         else if (!kref_get_unless_zero(&ns->dev->kref))
1980                 ret = -ENXIO;
1981         spin_unlock(&dev_list_lock);
1982
1983         return ret;
1984 }
1985
1986 static void nvme_free_dev(struct kref *kref);
1987
1988 static void nvme_release(struct gendisk *disk, fmode_t mode)
1989 {
1990         struct nvme_ns *ns = disk->private_data;
1991         struct nvme_dev *dev = ns->dev;
1992
1993         kref_put(&dev->kref, nvme_free_dev);
1994 }
1995
1996 static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1997 {
1998         /* some standard values */
1999         geo->heads = 1 << 6;
2000         geo->sectors = 1 << 5;
2001         geo->cylinders = get_capacity(bd->bd_disk) >> 11;
2002         return 0;
2003 }
2004
2005 static void nvme_config_discard(struct nvme_ns *ns)
2006 {
2007         u32 logical_block_size = queue_logical_block_size(ns->queue);
2008         ns->queue->limits.discard_zeroes_data = 0;
2009         ns->queue->limits.discard_alignment = logical_block_size;
2010         ns->queue->limits.discard_granularity = logical_block_size;
2011         ns->queue->limits.max_discard_sectors = 0xffffffff;
2012         queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
2013 }
2014
2015 static int nvme_revalidate_disk(struct gendisk *disk)
2016 {
2017         struct nvme_ns *ns = disk->private_data;
2018         struct nvme_dev *dev = ns->dev;
2019         struct nvme_id_ns *id;
2020         dma_addr_t dma_addr;
2021         int lbaf, pi_type, old_ms;
2022         unsigned short bs;
2023
2024         id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
2025                                                                 GFP_KERNEL);
2026         if (!id) {
2027                 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
2028                                                                 __func__);
2029                 return 0;
2030         }
2031         if (nvme_identify(dev, ns->ns_id, 0, dma_addr)) {
2032                 dev_warn(&dev->pci_dev->dev,
2033                         "identify failed ns:%d, setting capacity to 0\n",
2034                         ns->ns_id);
2035                 memset(id, 0, sizeof(*id));
2036         }
2037
2038         old_ms = ns->ms;
2039         lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
2040         ns->lba_shift = id->lbaf[lbaf].ds;
2041         ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
2042
2043         /*
2044          * If identify namespace failed, use default 512 byte block size so
2045          * block layer can use before failing read/write for 0 capacity.
2046          */
2047         if (ns->lba_shift == 0)
2048                 ns->lba_shift = 9;
2049         bs = 1 << ns->lba_shift;
2050
2051         /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2052         pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2053                                         id->dps & NVME_NS_DPS_PI_MASK : 0;
2054
2055         if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2056                                 ns->ms != old_ms ||
2057                                 bs != queue_logical_block_size(disk->queue) ||
2058                                 (ns->ms && id->flbas & NVME_NS_FLBAS_META_EXT)))
2059                 blk_integrity_unregister(disk);
2060
2061         ns->pi_type = pi_type;
2062         blk_queue_logical_block_size(ns->queue, bs);
2063
2064         if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
2065                                 !(id->flbas & NVME_NS_FLBAS_META_EXT))
2066                 nvme_init_integrity(ns);
2067
2068         if (id->ncap == 0 || (ns->ms && !blk_get_integrity(disk)))
2069                 set_capacity(disk, 0);
2070         else
2071                 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2072
2073         if (dev->oncs & NVME_CTRL_ONCS_DSM)
2074                 nvme_config_discard(ns);
2075
2076         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
2077         return 0;
2078 }
2079
2080 static const struct block_device_operations nvme_fops = {
2081         .owner          = THIS_MODULE,
2082         .ioctl          = nvme_ioctl,
2083         .compat_ioctl   = nvme_compat_ioctl,
2084         .open           = nvme_open,
2085         .release        = nvme_release,
2086         .getgeo         = nvme_getgeo,
2087         .revalidate_disk= nvme_revalidate_disk,
2088 };
2089
2090 static int nvme_kthread(void *data)
2091 {
2092         struct nvme_dev *dev, *next;
2093
2094         while (!kthread_should_stop()) {
2095                 set_current_state(TASK_INTERRUPTIBLE);
2096                 spin_lock(&dev_list_lock);
2097                 list_for_each_entry_safe(dev, next, &dev_list, node) {
2098                         int i;
2099                         if (readl(&dev->bar->csts) & NVME_CSTS_CFS) {
2100                                 if (work_busy(&dev->reset_work))
2101                                         continue;
2102                                 list_del_init(&dev->node);
2103                                 dev_warn(&dev->pci_dev->dev,
2104                                         "Failed status: %x, reset controller\n",
2105                                         readl(&dev->bar->csts));
2106                                 dev->reset_workfn = nvme_reset_failed_dev;
2107                                 queue_work(nvme_workq, &dev->reset_work);
2108                                 continue;
2109                         }
2110                         for (i = 0; i < dev->queue_count; i++) {
2111                                 struct nvme_queue *nvmeq = dev->queues[i];
2112                                 if (!nvmeq)
2113                                         continue;
2114                                 spin_lock_irq(&nvmeq->q_lock);
2115                                 nvme_process_cq(nvmeq);
2116
2117                                 while ((i == 0) && (dev->event_limit > 0)) {
2118                                         if (nvme_submit_async_admin_req(dev))
2119                                                 break;
2120                                         dev->event_limit--;
2121                                 }
2122                                 spin_unlock_irq(&nvmeq->q_lock);
2123                         }
2124                 }
2125                 spin_unlock(&dev_list_lock);
2126                 schedule_timeout(round_jiffies_relative(HZ));
2127         }
2128         return 0;
2129 }
2130
2131 static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
2132 {
2133         struct nvme_ns *ns;
2134         struct gendisk *disk;
2135         int node = dev_to_node(&dev->pci_dev->dev);
2136
2137         ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2138         if (!ns)
2139                 return;
2140
2141         ns->queue = blk_mq_init_queue(&dev->tagset);
2142         if (IS_ERR(ns->queue))
2143                 goto out_free_ns;
2144         queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2145         queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2146         queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
2147         ns->dev = dev;
2148         ns->queue->queuedata = ns;
2149
2150         disk = alloc_disk_node(0, node);
2151         if (!disk)
2152                 goto out_free_queue;
2153
2154         ns->ns_id = nsid;
2155         ns->disk = disk;
2156         ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2157         list_add_tail(&ns->list, &dev->namespaces);
2158
2159         blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
2160         if (dev->max_hw_sectors)
2161                 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
2162         if (dev->stripe_size)
2163                 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
2164         if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2165                 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
2166
2167         disk->major = nvme_major;
2168         disk->first_minor = 0;
2169         disk->fops = &nvme_fops;
2170         disk->private_data = ns;
2171         disk->queue = ns->queue;
2172         disk->driverfs_dev = dev->device;
2173         disk->flags = GENHD_FL_EXT_DEVT;
2174         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
2175
2176         /*
2177          * Initialize capacity to 0 until we establish the namespace format and
2178          * setup integrity extentions if necessary. The revalidate_disk after
2179          * add_disk allows the driver to register with integrity if the format
2180          * requires it.
2181          */
2182         set_capacity(disk, 0);
2183         nvme_revalidate_disk(ns->disk);
2184         add_disk(ns->disk);
2185         if (ns->ms)
2186                 revalidate_disk(ns->disk);
2187         return;
2188  out_free_queue:
2189         blk_cleanup_queue(ns->queue);
2190  out_free_ns:
2191         kfree(ns);
2192 }
2193
2194 static void nvme_create_io_queues(struct nvme_dev *dev)
2195 {
2196         unsigned i;
2197
2198         for (i = dev->queue_count; i <= dev->max_qid; i++)
2199                 if (!nvme_alloc_queue(dev, i, dev->q_depth))
2200                         break;
2201
2202         for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2203                 if (nvme_create_queue(dev->queues[i], i))
2204                         break;
2205 }
2206
2207 static int set_queue_count(struct nvme_dev *dev, int count)
2208 {
2209         int status;
2210         u32 result;
2211         u32 q_count = (count - 1) | ((count - 1) << 16);
2212
2213         status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
2214                                                                 &result);
2215         if (status < 0)
2216                 return status;
2217         if (status > 0) {
2218                 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2219                                                                         status);
2220                 return 0;
2221         }
2222         return min(result & 0xffff, result >> 16) + 1;
2223 }
2224
2225 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2226 {
2227         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
2228 }
2229
2230 static int nvme_setup_io_queues(struct nvme_dev *dev)
2231 {
2232         struct nvme_queue *adminq = dev->queues[0];
2233         struct pci_dev *pdev = dev->pci_dev;
2234         int result, i, vecs, nr_io_queues, size;
2235
2236         nr_io_queues = num_possible_cpus();
2237         result = set_queue_count(dev, nr_io_queues);
2238         if (result <= 0)
2239                 return result;
2240         if (result < nr_io_queues)
2241                 nr_io_queues = result;
2242
2243         size = db_bar_size(dev, nr_io_queues);
2244         if (size > 8192) {
2245                 iounmap(dev->bar);
2246                 do {
2247                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2248                         if (dev->bar)
2249                                 break;
2250                         if (!--nr_io_queues)
2251                                 return -ENOMEM;
2252                         size = db_bar_size(dev, nr_io_queues);
2253                 } while (1);
2254                 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2255                 adminq->q_db = dev->dbs;
2256         }
2257
2258         /* Deregister the admin queue's interrupt */
2259         free_irq(dev->entry[0].vector, adminq);
2260
2261         /*
2262          * If we enable msix early due to not intx, disable it again before
2263          * setting up the full range we need.
2264          */
2265         if (!pdev->irq)
2266                 pci_disable_msix(pdev);
2267
2268         for (i = 0; i < nr_io_queues; i++)
2269                 dev->entry[i].entry = i;
2270         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2271         if (vecs < 0) {
2272                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2273                 if (vecs < 0) {
2274                         vecs = 1;
2275                 } else {
2276                         for (i = 0; i < vecs; i++)
2277                                 dev->entry[i].vector = i + pdev->irq;
2278                 }
2279         }
2280
2281         /*
2282          * Should investigate if there's a performance win from allocating
2283          * more queues than interrupt vectors; it might allow the submission
2284          * path to scale better, even if the receive path is limited by the
2285          * number of interrupts.
2286          */
2287         nr_io_queues = vecs;
2288         dev->max_qid = nr_io_queues;
2289
2290         result = queue_request_irq(dev, adminq, adminq->irqname);
2291         if (result)
2292                 goto free_queues;
2293
2294         /* Free previously allocated queues that are no longer usable */
2295         nvme_free_queues(dev, nr_io_queues + 1);
2296         nvme_create_io_queues(dev);
2297
2298         return 0;
2299
2300  free_queues:
2301         nvme_free_queues(dev, 1);
2302         return result;
2303 }
2304
2305 /*
2306  * Return: error value if an error occurred setting up the queues or calling
2307  * Identify Device.  0 if these succeeded, even if adding some of the
2308  * namespaces failed.  At the moment, these failures are silent.  TBD which
2309  * failures should be reported.
2310  */
2311 static int nvme_dev_add(struct nvme_dev *dev)
2312 {
2313         struct pci_dev *pdev = dev->pci_dev;
2314         int res;
2315         unsigned nn, i;
2316         struct nvme_id_ctrl *ctrl;
2317         void *mem;
2318         dma_addr_t dma_addr;
2319         int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
2320
2321         mem = dma_alloc_coherent(&pdev->dev, 4096, &dma_addr, GFP_KERNEL);
2322         if (!mem)
2323                 return -ENOMEM;
2324
2325         res = nvme_identify(dev, 0, 1, dma_addr);
2326         if (res) {
2327                 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
2328                 dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
2329                 return -EIO;
2330         }
2331
2332         ctrl = mem;
2333         nn = le32_to_cpup(&ctrl->nn);
2334         dev->oncs = le16_to_cpup(&ctrl->oncs);
2335         dev->abort_limit = ctrl->acl + 1;
2336         dev->vwc = ctrl->vwc;
2337         dev->event_limit = min(ctrl->aerl + 1, 8);
2338         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2339         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2340         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
2341         if (ctrl->mdts)
2342                 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
2343         if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2344                         (pdev->device == 0x0953) && ctrl->vs[3]) {
2345                 unsigned int max_hw_sectors;
2346
2347                 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
2348                 max_hw_sectors = dev->stripe_size >> (shift - 9);
2349                 if (dev->max_hw_sectors) {
2350                         dev->max_hw_sectors = min(max_hw_sectors,
2351                                                         dev->max_hw_sectors);
2352                 } else
2353                         dev->max_hw_sectors = max_hw_sectors;
2354         }
2355         dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr);
2356
2357         dev->tagset.ops = &nvme_mq_ops;
2358         dev->tagset.nr_hw_queues = dev->online_queues - 1;
2359         dev->tagset.timeout = NVME_IO_TIMEOUT;
2360         dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2361         dev->tagset.queue_depth =
2362                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2363         dev->tagset.cmd_size = nvme_cmd_size(dev);
2364         dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2365         dev->tagset.driver_data = dev;
2366
2367         if (blk_mq_alloc_tag_set(&dev->tagset))
2368                 return 0;
2369
2370         for (i = 1; i <= nn; i++)
2371                 nvme_alloc_ns(dev, i);
2372
2373         return 0;
2374 }
2375
2376 static int nvme_dev_map(struct nvme_dev *dev)
2377 {
2378         u64 cap;
2379         int bars, result = -ENOMEM;
2380         struct pci_dev *pdev = dev->pci_dev;
2381
2382         if (pci_enable_device_mem(pdev))
2383                 return result;
2384
2385         dev->entry[0].vector = pdev->irq;
2386         pci_set_master(pdev);
2387         bars = pci_select_bars(pdev, IORESOURCE_MEM);
2388         if (!bars)
2389                 goto disable_pci;
2390
2391         if (pci_request_selected_regions(pdev, bars, "nvme"))
2392                 goto disable_pci;
2393
2394         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2395             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2396                 goto disable;
2397
2398         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2399         if (!dev->bar)
2400                 goto disable;
2401
2402         if (readl(&dev->bar->csts) == -1) {
2403                 result = -ENODEV;
2404                 goto unmap;
2405         }
2406
2407         /*
2408          * Some devices don't advertse INTx interrupts, pre-enable a single
2409          * MSIX vec for setup. We'll adjust this later.
2410          */
2411         if (!pdev->irq) {
2412                 result = pci_enable_msix(pdev, dev->entry, 1);
2413                 if (result < 0)
2414                         goto unmap;
2415         }
2416
2417         cap = readq(&dev->bar->cap);
2418         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2419         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
2420         dev->dbs = ((void __iomem *)dev->bar) + 4096;
2421
2422         return 0;
2423
2424  unmap:
2425         iounmap(dev->bar);
2426         dev->bar = NULL;
2427  disable:
2428         pci_release_regions(pdev);
2429  disable_pci:
2430         pci_disable_device(pdev);
2431         return result;
2432 }
2433
2434 static void nvme_dev_unmap(struct nvme_dev *dev)
2435 {
2436         if (dev->pci_dev->msi_enabled)
2437                 pci_disable_msi(dev->pci_dev);
2438         else if (dev->pci_dev->msix_enabled)
2439                 pci_disable_msix(dev->pci_dev);
2440
2441         if (dev->bar) {
2442                 iounmap(dev->bar);
2443                 dev->bar = NULL;
2444                 pci_release_regions(dev->pci_dev);
2445         }
2446
2447         if (pci_is_enabled(dev->pci_dev))
2448                 pci_disable_device(dev->pci_dev);
2449 }
2450
2451 struct nvme_delq_ctx {
2452         struct task_struct *waiter;
2453         struct kthread_worker *worker;
2454         atomic_t refcount;
2455 };
2456
2457 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2458 {
2459         dq->waiter = current;
2460         mb();
2461
2462         for (;;) {
2463                 set_current_state(TASK_KILLABLE);
2464                 if (!atomic_read(&dq->refcount))
2465                         break;
2466                 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2467                                         fatal_signal_pending(current)) {
2468                         /*
2469                          * Disable the controller first since we can't trust it
2470                          * at this point, but leave the admin queue enabled
2471                          * until all queue deletion requests are flushed.
2472                          * FIXME: This may take a while if there are more h/w
2473                          * queues than admin tags.
2474                          */
2475                         set_current_state(TASK_RUNNING);
2476                         nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2477                         nvme_clear_queue(dev->queues[0]);
2478                         flush_kthread_worker(dq->worker);
2479                         nvme_disable_queue(dev, 0);
2480                         return;
2481                 }
2482         }
2483         set_current_state(TASK_RUNNING);
2484 }
2485
2486 static void nvme_put_dq(struct nvme_delq_ctx *dq)
2487 {
2488         atomic_dec(&dq->refcount);
2489         if (dq->waiter)
2490                 wake_up_process(dq->waiter);
2491 }
2492
2493 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2494 {
2495         atomic_inc(&dq->refcount);
2496         return dq;
2497 }
2498
2499 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2500 {
2501         struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2502         nvme_put_dq(dq);
2503 }
2504
2505 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2506                                                 kthread_work_func_t fn)
2507 {
2508         struct nvme_command c;
2509
2510         memset(&c, 0, sizeof(c));
2511         c.delete_queue.opcode = opcode;
2512         c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2513
2514         init_kthread_work(&nvmeq->cmdinfo.work, fn);
2515         return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2516                                                                 ADMIN_TIMEOUT);
2517 }
2518
2519 static void nvme_del_cq_work_handler(struct kthread_work *work)
2520 {
2521         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2522                                                         cmdinfo.work);
2523         nvme_del_queue_end(nvmeq);
2524 }
2525
2526 static int nvme_delete_cq(struct nvme_queue *nvmeq)
2527 {
2528         return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2529                                                 nvme_del_cq_work_handler);
2530 }
2531
2532 static void nvme_del_sq_work_handler(struct kthread_work *work)
2533 {
2534         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2535                                                         cmdinfo.work);
2536         int status = nvmeq->cmdinfo.status;
2537
2538         if (!status)
2539                 status = nvme_delete_cq(nvmeq);
2540         if (status)
2541                 nvme_del_queue_end(nvmeq);
2542 }
2543
2544 static int nvme_delete_sq(struct nvme_queue *nvmeq)
2545 {
2546         return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2547                                                 nvme_del_sq_work_handler);
2548 }
2549
2550 static void nvme_del_queue_start(struct kthread_work *work)
2551 {
2552         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2553                                                         cmdinfo.work);
2554         if (nvme_delete_sq(nvmeq))
2555                 nvme_del_queue_end(nvmeq);
2556 }
2557
2558 static void nvme_disable_io_queues(struct nvme_dev *dev)
2559 {
2560         int i;
2561         DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2562         struct nvme_delq_ctx dq;
2563         struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2564                                         &worker, "nvme%d", dev->instance);
2565
2566         if (IS_ERR(kworker_task)) {
2567                 dev_err(&dev->pci_dev->dev,
2568                         "Failed to create queue del task\n");
2569                 for (i = dev->queue_count - 1; i > 0; i--)
2570                         nvme_disable_queue(dev, i);
2571                 return;
2572         }
2573
2574         dq.waiter = NULL;
2575         atomic_set(&dq.refcount, 0);
2576         dq.worker = &worker;
2577         for (i = dev->queue_count - 1; i > 0; i--) {
2578                 struct nvme_queue *nvmeq = dev->queues[i];
2579
2580                 if (nvme_suspend_queue(nvmeq))
2581                         continue;
2582                 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2583                 nvmeq->cmdinfo.worker = dq.worker;
2584                 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2585                 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2586         }
2587         nvme_wait_dq(&dq, dev);
2588         kthread_stop(kworker_task);
2589 }
2590
2591 /*
2592 * Remove the node from the device list and check
2593 * for whether or not we need to stop the nvme_thread.
2594 */
2595 static void nvme_dev_list_remove(struct nvme_dev *dev)
2596 {
2597         struct task_struct *tmp = NULL;
2598
2599         spin_lock(&dev_list_lock);
2600         list_del_init(&dev->node);
2601         if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2602                 tmp = nvme_thread;
2603                 nvme_thread = NULL;
2604         }
2605         spin_unlock(&dev_list_lock);
2606
2607         if (tmp)
2608                 kthread_stop(tmp);
2609 }
2610
2611 static void nvme_freeze_queues(struct nvme_dev *dev)
2612 {
2613         struct nvme_ns *ns;
2614
2615         list_for_each_entry(ns, &dev->namespaces, list) {
2616                 blk_mq_freeze_queue_start(ns->queue);
2617
2618                 spin_lock(ns->queue->queue_lock);
2619                 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2620                 spin_unlock(ns->queue->queue_lock);
2621
2622                 blk_mq_cancel_requeue_work(ns->queue);
2623                 blk_mq_stop_hw_queues(ns->queue);
2624         }
2625 }
2626
2627 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2628 {
2629         struct nvme_ns *ns;
2630
2631         list_for_each_entry(ns, &dev->namespaces, list) {
2632                 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2633                 blk_mq_unfreeze_queue(ns->queue);
2634                 blk_mq_start_stopped_hw_queues(ns->queue, true);
2635                 blk_mq_kick_requeue_list(ns->queue);
2636         }
2637 }
2638
2639 static void nvme_dev_shutdown(struct nvme_dev *dev)
2640 {
2641         int i;
2642         u32 csts = -1;
2643
2644         nvme_dev_list_remove(dev);
2645
2646         if (dev->bar) {
2647                 nvme_freeze_queues(dev);
2648                 csts = readl(&dev->bar->csts);
2649         }
2650         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2651                 for (i = dev->queue_count - 1; i >= 0; i--) {
2652                         struct nvme_queue *nvmeq = dev->queues[i];
2653                         nvme_suspend_queue(nvmeq);
2654                 }
2655         } else {
2656                 nvme_disable_io_queues(dev);
2657                 nvme_shutdown_ctrl(dev);
2658                 nvme_disable_queue(dev, 0);
2659         }
2660         nvme_dev_unmap(dev);
2661
2662         for (i = dev->queue_count - 1; i >= 0; i--)
2663                 nvme_clear_queue(dev->queues[i]);
2664 }
2665
2666 static void nvme_dev_remove(struct nvme_dev *dev)
2667 {
2668         struct nvme_ns *ns;
2669
2670         list_for_each_entry(ns, &dev->namespaces, list) {
2671                 if (ns->disk->flags & GENHD_FL_UP) {
2672                         if (blk_get_integrity(ns->disk))
2673                                 blk_integrity_unregister(ns->disk);
2674                         del_gendisk(ns->disk);
2675                 }
2676                 if (!blk_queue_dying(ns->queue)) {
2677                         blk_mq_abort_requeue_list(ns->queue);
2678                         blk_cleanup_queue(ns->queue);
2679                 }
2680         }
2681 }
2682
2683 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2684 {
2685         struct device *dmadev = &dev->pci_dev->dev;
2686         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2687                                                 PAGE_SIZE, PAGE_SIZE, 0);
2688         if (!dev->prp_page_pool)
2689                 return -ENOMEM;
2690
2691         /* Optimisation for I/Os between 4k and 128k */
2692         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2693                                                 256, 256, 0);
2694         if (!dev->prp_small_pool) {
2695                 dma_pool_destroy(dev->prp_page_pool);
2696                 return -ENOMEM;
2697         }
2698         return 0;
2699 }
2700
2701 static void nvme_release_prp_pools(struct nvme_dev *dev)
2702 {
2703         dma_pool_destroy(dev->prp_page_pool);
2704         dma_pool_destroy(dev->prp_small_pool);
2705 }
2706
2707 static DEFINE_IDA(nvme_instance_ida);
2708
2709 static int nvme_set_instance(struct nvme_dev *dev)
2710 {
2711         int instance, error;
2712
2713         do {
2714                 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2715                         return -ENODEV;
2716
2717                 spin_lock(&dev_list_lock);
2718                 error = ida_get_new(&nvme_instance_ida, &instance);
2719                 spin_unlock(&dev_list_lock);
2720         } while (error == -EAGAIN);
2721
2722         if (error)
2723                 return -ENODEV;
2724
2725         dev->instance = instance;
2726         return 0;
2727 }
2728
2729 static void nvme_release_instance(struct nvme_dev *dev)
2730 {
2731         spin_lock(&dev_list_lock);
2732         ida_remove(&nvme_instance_ida, dev->instance);
2733         spin_unlock(&dev_list_lock);
2734 }
2735
2736 static void nvme_free_namespaces(struct nvme_dev *dev)
2737 {
2738         struct nvme_ns *ns, *next;
2739
2740         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2741                 list_del(&ns->list);
2742
2743                 spin_lock(&dev_list_lock);
2744                 ns->disk->private_data = NULL;
2745                 spin_unlock(&dev_list_lock);
2746
2747                 put_disk(ns->disk);
2748                 kfree(ns);
2749         }
2750 }
2751
2752 static void nvme_free_dev(struct kref *kref)
2753 {
2754         struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
2755
2756         pci_dev_put(dev->pci_dev);
2757         put_device(dev->device);
2758         nvme_free_namespaces(dev);
2759         nvme_release_instance(dev);
2760         blk_mq_free_tag_set(&dev->tagset);
2761         blk_put_queue(dev->admin_q);
2762         kfree(dev->queues);
2763         kfree(dev->entry);
2764         kfree(dev);
2765 }
2766
2767 static int nvme_dev_open(struct inode *inode, struct file *f)
2768 {
2769         struct nvme_dev *dev;
2770         int instance = iminor(inode);
2771         int ret = -ENODEV;
2772
2773         spin_lock(&dev_list_lock);
2774         list_for_each_entry(dev, &dev_list, node) {
2775                 if (dev->instance == instance) {
2776                         if (!dev->admin_q) {
2777                                 ret = -EWOULDBLOCK;
2778                                 break;
2779                         }
2780                         if (!kref_get_unless_zero(&dev->kref))
2781                                 break;
2782                         f->private_data = dev;
2783                         ret = 0;
2784                         break;
2785                 }
2786         }
2787         spin_unlock(&dev_list_lock);
2788
2789         return ret;
2790 }
2791
2792 static int nvme_dev_release(struct inode *inode, struct file *f)
2793 {
2794         struct nvme_dev *dev = f->private_data;
2795         kref_put(&dev->kref, nvme_free_dev);
2796         return 0;
2797 }
2798
2799 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2800 {
2801         struct nvme_dev *dev = f->private_data;
2802         struct nvme_ns *ns;
2803
2804         switch (cmd) {
2805         case NVME_IOCTL_ADMIN_CMD:
2806                 return nvme_user_cmd(dev, NULL, (void __user *)arg);
2807         case NVME_IOCTL_IO_CMD:
2808                 if (list_empty(&dev->namespaces))
2809                         return -ENOTTY;
2810                 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2811                 return nvme_user_cmd(dev, ns, (void __user *)arg);
2812         default:
2813                 return -ENOTTY;
2814         }
2815 }
2816
2817 static const struct file_operations nvme_dev_fops = {
2818         .owner          = THIS_MODULE,
2819         .open           = nvme_dev_open,
2820         .release        = nvme_dev_release,
2821         .unlocked_ioctl = nvme_dev_ioctl,
2822         .compat_ioctl   = nvme_dev_ioctl,
2823 };
2824
2825 static void nvme_set_irq_hints(struct nvme_dev *dev)
2826 {
2827         struct nvme_queue *nvmeq;
2828         int i;
2829
2830         for (i = 0; i < dev->online_queues; i++) {
2831                 nvmeq = dev->queues[i];
2832
2833                 if (!nvmeq->hctx)
2834                         continue;
2835
2836                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2837                                                         nvmeq->hctx->cpumask);
2838         }
2839 }
2840
2841 static int nvme_dev_start(struct nvme_dev *dev)
2842 {
2843         int result;
2844         bool start_thread = false;
2845
2846         result = nvme_dev_map(dev);
2847         if (result)
2848                 return result;
2849
2850         result = nvme_configure_admin_queue(dev);
2851         if (result)
2852                 goto unmap;
2853
2854         spin_lock(&dev_list_lock);
2855         if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2856                 start_thread = true;
2857                 nvme_thread = NULL;
2858         }
2859         list_add(&dev->node, &dev_list);
2860         spin_unlock(&dev_list_lock);
2861
2862         if (start_thread) {
2863                 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2864                 wake_up_all(&nvme_kthread_wait);
2865         } else
2866                 wait_event_killable(nvme_kthread_wait, nvme_thread);
2867
2868         if (IS_ERR_OR_NULL(nvme_thread)) {
2869                 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2870                 goto disable;
2871         }
2872
2873         nvme_init_queue(dev->queues[0], 0);
2874         result = nvme_alloc_admin_tags(dev);
2875         if (result)
2876                 goto disable;
2877
2878         result = nvme_setup_io_queues(dev);
2879         if (result)
2880                 goto free_tags;
2881
2882         nvme_set_irq_hints(dev);
2883
2884         return result;
2885
2886  free_tags:
2887         nvme_dev_remove_admin(dev);
2888  disable:
2889         nvme_disable_queue(dev, 0);
2890         nvme_dev_list_remove(dev);
2891  unmap:
2892         nvme_dev_unmap(dev);
2893         return result;
2894 }
2895
2896 static int nvme_remove_dead_ctrl(void *arg)
2897 {
2898         struct nvme_dev *dev = (struct nvme_dev *)arg;
2899         struct pci_dev *pdev = dev->pci_dev;
2900
2901         if (pci_get_drvdata(pdev))
2902                 pci_stop_and_remove_bus_device_locked(pdev);
2903         kref_put(&dev->kref, nvme_free_dev);
2904         return 0;
2905 }
2906
2907 static void nvme_remove_disks(struct work_struct *ws)
2908 {
2909         struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2910
2911         nvme_free_queues(dev, 1);
2912         nvme_dev_remove(dev);
2913 }
2914
2915 static int nvme_dev_resume(struct nvme_dev *dev)
2916 {
2917         int ret;
2918
2919         ret = nvme_dev_start(dev);
2920         if (ret)
2921                 return ret;
2922         if (dev->online_queues < 2) {
2923                 spin_lock(&dev_list_lock);
2924                 dev->reset_workfn = nvme_remove_disks;
2925                 queue_work(nvme_workq, &dev->reset_work);
2926                 spin_unlock(&dev_list_lock);
2927         } else {
2928                 nvme_unfreeze_queues(dev);
2929                 nvme_set_irq_hints(dev);
2930         }
2931         return 0;
2932 }
2933
2934 static void nvme_dev_reset(struct nvme_dev *dev)
2935 {
2936         nvme_dev_shutdown(dev);
2937         if (nvme_dev_resume(dev)) {
2938                 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
2939                 kref_get(&dev->kref);
2940                 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2941                                                         dev->instance))) {
2942                         dev_err(&dev->pci_dev->dev,
2943                                 "Failed to start controller remove task\n");
2944                         kref_put(&dev->kref, nvme_free_dev);
2945                 }
2946         }
2947 }
2948
2949 static void nvme_reset_failed_dev(struct work_struct *ws)
2950 {
2951         struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2952         nvme_dev_reset(dev);
2953 }
2954
2955 static void nvme_reset_workfn(struct work_struct *work)
2956 {
2957         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2958         dev->reset_workfn(work);
2959 }
2960
2961 static void nvme_async_probe(struct work_struct *work);
2962 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2963 {
2964         int node, result = -ENOMEM;
2965         struct nvme_dev *dev;
2966
2967         node = dev_to_node(&pdev->dev);
2968         if (node == NUMA_NO_NODE)
2969                 set_dev_node(&pdev->dev, 0);
2970
2971         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2972         if (!dev)
2973                 return -ENOMEM;
2974         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2975                                                         GFP_KERNEL, node);
2976         if (!dev->entry)
2977                 goto free;
2978         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2979                                                         GFP_KERNEL, node);
2980         if (!dev->queues)
2981                 goto free;
2982
2983         INIT_LIST_HEAD(&dev->namespaces);
2984         dev->reset_workfn = nvme_reset_failed_dev;
2985         INIT_WORK(&dev->reset_work, nvme_reset_workfn);
2986         dev->pci_dev = pci_dev_get(pdev);
2987         pci_set_drvdata(pdev, dev);
2988         result = nvme_set_instance(dev);
2989         if (result)
2990                 goto put_pci;
2991
2992         result = nvme_setup_prp_pools(dev);
2993         if (result)
2994                 goto release;
2995
2996         kref_init(&dev->kref);
2997         dev->device = device_create(nvme_class, &pdev->dev,
2998                                 MKDEV(nvme_char_major, dev->instance),
2999                                 dev, "nvme%d", dev->instance);
3000         if (IS_ERR(dev->device)) {
3001                 result = PTR_ERR(dev->device);
3002                 goto release_pools;
3003         }
3004         get_device(dev->device);
3005
3006         INIT_WORK(&dev->probe_work, nvme_async_probe);
3007         schedule_work(&dev->probe_work);
3008         return 0;
3009
3010  release_pools:
3011         nvme_release_prp_pools(dev);
3012  release:
3013         nvme_release_instance(dev);
3014  put_pci:
3015         pci_dev_put(dev->pci_dev);
3016  free:
3017         kfree(dev->queues);
3018         kfree(dev->entry);
3019         kfree(dev);
3020         return result;
3021 }
3022
3023 static void nvme_async_probe(struct work_struct *work)
3024 {
3025         struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
3026         int result;
3027
3028         result = nvme_dev_start(dev);
3029         if (result)
3030                 goto reset;
3031
3032         if (dev->online_queues > 1)
3033                 result = nvme_dev_add(dev);
3034         if (result)
3035                 goto reset;
3036
3037         nvme_set_irq_hints(dev);
3038         return;
3039  reset:
3040         if (!work_busy(&dev->reset_work)) {
3041                 dev->reset_workfn = nvme_reset_failed_dev;
3042                 queue_work(nvme_workq, &dev->reset_work);
3043         }
3044 }
3045
3046 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3047 {
3048         struct nvme_dev *dev = pci_get_drvdata(pdev);
3049
3050         if (prepare)
3051                 nvme_dev_shutdown(dev);
3052         else
3053                 nvme_dev_resume(dev);
3054 }
3055
3056 static void nvme_shutdown(struct pci_dev *pdev)
3057 {
3058         struct nvme_dev *dev = pci_get_drvdata(pdev);
3059         nvme_dev_shutdown(dev);
3060 }
3061
3062 static void nvme_remove(struct pci_dev *pdev)
3063 {
3064         struct nvme_dev *dev = pci_get_drvdata(pdev);
3065
3066         spin_lock(&dev_list_lock);
3067         list_del_init(&dev->node);
3068         spin_unlock(&dev_list_lock);
3069
3070         pci_set_drvdata(pdev, NULL);
3071         flush_work(&dev->probe_work);
3072         flush_work(&dev->reset_work);
3073         nvme_dev_shutdown(dev);
3074         nvme_dev_remove(dev);
3075         nvme_dev_remove_admin(dev);
3076         device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3077         nvme_free_queues(dev, 0);
3078         nvme_release_prp_pools(dev);
3079         kref_put(&dev->kref, nvme_free_dev);
3080 }
3081
3082 /* These functions are yet to be implemented */
3083 #define nvme_error_detected NULL
3084 #define nvme_dump_registers NULL
3085 #define nvme_link_reset NULL
3086 #define nvme_slot_reset NULL
3087 #define nvme_error_resume NULL
3088
3089 #ifdef CONFIG_PM_SLEEP
3090 static int nvme_suspend(struct device *dev)
3091 {
3092         struct pci_dev *pdev = to_pci_dev(dev);
3093         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3094
3095         nvme_dev_shutdown(ndev);
3096         return 0;
3097 }
3098
3099 static int nvme_resume(struct device *dev)
3100 {
3101         struct pci_dev *pdev = to_pci_dev(dev);
3102         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3103
3104         if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
3105                 ndev->reset_workfn = nvme_reset_failed_dev;
3106                 queue_work(nvme_workq, &ndev->reset_work);
3107         }
3108         return 0;
3109 }
3110 #endif
3111
3112 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
3113
3114 static const struct pci_error_handlers nvme_err_handler = {
3115         .error_detected = nvme_error_detected,
3116         .mmio_enabled   = nvme_dump_registers,
3117         .link_reset     = nvme_link_reset,
3118         .slot_reset     = nvme_slot_reset,
3119         .resume         = nvme_error_resume,
3120         .reset_notify   = nvme_reset_notify,
3121 };
3122
3123 /* Move to pci_ids.h later */
3124 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
3125
3126 static const struct pci_device_id nvme_id_table[] = {
3127         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3128         { 0, }
3129 };
3130 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3131
3132 static struct pci_driver nvme_driver = {
3133         .name           = "nvme",
3134         .id_table       = nvme_id_table,
3135         .probe          = nvme_probe,
3136         .remove         = nvme_remove,
3137         .shutdown       = nvme_shutdown,
3138         .driver         = {
3139                 .pm     = &nvme_dev_pm_ops,
3140         },
3141         .err_handler    = &nvme_err_handler,
3142 };
3143
3144 static int __init nvme_init(void)
3145 {
3146         int result;
3147
3148         init_waitqueue_head(&nvme_kthread_wait);
3149
3150         nvme_workq = create_singlethread_workqueue("nvme");
3151         if (!nvme_workq)
3152                 return -ENOMEM;
3153
3154         result = register_blkdev(nvme_major, "nvme");
3155         if (result < 0)
3156                 goto kill_workq;
3157         else if (result > 0)
3158                 nvme_major = result;
3159
3160         result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3161                                                         &nvme_dev_fops);
3162         if (result < 0)
3163                 goto unregister_blkdev;
3164         else if (result > 0)
3165                 nvme_char_major = result;
3166
3167         nvme_class = class_create(THIS_MODULE, "nvme");
3168         if (!nvme_class)
3169                 goto unregister_chrdev;
3170
3171         result = pci_register_driver(&nvme_driver);
3172         if (result)
3173                 goto destroy_class;
3174         return 0;
3175
3176  destroy_class:
3177         class_destroy(nvme_class);
3178  unregister_chrdev:
3179         __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3180  unregister_blkdev:
3181         unregister_blkdev(nvme_major, "nvme");
3182  kill_workq:
3183         destroy_workqueue(nvme_workq);
3184         return result;
3185 }
3186
3187 static void __exit nvme_exit(void)
3188 {
3189         pci_unregister_driver(&nvme_driver);
3190         unregister_blkdev(nvme_major, "nvme");
3191         destroy_workqueue(nvme_workq);
3192         class_destroy(nvme_class);
3193         __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3194         BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
3195         _nvme_check_size();
3196 }
3197
3198 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3199 MODULE_LICENSE("GPL");
3200 MODULE_VERSION("1.0");
3201 module_init(nvme_init);
3202 module_exit(nvme_exit);