2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/ptrace.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/types.h>
44 #include <asm-generic/io-64-nonatomic-lo-hi.h>
46 #define NVME_Q_DEPTH 1024
47 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
48 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
49 #define NVME_MINORS 64
50 #define ADMIN_TIMEOUT (60 * HZ)
52 static int nvme_major;
53 module_param(nvme_major, int, 0);
55 static int use_threaded_interrupts;
56 module_param(use_threaded_interrupts, int, 0);
58 static DEFINE_SPINLOCK(dev_list_lock);
59 static LIST_HEAD(dev_list);
60 static struct task_struct *nvme_thread;
63 * An NVM Express queue. Each device has at least two (one for admin
64 * commands and one for I/O commands).
67 struct device *q_dmadev;
70 struct nvme_command *sq_cmds;
71 volatile struct nvme_completion *cqes;
72 dma_addr_t sq_dma_addr;
73 dma_addr_t cq_dma_addr;
74 wait_queue_head_t sq_full;
75 wait_queue_t sq_cong_wait;
76 struct bio_list sq_cong;
86 unsigned long cmdid_data[];
90 * Check we didin't inadvertently grow the command struct
92 static inline void _nvme_check_size(void)
94 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
95 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
96 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
97 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
98 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
99 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
100 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
101 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
102 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
103 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
104 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
107 typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
108 struct nvme_completion *);
110 struct nvme_cmd_info {
111 nvme_completion_fn fn;
113 unsigned long timeout;
116 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
118 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
121 static unsigned nvme_queue_extra(int depth)
123 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
127 * alloc_cmdid() - Allocate a Command ID
128 * @nvmeq: The queue that will be used for this command
129 * @ctx: A pointer that will be passed to the handler
130 * @handler: The function to call on completion
132 * Allocate a Command ID for a queue. The data passed in will
133 * be passed to the completion handler. This is implemented by using
134 * the bottom two bits of the ctx pointer to store the handler ID.
135 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
136 * We can change this if it becomes a problem.
138 * May be called with local interrupts disabled and the q_lock held,
139 * or with interrupts enabled and no locks held.
141 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
142 nvme_completion_fn handler, unsigned timeout)
144 int depth = nvmeq->q_depth - 1;
145 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
149 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
152 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
154 info[cmdid].fn = handler;
155 info[cmdid].ctx = ctx;
156 info[cmdid].timeout = jiffies + timeout;
160 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
161 nvme_completion_fn handler, unsigned timeout)
164 wait_event_killable(nvmeq->sq_full,
165 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
166 return (cmdid < 0) ? -EINTR : cmdid;
169 /* Special values must be less than 0x1000 */
170 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
171 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
172 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
173 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
174 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
176 static void special_completion(struct nvme_dev *dev, void *ctx,
177 struct nvme_completion *cqe)
179 if (ctx == CMD_CTX_CANCELLED)
181 if (ctx == CMD_CTX_FLUSH)
183 if (ctx == CMD_CTX_COMPLETED) {
184 dev_warn(&dev->pci_dev->dev,
185 "completed id %d twice on queue %d\n",
186 cqe->command_id, le16_to_cpup(&cqe->sq_id));
189 if (ctx == CMD_CTX_INVALID) {
190 dev_warn(&dev->pci_dev->dev,
191 "invalid id %d completed on queue %d\n",
192 cqe->command_id, le16_to_cpup(&cqe->sq_id));
196 dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
200 * Called with local interrupts disabled and the q_lock held. May not sleep.
202 static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
203 nvme_completion_fn *fn)
206 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
208 if (cmdid >= nvmeq->q_depth) {
209 *fn = special_completion;
210 return CMD_CTX_INVALID;
213 *fn = info[cmdid].fn;
214 ctx = info[cmdid].ctx;
215 info[cmdid].fn = special_completion;
216 info[cmdid].ctx = CMD_CTX_COMPLETED;
217 clear_bit(cmdid, nvmeq->cmdid_data);
218 wake_up(&nvmeq->sq_full);
222 static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
223 nvme_completion_fn *fn)
226 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
228 *fn = info[cmdid].fn;
229 ctx = info[cmdid].ctx;
230 info[cmdid].fn = special_completion;
231 info[cmdid].ctx = CMD_CTX_CANCELLED;
235 struct nvme_queue *get_nvmeq(struct nvme_dev *dev)
237 return dev->queues[get_cpu() + 1];
240 void put_nvmeq(struct nvme_queue *nvmeq)
246 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
247 * @nvmeq: The queue to use
248 * @cmd: The command to send
250 * Safe to use from interrupt context
252 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
256 spin_lock_irqsave(&nvmeq->q_lock, flags);
257 tail = nvmeq->sq_tail;
258 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
259 if (++tail == nvmeq->q_depth)
261 writel(tail, nvmeq->q_db);
262 nvmeq->sq_tail = tail;
263 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
268 static __le64 **iod_list(struct nvme_iod *iod)
270 return ((void *)iod) + iod->offset;
274 * Will slightly overestimate the number of pages needed. This is OK
275 * as it only leads to a small amount of wasted memory for the lifetime of
278 static int nvme_npages(unsigned size)
280 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
281 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
284 static struct nvme_iod *
285 nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
287 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
288 sizeof(__le64 *) * nvme_npages(nbytes) +
289 sizeof(struct scatterlist) * nseg, gfp);
292 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
294 iod->length = nbytes;
296 iod->start_time = jiffies;
302 void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
304 const int last_prp = PAGE_SIZE / 8 - 1;
306 __le64 **list = iod_list(iod);
307 dma_addr_t prp_dma = iod->first_dma;
309 if (iod->npages == 0)
310 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
311 for (i = 0; i < iod->npages; i++) {
312 __le64 *prp_list = list[i];
313 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
314 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
315 prp_dma = next_prp_dma;
320 static void nvme_start_io_acct(struct bio *bio)
322 struct gendisk *disk = bio->bi_bdev->bd_disk;
323 const int rw = bio_data_dir(bio);
324 int cpu = part_stat_lock();
325 part_round_stats(cpu, &disk->part0);
326 part_stat_inc(cpu, &disk->part0, ios[rw]);
327 part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio));
328 part_inc_in_flight(&disk->part0, rw);
332 static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
334 struct gendisk *disk = bio->bi_bdev->bd_disk;
335 const int rw = bio_data_dir(bio);
336 unsigned long duration = jiffies - start_time;
337 int cpu = part_stat_lock();
338 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
339 part_round_stats(cpu, &disk->part0);
340 part_dec_in_flight(&disk->part0, rw);
344 static void bio_completion(struct nvme_dev *dev, void *ctx,
345 struct nvme_completion *cqe)
347 struct nvme_iod *iod = ctx;
348 struct bio *bio = iod->private;
349 u16 status = le16_to_cpup(&cqe->status) >> 1;
352 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
353 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
354 nvme_end_io_acct(bio, iod->start_time);
356 nvme_free_iod(dev, iod);
358 bio_endio(bio, -EIO);
363 /* length is in bytes. gfp flags indicates whether we may sleep. */
364 int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd,
365 struct nvme_iod *iod, int total_len, gfp_t gfp)
367 struct dma_pool *pool;
368 int length = total_len;
369 struct scatterlist *sg = iod->sg;
370 int dma_len = sg_dma_len(sg);
371 u64 dma_addr = sg_dma_address(sg);
372 int offset = offset_in_page(dma_addr);
374 __le64 **list = iod_list(iod);
378 cmd->prp1 = cpu_to_le64(dma_addr);
379 length -= (PAGE_SIZE - offset);
383 dma_len -= (PAGE_SIZE - offset);
385 dma_addr += (PAGE_SIZE - offset);
388 dma_addr = sg_dma_address(sg);
389 dma_len = sg_dma_len(sg);
392 if (length <= PAGE_SIZE) {
393 cmd->prp2 = cpu_to_le64(dma_addr);
397 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
398 if (nprps <= (256 / 8)) {
399 pool = dev->prp_small_pool;
402 pool = dev->prp_page_pool;
406 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
408 cmd->prp2 = cpu_to_le64(dma_addr);
410 return (total_len - length) + PAGE_SIZE;
413 iod->first_dma = prp_dma;
414 cmd->prp2 = cpu_to_le64(prp_dma);
417 if (i == PAGE_SIZE / 8) {
418 __le64 *old_prp_list = prp_list;
419 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
421 return total_len - length;
422 list[iod->npages++] = prp_list;
423 prp_list[0] = old_prp_list[i - 1];
424 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
427 prp_list[i++] = cpu_to_le64(dma_addr);
428 dma_len -= PAGE_SIZE;
429 dma_addr += PAGE_SIZE;
437 dma_addr = sg_dma_address(sg);
438 dma_len = sg_dma_len(sg);
444 static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
447 struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL);
451 bio_chain(split, bio);
453 if (bio_list_empty(&nvmeq->sq_cong))
454 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
455 bio_list_add(&nvmeq->sq_cong, split);
456 bio_list_add(&nvmeq->sq_cong, bio);
461 /* NVMe scatterlists require no holes in the virtual address */
462 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
463 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
465 static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
466 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
468 struct bio_vec bvec, bvprv;
469 struct bvec_iter iter;
470 struct scatterlist *sg = NULL;
471 int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size;
474 if (nvmeq->dev->stripe_size)
475 split_len = nvmeq->dev->stripe_size -
476 ((bio->bi_iter.bi_sector << 9) &
477 (nvmeq->dev->stripe_size - 1));
479 sg_init_table(iod->sg, psegs);
480 bio_for_each_segment(bvec, bio, iter) {
481 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
482 sg->length += bvec.bv_len;
484 if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec))
485 return nvme_split_and_submit(bio, nvmeq,
488 sg = sg ? sg + 1 : iod->sg;
489 sg_set_page(sg, bvec.bv_page,
490 bvec.bv_len, bvec.bv_offset);
494 if (split_len - length < bvec.bv_len)
495 return nvme_split_and_submit(bio, nvmeq, split_len);
496 length += bvec.bv_len;
502 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
505 BUG_ON(length != bio->bi_iter.bi_size);
510 * We reuse the small pool to allocate the 16-byte range here as it is not
511 * worth having a special pool for these or additional cases to handle freeing
514 static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
515 struct bio *bio, struct nvme_iod *iod, int cmdid)
517 struct nvme_dsm_range *range;
518 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
520 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
525 iod_list(iod)[0] = (__le64 *)range;
528 range->cattr = cpu_to_le32(0);
529 range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift);
530 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
532 memset(cmnd, 0, sizeof(*cmnd));
533 cmnd->dsm.opcode = nvme_cmd_dsm;
534 cmnd->dsm.command_id = cmdid;
535 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
536 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
538 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
540 if (++nvmeq->sq_tail == nvmeq->q_depth)
542 writel(nvmeq->sq_tail, nvmeq->q_db);
547 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
550 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
552 memset(cmnd, 0, sizeof(*cmnd));
553 cmnd->common.opcode = nvme_cmd_flush;
554 cmnd->common.command_id = cmdid;
555 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
557 if (++nvmeq->sq_tail == nvmeq->q_depth)
559 writel(nvmeq->sq_tail, nvmeq->q_db);
564 int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
566 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
567 special_completion, NVME_IO_TIMEOUT);
568 if (unlikely(cmdid < 0))
571 return nvme_submit_flush(nvmeq, ns, cmdid);
575 * Called with local interrupts disabled and the q_lock held. May not sleep.
577 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
580 struct nvme_command *cmnd;
581 struct nvme_iod *iod;
582 enum dma_data_direction dma_dir;
583 int cmdid, length, result;
586 int psegs = bio_phys_segments(ns->queue, bio);
588 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
589 result = nvme_submit_flush_data(nvmeq, ns);
595 iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC);
601 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
602 if (unlikely(cmdid < 0))
605 if (bio->bi_rw & REQ_DISCARD) {
606 result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
611 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
612 return nvme_submit_flush(nvmeq, ns, cmdid);
615 if (bio->bi_rw & REQ_FUA)
616 control |= NVME_RW_FUA;
617 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
618 control |= NVME_RW_LR;
621 if (bio->bi_rw & REQ_RAHEAD)
622 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
624 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
626 memset(cmnd, 0, sizeof(*cmnd));
627 if (bio_data_dir(bio)) {
628 cmnd->rw.opcode = nvme_cmd_write;
629 dma_dir = DMA_TO_DEVICE;
631 cmnd->rw.opcode = nvme_cmd_read;
632 dma_dir = DMA_FROM_DEVICE;
635 result = nvme_map_bio(nvmeq, iod, bio, dma_dir, psegs);
640 cmnd->rw.command_id = cmdid;
641 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
642 length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
644 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
645 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
646 cmnd->rw.control = cpu_to_le16(control);
647 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
649 nvme_start_io_acct(bio);
650 if (++nvmeq->sq_tail == nvmeq->q_depth)
652 writel(nvmeq->sq_tail, nvmeq->q_db);
657 free_cmdid(nvmeq, cmdid, NULL);
659 nvme_free_iod(nvmeq->dev, iod);
664 static int nvme_process_cq(struct nvme_queue *nvmeq)
668 head = nvmeq->cq_head;
669 phase = nvmeq->cq_phase;
673 nvme_completion_fn fn;
674 struct nvme_completion cqe = nvmeq->cqes[head];
675 if ((le16_to_cpu(cqe.status) & 1) != phase)
677 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
678 if (++head == nvmeq->q_depth) {
683 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
684 fn(nvmeq->dev, ctx, &cqe);
687 /* If the controller ignores the cq head doorbell and continuously
688 * writes to the queue, it is theoretically possible to wrap around
689 * the queue twice and mistakenly return IRQ_NONE. Linux only
690 * requires that 0.1% of your interrupts are handled, so this isn't
693 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
696 writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride));
697 nvmeq->cq_head = head;
698 nvmeq->cq_phase = phase;
704 static void nvme_make_request(struct request_queue *q, struct bio *bio)
706 struct nvme_ns *ns = q->queuedata;
707 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
712 bio_endio(bio, -EIO);
716 spin_lock_irq(&nvmeq->q_lock);
717 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
718 result = nvme_submit_bio_queue(nvmeq, ns, bio);
719 if (unlikely(result)) {
720 if (bio_list_empty(&nvmeq->sq_cong))
721 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
722 bio_list_add(&nvmeq->sq_cong, bio);
725 nvme_process_cq(nvmeq);
726 spin_unlock_irq(&nvmeq->q_lock);
730 static irqreturn_t nvme_irq(int irq, void *data)
733 struct nvme_queue *nvmeq = data;
734 spin_lock(&nvmeq->q_lock);
735 nvme_process_cq(nvmeq);
736 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
738 spin_unlock(&nvmeq->q_lock);
742 static irqreturn_t nvme_irq_check(int irq, void *data)
744 struct nvme_queue *nvmeq = data;
745 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
746 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
748 return IRQ_WAKE_THREAD;
751 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
753 spin_lock_irq(&nvmeq->q_lock);
754 cancel_cmdid(nvmeq, cmdid, NULL);
755 spin_unlock_irq(&nvmeq->q_lock);
758 struct sync_cmd_info {
759 struct task_struct *task;
764 static void sync_completion(struct nvme_dev *dev, void *ctx,
765 struct nvme_completion *cqe)
767 struct sync_cmd_info *cmdinfo = ctx;
768 cmdinfo->result = le32_to_cpup(&cqe->result);
769 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
770 wake_up_process(cmdinfo->task);
774 * Returns 0 on success. If the result is negative, it's a Linux error code;
775 * if the result is positive, it's an NVM Express status code
777 int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
778 u32 *result, unsigned timeout)
781 struct sync_cmd_info cmdinfo;
783 cmdinfo.task = current;
784 cmdinfo.status = -EINTR;
786 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
790 cmd->common.command_id = cmdid;
792 set_current_state(TASK_KILLABLE);
793 nvme_submit_cmd(nvmeq, cmd);
794 schedule_timeout(timeout);
796 if (cmdinfo.status == -EINTR) {
797 nvme_abort_command(nvmeq, cmdid);
802 *result = cmdinfo.result;
804 return cmdinfo.status;
807 int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
810 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
813 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
816 struct nvme_command c;
818 memset(&c, 0, sizeof(c));
819 c.delete_queue.opcode = opcode;
820 c.delete_queue.qid = cpu_to_le16(id);
822 status = nvme_submit_admin_cmd(dev, &c, NULL);
828 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
829 struct nvme_queue *nvmeq)
832 struct nvme_command c;
833 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
835 memset(&c, 0, sizeof(c));
836 c.create_cq.opcode = nvme_admin_create_cq;
837 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
838 c.create_cq.cqid = cpu_to_le16(qid);
839 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
840 c.create_cq.cq_flags = cpu_to_le16(flags);
841 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
843 status = nvme_submit_admin_cmd(dev, &c, NULL);
849 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
850 struct nvme_queue *nvmeq)
853 struct nvme_command c;
854 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
856 memset(&c, 0, sizeof(c));
857 c.create_sq.opcode = nvme_admin_create_sq;
858 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
859 c.create_sq.sqid = cpu_to_le16(qid);
860 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
861 c.create_sq.sq_flags = cpu_to_le16(flags);
862 c.create_sq.cqid = cpu_to_le16(qid);
864 status = nvme_submit_admin_cmd(dev, &c, NULL);
870 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
872 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
875 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
877 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
880 int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
883 struct nvme_command c;
885 memset(&c, 0, sizeof(c));
886 c.identify.opcode = nvme_admin_identify;
887 c.identify.nsid = cpu_to_le32(nsid);
888 c.identify.prp1 = cpu_to_le64(dma_addr);
889 c.identify.cns = cpu_to_le32(cns);
891 return nvme_submit_admin_cmd(dev, &c, NULL);
894 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
895 dma_addr_t dma_addr, u32 *result)
897 struct nvme_command c;
899 memset(&c, 0, sizeof(c));
900 c.features.opcode = nvme_admin_get_features;
901 c.features.nsid = cpu_to_le32(nsid);
902 c.features.prp1 = cpu_to_le64(dma_addr);
903 c.features.fid = cpu_to_le32(fid);
905 return nvme_submit_admin_cmd(dev, &c, result);
908 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
909 dma_addr_t dma_addr, u32 *result)
911 struct nvme_command c;
913 memset(&c, 0, sizeof(c));
914 c.features.opcode = nvme_admin_set_features;
915 c.features.prp1 = cpu_to_le64(dma_addr);
916 c.features.fid = cpu_to_le32(fid);
917 c.features.dword11 = cpu_to_le32(dword11);
919 return nvme_submit_admin_cmd(dev, &c, result);
923 * nvme_cancel_ios - Cancel outstanding I/Os
924 * @queue: The queue to cancel I/Os on
925 * @timeout: True to only cancel I/Os which have timed out
927 static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
929 int depth = nvmeq->q_depth - 1;
930 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
931 unsigned long now = jiffies;
934 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
936 nvme_completion_fn fn;
937 static struct nvme_completion cqe = {
938 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
941 if (timeout && !time_after(now, info[cmdid].timeout))
943 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
945 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid);
946 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
947 fn(nvmeq->dev, ctx, &cqe);
951 static void nvme_free_queue(struct nvme_queue *nvmeq)
953 spin_lock_irq(&nvmeq->q_lock);
954 while (bio_list_peek(&nvmeq->sq_cong)) {
955 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
956 bio_endio(bio, -EIO);
958 spin_unlock_irq(&nvmeq->q_lock);
960 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
961 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
962 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
963 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
967 static void nvme_free_queues(struct nvme_dev *dev)
971 for (i = dev->queue_count - 1; i >= 0; i--) {
972 nvme_free_queue(dev->queues[i]);
974 dev->queues[i] = NULL;
978 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
980 struct nvme_queue *nvmeq = dev->queues[qid];
981 int vector = dev->entry[nvmeq->cq_vector].vector;
983 spin_lock_irq(&nvmeq->q_lock);
984 if (nvmeq->q_suspended) {
985 spin_unlock_irq(&nvmeq->q_lock);
988 nvmeq->q_suspended = 1;
989 spin_unlock_irq(&nvmeq->q_lock);
991 irq_set_affinity_hint(vector, NULL);
992 free_irq(vector, nvmeq);
994 /* Don't tell the adapter to delete the admin queue */
996 adapter_delete_sq(dev, qid);
997 adapter_delete_cq(dev, qid);
1000 spin_lock_irq(&nvmeq->q_lock);
1001 nvme_process_cq(nvmeq);
1002 nvme_cancel_ios(nvmeq, false);
1003 spin_unlock_irq(&nvmeq->q_lock);
1006 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1007 int depth, int vector)
1009 struct device *dmadev = &dev->pci_dev->dev;
1010 unsigned extra = nvme_queue_extra(depth);
1011 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1015 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1016 &nvmeq->cq_dma_addr, GFP_KERNEL);
1019 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1021 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1022 &nvmeq->sq_dma_addr, GFP_KERNEL);
1023 if (!nvmeq->sq_cmds)
1026 nvmeq->q_dmadev = dmadev;
1028 spin_lock_init(&nvmeq->q_lock);
1030 nvmeq->cq_phase = 1;
1031 init_waitqueue_head(&nvmeq->sq_full);
1032 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
1033 bio_list_init(&nvmeq->sq_cong);
1034 nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
1035 nvmeq->q_depth = depth;
1036 nvmeq->cq_vector = vector;
1037 nvmeq->q_suspended = 1;
1043 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1044 nvmeq->cq_dma_addr);
1050 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1053 if (use_threaded_interrupts)
1054 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1055 nvme_irq_check, nvme_irq,
1056 IRQF_DISABLED | IRQF_SHARED,
1058 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1059 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
1062 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1064 struct nvme_dev *dev = nvmeq->dev;
1065 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
1069 nvmeq->cq_phase = 1;
1070 nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
1071 memset(nvmeq->cmdid_data, 0, extra);
1072 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1073 nvme_cancel_ios(nvmeq, false);
1074 nvmeq->q_suspended = 0;
1077 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1079 struct nvme_dev *dev = nvmeq->dev;
1082 result = adapter_alloc_cq(dev, qid, nvmeq);
1086 result = adapter_alloc_sq(dev, qid, nvmeq);
1090 result = queue_request_irq(dev, nvmeq, "nvme");
1094 spin_lock(&nvmeq->q_lock);
1095 nvme_init_queue(nvmeq, qid);
1096 spin_unlock(&nvmeq->q_lock);
1101 adapter_delete_sq(dev, qid);
1103 adapter_delete_cq(dev, qid);
1107 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1109 unsigned long timeout;
1110 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1112 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1114 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1116 if (fatal_signal_pending(current))
1118 if (time_after(jiffies, timeout)) {
1119 dev_err(&dev->pci_dev->dev,
1120 "Device not ready; aborting initialisation\n");
1129 * If the device has been passed off to us in an enabled state, just clear
1130 * the enabled bit. The spec says we should set the 'shutdown notification
1131 * bits', but doing so may cause the device to complete commands to the
1132 * admin queue ... and we don't know what memory that might be pointing at!
1134 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1136 u32 cc = readl(&dev->bar->cc);
1138 if (cc & NVME_CC_ENABLE)
1139 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
1140 return nvme_wait_ready(dev, cap, false);
1143 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1145 return nvme_wait_ready(dev, cap, true);
1148 static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1150 unsigned long timeout;
1153 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1154 writel(cc, &dev->bar->cc);
1156 timeout = 2 * HZ + jiffies;
1157 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1158 NVME_CSTS_SHST_CMPLT) {
1160 if (fatal_signal_pending(current))
1162 if (time_after(jiffies, timeout)) {
1163 dev_err(&dev->pci_dev->dev,
1164 "Device shutdown incomplete; abort shutdown\n");
1172 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1176 u64 cap = readq(&dev->bar->cap);
1177 struct nvme_queue *nvmeq;
1179 result = nvme_disable_ctrl(dev, cap);
1183 nvmeq = dev->queues[0];
1185 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1188 dev->queues[0] = nvmeq;
1191 aqa = nvmeq->q_depth - 1;
1194 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1195 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1196 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1197 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1199 writel(aqa, &dev->bar->aqa);
1200 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1201 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1202 writel(dev->ctrl_config, &dev->bar->cc);
1204 result = nvme_enable_ctrl(dev, cap);
1208 result = queue_request_irq(dev, nvmeq, "nvme admin");
1212 spin_lock(&nvmeq->q_lock);
1213 nvme_init_queue(nvmeq, 0);
1214 spin_unlock(&nvmeq->q_lock);
1218 struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1219 unsigned long addr, unsigned length)
1221 int i, err, count, nents, offset;
1222 struct scatterlist *sg;
1223 struct page **pages;
1224 struct nvme_iod *iod;
1227 return ERR_PTR(-EINVAL);
1228 if (!length || length > INT_MAX - PAGE_SIZE)
1229 return ERR_PTR(-EINVAL);
1231 offset = offset_in_page(addr);
1232 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1233 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1235 return ERR_PTR(-ENOMEM);
1237 err = get_user_pages_fast(addr, count, 1, pages);
1244 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1246 sg_init_table(sg, count);
1247 for (i = 0; i < count; i++) {
1248 sg_set_page(&sg[i], pages[i],
1249 min_t(unsigned, length, PAGE_SIZE - offset),
1251 length -= (PAGE_SIZE - offset);
1254 sg_mark_end(&sg[i - 1]);
1258 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1259 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1269 for (i = 0; i < count; i++)
1272 return ERR_PTR(err);
1275 void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1276 struct nvme_iod *iod)
1280 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1281 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1283 for (i = 0; i < iod->nents; i++)
1284 put_page(sg_page(&iod->sg[i]));
1287 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1289 struct nvme_dev *dev = ns->dev;
1290 struct nvme_queue *nvmeq;
1291 struct nvme_user_io io;
1292 struct nvme_command c;
1293 unsigned length, meta_len;
1295 struct nvme_iod *iod, *meta_iod = NULL;
1296 dma_addr_t meta_dma_addr;
1297 void *meta, *uninitialized_var(meta_mem);
1299 if (copy_from_user(&io, uio, sizeof(io)))
1301 length = (io.nblocks + 1) << ns->lba_shift;
1302 meta_len = (io.nblocks + 1) * ns->ms;
1304 if (meta_len && ((io.metadata & 3) || !io.metadata))
1307 switch (io.opcode) {
1308 case nvme_cmd_write:
1310 case nvme_cmd_compare:
1311 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
1318 return PTR_ERR(iod);
1320 memset(&c, 0, sizeof(c));
1321 c.rw.opcode = io.opcode;
1322 c.rw.flags = io.flags;
1323 c.rw.nsid = cpu_to_le32(ns->ns_id);
1324 c.rw.slba = cpu_to_le64(io.slba);
1325 c.rw.length = cpu_to_le16(io.nblocks);
1326 c.rw.control = cpu_to_le16(io.control);
1327 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1328 c.rw.reftag = cpu_to_le32(io.reftag);
1329 c.rw.apptag = cpu_to_le16(io.apptag);
1330 c.rw.appmask = cpu_to_le16(io.appmask);
1333 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1335 if (IS_ERR(meta_iod)) {
1336 status = PTR_ERR(meta_iod);
1341 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1342 &meta_dma_addr, GFP_KERNEL);
1348 if (io.opcode & 1) {
1349 int meta_offset = 0;
1351 for (i = 0; i < meta_iod->nents; i++) {
1352 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1353 meta_iod->sg[i].offset;
1354 memcpy(meta_mem + meta_offset, meta,
1355 meta_iod->sg[i].length);
1356 kunmap_atomic(meta);
1357 meta_offset += meta_iod->sg[i].length;
1361 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1364 length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
1366 nvmeq = get_nvmeq(dev);
1368 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1369 * disabled. We may be preempted at any point, and be rescheduled
1370 * to a different CPU. That will cause cacheline bouncing, but no
1371 * additional races since q_lock already protects against other CPUs.
1374 if (length != (io.nblocks + 1) << ns->lba_shift)
1376 else if (!nvmeq || nvmeq->q_suspended)
1379 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
1382 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1383 int meta_offset = 0;
1385 for (i = 0; i < meta_iod->nents; i++) {
1386 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1387 meta_iod->sg[i].offset;
1388 memcpy(meta, meta_mem + meta_offset,
1389 meta_iod->sg[i].length);
1390 kunmap_atomic(meta);
1391 meta_offset += meta_iod->sg[i].length;
1395 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1400 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
1401 nvme_free_iod(dev, iod);
1404 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1405 nvme_free_iod(dev, meta_iod);
1411 static int nvme_user_admin_cmd(struct nvme_dev *dev,
1412 struct nvme_admin_cmd __user *ucmd)
1414 struct nvme_admin_cmd cmd;
1415 struct nvme_command c;
1417 struct nvme_iod *uninitialized_var(iod);
1420 if (!capable(CAP_SYS_ADMIN))
1422 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1425 memset(&c, 0, sizeof(c));
1426 c.common.opcode = cmd.opcode;
1427 c.common.flags = cmd.flags;
1428 c.common.nsid = cpu_to_le32(cmd.nsid);
1429 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1430 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1431 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1432 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1433 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1434 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1435 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1436 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1438 length = cmd.data_len;
1440 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1443 return PTR_ERR(iod);
1444 length = nvme_setup_prps(dev, &c.common, iod, length,
1448 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1450 if (length != cmd.data_len)
1453 status = nvme_submit_sync_cmd(dev->queues[0], &c, &cmd.result,
1457 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1458 nvme_free_iod(dev, iod);
1461 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
1462 sizeof(cmd.result)))
1468 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1471 struct nvme_ns *ns = bdev->bd_disk->private_data;
1475 force_successful_syscall_return();
1477 case NVME_IOCTL_ADMIN_CMD:
1478 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
1479 case NVME_IOCTL_SUBMIT_IO:
1480 return nvme_submit_io(ns, (void __user *)arg);
1481 case SG_GET_VERSION_NUM:
1482 return nvme_sg_get_version_num((void __user *)arg);
1484 return nvme_sg_io(ns, (void __user *)arg);
1490 static const struct block_device_operations nvme_fops = {
1491 .owner = THIS_MODULE,
1492 .ioctl = nvme_ioctl,
1493 .compat_ioctl = nvme_ioctl,
1496 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1498 while (bio_list_peek(&nvmeq->sq_cong)) {
1499 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1500 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1502 if (bio_list_empty(&nvmeq->sq_cong))
1503 remove_wait_queue(&nvmeq->sq_full,
1504 &nvmeq->sq_cong_wait);
1505 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1506 if (bio_list_empty(&nvmeq->sq_cong))
1507 add_wait_queue(&nvmeq->sq_full,
1508 &nvmeq->sq_cong_wait);
1509 bio_list_add_head(&nvmeq->sq_cong, bio);
1515 static int nvme_kthread(void *data)
1517 struct nvme_dev *dev;
1519 while (!kthread_should_stop()) {
1520 set_current_state(TASK_INTERRUPTIBLE);
1521 spin_lock(&dev_list_lock);
1522 list_for_each_entry(dev, &dev_list, node) {
1524 for (i = 0; i < dev->queue_count; i++) {
1525 struct nvme_queue *nvmeq = dev->queues[i];
1528 spin_lock_irq(&nvmeq->q_lock);
1529 if (nvmeq->q_suspended)
1531 nvme_process_cq(nvmeq);
1532 nvme_cancel_ios(nvmeq, true);
1533 nvme_resubmit_bios(nvmeq);
1535 spin_unlock_irq(&nvmeq->q_lock);
1538 spin_unlock(&dev_list_lock);
1539 schedule_timeout(round_jiffies_relative(HZ));
1544 static DEFINE_IDA(nvme_index_ida);
1546 static int nvme_get_ns_idx(void)
1551 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1554 spin_lock(&dev_list_lock);
1555 error = ida_get_new(&nvme_index_ida, &index);
1556 spin_unlock(&dev_list_lock);
1557 } while (error == -EAGAIN);
1564 static void nvme_put_ns_idx(int index)
1566 spin_lock(&dev_list_lock);
1567 ida_remove(&nvme_index_ida, index);
1568 spin_unlock(&dev_list_lock);
1571 static void nvme_config_discard(struct nvme_ns *ns)
1573 u32 logical_block_size = queue_logical_block_size(ns->queue);
1574 ns->queue->limits.discard_zeroes_data = 0;
1575 ns->queue->limits.discard_alignment = logical_block_size;
1576 ns->queue->limits.discard_granularity = logical_block_size;
1577 ns->queue->limits.max_discard_sectors = 0xffffffff;
1578 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1581 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
1582 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1585 struct gendisk *disk;
1588 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1591 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1594 ns->queue = blk_alloc_queue(GFP_KERNEL);
1597 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1598 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1599 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1600 blk_queue_make_request(ns->queue, nvme_make_request);
1602 ns->queue->queuedata = ns;
1604 disk = alloc_disk(NVME_MINORS);
1606 goto out_free_queue;
1609 lbaf = id->flbas & 0xf;
1610 ns->lba_shift = id->lbaf[lbaf].ds;
1611 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
1612 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1613 if (dev->max_hw_sectors)
1614 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
1616 disk->major = nvme_major;
1617 disk->minors = NVME_MINORS;
1618 disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
1619 disk->fops = &nvme_fops;
1620 disk->private_data = ns;
1621 disk->queue = ns->queue;
1622 disk->driverfs_dev = &dev->pci_dev->dev;
1623 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1624 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1626 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1627 nvme_config_discard(ns);
1632 blk_cleanup_queue(ns->queue);
1638 static void nvme_ns_free(struct nvme_ns *ns)
1640 int index = ns->disk->first_minor / NVME_MINORS;
1642 nvme_put_ns_idx(index);
1643 blk_cleanup_queue(ns->queue);
1647 static int set_queue_count(struct nvme_dev *dev, int count)
1651 u32 q_count = (count - 1) | ((count - 1) << 16);
1653 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1656 return status < 0 ? -EIO : -EBUSY;
1657 return min(result & 0xffff, result >> 16) + 1;
1660 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1662 return 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
1665 static int nvme_setup_io_queues(struct nvme_dev *dev)
1667 struct pci_dev *pdev = dev->pci_dev;
1668 int result, cpu, i, vecs, nr_io_queues, size, q_depth;
1670 nr_io_queues = num_online_cpus();
1671 result = set_queue_count(dev, nr_io_queues);
1674 if (result < nr_io_queues)
1675 nr_io_queues = result;
1677 size = db_bar_size(dev, nr_io_queues);
1681 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1684 if (!--nr_io_queues)
1686 size = db_bar_size(dev, nr_io_queues);
1688 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1689 dev->queues[0]->q_db = dev->dbs;
1692 /* Deregister the admin queue's interrupt */
1693 free_irq(dev->entry[0].vector, dev->queues[0]);
1695 vecs = nr_io_queues;
1696 for (i = 0; i < vecs; i++)
1697 dev->entry[i].entry = i;
1699 result = pci_enable_msix(pdev, dev->entry, vecs);
1706 vecs = nr_io_queues;
1710 result = pci_enable_msi_block(pdev, vecs);
1712 for (i = 0; i < vecs; i++)
1713 dev->entry[i].vector = i + pdev->irq;
1715 } else if (result < 0) {
1724 * Should investigate if there's a performance win from allocating
1725 * more queues than interrupt vectors; it might allow the submission
1726 * path to scale better, even if the receive path is limited by the
1727 * number of interrupts.
1729 nr_io_queues = vecs;
1731 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1733 dev->queues[0]->q_suspended = 1;
1737 /* Free previously allocated queues that are no longer usable */
1738 spin_lock(&dev_list_lock);
1739 for (i = dev->queue_count - 1; i > nr_io_queues; i--) {
1740 struct nvme_queue *nvmeq = dev->queues[i];
1742 spin_lock(&nvmeq->q_lock);
1743 nvme_cancel_ios(nvmeq, false);
1744 spin_unlock(&nvmeq->q_lock);
1746 nvme_free_queue(nvmeq);
1748 dev->queues[i] = NULL;
1750 spin_unlock(&dev_list_lock);
1752 cpu = cpumask_first(cpu_online_mask);
1753 for (i = 0; i < nr_io_queues; i++) {
1754 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1755 cpu = cpumask_next(cpu, cpu_online_mask);
1758 q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1,
1760 for (i = dev->queue_count - 1; i < nr_io_queues; i++) {
1761 dev->queues[i + 1] = nvme_alloc_queue(dev, i + 1, q_depth, i);
1762 if (!dev->queues[i + 1]) {
1768 for (; i < num_possible_cpus(); i++) {
1769 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1770 dev->queues[i + 1] = dev->queues[target + 1];
1773 for (i = 1; i < dev->queue_count; i++) {
1774 result = nvme_create_queue(dev->queues[i], i);
1776 for (--i; i > 0; i--)
1777 nvme_disable_queue(dev, i);
1785 nvme_free_queues(dev);
1790 * Return: error value if an error occurred setting up the queues or calling
1791 * Identify Device. 0 if these succeeded, even if adding some of the
1792 * namespaces failed. At the moment, these failures are silent. TBD which
1793 * failures should be reported.
1795 static int nvme_dev_add(struct nvme_dev *dev)
1800 struct nvme_id_ctrl *ctrl;
1801 struct nvme_id_ns *id_ns;
1803 dma_addr_t dma_addr;
1804 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
1806 mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1811 res = nvme_identify(dev, 0, 1, dma_addr);
1818 nn = le32_to_cpup(&ctrl->nn);
1819 dev->oncs = le16_to_cpup(&ctrl->oncs);
1820 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1821 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1822 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1824 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
1825 if ((dev->pci_dev->vendor == PCI_VENDOR_ID_INTEL) &&
1826 (dev->pci_dev->device == 0x0953) && ctrl->vs[3])
1827 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
1830 for (i = 1; i <= nn; i++) {
1831 res = nvme_identify(dev, i, 0, dma_addr);
1835 if (id_ns->ncap == 0)
1838 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
1839 dma_addr + 4096, NULL);
1841 memset(mem + 4096, 0, 4096);
1843 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
1845 list_add_tail(&ns->list, &dev->namespaces);
1847 list_for_each_entry(ns, &dev->namespaces, list)
1852 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
1856 static int nvme_dev_map(struct nvme_dev *dev)
1858 int bars, result = -ENOMEM;
1859 struct pci_dev *pdev = dev->pci_dev;
1861 if (pci_enable_device_mem(pdev))
1864 dev->entry[0].vector = pdev->irq;
1865 pci_set_master(pdev);
1866 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1867 if (pci_request_selected_regions(pdev, bars, "nvme"))
1870 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
1871 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
1874 pci_set_drvdata(pdev, dev);
1875 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1879 dev->db_stride = NVME_CAP_STRIDE(readq(&dev->bar->cap));
1880 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1885 pci_release_regions(pdev);
1887 pci_disable_device(pdev);
1891 static void nvme_dev_unmap(struct nvme_dev *dev)
1893 if (dev->pci_dev->msi_enabled)
1894 pci_disable_msi(dev->pci_dev);
1895 else if (dev->pci_dev->msix_enabled)
1896 pci_disable_msix(dev->pci_dev);
1903 pci_release_regions(dev->pci_dev);
1904 if (pci_is_enabled(dev->pci_dev))
1905 pci_disable_device(dev->pci_dev);
1908 static void nvme_dev_shutdown(struct nvme_dev *dev)
1912 for (i = dev->queue_count - 1; i >= 0; i--)
1913 nvme_disable_queue(dev, i);
1915 spin_lock(&dev_list_lock);
1916 list_del_init(&dev->node);
1917 spin_unlock(&dev_list_lock);
1920 nvme_shutdown_ctrl(dev);
1921 nvme_dev_unmap(dev);
1924 static void nvme_dev_remove(struct nvme_dev *dev)
1926 struct nvme_ns *ns, *next;
1928 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1929 list_del(&ns->list);
1930 del_gendisk(ns->disk);
1935 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1937 struct device *dmadev = &dev->pci_dev->dev;
1938 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1939 PAGE_SIZE, PAGE_SIZE, 0);
1940 if (!dev->prp_page_pool)
1943 /* Optimisation for I/Os between 4k and 128k */
1944 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1946 if (!dev->prp_small_pool) {
1947 dma_pool_destroy(dev->prp_page_pool);
1953 static void nvme_release_prp_pools(struct nvme_dev *dev)
1955 dma_pool_destroy(dev->prp_page_pool);
1956 dma_pool_destroy(dev->prp_small_pool);
1959 static DEFINE_IDA(nvme_instance_ida);
1961 static int nvme_set_instance(struct nvme_dev *dev)
1963 int instance, error;
1966 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
1969 spin_lock(&dev_list_lock);
1970 error = ida_get_new(&nvme_instance_ida, &instance);
1971 spin_unlock(&dev_list_lock);
1972 } while (error == -EAGAIN);
1977 dev->instance = instance;
1981 static void nvme_release_instance(struct nvme_dev *dev)
1983 spin_lock(&dev_list_lock);
1984 ida_remove(&nvme_instance_ida, dev->instance);
1985 spin_unlock(&dev_list_lock);
1988 static void nvme_free_dev(struct kref *kref)
1990 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
1991 nvme_dev_remove(dev);
1992 nvme_dev_shutdown(dev);
1993 nvme_free_queues(dev);
1994 nvme_release_instance(dev);
1995 nvme_release_prp_pools(dev);
2001 static int nvme_dev_open(struct inode *inode, struct file *f)
2003 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2005 kref_get(&dev->kref);
2006 f->private_data = dev;
2010 static int nvme_dev_release(struct inode *inode, struct file *f)
2012 struct nvme_dev *dev = f->private_data;
2013 kref_put(&dev->kref, nvme_free_dev);
2017 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2019 struct nvme_dev *dev = f->private_data;
2021 case NVME_IOCTL_ADMIN_CMD:
2022 return nvme_user_admin_cmd(dev, (void __user *)arg);
2028 static const struct file_operations nvme_dev_fops = {
2029 .owner = THIS_MODULE,
2030 .open = nvme_dev_open,
2031 .release = nvme_dev_release,
2032 .unlocked_ioctl = nvme_dev_ioctl,
2033 .compat_ioctl = nvme_dev_ioctl,
2036 static int nvme_dev_start(struct nvme_dev *dev)
2040 result = nvme_dev_map(dev);
2044 result = nvme_configure_admin_queue(dev);
2048 spin_lock(&dev_list_lock);
2049 list_add(&dev->node, &dev_list);
2050 spin_unlock(&dev_list_lock);
2052 result = nvme_setup_io_queues(dev);
2053 if (result && result != -EBUSY)
2059 spin_lock(&dev_list_lock);
2060 list_del_init(&dev->node);
2061 spin_unlock(&dev_list_lock);
2063 nvme_dev_unmap(dev);
2067 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2069 int result = -ENOMEM;
2070 struct nvme_dev *dev;
2072 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2075 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2079 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2084 INIT_LIST_HEAD(&dev->namespaces);
2085 dev->pci_dev = pdev;
2087 result = nvme_set_instance(dev);
2091 result = nvme_setup_prp_pools(dev);
2095 result = nvme_dev_start(dev);
2097 if (result == -EBUSY)
2102 result = nvme_dev_add(dev);
2107 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2108 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2109 dev->miscdev.parent = &pdev->dev;
2110 dev->miscdev.name = dev->name;
2111 dev->miscdev.fops = &nvme_dev_fops;
2112 result = misc_register(&dev->miscdev);
2116 kref_init(&dev->kref);
2120 nvme_dev_remove(dev);
2122 nvme_dev_shutdown(dev);
2124 nvme_free_queues(dev);
2125 nvme_release_prp_pools(dev);
2127 nvme_release_instance(dev);
2135 static void nvme_remove(struct pci_dev *pdev)
2137 struct nvme_dev *dev = pci_get_drvdata(pdev);
2138 misc_deregister(&dev->miscdev);
2139 kref_put(&dev->kref, nvme_free_dev);
2142 /* These functions are yet to be implemented */
2143 #define nvme_error_detected NULL
2144 #define nvme_dump_registers NULL
2145 #define nvme_link_reset NULL
2146 #define nvme_slot_reset NULL
2147 #define nvme_error_resume NULL
2149 static int nvme_suspend(struct device *dev)
2151 struct pci_dev *pdev = to_pci_dev(dev);
2152 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2154 nvme_dev_shutdown(ndev);
2158 static int nvme_resume(struct device *dev)
2160 struct pci_dev *pdev = to_pci_dev(dev);
2161 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2164 ret = nvme_dev_start(ndev);
2165 /* XXX: should remove gendisks if resume fails */
2167 nvme_free_queues(ndev);
2171 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2173 static const struct pci_error_handlers nvme_err_handler = {
2174 .error_detected = nvme_error_detected,
2175 .mmio_enabled = nvme_dump_registers,
2176 .link_reset = nvme_link_reset,
2177 .slot_reset = nvme_slot_reset,
2178 .resume = nvme_error_resume,
2181 /* Move to pci_ids.h later */
2182 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2184 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
2185 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2188 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2190 static struct pci_driver nvme_driver = {
2192 .id_table = nvme_id_table,
2193 .probe = nvme_probe,
2194 .remove = nvme_remove,
2196 .pm = &nvme_dev_pm_ops,
2198 .err_handler = &nvme_err_handler,
2201 static int __init nvme_init(void)
2205 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2206 if (IS_ERR(nvme_thread))
2207 return PTR_ERR(nvme_thread);
2209 result = register_blkdev(nvme_major, "nvme");
2212 else if (result > 0)
2213 nvme_major = result;
2215 result = pci_register_driver(&nvme_driver);
2217 goto unregister_blkdev;
2221 unregister_blkdev(nvme_major, "nvme");
2223 kthread_stop(nvme_thread);
2227 static void __exit nvme_exit(void)
2229 pci_unregister_driver(&nvme_driver);
2230 unregister_blkdev(nvme_major, "nvme");
2231 kthread_stop(nvme_thread);
2234 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2235 MODULE_LICENSE("GPL");
2236 MODULE_VERSION("0.8");
2237 module_init(nvme_init);
2238 module_exit(nvme_exit);