2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include "sata_promise.h"
47 #define DRV_NAME "sata_promise"
48 #define DRV_VERSION "2.05"
54 /* register offsets */
55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
62 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
63 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
64 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
65 PDC_FLASH_CTL = 0x44, /* Flash control register */
66 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
67 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
68 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
69 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
73 /* PDC_GLOBAL_CTL bit definitions */
74 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
75 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
76 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
77 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
78 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
79 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
80 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
81 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
82 PDC_DRIVE_ERR = (1 << 21), /* drive error */
83 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
84 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
85 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
86 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR,
87 PDC_ERR_MASK = (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC_OVERRUN_ERR
88 | PDC_UNDERRUN_ERR | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR
89 | PDC1_ERR_MASK | PDC2_ERR_MASK),
91 board_2037x = 0, /* FastTrak S150 TX2plus */
92 board_20319 = 1, /* FastTrak S150 TX4 */
93 board_20619 = 2, /* FastTrak TX4000 */
94 board_2057x = 3, /* SATAII150 Tx2plus */
95 board_40518 = 4, /* SATAII150 Tx4 */
97 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
99 /* Sequence counter control registers bit definitions */
100 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
102 /* Feature register values */
103 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
104 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
106 /* Device/Head register values */
107 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
109 /* PDC_CTLSTAT bit definitions */
110 PDC_DMA_ENABLE = (1 << 7),
111 PDC_IRQ_DISABLE = (1 << 10),
112 PDC_RESET = (1 << 11), /* HDMA reset */
114 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
116 ATA_FLAG_PIO_POLLING,
119 PDC_FLAG_GEN_II = (1 << 0),
123 struct pdc_port_priv {
128 struct pdc_host_priv {
130 unsigned long port_flags[ATA_MAX_PORTS];
133 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
134 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
135 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
136 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
137 static int pdc_port_start(struct ata_port *ap);
138 static void pdc_qc_prep(struct ata_queued_cmd *qc);
139 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
140 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
141 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
142 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
143 static void pdc_irq_clear(struct ata_port *ap);
144 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
145 static void pdc_freeze(struct ata_port *ap);
146 static void pdc_thaw(struct ata_port *ap);
147 static void pdc_pata_error_handler(struct ata_port *ap);
148 static void pdc_sata_error_handler(struct ata_port *ap);
149 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
150 static int pdc_pata_cable_detect(struct ata_port *ap);
151 static int pdc_sata_cable_detect(struct ata_port *ap);
153 static struct scsi_host_template pdc_ata_sht = {
154 .module = THIS_MODULE,
156 .ioctl = ata_scsi_ioctl,
157 .queuecommand = ata_scsi_queuecmd,
158 .can_queue = ATA_DEF_QUEUE,
159 .this_id = ATA_SHT_THIS_ID,
160 .sg_tablesize = LIBATA_MAX_PRD,
161 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
162 .emulated = ATA_SHT_EMULATED,
163 .use_clustering = ATA_SHT_USE_CLUSTERING,
164 .proc_name = DRV_NAME,
165 .dma_boundary = ATA_DMA_BOUNDARY,
166 .slave_configure = ata_scsi_slave_config,
167 .slave_destroy = ata_scsi_slave_destroy,
168 .bios_param = ata_std_bios_param,
171 static const struct ata_port_operations pdc_sata_ops = {
172 .port_disable = ata_port_disable,
173 .tf_load = pdc_tf_load_mmio,
174 .tf_read = ata_tf_read,
175 .check_status = ata_check_status,
176 .exec_command = pdc_exec_command_mmio,
177 .dev_select = ata_std_dev_select,
178 .check_atapi_dma = pdc_check_atapi_dma,
180 .qc_prep = pdc_qc_prep,
181 .qc_issue = pdc_qc_issue_prot,
182 .freeze = pdc_freeze,
184 .error_handler = pdc_sata_error_handler,
185 .post_internal_cmd = pdc_post_internal_cmd,
186 .cable_detect = pdc_sata_cable_detect,
187 .data_xfer = ata_data_xfer,
188 .irq_handler = pdc_interrupt,
189 .irq_clear = pdc_irq_clear,
190 .irq_on = ata_irq_on,
191 .irq_ack = ata_irq_ack,
193 .scr_read = pdc_sata_scr_read,
194 .scr_write = pdc_sata_scr_write,
195 .port_start = pdc_port_start,
198 /* First-generation chips need a more restrictive ->check_atapi_dma op */
199 static const struct ata_port_operations pdc_old_sata_ops = {
200 .port_disable = ata_port_disable,
201 .tf_load = pdc_tf_load_mmio,
202 .tf_read = ata_tf_read,
203 .check_status = ata_check_status,
204 .exec_command = pdc_exec_command_mmio,
205 .dev_select = ata_std_dev_select,
206 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
208 .qc_prep = pdc_qc_prep,
209 .qc_issue = pdc_qc_issue_prot,
210 .freeze = pdc_freeze,
212 .error_handler = pdc_sata_error_handler,
213 .post_internal_cmd = pdc_post_internal_cmd,
214 .cable_detect = pdc_sata_cable_detect,
215 .data_xfer = ata_data_xfer,
216 .irq_handler = pdc_interrupt,
217 .irq_clear = pdc_irq_clear,
218 .irq_on = ata_irq_on,
219 .irq_ack = ata_irq_ack,
221 .scr_read = pdc_sata_scr_read,
222 .scr_write = pdc_sata_scr_write,
223 .port_start = pdc_port_start,
226 static const struct ata_port_operations pdc_pata_ops = {
227 .port_disable = ata_port_disable,
228 .tf_load = pdc_tf_load_mmio,
229 .tf_read = ata_tf_read,
230 .check_status = ata_check_status,
231 .exec_command = pdc_exec_command_mmio,
232 .dev_select = ata_std_dev_select,
233 .check_atapi_dma = pdc_check_atapi_dma,
235 .qc_prep = pdc_qc_prep,
236 .qc_issue = pdc_qc_issue_prot,
237 .freeze = pdc_freeze,
239 .error_handler = pdc_pata_error_handler,
240 .post_internal_cmd = pdc_post_internal_cmd,
241 .cable_detect = pdc_pata_cable_detect,
242 .data_xfer = ata_data_xfer,
243 .irq_handler = pdc_interrupt,
244 .irq_clear = pdc_irq_clear,
245 .irq_on = ata_irq_on,
246 .irq_ack = ata_irq_ack,
248 .port_start = pdc_port_start,
251 static const struct ata_port_info pdc_port_info[] = {
255 .flags = PDC_COMMON_FLAGS,
256 .pio_mask = 0x1f, /* pio0-4 */
257 .mwdma_mask = 0x07, /* mwdma0-2 */
258 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
259 .port_ops = &pdc_old_sata_ops,
265 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
266 .pio_mask = 0x1f, /* pio0-4 */
267 .mwdma_mask = 0x07, /* mwdma0-2 */
268 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
269 .port_ops = &pdc_old_sata_ops,
275 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
276 .pio_mask = 0x1f, /* pio0-4 */
277 .mwdma_mask = 0x07, /* mwdma0-2 */
278 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
279 .port_ops = &pdc_pata_ops,
285 .flags = PDC_COMMON_FLAGS,
286 .pio_mask = 0x1f, /* pio0-4 */
287 .mwdma_mask = 0x07, /* mwdma0-2 */
288 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
289 .port_ops = &pdc_sata_ops,
295 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
296 .pio_mask = 0x1f, /* pio0-4 */
297 .mwdma_mask = 0x07, /* mwdma0-2 */
298 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
299 .port_ops = &pdc_sata_ops,
303 static const struct pci_device_id pdc_ata_pci_tbl[] = {
304 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
305 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
306 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
307 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
308 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
309 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
310 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
311 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
312 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
313 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
315 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
316 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
317 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
318 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
319 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
320 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
322 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
324 { } /* terminate list */
328 static struct pci_driver pdc_ata_pci_driver = {
330 .id_table = pdc_ata_pci_tbl,
331 .probe = pdc_ata_init_one,
332 .remove = ata_pci_remove_one,
336 static int pdc_common_port_start(struct ata_port *ap)
338 struct device *dev = ap->host->dev;
339 struct pdc_port_priv *pp;
342 rc = ata_port_start(ap);
346 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
350 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
354 ap->private_data = pp;
359 static int pdc_sata_port_start(struct ata_port *ap)
361 struct pdc_host_priv *hp = ap->host->private_data;
364 rc = pdc_common_port_start(ap);
368 /* fix up PHYMODE4 align timing */
369 if (hp->flags & PDC_FLAG_GEN_II) {
370 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
373 tmp = readl(mmio + 0x014);
374 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
375 writel(tmp, mmio + 0x014);
381 static int pdc_port_start(struct ata_port *ap)
383 struct pdc_host_priv *hp = ap->host->private_data;
385 /* fix up port flags and cable type for SATA+PATA chips */
386 ap->flags |= hp->port_flags[ap->port_no];
387 if (ap->flags & ATA_FLAG_SATA) {
388 ap->cbl = ATA_CBL_SATA;
389 return pdc_sata_port_start(ap);
391 ap->ops = &pdc_pata_ops;
392 return pdc_common_port_start(ap);
396 static void pdc_reset_port(struct ata_port *ap)
398 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
402 for (i = 11; i > 0; i--) {
415 readl(mmio); /* flush */
418 static int pdc_pata_cable_detect(struct ata_port *ap)
421 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
425 return ATA_CBL_PATA40;
426 return ATA_CBL_PATA80;
429 static int pdc_sata_cable_detect(struct ata_port *ap)
434 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
436 if (sc_reg > SCR_CONTROL)
438 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
442 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
445 if (sc_reg > SCR_CONTROL)
447 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
450 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
452 struct ata_port *ap = qc->ap;
453 dma_addr_t sg_table = ap->prd_dma;
454 unsigned int cdb_len = qc->dev->cdb_len;
456 struct pdc_port_priv *pp = ap->private_data;
458 u32 *buf32 = (u32 *) buf;
459 unsigned int dev_sel, feature, nbytes;
461 /* set control bits (byte 0), zero delay seq id (byte 3),
462 * and seq id (byte 2)
464 switch (qc->tf.protocol) {
465 case ATA_PROT_ATAPI_DMA:
466 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
467 buf32[0] = cpu_to_le32(PDC_PKT_READ);
471 case ATA_PROT_ATAPI_NODATA:
472 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
478 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
479 buf32[2] = 0; /* no next-packet */
482 if (sata_scr_valid(ap)) {
483 dev_sel = PDC_DEVICE_SATA;
485 dev_sel = ATA_DEVICE_OBS;
486 if (qc->dev->devno != 0)
489 buf[12] = (1 << 5) | ATA_REG_DEVICE;
491 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
492 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
494 buf[16] = (1 << 5) | ATA_REG_NSECT;
496 buf[18] = (1 << 5) | ATA_REG_LBAL;
499 /* set feature and byte counter registers */
500 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
501 feature = PDC_FEATURE_ATAPI_PIO;
502 /* set byte counter register to real transfer byte count */
507 feature = PDC_FEATURE_ATAPI_DMA;
508 /* set byte counter register to 0 */
511 buf[20] = (1 << 5) | ATA_REG_FEATURE;
513 buf[22] = (1 << 5) | ATA_REG_BYTEL;
514 buf[23] = nbytes & 0xFF;
515 buf[24] = (1 << 5) | ATA_REG_BYTEH;
516 buf[25] = (nbytes >> 8) & 0xFF;
518 /* send ATAPI packet command 0xA0 */
519 buf[26] = (1 << 5) | ATA_REG_CMD;
520 buf[27] = ATA_CMD_PACKET;
522 /* select drive and check DRQ */
523 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
526 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
527 BUG_ON(cdb_len & ~0x1E);
529 /* append the CDB as the final part */
530 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
531 memcpy(buf+31, cdb, cdb_len);
534 static void pdc_qc_prep(struct ata_queued_cmd *qc)
536 struct pdc_port_priv *pp = qc->ap->private_data;
541 switch (qc->tf.protocol) {
546 case ATA_PROT_NODATA:
547 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
548 qc->dev->devno, pp->pkt);
550 if (qc->tf.flags & ATA_TFLAG_LBA48)
551 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
553 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
555 pdc_pkt_footer(&qc->tf, pp->pkt, i);
562 case ATA_PROT_ATAPI_DMA:
565 case ATA_PROT_ATAPI_NODATA:
574 static void pdc_freeze(struct ata_port *ap)
576 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
579 tmp = readl(mmio + PDC_CTLSTAT);
580 tmp |= PDC_IRQ_DISABLE;
581 tmp &= ~PDC_DMA_ENABLE;
582 writel(tmp, mmio + PDC_CTLSTAT);
583 readl(mmio + PDC_CTLSTAT); /* flush */
586 static void pdc_thaw(struct ata_port *ap)
588 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
592 readl(mmio + PDC_INT_SEQMASK);
594 /* turn IRQ back on */
595 tmp = readl(mmio + PDC_CTLSTAT);
596 tmp &= ~PDC_IRQ_DISABLE;
597 writel(tmp, mmio + PDC_CTLSTAT);
598 readl(mmio + PDC_CTLSTAT); /* flush */
601 static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
603 if (!(ap->pflags & ATA_PFLAG_FROZEN))
606 /* perform recovery */
607 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
611 static void pdc_pata_error_handler(struct ata_port *ap)
613 pdc_common_error_handler(ap, NULL);
616 static void pdc_sata_error_handler(struct ata_port *ap)
618 pdc_common_error_handler(ap, sata_std_hardreset);
621 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
623 struct ata_port *ap = qc->ap;
625 /* make DMA engine forget about the failed command */
626 if (qc->flags & ATA_QCFLAG_FAILED)
630 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
631 u32 port_status, u32 err_mask)
633 struct ata_eh_info *ehi = &ap->eh_info;
634 unsigned int ac_err_mask = 0;
636 ata_ehi_clear_desc(ehi);
637 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
638 port_status &= err_mask;
640 if (port_status & PDC_DRIVE_ERR)
641 ac_err_mask |= AC_ERR_DEV;
642 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
643 ac_err_mask |= AC_ERR_HSM;
644 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
645 ac_err_mask |= AC_ERR_ATA_BUS;
646 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
647 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
648 ac_err_mask |= AC_ERR_HOST_BUS;
650 if (sata_scr_valid(ap))
651 ehi->serror |= pdc_sata_scr_read(ap, SCR_ERROR);
653 qc->err_mask |= ac_err_mask;
658 static inline unsigned int pdc_host_intr( struct ata_port *ap,
659 struct ata_queued_cmd *qc)
661 unsigned int handled = 0;
662 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
663 struct pdc_host_priv *hp = ap->host->private_data;
664 u32 port_status, err_mask;
666 err_mask = PDC_ERR_MASK;
667 if (hp->flags & PDC_FLAG_GEN_II)
668 err_mask &= ~PDC1_ERR_MASK;
670 err_mask &= ~PDC2_ERR_MASK;
671 port_status = readl(port_mmio + PDC_GLOBAL_CTL);
672 if (unlikely(port_status & err_mask)) {
673 pdc_error_intr(ap, qc, port_status, err_mask);
677 switch (qc->tf.protocol) {
679 case ATA_PROT_NODATA:
680 case ATA_PROT_ATAPI_DMA:
681 case ATA_PROT_ATAPI_NODATA:
682 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
688 ap->stats.idle_irq++;
695 static void pdc_irq_clear(struct ata_port *ap)
697 struct ata_host *host = ap->host;
698 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
700 readl(mmio + PDC_INT_SEQMASK);
703 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
705 struct ata_host *host = dev_instance;
709 unsigned int handled = 0;
710 void __iomem *mmio_base;
714 if (!host || !host->iomap[PDC_MMIO_BAR]) {
715 VPRINTK("QUICK EXIT\n");
719 mmio_base = host->iomap[PDC_MMIO_BAR];
721 /* reading should also clear interrupts */
722 mask = readl(mmio_base + PDC_INT_SEQMASK);
724 if (mask == 0xffffffff) {
725 VPRINTK("QUICK EXIT 2\n");
729 spin_lock(&host->lock);
731 mask &= 0xffff; /* only 16 tags possible */
733 VPRINTK("QUICK EXIT 3\n");
737 writel(mask, mmio_base + PDC_INT_SEQMASK);
739 for (i = 0; i < host->n_ports; i++) {
740 VPRINTK("port %u\n", i);
742 tmp = mask & (1 << (i + 1));
744 !(ap->flags & ATA_FLAG_DISABLED)) {
745 struct ata_queued_cmd *qc;
747 qc = ata_qc_from_tag(ap, ap->active_tag);
748 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
749 handled += pdc_host_intr(ap, qc);
756 spin_unlock(&host->lock);
757 return IRQ_RETVAL(handled);
760 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
762 struct ata_port *ap = qc->ap;
763 struct pdc_port_priv *pp = ap->private_data;
764 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
765 unsigned int port_no = ap->port_no;
766 u8 seq = (u8) (port_no + 1);
768 VPRINTK("ENTER, ap %p\n", ap);
770 writel(0x00000001, mmio + (seq * 4));
771 readl(mmio + (seq * 4)); /* flush */
774 wmb(); /* flush PRD, pkt writes */
775 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
776 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
779 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
781 switch (qc->tf.protocol) {
782 case ATA_PROT_ATAPI_NODATA:
783 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
786 case ATA_PROT_ATAPI_DMA:
788 case ATA_PROT_NODATA:
789 pdc_packet_start(qc);
796 return ata_qc_issue_prot(qc);
799 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
801 WARN_ON (tf->protocol == ATA_PROT_DMA ||
802 tf->protocol == ATA_PROT_NODATA);
807 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
809 WARN_ON (tf->protocol == ATA_PROT_DMA ||
810 tf->protocol == ATA_PROT_NODATA);
811 ata_exec_command(ap, tf);
814 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
816 u8 *scsicmd = qc->scsicmd->cmnd;
817 int pio = 1; /* atapi dma off by default */
819 /* Whitelist commands that may use DMA. */
820 switch (scsicmd[0]) {
827 case 0xad: /* READ_DVD_STRUCTURE */
828 case 0xbe: /* READ_CD */
831 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
832 if (scsicmd[0] == WRITE_10) {
834 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
835 if (lba >= 0xFFFF4FA2)
841 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
843 /* First generation chips cannot use ATAPI DMA on SATA ports */
847 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base,
848 void __iomem *scr_addr)
850 port->cmd_addr = base;
851 port->data_addr = base;
853 port->error_addr = base + 0x4;
854 port->nsect_addr = base + 0x8;
855 port->lbal_addr = base + 0xc;
856 port->lbam_addr = base + 0x10;
857 port->lbah_addr = base + 0x14;
858 port->device_addr = base + 0x18;
860 port->status_addr = base + 0x1c;
861 port->altstatus_addr =
862 port->ctl_addr = base + 0x38;
863 port->scr_addr = scr_addr;
867 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
869 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
870 struct pdc_host_priv *hp = pe->private_data;
874 if (hp->flags & PDC_FLAG_GEN_II)
875 hotplug_offset = PDC2_SATA_PLUG_CSR;
877 hotplug_offset = PDC_SATA_PLUG_CSR;
880 * Except for the hotplug stuff, this is voodoo from the
881 * Promise driver. Label this entire section
882 * "TODO: figure out why we do this"
885 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
886 tmp = readl(mmio + PDC_FLASH_CTL);
887 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
888 if (!(hp->flags & PDC_FLAG_GEN_II))
889 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
890 writel(tmp, mmio + PDC_FLASH_CTL);
892 /* clear plug/unplug flags for all ports */
893 tmp = readl(mmio + hotplug_offset);
894 writel(tmp | 0xff, mmio + hotplug_offset);
896 /* mask plug/unplug ints */
897 tmp = readl(mmio + hotplug_offset);
898 writel(tmp | 0xff0000, mmio + hotplug_offset);
900 /* don't initialise TBG or SLEW on 2nd generation chips */
901 if (hp->flags & PDC_FLAG_GEN_II)
904 /* reduce TBG clock to 133 Mhz. */
905 tmp = readl(mmio + PDC_TBG_MODE);
906 tmp &= ~0x30000; /* clear bit 17, 16*/
907 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
908 writel(tmp, mmio + PDC_TBG_MODE);
910 readl(mmio + PDC_TBG_MODE); /* flush */
913 /* adjust slew rate control register. */
914 tmp = readl(mmio + PDC_SLEW_CTL);
915 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
916 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
917 writel(tmp, mmio + PDC_SLEW_CTL);
920 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
922 static int printed_version;
923 struct ata_probe_ent *probe_ent;
924 struct pdc_host_priv *hp;
926 unsigned int board_idx = (unsigned int) ent->driver_data;
930 if (!printed_version++)
931 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
933 rc = pcim_enable_device(pdev);
937 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
939 pcim_pin_device(pdev);
943 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
946 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
950 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
951 if (probe_ent == NULL)
954 probe_ent->dev = pci_dev_to_dev(pdev);
955 INIT_LIST_HEAD(&probe_ent->node);
957 hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL);
961 probe_ent->private_data = hp;
963 probe_ent->sht = pdc_port_info[board_idx].sht;
964 probe_ent->port_flags = pdc_port_info[board_idx].flags;
965 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
966 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
967 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
968 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
970 probe_ent->irq = pdev->irq;
971 probe_ent->irq_flags = IRQF_SHARED;
972 probe_ent->iomap = pcim_iomap_table(pdev);
974 base = probe_ent->iomap[PDC_MMIO_BAR];
976 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200, base + 0x400);
977 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280, base + 0x500);
979 /* notice 4-port boards */
982 hp->flags |= PDC_FLAG_GEN_II;
985 probe_ent->n_ports = 4;
986 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, base + 0x600);
987 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, base + 0x700);
990 hp->flags |= PDC_FLAG_GEN_II;
993 /* TX2plus boards also have a PATA port */
994 tmp = readb(base + PDC_FLASH_CTL+1);
996 probe_ent->n_ports = 3;
997 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
998 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
999 printk(KERN_INFO DRV_NAME " PATA port found\n");
1001 probe_ent->n_ports = 2;
1002 hp->port_flags[0] = ATA_FLAG_SATA;
1003 hp->port_flags[1] = ATA_FLAG_SATA;
1006 probe_ent->n_ports = 4;
1007 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
1008 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, NULL);
1015 pci_set_master(pdev);
1017 /* initialize adapter */
1018 pdc_host_init(board_idx, probe_ent);
1020 if (!ata_device_add(probe_ent))
1023 devm_kfree(&pdev->dev, probe_ent);
1028 static int __init pdc_ata_init(void)
1030 return pci_register_driver(&pdc_ata_pci_driver);
1034 static void __exit pdc_ata_exit(void)
1036 pci_unregister_driver(&pdc_ata_pci_driver);
1040 MODULE_AUTHOR("Jeff Garzik");
1041 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1042 MODULE_LICENSE("GPL");
1043 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1044 MODULE_VERSION(DRV_VERSION);
1046 module_init(pdc_ata_init);
1047 module_exit(pdc_ata_exit);