2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 * --> Develop a low-power-consumption strategy, and implement it.
33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
44 * 80x1-B2 errata PCI#11:
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
52 #include <linux/kernel.h>
53 #include <linux/module.h>
54 #include <linux/pci.h>
55 #include <linux/init.h>
56 #include <linux/blkdev.h>
57 #include <linux/delay.h>
58 #include <linux/interrupt.h>
59 #include <linux/dmapool.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/device.h>
62 #include <linux/platform_device.h>
63 #include <linux/ata_platform.h>
64 #include <linux/mbus.h>
65 #include <linux/bitops.h>
66 #include <scsi/scsi_host.h>
67 #include <scsi/scsi_cmnd.h>
68 #include <scsi/scsi_device.h>
69 #include <linux/libata.h>
71 #define DRV_NAME "sata_mv"
72 #define DRV_VERSION "1.27"
80 module_param(msi, int, S_IRUGO);
81 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
84 static int irq_coalescing_io_count;
85 module_param(irq_coalescing_io_count, int, S_IRUGO);
86 MODULE_PARM_DESC(irq_coalescing_io_count,
87 "IRQ coalescing I/O count threshold (0..255)");
89 static int irq_coalescing_usecs;
90 module_param(irq_coalescing_usecs, int, S_IRUGO);
91 MODULE_PARM_DESC(irq_coalescing_usecs,
92 "IRQ coalescing time threshold in usecs");
95 /* BAR's are enumerated in terms of pci_resource_start() terms */
96 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
97 MV_IO_BAR = 2, /* offset 0x18: IO space */
98 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
100 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
101 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
103 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
104 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
105 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
106 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
111 * Per-chip ("all ports") interrupt coalescing feature.
112 * This is only for GEN_II / GEN_IIE hardware.
114 * Coalescing defers the interrupt until either the IO_THRESHOLD
115 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
117 MV_COAL_REG_BASE = 0x18000,
118 MV_IRQ_COAL_CAUSE = (MV_COAL_REG_BASE + 0x08),
119 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
121 MV_IRQ_COAL_IO_THRESHOLD = (MV_COAL_REG_BASE + 0xcc),
122 MV_IRQ_COAL_TIME_THRESHOLD = (MV_COAL_REG_BASE + 0xd0),
125 * Registers for the (unused here) transaction coalescing feature:
127 MV_TRAN_COAL_CAUSE_LO = (MV_COAL_REG_BASE + 0x88),
128 MV_TRAN_COAL_CAUSE_HI = (MV_COAL_REG_BASE + 0x8c),
130 MV_SATAHC0_REG_BASE = 0x20000,
131 MV_FLASH_CTL_OFS = 0x1046c,
132 MV_GPIO_PORT_CTL_OFS = 0x104f0,
133 MV_RESET_CFG_OFS = 0x180d8,
135 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
136 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
137 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
138 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
141 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
143 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
144 * CRPB needs alignment on a 256B boundary. Size == 256B
145 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
147 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
148 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
150 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
152 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
153 MV_PORT_HC_SHIFT = 2,
154 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
155 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
156 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
159 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
161 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
162 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
164 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
166 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
167 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
169 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
171 CRQB_FLAG_READ = (1 << 0),
173 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
174 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
175 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
176 CRQB_CMD_ADDR_SHIFT = 8,
177 CRQB_CMD_CS = (0x2 << 11),
178 CRQB_CMD_LAST = (1 << 15),
180 CRPB_FLAG_STATUS_SHIFT = 8,
181 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
182 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
184 EPRD_FLAG_END_OF_TBL = (1 << 31),
186 /* PCI interface registers */
188 PCI_COMMAND_OFS = 0xc00,
189 PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
190 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
192 PCI_MAIN_CMD_STS_OFS = 0xd30,
193 STOP_PCI_MASTER = (1 << 2),
194 PCI_MASTER_EMPTY = (1 << 3),
195 GLOB_SFT_RST = (1 << 4),
197 MV_PCI_MODE_OFS = 0xd00,
198 MV_PCI_MODE_MASK = 0x30,
200 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
201 MV_PCI_DISC_TIMER = 0xd04,
202 MV_PCI_MSI_TRIGGER = 0xc38,
203 MV_PCI_SERR_MASK = 0xc28,
204 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
205 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
206 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
207 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
208 MV_PCI_ERR_COMMAND = 0x1d50,
210 PCI_IRQ_CAUSE_OFS = 0x1d58,
211 PCI_IRQ_MASK_OFS = 0x1d5c,
212 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
214 PCIE_IRQ_CAUSE_OFS = 0x1900,
215 PCIE_IRQ_MASK_OFS = 0x1910,
216 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
218 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
219 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
220 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
221 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
222 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
223 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
224 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
225 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
226 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
227 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
228 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
230 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
231 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
232 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
233 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
234 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
235 GPIO_INT = (1 << 22),
236 SELF_INT = (1 << 23),
237 TWSI_INT = (1 << 24),
238 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
239 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
240 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
242 /* SATAHC registers */
245 HC_IRQ_CAUSE_OFS = 0x14,
246 DMA_IRQ = (1 << 0), /* shift by port # */
247 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
248 DEV_IRQ = (1 << 8), /* shift by port # */
251 * Per-HC (Host-Controller) interrupt coalescing feature.
252 * This is present on all chip generations.
254 * Coalescing defers the interrupt until either the IO_THRESHOLD
255 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
257 HC_IRQ_COAL_IO_THRESHOLD_OFS = 0x000c,
258 HC_IRQ_COAL_TIME_THRESHOLD_OFS = 0x0010,
260 SOC_LED_CTRL_OFS = 0x2c,
261 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
262 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
263 /* with dev activity LED */
265 /* Shadow block registers */
267 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
270 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
271 SATA_ACTIVE_OFS = 0x350,
272 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
273 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
275 LTMODE_OFS = 0x30c, /* requires read-after-write */
276 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
278 PHY_MODE2_OFS = 0x330,
279 PHY_MODE3_OFS = 0x310,
280 PHY_MODE4_OFS = 0x314, /* requires read-after-write */
281 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
282 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
283 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
284 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
286 SATA_IFCTL_OFS = 0x344,
287 SATA_TESTCTL_OFS = 0x348,
288 SATA_IFSTAT_OFS = 0x34c,
289 VENDOR_UNIQUE_FIS_OFS = 0x35c,
292 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
293 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
296 MV5_LTMODE_OFS = 0x30,
297 MV5_PHY_CTL_OFS = 0x0C,
298 SATA_INTERFACE_CFG_OFS = 0x050,
300 MV_M2_PREAMP_MASK = 0x7e0,
304 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
305 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
306 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
307 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
308 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
309 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
310 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
312 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
313 EDMA_ERR_IRQ_MASK_OFS = 0xc,
314 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
315 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
316 EDMA_ERR_DEV = (1 << 2), /* device error */
317 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
318 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
319 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
320 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
321 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
322 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
323 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
324 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
325 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
326 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
327 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
329 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
330 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
331 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
332 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
333 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
335 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
337 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
338 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
339 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
340 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
341 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
342 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
344 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
346 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
347 EDMA_ERR_OVERRUN_5 = (1 << 5),
348 EDMA_ERR_UNDERRUN_5 = (1 << 6),
350 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
351 EDMA_ERR_LNK_CTRL_RX_1 |
352 EDMA_ERR_LNK_CTRL_RX_3 |
353 EDMA_ERR_LNK_CTRL_TX,
355 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
365 EDMA_ERR_LNK_CTRL_RX_2 |
366 EDMA_ERR_LNK_DATA_RX |
367 EDMA_ERR_LNK_DATA_TX |
368 EDMA_ERR_TRANS_PROTO,
370 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
375 EDMA_ERR_UNDERRUN_5 |
376 EDMA_ERR_SELF_DIS_5 |
382 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
383 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
385 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
386 EDMA_REQ_Q_PTR_SHIFT = 5,
388 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
389 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
390 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
391 EDMA_RSP_Q_PTR_SHIFT = 3,
393 EDMA_CMD_OFS = 0x28, /* EDMA command register */
394 EDMA_EN = (1 << 0), /* enable EDMA */
395 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
396 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
398 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
399 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
400 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
402 EDMA_IORDY_TMOUT_OFS = 0x34,
403 EDMA_ARB_CFG_OFS = 0x38,
405 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
406 EDMA_UNKNOWN_RSVD_OFS = 0x6C, /* GenIIe unknown/reserved */
408 BMDMA_CMD_OFS = 0x224, /* bmdma command register */
409 BMDMA_STATUS_OFS = 0x228, /* bmdma status register */
410 BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */
411 BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */
413 /* Host private flags (hp_flags) */
414 MV_HP_FLAG_MSI = (1 << 0),
415 MV_HP_ERRATA_50XXB0 = (1 << 1),
416 MV_HP_ERRATA_50XXB2 = (1 << 2),
417 MV_HP_ERRATA_60X1B2 = (1 << 3),
418 MV_HP_ERRATA_60X1C0 = (1 << 4),
419 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
420 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
421 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
422 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
423 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
424 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
425 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
427 /* Port private flags (pp_flags) */
428 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
429 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
430 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
431 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
432 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
435 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
436 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
437 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
438 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
439 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
441 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
442 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
445 /* DMA boundary 0xffff is required by the s/g splitting
446 * we need on /length/ in mv_fill-sg().
448 MV_DMA_BOUNDARY = 0xffffU,
450 /* mask of register bits containing lower 32 bits
451 * of EDMA request queue DMA address
453 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
455 /* ditto, for response queue */
456 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
470 /* Command ReQuest Block: 32B */
486 /* Command ResPonse Block: 8B */
493 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
502 * We keep a local cache of a few frequently accessed port
503 * registers here, to avoid having to read them (very slow)
504 * when switching between EDMA and non-EDMA modes.
506 struct mv_cached_regs {
513 struct mv_port_priv {
514 struct mv_crqb *crqb;
516 struct mv_crpb *crpb;
518 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
519 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
521 unsigned int req_idx;
522 unsigned int resp_idx;
525 struct mv_cached_regs cached;
526 unsigned int delayed_eh_pmp_map;
529 struct mv_port_signal {
534 struct mv_host_priv {
537 struct mv_port_signal signal[8];
538 const struct mv_hw_ops *ops;
541 void __iomem *main_irq_cause_addr;
542 void __iomem *main_irq_mask_addr;
547 * These consistent DMA memory pools give us guaranteed
548 * alignment for hardware-accessed data structures,
549 * and less memory waste in accomplishing the alignment.
551 struct dma_pool *crqb_pool;
552 struct dma_pool *crpb_pool;
553 struct dma_pool *sg_tbl_pool;
557 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
559 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
560 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
562 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
564 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
565 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
568 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
569 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
570 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
571 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
572 static int mv_port_start(struct ata_port *ap);
573 static void mv_port_stop(struct ata_port *ap);
574 static int mv_qc_defer(struct ata_queued_cmd *qc);
575 static void mv_qc_prep(struct ata_queued_cmd *qc);
576 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
577 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
578 static int mv_hardreset(struct ata_link *link, unsigned int *class,
579 unsigned long deadline);
580 static void mv_eh_freeze(struct ata_port *ap);
581 static void mv_eh_thaw(struct ata_port *ap);
582 static void mv6_dev_config(struct ata_device *dev);
584 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
586 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
587 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
589 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
591 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
592 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
594 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
596 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
597 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
599 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
601 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
602 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
604 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
606 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
607 void __iomem *mmio, unsigned int n_hc);
608 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
610 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
611 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
612 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
613 unsigned int port_no);
614 static int mv_stop_edma(struct ata_port *ap);
615 static int mv_stop_edma_engine(void __iomem *port_mmio);
616 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
618 static void mv_pmp_select(struct ata_port *ap, int pmp);
619 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
620 unsigned long deadline);
621 static int mv_softreset(struct ata_link *link, unsigned int *class,
622 unsigned long deadline);
623 static void mv_pmp_error_handler(struct ata_port *ap);
624 static void mv_process_crpb_entries(struct ata_port *ap,
625 struct mv_port_priv *pp);
627 static void mv_sff_irq_clear(struct ata_port *ap);
628 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
629 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
630 static void mv_bmdma_start(struct ata_queued_cmd *qc);
631 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
632 static u8 mv_bmdma_status(struct ata_port *ap);
633 static u8 mv_sff_check_status(struct ata_port *ap);
635 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
636 * because we have to allow room for worst case splitting of
637 * PRDs for 64K boundaries in mv_fill_sg().
639 static struct scsi_host_template mv5_sht = {
640 ATA_BASE_SHT(DRV_NAME),
641 .sg_tablesize = MV_MAX_SG_CT / 2,
642 .dma_boundary = MV_DMA_BOUNDARY,
645 static struct scsi_host_template mv6_sht = {
646 ATA_NCQ_SHT(DRV_NAME),
647 .can_queue = MV_MAX_Q_DEPTH - 1,
648 .sg_tablesize = MV_MAX_SG_CT / 2,
649 .dma_boundary = MV_DMA_BOUNDARY,
652 static struct ata_port_operations mv5_ops = {
653 .inherits = &ata_sff_port_ops,
655 .lost_interrupt = ATA_OP_NULL,
657 .qc_defer = mv_qc_defer,
658 .qc_prep = mv_qc_prep,
659 .qc_issue = mv_qc_issue,
661 .freeze = mv_eh_freeze,
663 .hardreset = mv_hardreset,
664 .error_handler = ata_std_error_handler, /* avoid SFF EH */
665 .post_internal_cmd = ATA_OP_NULL,
667 .scr_read = mv5_scr_read,
668 .scr_write = mv5_scr_write,
670 .port_start = mv_port_start,
671 .port_stop = mv_port_stop,
674 static struct ata_port_operations mv6_ops = {
675 .inherits = &mv5_ops,
676 .dev_config = mv6_dev_config,
677 .scr_read = mv_scr_read,
678 .scr_write = mv_scr_write,
680 .pmp_hardreset = mv_pmp_hardreset,
681 .pmp_softreset = mv_softreset,
682 .softreset = mv_softreset,
683 .error_handler = mv_pmp_error_handler,
685 .sff_check_status = mv_sff_check_status,
686 .sff_irq_clear = mv_sff_irq_clear,
687 .check_atapi_dma = mv_check_atapi_dma,
688 .bmdma_setup = mv_bmdma_setup,
689 .bmdma_start = mv_bmdma_start,
690 .bmdma_stop = mv_bmdma_stop,
691 .bmdma_status = mv_bmdma_status,
694 static struct ata_port_operations mv_iie_ops = {
695 .inherits = &mv6_ops,
696 .dev_config = ATA_OP_NULL,
697 .qc_prep = mv_qc_prep_iie,
700 static const struct ata_port_info mv_port_info[] = {
702 .flags = MV_GEN_I_FLAGS,
703 .pio_mask = ATA_PIO4,
704 .udma_mask = ATA_UDMA6,
705 .port_ops = &mv5_ops,
708 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
709 .pio_mask = ATA_PIO4,
710 .udma_mask = ATA_UDMA6,
711 .port_ops = &mv5_ops,
714 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
715 .pio_mask = ATA_PIO4,
716 .udma_mask = ATA_UDMA6,
717 .port_ops = &mv5_ops,
720 .flags = MV_GEN_II_FLAGS,
721 .pio_mask = ATA_PIO4,
722 .udma_mask = ATA_UDMA6,
723 .port_ops = &mv6_ops,
726 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
727 .pio_mask = ATA_PIO4,
728 .udma_mask = ATA_UDMA6,
729 .port_ops = &mv6_ops,
732 .flags = MV_GEN_IIE_FLAGS,
733 .pio_mask = ATA_PIO4,
734 .udma_mask = ATA_UDMA6,
735 .port_ops = &mv_iie_ops,
738 .flags = MV_GEN_IIE_FLAGS,
739 .pio_mask = ATA_PIO4,
740 .udma_mask = ATA_UDMA6,
741 .port_ops = &mv_iie_ops,
744 .flags = MV_GEN_IIE_FLAGS,
745 .pio_mask = ATA_PIO4,
746 .udma_mask = ATA_UDMA6,
747 .port_ops = &mv_iie_ops,
751 static const struct pci_device_id mv_pci_tbl[] = {
752 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
753 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
754 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
755 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
756 /* RocketRAID 1720/174x have different identifiers */
757 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
758 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
759 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
761 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
762 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
763 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
764 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
765 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
767 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
770 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
772 /* Marvell 7042 support */
773 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
775 /* Highpoint RocketRAID PCIe series */
776 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
777 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
779 { } /* terminate list */
782 static const struct mv_hw_ops mv5xxx_ops = {
783 .phy_errata = mv5_phy_errata,
784 .enable_leds = mv5_enable_leds,
785 .read_preamp = mv5_read_preamp,
786 .reset_hc = mv5_reset_hc,
787 .reset_flash = mv5_reset_flash,
788 .reset_bus = mv5_reset_bus,
791 static const struct mv_hw_ops mv6xxx_ops = {
792 .phy_errata = mv6_phy_errata,
793 .enable_leds = mv6_enable_leds,
794 .read_preamp = mv6_read_preamp,
795 .reset_hc = mv6_reset_hc,
796 .reset_flash = mv6_reset_flash,
797 .reset_bus = mv_reset_pci_bus,
800 static const struct mv_hw_ops mv_soc_ops = {
801 .phy_errata = mv6_phy_errata,
802 .enable_leds = mv_soc_enable_leds,
803 .read_preamp = mv_soc_read_preamp,
804 .reset_hc = mv_soc_reset_hc,
805 .reset_flash = mv_soc_reset_flash,
806 .reset_bus = mv_soc_reset_bus,
813 static inline void writelfl(unsigned long data, void __iomem *addr)
816 (void) readl(addr); /* flush to avoid PCI posted write */
819 static inline unsigned int mv_hc_from_port(unsigned int port)
821 return port >> MV_PORT_HC_SHIFT;
824 static inline unsigned int mv_hardport_from_port(unsigned int port)
826 return port & MV_PORT_MASK;
830 * Consolidate some rather tricky bit shift calculations.
831 * This is hot-path stuff, so not a function.
832 * Simple code, with two return values, so macro rather than inline.
834 * port is the sole input, in range 0..7.
835 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
836 * hardport is the other output, in range 0..3.
838 * Note that port and hardport may be the same variable in some cases.
840 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
842 shift = mv_hc_from_port(port) * HC_SHIFT; \
843 hardport = mv_hardport_from_port(port); \
844 shift += hardport * 2; \
847 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
849 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
852 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
855 return mv_hc_base(base, mv_hc_from_port(port));
858 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
860 return mv_hc_base_from_port(base, port) +
861 MV_SATAHC_ARBTR_REG_SZ +
862 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
865 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
867 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
868 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
870 return hc_mmio + ofs;
873 static inline void __iomem *mv_host_base(struct ata_host *host)
875 struct mv_host_priv *hpriv = host->private_data;
879 static inline void __iomem *mv_ap_base(struct ata_port *ap)
881 return mv_port_base(mv_host_base(ap->host), ap->port_no);
884 static inline int mv_get_hc_count(unsigned long port_flags)
886 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
890 * mv_save_cached_regs - (re-)initialize cached port registers
891 * @ap: the port whose registers we are caching
893 * Initialize the local cache of port registers,
894 * so that reading them over and over again can
895 * be avoided on the hotter paths of this driver.
896 * This saves a few microseconds each time we switch
897 * to/from EDMA mode to perform (eg.) a drive cache flush.
899 static void mv_save_cached_regs(struct ata_port *ap)
901 void __iomem *port_mmio = mv_ap_base(ap);
902 struct mv_port_priv *pp = ap->private_data;
904 pp->cached.fiscfg = readl(port_mmio + FISCFG_OFS);
905 pp->cached.ltmode = readl(port_mmio + LTMODE_OFS);
906 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
907 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD_OFS);
911 * mv_write_cached_reg - write to a cached port register
912 * @addr: hardware address of the register
913 * @old: pointer to cached value of the register
914 * @new: new value for the register
916 * Write a new value to a cached register,
917 * but only if the value is different from before.
919 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
925 * Workaround for 88SX60x1-B2 FEr SATA#13:
926 * Read-after-write is needed to prevent generating 64-bit
927 * write cycles on the PCI bus for SATA interface registers
928 * at offsets ending in 0x4 or 0xc.
930 * Looks like a lot of fuss, but it avoids an unnecessary
931 * +1 usec read-after-write delay for unaffected registers.
933 laddr = (long)addr & 0xffff;
934 if (laddr >= 0x300 && laddr <= 0x33c) {
936 if (laddr == 0x4 || laddr == 0xc) {
937 writelfl(new, addr); /* read after write */
941 writel(new, addr); /* unaffected by the errata */
945 static void mv_set_edma_ptrs(void __iomem *port_mmio,
946 struct mv_host_priv *hpriv,
947 struct mv_port_priv *pp)
952 * initialize request queue
954 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
955 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
957 WARN_ON(pp->crqb_dma & 0x3ff);
958 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
959 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
960 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
961 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
964 * initialize response queue
966 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
967 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
969 WARN_ON(pp->crpb_dma & 0xff);
970 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
971 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
972 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
973 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
976 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
979 * When writing to the main_irq_mask in hardware,
980 * we must ensure exclusivity between the interrupt coalescing bits
981 * and the corresponding individual port DONE_IRQ bits.
983 * Note that this register is really an "IRQ enable" register,
984 * not an "IRQ mask" register as Marvell's naming might suggest.
986 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
987 mask &= ~DONE_IRQ_0_3;
988 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
989 mask &= ~DONE_IRQ_4_7;
990 writelfl(mask, hpriv->main_irq_mask_addr);
993 static void mv_set_main_irq_mask(struct ata_host *host,
994 u32 disable_bits, u32 enable_bits)
996 struct mv_host_priv *hpriv = host->private_data;
997 u32 old_mask, new_mask;
999 old_mask = hpriv->main_irq_mask;
1000 new_mask = (old_mask & ~disable_bits) | enable_bits;
1001 if (new_mask != old_mask) {
1002 hpriv->main_irq_mask = new_mask;
1003 mv_write_main_irq_mask(new_mask, hpriv);
1007 static void mv_enable_port_irqs(struct ata_port *ap,
1008 unsigned int port_bits)
1010 unsigned int shift, hardport, port = ap->port_no;
1011 u32 disable_bits, enable_bits;
1013 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1015 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1016 enable_bits = port_bits << shift;
1017 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1020 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1021 void __iomem *port_mmio,
1022 unsigned int port_irqs)
1024 struct mv_host_priv *hpriv = ap->host->private_data;
1025 int hardport = mv_hardport_from_port(ap->port_no);
1026 void __iomem *hc_mmio = mv_hc_base_from_port(
1027 mv_host_base(ap->host), ap->port_no);
1030 /* clear EDMA event indicators, if any */
1031 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1033 /* clear pending irq events */
1034 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1035 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1037 /* clear FIS IRQ Cause */
1038 if (IS_GEN_IIE(hpriv))
1039 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1041 mv_enable_port_irqs(ap, port_irqs);
1044 static void mv_set_irq_coalescing(struct ata_host *host,
1045 unsigned int count, unsigned int usecs)
1047 struct mv_host_priv *hpriv = host->private_data;
1048 void __iomem *mmio = hpriv->base, *hc_mmio;
1049 u32 coal_enable = 0;
1050 unsigned long flags;
1051 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1052 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1053 ALL_PORTS_COAL_DONE;
1055 /* Disable IRQ coalescing if either threshold is zero */
1056 if (!usecs || !count) {
1059 /* Respect maximum limits of the hardware */
1060 clks = usecs * COAL_CLOCKS_PER_USEC;
1061 if (clks > MAX_COAL_TIME_THRESHOLD)
1062 clks = MAX_COAL_TIME_THRESHOLD;
1063 if (count > MAX_COAL_IO_COUNT)
1064 count = MAX_COAL_IO_COUNT;
1067 spin_lock_irqsave(&host->lock, flags);
1068 mv_set_main_irq_mask(host, coal_disable, 0);
1070 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1072 * GEN_II/GEN_IIE with dual host controllers:
1073 * one set of global thresholds for the entire chip.
1075 writel(clks, mmio + MV_IRQ_COAL_TIME_THRESHOLD);
1076 writel(count, mmio + MV_IRQ_COAL_IO_THRESHOLD);
1077 /* clear leftover coal IRQ bit */
1078 writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE);
1080 coal_enable = ALL_PORTS_COAL_DONE;
1081 clks = count = 0; /* force clearing of regular regs below */
1085 * All chips: independent thresholds for each HC on the chip.
1087 hc_mmio = mv_hc_base_from_port(mmio, 0);
1088 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS);
1089 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS);
1090 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS);
1092 coal_enable |= PORTS_0_3_COAL_DONE;
1094 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1095 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS);
1096 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS);
1097 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS);
1099 coal_enable |= PORTS_4_7_COAL_DONE;
1102 mv_set_main_irq_mask(host, 0, coal_enable);
1103 spin_unlock_irqrestore(&host->lock, flags);
1107 * mv_start_edma - Enable eDMA engine
1108 * @base: port base address
1109 * @pp: port private data
1111 * Verify the local cache of the eDMA state is accurate with a
1115 * Inherited from caller.
1117 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
1118 struct mv_port_priv *pp, u8 protocol)
1120 int want_ncq = (protocol == ATA_PROT_NCQ);
1122 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1123 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1124 if (want_ncq != using_ncq)
1127 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1128 struct mv_host_priv *hpriv = ap->host->private_data;
1130 mv_edma_cfg(ap, want_ncq, 1);
1132 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1133 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
1135 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
1136 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1140 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1142 void __iomem *port_mmio = mv_ap_base(ap);
1143 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1144 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1148 * Wait for the EDMA engine to finish transactions in progress.
1149 * No idea what a good "timeout" value might be, but measurements
1150 * indicate that it often requires hundreds of microseconds
1151 * with two drives in-use. So we use the 15msec value above
1152 * as a rough guess at what even more drives might require.
1154 for (i = 0; i < timeout; ++i) {
1155 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
1156 if ((edma_stat & empty_idle) == empty_idle)
1160 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1164 * mv_stop_edma_engine - Disable eDMA engine
1165 * @port_mmio: io base address
1168 * Inherited from caller.
1170 static int mv_stop_edma_engine(void __iomem *port_mmio)
1174 /* Disable eDMA. The disable bit auto clears. */
1175 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1177 /* Wait for the chip to confirm eDMA is off. */
1178 for (i = 10000; i > 0; i--) {
1179 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
1180 if (!(reg & EDMA_EN))
1187 static int mv_stop_edma(struct ata_port *ap)
1189 void __iomem *port_mmio = mv_ap_base(ap);
1190 struct mv_port_priv *pp = ap->private_data;
1193 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1195 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1196 mv_wait_for_edma_empty_idle(ap);
1197 if (mv_stop_edma_engine(port_mmio)) {
1198 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
1201 mv_edma_cfg(ap, 0, 0);
1206 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1209 for (b = 0; b < bytes; ) {
1210 DPRINTK("%p: ", start + b);
1211 for (w = 0; b < bytes && w < 4; w++) {
1212 printk("%08x ", readl(start + b));
1220 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1225 for (b = 0; b < bytes; ) {
1226 DPRINTK("%02x: ", b);
1227 for (w = 0; b < bytes && w < 4; w++) {
1228 (void) pci_read_config_dword(pdev, b, &dw);
1229 printk("%08x ", dw);
1236 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1237 struct pci_dev *pdev)
1240 void __iomem *hc_base = mv_hc_base(mmio_base,
1241 port >> MV_PORT_HC_SHIFT);
1242 void __iomem *port_base;
1243 int start_port, num_ports, p, start_hc, num_hcs, hc;
1246 start_hc = start_port = 0;
1247 num_ports = 8; /* shld be benign for 4 port devs */
1250 start_hc = port >> MV_PORT_HC_SHIFT;
1252 num_ports = num_hcs = 1;
1254 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1255 num_ports > 1 ? num_ports - 1 : start_port);
1258 DPRINTK("PCI config space regs:\n");
1259 mv_dump_pci_cfg(pdev, 0x68);
1261 DPRINTK("PCI regs:\n");
1262 mv_dump_mem(mmio_base+0xc00, 0x3c);
1263 mv_dump_mem(mmio_base+0xd00, 0x34);
1264 mv_dump_mem(mmio_base+0xf00, 0x4);
1265 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1266 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1267 hc_base = mv_hc_base(mmio_base, hc);
1268 DPRINTK("HC regs (HC %i):\n", hc);
1269 mv_dump_mem(hc_base, 0x1c);
1271 for (p = start_port; p < start_port + num_ports; p++) {
1272 port_base = mv_port_base(mmio_base, p);
1273 DPRINTK("EDMA regs (port %i):\n", p);
1274 mv_dump_mem(port_base, 0x54);
1275 DPRINTK("SATA regs (port %i):\n", p);
1276 mv_dump_mem(port_base+0x300, 0x60);
1281 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1285 switch (sc_reg_in) {
1289 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1292 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1301 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1303 unsigned int ofs = mv_scr_offset(sc_reg_in);
1305 if (ofs != 0xffffffffU) {
1306 *val = readl(mv_ap_base(link->ap) + ofs);
1312 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1314 unsigned int ofs = mv_scr_offset(sc_reg_in);
1316 if (ofs != 0xffffffffU) {
1317 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1318 if (sc_reg_in == SCR_CONTROL) {
1320 * Workaround for 88SX60x1 FEr SATA#26:
1322 * COMRESETs have to take care not to accidently
1323 * put the drive to sleep when writing SCR_CONTROL.
1324 * Setting bits 12..15 prevents this problem.
1326 * So if we see an outbound COMMRESET, set those bits.
1327 * Ditto for the followup write that clears the reset.
1329 * The proprietary driver does this for
1330 * all chip versions, and so do we.
1332 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1335 writelfl(val, addr);
1341 static void mv6_dev_config(struct ata_device *adev)
1344 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1346 * Gen-II does not support NCQ over a port multiplier
1347 * (no FIS-based switching).
1349 if (adev->flags & ATA_DFLAG_NCQ) {
1350 if (sata_pmp_attached(adev->link->ap)) {
1351 adev->flags &= ~ATA_DFLAG_NCQ;
1352 ata_dev_printk(adev, KERN_INFO,
1353 "NCQ disabled for command-based switching\n");
1358 static int mv_qc_defer(struct ata_queued_cmd *qc)
1360 struct ata_link *link = qc->dev->link;
1361 struct ata_port *ap = link->ap;
1362 struct mv_port_priv *pp = ap->private_data;
1365 * Don't allow new commands if we're in a delayed EH state
1366 * for NCQ and/or FIS-based switching.
1368 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1369 return ATA_DEFER_PORT;
1371 * If the port is completely idle, then allow the new qc.
1373 if (ap->nr_active_links == 0)
1377 * The port is operating in host queuing mode (EDMA) with NCQ
1378 * enabled, allow multiple NCQ commands. EDMA also allows
1379 * queueing multiple DMA commands but libata core currently
1382 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1383 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1386 return ATA_DEFER_PORT;
1389 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1391 struct mv_port_priv *pp = ap->private_data;
1392 void __iomem *port_mmio;
1394 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1395 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1396 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1398 ltmode = *old_ltmode & ~LTMODE_BIT8;
1399 haltcond = *old_haltcond | EDMA_ERR_DEV;
1402 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1403 ltmode = *old_ltmode | LTMODE_BIT8;
1405 haltcond &= ~EDMA_ERR_DEV;
1407 fiscfg |= FISCFG_WAIT_DEV_ERR;
1409 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1412 port_mmio = mv_ap_base(ap);
1413 mv_write_cached_reg(port_mmio + FISCFG_OFS, old_fiscfg, fiscfg);
1414 mv_write_cached_reg(port_mmio + LTMODE_OFS, old_ltmode, ltmode);
1415 mv_write_cached_reg(port_mmio + EDMA_HALTCOND_OFS, old_haltcond, haltcond);
1418 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1420 struct mv_host_priv *hpriv = ap->host->private_data;
1423 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1424 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1426 new = old | (1 << 22);
1428 new = old & ~(1 << 22);
1430 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1434 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1435 * @ap: Port being initialized
1437 * There are two DMA modes on these chips: basic DMA, and EDMA.
1439 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1440 * of basic DMA on the GEN_IIE versions of the chips.
1442 * This bit survives EDMA resets, and must be set for basic DMA
1443 * to function, and should be cleared when EDMA is active.
1445 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1447 struct mv_port_priv *pp = ap->private_data;
1448 u32 new, *old = &pp->cached.unknown_rsvd;
1454 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD_OFS, old, new);
1458 * SOC chips have an issue whereby the HDD LEDs don't always blink
1459 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1460 * of the SOC takes care of it, generating a steady blink rate when
1461 * any drive on the chip is active.
1463 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1464 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1466 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1467 * LED operation works then, and provides better (more accurate) feedback.
1469 * Note that this code assumes that an SOC never has more than one HC onboard.
1471 static void mv_soc_led_blink_enable(struct ata_port *ap)
1473 struct ata_host *host = ap->host;
1474 struct mv_host_priv *hpriv = host->private_data;
1475 void __iomem *hc_mmio;
1478 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1480 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1481 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1482 led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS);
1483 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS);
1486 static void mv_soc_led_blink_disable(struct ata_port *ap)
1488 struct ata_host *host = ap->host;
1489 struct mv_host_priv *hpriv = host->private_data;
1490 void __iomem *hc_mmio;
1494 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1497 /* disable led-blink only if no ports are using NCQ */
1498 for (port = 0; port < hpriv->n_ports; port++) {
1499 struct ata_port *this_ap = host->ports[port];
1500 struct mv_port_priv *pp = this_ap->private_data;
1502 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1506 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1507 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1508 led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS);
1509 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS);
1512 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1515 struct mv_port_priv *pp = ap->private_data;
1516 struct mv_host_priv *hpriv = ap->host->private_data;
1517 void __iomem *port_mmio = mv_ap_base(ap);
1519 /* set up non-NCQ EDMA configuration */
1520 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1522 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
1524 if (IS_GEN_I(hpriv))
1525 cfg |= (1 << 8); /* enab config burst size mask */
1527 else if (IS_GEN_II(hpriv)) {
1528 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1529 mv_60x1_errata_sata25(ap, want_ncq);
1531 } else if (IS_GEN_IIE(hpriv)) {
1532 int want_fbs = sata_pmp_attached(ap);
1534 * Possible future enhancement:
1536 * The chip can use FBS with non-NCQ, if we allow it,
1537 * But first we need to have the error handling in place
1538 * for this mode (datasheet section 7.3.15.4.2.3).
1539 * So disallow non-NCQ FBS for now.
1541 want_fbs &= want_ncq;
1543 mv_config_fbs(ap, want_ncq, want_fbs);
1546 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1547 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1550 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1552 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1554 cfg |= (1 << 18); /* enab early completion */
1556 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1557 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1558 mv_bmdma_enable_iie(ap, !want_edma);
1560 if (IS_SOC(hpriv)) {
1562 mv_soc_led_blink_enable(ap);
1564 mv_soc_led_blink_disable(ap);
1569 cfg |= EDMA_CFG_NCQ;
1570 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1573 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1576 static void mv_port_free_dma_mem(struct ata_port *ap)
1578 struct mv_host_priv *hpriv = ap->host->private_data;
1579 struct mv_port_priv *pp = ap->private_data;
1583 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1587 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1591 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1592 * For later hardware, we have one unique sg_tbl per NCQ tag.
1594 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1595 if (pp->sg_tbl[tag]) {
1596 if (tag == 0 || !IS_GEN_I(hpriv))
1597 dma_pool_free(hpriv->sg_tbl_pool,
1599 pp->sg_tbl_dma[tag]);
1600 pp->sg_tbl[tag] = NULL;
1606 * mv_port_start - Port specific init/start routine.
1607 * @ap: ATA channel to manipulate
1609 * Allocate and point to DMA memory, init port private memory,
1613 * Inherited from caller.
1615 static int mv_port_start(struct ata_port *ap)
1617 struct device *dev = ap->host->dev;
1618 struct mv_host_priv *hpriv = ap->host->private_data;
1619 struct mv_port_priv *pp;
1620 unsigned long flags;
1623 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1626 ap->private_data = pp;
1628 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1631 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1633 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1635 goto out_port_free_dma_mem;
1636 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1638 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1639 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1640 ap->flags |= ATA_FLAG_AN;
1642 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1643 * For later hardware, we need one unique sg_tbl per NCQ tag.
1645 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1646 if (tag == 0 || !IS_GEN_I(hpriv)) {
1647 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1648 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1649 if (!pp->sg_tbl[tag])
1650 goto out_port_free_dma_mem;
1652 pp->sg_tbl[tag] = pp->sg_tbl[0];
1653 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1657 spin_lock_irqsave(ap->lock, flags);
1658 mv_save_cached_regs(ap);
1659 mv_edma_cfg(ap, 0, 0);
1660 spin_unlock_irqrestore(ap->lock, flags);
1664 out_port_free_dma_mem:
1665 mv_port_free_dma_mem(ap);
1670 * mv_port_stop - Port specific cleanup/stop routine.
1671 * @ap: ATA channel to manipulate
1673 * Stop DMA, cleanup port memory.
1676 * This routine uses the host lock to protect the DMA stop.
1678 static void mv_port_stop(struct ata_port *ap)
1680 unsigned long flags;
1682 spin_lock_irqsave(ap->lock, flags);
1684 mv_enable_port_irqs(ap, 0);
1685 spin_unlock_irqrestore(ap->lock, flags);
1686 mv_port_free_dma_mem(ap);
1690 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1691 * @qc: queued command whose SG list to source from
1693 * Populate the SG list and mark the last entry.
1696 * Inherited from caller.
1698 static void mv_fill_sg(struct ata_queued_cmd *qc)
1700 struct mv_port_priv *pp = qc->ap->private_data;
1701 struct scatterlist *sg;
1702 struct mv_sg *mv_sg, *last_sg = NULL;
1705 mv_sg = pp->sg_tbl[qc->tag];
1706 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1707 dma_addr_t addr = sg_dma_address(sg);
1708 u32 sg_len = sg_dma_len(sg);
1711 u32 offset = addr & 0xffff;
1714 if (offset + len > 0x10000)
1715 len = 0x10000 - offset;
1717 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1718 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1719 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1720 mv_sg->reserved = 0;
1730 if (likely(last_sg))
1731 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1732 mb(); /* ensure data structure is visible to the chipset */
1735 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1737 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1738 (last ? CRQB_CMD_LAST : 0);
1739 *cmdw = cpu_to_le16(tmp);
1743 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1744 * @ap: Port associated with this ATA transaction.
1746 * We need this only for ATAPI bmdma transactions,
1747 * as otherwise we experience spurious interrupts
1748 * after libata-sff handles the bmdma interrupts.
1750 static void mv_sff_irq_clear(struct ata_port *ap)
1752 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1756 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1757 * @qc: queued command to check for chipset/DMA compatibility.
1759 * The bmdma engines cannot handle speculative data sizes
1760 * (bytecount under/over flow). So only allow DMA for
1761 * data transfer commands with known data sizes.
1764 * Inherited from caller.
1766 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1768 struct scsi_cmnd *scmd = qc->scsicmd;
1771 switch (scmd->cmnd[0]) {
1779 case GPCMD_SEND_DVD_STRUCTURE:
1780 case GPCMD_SEND_CUE_SHEET:
1781 return 0; /* DMA is safe */
1784 return -EOPNOTSUPP; /* use PIO instead */
1788 * mv_bmdma_setup - Set up BMDMA transaction
1789 * @qc: queued command to prepare DMA for.
1792 * Inherited from caller.
1794 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1796 struct ata_port *ap = qc->ap;
1797 void __iomem *port_mmio = mv_ap_base(ap);
1798 struct mv_port_priv *pp = ap->private_data;
1802 /* clear all DMA cmd bits */
1803 writel(0, port_mmio + BMDMA_CMD_OFS);
1805 /* load PRD table addr. */
1806 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1807 port_mmio + BMDMA_PRD_HIGH_OFS);
1808 writelfl(pp->sg_tbl_dma[qc->tag],
1809 port_mmio + BMDMA_PRD_LOW_OFS);
1811 /* issue r/w command */
1812 ap->ops->sff_exec_command(ap, &qc->tf);
1816 * mv_bmdma_start - Start a BMDMA transaction
1817 * @qc: queued command to start DMA on.
1820 * Inherited from caller.
1822 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1824 struct ata_port *ap = qc->ap;
1825 void __iomem *port_mmio = mv_ap_base(ap);
1826 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1827 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1829 /* start host DMA transaction */
1830 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1834 * mv_bmdma_stop - Stop BMDMA transfer
1835 * @qc: queued command to stop DMA on.
1837 * Clears the ATA_DMA_START flag in the bmdma control register
1840 * Inherited from caller.
1842 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1844 struct ata_port *ap = qc->ap;
1845 void __iomem *port_mmio = mv_ap_base(ap);
1848 /* clear start/stop bit */
1849 cmd = readl(port_mmio + BMDMA_CMD_OFS);
1850 cmd &= ~ATA_DMA_START;
1851 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1853 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1854 ata_sff_dma_pause(ap);
1858 * mv_bmdma_status - Read BMDMA status
1859 * @ap: port for which to retrieve DMA status.
1861 * Read and return equivalent of the sff BMDMA status register.
1864 * Inherited from caller.
1866 static u8 mv_bmdma_status(struct ata_port *ap)
1868 void __iomem *port_mmio = mv_ap_base(ap);
1872 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1873 * and the ATA_DMA_INTR bit doesn't exist.
1875 reg = readl(port_mmio + BMDMA_STATUS_OFS);
1876 if (reg & ATA_DMA_ACTIVE)
1877 status = ATA_DMA_ACTIVE;
1879 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1884 * mv_qc_prep - Host specific command preparation.
1885 * @qc: queued command to prepare
1887 * This routine simply redirects to the general purpose routine
1888 * if command is not DMA. Else, it handles prep of the CRQB
1889 * (command request block), does some sanity checking, and calls
1890 * the SG load routine.
1893 * Inherited from caller.
1895 static void mv_qc_prep(struct ata_queued_cmd *qc)
1897 struct ata_port *ap = qc->ap;
1898 struct mv_port_priv *pp = ap->private_data;
1900 struct ata_taskfile *tf;
1904 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1905 (qc->tf.protocol != ATA_PROT_NCQ))
1908 /* Fill in command request block
1910 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1911 flags |= CRQB_FLAG_READ;
1912 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1913 flags |= qc->tag << CRQB_TAG_SHIFT;
1914 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1916 /* get current queue index from software */
1917 in_index = pp->req_idx;
1919 pp->crqb[in_index].sg_addr =
1920 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1921 pp->crqb[in_index].sg_addr_hi =
1922 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1923 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1925 cw = &pp->crqb[in_index].ata_cmd[0];
1928 /* Sadly, the CRQB cannot accomodate all registers--there are
1929 * only 11 bytes...so we must pick and choose required
1930 * registers based on the command. So, we drop feature and
1931 * hob_feature for [RW] DMA commands, but they are needed for
1932 * NCQ. NCQ will drop hob_nsect, which is not needed there
1933 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
1935 switch (tf->command) {
1937 case ATA_CMD_READ_EXT:
1939 case ATA_CMD_WRITE_EXT:
1940 case ATA_CMD_WRITE_FUA_EXT:
1941 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1943 case ATA_CMD_FPDMA_READ:
1944 case ATA_CMD_FPDMA_WRITE:
1945 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1946 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1949 /* The only other commands EDMA supports in non-queued and
1950 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1951 * of which are defined/used by Linux. If we get here, this
1952 * driver needs work.
1954 * FIXME: modify libata to give qc_prep a return value and
1955 * return error here.
1957 BUG_ON(tf->command);
1960 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1961 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1962 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1963 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1964 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1965 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1966 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1967 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1968 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1970 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1976 * mv_qc_prep_iie - Host specific command preparation.
1977 * @qc: queued command to prepare
1979 * This routine simply redirects to the general purpose routine
1980 * if command is not DMA. Else, it handles prep of the CRQB
1981 * (command request block), does some sanity checking, and calls
1982 * the SG load routine.
1985 * Inherited from caller.
1987 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1989 struct ata_port *ap = qc->ap;
1990 struct mv_port_priv *pp = ap->private_data;
1991 struct mv_crqb_iie *crqb;
1992 struct ata_taskfile *tf;
1996 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1997 (qc->tf.protocol != ATA_PROT_NCQ))
2000 /* Fill in Gen IIE command request block */
2001 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
2002 flags |= CRQB_FLAG_READ;
2004 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2005 flags |= qc->tag << CRQB_TAG_SHIFT;
2006 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
2007 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2009 /* get current queue index from software */
2010 in_index = pp->req_idx;
2012 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
2013 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2014 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2015 crqb->flags = cpu_to_le32(flags);
2018 crqb->ata_cmd[0] = cpu_to_le32(
2019 (tf->command << 16) |
2022 crqb->ata_cmd[1] = cpu_to_le32(
2028 crqb->ata_cmd[2] = cpu_to_le32(
2029 (tf->hob_lbal << 0) |
2030 (tf->hob_lbam << 8) |
2031 (tf->hob_lbah << 16) |
2032 (tf->hob_feature << 24)
2034 crqb->ata_cmd[3] = cpu_to_le32(
2036 (tf->hob_nsect << 8)
2039 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2045 * mv_sff_check_status - fetch device status, if valid
2046 * @ap: ATA port to fetch status from
2048 * When using command issue via mv_qc_issue_fis(),
2049 * the initial ATA_BUSY state does not show up in the
2050 * ATA status (shadow) register. This can confuse libata!
2052 * So we have a hook here to fake ATA_BUSY for that situation,
2053 * until the first time a BUSY, DRQ, or ERR bit is seen.
2055 * The rest of the time, it simply returns the ATA status register.
2057 static u8 mv_sff_check_status(struct ata_port *ap)
2059 u8 stat = ioread8(ap->ioaddr.status_addr);
2060 struct mv_port_priv *pp = ap->private_data;
2062 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2063 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2064 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2072 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2073 * @fis: fis to be sent
2074 * @nwords: number of 32-bit words in the fis
2076 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2078 void __iomem *port_mmio = mv_ap_base(ap);
2079 u32 ifctl, old_ifctl, ifstat;
2080 int i, timeout = 200, final_word = nwords - 1;
2082 /* Initiate FIS transmission mode */
2083 old_ifctl = readl(port_mmio + SATA_IFCTL_OFS);
2084 ifctl = 0x100 | (old_ifctl & 0xf);
2085 writelfl(ifctl, port_mmio + SATA_IFCTL_OFS);
2087 /* Send all words of the FIS except for the final word */
2088 for (i = 0; i < final_word; ++i)
2089 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS_OFS);
2091 /* Flag end-of-transmission, and then send the final word */
2092 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL_OFS);
2093 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS_OFS);
2096 * Wait for FIS transmission to complete.
2097 * This typically takes just a single iteration.
2100 ifstat = readl(port_mmio + SATA_IFSTAT_OFS);
2101 } while (!(ifstat & 0x1000) && --timeout);
2103 /* Restore original port configuration */
2104 writelfl(old_ifctl, port_mmio + SATA_IFCTL_OFS);
2106 /* See if it worked */
2107 if ((ifstat & 0x3000) != 0x1000) {
2108 ata_port_printk(ap, KERN_WARNING,
2109 "%s transmission error, ifstat=%08x\n",
2111 return AC_ERR_OTHER;
2117 * mv_qc_issue_fis - Issue a command directly as a FIS
2118 * @qc: queued command to start
2120 * Note that the ATA shadow registers are not updated
2121 * after command issue, so the device will appear "READY"
2122 * if polled, even while it is BUSY processing the command.
2124 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2126 * Note: we don't get updated shadow regs on *completion*
2127 * of non-data commands. So avoid sending them via this function,
2128 * as they will appear to have completed immediately.
2130 * GEN_IIE has special registers that we could get the result tf from,
2131 * but earlier chipsets do not. For now, we ignore those registers.
2133 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2135 struct ata_port *ap = qc->ap;
2136 struct mv_port_priv *pp = ap->private_data;
2137 struct ata_link *link = qc->dev->link;
2141 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2142 err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0]));
2146 switch (qc->tf.protocol) {
2147 case ATAPI_PROT_PIO:
2148 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2150 case ATAPI_PROT_NODATA:
2151 ap->hsm_task_state = HSM_ST_FIRST;
2154 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2155 if (qc->tf.flags & ATA_TFLAG_WRITE)
2156 ap->hsm_task_state = HSM_ST_FIRST;
2158 ap->hsm_task_state = HSM_ST;
2161 ap->hsm_task_state = HSM_ST_LAST;
2165 if (qc->tf.flags & ATA_TFLAG_POLLING)
2166 ata_pio_queue_task(ap, qc, 0);
2171 * mv_qc_issue - Initiate a command to the host
2172 * @qc: queued command to start
2174 * This routine simply redirects to the general purpose routine
2175 * if command is not DMA. Else, it sanity checks our local
2176 * caches of the request producer/consumer indices then enables
2177 * DMA and bumps the request producer index.
2180 * Inherited from caller.
2182 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2184 static int limit_warnings = 10;
2185 struct ata_port *ap = qc->ap;
2186 void __iomem *port_mmio = mv_ap_base(ap);
2187 struct mv_port_priv *pp = ap->private_data;
2189 unsigned int port_irqs;
2191 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2193 switch (qc->tf.protocol) {
2196 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2197 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2198 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2200 /* Write the request in pointer to kick the EDMA to life */
2201 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2202 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
2207 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2209 * Someday, we might implement special polling workarounds
2210 * for these, but it all seems rather unnecessary since we
2211 * normally use only DMA for commands which transfer more
2212 * than a single block of data.
2214 * Much of the time, this could just work regardless.
2215 * So for now, just log the incident, and allow the attempt.
2217 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2219 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2220 ": attempting PIO w/multiple DRQ: "
2221 "this may fail due to h/w errata\n");
2224 case ATA_PROT_NODATA:
2225 case ATAPI_PROT_PIO:
2226 case ATAPI_PROT_NODATA:
2227 if (ap->flags & ATA_FLAG_PIO_POLLING)
2228 qc->tf.flags |= ATA_TFLAG_POLLING;
2232 if (qc->tf.flags & ATA_TFLAG_POLLING)
2233 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2235 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2238 * We're about to send a non-EDMA capable command to the
2239 * port. Turn off EDMA so there won't be problems accessing
2240 * shadow block, etc registers.
2243 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2244 mv_pmp_select(ap, qc->dev->link->pmp);
2246 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2247 struct mv_host_priv *hpriv = ap->host->private_data;
2249 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2251 * After any NCQ error, the READ_LOG_EXT command
2252 * from libata-eh *must* use mv_qc_issue_fis().
2253 * Otherwise it might fail, due to chip errata.
2255 * Rather than special-case it, we'll just *always*
2256 * use this method here for READ_LOG_EXT, making for
2259 if (IS_GEN_II(hpriv))
2260 return mv_qc_issue_fis(qc);
2262 return ata_sff_qc_issue(qc);
2265 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2267 struct mv_port_priv *pp = ap->private_data;
2268 struct ata_queued_cmd *qc;
2270 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2272 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2274 if (qc->tf.flags & ATA_TFLAG_POLLING)
2276 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
2282 static void mv_pmp_error_handler(struct ata_port *ap)
2284 unsigned int pmp, pmp_map;
2285 struct mv_port_priv *pp = ap->private_data;
2287 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2289 * Perform NCQ error analysis on failed PMPs
2290 * before we freeze the port entirely.
2292 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2294 pmp_map = pp->delayed_eh_pmp_map;
2295 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2296 for (pmp = 0; pmp_map != 0; pmp++) {
2297 unsigned int this_pmp = (1 << pmp);
2298 if (pmp_map & this_pmp) {
2299 struct ata_link *link = &ap->pmp_link[pmp];
2300 pmp_map &= ~this_pmp;
2301 ata_eh_analyze_ncq_error(link);
2304 ata_port_freeze(ap);
2306 sata_pmp_error_handler(ap);
2309 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2311 void __iomem *port_mmio = mv_ap_base(ap);
2313 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
2316 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2318 struct ata_eh_info *ehi;
2322 * Initialize EH info for PMPs which saw device errors
2324 ehi = &ap->link.eh_info;
2325 for (pmp = 0; pmp_map != 0; pmp++) {
2326 unsigned int this_pmp = (1 << pmp);
2327 if (pmp_map & this_pmp) {
2328 struct ata_link *link = &ap->pmp_link[pmp];
2330 pmp_map &= ~this_pmp;
2331 ehi = &link->eh_info;
2332 ata_ehi_clear_desc(ehi);
2333 ata_ehi_push_desc(ehi, "dev err");
2334 ehi->err_mask |= AC_ERR_DEV;
2335 ehi->action |= ATA_EH_RESET;
2336 ata_link_abort(link);
2341 static int mv_req_q_empty(struct ata_port *ap)
2343 void __iomem *port_mmio = mv_ap_base(ap);
2344 u32 in_ptr, out_ptr;
2346 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
2347 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2348 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
2349 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2350 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2353 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2355 struct mv_port_priv *pp = ap->private_data;
2357 unsigned int old_map, new_map;
2360 * Device error during FBS+NCQ operation:
2362 * Set a port flag to prevent further I/O being enqueued.
2363 * Leave the EDMA running to drain outstanding commands from this port.
2364 * Perform the post-mortem/EH only when all responses are complete.
2365 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2367 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2368 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2369 pp->delayed_eh_pmp_map = 0;
2371 old_map = pp->delayed_eh_pmp_map;
2372 new_map = old_map | mv_get_err_pmp_map(ap);
2374 if (old_map != new_map) {
2375 pp->delayed_eh_pmp_map = new_map;
2376 mv_pmp_eh_prep(ap, new_map & ~old_map);
2378 failed_links = hweight16(new_map);
2380 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2381 "failed_links=%d nr_active_links=%d\n",
2382 __func__, pp->delayed_eh_pmp_map,
2383 ap->qc_active, failed_links,
2384 ap->nr_active_links);
2386 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2387 mv_process_crpb_entries(ap, pp);
2390 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2391 return 1; /* handled */
2393 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2394 return 1; /* handled */
2397 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2400 * Possible future enhancement:
2402 * FBS+non-NCQ operation is not yet implemented.
2403 * See related notes in mv_edma_cfg().
2405 * Device error during FBS+non-NCQ operation:
2407 * We need to snapshot the shadow registers for each failed command.
2408 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2410 return 0; /* not handled */
2413 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2415 struct mv_port_priv *pp = ap->private_data;
2417 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2418 return 0; /* EDMA was not active: not handled */
2419 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2420 return 0; /* FBS was not active: not handled */
2422 if (!(edma_err_cause & EDMA_ERR_DEV))
2423 return 0; /* non DEV error: not handled */
2424 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2425 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2426 return 0; /* other problems: not handled */
2428 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2430 * EDMA should NOT have self-disabled for this case.
2431 * If it did, then something is wrong elsewhere,
2432 * and we cannot handle it here.
2434 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2435 ata_port_printk(ap, KERN_WARNING,
2436 "%s: err_cause=0x%x pp_flags=0x%x\n",
2437 __func__, edma_err_cause, pp->pp_flags);
2438 return 0; /* not handled */
2440 return mv_handle_fbs_ncq_dev_err(ap);
2443 * EDMA should have self-disabled for this case.
2444 * If it did not, then something is wrong elsewhere,
2445 * and we cannot handle it here.
2447 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2448 ata_port_printk(ap, KERN_WARNING,
2449 "%s: err_cause=0x%x pp_flags=0x%x\n",
2450 __func__, edma_err_cause, pp->pp_flags);
2451 return 0; /* not handled */
2453 return mv_handle_fbs_non_ncq_dev_err(ap);
2455 return 0; /* not handled */
2458 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2460 struct ata_eh_info *ehi = &ap->link.eh_info;
2461 char *when = "idle";
2463 ata_ehi_clear_desc(ehi);
2464 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2466 } else if (edma_was_enabled) {
2467 when = "EDMA enabled";
2469 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2470 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2473 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2474 ehi->err_mask |= AC_ERR_OTHER;
2475 ehi->action |= ATA_EH_RESET;
2476 ata_port_freeze(ap);
2480 * mv_err_intr - Handle error interrupts on the port
2481 * @ap: ATA channel to manipulate
2483 * Most cases require a full reset of the chip's state machine,
2484 * which also performs a COMRESET.
2485 * Also, if the port disabled DMA, update our cached copy to match.
2488 * Inherited from caller.
2490 static void mv_err_intr(struct ata_port *ap)
2492 void __iomem *port_mmio = mv_ap_base(ap);
2493 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2495 struct mv_port_priv *pp = ap->private_data;
2496 struct mv_host_priv *hpriv = ap->host->private_data;
2497 unsigned int action = 0, err_mask = 0;
2498 struct ata_eh_info *ehi = &ap->link.eh_info;
2499 struct ata_queued_cmd *qc;
2503 * Read and clear the SError and err_cause bits.
2504 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2505 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2507 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2508 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2510 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2511 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2512 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2513 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2515 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2517 if (edma_err_cause & EDMA_ERR_DEV) {
2519 * Device errors during FIS-based switching operation
2520 * require special handling.
2522 if (mv_handle_dev_err(ap, edma_err_cause))
2526 qc = mv_get_active_qc(ap);
2527 ata_ehi_clear_desc(ehi);
2528 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2529 edma_err_cause, pp->pp_flags);
2531 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2532 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2533 if (fis_cause & SATA_FIS_IRQ_AN) {
2534 u32 ec = edma_err_cause &
2535 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2536 sata_async_notification(ap);
2538 return; /* Just an AN; no need for the nukes */
2539 ata_ehi_push_desc(ehi, "SDB notify");
2543 * All generations share these EDMA error cause bits:
2545 if (edma_err_cause & EDMA_ERR_DEV) {
2546 err_mask |= AC_ERR_DEV;
2547 action |= ATA_EH_RESET;
2548 ata_ehi_push_desc(ehi, "dev error");
2550 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2551 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2552 EDMA_ERR_INTRL_PAR)) {
2553 err_mask |= AC_ERR_ATA_BUS;
2554 action |= ATA_EH_RESET;
2555 ata_ehi_push_desc(ehi, "parity error");
2557 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2558 ata_ehi_hotplugged(ehi);
2559 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2560 "dev disconnect" : "dev connect");
2561 action |= ATA_EH_RESET;
2565 * Gen-I has a different SELF_DIS bit,
2566 * different FREEZE bits, and no SERR bit:
2568 if (IS_GEN_I(hpriv)) {
2569 eh_freeze_mask = EDMA_EH_FREEZE_5;
2570 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2571 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2572 ata_ehi_push_desc(ehi, "EDMA self-disable");
2575 eh_freeze_mask = EDMA_EH_FREEZE;
2576 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2577 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2578 ata_ehi_push_desc(ehi, "EDMA self-disable");
2580 if (edma_err_cause & EDMA_ERR_SERR) {
2581 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2582 err_mask |= AC_ERR_ATA_BUS;
2583 action |= ATA_EH_RESET;
2588 err_mask = AC_ERR_OTHER;
2589 action |= ATA_EH_RESET;
2592 ehi->serror |= serr;
2593 ehi->action |= action;
2596 qc->err_mask |= err_mask;
2598 ehi->err_mask |= err_mask;
2600 if (err_mask == AC_ERR_DEV) {
2602 * Cannot do ata_port_freeze() here,
2603 * because it would kill PIO access,
2604 * which is needed for further diagnosis.
2608 } else if (edma_err_cause & eh_freeze_mask) {
2610 * Note to self: ata_port_freeze() calls ata_port_abort()
2612 ata_port_freeze(ap);
2619 ata_link_abort(qc->dev->link);
2625 static void mv_process_crpb_response(struct ata_port *ap,
2626 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2628 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2632 u16 edma_status = le16_to_cpu(response->flags);
2634 * edma_status from a response queue entry:
2635 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
2636 * MSB is saved ATA status from command completion.
2639 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2642 * Error will be seen/handled by mv_err_intr().
2643 * So do nothing at all here.
2648 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2649 if (!ac_err_mask(ata_status))
2650 ata_qc_complete(qc);
2651 /* else: leave it for mv_err_intr() */
2653 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2658 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2660 void __iomem *port_mmio = mv_ap_base(ap);
2661 struct mv_host_priv *hpriv = ap->host->private_data;
2663 bool work_done = false;
2664 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2666 /* Get the hardware queue position index */
2667 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2668 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2670 /* Process new responses from since the last time we looked */
2671 while (in_index != pp->resp_idx) {
2673 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2675 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2677 if (IS_GEN_I(hpriv)) {
2678 /* 50xx: no NCQ, only one command active at a time */
2679 tag = ap->link.active_tag;
2681 /* Gen II/IIE: get command tag from CRPB entry */
2682 tag = le16_to_cpu(response->id) & 0x1f;
2684 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2688 /* Update the software queue position index in hardware */
2690 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2691 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2692 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
2695 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2697 struct mv_port_priv *pp;
2698 int edma_was_enabled;
2700 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2701 mv_unexpected_intr(ap, 0);
2705 * Grab a snapshot of the EDMA_EN flag setting,
2706 * so that we have a consistent view for this port,
2707 * even if something we call of our routines changes it.
2709 pp = ap->private_data;
2710 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2712 * Process completed CRPB response(s) before other events.
2714 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2715 mv_process_crpb_entries(ap, pp);
2716 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2717 mv_handle_fbs_ncq_dev_err(ap);
2720 * Handle chip-reported errors, or continue on to handle PIO.
2722 if (unlikely(port_cause & ERR_IRQ)) {
2724 } else if (!edma_was_enabled) {
2725 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2727 ata_sff_host_intr(ap, qc);
2729 mv_unexpected_intr(ap, edma_was_enabled);
2734 * mv_host_intr - Handle all interrupts on the given host controller
2735 * @host: host specific structure
2736 * @main_irq_cause: Main interrupt cause register for the chip.
2739 * Inherited from caller.
2741 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2743 struct mv_host_priv *hpriv = host->private_data;
2744 void __iomem *mmio = hpriv->base, *hc_mmio;
2745 unsigned int handled = 0, port;
2747 /* If asserted, clear the "all ports" IRQ coalescing bit */
2748 if (main_irq_cause & ALL_PORTS_COAL_DONE)
2749 writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE);
2751 for (port = 0; port < hpriv->n_ports; port++) {
2752 struct ata_port *ap = host->ports[port];
2753 unsigned int p, shift, hardport, port_cause;
2755 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2757 * Each hc within the host has its own hc_irq_cause register,
2758 * where the interrupting ports bits get ack'd.
2760 if (hardport == 0) { /* first port on this hc ? */
2761 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2762 u32 port_mask, ack_irqs;
2764 * Skip this entire hc if nothing pending for any ports
2767 port += MV_PORTS_PER_HC - 1;
2771 * We don't need/want to read the hc_irq_cause register,
2772 * because doing so hurts performance, and
2773 * main_irq_cause already gives us everything we need.
2775 * But we do have to *write* to the hc_irq_cause to ack
2776 * the ports that we are handling this time through.
2778 * This requires that we create a bitmap for those
2779 * ports which interrupted us, and use that bitmap
2780 * to ack (only) those ports via hc_irq_cause.
2783 if (hc_cause & PORTS_0_3_COAL_DONE)
2784 ack_irqs = HC_COAL_IRQ;
2785 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2786 if ((port + p) >= hpriv->n_ports)
2788 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2789 if (hc_cause & port_mask)
2790 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2792 hc_mmio = mv_hc_base_from_port(mmio, port);
2793 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
2797 * Handle interrupts signalled for this port:
2799 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2801 mv_port_intr(ap, port_cause);
2806 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2808 struct mv_host_priv *hpriv = host->private_data;
2809 struct ata_port *ap;
2810 struct ata_queued_cmd *qc;
2811 struct ata_eh_info *ehi;
2812 unsigned int i, err_mask, printed = 0;
2815 err_cause = readl(mmio + hpriv->irq_cause_ofs);
2817 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2820 DPRINTK("All regs @ PCI error\n");
2821 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2823 writelfl(0, mmio + hpriv->irq_cause_ofs);
2825 for (i = 0; i < host->n_ports; i++) {
2826 ap = host->ports[i];
2827 if (!ata_link_offline(&ap->link)) {
2828 ehi = &ap->link.eh_info;
2829 ata_ehi_clear_desc(ehi);
2831 ata_ehi_push_desc(ehi,
2832 "PCI err cause 0x%08x", err_cause);
2833 err_mask = AC_ERR_HOST_BUS;
2834 ehi->action = ATA_EH_RESET;
2835 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2837 qc->err_mask |= err_mask;
2839 ehi->err_mask |= err_mask;
2841 ata_port_freeze(ap);
2844 return 1; /* handled */
2848 * mv_interrupt - Main interrupt event handler
2850 * @dev_instance: private data; in this case the host structure
2852 * Read the read only register to determine if any host
2853 * controllers have pending interrupts. If so, call lower level
2854 * routine to handle. Also check for PCI errors which are only
2858 * This routine holds the host lock while processing pending
2861 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2863 struct ata_host *host = dev_instance;
2864 struct mv_host_priv *hpriv = host->private_data;
2865 unsigned int handled = 0;
2866 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2867 u32 main_irq_cause, pending_irqs;
2869 spin_lock(&host->lock);
2871 /* for MSI: block new interrupts while in here */
2873 mv_write_main_irq_mask(0, hpriv);
2875 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2876 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2878 * Deal with cases where we either have nothing pending, or have read
2879 * a bogus register value which can indicate HW removal or PCI fault.
2881 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2882 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2883 handled = mv_pci_error(host, hpriv->base);
2885 handled = mv_host_intr(host, pending_irqs);
2888 /* for MSI: unmask; interrupt cause bits will retrigger now */
2890 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
2892 spin_unlock(&host->lock);
2894 return IRQ_RETVAL(handled);
2897 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2901 switch (sc_reg_in) {
2905 ofs = sc_reg_in * sizeof(u32);
2914 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
2916 struct mv_host_priv *hpriv = link->ap->host->private_data;
2917 void __iomem *mmio = hpriv->base;
2918 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2919 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2921 if (ofs != 0xffffffffU) {
2922 *val = readl(addr + ofs);
2928 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
2930 struct mv_host_priv *hpriv = link->ap->host->private_data;
2931 void __iomem *mmio = hpriv->base;
2932 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2933 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2935 if (ofs != 0xffffffffU) {
2936 writelfl(val, addr + ofs);
2942 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2944 struct pci_dev *pdev = to_pci_dev(host->dev);
2947 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
2950 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2952 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2955 mv_reset_pci_bus(host, mmio);
2958 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2960 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2963 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2966 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2969 tmp = readl(phy_mmio + MV5_PHY_MODE);
2971 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2972 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2975 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2979 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2981 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2983 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2985 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2988 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2991 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2992 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2994 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2997 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2999 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
3001 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
3004 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
3007 tmp = readl(phy_mmio + MV5_PHY_MODE);
3009 tmp |= hpriv->signal[port].pre;
3010 tmp |= hpriv->signal[port].amps;
3011 writel(tmp, phy_mmio + MV5_PHY_MODE);
3016 #define ZERO(reg) writel(0, port_mmio + (reg))
3017 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3020 void __iomem *port_mmio = mv_port_base(mmio, port);
3022 mv_reset_channel(hpriv, mmio, port);
3024 ZERO(0x028); /* command */
3025 writel(0x11f, port_mmio + EDMA_CFG_OFS);
3026 ZERO(0x004); /* timer */
3027 ZERO(0x008); /* irq err cause */
3028 ZERO(0x00c); /* irq err mask */
3029 ZERO(0x010); /* rq bah */
3030 ZERO(0x014); /* rq inp */
3031 ZERO(0x018); /* rq outp */
3032 ZERO(0x01c); /* respq bah */
3033 ZERO(0x024); /* respq outp */
3034 ZERO(0x020); /* respq inp */
3035 ZERO(0x02c); /* test control */
3036 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
3040 #define ZERO(reg) writel(0, hc_mmio + (reg))
3041 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3044 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3052 tmp = readl(hc_mmio + 0x20);
3055 writel(tmp, hc_mmio + 0x20);
3059 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3062 unsigned int hc, port;
3064 for (hc = 0; hc < n_hc; hc++) {
3065 for (port = 0; port < MV_PORTS_PER_HC; port++)
3066 mv5_reset_hc_port(hpriv, mmio,
3067 (hc * MV_PORTS_PER_HC) + port);
3069 mv5_reset_one_hc(hpriv, mmio, hc);
3076 #define ZERO(reg) writel(0, mmio + (reg))
3077 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3079 struct mv_host_priv *hpriv = host->private_data;
3082 tmp = readl(mmio + MV_PCI_MODE_OFS);
3084 writel(tmp, mmio + MV_PCI_MODE_OFS);
3086 ZERO(MV_PCI_DISC_TIMER);
3087 ZERO(MV_PCI_MSI_TRIGGER);
3088 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
3089 ZERO(MV_PCI_SERR_MASK);
3090 ZERO(hpriv->irq_cause_ofs);
3091 ZERO(hpriv->irq_mask_ofs);
3092 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3093 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3094 ZERO(MV_PCI_ERR_ATTRIBUTE);
3095 ZERO(MV_PCI_ERR_COMMAND);
3099 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3103 mv5_reset_flash(hpriv, mmio);
3105 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
3107 tmp |= (1 << 5) | (1 << 6);
3108 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
3112 * mv6_reset_hc - Perform the 6xxx global soft reset
3113 * @mmio: base address of the HBA
3115 * This routine only applies to 6xxx parts.
3118 * Inherited from caller.
3120 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3123 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
3127 /* Following procedure defined in PCI "main command and status
3131 writel(t | STOP_PCI_MASTER, reg);
3133 for (i = 0; i < 1000; i++) {
3136 if (PCI_MASTER_EMPTY & t)
3139 if (!(PCI_MASTER_EMPTY & t)) {
3140 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3148 writel(t | GLOB_SFT_RST, reg);
3151 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3153 if (!(GLOB_SFT_RST & t)) {
3154 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3159 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3162 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3165 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3167 if (GLOB_SFT_RST & t) {
3168 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3175 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3178 void __iomem *port_mmio;
3181 tmp = readl(mmio + MV_RESET_CFG_OFS);
3182 if ((tmp & (1 << 0)) == 0) {
3183 hpriv->signal[idx].amps = 0x7 << 8;
3184 hpriv->signal[idx].pre = 0x1 << 5;
3188 port_mmio = mv_port_base(mmio, idx);
3189 tmp = readl(port_mmio + PHY_MODE2_OFS);
3191 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3192 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3195 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3197 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
3200 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3203 void __iomem *port_mmio = mv_port_base(mmio, port);
3205 u32 hp_flags = hpriv->hp_flags;
3207 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3209 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3212 if (fix_phy_mode2) {
3213 m2 = readl(port_mmio + PHY_MODE2_OFS);
3216 writel(m2, port_mmio + PHY_MODE2_OFS);
3220 m2 = readl(port_mmio + PHY_MODE2_OFS);
3221 m2 &= ~((1 << 16) | (1 << 31));
3222 writel(m2, port_mmio + PHY_MODE2_OFS);
3228 * Gen-II/IIe PHY_MODE3_OFS errata RM#2:
3229 * Achieves better receiver noise performance than the h/w default:
3231 m3 = readl(port_mmio + PHY_MODE3_OFS);
3232 m3 = (m3 & 0x1f) | (0x5555601 << 5);
3234 /* Guideline 88F5182 (GL# SATA-S11) */
3238 if (fix_phy_mode4) {
3239 u32 m4 = readl(port_mmio + PHY_MODE4_OFS);
3241 * Enforce reserved-bit restrictions on GenIIe devices only.
3242 * For earlier chipsets, force only the internal config field
3243 * (workaround for errata FEr SATA#10 part 1).
3245 if (IS_GEN_IIE(hpriv))
3246 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3248 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3249 writel(m4, port_mmio + PHY_MODE4_OFS);
3252 * Workaround for 60x1-B2 errata SATA#13:
3253 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3254 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3255 * Or ensure we use writelfl() when writing PHY_MODE4.
3257 writel(m3, port_mmio + PHY_MODE3_OFS);
3259 /* Revert values of pre-emphasis and signal amps to the saved ones */
3260 m2 = readl(port_mmio + PHY_MODE2_OFS);
3262 m2 &= ~MV_M2_PREAMP_MASK;
3263 m2 |= hpriv->signal[port].amps;
3264 m2 |= hpriv->signal[port].pre;
3267 /* according to mvSata 3.6.1, some IIE values are fixed */
3268 if (IS_GEN_IIE(hpriv)) {
3273 writel(m2, port_mmio + PHY_MODE2_OFS);
3276 /* TODO: use the generic LED interface to configure the SATA Presence */
3277 /* & Acitivy LEDs on the board */
3278 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3284 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3287 void __iomem *port_mmio;
3290 port_mmio = mv_port_base(mmio, idx);
3291 tmp = readl(port_mmio + PHY_MODE2_OFS);
3293 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3294 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3298 #define ZERO(reg) writel(0, port_mmio + (reg))
3299 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3300 void __iomem *mmio, unsigned int port)
3302 void __iomem *port_mmio = mv_port_base(mmio, port);
3304 mv_reset_channel(hpriv, mmio, port);
3306 ZERO(0x028); /* command */
3307 writel(0x101f, port_mmio + EDMA_CFG_OFS);
3308 ZERO(0x004); /* timer */
3309 ZERO(0x008); /* irq err cause */
3310 ZERO(0x00c); /* irq err mask */
3311 ZERO(0x010); /* rq bah */
3312 ZERO(0x014); /* rq inp */
3313 ZERO(0x018); /* rq outp */
3314 ZERO(0x01c); /* respq bah */
3315 ZERO(0x024); /* respq outp */
3316 ZERO(0x020); /* respq inp */
3317 ZERO(0x02c); /* test control */
3318 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
3323 #define ZERO(reg) writel(0, hc_mmio + (reg))
3324 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3327 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3337 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3338 void __iomem *mmio, unsigned int n_hc)
3342 for (port = 0; port < hpriv->n_ports; port++)
3343 mv_soc_reset_hc_port(hpriv, mmio, port);
3345 mv_soc_reset_one_hc(hpriv, mmio);
3350 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3356 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3361 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3363 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
3365 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
3367 ifcfg |= (1 << 7); /* enable gen2i speed */
3368 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
3371 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3372 unsigned int port_no)
3374 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3377 * The datasheet warns against setting EDMA_RESET when EDMA is active
3378 * (but doesn't say what the problem might be). So we first try
3379 * to disable the EDMA engine before doing the EDMA_RESET operation.
3381 mv_stop_edma_engine(port_mmio);
3382 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
3384 if (!IS_GEN_I(hpriv)) {
3385 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3386 mv_setup_ifcfg(port_mmio, 1);
3389 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3390 * link, and physical layers. It resets all SATA interface registers
3391 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
3393 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
3394 udelay(25); /* allow reset propagation */
3395 writelfl(0, port_mmio + EDMA_CMD_OFS);
3397 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3399 if (IS_GEN_I(hpriv))
3403 static void mv_pmp_select(struct ata_port *ap, int pmp)
3405 if (sata_pmp_supported(ap)) {
3406 void __iomem *port_mmio = mv_ap_base(ap);
3407 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
3408 int old = reg & 0xf;
3411 reg = (reg & ~0xf) | pmp;
3412 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
3417 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3418 unsigned long deadline)
3420 mv_pmp_select(link->ap, sata_srst_pmp(link));
3421 return sata_std_hardreset(link, class, deadline);
3424 static int mv_softreset(struct ata_link *link, unsigned int *class,
3425 unsigned long deadline)
3427 mv_pmp_select(link->ap, sata_srst_pmp(link));
3428 return ata_sff_softreset(link, class, deadline);
3431 static int mv_hardreset(struct ata_link *link, unsigned int *class,
3432 unsigned long deadline)
3434 struct ata_port *ap = link->ap;
3435 struct mv_host_priv *hpriv = ap->host->private_data;
3436 struct mv_port_priv *pp = ap->private_data;
3437 void __iomem *mmio = hpriv->base;
3438 int rc, attempts = 0, extra = 0;
3442 mv_reset_channel(hpriv, mmio, ap->port_no);
3443 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3445 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
3447 /* Workaround for errata FEr SATA#10 (part 2) */
3449 const unsigned long *timing =
3450 sata_ehc_deb_timing(&link->eh_context);
3452 rc = sata_link_hardreset(link, timing, deadline + extra,
3454 rc = online ? -EAGAIN : rc;
3457 sata_scr_read(link, SCR_STATUS, &sstatus);
3458 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3459 /* Force 1.5gb/s link speed and try again */
3460 mv_setup_ifcfg(mv_ap_base(ap), 0);
3461 if (time_after(jiffies + HZ, deadline))
3462 extra = HZ; /* only extend it once, max */
3464 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3465 mv_save_cached_regs(ap);
3466 mv_edma_cfg(ap, 0, 0);
3471 static void mv_eh_freeze(struct ata_port *ap)
3474 mv_enable_port_irqs(ap, 0);
3477 static void mv_eh_thaw(struct ata_port *ap)
3479 struct mv_host_priv *hpriv = ap->host->private_data;
3480 unsigned int port = ap->port_no;
3481 unsigned int hardport = mv_hardport_from_port(port);
3482 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3483 void __iomem *port_mmio = mv_ap_base(ap);
3486 /* clear EDMA errors on this port */
3487 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3489 /* clear pending irq events */
3490 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3491 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
3493 mv_enable_port_irqs(ap, ERR_IRQ);
3497 * mv_port_init - Perform some early initialization on a single port.
3498 * @port: libata data structure storing shadow register addresses
3499 * @port_mmio: base address of the port
3501 * Initialize shadow register mmio addresses, clear outstanding
3502 * interrupts on the port, and unmask interrupts for the future
3503 * start of the port.
3506 * Inherited from caller.
3508 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3510 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
3513 /* PIO related setup
3515 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3517 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3518 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3519 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3520 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3521 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3522 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3524 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3525 /* special case: control/altstatus doesn't have ATA_REG_ address */
3526 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
3529 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
3531 /* Clear any currently outstanding port interrupt conditions */
3532 serr_ofs = mv_scr_offset(SCR_ERROR);
3533 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
3534 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3536 /* unmask all non-transient EDMA error interrupts */
3537 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
3539 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3540 readl(port_mmio + EDMA_CFG_OFS),
3541 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
3542 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
3545 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3547 struct mv_host_priv *hpriv = host->private_data;
3548 void __iomem *mmio = hpriv->base;
3551 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3552 return 0; /* not PCI-X capable */
3553 reg = readl(mmio + MV_PCI_MODE_OFS);
3554 if ((reg & MV_PCI_MODE_MASK) == 0)
3555 return 0; /* conventional PCI mode */
3556 return 1; /* chip is in PCI-X mode */
3559 static int mv_pci_cut_through_okay(struct ata_host *host)
3561 struct mv_host_priv *hpriv = host->private_data;
3562 void __iomem *mmio = hpriv->base;
3565 if (!mv_in_pcix_mode(host)) {
3566 reg = readl(mmio + PCI_COMMAND_OFS);
3567 if (reg & PCI_COMMAND_MRDTRIG)
3568 return 0; /* not okay */
3570 return 1; /* okay */
3573 static void mv_60x1b2_errata_pci7(struct ata_host *host)
3575 struct mv_host_priv *hpriv = host->private_data;
3576 void __iomem *mmio = hpriv->base;
3578 /* workaround for 60x1-B2 errata PCI#7 */
3579 if (mv_in_pcix_mode(host)) {
3580 u32 reg = readl(mmio + PCI_COMMAND_OFS);
3581 writelfl(reg & ~PCI_COMMAND_MWRCOM, mmio + PCI_COMMAND_OFS);
3585 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3587 struct pci_dev *pdev = to_pci_dev(host->dev);
3588 struct mv_host_priv *hpriv = host->private_data;
3589 u32 hp_flags = hpriv->hp_flags;
3591 switch (board_idx) {
3593 hpriv->ops = &mv5xxx_ops;
3594 hp_flags |= MV_HP_GEN_I;
3596 switch (pdev->revision) {
3598 hp_flags |= MV_HP_ERRATA_50XXB0;
3601 hp_flags |= MV_HP_ERRATA_50XXB2;
3604 dev_printk(KERN_WARNING, &pdev->dev,
3605 "Applying 50XXB2 workarounds to unknown rev\n");
3606 hp_flags |= MV_HP_ERRATA_50XXB2;
3613 hpriv->ops = &mv5xxx_ops;
3614 hp_flags |= MV_HP_GEN_I;
3616 switch (pdev->revision) {
3618 hp_flags |= MV_HP_ERRATA_50XXB0;
3621 hp_flags |= MV_HP_ERRATA_50XXB2;
3624 dev_printk(KERN_WARNING, &pdev->dev,
3625 "Applying B2 workarounds to unknown rev\n");
3626 hp_flags |= MV_HP_ERRATA_50XXB2;
3633 hpriv->ops = &mv6xxx_ops;
3634 hp_flags |= MV_HP_GEN_II;
3636 switch (pdev->revision) {
3638 mv_60x1b2_errata_pci7(host);
3639 hp_flags |= MV_HP_ERRATA_60X1B2;
3642 hp_flags |= MV_HP_ERRATA_60X1C0;
3645 dev_printk(KERN_WARNING, &pdev->dev,
3646 "Applying B2 workarounds to unknown rev\n");
3647 hp_flags |= MV_HP_ERRATA_60X1B2;
3653 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3654 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3655 (pdev->device == 0x2300 || pdev->device == 0x2310))
3658 * Highpoint RocketRAID PCIe 23xx series cards:
3660 * Unconfigured drives are treated as "Legacy"
3661 * by the BIOS, and it overwrites sector 8 with
3662 * a "Lgcy" metadata block prior to Linux boot.
3664 * Configured drives (RAID or JBOD) leave sector 8
3665 * alone, but instead overwrite a high numbered
3666 * sector for the RAID metadata. This sector can
3667 * be determined exactly, by truncating the physical
3668 * drive capacity to a nice even GB value.
3670 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3672 * Warn the user, lest they think we're just buggy.
3674 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3675 " BIOS CORRUPTS DATA on all attached drives,"
3676 " regardless of if/how they are configured."
3678 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3679 " use sectors 8-9 on \"Legacy\" drives,"
3680 " and avoid the final two gigabytes on"
3681 " all RocketRAID BIOS initialized drives.\n");
3685 hpriv->ops = &mv6xxx_ops;
3686 hp_flags |= MV_HP_GEN_IIE;
3687 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3688 hp_flags |= MV_HP_CUT_THROUGH;
3690 switch (pdev->revision) {
3691 case 0x2: /* Rev.B0: the first/only public release */
3692 hp_flags |= MV_HP_ERRATA_60X1C0;
3695 dev_printk(KERN_WARNING, &pdev->dev,
3696 "Applying 60X1C0 workarounds to unknown rev\n");
3697 hp_flags |= MV_HP_ERRATA_60X1C0;
3702 hpriv->ops = &mv_soc_ops;
3703 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3704 MV_HP_ERRATA_60X1C0;
3708 dev_printk(KERN_ERR, host->dev,
3709 "BUG: invalid board index %u\n", board_idx);
3713 hpriv->hp_flags = hp_flags;
3714 if (hp_flags & MV_HP_PCIE) {
3715 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3716 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3717 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3719 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3720 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3721 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3728 * mv_init_host - Perform some early initialization of the host.
3729 * @host: ATA host to initialize
3730 * @board_idx: controller index
3732 * If possible, do an early global reset of the host. Then do
3733 * our port init and clear/unmask all/relevant host interrupts.
3736 * Inherited from caller.
3738 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3740 int rc = 0, n_hc, port, hc;
3741 struct mv_host_priv *hpriv = host->private_data;
3742 void __iomem *mmio = hpriv->base;
3744 rc = mv_chip_id(host, board_idx);
3748 if (IS_SOC(hpriv)) {
3749 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3750 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3752 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3753 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3756 /* initialize shadow irq mask with register's value */
3757 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3759 /* global interrupt mask: 0 == mask everything */
3760 mv_set_main_irq_mask(host, ~0, 0);
3762 n_hc = mv_get_hc_count(host->ports[0]->flags);
3764 for (port = 0; port < host->n_ports; port++)
3765 hpriv->ops->read_preamp(hpriv, port, mmio);
3767 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3771 hpriv->ops->reset_flash(hpriv, mmio);
3772 hpriv->ops->reset_bus(host, mmio);
3773 hpriv->ops->enable_leds(hpriv, mmio);
3775 for (port = 0; port < host->n_ports; port++) {
3776 struct ata_port *ap = host->ports[port];
3777 void __iomem *port_mmio = mv_port_base(mmio, port);
3779 mv_port_init(&ap->ioaddr, port_mmio);
3782 if (!IS_SOC(hpriv)) {
3783 unsigned int offset = port_mmio - mmio;
3784 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3785 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3790 for (hc = 0; hc < n_hc; hc++) {
3791 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3793 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3794 "(before clear)=0x%08x\n", hc,
3795 readl(hc_mmio + HC_CFG_OFS),
3796 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3798 /* Clear any currently outstanding hc interrupt conditions */
3799 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3802 if (!IS_SOC(hpriv)) {
3803 /* Clear any currently outstanding host interrupt conditions */
3804 writelfl(0, mmio + hpriv->irq_cause_ofs);
3806 /* and unmask interrupt generation for host regs */
3807 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3811 * enable only global host interrupts for now.
3812 * The per-port interrupts get done later as ports are set up.
3814 mv_set_main_irq_mask(host, 0, PCI_ERR);
3815 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3816 irq_coalescing_usecs);
3821 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3823 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3825 if (!hpriv->crqb_pool)
3828 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3830 if (!hpriv->crpb_pool)
3833 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3835 if (!hpriv->sg_tbl_pool)
3841 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3842 struct mbus_dram_target_info *dram)
3846 for (i = 0; i < 4; i++) {
3847 writel(0, hpriv->base + WINDOW_CTRL(i));
3848 writel(0, hpriv->base + WINDOW_BASE(i));
3851 for (i = 0; i < dram->num_cs; i++) {
3852 struct mbus_dram_window *cs = dram->cs + i;
3854 writel(((cs->size - 1) & 0xffff0000) |
3855 (cs->mbus_attr << 8) |
3856 (dram->mbus_dram_target_id << 4) | 1,
3857 hpriv->base + WINDOW_CTRL(i));
3858 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3863 * mv_platform_probe - handle a positive probe of an soc Marvell
3865 * @pdev: platform device found
3868 * Inherited from caller.
3870 static int mv_platform_probe(struct platform_device *pdev)
3872 static int printed_version;
3873 const struct mv_sata_platform_data *mv_platform_data;
3874 const struct ata_port_info *ppi[] =
3875 { &mv_port_info[chip_soc], NULL };
3876 struct ata_host *host;
3877 struct mv_host_priv *hpriv;
3878 struct resource *res;
3881 if (!printed_version++)
3882 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3885 * Simple resource validation ..
3887 if (unlikely(pdev->num_resources != 2)) {
3888 dev_err(&pdev->dev, "invalid number of resources\n");
3893 * Get the register base first
3895 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3900 mv_platform_data = pdev->dev.platform_data;
3901 n_ports = mv_platform_data->n_ports;
3903 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3904 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3906 if (!host || !hpriv)
3908 host->private_data = hpriv;
3909 hpriv->n_ports = n_ports;
3912 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3913 res->end - res->start + 1);
3914 hpriv->base -= MV_SATAHC0_REG_BASE;
3917 * (Re-)program MBUS remapping windows if we are asked to.
3919 if (mv_platform_data->dram != NULL)
3920 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3922 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3926 /* initialize adapter */
3927 rc = mv_init_host(host, chip_soc);
3931 dev_printk(KERN_INFO, &pdev->dev,
3932 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3935 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3936 IRQF_SHARED, &mv6_sht);
3941 * mv_platform_remove - unplug a platform interface
3942 * @pdev: platform device
3944 * A platform bus SATA device has been unplugged. Perform the needed
3945 * cleanup. Also called on module unload for any active devices.
3947 static int __devexit mv_platform_remove(struct platform_device *pdev)
3949 struct device *dev = &pdev->dev;
3950 struct ata_host *host = dev_get_drvdata(dev);
3952 ata_host_detach(host);
3956 static struct platform_driver mv_platform_driver = {
3957 .probe = mv_platform_probe,
3958 .remove = __devexit_p(mv_platform_remove),
3961 .owner = THIS_MODULE,
3967 static int mv_pci_init_one(struct pci_dev *pdev,
3968 const struct pci_device_id *ent);
3971 static struct pci_driver mv_pci_driver = {
3973 .id_table = mv_pci_tbl,
3974 .probe = mv_pci_init_one,
3975 .remove = ata_pci_remove_one,
3978 /* move to PCI layer or libata core? */
3979 static int pci_go_64(struct pci_dev *pdev)
3983 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3984 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3986 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3988 dev_printk(KERN_ERR, &pdev->dev,
3989 "64-bit DMA enable failed\n");
3994 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3996 dev_printk(KERN_ERR, &pdev->dev,
3997 "32-bit DMA enable failed\n");
4000 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
4002 dev_printk(KERN_ERR, &pdev->dev,
4003 "32-bit consistent DMA enable failed\n");
4012 * mv_print_info - Dump key info to kernel log for perusal.
4013 * @host: ATA host to print info about
4015 * FIXME: complete this.
4018 * Inherited from caller.
4020 static void mv_print_info(struct ata_host *host)
4022 struct pci_dev *pdev = to_pci_dev(host->dev);
4023 struct mv_host_priv *hpriv = host->private_data;
4025 const char *scc_s, *gen;
4027 /* Use this to determine the HW stepping of the chip so we know
4028 * what errata to workaround
4030 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4033 else if (scc == 0x01)
4038 if (IS_GEN_I(hpriv))
4040 else if (IS_GEN_II(hpriv))
4042 else if (IS_GEN_IIE(hpriv))
4047 dev_printk(KERN_INFO, &pdev->dev,
4048 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4049 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4050 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4054 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4055 * @pdev: PCI device found
4056 * @ent: PCI device ID entry for the matched host
4059 * Inherited from caller.
4061 static int mv_pci_init_one(struct pci_dev *pdev,
4062 const struct pci_device_id *ent)
4064 static int printed_version;
4065 unsigned int board_idx = (unsigned int)ent->driver_data;
4066 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4067 struct ata_host *host;
4068 struct mv_host_priv *hpriv;
4071 if (!printed_version++)
4072 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4075 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4077 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4078 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4079 if (!host || !hpriv)
4081 host->private_data = hpriv;
4082 hpriv->n_ports = n_ports;
4084 /* acquire resources */
4085 rc = pcim_enable_device(pdev);
4089 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4091 pcim_pin_device(pdev);
4094 host->iomap = pcim_iomap_table(pdev);
4095 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4097 rc = pci_go_64(pdev);
4101 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4105 /* initialize adapter */
4106 rc = mv_init_host(host, board_idx);
4110 /* Enable message-switched interrupts, if requested */
4111 if (msi && pci_enable_msi(pdev) == 0)
4112 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4114 mv_dump_pci_cfg(pdev, 0x68);
4115 mv_print_info(host);
4117 pci_set_master(pdev);
4118 pci_try_set_mwi(pdev);
4119 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4120 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4124 static int mv_platform_probe(struct platform_device *pdev);
4125 static int __devexit mv_platform_remove(struct platform_device *pdev);
4127 static int __init mv_init(void)
4131 rc = pci_register_driver(&mv_pci_driver);
4135 rc = platform_driver_register(&mv_platform_driver);
4139 pci_unregister_driver(&mv_pci_driver);
4144 static void __exit mv_exit(void)
4147 pci_unregister_driver(&mv_pci_driver);
4149 platform_driver_unregister(&mv_platform_driver);
4152 MODULE_AUTHOR("Brett Russ");
4153 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4154 MODULE_LICENSE("GPL");
4155 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4156 MODULE_VERSION(DRV_VERSION);
4157 MODULE_ALIAS("platform:" DRV_NAME);
4159 module_init(mv_init);
4160 module_exit(mv_exit);