2 * pata_cs5536.c - CS5536 PATA for new ATA layer
3 * (C) 2007 Martin K. Petersen <mkp@mkp.net>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 * Available from AMD web site.
21 * The IDE timing registers for the CS5536 live in the Geode Machine
22 * Specific Register file and not PCI config space. Most BIOSes
23 * virtualize the PCI registers so the chip looks like a standard IDE
24 * controller. Unfortunately not all implementations get this right.
25 * In particular some have problems with unaligned accesses to the
26 * virtualized PCI registers. This driver always does full dword
27 * writes to work around the issue. Also, in case of a bad BIOS this
28 * driver can be loaded with the "msr=1" parameter which forces using
29 * the Machine Specific Registers to configure the device.
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
35 #include <linux/init.h>
36 #include <linux/blkdev.h>
37 #include <linux/delay.h>
38 #include <linux/libata.h>
39 #include <scsi/scsi_host.h>
42 #define DRV_NAME "pata_cs5536"
43 #define DRV_VERSION "0.0.7"
51 MSR_IDE_BASE = 0x51300000,
52 MSR_IDE_CFG = (MSR_IDE_BASE + 0x10),
53 MSR_IDE_DTC = (MSR_IDE_BASE + 0x12),
54 MSR_IDE_CAST = (MSR_IDE_BASE + 0x13),
55 MSR_IDE_ETC = (MSR_IDE_BASE + 0x14),
63 IDE_CFG_CABLE = 0x10000,
69 IDE_CAST_D0_SHIFT = 6,
70 IDE_CAST_D1_SHIFT = 4,
71 IDE_CAST_DRV_MASK = 0x3,
72 IDE_CAST_CMD_MASK = 0xff,
73 IDE_CAST_CMD_SHIFT = 24,
80 static const u32 msr_reg[4] = {
81 MSR_IDE_CFG, MSR_IDE_DTC, MSR_IDE_CAST, MSR_IDE_ETC,
84 static const u8 pci_reg[4] = {
85 PCI_IDE_CFG, PCI_IDE_DTC, PCI_IDE_CAST, PCI_IDE_ETC,
88 static inline int cs5536_read(struct pci_dev *pdev, int reg, u32 *val)
90 if (unlikely(use_msr)) {
93 rdmsr(msr_reg[reg], *val, dummy);
97 return pci_read_config_dword(pdev, pci_reg[reg], val);
100 static inline int cs5536_write(struct pci_dev *pdev, int reg, int val)
102 if (unlikely(use_msr)) {
103 wrmsr(msr_reg[reg], val, 0);
107 return pci_write_config_dword(pdev, pci_reg[reg], val);
111 * cs5536_cable_detect - detect cable type
112 * @ap: Port to detect on
113 * @deadline: deadline jiffies for the operation
115 * Perform cable detection for ATA66 capable cable. Return a libata
119 static int cs5536_cable_detect(struct ata_port *ap)
121 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
124 cs5536_read(pdev, CFG, &cfg);
126 if (cfg & (IDE_CFG_CABLE << ap->port_no))
127 return ATA_CBL_PATA80;
129 return ATA_CBL_PATA40;
133 * cs5536_set_piomode - PIO setup
135 * @adev: device on the interface
138 static void cs5536_set_piomode(struct ata_port *ap, struct ata_device *adev)
140 static const u8 drv_timings[5] = {
141 0x98, 0x55, 0x32, 0x21, 0x20,
144 static const u8 addr_timings[5] = {
145 0x2, 0x1, 0x0, 0x0, 0x0,
148 static const u8 cmd_timings[5] = {
149 0x99, 0x92, 0x90, 0x22, 0x20,
152 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
153 struct ata_device *pair = ata_dev_pair(adev);
154 int mode = adev->pio_mode - XFER_PIO_0;
156 int dshift = adev->devno ? IDE_D1_SHIFT : IDE_D0_SHIFT;
157 int cshift = adev->devno ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT;
161 cmdmode = min(mode, pair->pio_mode - XFER_PIO_0);
163 cs5536_read(pdev, DTC, &dtc);
164 cs5536_read(pdev, CAST, &cast);
165 cs5536_read(pdev, ETC, &etc);
167 dtc &= ~(IDE_DRV_MASK << dshift);
168 dtc |= drv_timings[mode] << dshift;
170 cast &= ~(IDE_CAST_DRV_MASK << cshift);
171 cast |= addr_timings[mode] << cshift;
173 cast &= ~(IDE_CAST_CMD_MASK << IDE_CAST_CMD_SHIFT);
174 cast |= cmd_timings[cmdmode] << IDE_CAST_CMD_SHIFT;
176 etc &= ~(IDE_DRV_MASK << dshift);
177 etc |= IDE_ETC_NODMA << dshift;
179 cs5536_write(pdev, DTC, dtc);
180 cs5536_write(pdev, CAST, cast);
181 cs5536_write(pdev, ETC, etc);
185 * cs5536_set_dmamode - DMA timing setup
187 * @adev: Device being configured
191 static void cs5536_set_dmamode(struct ata_port *ap, struct ata_device *adev)
193 static const u8 udma_timings[6] = {
194 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6,
197 static const u8 mwdma_timings[3] = {
201 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
203 int mode = adev->dma_mode;
204 int dshift = adev->devno ? IDE_D1_SHIFT : IDE_D0_SHIFT;
206 if (mode >= XFER_UDMA_0) {
207 cs5536_read(pdev, ETC, &etc);
209 etc &= ~(IDE_DRV_MASK << dshift);
210 etc |= udma_timings[mode - XFER_UDMA_0] << dshift;
212 cs5536_write(pdev, ETC, etc);
214 cs5536_read(pdev, DTC, &dtc);
216 dtc &= ~(IDE_DRV_MASK << dshift);
217 dtc |= mwdma_timings[mode - XFER_MW_DMA_0] << dshift;
219 cs5536_write(pdev, DTC, dtc);
223 static struct scsi_host_template cs5536_sht = {
224 ATA_BMDMA_SHT(DRV_NAME),
227 static struct ata_port_operations cs5536_port_ops = {
228 .set_piomode = cs5536_set_piomode,
229 .set_dmamode = cs5536_set_dmamode,
230 .mode_filter = ata_pci_default_filter,
232 .tf_load = ata_tf_load,
233 .tf_read = ata_tf_read,
234 .check_status = ata_check_status,
235 .exec_command = ata_exec_command,
236 .dev_select = ata_std_dev_select,
238 .freeze = ata_bmdma_freeze,
239 .thaw = ata_bmdma_thaw,
240 .error_handler = ata_bmdma_error_handler,
241 .post_internal_cmd = ata_bmdma_post_internal_cmd,
242 .cable_detect = cs5536_cable_detect,
244 .bmdma_setup = ata_bmdma_setup,
245 .bmdma_start = ata_bmdma_start,
246 .bmdma_stop = ata_bmdma_stop,
247 .bmdma_status = ata_bmdma_status,
249 .qc_prep = ata_qc_prep,
250 .qc_issue = ata_qc_issue_prot,
252 .data_xfer = ata_data_xfer,
254 .irq_handler = ata_interrupt,
255 .irq_clear = ata_bmdma_irq_clear,
256 .irq_on = ata_irq_on,
258 .port_start = ata_sff_port_start,
264 * @id: Entry in match table
268 static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
270 static const struct ata_port_info info = {
272 .flags = ATA_FLAG_SLAVE_POSS,
275 .udma_mask = ATA_UDMA5,
276 .port_ops = &cs5536_port_ops,
279 const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
283 printk(KERN_ERR DRV_NAME ": Using MSR regs instead of PCI\n");
285 cs5536_read(dev, CFG, &cfg);
287 if ((cfg & IDE_CFG_CHANEN) == 0) {
288 printk(KERN_ERR DRV_NAME ": disabled by BIOS\n");
292 return ata_pci_init_one(dev, ppi);
295 static const struct pci_device_id cs5536[] = {
296 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), },
300 static struct pci_driver cs5536_pci_driver = {
303 .probe = cs5536_init_one,
304 .remove = ata_pci_remove_one,
306 .suspend = ata_pci_device_suspend,
307 .resume = ata_pci_device_resume,
311 static int __init cs5536_init(void)
313 return pci_register_driver(&cs5536_pci_driver);
316 static void __exit cs5536_exit(void)
318 pci_unregister_driver(&cs5536_pci_driver);
321 MODULE_AUTHOR("Martin K. Petersen");
322 MODULE_DESCRIPTION("low-level driver for the CS5536 IDE controller");
323 MODULE_LICENSE("GPL");
324 MODULE_DEVICE_TABLE(pci, cs5536);
325 MODULE_VERSION(DRV_VERSION);
326 module_param_named(msr, use_msr, int, 0644);
327 MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)");
329 module_init(cs5536_init);
330 module_exit(cs5536_exit);