2 * libata-sff.c - helper library for PCI IDE BMDMA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
35 #include <linux/kernel.h>
36 #include <linux/pci.h>
37 #include <linux/libata.h>
38 #include <linux/highmem.h>
42 const struct ata_port_operations ata_sff_port_ops = {
43 .inherits = &ata_base_port_ops,
45 .qc_prep = ata_qc_prep,
46 .qc_issue = ata_qc_issue_prot,
48 .freeze = ata_bmdma_freeze,
49 .thaw = ata_bmdma_thaw,
50 .softreset = ata_std_softreset,
51 .error_handler = ata_bmdma_error_handler,
52 .post_internal_cmd = ata_bmdma_post_internal_cmd,
54 .dev_select = ata_std_dev_select,
55 .check_status = ata_check_status,
56 .tf_load = ata_tf_load,
57 .tf_read = ata_tf_read,
58 .exec_command = ata_exec_command,
59 .data_xfer = ata_data_xfer,
62 .port_start = ata_sff_port_start,
65 const struct ata_port_operations ata_bmdma_port_ops = {
66 .inherits = &ata_sff_port_ops,
68 .mode_filter = ata_pci_default_filter,
70 .bmdma_setup = ata_bmdma_setup,
71 .bmdma_start = ata_bmdma_start,
72 .bmdma_stop = ata_bmdma_stop,
73 .bmdma_status = ata_bmdma_status,
74 .irq_clear = ata_bmdma_irq_clear,
78 * ata_fill_sg - Fill PCI IDE PRD table
79 * @qc: Metadata associated with taskfile to be transferred
81 * Fill PCI IDE PRD (scatter-gather) table with segments
82 * associated with the current disk command.
85 * spin_lock_irqsave(host lock)
88 static void ata_fill_sg(struct ata_queued_cmd *qc)
90 struct ata_port *ap = qc->ap;
91 struct scatterlist *sg;
95 for_each_sg(qc->sg, sg, qc->n_elem, si) {
99 /* determine if physical DMA addr spans 64K boundary.
100 * Note h/w doesn't support 64-bit, so we unconditionally
101 * truncate dma_addr_t to u32.
103 addr = (u32) sg_dma_address(sg);
104 sg_len = sg_dma_len(sg);
107 offset = addr & 0xffff;
109 if ((offset + sg_len) > 0x10000)
110 len = 0x10000 - offset;
112 ap->prd[pi].addr = cpu_to_le32(addr);
113 ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
114 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
122 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
126 * ata_fill_sg_dumb - Fill PCI IDE PRD table
127 * @qc: Metadata associated with taskfile to be transferred
129 * Fill PCI IDE PRD (scatter-gather) table with segments
130 * associated with the current disk command. Perform the fill
131 * so that we avoid writing any length 64K records for
132 * controllers that don't follow the spec.
135 * spin_lock_irqsave(host lock)
138 static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
140 struct ata_port *ap = qc->ap;
141 struct scatterlist *sg;
145 for_each_sg(qc->sg, sg, qc->n_elem, si) {
147 u32 sg_len, len, blen;
149 /* determine if physical DMA addr spans 64K boundary.
150 * Note h/w doesn't support 64-bit, so we unconditionally
151 * truncate dma_addr_t to u32.
153 addr = (u32) sg_dma_address(sg);
154 sg_len = sg_dma_len(sg);
157 offset = addr & 0xffff;
159 if ((offset + sg_len) > 0x10000)
160 len = 0x10000 - offset;
163 ap->prd[pi].addr = cpu_to_le32(addr);
165 /* Some PATA chipsets like the CS5530 can't
166 cope with 0x0000 meaning 64K as the spec says */
167 ap->prd[pi].flags_len = cpu_to_le32(0x8000);
169 ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
171 ap->prd[pi].flags_len = cpu_to_le32(blen);
172 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
180 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
184 * ata_qc_prep - Prepare taskfile for submission
185 * @qc: Metadata associated with taskfile to be prepared
187 * Prepare ATA taskfile for submission.
190 * spin_lock_irqsave(host lock)
192 void ata_qc_prep(struct ata_queued_cmd *qc)
194 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
201 * ata_dumb_qc_prep - Prepare taskfile for submission
202 * @qc: Metadata associated with taskfile to be prepared
204 * Prepare ATA taskfile for submission.
207 * spin_lock_irqsave(host lock)
209 void ata_dumb_qc_prep(struct ata_queued_cmd *qc)
211 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
214 ata_fill_sg_dumb(qc);
218 * ata_check_status - Read device status reg & clear interrupt
219 * @ap: port where the device is
221 * Reads ATA taskfile status register for currently-selected device
222 * and return its value. This also clears pending interrupts
226 * Inherited from caller.
228 u8 ata_check_status(struct ata_port *ap)
230 return ioread8(ap->ioaddr.status_addr);
234 * ata_altstatus - Read device alternate status reg
235 * @ap: port where the device is
237 * Reads ATA taskfile alternate status register for
238 * currently-selected device and return its value.
240 * Note: may NOT be used as the check_altstatus() entry in
241 * ata_port_operations.
244 * Inherited from caller.
246 u8 ata_altstatus(struct ata_port *ap)
248 if (ap->ops->check_altstatus)
249 return ap->ops->check_altstatus(ap);
251 return ioread8(ap->ioaddr.altstatus_addr);
255 * ata_busy_sleep - sleep until BSY clears, or timeout
256 * @ap: port containing status register to be polled
257 * @tmout_pat: impatience timeout
258 * @tmout: overall timeout
260 * Sleep until ATA Status register bit BSY clears,
261 * or a timeout occurs.
264 * Kernel thread context (may sleep).
267 * 0 on success, -errno otherwise.
269 int ata_busy_sleep(struct ata_port *ap,
270 unsigned long tmout_pat, unsigned long tmout)
272 unsigned long timer_start, timeout;
275 status = ata_busy_wait(ap, ATA_BUSY, 300);
276 timer_start = jiffies;
277 timeout = timer_start + tmout_pat;
278 while (status != 0xff && (status & ATA_BUSY) &&
279 time_before(jiffies, timeout)) {
281 status = ata_busy_wait(ap, ATA_BUSY, 3);
284 if (status != 0xff && (status & ATA_BUSY))
285 ata_port_printk(ap, KERN_WARNING,
286 "port is slow to respond, please be patient "
287 "(Status 0x%x)\n", status);
289 timeout = timer_start + tmout;
290 while (status != 0xff && (status & ATA_BUSY) &&
291 time_before(jiffies, timeout)) {
293 status = ap->ops->check_status(ap);
299 if (status & ATA_BUSY) {
300 ata_port_printk(ap, KERN_ERR, "port failed to respond "
301 "(%lu secs, Status 0x%x)\n",
310 * ata_wait_ready - sleep until BSY clears, or timeout
311 * @ap: port containing status register to be polled
312 * @deadline: deadline jiffies for the operation
314 * Sleep until ATA Status register bit BSY clears, or timeout
318 * Kernel thread context (may sleep).
321 * 0 on success, -errno otherwise.
323 int ata_wait_ready(struct ata_port *ap, unsigned long deadline)
325 unsigned long start = jiffies;
329 u8 status = ap->ops->check_status(ap);
330 unsigned long now = jiffies;
332 if (!(status & ATA_BUSY))
334 if (!ata_link_online(&ap->link) && status == 0xff)
336 if (time_after(now, deadline))
339 if (!warned && time_after(now, start + 5 * HZ) &&
340 (deadline - now > 3 * HZ)) {
341 ata_port_printk(ap, KERN_WARNING,
342 "port is slow to respond, please be patient "
343 "(Status 0x%x)\n", status);
352 * ata_std_dev_select - Select device 0/1 on ATA bus
353 * @ap: ATA channel to manipulate
354 * @device: ATA device (numbered from zero) to select
356 * Use the method defined in the ATA specification to
357 * make either device 0, or device 1, active on the
358 * ATA channel. Works with both PIO and MMIO.
360 * May be used as the dev_select() entry in ata_port_operations.
365 void ata_std_dev_select(struct ata_port *ap, unsigned int device)
370 tmp = ATA_DEVICE_OBS;
372 tmp = ATA_DEVICE_OBS | ATA_DEV1;
374 iowrite8(tmp, ap->ioaddr.device_addr);
375 ata_pause(ap); /* needed; also flushes, for mmio */
379 * ata_dev_select - Select device 0/1 on ATA bus
380 * @ap: ATA channel to manipulate
381 * @device: ATA device (numbered from zero) to select
382 * @wait: non-zero to wait for Status register BSY bit to clear
383 * @can_sleep: non-zero if context allows sleeping
385 * Use the method defined in the ATA specification to
386 * make either device 0, or device 1, active on the
389 * This is a high-level version of ata_std_dev_select(),
390 * which additionally provides the services of inserting
391 * the proper pauses and status polling, where needed.
396 void ata_dev_select(struct ata_port *ap, unsigned int device,
397 unsigned int wait, unsigned int can_sleep)
399 if (ata_msg_probe(ap))
400 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
401 "device %u, wait %u\n", device, wait);
406 ap->ops->dev_select(ap, device);
409 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
416 * ata_irq_on - Enable interrupts on a port.
417 * @ap: Port on which interrupts are enabled.
419 * Enable interrupts on a legacy IDE device using MMIO or PIO,
420 * wait for idle, clear any pending interrupts.
423 * Inherited from caller.
425 u8 ata_irq_on(struct ata_port *ap)
427 struct ata_ioports *ioaddr = &ap->ioaddr;
430 ap->ctl &= ~ATA_NIEN;
431 ap->last_ctl = ap->ctl;
433 if (ioaddr->ctl_addr)
434 iowrite8(ap->ctl, ioaddr->ctl_addr);
435 tmp = ata_wait_idle(ap);
437 ap->ops->irq_clear(ap);
443 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
444 * @ap: Port associated with this ATA transaction.
446 * Clear interrupt and error flags in DMA status register.
448 * May be used as the irq_clear() entry in ata_port_operations.
451 * spin_lock_irqsave(host lock)
453 void ata_bmdma_irq_clear(struct ata_port *ap)
455 void __iomem *mmio = ap->ioaddr.bmdma_addr;
460 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
464 * ata_tf_load - send taskfile registers to host controller
465 * @ap: Port to which output is sent
466 * @tf: ATA taskfile register set
468 * Outputs ATA taskfile to standard ATA host controller.
471 * Inherited from caller.
473 void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
475 struct ata_ioports *ioaddr = &ap->ioaddr;
476 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
478 if (tf->ctl != ap->last_ctl) {
479 if (ioaddr->ctl_addr)
480 iowrite8(tf->ctl, ioaddr->ctl_addr);
481 ap->last_ctl = tf->ctl;
485 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
486 WARN_ON(!ioaddr->ctl_addr);
487 iowrite8(tf->hob_feature, ioaddr->feature_addr);
488 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
489 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
490 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
491 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
492 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
501 iowrite8(tf->feature, ioaddr->feature_addr);
502 iowrite8(tf->nsect, ioaddr->nsect_addr);
503 iowrite8(tf->lbal, ioaddr->lbal_addr);
504 iowrite8(tf->lbam, ioaddr->lbam_addr);
505 iowrite8(tf->lbah, ioaddr->lbah_addr);
506 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
514 if (tf->flags & ATA_TFLAG_DEVICE) {
515 iowrite8(tf->device, ioaddr->device_addr);
516 VPRINTK("device 0x%X\n", tf->device);
523 * ata_tf_read - input device's ATA taskfile shadow registers
524 * @ap: Port from which input is read
525 * @tf: ATA taskfile register set for storing input
527 * Reads ATA taskfile registers for currently-selected device
528 * into @tf. Assumes the device has a fully SFF compliant task file
529 * layout and behaviour. If you device does not (eg has a different
530 * status method) then you will need to provide a replacement tf_read
533 * Inherited from caller.
535 void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
537 struct ata_ioports *ioaddr = &ap->ioaddr;
539 tf->command = ata_check_status(ap);
540 tf->feature = ioread8(ioaddr->error_addr);
541 tf->nsect = ioread8(ioaddr->nsect_addr);
542 tf->lbal = ioread8(ioaddr->lbal_addr);
543 tf->lbam = ioread8(ioaddr->lbam_addr);
544 tf->lbah = ioread8(ioaddr->lbah_addr);
545 tf->device = ioread8(ioaddr->device_addr);
547 if (tf->flags & ATA_TFLAG_LBA48) {
548 if (likely(ioaddr->ctl_addr)) {
549 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
550 tf->hob_feature = ioread8(ioaddr->error_addr);
551 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
552 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
553 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
554 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
555 iowrite8(tf->ctl, ioaddr->ctl_addr);
556 ap->last_ctl = tf->ctl;
563 * ata_exec_command - issue ATA command to host controller
564 * @ap: port to which command is being issued
565 * @tf: ATA taskfile register set
567 * Issues ATA command, with proper synchronization with interrupt
568 * handler / other threads.
571 * spin_lock_irqsave(host lock)
573 void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
575 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
577 iowrite8(tf->command, ap->ioaddr.command_addr);
582 * ata_tf_to_host - issue ATA taskfile to host controller
583 * @ap: port to which command is being issued
584 * @tf: ATA taskfile register set
586 * Issues ATA taskfile register set to ATA host controller,
587 * with proper synchronization with interrupt handler and
591 * spin_lock_irqsave(host lock)
593 static inline void ata_tf_to_host(struct ata_port *ap,
594 const struct ata_taskfile *tf)
596 ap->ops->tf_load(ap, tf);
597 ap->ops->exec_command(ap, tf);
601 * ata_data_xfer - Transfer data by PIO
602 * @dev: device to target
604 * @buflen: buffer length
607 * Transfer data from/to the device data register by PIO.
610 * Inherited from caller.
615 unsigned int ata_data_xfer(struct ata_device *dev, unsigned char *buf,
616 unsigned int buflen, int rw)
618 struct ata_port *ap = dev->link->ap;
619 void __iomem *data_addr = ap->ioaddr.data_addr;
620 unsigned int words = buflen >> 1;
622 /* Transfer multiple of 2 bytes */
624 ioread16_rep(data_addr, buf, words);
626 iowrite16_rep(data_addr, buf, words);
628 /* Transfer trailing 1 byte, if any. */
629 if (unlikely(buflen & 0x01)) {
630 __le16 align_buf[1] = { 0 };
631 unsigned char *trailing_buf = buf + buflen - 1;
634 align_buf[0] = cpu_to_le16(ioread16(data_addr));
635 memcpy(trailing_buf, align_buf, 1);
637 memcpy(align_buf, trailing_buf, 1);
638 iowrite16(le16_to_cpu(align_buf[0]), data_addr);
647 * ata_data_xfer_noirq - Transfer data by PIO
648 * @dev: device to target
650 * @buflen: buffer length
653 * Transfer data from/to the device data register by PIO. Do the
654 * transfer with interrupts disabled.
657 * Inherited from caller.
662 unsigned int ata_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
663 unsigned int buflen, int rw)
666 unsigned int consumed;
668 local_irq_save(flags);
669 consumed = ata_data_xfer(dev, buf, buflen, rw);
670 local_irq_restore(flags);
676 * ata_pio_sector - Transfer a sector of data.
677 * @qc: Command on going
679 * Transfer qc->sect_size bytes of data from/to the ATA device.
682 * Inherited from caller.
684 static void ata_pio_sector(struct ata_queued_cmd *qc)
686 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
687 struct ata_port *ap = qc->ap;
692 if (qc->curbytes == qc->nbytes - qc->sect_size)
693 ap->hsm_task_state = HSM_ST_LAST;
695 page = sg_page(qc->cursg);
696 offset = qc->cursg->offset + qc->cursg_ofs;
698 /* get the current page and offset */
699 page = nth_page(page, (offset >> PAGE_SHIFT));
702 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
704 if (PageHighMem(page)) {
707 /* FIXME: use a bounce buffer */
708 local_irq_save(flags);
709 buf = kmap_atomic(page, KM_IRQ0);
711 /* do the actual data transfer */
712 ap->ops->data_xfer(qc->dev, buf + offset, qc->sect_size, do_write);
714 kunmap_atomic(buf, KM_IRQ0);
715 local_irq_restore(flags);
717 buf = page_address(page);
718 ap->ops->data_xfer(qc->dev, buf + offset, qc->sect_size, do_write);
721 qc->curbytes += qc->sect_size;
722 qc->cursg_ofs += qc->sect_size;
724 if (qc->cursg_ofs == qc->cursg->length) {
725 qc->cursg = sg_next(qc->cursg);
731 * ata_pio_sectors - Transfer one or many sectors.
732 * @qc: Command on going
734 * Transfer one or many sectors of data from/to the
735 * ATA device for the DRQ request.
738 * Inherited from caller.
740 static void ata_pio_sectors(struct ata_queued_cmd *qc)
742 if (is_multi_taskfile(&qc->tf)) {
743 /* READ/WRITE MULTIPLE */
746 WARN_ON(qc->dev->multi_count == 0);
748 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
749 qc->dev->multi_count);
755 ata_altstatus(qc->ap); /* flush */
759 * atapi_send_cdb - Write CDB bytes to hardware
760 * @ap: Port to which ATAPI device is attached.
761 * @qc: Taskfile currently active
763 * When device has indicated its readiness to accept
764 * a CDB, this function is called. Send the CDB.
769 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
772 DPRINTK("send cdb\n");
773 WARN_ON(qc->dev->cdb_len < 12);
775 ap->ops->data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
776 ata_altstatus(ap); /* flush */
778 switch (qc->tf.protocol) {
780 ap->hsm_task_state = HSM_ST;
782 case ATAPI_PROT_NODATA:
783 ap->hsm_task_state = HSM_ST_LAST;
786 ap->hsm_task_state = HSM_ST_LAST;
788 ap->ops->bmdma_start(qc);
794 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
795 * @qc: Command on going
796 * @bytes: number of bytes
798 * Transfer Transfer data from/to the ATAPI device.
801 * Inherited from caller.
804 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
806 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
807 struct ata_port *ap = qc->ap;
808 struct ata_device *dev = qc->dev;
809 struct ata_eh_info *ehi = &dev->link->eh_info;
810 struct scatterlist *sg;
813 unsigned int offset, count, consumed;
818 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
819 "buf=%u cur=%u bytes=%u",
820 qc->nbytes, qc->curbytes, bytes);
825 offset = sg->offset + qc->cursg_ofs;
827 /* get the current page and offset */
828 page = nth_page(page, (offset >> PAGE_SHIFT));
831 /* don't overrun current sg */
832 count = min(sg->length - qc->cursg_ofs, bytes);
834 /* don't cross page boundaries */
835 count = min(count, (unsigned int)PAGE_SIZE - offset);
837 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
839 if (PageHighMem(page)) {
842 /* FIXME: use bounce buffer */
843 local_irq_save(flags);
844 buf = kmap_atomic(page, KM_IRQ0);
846 /* do the actual data transfer */
847 consumed = ap->ops->data_xfer(dev, buf + offset, count, rw);
849 kunmap_atomic(buf, KM_IRQ0);
850 local_irq_restore(flags);
852 buf = page_address(page);
853 consumed = ap->ops->data_xfer(dev, buf + offset, count, rw);
856 bytes -= min(bytes, consumed);
857 qc->curbytes += count;
858 qc->cursg_ofs += count;
860 if (qc->cursg_ofs == sg->length) {
861 qc->cursg = sg_next(qc->cursg);
865 /* consumed can be larger than count only for the last transfer */
866 WARN_ON(qc->cursg && count != consumed);
874 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
875 * @qc: Command on going
877 * Transfer Transfer data from/to the ATAPI device.
880 * Inherited from caller.
882 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
884 struct ata_port *ap = qc->ap;
885 struct ata_device *dev = qc->dev;
886 struct ata_eh_info *ehi = &dev->link->eh_info;
887 unsigned int ireason, bc_lo, bc_hi, bytes;
888 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
890 /* Abuse qc->result_tf for temp storage of intermediate TF
891 * here to save some kernel stack usage.
892 * For normal completion, qc->result_tf is not relevant. For
893 * error, qc->result_tf is later overwritten by ata_qc_complete().
894 * So, the correctness of qc->result_tf is not affected.
896 ap->ops->tf_read(ap, &qc->result_tf);
897 ireason = qc->result_tf.nsect;
898 bc_lo = qc->result_tf.lbam;
899 bc_hi = qc->result_tf.lbah;
900 bytes = (bc_hi << 8) | bc_lo;
902 /* shall be cleared to zero, indicating xfer of data */
903 if (unlikely(ireason & (1 << 0)))
906 /* make sure transfer direction matches expected */
907 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
908 if (unlikely(do_write != i_write))
911 if (unlikely(!bytes))
914 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
916 if (unlikely(__atapi_pio_bytes(qc, bytes)))
918 ata_altstatus(ap); /* flush */
923 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
926 qc->err_mask |= AC_ERR_HSM;
927 ap->hsm_task_state = HSM_ST_ERR;
931 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
932 * @ap: the target ata_port
936 * 1 if ok in workqueue, 0 otherwise.
938 static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
940 if (qc->tf.flags & ATA_TFLAG_POLLING)
943 if (ap->hsm_task_state == HSM_ST_FIRST) {
944 if (qc->tf.protocol == ATA_PROT_PIO &&
945 (qc->tf.flags & ATA_TFLAG_WRITE))
948 if (ata_is_atapi(qc->tf.protocol) &&
949 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
957 * ata_hsm_qc_complete - finish a qc running on standard HSM
958 * @qc: Command to complete
959 * @in_wq: 1 if called from workqueue, 0 otherwise
961 * Finish @qc which is running on standard HSM.
964 * If @in_wq is zero, spin_lock_irqsave(host lock).
965 * Otherwise, none on entry and grabs host lock.
967 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
969 struct ata_port *ap = qc->ap;
972 if (ap->ops->error_handler) {
974 spin_lock_irqsave(ap->lock, flags);
976 /* EH might have kicked in while host lock is
979 qc = ata_qc_from_tag(ap, qc->tag);
981 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
988 spin_unlock_irqrestore(ap->lock, flags);
990 if (likely(!(qc->err_mask & AC_ERR_HSM)))
997 spin_lock_irqsave(ap->lock, flags);
1000 spin_unlock_irqrestore(ap->lock, flags);
1002 ata_qc_complete(qc);
1007 * ata_hsm_move - move the HSM to the next state.
1008 * @ap: the target ata_port
1010 * @status: current device status
1011 * @in_wq: 1 if called from workqueue, 0 otherwise
1014 * 1 when poll next status needed, 0 otherwise.
1016 int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1017 u8 status, int in_wq)
1019 unsigned long flags = 0;
1022 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1024 /* Make sure ata_qc_issue_prot() does not throw things
1025 * like DMA polling into the workqueue. Notice that
1026 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1028 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
1031 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1032 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1034 switch (ap->hsm_task_state) {
1036 /* Send first data block or PACKET CDB */
1038 /* If polling, we will stay in the work queue after
1039 * sending the data. Otherwise, interrupt handler
1040 * takes over after sending the data.
1042 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1044 /* check device status */
1045 if (unlikely((status & ATA_DRQ) == 0)) {
1046 /* handle BSY=0, DRQ=0 as error */
1047 if (likely(status & (ATA_ERR | ATA_DF)))
1048 /* device stops HSM for abort/error */
1049 qc->err_mask |= AC_ERR_DEV;
1051 /* HSM violation. Let EH handle this */
1052 qc->err_mask |= AC_ERR_HSM;
1054 ap->hsm_task_state = HSM_ST_ERR;
1058 /* Device should not ask for data transfer (DRQ=1)
1059 * when it finds something wrong.
1060 * We ignore DRQ here and stop the HSM by
1061 * changing hsm_task_state to HSM_ST_ERR and
1062 * let the EH abort the command or reset the device.
1064 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1065 /* Some ATAPI tape drives forget to clear the ERR bit
1066 * when doing the next command (mostly request sense).
1067 * We ignore ERR here to workaround and proceed sending
1070 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1071 ata_port_printk(ap, KERN_WARNING,
1072 "DRQ=1 with device error, "
1073 "dev_stat 0x%X\n", status);
1074 qc->err_mask |= AC_ERR_HSM;
1075 ap->hsm_task_state = HSM_ST_ERR;
1080 /* Send the CDB (atapi) or the first data block (ata pio out).
1081 * During the state transition, interrupt handler shouldn't
1082 * be invoked before the data transfer is complete and
1083 * hsm_task_state is changed. Hence, the following locking.
1086 spin_lock_irqsave(ap->lock, flags);
1088 if (qc->tf.protocol == ATA_PROT_PIO) {
1089 /* PIO data out protocol.
1090 * send first data block.
1093 /* ata_pio_sectors() might change the state
1094 * to HSM_ST_LAST. so, the state is changed here
1095 * before ata_pio_sectors().
1097 ap->hsm_task_state = HSM_ST;
1098 ata_pio_sectors(qc);
1101 atapi_send_cdb(ap, qc);
1104 spin_unlock_irqrestore(ap->lock, flags);
1106 /* if polling, ata_pio_task() handles the rest.
1107 * otherwise, interrupt handler takes over from here.
1112 /* complete command or read/write the data register */
1113 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1114 /* ATAPI PIO protocol */
1115 if ((status & ATA_DRQ) == 0) {
1116 /* No more data to transfer or device error.
1117 * Device error will be tagged in HSM_ST_LAST.
1119 ap->hsm_task_state = HSM_ST_LAST;
1123 /* Device should not ask for data transfer (DRQ=1)
1124 * when it finds something wrong.
1125 * We ignore DRQ here and stop the HSM by
1126 * changing hsm_task_state to HSM_ST_ERR and
1127 * let the EH abort the command or reset the device.
1129 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1130 ata_port_printk(ap, KERN_WARNING, "DRQ=1 with "
1131 "device error, dev_stat 0x%X\n",
1133 qc->err_mask |= AC_ERR_HSM;
1134 ap->hsm_task_state = HSM_ST_ERR;
1138 atapi_pio_bytes(qc);
1140 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1141 /* bad ireason reported by device */
1145 /* ATA PIO protocol */
1146 if (unlikely((status & ATA_DRQ) == 0)) {
1147 /* handle BSY=0, DRQ=0 as error */
1148 if (likely(status & (ATA_ERR | ATA_DF)))
1149 /* device stops HSM for abort/error */
1150 qc->err_mask |= AC_ERR_DEV;
1152 /* HSM violation. Let EH handle this.
1153 * Phantom devices also trigger this
1154 * condition. Mark hint.
1156 qc->err_mask |= AC_ERR_HSM |
1159 ap->hsm_task_state = HSM_ST_ERR;
1163 /* For PIO reads, some devices may ask for
1164 * data transfer (DRQ=1) alone with ERR=1.
1165 * We respect DRQ here and transfer one
1166 * block of junk data before changing the
1167 * hsm_task_state to HSM_ST_ERR.
1169 * For PIO writes, ERR=1 DRQ=1 doesn't make
1170 * sense since the data block has been
1171 * transferred to the device.
1173 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1174 /* data might be corrputed */
1175 qc->err_mask |= AC_ERR_DEV;
1177 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1178 ata_pio_sectors(qc);
1179 status = ata_wait_idle(ap);
1182 if (status & (ATA_BUSY | ATA_DRQ))
1183 qc->err_mask |= AC_ERR_HSM;
1185 /* ata_pio_sectors() might change the
1186 * state to HSM_ST_LAST. so, the state
1187 * is changed after ata_pio_sectors().
1189 ap->hsm_task_state = HSM_ST_ERR;
1193 ata_pio_sectors(qc);
1195 if (ap->hsm_task_state == HSM_ST_LAST &&
1196 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1198 status = ata_wait_idle(ap);
1207 if (unlikely(!ata_ok(status))) {
1208 qc->err_mask |= __ac_err_mask(status);
1209 ap->hsm_task_state = HSM_ST_ERR;
1213 /* no more data to transfer */
1214 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1215 ap->print_id, qc->dev->devno, status);
1217 WARN_ON(qc->err_mask);
1219 ap->hsm_task_state = HSM_ST_IDLE;
1221 /* complete taskfile transaction */
1222 ata_hsm_qc_complete(qc, in_wq);
1228 /* make sure qc->err_mask is available to
1229 * know what's wrong and recover
1231 WARN_ON(qc->err_mask == 0);
1233 ap->hsm_task_state = HSM_ST_IDLE;
1235 /* complete taskfile transaction */
1236 ata_hsm_qc_complete(qc, in_wq);
1248 void ata_pio_task(struct work_struct *work)
1250 struct ata_port *ap =
1251 container_of(work, struct ata_port, port_task.work);
1252 struct ata_queued_cmd *qc = ap->port_task_data;
1257 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
1260 * This is purely heuristic. This is a fast path.
1261 * Sometimes when we enter, BSY will be cleared in
1262 * a chk-status or two. If not, the drive is probably seeking
1263 * or something. Snooze for a couple msecs, then
1264 * chk-status again. If still busy, queue delayed work.
1266 status = ata_busy_wait(ap, ATA_BUSY, 5);
1267 if (status & ATA_BUSY) {
1269 status = ata_busy_wait(ap, ATA_BUSY, 10);
1270 if (status & ATA_BUSY) {
1271 ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
1277 poll_next = ata_hsm_move(ap, qc, status, 1);
1279 /* another command or interrupt handler
1280 * may be running at this point.
1287 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
1288 * @qc: command to issue to device
1290 * Using various libata functions and hooks, this function
1291 * starts an ATA command. ATA commands are grouped into
1292 * classes called "protocols", and issuing each type of protocol
1293 * is slightly different.
1295 * May be used as the qc_issue() entry in ata_port_operations.
1298 * spin_lock_irqsave(host lock)
1301 * Zero on success, AC_ERR_* mask on failure
1303 unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1305 struct ata_port *ap = qc->ap;
1307 /* Use polling pio if the LLD doesn't handle
1308 * interrupt driven pio and atapi CDB interrupt.
1310 if (ap->flags & ATA_FLAG_PIO_POLLING) {
1311 switch (qc->tf.protocol) {
1313 case ATA_PROT_NODATA:
1314 case ATAPI_PROT_PIO:
1315 case ATAPI_PROT_NODATA:
1316 qc->tf.flags |= ATA_TFLAG_POLLING;
1318 case ATAPI_PROT_DMA:
1319 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1320 /* see ata_dma_blacklisted() */
1328 /* select the device */
1329 ata_dev_select(ap, qc->dev->devno, 1, 0);
1331 /* start the command */
1332 switch (qc->tf.protocol) {
1333 case ATA_PROT_NODATA:
1334 if (qc->tf.flags & ATA_TFLAG_POLLING)
1335 ata_qc_set_polling(qc);
1337 ata_tf_to_host(ap, &qc->tf);
1338 ap->hsm_task_state = HSM_ST_LAST;
1340 if (qc->tf.flags & ATA_TFLAG_POLLING)
1341 ata_pio_queue_task(ap, qc, 0);
1346 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1348 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
1349 ap->ops->bmdma_setup(qc); /* set up bmdma */
1350 ap->ops->bmdma_start(qc); /* initiate bmdma */
1351 ap->hsm_task_state = HSM_ST_LAST;
1355 if (qc->tf.flags & ATA_TFLAG_POLLING)
1356 ata_qc_set_polling(qc);
1358 ata_tf_to_host(ap, &qc->tf);
1360 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1361 /* PIO data out protocol */
1362 ap->hsm_task_state = HSM_ST_FIRST;
1363 ata_pio_queue_task(ap, qc, 0);
1365 /* always send first data block using
1366 * the ata_pio_task() codepath.
1369 /* PIO data in protocol */
1370 ap->hsm_task_state = HSM_ST;
1372 if (qc->tf.flags & ATA_TFLAG_POLLING)
1373 ata_pio_queue_task(ap, qc, 0);
1375 /* if polling, ata_pio_task() handles the rest.
1376 * otherwise, interrupt handler takes over from here.
1382 case ATAPI_PROT_PIO:
1383 case ATAPI_PROT_NODATA:
1384 if (qc->tf.flags & ATA_TFLAG_POLLING)
1385 ata_qc_set_polling(qc);
1387 ata_tf_to_host(ap, &qc->tf);
1389 ap->hsm_task_state = HSM_ST_FIRST;
1391 /* send cdb by polling if no cdb interrupt */
1392 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1393 (qc->tf.flags & ATA_TFLAG_POLLING))
1394 ata_pio_queue_task(ap, qc, 0);
1397 case ATAPI_PROT_DMA:
1398 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1400 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
1401 ap->ops->bmdma_setup(qc); /* set up bmdma */
1402 ap->hsm_task_state = HSM_ST_FIRST;
1404 /* send cdb by polling if no cdb interrupt */
1405 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1406 ata_pio_queue_task(ap, qc, 0);
1411 return AC_ERR_SYSTEM;
1418 * ata_host_intr - Handle host interrupt for given (port, task)
1419 * @ap: Port on which interrupt arrived (possibly...)
1420 * @qc: Taskfile currently active in engine
1422 * Handle host interrupt for given queued command. Currently,
1423 * only DMA interrupts are handled. All other commands are
1424 * handled via polling with interrupts disabled (nIEN bit).
1427 * spin_lock_irqsave(host lock)
1430 * One if interrupt was handled, zero if not (shared irq).
1432 inline unsigned int ata_host_intr(struct ata_port *ap,
1433 struct ata_queued_cmd *qc)
1435 struct ata_eh_info *ehi = &ap->link.eh_info;
1436 u8 status, host_stat = 0;
1438 VPRINTK("ata%u: protocol %d task_state %d\n",
1439 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1441 /* Check whether we are expecting interrupt in this state */
1442 switch (ap->hsm_task_state) {
1444 /* Some pre-ATAPI-4 devices assert INTRQ
1445 * at this state when ready to receive CDB.
1448 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1449 * The flag was turned on only for atapi devices. No
1450 * need to check ata_is_atapi(qc->tf.protocol) again.
1452 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1456 if (qc->tf.protocol == ATA_PROT_DMA ||
1457 qc->tf.protocol == ATAPI_PROT_DMA) {
1458 /* check status of DMA engine */
1459 host_stat = ap->ops->bmdma_status(ap);
1460 VPRINTK("ata%u: host_stat 0x%X\n",
1461 ap->print_id, host_stat);
1463 /* if it's not our irq... */
1464 if (!(host_stat & ATA_DMA_INTR))
1467 /* before we do anything else, clear DMA-Start bit */
1468 ap->ops->bmdma_stop(qc);
1470 if (unlikely(host_stat & ATA_DMA_ERR)) {
1471 /* error when transfering data to/from memory */
1472 qc->err_mask |= AC_ERR_HOST_BUS;
1473 ap->hsm_task_state = HSM_ST_ERR;
1483 /* check altstatus */
1484 status = ata_altstatus(ap);
1485 if (status & ATA_BUSY)
1488 /* check main status, clearing INTRQ */
1489 status = ap->ops->check_status(ap);
1490 if (unlikely(status & ATA_BUSY))
1493 /* ack bmdma irq events */
1494 ap->ops->irq_clear(ap);
1496 ata_hsm_move(ap, qc, status, 0);
1498 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1499 qc->tf.protocol == ATAPI_PROT_DMA))
1500 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1502 return 1; /* irq handled */
1505 ap->stats.idle_irq++;
1508 if ((ap->stats.idle_irq % 1000) == 0) {
1509 ap->ops->check_status(ap);
1510 ap->ops->irq_clear(ap);
1511 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1515 return 0; /* irq not handled */
1519 * ata_interrupt - Default ATA host interrupt handler
1520 * @irq: irq line (unused)
1521 * @dev_instance: pointer to our ata_host information structure
1523 * Default interrupt handler for PCI IDE devices. Calls
1524 * ata_host_intr() for each port that is not disabled.
1527 * Obtains host lock during operation.
1530 * IRQ_NONE or IRQ_HANDLED.
1532 irqreturn_t ata_interrupt(int irq, void *dev_instance)
1534 struct ata_host *host = dev_instance;
1536 unsigned int handled = 0;
1537 unsigned long flags;
1539 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1540 spin_lock_irqsave(&host->lock, flags);
1542 for (i = 0; i < host->n_ports; i++) {
1543 struct ata_port *ap;
1545 ap = host->ports[i];
1547 !(ap->flags & ATA_FLAG_DISABLED)) {
1548 struct ata_queued_cmd *qc;
1550 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1551 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
1552 (qc->flags & ATA_QCFLAG_ACTIVE))
1553 handled |= ata_host_intr(ap, qc);
1557 spin_unlock_irqrestore(&host->lock, flags);
1559 return IRQ_RETVAL(handled);
1563 * ata_bmdma_freeze - Freeze BMDMA controller port
1564 * @ap: port to freeze
1566 * Freeze BMDMA controller port.
1569 * Inherited from caller.
1571 void ata_bmdma_freeze(struct ata_port *ap)
1573 struct ata_ioports *ioaddr = &ap->ioaddr;
1575 ap->ctl |= ATA_NIEN;
1576 ap->last_ctl = ap->ctl;
1578 if (ioaddr->ctl_addr)
1579 iowrite8(ap->ctl, ioaddr->ctl_addr);
1581 /* Under certain circumstances, some controllers raise IRQ on
1582 * ATA_NIEN manipulation. Also, many controllers fail to mask
1583 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1585 ap->ops->check_status(ap);
1587 ap->ops->irq_clear(ap);
1591 * ata_bmdma_thaw - Thaw BMDMA controller port
1594 * Thaw BMDMA controller port.
1597 * Inherited from caller.
1599 void ata_bmdma_thaw(struct ata_port *ap)
1601 /* clear & re-enable interrupts */
1602 ap->ops->check_status(ap);
1603 ap->ops->irq_clear(ap);
1604 ap->ops->irq_on(ap);
1608 * ata_devchk - PATA device presence detection
1609 * @ap: ATA channel to examine
1610 * @device: Device to examine (starting at zero)
1612 * This technique was originally described in
1613 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1614 * later found its way into the ATA/ATAPI spec.
1616 * Write a pattern to the ATA shadow registers,
1617 * and if a device is present, it will respond by
1618 * correctly storing and echoing back the
1619 * ATA shadow register contents.
1624 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1626 struct ata_ioports *ioaddr = &ap->ioaddr;
1629 ap->ops->dev_select(ap, device);
1631 iowrite8(0x55, ioaddr->nsect_addr);
1632 iowrite8(0xaa, ioaddr->lbal_addr);
1634 iowrite8(0xaa, ioaddr->nsect_addr);
1635 iowrite8(0x55, ioaddr->lbal_addr);
1637 iowrite8(0x55, ioaddr->nsect_addr);
1638 iowrite8(0xaa, ioaddr->lbal_addr);
1640 nsect = ioread8(ioaddr->nsect_addr);
1641 lbal = ioread8(ioaddr->lbal_addr);
1643 if ((nsect == 0x55) && (lbal == 0xaa))
1644 return 1; /* we found a device */
1646 return 0; /* nothing found */
1650 * ata_dev_try_classify - Parse returned ATA device signature
1651 * @dev: ATA device to classify (starting at zero)
1652 * @present: device seems present
1653 * @r_err: Value of error register on completion
1655 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1656 * an ATA/ATAPI-defined set of values is placed in the ATA
1657 * shadow registers, indicating the results of device detection
1660 * Select the ATA device, and read the values from the ATA shadow
1661 * registers. Then parse according to the Error register value,
1662 * and the spec-defined values examined by ata_dev_classify().
1668 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1670 unsigned int ata_dev_try_classify(struct ata_device *dev, int present,
1673 struct ata_port *ap = dev->link->ap;
1674 struct ata_taskfile tf;
1678 ap->ops->dev_select(ap, dev->devno);
1680 memset(&tf, 0, sizeof(tf));
1682 ap->ops->tf_read(ap, &tf);
1687 /* see if device passed diags: continue and warn later */
1689 /* diagnostic fail : do nothing _YET_ */
1690 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1693 else if ((dev->devno == 0) && (err == 0x81))
1696 return ATA_DEV_NONE;
1698 /* determine if device is ATA or ATAPI */
1699 class = ata_dev_classify(&tf);
1701 if (class == ATA_DEV_UNKNOWN) {
1702 /* If the device failed diagnostic, it's likely to
1703 * have reported incorrect device signature too.
1704 * Assume ATA device if the device seems present but
1705 * device signature is invalid with diagnostic
1708 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1709 class = ATA_DEV_ATA;
1711 class = ATA_DEV_NONE;
1712 } else if ((class == ATA_DEV_ATA) && (ap->ops->check_status(ap) == 0))
1713 class = ATA_DEV_NONE;
1718 static int ata_bus_post_reset(struct ata_port *ap, unsigned int devmask,
1719 unsigned long deadline)
1721 struct ata_ioports *ioaddr = &ap->ioaddr;
1722 unsigned int dev0 = devmask & (1 << 0);
1723 unsigned int dev1 = devmask & (1 << 1);
1726 /* if device 0 was found in ata_devchk, wait for its
1730 rc = ata_wait_ready(ap, deadline);
1738 /* if device 1 was found in ata_devchk, wait for register
1739 * access briefly, then wait for BSY to clear.
1744 ap->ops->dev_select(ap, 1);
1746 /* Wait for register access. Some ATAPI devices fail
1747 * to set nsect/lbal after reset, so don't waste too
1748 * much time on it. We're gonna wait for !BSY anyway.
1750 for (i = 0; i < 2; i++) {
1753 nsect = ioread8(ioaddr->nsect_addr);
1754 lbal = ioread8(ioaddr->lbal_addr);
1755 if ((nsect == 1) && (lbal == 1))
1757 msleep(50); /* give drive a breather */
1760 rc = ata_wait_ready(ap, deadline);
1768 /* is all this really necessary? */
1769 ap->ops->dev_select(ap, 0);
1771 ap->ops->dev_select(ap, 1);
1773 ap->ops->dev_select(ap, 0);
1779 * ata_wait_after_reset - wait before checking status after reset
1780 * @ap: port containing status register to be polled
1781 * @deadline: deadline jiffies for the operation
1783 * After reset, we need to pause a while before reading status.
1784 * Also, certain combination of controller and device report 0xff
1785 * for some duration (e.g. until SATA PHY is up and running)
1786 * which is interpreted as empty port in ATA world. This
1787 * function also waits for such devices to get out of 0xff
1791 * Kernel thread context (may sleep).
1793 void ata_wait_after_reset(struct ata_port *ap, unsigned long deadline)
1795 unsigned long until = jiffies + ATA_TMOUT_FF_WAIT;
1797 if (time_before(until, deadline))
1800 /* Spec mandates ">= 2ms" before checking status. We wait
1801 * 150ms, because that was the magic delay used for ATAPI
1802 * devices in Hale Landis's ATADRVR, for the period of time
1803 * between when the ATA command register is written, and then
1804 * status is checked. Because waiting for "a while" before
1805 * checking status is fine, post SRST, we perform this magic
1806 * delay here as well.
1808 * Old drivers/ide uses the 2mS rule and then waits for ready.
1812 /* Wait for 0xff to clear. Some SATA devices take a long time
1813 * to clear 0xff after reset. For example, HHD424020F7SV00
1814 * iVDR needs >= 800ms while. Quantum GoVault needs even more
1817 * Note that some PATA controllers (pata_ali) explode if
1818 * status register is read more than once when there's no
1821 if (ap->flags & ATA_FLAG_SATA) {
1823 u8 status = ap->ops->check_status(ap);
1825 if (status != 0xff || time_after(jiffies, deadline))
1833 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1834 unsigned long deadline)
1836 struct ata_ioports *ioaddr = &ap->ioaddr;
1838 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
1840 /* software reset. causes dev0 to be selected */
1841 iowrite8(ap->ctl, ioaddr->ctl_addr);
1842 udelay(20); /* FIXME: flush */
1843 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1844 udelay(20); /* FIXME: flush */
1845 iowrite8(ap->ctl, ioaddr->ctl_addr);
1847 /* wait a while before checking status */
1848 ata_wait_after_reset(ap, deadline);
1850 /* Before we perform post reset processing we want to see if
1851 * the bus shows 0xFF because the odd clown forgets the D7
1852 * pulldown resistor.
1854 if (ap->ops->check_status(ap) == 0xFF)
1857 return ata_bus_post_reset(ap, devmask, deadline);
1861 * ata_std_softreset - reset host port via ATA SRST
1862 * @link: ATA link to reset
1863 * @classes: resulting classes of attached devices
1864 * @deadline: deadline jiffies for the operation
1866 * Reset host port using ATA SRST.
1869 * Kernel thread context (may sleep)
1872 * 0 on success, -errno otherwise.
1874 int ata_std_softreset(struct ata_link *link, unsigned int *classes,
1875 unsigned long deadline)
1877 struct ata_port *ap = link->ap;
1878 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1879 unsigned int devmask = 0;
1885 if (ata_link_offline(link)) {
1886 classes[0] = ATA_DEV_NONE;
1890 /* determine if device 0/1 are present */
1891 if (ata_devchk(ap, 0))
1892 devmask |= (1 << 0);
1893 if (slave_possible && ata_devchk(ap, 1))
1894 devmask |= (1 << 1);
1896 /* select device 0 again */
1897 ap->ops->dev_select(ap, 0);
1899 /* issue bus reset */
1900 DPRINTK("about to softreset, devmask=%x\n", devmask);
1901 rc = ata_bus_softreset(ap, devmask, deadline);
1902 /* if link is occupied, -ENODEV too is an error */
1903 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1904 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
1908 /* determine by signature whether we have ATA or ATAPI devices */
1909 classes[0] = ata_dev_try_classify(&link->device[0],
1910 devmask & (1 << 0), &err);
1911 if (slave_possible && err != 0x81)
1912 classes[1] = ata_dev_try_classify(&link->device[1],
1913 devmask & (1 << 1), &err);
1916 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
1921 * sata_std_hardreset - reset host port via SATA phy reset
1922 * @link: link to reset
1923 * @class: resulting class of attached device
1924 * @deadline: deadline jiffies for the operation
1926 * SATA phy-reset host port using DET bits of SControl register,
1927 * wait for !BSY and classify the attached device.
1930 * Kernel thread context (may sleep)
1933 * 0 on success, -errno otherwise.
1935 int sata_std_hardreset(struct ata_link *link, unsigned int *class,
1936 unsigned long deadline)
1938 struct ata_port *ap = link->ap;
1939 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1945 rc = sata_link_hardreset(link, timing, deadline);
1947 ata_link_printk(link, KERN_ERR,
1948 "COMRESET failed (errno=%d)\n", rc);
1952 /* TODO: phy layer with polling, timeouts, etc. */
1953 if (ata_link_offline(link)) {
1954 *class = ATA_DEV_NONE;
1955 DPRINTK("EXIT, link offline\n");
1959 /* wait a while before checking status */
1960 ata_wait_after_reset(ap, deadline);
1962 /* If PMP is supported, we have to do follow-up SRST. Note
1963 * that some PMPs don't send D2H Reg FIS after hardreset at
1964 * all if the first port is empty. Wait for it just for a
1965 * second and request follow-up SRST.
1967 if (ap->flags & ATA_FLAG_PMP) {
1968 ata_wait_ready(ap, jiffies + HZ);
1972 rc = ata_wait_ready(ap, deadline);
1973 /* link occupied, -ENODEV too is an error */
1975 ata_link_printk(link, KERN_ERR,
1976 "COMRESET failed (errno=%d)\n", rc);
1980 ap->ops->dev_select(ap, 0); /* probably unnecessary */
1982 *class = ata_dev_try_classify(link->device, 1, NULL);
1984 DPRINTK("EXIT, class=%u\n", *class);
1989 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
1990 * @ap: port to handle error for
1992 * Stock error handler for BMDMA controller. It can handle both
1993 * PATA and SATA controllers. Many controllers should be able to
1994 * use this EH as-is or with some added handling before and
1998 * Kernel thread context (may sleep)
2000 void ata_bmdma_error_handler(struct ata_port *ap)
2002 ata_reset_fn_t softreset = ap->ops->softreset;
2003 ata_reset_fn_t hardreset = ap->ops->hardreset;
2004 struct ata_queued_cmd *qc;
2005 unsigned long flags;
2008 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2009 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2012 /* reset PIO HSM and stop DMA engine */
2013 spin_lock_irqsave(ap->lock, flags);
2015 ap->hsm_task_state = HSM_ST_IDLE;
2017 if (ap->ioaddr.bmdma_addr &&
2018 qc && (qc->tf.protocol == ATA_PROT_DMA ||
2019 qc->tf.protocol == ATAPI_PROT_DMA)) {
2022 host_stat = ap->ops->bmdma_status(ap);
2024 /* BMDMA controllers indicate host bus error by
2025 * setting DMA_ERR bit and timing out. As it wasn't
2026 * really a timeout event, adjust error mask and
2027 * cancel frozen state.
2029 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2030 qc->err_mask = AC_ERR_HOST_BUS;
2034 ap->ops->bmdma_stop(qc);
2038 ap->ops->check_status(ap);
2039 ap->ops->irq_clear(ap);
2041 spin_unlock_irqrestore(ap->lock, flags);
2044 ata_eh_thaw_port(ap);
2046 /* PIO and DMA engines have been stopped, perform recovery */
2048 /* ata_std_softreset and sata_std_hardreset are inherited to
2049 * all SFF drivers from ata_sff_port_ops. Ignore softreset if
2050 * ctl isn't accessible. Ignore hardreset if SCR access isn't
2053 if (softreset == ata_std_softreset && !ap->ioaddr.ctl_addr)
2055 if (hardreset == sata_std_hardreset && !sata_scr_valid(&ap->link))
2058 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2059 ap->ops->postreset);
2063 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for
2065 * @qc: internal command to clean up
2068 * Kernel thread context (may sleep)
2070 void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
2072 if (qc->ap->ioaddr.bmdma_addr)
2077 * ata_sff_port_start - Set port up for dma.
2078 * @ap: Port to initialize
2080 * Called just after data structures for each port are
2081 * initialized. Allocates space for PRD table if the device
2082 * is DMA capable SFF.
2084 * May be used as the port_start() entry in ata_port_operations.
2087 * Inherited from caller.
2089 int ata_sff_port_start(struct ata_port *ap)
2091 if (ap->ioaddr.bmdma_addr)
2092 return ata_port_start(ap);
2097 * ata_std_ports - initialize ioaddr with standard port offsets.
2098 * @ioaddr: IO address structure to be initialized
2100 * Utility function which initializes data_addr, error_addr,
2101 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2102 * device_addr, status_addr, and command_addr to standard offsets
2103 * relative to cmd_addr.
2105 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2107 void ata_std_ports(struct ata_ioports *ioaddr)
2109 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2110 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2111 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2112 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2113 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2114 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2115 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2116 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2117 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2118 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2121 unsigned long ata_pci_default_filter(struct ata_device *adev, unsigned long xfer_mask)
2123 /* Filter out DMA modes if the device has been configured by
2124 the BIOS as PIO only */
2126 if (adev->link->ap->ioaddr.bmdma_addr == NULL)
2127 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
2132 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2133 * @qc: Info associated with this ATA transaction.
2136 * spin_lock_irqsave(host lock)
2138 void ata_bmdma_setup(struct ata_queued_cmd *qc)
2140 struct ata_port *ap = qc->ap;
2141 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2144 /* load PRD table addr. */
2145 mb(); /* make sure PRD table writes are visible to controller */
2146 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2148 /* specify data direction, triple-check start bit is clear */
2149 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2150 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2152 dmactl |= ATA_DMA_WR;
2153 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2155 /* issue r/w command */
2156 ap->ops->exec_command(ap, &qc->tf);
2160 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2161 * @qc: Info associated with this ATA transaction.
2164 * spin_lock_irqsave(host lock)
2166 void ata_bmdma_start(struct ata_queued_cmd *qc)
2168 struct ata_port *ap = qc->ap;
2171 /* start host DMA transaction */
2172 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2173 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2175 /* Strictly, one may wish to issue an ioread8() here, to
2176 * flush the mmio write. However, control also passes
2177 * to the hardware at this point, and it will interrupt
2178 * us when we are to resume control. So, in effect,
2179 * we don't care when the mmio write flushes.
2180 * Further, a read of the DMA status register _immediately_
2181 * following the write may not be what certain flaky hardware
2182 * is expected, so I think it is best to not add a readb()
2183 * without first all the MMIO ATA cards/mobos.
2184 * Or maybe I'm just being paranoid.
2186 * FIXME: The posting of this write means I/O starts are
2187 * unneccessarily delayed for MMIO
2192 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2193 * @qc: Command we are ending DMA for
2195 * Clears the ATA_DMA_START flag in the dma control register
2197 * May be used as the bmdma_stop() entry in ata_port_operations.
2200 * spin_lock_irqsave(host lock)
2202 void ata_bmdma_stop(struct ata_queued_cmd *qc)
2204 struct ata_port *ap = qc->ap;
2205 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2207 /* clear start/stop bit */
2208 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
2209 mmio + ATA_DMA_CMD);
2211 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
2212 ata_altstatus(ap); /* dummy read */
2216 * ata_bmdma_status - Read PCI IDE BMDMA status
2217 * @ap: Port associated with this ATA transaction.
2219 * Read and return BMDMA status register.
2221 * May be used as the bmdma_status() entry in ata_port_operations.
2224 * spin_lock_irqsave(host lock)
2226 u8 ata_bmdma_status(struct ata_port *ap)
2228 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
2232 * ata_bus_reset - reset host port and associated ATA channel
2233 * @ap: port to reset
2235 * This is typically the first time we actually start issuing
2236 * commands to the ATA channel. We wait for BSY to clear, then
2237 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2238 * result. Determine what devices, if any, are on the channel
2239 * by looking at the device 0/1 error register. Look at the signature
2240 * stored in each device's taskfile registers, to determine if
2241 * the device is ATA or ATAPI.
2244 * PCI/etc. bus probe sem.
2245 * Obtains host lock.
2248 * Sets ATA_FLAG_DISABLED if bus reset fails.
2251 * This function is only for drivers which still use old EH and
2252 * will be removed soon.
2254 void ata_bus_reset(struct ata_port *ap)
2256 struct ata_device *device = ap->link.device;
2257 struct ata_ioports *ioaddr = &ap->ioaddr;
2258 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2260 unsigned int dev0, dev1 = 0, devmask = 0;
2263 DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no);
2265 /* determine if device 0/1 are present */
2266 if (ap->flags & ATA_FLAG_SATA_RESET)
2269 dev0 = ata_devchk(ap, 0);
2271 dev1 = ata_devchk(ap, 1);
2275 devmask |= (1 << 0);
2277 devmask |= (1 << 1);
2279 /* select device 0 again */
2280 ap->ops->dev_select(ap, 0);
2282 /* issue bus reset */
2283 if (ap->flags & ATA_FLAG_SRST) {
2284 rc = ata_bus_softreset(ap, devmask, jiffies + 40 * HZ);
2285 if (rc && rc != -ENODEV)
2290 * determine by signature whether we have ATA or ATAPI devices
2292 device[0].class = ata_dev_try_classify(&device[0], dev0, &err);
2293 if ((slave_possible) && (err != 0x81))
2294 device[1].class = ata_dev_try_classify(&device[1], dev1, &err);
2296 /* is double-select really necessary? */
2297 if (device[1].class != ATA_DEV_NONE)
2298 ap->ops->dev_select(ap, 1);
2299 if (device[0].class != ATA_DEV_NONE)
2300 ap->ops->dev_select(ap, 0);
2302 /* if no devices were detected, disable this port */
2303 if ((device[0].class == ATA_DEV_NONE) &&
2304 (device[1].class == ATA_DEV_NONE))
2307 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2308 /* set up device control for ATA_FLAG_SATA_RESET */
2309 iowrite8(ap->ctl, ioaddr->ctl_addr);
2316 ata_port_printk(ap, KERN_ERR, "disabling port\n");
2317 ata_port_disable(ap);
2325 * ata_pci_clear_simplex - attempt to kick device out of simplex
2328 * Some PCI ATA devices report simplex mode but in fact can be told to
2329 * enter non simplex mode. This implements the necessary logic to
2330 * perform the task on such devices. Calling it on other devices will
2331 * have -undefined- behaviour.
2333 int ata_pci_clear_simplex(struct pci_dev *pdev)
2335 unsigned long bmdma = pci_resource_start(pdev, 4);
2341 simplex = inb(bmdma + 0x02);
2342 outb(simplex & 0x60, bmdma + 0x02);
2343 simplex = inb(bmdma + 0x02);
2350 * ata_pci_init_bmdma - acquire PCI BMDMA resources and init ATA host
2351 * @host: target ATA host
2353 * Acquire PCI BMDMA resources and initialize @host accordingly.
2356 * Inherited from calling layer (may sleep).
2359 * 0 on success, -errno otherwise.
2361 int ata_pci_init_bmdma(struct ata_host *host)
2363 struct device *gdev = host->dev;
2364 struct pci_dev *pdev = to_pci_dev(gdev);
2367 /* No BAR4 allocation: No DMA */
2368 if (pci_resource_start(pdev, 4) == 0)
2371 /* TODO: If we get no DMA mask we should fall back to PIO */
2372 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
2375 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
2379 /* request and iomap DMA region */
2380 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
2382 dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
2385 host->iomap = pcim_iomap_table(pdev);
2387 for (i = 0; i < 2; i++) {
2388 struct ata_port *ap = host->ports[i];
2389 void __iomem *bmdma = host->iomap[4] + 8 * i;
2391 if (ata_port_is_dummy(ap))
2394 ap->ioaddr.bmdma_addr = bmdma;
2395 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
2396 (ioread8(bmdma + 2) & 0x80))
2397 host->flags |= ATA_HOST_SIMPLEX;
2399 ata_port_desc(ap, "bmdma 0x%llx",
2400 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
2406 static int ata_resources_present(struct pci_dev *pdev, int port)
2410 /* Check the PCI resources for this channel are enabled */
2412 for (i = 0; i < 2; i ++) {
2413 if (pci_resource_start(pdev, port + i) == 0 ||
2414 pci_resource_len(pdev, port + i) == 0)
2421 * ata_pci_init_sff_host - acquire native PCI ATA resources and init host
2422 * @host: target ATA host
2424 * Acquire native PCI ATA resources for @host and initialize the
2425 * first two ports of @host accordingly. Ports marked dummy are
2426 * skipped and allocation failure makes the port dummy.
2428 * Note that native PCI resources are valid even for legacy hosts
2429 * as we fix up pdev resources array early in boot, so this
2430 * function can be used for both native and legacy SFF hosts.
2433 * Inherited from calling layer (may sleep).
2436 * 0 if at least one port is initialized, -ENODEV if no port is
2439 int ata_pci_init_sff_host(struct ata_host *host)
2441 struct device *gdev = host->dev;
2442 struct pci_dev *pdev = to_pci_dev(gdev);
2443 unsigned int mask = 0;
2446 /* request, iomap BARs and init port addresses accordingly */
2447 for (i = 0; i < 2; i++) {
2448 struct ata_port *ap = host->ports[i];
2450 void __iomem * const *iomap;
2452 if (ata_port_is_dummy(ap))
2455 /* Discard disabled ports. Some controllers show
2456 * their unused channels this way. Disabled ports are
2459 if (!ata_resources_present(pdev, i)) {
2460 ap->ops = &ata_dummy_port_ops;
2464 rc = pcim_iomap_regions(pdev, 0x3 << base,
2465 dev_driver_string(gdev));
2467 dev_printk(KERN_WARNING, gdev,
2468 "failed to request/iomap BARs for port %d "
2469 "(errno=%d)\n", i, rc);
2471 pcim_pin_device(pdev);
2472 ap->ops = &ata_dummy_port_ops;
2475 host->iomap = iomap = pcim_iomap_table(pdev);
2477 ap->ioaddr.cmd_addr = iomap[base];
2478 ap->ioaddr.altstatus_addr =
2479 ap->ioaddr.ctl_addr = (void __iomem *)
2480 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2481 ata_std_ports(&ap->ioaddr);
2483 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2484 (unsigned long long)pci_resource_start(pdev, base),
2485 (unsigned long long)pci_resource_start(pdev, base + 1));
2491 dev_printk(KERN_ERR, gdev, "no available native port\n");
2499 * ata_pci_prepare_sff_host - helper to prepare native PCI ATA host
2500 * @pdev: target PCI device
2501 * @ppi: array of port_info, must be enough for two ports
2502 * @r_host: out argument for the initialized ATA host
2504 * Helper to allocate ATA host for @pdev, acquire all native PCI
2505 * resources and initialize it accordingly in one go.
2508 * Inherited from calling layer (may sleep).
2511 * 0 on success, -errno otherwise.
2513 int ata_pci_prepare_sff_host(struct pci_dev *pdev,
2514 const struct ata_port_info * const * ppi,
2515 struct ata_host **r_host)
2517 struct ata_host *host;
2520 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2523 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2525 dev_printk(KERN_ERR, &pdev->dev,
2526 "failed to allocate ATA host\n");
2531 rc = ata_pci_init_sff_host(host);
2535 /* init DMA related stuff */
2536 rc = ata_pci_init_bmdma(host);
2540 devres_remove_group(&pdev->dev, NULL);
2545 /* This is necessary because PCI and iomap resources are
2546 * merged and releasing the top group won't release the
2547 * acquired resources if some of those have been acquired
2548 * before entering this function.
2550 pcim_iounmap_regions(pdev, 0xf);
2552 devres_release_group(&pdev->dev, NULL);
2557 * ata_pci_activate_sff_host - start SFF host, request IRQ and register it
2558 * @host: target SFF ATA host
2559 * @irq_handler: irq_handler used when requesting IRQ(s)
2560 * @sht: scsi_host_template to use when registering the host
2562 * This is the counterpart of ata_host_activate() for SFF ATA
2563 * hosts. This separate helper is necessary because SFF hosts
2564 * use two separate interrupts in legacy mode.
2567 * Inherited from calling layer (may sleep).
2570 * 0 on success, -errno otherwise.
2572 int ata_pci_activate_sff_host(struct ata_host *host,
2573 irq_handler_t irq_handler,
2574 struct scsi_host_template *sht)
2576 struct device *dev = host->dev;
2577 struct pci_dev *pdev = to_pci_dev(dev);
2578 const char *drv_name = dev_driver_string(host->dev);
2579 int legacy_mode = 0, rc;
2581 rc = ata_host_start(host);
2585 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2588 /* TODO: What if one channel is in native mode ... */
2589 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2590 mask = (1 << 2) | (1 << 0);
2591 if ((tmp8 & mask) != mask)
2593 #if defined(CONFIG_NO_ATA_LEGACY)
2594 /* Some platforms with PCI limits cannot address compat
2595 port space. In that case we punt if their firmware has
2596 left a device in compatibility mode */
2598 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
2604 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2607 if (!legacy_mode && pdev->irq) {
2608 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2609 IRQF_SHARED, drv_name, host);
2613 ata_port_desc(host->ports[0], "irq %d", pdev->irq);
2614 ata_port_desc(host->ports[1], "irq %d", pdev->irq);
2615 } else if (legacy_mode) {
2616 if (!ata_port_is_dummy(host->ports[0])) {
2617 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2618 irq_handler, IRQF_SHARED,
2623 ata_port_desc(host->ports[0], "irq %d",
2624 ATA_PRIMARY_IRQ(pdev));
2627 if (!ata_port_is_dummy(host->ports[1])) {
2628 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2629 irq_handler, IRQF_SHARED,
2634 ata_port_desc(host->ports[1], "irq %d",
2635 ATA_SECONDARY_IRQ(pdev));
2639 rc = ata_host_register(host, sht);
2642 devres_remove_group(dev, NULL);
2644 devres_release_group(dev, NULL);
2650 * ata_pci_init_one - Initialize/register PCI IDE host controller
2651 * @pdev: Controller to be initialized
2652 * @ppi: array of port_info, must be enough for two ports
2653 * @sht: scsi_host_template to use when registering the host
2654 * @host_priv: host private_data
2656 * This is a helper function which can be called from a driver's
2657 * xxx_init_one() probe function if the hardware uses traditional
2658 * IDE taskfile registers.
2660 * This function calls pci_enable_device(), reserves its register
2661 * regions, sets the dma mask, enables bus master mode, and calls
2665 * Nobody makes a single channel controller that appears solely as
2666 * the secondary legacy port on PCI.
2669 * Inherited from PCI layer (may sleep).
2672 * Zero on success, negative on errno-based value on error.
2674 int ata_pci_init_one(struct pci_dev *pdev,
2675 const struct ata_port_info * const * ppi,
2676 struct scsi_host_template *sht, void *host_priv)
2678 struct device *dev = &pdev->dev;
2679 const struct ata_port_info *pi = NULL;
2680 struct ata_host *host = NULL;
2685 /* look up the first valid port_info */
2686 for (i = 0; i < 2 && ppi[i]; i++) {
2687 if (ppi[i]->port_ops != &ata_dummy_port_ops) {
2694 dev_printk(KERN_ERR, &pdev->dev,
2695 "no valid port_info specified\n");
2699 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2702 rc = pcim_enable_device(pdev);
2706 /* prepare and activate SFF host */
2707 rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
2710 host->private_data = host_priv;
2712 pci_set_master(pdev);
2713 rc = ata_pci_activate_sff_host(host, ata_interrupt, sht);
2716 devres_remove_group(&pdev->dev, NULL);
2718 devres_release_group(&pdev->dev, NULL);
2723 #endif /* CONFIG_PCI */
2725 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
2726 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2727 EXPORT_SYMBOL_GPL(ata_qc_prep);
2728 EXPORT_SYMBOL_GPL(ata_dumb_qc_prep);
2729 EXPORT_SYMBOL_GPL(ata_std_dev_select);
2730 EXPORT_SYMBOL_GPL(ata_check_status);
2731 EXPORT_SYMBOL_GPL(ata_altstatus);
2732 EXPORT_SYMBOL_GPL(ata_busy_sleep);
2733 EXPORT_SYMBOL_GPL(ata_wait_ready);
2734 EXPORT_SYMBOL_GPL(ata_tf_load);
2735 EXPORT_SYMBOL_GPL(ata_tf_read);
2736 EXPORT_SYMBOL_GPL(ata_exec_command);
2737 EXPORT_SYMBOL_GPL(ata_data_xfer);
2738 EXPORT_SYMBOL_GPL(ata_data_xfer_noirq);
2739 EXPORT_SYMBOL_GPL(ata_irq_on);
2740 EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
2741 EXPORT_SYMBOL_GPL(ata_hsm_move);
2742 EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
2743 EXPORT_SYMBOL_GPL(ata_host_intr);
2744 EXPORT_SYMBOL_GPL(ata_interrupt);
2745 EXPORT_SYMBOL_GPL(ata_bmdma_freeze);
2746 EXPORT_SYMBOL_GPL(ata_bmdma_thaw);
2747 EXPORT_SYMBOL_GPL(ata_std_prereset);
2748 EXPORT_SYMBOL_GPL(ata_dev_try_classify);
2749 EXPORT_SYMBOL_GPL(ata_wait_after_reset);
2750 EXPORT_SYMBOL_GPL(ata_std_softreset);
2751 EXPORT_SYMBOL_GPL(sata_std_hardreset);
2752 EXPORT_SYMBOL_GPL(ata_std_postreset);
2753 EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2754 EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2755 EXPORT_SYMBOL_GPL(ata_sff_port_start);
2756 EXPORT_SYMBOL_GPL(ata_std_ports);
2757 EXPORT_SYMBOL_GPL(ata_pci_default_filter);
2758 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2759 EXPORT_SYMBOL_GPL(ata_bmdma_start);
2760 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2761 EXPORT_SYMBOL_GPL(ata_bmdma_status);
2762 EXPORT_SYMBOL_GPL(ata_bus_reset);
2764 EXPORT_SYMBOL_GPL(ata_pci_clear_simplex);
2765 EXPORT_SYMBOL_GPL(ata_pci_init_bmdma);
2766 EXPORT_SYMBOL_GPL(ata_pci_init_sff_host);
2767 EXPORT_SYMBOL_GPL(ata_pci_prepare_sff_host);
2768 EXPORT_SYMBOL_GPL(ata_pci_activate_sff_host);
2769 EXPORT_SYMBOL_GPL(ata_pci_init_one);
2770 #endif /* CONFIG_PCI */