2 * libahci.c - Common AHCI SATA low-level routines
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include <linux/pci.h>
50 static int ahci_skip_host_reset;
52 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
54 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
55 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
57 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
58 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
60 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73 static int ahci_port_start(struct ata_port *ap);
74 static void ahci_port_stop(struct ata_port *ap);
75 static void ahci_qc_prep(struct ata_queued_cmd *qc);
76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77 static void ahci_freeze(struct ata_port *ap);
78 static void ahci_thaw(struct ata_port *ap);
79 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
80 static void ahci_enable_fbs(struct ata_port *ap);
81 static void ahci_disable_fbs(struct ata_port *ap);
82 static void ahci_pmp_attach(struct ata_port *ap);
83 static void ahci_pmp_detach(struct ata_port *ap);
84 static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static void ahci_postreset(struct ata_link *link, unsigned int *class);
91 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
92 static void ahci_dev_config(struct ata_device *dev);
94 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
97 static ssize_t ahci_activity_store(struct ata_device *dev,
98 enum sw_activity val);
99 static void ahci_init_sw_activity(struct ata_link *link);
101 static ssize_t ahci_show_host_caps(struct device *dev,
102 struct device_attribute *attr, char *buf);
103 static ssize_t ahci_show_host_cap2(struct device *dev,
104 struct device_attribute *attr, char *buf);
105 static ssize_t ahci_show_host_version(struct device *dev,
106 struct device_attribute *attr, char *buf);
107 static ssize_t ahci_show_port_cmd(struct device *dev,
108 struct device_attribute *attr, char *buf);
109 static ssize_t ahci_read_em_buffer(struct device *dev,
110 struct device_attribute *attr, char *buf);
111 static ssize_t ahci_store_em_buffer(struct device *dev,
112 struct device_attribute *attr,
113 const char *buf, size_t size);
114 static ssize_t ahci_show_em_supported(struct device *dev,
115 struct device_attribute *attr, char *buf);
116 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
118 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
119 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
120 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
121 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
122 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
123 ahci_read_em_buffer, ahci_store_em_buffer);
124 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
126 struct device_attribute *ahci_shost_attrs[] = {
127 &dev_attr_link_power_management_policy,
128 &dev_attr_em_message_type,
129 &dev_attr_em_message,
130 &dev_attr_ahci_host_caps,
131 &dev_attr_ahci_host_cap2,
132 &dev_attr_ahci_host_version,
133 &dev_attr_ahci_port_cmd,
135 &dev_attr_em_message_supported,
138 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
140 struct device_attribute *ahci_sdev_attrs[] = {
141 &dev_attr_sw_activity,
142 &dev_attr_unload_heads,
143 &dev_attr_ncq_prio_enable,
146 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
148 struct ata_port_operations ahci_ops = {
149 .inherits = &sata_pmp_port_ops,
151 .qc_defer = ahci_pmp_qc_defer,
152 .qc_prep = ahci_qc_prep,
153 .qc_issue = ahci_qc_issue,
154 .qc_fill_rtf = ahci_qc_fill_rtf,
156 .freeze = ahci_freeze,
158 .softreset = ahci_softreset,
159 .hardreset = ahci_hardreset,
160 .postreset = ahci_postreset,
161 .pmp_softreset = ahci_softreset,
162 .error_handler = ahci_error_handler,
163 .post_internal_cmd = ahci_post_internal_cmd,
164 .dev_config = ahci_dev_config,
166 .scr_read = ahci_scr_read,
167 .scr_write = ahci_scr_write,
168 .pmp_attach = ahci_pmp_attach,
169 .pmp_detach = ahci_pmp_detach,
171 .set_lpm = ahci_set_lpm,
172 .em_show = ahci_led_show,
173 .em_store = ahci_led_store,
174 .sw_activity_show = ahci_activity_show,
175 .sw_activity_store = ahci_activity_store,
176 .transmit_led_message = ahci_transmit_led_message,
178 .port_suspend = ahci_port_suspend,
179 .port_resume = ahci_port_resume,
181 .port_start = ahci_port_start,
182 .port_stop = ahci_port_stop,
184 EXPORT_SYMBOL_GPL(ahci_ops);
186 struct ata_port_operations ahci_pmp_retry_srst_ops = {
187 .inherits = &ahci_ops,
188 .softreset = ahci_pmp_retry_softreset,
190 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
192 static bool ahci_em_messages __read_mostly = true;
193 EXPORT_SYMBOL_GPL(ahci_em_messages);
194 module_param(ahci_em_messages, bool, 0444);
195 /* add other LED protocol types when they become supported */
196 MODULE_PARM_DESC(ahci_em_messages,
197 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
199 /* device sleep idle timeout in ms */
200 static int devslp_idle_timeout __read_mostly = 1000;
201 module_param(devslp_idle_timeout, int, 0644);
202 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
204 static void ahci_enable_ahci(void __iomem *mmio)
209 /* turn on AHCI_EN */
210 tmp = readl(mmio + HOST_CTL);
211 if (tmp & HOST_AHCI_EN)
214 /* Some controllers need AHCI_EN to be written multiple times.
215 * Try a few times before giving up.
217 for (i = 0; i < 5; i++) {
219 writel(tmp, mmio + HOST_CTL);
220 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
221 if (tmp & HOST_AHCI_EN)
230 * ahci_rpm_get_port - Make sure the port is powered on
231 * @ap: Port to power on
233 * Whenever there is need to access the AHCI host registers outside of
234 * normal execution paths, call this function to make sure the host is
235 * actually powered on.
237 static int ahci_rpm_get_port(struct ata_port *ap)
239 return pm_runtime_get_sync(ap->dev);
243 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
244 * @ap: Port to power down
246 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
247 * if it has no more active users.
249 static void ahci_rpm_put_port(struct ata_port *ap)
251 pm_runtime_put(ap->dev);
254 static ssize_t ahci_show_host_caps(struct device *dev,
255 struct device_attribute *attr, char *buf)
257 struct Scsi_Host *shost = class_to_shost(dev);
258 struct ata_port *ap = ata_shost_to_port(shost);
259 struct ahci_host_priv *hpriv = ap->host->private_data;
261 return sprintf(buf, "%x\n", hpriv->cap);
264 static ssize_t ahci_show_host_cap2(struct device *dev,
265 struct device_attribute *attr, char *buf)
267 struct Scsi_Host *shost = class_to_shost(dev);
268 struct ata_port *ap = ata_shost_to_port(shost);
269 struct ahci_host_priv *hpriv = ap->host->private_data;
271 return sprintf(buf, "%x\n", hpriv->cap2);
274 static ssize_t ahci_show_host_version(struct device *dev,
275 struct device_attribute *attr, char *buf)
277 struct Scsi_Host *shost = class_to_shost(dev);
278 struct ata_port *ap = ata_shost_to_port(shost);
279 struct ahci_host_priv *hpriv = ap->host->private_data;
281 return sprintf(buf, "%x\n", hpriv->version);
284 static ssize_t ahci_show_port_cmd(struct device *dev,
285 struct device_attribute *attr, char *buf)
287 struct Scsi_Host *shost = class_to_shost(dev);
288 struct ata_port *ap = ata_shost_to_port(shost);
289 void __iomem *port_mmio = ahci_port_base(ap);
292 ahci_rpm_get_port(ap);
293 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
294 ahci_rpm_put_port(ap);
299 static ssize_t ahci_read_em_buffer(struct device *dev,
300 struct device_attribute *attr, char *buf)
302 struct Scsi_Host *shost = class_to_shost(dev);
303 struct ata_port *ap = ata_shost_to_port(shost);
304 struct ahci_host_priv *hpriv = ap->host->private_data;
305 void __iomem *mmio = hpriv->mmio;
306 void __iomem *em_mmio = mmio + hpriv->em_loc;
312 ahci_rpm_get_port(ap);
313 spin_lock_irqsave(ap->lock, flags);
315 em_ctl = readl(mmio + HOST_EM_CTL);
316 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
317 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
318 spin_unlock_irqrestore(ap->lock, flags);
319 ahci_rpm_put_port(ap);
323 if (!(em_ctl & EM_CTL_MR)) {
324 spin_unlock_irqrestore(ap->lock, flags);
325 ahci_rpm_put_port(ap);
329 if (!(em_ctl & EM_CTL_SMB))
330 em_mmio += hpriv->em_buf_sz;
332 count = hpriv->em_buf_sz;
334 /* the count should not be larger than PAGE_SIZE */
335 if (count > PAGE_SIZE) {
336 if (printk_ratelimit())
338 "EM read buffer size too large: "
339 "buffer size %u, page size %lu\n",
340 hpriv->em_buf_sz, PAGE_SIZE);
344 for (i = 0; i < count; i += 4) {
345 msg = readl(em_mmio + i);
347 buf[i + 1] = (msg >> 8) & 0xff;
348 buf[i + 2] = (msg >> 16) & 0xff;
349 buf[i + 3] = (msg >> 24) & 0xff;
352 spin_unlock_irqrestore(ap->lock, flags);
353 ahci_rpm_put_port(ap);
358 static ssize_t ahci_store_em_buffer(struct device *dev,
359 struct device_attribute *attr,
360 const char *buf, size_t size)
362 struct Scsi_Host *shost = class_to_shost(dev);
363 struct ata_port *ap = ata_shost_to_port(shost);
364 struct ahci_host_priv *hpriv = ap->host->private_data;
365 void __iomem *mmio = hpriv->mmio;
366 void __iomem *em_mmio = mmio + hpriv->em_loc;
367 const unsigned char *msg_buf = buf;
372 /* check size validity */
373 if (!(ap->flags & ATA_FLAG_EM) ||
374 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
375 size % 4 || size > hpriv->em_buf_sz)
378 ahci_rpm_get_port(ap);
379 spin_lock_irqsave(ap->lock, flags);
381 em_ctl = readl(mmio + HOST_EM_CTL);
382 if (em_ctl & EM_CTL_TM) {
383 spin_unlock_irqrestore(ap->lock, flags);
384 ahci_rpm_put_port(ap);
388 for (i = 0; i < size; i += 4) {
389 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
390 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
391 writel(msg, em_mmio + i);
394 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
396 spin_unlock_irqrestore(ap->lock, flags);
397 ahci_rpm_put_port(ap);
402 static ssize_t ahci_show_em_supported(struct device *dev,
403 struct device_attribute *attr, char *buf)
405 struct Scsi_Host *shost = class_to_shost(dev);
406 struct ata_port *ap = ata_shost_to_port(shost);
407 struct ahci_host_priv *hpriv = ap->host->private_data;
408 void __iomem *mmio = hpriv->mmio;
411 ahci_rpm_get_port(ap);
412 em_ctl = readl(mmio + HOST_EM_CTL);
413 ahci_rpm_put_port(ap);
415 return sprintf(buf, "%s%s%s%s\n",
416 em_ctl & EM_CTL_LED ? "led " : "",
417 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
418 em_ctl & EM_CTL_SES ? "ses-2 " : "",
419 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
423 * ahci_save_initial_config - Save and fixup initial config values
424 * @dev: target AHCI device
425 * @hpriv: host private area to store config values
427 * Some registers containing configuration info might be setup by
428 * BIOS and might be cleared on reset. This function saves the
429 * initial values of those registers into @hpriv such that they
430 * can be restored after controller reset.
432 * If inconsistent, config values are fixed up by this function.
434 * If it is not set already this function sets hpriv->start_engine to
440 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
442 void __iomem *mmio = hpriv->mmio;
443 u32 cap, cap2, vers, port_map;
446 /* make sure AHCI mode is enabled before accessing CAP */
447 ahci_enable_ahci(mmio);
449 /* Values prefixed with saved_ are written back to host after
450 * reset. Values without are used for driver operation.
452 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
453 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
455 /* CAP2 register is only defined for AHCI 1.2 and later */
456 vers = readl(mmio + HOST_VERSION);
457 if ((vers >> 16) > 1 ||
458 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
459 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
461 hpriv->saved_cap2 = cap2 = 0;
463 /* some chips have errata preventing 64bit use */
464 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
465 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
469 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
470 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
471 cap &= ~HOST_CAP_NCQ;
474 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
475 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
479 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
480 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
481 cap &= ~HOST_CAP_PMP;
484 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
486 "controller can't do SNTF, turning off CAP_SNTF\n");
487 cap &= ~HOST_CAP_SNTF;
490 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
492 "controller can't do DEVSLP, turning off\n");
493 cap2 &= ~HOST_CAP2_SDS;
494 cap2 &= ~HOST_CAP2_SADM;
497 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
498 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
502 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
503 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
504 cap &= ~HOST_CAP_FBS;
507 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
508 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
509 cap |= HOST_CAP_ALPM;
512 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
513 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
514 port_map, hpriv->force_port_map);
515 port_map = hpriv->force_port_map;
516 hpriv->saved_port_map = port_map;
519 if (hpriv->mask_port_map) {
520 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
522 port_map & hpriv->mask_port_map);
523 port_map &= hpriv->mask_port_map;
526 /* cross check port_map and cap.n_ports */
530 for (i = 0; i < AHCI_MAX_PORTS; i++)
531 if (port_map & (1 << i))
534 /* If PI has more ports than n_ports, whine, clear
535 * port_map and let it be generated from n_ports.
537 if (map_ports > ahci_nr_ports(cap)) {
539 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
540 port_map, ahci_nr_ports(cap));
545 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
546 if (!port_map && vers < 0x10300) {
547 port_map = (1 << ahci_nr_ports(cap)) - 1;
548 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
550 /* write the fixed up value to the PI register */
551 hpriv->saved_port_map = port_map;
554 /* record values to use during operation */
557 hpriv->version = readl(mmio + HOST_VERSION);
558 hpriv->port_map = port_map;
560 if (!hpriv->start_engine)
561 hpriv->start_engine = ahci_start_engine;
563 if (!hpriv->stop_engine)
564 hpriv->stop_engine = ahci_stop_engine;
566 if (!hpriv->irq_handler)
567 hpriv->irq_handler = ahci_single_level_irq_intr;
569 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
572 * ahci_restore_initial_config - Restore initial config
573 * @host: target ATA host
575 * Restore initial config stored by ahci_save_initial_config().
580 static void ahci_restore_initial_config(struct ata_host *host)
582 struct ahci_host_priv *hpriv = host->private_data;
583 void __iomem *mmio = hpriv->mmio;
585 writel(hpriv->saved_cap, mmio + HOST_CAP);
586 if (hpriv->saved_cap2)
587 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
588 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
589 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
592 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
594 static const int offset[] = {
595 [SCR_STATUS] = PORT_SCR_STAT,
596 [SCR_CONTROL] = PORT_SCR_CTL,
597 [SCR_ERROR] = PORT_SCR_ERR,
598 [SCR_ACTIVE] = PORT_SCR_ACT,
599 [SCR_NOTIFICATION] = PORT_SCR_NTF,
601 struct ahci_host_priv *hpriv = ap->host->private_data;
603 if (sc_reg < ARRAY_SIZE(offset) &&
604 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
605 return offset[sc_reg];
609 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
611 void __iomem *port_mmio = ahci_port_base(link->ap);
612 int offset = ahci_scr_offset(link->ap, sc_reg);
615 *val = readl(port_mmio + offset);
621 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
623 void __iomem *port_mmio = ahci_port_base(link->ap);
624 int offset = ahci_scr_offset(link->ap, sc_reg);
627 writel(val, port_mmio + offset);
633 void ahci_start_engine(struct ata_port *ap)
635 void __iomem *port_mmio = ahci_port_base(ap);
639 tmp = readl(port_mmio + PORT_CMD);
640 tmp |= PORT_CMD_START;
641 writel(tmp, port_mmio + PORT_CMD);
642 readl(port_mmio + PORT_CMD); /* flush */
644 EXPORT_SYMBOL_GPL(ahci_start_engine);
646 int ahci_stop_engine(struct ata_port *ap)
648 void __iomem *port_mmio = ahci_port_base(ap);
649 struct ahci_host_priv *hpriv = ap->host->private_data;
653 * On some controllers, stopping a port's DMA engine while the port
654 * is in ALPM state (partial or slumber) results in failures on
655 * subsequent DMA engine starts. For those controllers, put the
656 * port back in active state before stopping its DMA engine.
658 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
659 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
660 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
661 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
665 tmp = readl(port_mmio + PORT_CMD);
667 /* check if the HBA is idle */
668 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
672 * Don't try to issue commands but return with ENODEV if the
673 * AHCI controller not available anymore (e.g. due to PCIe hot
674 * unplugging). Otherwise a 500ms delay for each port is added.
676 if (tmp == 0xffffffff) {
677 dev_err(ap->host->dev, "AHCI controller unavailable!\n");
681 /* setting HBA to idle */
682 tmp &= ~PORT_CMD_START;
683 writel(tmp, port_mmio + PORT_CMD);
685 /* wait for engine to stop. This could be as long as 500 msec */
686 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
687 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
688 if (tmp & PORT_CMD_LIST_ON)
693 EXPORT_SYMBOL_GPL(ahci_stop_engine);
695 void ahci_start_fis_rx(struct ata_port *ap)
697 void __iomem *port_mmio = ahci_port_base(ap);
698 struct ahci_host_priv *hpriv = ap->host->private_data;
699 struct ahci_port_priv *pp = ap->private_data;
702 /* set FIS registers */
703 if (hpriv->cap & HOST_CAP_64)
704 writel((pp->cmd_slot_dma >> 16) >> 16,
705 port_mmio + PORT_LST_ADDR_HI);
706 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
708 if (hpriv->cap & HOST_CAP_64)
709 writel((pp->rx_fis_dma >> 16) >> 16,
710 port_mmio + PORT_FIS_ADDR_HI);
711 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
713 /* enable FIS reception */
714 tmp = readl(port_mmio + PORT_CMD);
715 tmp |= PORT_CMD_FIS_RX;
716 writel(tmp, port_mmio + PORT_CMD);
719 readl(port_mmio + PORT_CMD);
721 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
723 static int ahci_stop_fis_rx(struct ata_port *ap)
725 void __iomem *port_mmio = ahci_port_base(ap);
728 /* disable FIS reception */
729 tmp = readl(port_mmio + PORT_CMD);
730 tmp &= ~PORT_CMD_FIS_RX;
731 writel(tmp, port_mmio + PORT_CMD);
733 /* wait for completion, spec says 500ms, give it 1000 */
734 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
735 PORT_CMD_FIS_ON, 10, 1000);
736 if (tmp & PORT_CMD_FIS_ON)
742 static void ahci_power_up(struct ata_port *ap)
744 struct ahci_host_priv *hpriv = ap->host->private_data;
745 void __iomem *port_mmio = ahci_port_base(ap);
748 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
751 if (hpriv->cap & HOST_CAP_SSS) {
752 cmd |= PORT_CMD_SPIN_UP;
753 writel(cmd, port_mmio + PORT_CMD);
757 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
760 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
763 struct ata_port *ap = link->ap;
764 struct ahci_host_priv *hpriv = ap->host->private_data;
765 struct ahci_port_priv *pp = ap->private_data;
766 void __iomem *port_mmio = ahci_port_base(ap);
768 if (policy != ATA_LPM_MAX_POWER) {
769 /* wakeup flag only applies to the max power policy */
770 hints &= ~ATA_LPM_WAKE_ONLY;
773 * Disable interrupts on Phy Ready. This keeps us from
774 * getting woken up due to spurious phy ready
777 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
778 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
780 sata_link_scr_lpm(link, policy, false);
783 if (hpriv->cap & HOST_CAP_ALPM) {
784 u32 cmd = readl(port_mmio + PORT_CMD);
786 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
787 if (!(hints & ATA_LPM_WAKE_ONLY))
788 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
789 cmd |= PORT_CMD_ICC_ACTIVE;
791 writel(cmd, port_mmio + PORT_CMD);
792 readl(port_mmio + PORT_CMD);
794 /* wait 10ms to be sure we've come out of LPM state */
797 if (hints & ATA_LPM_WAKE_ONLY)
800 cmd |= PORT_CMD_ALPE;
801 if (policy == ATA_LPM_MIN_POWER)
804 /* write out new cmd value */
805 writel(cmd, port_mmio + PORT_CMD);
809 /* set aggressive device sleep */
810 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
811 (hpriv->cap2 & HOST_CAP2_SADM) &&
812 (link->device->flags & ATA_DFLAG_DEVSLP)) {
813 if (policy == ATA_LPM_MIN_POWER)
814 ahci_set_aggressive_devslp(ap, true);
816 ahci_set_aggressive_devslp(ap, false);
819 if (policy == ATA_LPM_MAX_POWER) {
820 sata_link_scr_lpm(link, policy, false);
822 /* turn PHYRDY IRQ back on */
823 pp->intr_mask |= PORT_IRQ_PHYRDY;
824 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
831 static void ahci_power_down(struct ata_port *ap)
833 struct ahci_host_priv *hpriv = ap->host->private_data;
834 void __iomem *port_mmio = ahci_port_base(ap);
837 if (!(hpriv->cap & HOST_CAP_SSS))
840 /* put device into listen mode, first set PxSCTL.DET to 0 */
841 scontrol = readl(port_mmio + PORT_SCR_CTL);
843 writel(scontrol, port_mmio + PORT_SCR_CTL);
845 /* then set PxCMD.SUD to 0 */
846 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
847 cmd &= ~PORT_CMD_SPIN_UP;
848 writel(cmd, port_mmio + PORT_CMD);
852 static void ahci_start_port(struct ata_port *ap)
854 struct ahci_host_priv *hpriv = ap->host->private_data;
855 struct ahci_port_priv *pp = ap->private_data;
856 struct ata_link *link;
857 struct ahci_em_priv *emp;
861 /* enable FIS reception */
862 ahci_start_fis_rx(ap);
865 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
866 hpriv->start_engine(ap);
869 if (ap->flags & ATA_FLAG_EM) {
870 ata_for_each_link(link, ap, EDGE) {
871 emp = &pp->em_priv[link->pmp];
873 /* EM Transmit bit maybe busy during init */
874 for (i = 0; i < EM_MAX_RETRY; i++) {
875 rc = ap->ops->transmit_led_message(ap,
879 * If busy, give a breather but do not
880 * release EH ownership by using msleep()
881 * instead of ata_msleep(). EM Transmit
882 * bit is busy for the whole host and
883 * releasing ownership will cause other
884 * ports to fail the same way.
894 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
895 ata_for_each_link(link, ap, EDGE)
896 ahci_init_sw_activity(link);
900 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
903 struct ahci_host_priv *hpriv = ap->host->private_data;
906 rc = hpriv->stop_engine(ap);
908 *emsg = "failed to stop engine";
912 /* disable FIS reception */
913 rc = ahci_stop_fis_rx(ap);
915 *emsg = "failed stop FIS RX";
922 int ahci_reset_controller(struct ata_host *host)
924 struct ahci_host_priv *hpriv = host->private_data;
925 void __iomem *mmio = hpriv->mmio;
928 /* we must be in AHCI mode, before using anything
929 * AHCI-specific, such as HOST_RESET.
931 ahci_enable_ahci(mmio);
933 /* global controller reset */
934 if (!ahci_skip_host_reset) {
935 tmp = readl(mmio + HOST_CTL);
936 if ((tmp & HOST_RESET) == 0) {
937 writel(tmp | HOST_RESET, mmio + HOST_CTL);
938 readl(mmio + HOST_CTL); /* flush */
942 * to perform host reset, OS should set HOST_RESET
943 * and poll until this bit is read to be "0".
944 * reset must complete within 1 second, or
945 * the hardware should be considered fried.
947 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
948 HOST_RESET, 10, 1000);
950 if (tmp & HOST_RESET) {
951 dev_err(host->dev, "controller reset failed (0x%x)\n",
956 /* turn on AHCI mode */
957 ahci_enable_ahci(mmio);
959 /* Some registers might be cleared on reset. Restore
962 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
963 ahci_restore_initial_config(host);
965 dev_info(host->dev, "skipping global host reset\n");
969 EXPORT_SYMBOL_GPL(ahci_reset_controller);
971 static void ahci_sw_activity(struct ata_link *link)
973 struct ata_port *ap = link->ap;
974 struct ahci_port_priv *pp = ap->private_data;
975 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
977 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
981 if (!timer_pending(&emp->timer))
982 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
985 static void ahci_sw_activity_blink(struct timer_list *t)
987 struct ahci_em_priv *emp = from_timer(emp, t, timer);
988 struct ata_link *link = emp->link;
989 struct ata_port *ap = link->ap;
991 unsigned long led_message = emp->led_state;
992 u32 activity_led_state;
995 led_message &= EM_MSG_LED_VALUE;
996 led_message |= ap->port_no | (link->pmp << 8);
998 /* check to see if we've had activity. If so,
999 * toggle state of LED and reset timer. If not,
1000 * turn LED to desired idle state.
1002 spin_lock_irqsave(ap->lock, flags);
1003 if (emp->saved_activity != emp->activity) {
1004 emp->saved_activity = emp->activity;
1005 /* get the current LED state */
1006 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1008 if (activity_led_state)
1009 activity_led_state = 0;
1011 activity_led_state = 1;
1013 /* clear old state */
1014 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1017 led_message |= (activity_led_state << 16);
1018 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1020 /* switch to idle */
1021 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1022 if (emp->blink_policy == BLINK_OFF)
1023 led_message |= (1 << 16);
1025 spin_unlock_irqrestore(ap->lock, flags);
1026 ap->ops->transmit_led_message(ap, led_message, 4);
1029 static void ahci_init_sw_activity(struct ata_link *link)
1031 struct ata_port *ap = link->ap;
1032 struct ahci_port_priv *pp = ap->private_data;
1033 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1035 /* init activity stats, setup timer */
1036 emp->saved_activity = emp->activity = 0;
1038 timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
1040 /* check our blink policy and set flag for link if it's enabled */
1041 if (emp->blink_policy)
1042 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1045 int ahci_reset_em(struct ata_host *host)
1047 struct ahci_host_priv *hpriv = host->private_data;
1048 void __iomem *mmio = hpriv->mmio;
1051 em_ctl = readl(mmio + HOST_EM_CTL);
1052 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1055 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1058 EXPORT_SYMBOL_GPL(ahci_reset_em);
1060 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1063 struct ahci_host_priv *hpriv = ap->host->private_data;
1064 struct ahci_port_priv *pp = ap->private_data;
1065 void __iomem *mmio = hpriv->mmio;
1067 u32 message[] = {0, 0};
1068 unsigned long flags;
1070 struct ahci_em_priv *emp;
1072 /* get the slot number from the message */
1073 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1074 if (pmp < EM_MAX_SLOTS)
1075 emp = &pp->em_priv[pmp];
1079 ahci_rpm_get_port(ap);
1080 spin_lock_irqsave(ap->lock, flags);
1083 * if we are still busy transmitting a previous message,
1086 em_ctl = readl(mmio + HOST_EM_CTL);
1087 if (em_ctl & EM_CTL_TM) {
1088 spin_unlock_irqrestore(ap->lock, flags);
1089 ahci_rpm_put_port(ap);
1093 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1095 * create message header - this is all zero except for
1096 * the message size, which is 4 bytes.
1098 message[0] |= (4 << 8);
1100 /* ignore 0:4 of byte zero, fill in port info yourself */
1101 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1103 /* write message to EM_LOC */
1104 writel(message[0], mmio + hpriv->em_loc);
1105 writel(message[1], mmio + hpriv->em_loc+4);
1108 * tell hardware to transmit the message
1110 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1113 /* save off new led state for port/slot */
1114 emp->led_state = state;
1116 spin_unlock_irqrestore(ap->lock, flags);
1117 ahci_rpm_put_port(ap);
1122 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1124 struct ahci_port_priv *pp = ap->private_data;
1125 struct ata_link *link;
1126 struct ahci_em_priv *emp;
1129 ata_for_each_link(link, ap, EDGE) {
1130 emp = &pp->em_priv[link->pmp];
1131 rc += sprintf(buf, "%lx\n", emp->led_state);
1136 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1141 struct ahci_port_priv *pp = ap->private_data;
1142 struct ahci_em_priv *emp;
1144 if (kstrtouint(buf, 0, &state) < 0)
1147 /* get the slot number from the message */
1148 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1149 if (pmp < EM_MAX_SLOTS)
1150 emp = &pp->em_priv[pmp];
1154 /* mask off the activity bits if we are in sw_activity
1155 * mode, user should turn off sw_activity before setting
1156 * activity led through em_message
1158 if (emp->blink_policy)
1159 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1161 return ap->ops->transmit_led_message(ap, state, size);
1164 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1166 struct ata_link *link = dev->link;
1167 struct ata_port *ap = link->ap;
1168 struct ahci_port_priv *pp = ap->private_data;
1169 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1170 u32 port_led_state = emp->led_state;
1172 /* save the desired Activity LED behavior */
1175 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1177 /* set the LED to OFF */
1178 port_led_state &= EM_MSG_LED_VALUE_OFF;
1179 port_led_state |= (ap->port_no | (link->pmp << 8));
1180 ap->ops->transmit_led_message(ap, port_led_state, 4);
1182 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1183 if (val == BLINK_OFF) {
1184 /* set LED to ON for idle */
1185 port_led_state &= EM_MSG_LED_VALUE_OFF;
1186 port_led_state |= (ap->port_no | (link->pmp << 8));
1187 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1188 ap->ops->transmit_led_message(ap, port_led_state, 4);
1191 emp->blink_policy = val;
1195 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1197 struct ata_link *link = dev->link;
1198 struct ata_port *ap = link->ap;
1199 struct ahci_port_priv *pp = ap->private_data;
1200 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1202 /* display the saved value of activity behavior for this
1205 return sprintf(buf, "%d\n", emp->blink_policy);
1208 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1209 int port_no, void __iomem *mmio,
1210 void __iomem *port_mmio)
1212 struct ahci_host_priv *hpriv = ap->host->private_data;
1213 const char *emsg = NULL;
1217 /* make sure port is not active */
1218 rc = ahci_deinit_port(ap, &emsg);
1220 dev_warn(dev, "%s (%d)\n", emsg, rc);
1223 tmp = readl(port_mmio + PORT_SCR_ERR);
1224 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1225 writel(tmp, port_mmio + PORT_SCR_ERR);
1227 /* clear port IRQ */
1228 tmp = readl(port_mmio + PORT_IRQ_STAT);
1229 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1231 writel(tmp, port_mmio + PORT_IRQ_STAT);
1233 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1235 /* mark esata ports */
1236 tmp = readl(port_mmio + PORT_CMD);
1237 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1238 ap->pflags |= ATA_PFLAG_EXTERNAL;
1241 void ahci_init_controller(struct ata_host *host)
1243 struct ahci_host_priv *hpriv = host->private_data;
1244 void __iomem *mmio = hpriv->mmio;
1246 void __iomem *port_mmio;
1249 for (i = 0; i < host->n_ports; i++) {
1250 struct ata_port *ap = host->ports[i];
1252 port_mmio = ahci_port_base(ap);
1253 if (ata_port_is_dummy(ap))
1256 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1259 tmp = readl(mmio + HOST_CTL);
1260 VPRINTK("HOST_CTL 0x%x\n", tmp);
1261 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1262 tmp = readl(mmio + HOST_CTL);
1263 VPRINTK("HOST_CTL 0x%x\n", tmp);
1265 EXPORT_SYMBOL_GPL(ahci_init_controller);
1267 static void ahci_dev_config(struct ata_device *dev)
1269 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1271 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1272 dev->max_sectors = 255;
1274 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1278 unsigned int ahci_dev_classify(struct ata_port *ap)
1280 void __iomem *port_mmio = ahci_port_base(ap);
1281 struct ata_taskfile tf;
1284 tmp = readl(port_mmio + PORT_SIG);
1285 tf.lbah = (tmp >> 24) & 0xff;
1286 tf.lbam = (tmp >> 16) & 0xff;
1287 tf.lbal = (tmp >> 8) & 0xff;
1288 tf.nsect = (tmp) & 0xff;
1290 return ata_dev_classify(&tf);
1292 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1294 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1297 dma_addr_t cmd_tbl_dma;
1299 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1301 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1302 pp->cmd_slot[tag].status = 0;
1303 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1304 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1306 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1308 int ahci_kick_engine(struct ata_port *ap)
1310 void __iomem *port_mmio = ahci_port_base(ap);
1311 struct ahci_host_priv *hpriv = ap->host->private_data;
1312 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1317 rc = hpriv->stop_engine(ap);
1322 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1324 busy = status & (ATA_BUSY | ATA_DRQ);
1325 if (!busy && !sata_pmp_attached(ap)) {
1330 if (!(hpriv->cap & HOST_CAP_CLO)) {
1336 tmp = readl(port_mmio + PORT_CMD);
1337 tmp |= PORT_CMD_CLO;
1338 writel(tmp, port_mmio + PORT_CMD);
1341 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1342 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1343 if (tmp & PORT_CMD_CLO)
1346 /* restart engine */
1348 hpriv->start_engine(ap);
1351 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1353 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1354 struct ata_taskfile *tf, int is_cmd, u16 flags,
1355 unsigned long timeout_msec)
1357 const u32 cmd_fis_len = 5; /* five dwords */
1358 struct ahci_port_priv *pp = ap->private_data;
1359 void __iomem *port_mmio = ahci_port_base(ap);
1360 u8 *fis = pp->cmd_tbl;
1363 /* prep the command */
1364 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1365 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1367 /* set port value for softreset of Port Multiplier */
1368 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1369 tmp = readl(port_mmio + PORT_FBS);
1370 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1371 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1372 writel(tmp, port_mmio + PORT_FBS);
1373 pp->fbs_last_dev = pmp;
1377 writel(1, port_mmio + PORT_CMD_ISSUE);
1380 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1381 0x1, 0x1, 1, timeout_msec);
1383 ahci_kick_engine(ap);
1387 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1392 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1393 int pmp, unsigned long deadline,
1394 int (*check_ready)(struct ata_link *link))
1396 struct ata_port *ap = link->ap;
1397 struct ahci_host_priv *hpriv = ap->host->private_data;
1398 struct ahci_port_priv *pp = ap->private_data;
1399 const char *reason = NULL;
1400 unsigned long now, msecs;
1401 struct ata_taskfile tf;
1402 bool fbs_disabled = false;
1407 /* prepare for SRST (AHCI-1.1 10.4.1) */
1408 rc = ahci_kick_engine(ap);
1409 if (rc && rc != -EOPNOTSUPP)
1410 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1413 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1414 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1415 * that is attached to port multiplier.
1417 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1418 ahci_disable_fbs(ap);
1419 fbs_disabled = true;
1422 ata_tf_init(link->device, &tf);
1424 /* issue the first H2D Register FIS */
1427 if (time_after(deadline, now))
1428 msecs = jiffies_to_msecs(deadline - now);
1431 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1432 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1434 reason = "1st FIS failed";
1438 /* spec says at least 5us, but be generous and sleep for 1ms */
1441 /* issue the second H2D Register FIS */
1442 tf.ctl &= ~ATA_SRST;
1443 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1445 /* wait for link to become ready */
1446 rc = ata_wait_after_reset(link, deadline, check_ready);
1447 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1449 * Workaround for cases where link online status can't
1450 * be trusted. Treat device readiness timeout as link
1453 ata_link_info(link, "device not ready, treating as offline\n");
1454 *class = ATA_DEV_NONE;
1456 /* link occupied, -ENODEV too is an error */
1457 reason = "device not ready";
1460 *class = ahci_dev_classify(ap);
1462 /* re-enable FBS if disabled before */
1464 ahci_enable_fbs(ap);
1466 DPRINTK("EXIT, class=%u\n", *class);
1470 ata_link_err(link, "softreset failed (%s)\n", reason);
1474 int ahci_check_ready(struct ata_link *link)
1476 void __iomem *port_mmio = ahci_port_base(link->ap);
1477 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1479 return ata_check_ready(status);
1481 EXPORT_SYMBOL_GPL(ahci_check_ready);
1483 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1484 unsigned long deadline)
1486 int pmp = sata_srst_pmp(link);
1490 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1492 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1494 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1496 void __iomem *port_mmio = ahci_port_base(link->ap);
1497 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1498 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1501 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1502 * which can save timeout delay.
1504 if (irq_status & PORT_IRQ_BAD_PMP)
1507 return ata_check_ready(status);
1510 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1511 unsigned long deadline)
1513 struct ata_port *ap = link->ap;
1514 void __iomem *port_mmio = ahci_port_base(ap);
1515 int pmp = sata_srst_pmp(link);
1521 rc = ahci_do_softreset(link, class, pmp, deadline,
1522 ahci_bad_pmp_check_ready);
1525 * Soft reset fails with IPMS set when PMP is enabled but
1526 * SATA HDD/ODD is connected to SATA port, do soft reset
1530 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1531 if (irq_sts & PORT_IRQ_BAD_PMP) {
1533 "applying PMP SRST workaround "
1535 rc = ahci_do_softreset(link, class, 0, deadline,
1543 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1544 unsigned long deadline, bool *online)
1546 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1547 struct ata_port *ap = link->ap;
1548 struct ahci_port_priv *pp = ap->private_data;
1549 struct ahci_host_priv *hpriv = ap->host->private_data;
1550 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1551 struct ata_taskfile tf;
1556 hpriv->stop_engine(ap);
1558 /* clear D2H reception area to properly wait for D2H FIS */
1559 ata_tf_init(link->device, &tf);
1560 tf.command = ATA_BUSY;
1561 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1563 rc = sata_link_hardreset(link, timing, deadline, online,
1566 hpriv->start_engine(ap);
1569 *class = ahci_dev_classify(ap);
1571 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1574 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1576 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1577 unsigned long deadline)
1581 return ahci_do_hardreset(link, class, deadline, &online);
1584 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1586 struct ata_port *ap = link->ap;
1587 void __iomem *port_mmio = ahci_port_base(ap);
1590 ata_std_postreset(link, class);
1592 /* Make sure port's ATAPI bit is set appropriately */
1593 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1594 if (*class == ATA_DEV_ATAPI)
1595 new_tmp |= PORT_CMD_ATAPI;
1597 new_tmp &= ~PORT_CMD_ATAPI;
1598 if (new_tmp != tmp) {
1599 writel(new_tmp, port_mmio + PORT_CMD);
1600 readl(port_mmio + PORT_CMD); /* flush */
1604 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1606 struct scatterlist *sg;
1607 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1613 * Next, the S/G list.
1615 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1616 dma_addr_t addr = sg_dma_address(sg);
1617 u32 sg_len = sg_dma_len(sg);
1619 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1620 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1621 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1627 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1629 struct ata_port *ap = qc->ap;
1630 struct ahci_port_priv *pp = ap->private_data;
1632 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1633 return ata_std_qc_defer(qc);
1635 return sata_pmp_qc_defer_cmd_switch(qc);
1638 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1640 struct ata_port *ap = qc->ap;
1641 struct ahci_port_priv *pp = ap->private_data;
1642 int is_atapi = ata_is_atapi(qc->tf.protocol);
1645 const u32 cmd_fis_len = 5; /* five dwords */
1646 unsigned int n_elem;
1649 * Fill in command table information. First, the header,
1650 * a SATA Register - Host to Device command FIS.
1652 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
1654 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1656 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1657 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1661 if (qc->flags & ATA_QCFLAG_DMAMAP)
1662 n_elem = ahci_fill_sg(qc, cmd_tbl);
1665 * Fill in command slot information.
1667 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1668 if (qc->tf.flags & ATA_TFLAG_WRITE)
1669 opts |= AHCI_CMD_WRITE;
1671 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1673 ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
1676 static void ahci_fbs_dec_intr(struct ata_port *ap)
1678 struct ahci_port_priv *pp = ap->private_data;
1679 void __iomem *port_mmio = ahci_port_base(ap);
1680 u32 fbs = readl(port_mmio + PORT_FBS);
1684 BUG_ON(!pp->fbs_enabled);
1686 /* time to wait for DEC is not specified by AHCI spec,
1687 * add a retry loop for safety.
1689 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1690 fbs = readl(port_mmio + PORT_FBS);
1691 while ((fbs & PORT_FBS_DEC) && retries--) {
1693 fbs = readl(port_mmio + PORT_FBS);
1696 if (fbs & PORT_FBS_DEC)
1697 dev_err(ap->host->dev, "failed to clear device error\n");
1700 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1702 struct ahci_host_priv *hpriv = ap->host->private_data;
1703 struct ahci_port_priv *pp = ap->private_data;
1704 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1705 struct ata_link *link = NULL;
1706 struct ata_queued_cmd *active_qc;
1707 struct ata_eh_info *active_ehi;
1708 bool fbs_need_dec = false;
1711 /* determine active link with error */
1712 if (pp->fbs_enabled) {
1713 void __iomem *port_mmio = ahci_port_base(ap);
1714 u32 fbs = readl(port_mmio + PORT_FBS);
1715 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1717 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1718 link = &ap->pmp_link[pmp];
1719 fbs_need_dec = true;
1723 ata_for_each_link(link, ap, EDGE)
1724 if (ata_link_active(link))
1730 active_qc = ata_qc_from_tag(ap, link->active_tag);
1731 active_ehi = &link->eh_info;
1733 /* record irq stat */
1734 ata_ehi_clear_desc(host_ehi);
1735 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1737 /* AHCI needs SError cleared; otherwise, it might lock up */
1738 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1739 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1740 host_ehi->serror |= serror;
1742 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1743 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1744 irq_stat &= ~PORT_IRQ_IF_ERR;
1746 if (irq_stat & PORT_IRQ_TF_ERR) {
1747 /* If qc is active, charge it; otherwise, the active
1748 * link. There's no active qc on NCQ errors. It will
1749 * be determined by EH by reading log page 10h.
1752 active_qc->err_mask |= AC_ERR_DEV;
1754 active_ehi->err_mask |= AC_ERR_DEV;
1756 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1757 host_ehi->serror &= ~SERR_INTERNAL;
1760 if (irq_stat & PORT_IRQ_UNK_FIS) {
1761 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1763 active_ehi->err_mask |= AC_ERR_HSM;
1764 active_ehi->action |= ATA_EH_RESET;
1765 ata_ehi_push_desc(active_ehi,
1766 "unknown FIS %08x %08x %08x %08x" ,
1767 unk[0], unk[1], unk[2], unk[3]);
1770 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1771 active_ehi->err_mask |= AC_ERR_HSM;
1772 active_ehi->action |= ATA_EH_RESET;
1773 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1776 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1777 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1778 host_ehi->action |= ATA_EH_RESET;
1779 ata_ehi_push_desc(host_ehi, "host bus error");
1782 if (irq_stat & PORT_IRQ_IF_ERR) {
1784 active_ehi->err_mask |= AC_ERR_DEV;
1786 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1787 host_ehi->action |= ATA_EH_RESET;
1790 ata_ehi_push_desc(host_ehi, "interface fatal error");
1793 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1794 ata_ehi_hotplugged(host_ehi);
1795 ata_ehi_push_desc(host_ehi, "%s",
1796 irq_stat & PORT_IRQ_CONNECT ?
1797 "connection status changed" : "PHY RDY changed");
1800 /* okay, let's hand over to EH */
1802 if (irq_stat & PORT_IRQ_FREEZE)
1803 ata_port_freeze(ap);
1804 else if (fbs_need_dec) {
1805 ata_link_abort(link);
1806 ahci_fbs_dec_intr(ap);
1811 static void ahci_handle_port_interrupt(struct ata_port *ap,
1812 void __iomem *port_mmio, u32 status)
1814 struct ata_eh_info *ehi = &ap->link.eh_info;
1815 struct ahci_port_priv *pp = ap->private_data;
1816 struct ahci_host_priv *hpriv = ap->host->private_data;
1817 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1821 /* ignore BAD_PMP while resetting */
1822 if (unlikely(resetting))
1823 status &= ~PORT_IRQ_BAD_PMP;
1825 if (sata_lpm_ignore_phy_events(&ap->link)) {
1826 status &= ~PORT_IRQ_PHYRDY;
1827 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1830 if (unlikely(status & PORT_IRQ_ERROR)) {
1831 ahci_error_intr(ap, status);
1835 if (status & PORT_IRQ_SDB_FIS) {
1836 /* If SNotification is available, leave notification
1837 * handling to sata_async_notification(). If not,
1838 * emulate it by snooping SDB FIS RX area.
1840 * Snooping FIS RX area is probably cheaper than
1841 * poking SNotification but some constrollers which
1842 * implement SNotification, ICH9 for example, don't
1843 * store AN SDB FIS into receive area.
1845 if (hpriv->cap & HOST_CAP_SNTF)
1846 sata_async_notification(ap);
1848 /* If the 'N' bit in word 0 of the FIS is set,
1849 * we just received asynchronous notification.
1850 * Tell libata about it.
1852 * Lack of SNotification should not appear in
1853 * ahci 1.2, so the workaround is unnecessary
1854 * when FBS is enabled.
1856 if (pp->fbs_enabled)
1859 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1860 u32 f0 = le32_to_cpu(f[0]);
1862 sata_async_notification(ap);
1867 /* pp->active_link is not reliable once FBS is enabled, both
1868 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1869 * NCQ and non-NCQ commands may be in flight at the same time.
1871 if (pp->fbs_enabled) {
1872 if (ap->qc_active) {
1873 qc_active = readl(port_mmio + PORT_SCR_ACT);
1874 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1877 /* pp->active_link is valid iff any command is in flight */
1878 if (ap->qc_active && pp->active_link->sactive)
1879 qc_active = readl(port_mmio + PORT_SCR_ACT);
1881 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1885 rc = ata_qc_complete_multiple(ap, qc_active);
1887 /* while resetting, invalid completions are expected */
1888 if (unlikely(rc < 0 && !resetting)) {
1889 ehi->err_mask |= AC_ERR_HSM;
1890 ehi->action |= ATA_EH_RESET;
1891 ata_port_freeze(ap);
1895 static void ahci_port_intr(struct ata_port *ap)
1897 void __iomem *port_mmio = ahci_port_base(ap);
1900 status = readl(port_mmio + PORT_IRQ_STAT);
1901 writel(status, port_mmio + PORT_IRQ_STAT);
1903 ahci_handle_port_interrupt(ap, port_mmio, status);
1906 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1908 struct ata_port *ap = dev_instance;
1909 void __iomem *port_mmio = ahci_port_base(ap);
1914 status = readl(port_mmio + PORT_IRQ_STAT);
1915 writel(status, port_mmio + PORT_IRQ_STAT);
1917 spin_lock(ap->lock);
1918 ahci_handle_port_interrupt(ap, port_mmio, status);
1919 spin_unlock(ap->lock);
1926 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1928 unsigned int i, handled = 0;
1930 for (i = 0; i < host->n_ports; i++) {
1931 struct ata_port *ap;
1933 if (!(irq_masked & (1 << i)))
1936 ap = host->ports[i];
1939 VPRINTK("port %u\n", i);
1941 VPRINTK("port %u (no irq)\n", i);
1942 if (ata_ratelimit())
1944 "interrupt on disabled port %u\n", i);
1952 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1954 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1956 struct ata_host *host = dev_instance;
1957 struct ahci_host_priv *hpriv;
1958 unsigned int rc = 0;
1960 u32 irq_stat, irq_masked;
1964 hpriv = host->private_data;
1967 /* sigh. 0xffffffff is a valid return from h/w */
1968 irq_stat = readl(mmio + HOST_IRQ_STAT);
1972 irq_masked = irq_stat & hpriv->port_map;
1974 spin_lock(&host->lock);
1976 rc = ahci_handle_port_intr(host, irq_masked);
1978 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1979 * it should be cleared after all the port events are cleared;
1980 * otherwise, it will raise a spurious interrupt after each
1981 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1984 * Also, use the unmasked value to clear interrupt as spurious
1985 * pending event on a dummy port might cause screaming IRQ.
1987 writel(irq_stat, mmio + HOST_IRQ_STAT);
1989 spin_unlock(&host->lock);
1993 return IRQ_RETVAL(rc);
1996 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1998 struct ata_port *ap = qc->ap;
1999 void __iomem *port_mmio = ahci_port_base(ap);
2000 struct ahci_port_priv *pp = ap->private_data;
2002 /* Keep track of the currently active link. It will be used
2003 * in completion path to determine whether NCQ phase is in
2006 pp->active_link = qc->dev->link;
2008 if (ata_is_ncq(qc->tf.protocol))
2009 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
2011 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2012 u32 fbs = readl(port_mmio + PORT_FBS);
2013 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2014 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2015 writel(fbs, port_mmio + PORT_FBS);
2016 pp->fbs_last_dev = qc->dev->link->pmp;
2019 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
2021 ahci_sw_activity(qc->dev->link);
2025 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2027 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2029 struct ahci_port_priv *pp = qc->ap->private_data;
2030 u8 *rx_fis = pp->rx_fis;
2032 if (pp->fbs_enabled)
2033 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2036 * After a successful execution of an ATA PIO data-in command,
2037 * the device doesn't send D2H Reg FIS to update the TF and
2038 * the host should take TF and E_Status from the preceding PIO
2041 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2042 !(qc->flags & ATA_QCFLAG_FAILED)) {
2043 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2044 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2046 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2051 static void ahci_freeze(struct ata_port *ap)
2053 void __iomem *port_mmio = ahci_port_base(ap);
2056 writel(0, port_mmio + PORT_IRQ_MASK);
2059 static void ahci_thaw(struct ata_port *ap)
2061 struct ahci_host_priv *hpriv = ap->host->private_data;
2062 void __iomem *mmio = hpriv->mmio;
2063 void __iomem *port_mmio = ahci_port_base(ap);
2065 struct ahci_port_priv *pp = ap->private_data;
2068 tmp = readl(port_mmio + PORT_IRQ_STAT);
2069 writel(tmp, port_mmio + PORT_IRQ_STAT);
2070 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2072 /* turn IRQ back on */
2073 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2076 void ahci_error_handler(struct ata_port *ap)
2078 struct ahci_host_priv *hpriv = ap->host->private_data;
2080 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2081 /* restart engine */
2082 hpriv->stop_engine(ap);
2083 hpriv->start_engine(ap);
2086 sata_pmp_error_handler(ap);
2088 if (!ata_dev_enabled(ap->link.device))
2089 hpriv->stop_engine(ap);
2091 EXPORT_SYMBOL_GPL(ahci_error_handler);
2093 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2095 struct ata_port *ap = qc->ap;
2097 /* make DMA engine forget about the failed command */
2098 if (qc->flags & ATA_QCFLAG_FAILED)
2099 ahci_kick_engine(ap);
2102 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2104 struct ahci_host_priv *hpriv = ap->host->private_data;
2105 void __iomem *port_mmio = ahci_port_base(ap);
2106 struct ata_device *dev = ap->link.device;
2107 u32 devslp, dm, dito, mdat, deto;
2109 unsigned int err_mask;
2111 devslp = readl(port_mmio + PORT_DEVSLP);
2112 if (!(devslp & PORT_DEVSLP_DSP)) {
2113 dev_info(ap->host->dev, "port does not support device sleep\n");
2117 /* disable device sleep */
2119 if (devslp & PORT_DEVSLP_ADSE) {
2120 writel(devslp & ~PORT_DEVSLP_ADSE,
2121 port_mmio + PORT_DEVSLP);
2122 err_mask = ata_dev_set_feature(dev,
2123 SETFEATURES_SATA_DISABLE,
2125 if (err_mask && err_mask != AC_ERR_DEV)
2126 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2131 /* device sleep was already enabled */
2132 if (devslp & PORT_DEVSLP_ADSE)
2135 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2136 rc = hpriv->stop_engine(ap);
2140 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2141 dito = devslp_idle_timeout / (dm + 1);
2145 /* Use the nominal value 10 ms if the read MDAT is zero,
2146 * the nominal value of DETO is 20 ms.
2148 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2149 ATA_LOG_DEVSLP_VALID_MASK) {
2150 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2151 ATA_LOG_DEVSLP_MDAT_MASK;
2154 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2162 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2163 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2164 (deto << PORT_DEVSLP_DETO_OFFSET) |
2166 writel(devslp, port_mmio + PORT_DEVSLP);
2168 hpriv->start_engine(ap);
2170 /* enable device sleep feature for the drive */
2171 err_mask = ata_dev_set_feature(dev,
2172 SETFEATURES_SATA_ENABLE,
2174 if (err_mask && err_mask != AC_ERR_DEV)
2175 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2178 static void ahci_enable_fbs(struct ata_port *ap)
2180 struct ahci_host_priv *hpriv = ap->host->private_data;
2181 struct ahci_port_priv *pp = ap->private_data;
2182 void __iomem *port_mmio = ahci_port_base(ap);
2186 if (!pp->fbs_supported)
2189 fbs = readl(port_mmio + PORT_FBS);
2190 if (fbs & PORT_FBS_EN) {
2191 pp->fbs_enabled = true;
2192 pp->fbs_last_dev = -1; /* initialization */
2196 rc = hpriv->stop_engine(ap);
2200 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2201 fbs = readl(port_mmio + PORT_FBS);
2202 if (fbs & PORT_FBS_EN) {
2203 dev_info(ap->host->dev, "FBS is enabled\n");
2204 pp->fbs_enabled = true;
2205 pp->fbs_last_dev = -1; /* initialization */
2207 dev_err(ap->host->dev, "Failed to enable FBS\n");
2209 hpriv->start_engine(ap);
2212 static void ahci_disable_fbs(struct ata_port *ap)
2214 struct ahci_host_priv *hpriv = ap->host->private_data;
2215 struct ahci_port_priv *pp = ap->private_data;
2216 void __iomem *port_mmio = ahci_port_base(ap);
2220 if (!pp->fbs_supported)
2223 fbs = readl(port_mmio + PORT_FBS);
2224 if ((fbs & PORT_FBS_EN) == 0) {
2225 pp->fbs_enabled = false;
2229 rc = hpriv->stop_engine(ap);
2233 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2234 fbs = readl(port_mmio + PORT_FBS);
2235 if (fbs & PORT_FBS_EN)
2236 dev_err(ap->host->dev, "Failed to disable FBS\n");
2238 dev_info(ap->host->dev, "FBS is disabled\n");
2239 pp->fbs_enabled = false;
2242 hpriv->start_engine(ap);
2245 static void ahci_pmp_attach(struct ata_port *ap)
2247 void __iomem *port_mmio = ahci_port_base(ap);
2248 struct ahci_port_priv *pp = ap->private_data;
2251 cmd = readl(port_mmio + PORT_CMD);
2252 cmd |= PORT_CMD_PMP;
2253 writel(cmd, port_mmio + PORT_CMD);
2255 ahci_enable_fbs(ap);
2257 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2260 * We must not change the port interrupt mask register if the
2261 * port is marked frozen, the value in pp->intr_mask will be
2262 * restored later when the port is thawed.
2264 * Note that during initialization, the port is marked as
2265 * frozen since the irq handler is not yet registered.
2267 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2268 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2271 static void ahci_pmp_detach(struct ata_port *ap)
2273 void __iomem *port_mmio = ahci_port_base(ap);
2274 struct ahci_port_priv *pp = ap->private_data;
2277 ahci_disable_fbs(ap);
2279 cmd = readl(port_mmio + PORT_CMD);
2280 cmd &= ~PORT_CMD_PMP;
2281 writel(cmd, port_mmio + PORT_CMD);
2283 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2285 /* see comment above in ahci_pmp_attach() */
2286 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2287 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2290 int ahci_port_resume(struct ata_port *ap)
2292 ahci_rpm_get_port(ap);
2295 ahci_start_port(ap);
2297 if (sata_pmp_attached(ap))
2298 ahci_pmp_attach(ap);
2300 ahci_pmp_detach(ap);
2304 EXPORT_SYMBOL_GPL(ahci_port_resume);
2307 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2309 const char *emsg = NULL;
2312 rc = ahci_deinit_port(ap, &emsg);
2314 ahci_power_down(ap);
2316 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2317 ata_port_freeze(ap);
2320 ahci_rpm_put_port(ap);
2325 static int ahci_port_start(struct ata_port *ap)
2327 struct ahci_host_priv *hpriv = ap->host->private_data;
2328 struct device *dev = ap->host->dev;
2329 struct ahci_port_priv *pp;
2332 size_t dma_sz, rx_fis_sz;
2334 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2338 if (ap->host->n_ports > 1) {
2339 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2340 if (!pp->irq_desc) {
2341 devm_kfree(dev, pp);
2344 snprintf(pp->irq_desc, 8,
2345 "%s%d", dev_driver_string(dev), ap->port_no);
2348 /* check FBS capability */
2349 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2350 void __iomem *port_mmio = ahci_port_base(ap);
2351 u32 cmd = readl(port_mmio + PORT_CMD);
2352 if (cmd & PORT_CMD_FBSCP)
2353 pp->fbs_supported = true;
2354 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2355 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2357 pp->fbs_supported = true;
2359 dev_warn(dev, "port %d is not capable of FBS\n",
2363 if (pp->fbs_supported) {
2364 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2365 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2367 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2368 rx_fis_sz = AHCI_RX_FIS_SZ;
2371 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2374 memset(mem, 0, dma_sz);
2377 * First item in chunk of DMA memory: 32-slot command table,
2378 * 32 bytes each in size
2381 pp->cmd_slot_dma = mem_dma;
2383 mem += AHCI_CMD_SLOT_SZ;
2384 mem_dma += AHCI_CMD_SLOT_SZ;
2387 * Second item: Received-FIS area
2390 pp->rx_fis_dma = mem_dma;
2393 mem_dma += rx_fis_sz;
2396 * Third item: data area for storing a single command
2397 * and its scatter-gather table
2400 pp->cmd_tbl_dma = mem_dma;
2403 * Save off initial list of interrupts to be enabled.
2404 * This could be changed later
2406 pp->intr_mask = DEF_PORT_IRQ;
2409 * Switch to per-port locking in case each port has its own MSI vector.
2411 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2412 spin_lock_init(&pp->lock);
2413 ap->lock = &pp->lock;
2416 ap->private_data = pp;
2418 /* engage engines, captain */
2419 return ahci_port_resume(ap);
2422 static void ahci_port_stop(struct ata_port *ap)
2424 const char *emsg = NULL;
2425 struct ahci_host_priv *hpriv = ap->host->private_data;
2426 void __iomem *host_mmio = hpriv->mmio;
2429 /* de-initialize port */
2430 rc = ahci_deinit_port(ap, &emsg);
2432 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2435 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2438 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2441 void ahci_print_info(struct ata_host *host, const char *scc_s)
2443 struct ahci_host_priv *hpriv = host->private_data;
2444 u32 vers, cap, cap2, impl, speed;
2445 const char *speed_s;
2447 vers = hpriv->version;
2450 impl = hpriv->port_map;
2452 speed = (cap >> 20) & 0xf;
2455 else if (speed == 2)
2457 else if (speed == 3)
2463 "AHCI %02x%02x.%02x%02x "
2464 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2467 (vers >> 24) & 0xff,
2468 (vers >> 16) & 0xff,
2472 ((cap >> 8) & 0x1f) + 1,
2486 cap & HOST_CAP_64 ? "64bit " : "",
2487 cap & HOST_CAP_NCQ ? "ncq " : "",
2488 cap & HOST_CAP_SNTF ? "sntf " : "",
2489 cap & HOST_CAP_MPS ? "ilck " : "",
2490 cap & HOST_CAP_SSS ? "stag " : "",
2491 cap & HOST_CAP_ALPM ? "pm " : "",
2492 cap & HOST_CAP_LED ? "led " : "",
2493 cap & HOST_CAP_CLO ? "clo " : "",
2494 cap & HOST_CAP_ONLY ? "only " : "",
2495 cap & HOST_CAP_PMP ? "pmp " : "",
2496 cap & HOST_CAP_FBS ? "fbs " : "",
2497 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2498 cap & HOST_CAP_SSC ? "slum " : "",
2499 cap & HOST_CAP_PART ? "part " : "",
2500 cap & HOST_CAP_CCC ? "ccc " : "",
2501 cap & HOST_CAP_EMS ? "ems " : "",
2502 cap & HOST_CAP_SXS ? "sxs " : "",
2503 cap2 & HOST_CAP2_DESO ? "deso " : "",
2504 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2505 cap2 & HOST_CAP2_SDS ? "sds " : "",
2506 cap2 & HOST_CAP2_APST ? "apst " : "",
2507 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2508 cap2 & HOST_CAP2_BOH ? "boh " : ""
2511 EXPORT_SYMBOL_GPL(ahci_print_info);
2513 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2514 struct ata_port_info *pi)
2517 void __iomem *mmio = hpriv->mmio;
2518 u32 em_loc = readl(mmio + HOST_EM_LOC);
2519 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2521 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2524 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2528 hpriv->em_loc = ((em_loc >> 16) * 4);
2529 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2530 hpriv->em_msg_type = messages;
2531 pi->flags |= ATA_FLAG_EM;
2532 if (!(em_ctl & EM_CTL_ALHD))
2533 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2536 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2538 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2539 struct scsi_host_template *sht)
2541 struct ahci_host_priv *hpriv = host->private_data;
2544 rc = ata_host_start(host);
2548 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2549 * allocated. That is one MSI per port, starting from @irq.
2551 for (i = 0; i < host->n_ports; i++) {
2552 struct ahci_port_priv *pp = host->ports[i]->private_data;
2553 int irq = hpriv->get_irq_vector(host, i);
2555 /* Do not receive interrupts sent by dummy ports */
2561 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2562 0, pp->irq_desc, host->ports[i]);
2566 ata_port_desc(host->ports[i], "irq %d", irq);
2569 return ata_host_register(host, sht);
2573 * ahci_host_activate - start AHCI host, request IRQs and register it
2574 * @host: target ATA host
2575 * @sht: scsi_host_template to use when registering the host
2578 * Inherited from calling layer (may sleep).
2581 * 0 on success, -errno otherwise.
2583 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2585 struct ahci_host_priv *hpriv = host->private_data;
2586 int irq = hpriv->irq;
2589 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2590 if (hpriv->irq_handler)
2592 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2593 if (!hpriv->get_irq_vector) {
2595 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2599 rc = ahci_host_activate_multi_irqs(host, sht);
2601 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2608 EXPORT_SYMBOL_GPL(ahci_host_activate);
2610 MODULE_AUTHOR("Jeff Garzik");
2611 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2612 MODULE_LICENSE("GPL");