drivers/ata/ahci_octeon.c

   1 /*
   2  * SATA glue for Cavium Octeon III SOCs.
   3  *
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file "COPYING" in the main directory of this archive
   7  * for more details.
   8  *
   9  * Copyright (C) 2010-2015 Cavium Networks
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of_platform.h>
  17
  18 #include <asm/octeon/octeon.h>
  19
  20 #define CVMX_SATA_UCTL_SHIM_CFG         0xE8
  21
  22 #define SATA_UCTL_ENDIAN_MODE_BIG       1
  23 #define SATA_UCTL_ENDIAN_MODE_LITTLE    0
  24 #define SATA_UCTL_ENDIAN_MODE_MASK      3
  25
  26 #define SATA_UCTL_DMA_ENDIAN_MODE_SHIFT 8
  27 #define SATA_UCTL_CSR_ENDIAN_MODE_SHIFT 0
  28 #define SATA_UCTL_DMA_READ_CMD_SHIFT    12
  29
  30 static int ahci_octeon_probe(struct platform_device *pdev)
  31 {
  32         struct device *dev = &pdev->dev;
  33         struct device_node *node = dev->of_node;
  34         struct resource *res;
  35         void __iomem *base;
  36         u64 cfg;
  37         int ret;
  38
  39         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  40         base = devm_ioremap_resource(&pdev->dev, res);
  41         if (IS_ERR(base))
  42                 return PTR_ERR(base);
  43
  44         cfg = cvmx_readq_csr(base + CVMX_SATA_UCTL_SHIM_CFG);
  45
  46         cfg &= ~(SATA_UCTL_ENDIAN_MODE_MASK << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT);
  47         cfg &= ~(SATA_UCTL_ENDIAN_MODE_MASK << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT);
  48
  49 #ifdef __BIG_ENDIAN
  50         cfg |= SATA_UCTL_ENDIAN_MODE_BIG << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT;
  51         cfg |= SATA_UCTL_ENDIAN_MODE_BIG << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT;
  52 #else
  53         cfg |= SATA_UCTL_ENDIAN_MODE_LITTLE << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT;
  54         cfg |= SATA_UCTL_ENDIAN_MODE_LITTLE << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT;
  55 #endif
  56
  57         cfg |= 1 << SATA_UCTL_DMA_READ_CMD_SHIFT;
  58
  59         cvmx_writeq_csr(base + CVMX_SATA_UCTL_SHIM_CFG, cfg);
  60
  61         if (!node) {
  62                 dev_err(dev, "no device node, failed to add octeon sata\n");
  63                 return -ENODEV;
  64         }
  65
  66         ret = of_platform_populate(node, NULL, NULL, dev);
  67         if (ret) {
  68                 dev_err(dev, "failed to add ahci-platform core\n");
  69                 return ret;
  70         }
  71
  72         return 0;
  73 }
  74
  75 static const struct of_device_id octeon_ahci_match[] = {
  76         { .compatible = "cavium,octeon-7130-sata-uctl", },
  77         { /* sentinel */ }
  78 };
  79 MODULE_DEVICE_TABLE(of, octeon_ahci_match);
  80
  81 static struct platform_driver ahci_octeon_driver = {
  82         .probe          = ahci_octeon_probe,
  83         .driver         = {
  84                 .name   = "octeon-ahci",
  85                 .of_match_table = octeon_ahci_match,
  86         },
  87 };
  88
  89 module_platform_driver(ahci_octeon_driver);
  90
  91 MODULE_LICENSE("GPL");
  92 MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>");
  93 MODULE_DESCRIPTION("Cavium Inc. sata config.");