1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ahci.c - AHCI SATA support
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <linux/msi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <linux/libata.h>
33 #include <linux/ahci-remap.h>
34 #include <linux/io-64-nonatomic-lo-hi.h>
37 #define DRV_NAME "ahci"
38 #define DRV_VERSION "3.0"
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
49 /* board IDs by feature in alphabetical order */
58 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_sb700, /* for SB700 and SB800 */
70 * board IDs for Intel chipsets that support more than 6 ports
71 * *and* end up needing the PCS quirk.
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
79 board_ahci_mcp79 = board_ahci_mcp77,
82 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
83 static void ahci_remove_one(struct pci_dev *dev);
84 static void ahci_shutdown_one(struct pci_dev *dev);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
90 static bool is_mcp89_apple(struct pci_dev *pdev);
91 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
94 static int ahci_pci_device_runtime_suspend(struct device *dev);
95 static int ahci_pci_device_runtime_resume(struct device *dev);
96 #ifdef CONFIG_PM_SLEEP
97 static int ahci_pci_device_suspend(struct device *dev);
98 static int ahci_pci_device_resume(struct device *dev);
100 #endif /* CONFIG_PM */
102 static struct scsi_host_template ahci_sht = {
106 static struct ata_port_operations ahci_vt8251_ops = {
107 .inherits = &ahci_ops,
108 .hardreset = ahci_vt8251_hardreset,
111 static struct ata_port_operations ahci_p5wdh_ops = {
112 .inherits = &ahci_ops,
113 .hardreset = ahci_p5wdh_hardreset,
116 static struct ata_port_operations ahci_avn_ops = {
117 .inherits = &ahci_ops,
118 .hardreset = ahci_avn_hardreset,
121 static const struct ata_port_info ahci_port_info[] = {
124 .flags = AHCI_FLAG_COMMON,
125 .pio_mask = ATA_PIO4,
126 .udma_mask = ATA_UDMA6,
127 .port_ops = &ahci_ops,
129 [board_ahci_ign_iferr] = {
130 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
136 [board_ahci_mobile] = {
137 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
138 .flags = AHCI_FLAG_COMMON,
139 .pio_mask = ATA_PIO4,
140 .udma_mask = ATA_UDMA6,
141 .port_ops = &ahci_ops,
143 [board_ahci_nomsi] = {
144 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
150 [board_ahci_noncq] = {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
152 .flags = AHCI_FLAG_COMMON,
153 .pio_mask = ATA_PIO4,
154 .udma_mask = ATA_UDMA6,
155 .port_ops = &ahci_ops,
157 [board_ahci_nosntf] = {
158 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
159 .flags = AHCI_FLAG_COMMON,
160 .pio_mask = ATA_PIO4,
161 .udma_mask = ATA_UDMA6,
162 .port_ops = &ahci_ops,
164 [board_ahci_yes_fbs] = {
165 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
166 .flags = AHCI_FLAG_COMMON,
167 .pio_mask = ATA_PIO4,
168 .udma_mask = ATA_UDMA6,
169 .port_ops = &ahci_ops,
173 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
174 .flags = AHCI_FLAG_COMMON,
175 .pio_mask = ATA_PIO4,
176 .udma_mask = ATA_UDMA6,
177 .port_ops = &ahci_ops,
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_avn_ops,
185 [board_ahci_mcp65] = {
186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
188 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_ops,
193 [board_ahci_mcp77] = {
194 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
200 [board_ahci_mcp89] = {
201 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
202 .flags = AHCI_FLAG_COMMON,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_ops,
208 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
209 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
210 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
211 .pio_mask = ATA_PIO4,
212 .udma_mask = ATA_UDMA6,
213 .port_ops = &ahci_ops,
215 [board_ahci_sb600] = {
216 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
217 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
218 AHCI_HFLAG_32BIT_ONLY),
219 .flags = AHCI_FLAG_COMMON,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_pmp_retry_srst_ops,
224 [board_ahci_sb700] = { /* for SB700 and SB800 */
225 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
226 .flags = AHCI_FLAG_COMMON,
227 .pio_mask = ATA_PIO4,
228 .udma_mask = ATA_UDMA6,
229 .port_ops = &ahci_pmp_retry_srst_ops,
231 [board_ahci_vt8251] = {
232 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
233 .flags = AHCI_FLAG_COMMON,
234 .pio_mask = ATA_PIO4,
235 .udma_mask = ATA_UDMA6,
236 .port_ops = &ahci_vt8251_ops,
238 [board_ahci_pcs7] = {
239 .flags = AHCI_FLAG_COMMON,
240 .pio_mask = ATA_PIO4,
241 .udma_mask = ATA_UDMA6,
242 .port_ops = &ahci_ops,
246 static const struct pci_device_id ahci_pci_tbl[] = {
248 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
249 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
250 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
251 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
252 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
253 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
254 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
255 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
256 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
257 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
258 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
259 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
260 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
261 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
262 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
263 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
264 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
265 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
266 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
267 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
268 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
269 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
270 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
271 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
272 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
273 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
274 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
275 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
276 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
277 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
278 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
279 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
280 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
281 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
282 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
283 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
284 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
285 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
286 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
287 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
288 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
309 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
310 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
311 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
312 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
313 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
314 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
315 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
316 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
317 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
318 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
319 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
320 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
321 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
322 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
323 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
324 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
325 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
326 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
327 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
328 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
329 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
330 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
331 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
332 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
333 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
334 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
335 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
336 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
337 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
338 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
339 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
341 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
342 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
343 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
344 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
345 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
346 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
347 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
348 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
352 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
353 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
354 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
355 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
360 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
361 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
362 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
363 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
364 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
365 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
366 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
367 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
368 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
369 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
370 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
371 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
372 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
373 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
374 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
375 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
376 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
377 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
378 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
379 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
380 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
381 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
382 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
383 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
384 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
385 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
386 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
387 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
388 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
389 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
390 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
391 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
392 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
393 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
394 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
395 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
396 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
397 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
398 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
399 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
400 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
401 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
402 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
403 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
404 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
405 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
406 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
407 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
408 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
410 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
411 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
412 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
413 /* JMicron 362B and 362C have an AHCI function with IDE class code */
414 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
415 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
416 /* May need to update quirk_jmicron_async_suspend() for additions */
419 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
420 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
421 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
422 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
423 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
424 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
425 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
427 /* Amazon's Annapurna Labs support */
428 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
429 .class = PCI_CLASS_STORAGE_SATA_AHCI,
430 .class_mask = 0xffffff,
433 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
434 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
435 /* AMD is using RAID class only for ahci controllers */
436 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
437 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
440 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
441 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
444 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
445 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
446 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
447 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
448 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
449 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
450 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
453 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
454 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
455 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
456 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
457 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
465 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
466 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
467 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
468 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
469 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
470 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
471 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
472 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
473 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
474 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
475 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
476 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
477 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
478 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
479 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
481 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
482 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
483 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
484 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
485 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
486 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
487 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
488 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
489 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
490 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
491 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
492 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
493 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
494 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
495 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
496 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
497 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
498 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
499 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
500 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
501 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
502 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
503 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
504 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
505 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
506 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
507 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
508 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
509 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
510 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
511 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
512 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
513 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
514 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
515 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
516 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
517 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
518 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
519 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
520 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
521 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
522 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
523 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
524 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
525 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
526 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
527 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
530 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
531 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
532 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
534 /* ST Microelectronics */
535 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
538 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
539 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
540 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
541 .class = PCI_CLASS_STORAGE_SATA_AHCI,
542 .class_mask = 0xffffff,
543 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
544 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
545 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
546 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
547 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
548 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
549 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
550 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
551 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
552 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
553 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
554 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
555 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
556 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
557 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
558 .driver_data = board_ahci_yes_fbs },
559 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
560 .driver_data = board_ahci_yes_fbs },
561 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
562 .driver_data = board_ahci_yes_fbs },
563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
564 .driver_data = board_ahci_yes_fbs },
565 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
566 .driver_data = board_ahci_yes_fbs },
567 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
568 .driver_data = board_ahci_yes_fbs },
571 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
572 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
575 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
576 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
577 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
578 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
579 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
580 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
583 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
584 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
586 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
587 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
590 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
592 /* Generic, PCI class code for AHCI */
593 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
594 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
596 { } /* terminate list */
599 static const struct dev_pm_ops ahci_pci_pm_ops = {
600 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
601 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
602 ahci_pci_device_runtime_resume, NULL)
605 static struct pci_driver ahci_pci_driver = {
607 .id_table = ahci_pci_tbl,
608 .probe = ahci_init_one,
609 .remove = ahci_remove_one,
610 .shutdown = ahci_shutdown_one,
612 .pm = &ahci_pci_pm_ops,
616 #if IS_ENABLED(CONFIG_PATA_MARVELL)
617 static int marvell_enable;
619 static int marvell_enable = 1;
621 module_param(marvell_enable, int, 0644);
622 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
624 static int mobile_lpm_policy = -1;
625 module_param(mobile_lpm_policy, int, 0644);
626 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
628 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
629 struct ahci_host_priv *hpriv)
631 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
632 dev_info(&pdev->dev, "JMB361 has only one port\n");
633 hpriv->force_port_map = 1;
637 * Temporary Marvell 6145 hack: PATA port presence
638 * is asserted through the standard AHCI port
639 * presence register, as bit 4 (counting from 0)
641 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
642 if (pdev->device == 0x6121)
643 hpriv->mask_port_map = 0x3;
645 hpriv->mask_port_map = 0xf;
647 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
650 ahci_save_initial_config(&pdev->dev, hpriv);
653 static void ahci_pci_init_controller(struct ata_host *host)
655 struct ahci_host_priv *hpriv = host->private_data;
656 struct pci_dev *pdev = to_pci_dev(host->dev);
657 void __iomem *port_mmio;
661 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
662 if (pdev->device == 0x6121)
666 port_mmio = __ahci_port_base(host, mv);
668 writel(0, port_mmio + PORT_IRQ_MASK);
671 tmp = readl(port_mmio + PORT_IRQ_STAT);
672 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
674 writel(tmp, port_mmio + PORT_IRQ_STAT);
677 ahci_init_controller(host);
680 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
681 unsigned long deadline)
683 struct ata_port *ap = link->ap;
684 struct ahci_host_priv *hpriv = ap->host->private_data;
690 hpriv->stop_engine(ap);
692 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
693 deadline, &online, NULL);
695 hpriv->start_engine(ap);
697 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
699 /* vt8251 doesn't clear BSY on signature FIS reception,
700 * request follow-up softreset.
702 return online ? -EAGAIN : rc;
705 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
706 unsigned long deadline)
708 struct ata_port *ap = link->ap;
709 struct ahci_port_priv *pp = ap->private_data;
710 struct ahci_host_priv *hpriv = ap->host->private_data;
711 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
712 struct ata_taskfile tf;
716 hpriv->stop_engine(ap);
718 /* clear D2H reception area to properly wait for D2H FIS */
719 ata_tf_init(link->device, &tf);
720 tf.command = ATA_BUSY;
721 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
723 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
724 deadline, &online, NULL);
726 hpriv->start_engine(ap);
728 /* The pseudo configuration device on SIMG4726 attached to
729 * ASUS P5W-DH Deluxe doesn't send signature FIS after
730 * hardreset if no device is attached to the first downstream
731 * port && the pseudo device locks up on SRST w/ PMP==0. To
732 * work around this, wait for !BSY only briefly. If BSY isn't
733 * cleared, perform CLO and proceed to IDENTIFY (achieved by
734 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
736 * Wait for two seconds. Devices attached to downstream port
737 * which can't process the following IDENTIFY after this will
738 * have to be reset again. For most cases, this should
739 * suffice while making probing snappish enough.
742 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
745 ahci_kick_engine(ap);
751 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
753 * It has been observed with some SSDs that the timing of events in the
754 * link synchronization phase can leave the port in a state that can not
755 * be recovered by a SATA-hard-reset alone. The failing signature is
756 * SStatus.DET stuck at 1 ("Device presence detected but Phy
757 * communication not established"). It was found that unloading and
758 * reloading the driver when this problem occurs allows the drive
759 * connection to be recovered (DET advanced to 0x3). The critical
760 * component of reloading the driver is that the port state machines are
761 * reset by bouncing "port enable" in the AHCI PCS configuration
762 * register. So, reproduce that effect by bouncing a port whenever we
763 * see DET==1 after a reset.
765 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
766 unsigned long deadline)
768 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
769 struct ata_port *ap = link->ap;
770 struct ahci_port_priv *pp = ap->private_data;
771 struct ahci_host_priv *hpriv = ap->host->private_data;
772 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
773 unsigned long tmo = deadline - jiffies;
774 struct ata_taskfile tf;
780 hpriv->stop_engine(ap);
782 for (i = 0; i < 2; i++) {
785 int port = ap->port_no;
786 struct ata_host *host = ap->host;
787 struct pci_dev *pdev = to_pci_dev(host->dev);
789 /* clear D2H reception area to properly wait for D2H FIS */
790 ata_tf_init(link->device, &tf);
791 tf.command = ATA_BUSY;
792 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
794 rc = sata_link_hardreset(link, timing, deadline, &online,
797 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
798 (sstatus & 0xf) != 1)
801 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
804 pci_read_config_word(pdev, 0x92, &val);
806 pci_write_config_word(pdev, 0x92, val);
807 ata_msleep(ap, 1000);
809 pci_write_config_word(pdev, 0x92, val);
813 hpriv->start_engine(ap);
816 *class = ahci_dev_classify(ap);
818 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
824 static void ahci_pci_disable_interrupts(struct ata_host *host)
826 struct ahci_host_priv *hpriv = host->private_data;
827 void __iomem *mmio = hpriv->mmio;
830 /* AHCI spec rev1.1 section 8.3.3:
831 * Software must disable interrupts prior to requesting a
832 * transition of the HBA to D3 state.
834 ctl = readl(mmio + HOST_CTL);
836 writel(ctl, mmio + HOST_CTL);
837 readl(mmio + HOST_CTL); /* flush */
840 static int ahci_pci_device_runtime_suspend(struct device *dev)
842 struct pci_dev *pdev = to_pci_dev(dev);
843 struct ata_host *host = pci_get_drvdata(pdev);
845 ahci_pci_disable_interrupts(host);
849 static int ahci_pci_device_runtime_resume(struct device *dev)
851 struct pci_dev *pdev = to_pci_dev(dev);
852 struct ata_host *host = pci_get_drvdata(pdev);
855 rc = ahci_reset_controller(host);
858 ahci_pci_init_controller(host);
862 #ifdef CONFIG_PM_SLEEP
863 static int ahci_pci_device_suspend(struct device *dev)
865 struct pci_dev *pdev = to_pci_dev(dev);
866 struct ata_host *host = pci_get_drvdata(pdev);
867 struct ahci_host_priv *hpriv = host->private_data;
869 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
871 "BIOS update required for suspend/resume\n");
875 ahci_pci_disable_interrupts(host);
876 return ata_host_suspend(host, PMSG_SUSPEND);
879 static int ahci_pci_device_resume(struct device *dev)
881 struct pci_dev *pdev = to_pci_dev(dev);
882 struct ata_host *host = pci_get_drvdata(pdev);
885 /* Apple BIOS helpfully mangles the registers on resume */
886 if (is_mcp89_apple(pdev))
887 ahci_mcp89_apple_enable(pdev);
889 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
890 rc = ahci_reset_controller(host);
894 ahci_pci_init_controller(host);
897 ata_host_resume(host);
903 #endif /* CONFIG_PM */
905 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
907 const int dma_bits = using_dac ? 64 : 32;
911 * If the device fixup already set the dma_mask to some non-standard
912 * value, don't extend it here. This happens on STA2X11, for example.
914 * XXX: manipulating the DMA mask from platform code is completely
915 * bogus, platform code should use dev->bus_dma_limit instead..
917 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
920 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
922 dev_err(&pdev->dev, "DMA enable failed\n");
926 static void ahci_pci_print_info(struct ata_host *host)
928 struct pci_dev *pdev = to_pci_dev(host->dev);
932 pci_read_config_word(pdev, 0x0a, &cc);
933 if (cc == PCI_CLASS_STORAGE_IDE)
935 else if (cc == PCI_CLASS_STORAGE_SATA)
937 else if (cc == PCI_CLASS_STORAGE_RAID)
942 ahci_print_info(host, scc_s);
945 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
946 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
947 * support PMP and the 4726 either directly exports the device
948 * attached to the first downstream port or acts as a hardware storage
949 * controller and emulate a single ATA device (can be RAID 0/1 or some
950 * other configuration).
952 * When there's no device attached to the first downstream port of the
953 * 4726, "Config Disk" appears, which is a pseudo ATA device to
954 * configure the 4726. However, ATA emulation of the device is very
955 * lame. It doesn't send signature D2H Reg FIS after the initial
956 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
958 * The following function works around the problem by always using
959 * hardreset on the port and not depending on receiving signature FIS
960 * afterward. If signature FIS isn't received soon, ATA class is
961 * assumed without follow-up softreset.
963 static void ahci_p5wdh_workaround(struct ata_host *host)
965 static const struct dmi_system_id sysids[] = {
967 .ident = "P5W DH Deluxe",
969 DMI_MATCH(DMI_SYS_VENDOR,
970 "ASUSTEK COMPUTER INC"),
971 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
976 struct pci_dev *pdev = to_pci_dev(host->dev);
978 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
979 dmi_check_system(sysids)) {
980 struct ata_port *ap = host->ports[1];
983 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
985 ap->ops = &ahci_p5wdh_ops;
986 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
991 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
992 * booting in BIOS compatibility mode. We restore the registers but not ID.
994 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
998 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1000 pci_read_config_dword(pdev, 0xf8, &val);
1002 /* the following changes the device ID, but appears not to affect function */
1003 /* val = (val & ~0xf0000000) | 0x80000000; */
1004 pci_write_config_dword(pdev, 0xf8, val);
1006 pci_read_config_dword(pdev, 0x54c, &val);
1008 pci_write_config_dword(pdev, 0x54c, val);
1010 pci_read_config_dword(pdev, 0x4a4, &val);
1013 pci_write_config_dword(pdev, 0x4a4, val);
1015 pci_read_config_dword(pdev, 0x54c, &val);
1017 pci_write_config_dword(pdev, 0x54c, val);
1019 pci_read_config_dword(pdev, 0xf8, &val);
1020 val &= ~(1 << 0x1b);
1021 pci_write_config_dword(pdev, 0xf8, val);
1024 static bool is_mcp89_apple(struct pci_dev *pdev)
1026 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1027 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1028 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1029 pdev->subsystem_device == 0xcb89;
1032 /* only some SB600 ahci controllers can do 64bit DMA */
1033 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1035 static const struct dmi_system_id sysids[] = {
1037 * The oldest version known to be broken is 0901 and
1038 * working is 1501 which was released on 2007-10-26.
1039 * Enable 64bit DMA on 1501 and anything newer.
1041 * Please read bko#9412 for more info.
1044 .ident = "ASUS M2A-VM",
1046 DMI_MATCH(DMI_BOARD_VENDOR,
1047 "ASUSTeK Computer INC."),
1048 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1050 .driver_data = "20071026", /* yyyymmdd */
1053 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1054 * support 64bit DMA.
1056 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1057 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1058 * This spelling mistake was fixed in BIOS version 1.5, so
1059 * 1.5 and later have the Manufacturer as
1060 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1061 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1063 * BIOS versions earlier than 1.9 had a Board Product Name
1064 * DMI field of "MS-7376". This was changed to be
1065 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1066 * match on DMI_BOARD_NAME of "MS-7376".
1069 .ident = "MSI K9A2 Platinum",
1071 DMI_MATCH(DMI_BOARD_VENDOR,
1072 "MICRO-STAR INTER"),
1073 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1077 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1080 * This board also had the typo mentioned above in the
1081 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1082 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1085 .ident = "MSI K9AGM2",
1087 DMI_MATCH(DMI_BOARD_VENDOR,
1088 "MICRO-STAR INTER"),
1089 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1093 * All BIOS versions for the Asus M3A support 64bit DMA.
1094 * (all release versions from 0301 to 1206 were tested)
1097 .ident = "ASUS M3A",
1099 DMI_MATCH(DMI_BOARD_VENDOR,
1100 "ASUSTeK Computer INC."),
1101 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1106 const struct dmi_system_id *match;
1107 int year, month, date;
1110 match = dmi_first_match(sysids);
1111 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1115 if (!match->driver_data)
1118 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1119 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1121 if (strcmp(buf, match->driver_data) >= 0)
1124 dev_warn(&pdev->dev,
1125 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1131 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1135 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1137 static const struct dmi_system_id broken_systems[] = {
1139 .ident = "HP Compaq nx6310",
1141 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1142 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1144 /* PCI slot number of the controller */
1145 .driver_data = (void *)0x1FUL,
1148 .ident = "HP Compaq 6720s",
1150 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1151 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1153 /* PCI slot number of the controller */
1154 .driver_data = (void *)0x1FUL,
1157 { } /* terminate list */
1159 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1162 unsigned long slot = (unsigned long)dmi->driver_data;
1163 /* apply the quirk only to on-board controllers */
1164 return slot == PCI_SLOT(pdev->devfn);
1170 static bool ahci_broken_suspend(struct pci_dev *pdev)
1172 static const struct dmi_system_id sysids[] = {
1174 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1175 * to the harddisk doesn't become online after
1176 * resuming from STR. Warn and fail suspend.
1178 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1180 * Use dates instead of versions to match as HP is
1181 * apparently recycling both product and version
1184 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1189 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1190 DMI_MATCH(DMI_PRODUCT_NAME,
1191 "HP Pavilion dv4 Notebook PC"),
1193 .driver_data = "20090105", /* F.30 */
1198 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1199 DMI_MATCH(DMI_PRODUCT_NAME,
1200 "HP Pavilion dv5 Notebook PC"),
1202 .driver_data = "20090506", /* F.16 */
1207 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1208 DMI_MATCH(DMI_PRODUCT_NAME,
1209 "HP Pavilion dv6 Notebook PC"),
1211 .driver_data = "20090423", /* F.21 */
1216 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1217 DMI_MATCH(DMI_PRODUCT_NAME,
1218 "HP HDX18 Notebook PC"),
1220 .driver_data = "20090430", /* F.23 */
1223 * Acer eMachines G725 has the same problem. BIOS
1224 * V1.03 is known to be broken. V3.04 is known to
1225 * work. Between, there are V1.06, V2.06 and V3.03
1226 * that we don't have much idea about. For now,
1227 * blacklist anything older than V3.04.
1229 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1234 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1235 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1237 .driver_data = "20091216", /* V3.04 */
1239 { } /* terminate list */
1241 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1242 int year, month, date;
1245 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1248 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1249 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1251 return strcmp(buf, dmi->driver_data) < 0;
1254 static bool ahci_broken_lpm(struct pci_dev *pdev)
1256 static const struct dmi_system_id sysids[] = {
1257 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1260 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1261 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1263 .driver_data = "20180406", /* 1.31 */
1267 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1268 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1270 .driver_data = "20180420", /* 1.28 */
1274 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1275 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1277 .driver_data = "20180315", /* 1.33 */
1281 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1282 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1285 * Note date based on release notes, 2.35 has been
1286 * reported to be good, but I've been unable to get
1287 * a hold of the reporter to get the DMI BIOS date.
1290 .driver_data = "20180310", /* 2.35 */
1292 { } /* terminate list */
1294 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1295 int year, month, date;
1301 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1302 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1304 return strcmp(buf, dmi->driver_data) < 0;
1307 static bool ahci_broken_online(struct pci_dev *pdev)
1309 #define ENCODE_BUSDEVFN(bus, slot, func) \
1310 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1311 static const struct dmi_system_id sysids[] = {
1313 * There are several gigabyte boards which use
1314 * SIMG5723s configured as hardware RAID. Certain
1315 * 5723 firmware revisions shipped there keep the link
1316 * online but fail to answer properly to SRST or
1317 * IDENTIFY when no device is attached downstream
1318 * causing libata to retry quite a few times leading
1319 * to excessive detection delay.
1321 * As these firmwares respond to the second reset try
1322 * with invalid device signature, considering unknown
1323 * sig as offline works around the problem acceptably.
1326 .ident = "EP45-DQ6",
1328 DMI_MATCH(DMI_BOARD_VENDOR,
1329 "Gigabyte Technology Co., Ltd."),
1330 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1332 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1335 .ident = "EP45-DS5",
1337 DMI_MATCH(DMI_BOARD_VENDOR,
1338 "Gigabyte Technology Co., Ltd."),
1339 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1341 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1343 { } /* terminate list */
1345 #undef ENCODE_BUSDEVFN
1346 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1352 val = (unsigned long)dmi->driver_data;
1354 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1357 static bool ahci_broken_devslp(struct pci_dev *pdev)
1359 /* device with broken DEVSLP but still showing SDS capability */
1360 static const struct pci_device_id ids[] = {
1361 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1365 return pci_match_id(ids, pdev);
1368 #ifdef CONFIG_ATA_ACPI
1369 static void ahci_gtf_filter_workaround(struct ata_host *host)
1371 static const struct dmi_system_id sysids[] = {
1373 * Aspire 3810T issues a bunch of SATA enable commands
1374 * via _GTF including an invalid one and one which is
1375 * rejected by the device. Among the successful ones
1376 * is FPDMA non-zero offset enable which when enabled
1377 * only on the drive side leads to NCQ command
1378 * failures. Filter it out.
1381 .ident = "Aspire 3810T",
1383 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1384 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1386 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1390 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1391 unsigned int filter;
1397 filter = (unsigned long)dmi->driver_data;
1398 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1399 filter, dmi->ident);
1401 for (i = 0; i < host->n_ports; i++) {
1402 struct ata_port *ap = host->ports[i];
1403 struct ata_link *link;
1404 struct ata_device *dev;
1406 ata_for_each_link(link, ap, EDGE)
1407 ata_for_each_dev(dev, link, ALL)
1408 dev->gtf_filter |= filter;
1412 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1417 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1418 * as DUMMY, or detected but eventually get a "link down" and never get up
1419 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1420 * port_map may hold a value of 0x00.
1422 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1423 * and can significantly reduce the occurrence of the problem.
1425 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1427 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1428 struct pci_dev *pdev)
1430 static const struct dmi_system_id sysids[] = {
1432 .ident = "Acer Switch Alpha 12",
1434 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1435 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1441 if (dmi_check_system(sysids)) {
1442 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1443 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1444 hpriv->port_map = 0x7;
1445 hpriv->cap = 0xC734FF02;
1452 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1453 * Workaround is to make sure all pending IRQs are served before leaving
1456 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1458 struct ata_host *host = dev_instance;
1459 struct ahci_host_priv *hpriv;
1460 unsigned int rc = 0;
1462 u32 irq_stat, irq_masked;
1463 unsigned int handled = 1;
1466 hpriv = host->private_data;
1468 irq_stat = readl(mmio + HOST_IRQ_STAT);
1473 irq_masked = irq_stat & hpriv->port_map;
1474 spin_lock(&host->lock);
1475 rc = ahci_handle_port_intr(host, irq_masked);
1478 writel(irq_stat, mmio + HOST_IRQ_STAT);
1479 irq_stat = readl(mmio + HOST_IRQ_STAT);
1480 spin_unlock(&host->lock);
1484 return IRQ_RETVAL(handled);
1488 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1489 struct ahci_host_priv *hpriv)
1495 * Check if this device might have remapped nvme devices.
1497 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1498 pci_resource_len(pdev, bar) < SZ_512K ||
1499 bar != AHCI_PCI_BAR_STANDARD ||
1500 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1503 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1504 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1505 if ((cap & (1 << i)) == 0)
1507 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1508 != PCI_CLASS_STORAGE_EXPRESS)
1511 /* We've found a remapped device */
1518 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1519 dev_warn(&pdev->dev,
1520 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1523 * Don't rely on the msi-x capability in the remap case,
1524 * share the legacy interrupt across ahci and remapped devices.
1526 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1529 static int ahci_get_irq_vector(struct ata_host *host, int port)
1531 return pci_irq_vector(to_pci_dev(host->dev), port);
1534 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1535 struct ahci_host_priv *hpriv)
1539 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1543 * If number of MSIs is less than number of ports then Sharing Last
1544 * Message mode could be enforced. In this case assume that advantage
1545 * of multipe MSIs is negated and use single MSI mode instead.
1548 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1549 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1551 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1552 hpriv->get_irq_vector = ahci_get_irq_vector;
1553 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1558 * Fallback to single MSI mode if the controller
1559 * enforced MRSM mode.
1562 "ahci: MRSM is on, fallback to single MSI\n");
1563 pci_free_irq_vectors(pdev);
1568 * If the host is not capable of supporting per-port vectors, fall
1569 * back to single MSI before finally attempting single MSI-X.
1571 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1574 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1577 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1578 struct ahci_host_priv *hpriv)
1580 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1583 /* Ignore processing for non mobile platforms */
1584 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1587 /* user modified policy via module param */
1588 if (mobile_lpm_policy != -1) {
1589 policy = mobile_lpm_policy;
1594 if (policy > ATA_LPM_MED_POWER &&
1595 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1596 if (hpriv->cap & HOST_CAP_PART)
1597 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1598 else if (hpriv->cap & HOST_CAP_SSC)
1599 policy = ATA_LPM_MIN_POWER;
1604 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1605 ap->target_lpm_policy = policy;
1608 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1610 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1614 * Only apply the 6-port PCS quirk for known legacy platforms.
1616 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1619 /* Skip applying the quirk on Denverton and beyond */
1620 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1624 * port_map is determined from PORTS_IMPL PCI register which is
1625 * implemented as write or write-once register. If the register
1626 * isn't programmed, ahci automatically generates it from number
1627 * of ports, which is good enough for PCS programming. It is
1628 * otherwise expected that platform firmware enables the ports
1629 * before the OS boots.
1631 pci_read_config_word(pdev, PCS_6, &tmp16);
1632 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1633 tmp16 |= hpriv->port_map;
1634 pci_write_config_word(pdev, PCS_6, tmp16);
1638 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1640 unsigned int board_id = ent->driver_data;
1641 struct ata_port_info pi = ahci_port_info[board_id];
1642 const struct ata_port_info *ppi[] = { &pi, NULL };
1643 struct device *dev = &pdev->dev;
1644 struct ahci_host_priv *hpriv;
1645 struct ata_host *host;
1647 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1651 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1653 ata_print_version_once(&pdev->dev, DRV_VERSION);
1655 /* The AHCI driver can only drive the SATA ports, the PATA driver
1656 can drive them all so if both drivers are selected make sure
1657 AHCI stays out of the way */
1658 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1661 /* Apple BIOS on MCP89 prevents us using AHCI */
1662 if (is_mcp89_apple(pdev))
1663 ahci_mcp89_apple_enable(pdev);
1665 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1666 * At the moment, we can only use the AHCI mode. Let the users know
1667 * that for SAS drives they're out of luck.
1669 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1670 dev_info(&pdev->dev,
1671 "PDC42819 can only drive SATA devices with this driver\n");
1673 /* Some devices use non-standard BARs */
1674 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1675 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1676 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1677 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1678 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1679 if (pdev->device == 0xa01c)
1680 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1681 if (pdev->device == 0xa084)
1682 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1685 /* acquire resources */
1686 rc = pcim_enable_device(pdev);
1690 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1691 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1694 /* ICH6s share the same PCI ID for both piix and ahci
1695 * modes. Enabling ahci mode while MAP indicates
1696 * combined mode is a bad idea. Yield to ata_piix.
1698 pci_read_config_byte(pdev, ICH_MAP, &map);
1700 dev_info(&pdev->dev,
1701 "controller is in combined mode, can't enable AHCI mode\n");
1706 /* AHCI controllers often implement SFF compatible interface.
1707 * Grab all PCI BARs just in case.
1709 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1711 pcim_pin_device(pdev);
1715 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1718 hpriv->flags |= (unsigned long)pi.private_data;
1720 /* MCP65 revision A1 and A2 can't do MSI */
1721 if (board_id == board_ahci_mcp65 &&
1722 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1723 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1725 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1726 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1727 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1729 /* only some SB600s can do 64bit DMA */
1730 if (ahci_sb600_enable_64bit(pdev))
1731 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1733 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1735 /* detect remapped nvme devices */
1736 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1738 /* must set flag prior to save config in order to take effect */
1739 if (ahci_broken_devslp(pdev))
1740 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1743 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1744 hpriv->irq_handler = ahci_thunderx_irq_handler;
1747 /* save initial config */
1748 ahci_pci_save_initial_config(pdev, hpriv);
1751 * If platform firmware failed to enable ports, try to enable
1754 ahci_intel_pcs_quirk(pdev, hpriv);
1757 if (hpriv->cap & HOST_CAP_NCQ) {
1758 pi.flags |= ATA_FLAG_NCQ;
1760 * Auto-activate optimization is supposed to be
1761 * supported on all AHCI controllers indicating NCQ
1762 * capability, but it seems to be broken on some
1763 * chipsets including NVIDIAs.
1765 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1766 pi.flags |= ATA_FLAG_FPDMA_AA;
1769 * All AHCI controllers should be forward-compatible
1770 * with the new auxiliary field. This code should be
1771 * conditionalized if any buggy AHCI controllers are
1774 pi.flags |= ATA_FLAG_FPDMA_AUX;
1777 if (hpriv->cap & HOST_CAP_PMP)
1778 pi.flags |= ATA_FLAG_PMP;
1780 ahci_set_em_messages(hpriv, &pi);
1782 if (ahci_broken_system_poweroff(pdev)) {
1783 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1784 dev_info(&pdev->dev,
1785 "quirky BIOS, skipping spindown on poweroff\n");
1788 if (ahci_broken_lpm(pdev)) {
1789 pi.flags |= ATA_FLAG_NO_LPM;
1790 dev_warn(&pdev->dev,
1791 "BIOS update required for Link Power Management support\n");
1794 if (ahci_broken_suspend(pdev)) {
1795 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1796 dev_warn(&pdev->dev,
1797 "BIOS update required for suspend/resume\n");
1800 if (ahci_broken_online(pdev)) {
1801 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1802 dev_info(&pdev->dev,
1803 "online status unreliable, applying workaround\n");
1807 /* Acer SA5-271 workaround modifies private_data */
1808 acer_sa5_271_workaround(hpriv, pdev);
1810 /* CAP.NP sometimes indicate the index of the last enabled
1811 * port, at other times, that of the last possible port, so
1812 * determining the maximum port number requires looking at
1813 * both CAP.NP and port_map.
1815 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1817 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1820 host->private_data = hpriv;
1822 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1823 /* legacy intx interrupts */
1826 hpriv->irq = pci_irq_vector(pdev, 0);
1828 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1829 host->flags |= ATA_HOST_PARALLEL_SCAN;
1831 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1833 if (pi.flags & ATA_FLAG_EM)
1834 ahci_reset_em(host);
1836 for (i = 0; i < host->n_ports; i++) {
1837 struct ata_port *ap = host->ports[i];
1839 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1840 ata_port_pbar_desc(ap, ahci_pci_bar,
1841 0x100 + ap->port_no * 0x80, "port");
1843 /* set enclosure management message type */
1844 if (ap->flags & ATA_FLAG_EM)
1845 ap->em_message_type = hpriv->em_msg_type;
1847 ahci_update_initial_lpm_policy(ap, hpriv);
1849 /* disabled/not-implemented port */
1850 if (!(hpriv->port_map & (1 << i)))
1851 ap->ops = &ata_dummy_port_ops;
1854 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1855 ahci_p5wdh_workaround(host);
1857 /* apply gtf filter quirk */
1858 ahci_gtf_filter_workaround(host);
1860 /* initialize adapter */
1861 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1865 rc = ahci_reset_controller(host);
1869 ahci_pci_init_controller(host);
1870 ahci_pci_print_info(host);
1872 pci_set_master(pdev);
1874 rc = ahci_host_activate(host, &ahci_sht);
1878 pm_runtime_put_noidle(&pdev->dev);
1882 static void ahci_shutdown_one(struct pci_dev *pdev)
1884 ata_pci_shutdown_one(pdev);
1887 static void ahci_remove_one(struct pci_dev *pdev)
1889 pm_runtime_get_noresume(&pdev->dev);
1890 ata_pci_remove_one(pdev);
1893 module_pci_driver(ahci_pci_driver);
1895 MODULE_AUTHOR("Jeff Garzik");
1896 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1897 MODULE_LICENSE("GPL");
1898 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1899 MODULE_VERSION(DRV_VERSION);