2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include <linux/ahci-remap.h>
50 #include <linux/io-64-nonatomic-lo-hi.h>
53 #define DRV_NAME "ahci"
54 #define DRV_VERSION "3.0"
57 AHCI_PCI_BAR_STA2X11 = 0,
58 AHCI_PCI_BAR_CAVIUM = 0,
59 AHCI_PCI_BAR_ENMOTUS = 2,
60 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
61 AHCI_PCI_BAR_STANDARD = 5,
65 /* board IDs by feature in alphabetical order */
73 /* board IDs for specific chipsets in alphabetical order */
80 board_ahci_sb700, /* for SB700 and SB800 */
84 board_ahci_mcp_linux = board_ahci_mcp65,
85 board_ahci_mcp67 = board_ahci_mcp65,
86 board_ahci_mcp73 = board_ahci_mcp65,
87 board_ahci_mcp79 = board_ahci_mcp77,
90 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
91 static void ahci_remove_one(struct pci_dev *dev);
92 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
94 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
96 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
97 static bool is_mcp89_apple(struct pci_dev *pdev);
98 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
99 unsigned long deadline);
101 static int ahci_pci_device_runtime_suspend(struct device *dev);
102 static int ahci_pci_device_runtime_resume(struct device *dev);
103 #ifdef CONFIG_PM_SLEEP
104 static int ahci_pci_device_suspend(struct device *dev);
105 static int ahci_pci_device_resume(struct device *dev);
107 #endif /* CONFIG_PM */
109 static struct scsi_host_template ahci_sht = {
113 static struct ata_port_operations ahci_vt8251_ops = {
114 .inherits = &ahci_ops,
115 .hardreset = ahci_vt8251_hardreset,
118 static struct ata_port_operations ahci_p5wdh_ops = {
119 .inherits = &ahci_ops,
120 .hardreset = ahci_p5wdh_hardreset,
123 static struct ata_port_operations ahci_avn_ops = {
124 .inherits = &ahci_ops,
125 .hardreset = ahci_avn_hardreset,
128 static const struct ata_port_info ahci_port_info[] = {
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
136 [board_ahci_ign_iferr] = {
137 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
138 .flags = AHCI_FLAG_COMMON,
139 .pio_mask = ATA_PIO4,
140 .udma_mask = ATA_UDMA6,
141 .port_ops = &ahci_ops,
143 [board_ahci_nomsi] = {
144 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
150 [board_ahci_noncq] = {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
152 .flags = AHCI_FLAG_COMMON,
153 .pio_mask = ATA_PIO4,
154 .udma_mask = ATA_UDMA6,
155 .port_ops = &ahci_ops,
157 [board_ahci_nosntf] = {
158 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
159 .flags = AHCI_FLAG_COMMON,
160 .pio_mask = ATA_PIO4,
161 .udma_mask = ATA_UDMA6,
162 .port_ops = &ahci_ops,
164 [board_ahci_yes_fbs] = {
165 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
166 .flags = AHCI_FLAG_COMMON,
167 .pio_mask = ATA_PIO4,
168 .udma_mask = ATA_UDMA6,
169 .port_ops = &ahci_ops,
173 .flags = AHCI_FLAG_COMMON,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_avn_ops,
178 [board_ahci_mcp65] = {
179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
181 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_ops,
186 [board_ahci_mcp77] = {
187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_ops,
193 [board_ahci_mcp89] = {
194 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
201 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
202 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
203 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
208 [board_ahci_sb600] = {
209 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
210 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
211 AHCI_HFLAG_32BIT_ONLY),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_pmp_retry_srst_ops,
217 [board_ahci_sb700] = { /* for SB700 and SB800 */
218 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
219 .flags = AHCI_FLAG_COMMON,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_pmp_retry_srst_ops,
224 [board_ahci_vt8251] = {
225 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
226 .flags = AHCI_FLAG_COMMON,
227 .pio_mask = ATA_PIO4,
228 .udma_mask = ATA_UDMA6,
229 .port_ops = &ahci_vt8251_ops,
233 static const struct pci_device_id ahci_pci_tbl[] = {
235 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
236 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
237 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
238 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
239 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
240 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
241 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
242 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
243 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
244 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
245 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
246 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
247 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
248 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
249 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
250 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
251 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
252 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
254 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
255 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
256 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
257 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
259 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
260 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
261 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
262 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
263 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
264 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
265 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
266 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
267 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
268 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
269 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
270 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
271 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
272 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
273 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
274 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
275 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
296 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
297 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
298 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
299 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
300 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
301 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
302 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
303 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
304 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
305 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
306 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
307 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
308 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
309 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
310 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
311 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
312 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
313 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
314 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
315 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
316 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
317 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
318 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
319 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
320 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
321 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
322 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
323 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
324 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
325 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
328 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
329 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
330 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
331 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
338 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
339 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
344 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
345 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
346 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
347 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
348 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
349 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
350 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
351 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
352 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
353 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
354 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
355 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
356 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
357 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
359 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
360 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
361 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
362 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
363 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
364 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
365 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
366 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
367 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
368 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
369 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
370 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
371 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
372 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
373 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
374 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
375 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
376 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
377 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
378 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
379 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
380 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
381 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
382 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
384 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
385 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
386 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
387 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
388 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
390 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
391 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
392 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
393 /* JMicron 362B and 362C have an AHCI function with IDE class code */
394 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
395 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
396 /* May need to update quirk_jmicron_async_suspend() for additions */
399 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
400 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
401 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
402 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
403 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
404 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
405 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
408 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
409 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
410 /* AMD is using RAID class only for ahci controllers */
411 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
412 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
415 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
416 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
419 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
420 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
421 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
422 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
423 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
424 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
427 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
440 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
441 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
442 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
455 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
480 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
482 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
483 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
491 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
492 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
493 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
494 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
495 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
496 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
502 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
505 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
506 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
507 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
509 /* ST Microelectronics */
510 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
513 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
514 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
515 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
516 .class = PCI_CLASS_STORAGE_SATA_AHCI,
517 .class_mask = 0xffffff,
518 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
519 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
520 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
521 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
522 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
523 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
524 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
525 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
526 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
527 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
528 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
529 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
530 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
531 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
532 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
533 .driver_data = board_ahci_yes_fbs },
534 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
535 .driver_data = board_ahci_yes_fbs },
536 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
537 .driver_data = board_ahci_yes_fbs },
538 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
539 .driver_data = board_ahci_yes_fbs },
540 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
541 .driver_data = board_ahci_yes_fbs },
544 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
545 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
548 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
549 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
550 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
551 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
552 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
553 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
556 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
557 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
559 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
560 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
563 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
565 /* Generic, PCI class code for AHCI */
566 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
567 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
569 { } /* terminate list */
572 static const struct dev_pm_ops ahci_pci_pm_ops = {
573 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
574 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
575 ahci_pci_device_runtime_resume, NULL)
578 static struct pci_driver ahci_pci_driver = {
580 .id_table = ahci_pci_tbl,
581 .probe = ahci_init_one,
582 .remove = ahci_remove_one,
584 .pm = &ahci_pci_pm_ops,
588 #if IS_ENABLED(CONFIG_PATA_MARVELL)
589 static int marvell_enable;
591 static int marvell_enable = 1;
593 module_param(marvell_enable, int, 0644);
594 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
597 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
598 struct ahci_host_priv *hpriv)
600 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
601 dev_info(&pdev->dev, "JMB361 has only one port\n");
602 hpriv->force_port_map = 1;
606 * Temporary Marvell 6145 hack: PATA port presence
607 * is asserted through the standard AHCI port
608 * presence register, as bit 4 (counting from 0)
610 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
611 if (pdev->device == 0x6121)
612 hpriv->mask_port_map = 0x3;
614 hpriv->mask_port_map = 0xf;
616 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
619 ahci_save_initial_config(&pdev->dev, hpriv);
622 static int ahci_pci_reset_controller(struct ata_host *host)
624 struct pci_dev *pdev = to_pci_dev(host->dev);
627 rc = ahci_reset_controller(host);
631 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
632 struct ahci_host_priv *hpriv = host->private_data;
636 pci_read_config_word(pdev, 0x92, &tmp16);
637 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
638 tmp16 |= hpriv->port_map;
639 pci_write_config_word(pdev, 0x92, tmp16);
646 static void ahci_pci_init_controller(struct ata_host *host)
648 struct ahci_host_priv *hpriv = host->private_data;
649 struct pci_dev *pdev = to_pci_dev(host->dev);
650 void __iomem *port_mmio;
654 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
655 if (pdev->device == 0x6121)
659 port_mmio = __ahci_port_base(host, mv);
661 writel(0, port_mmio + PORT_IRQ_MASK);
664 tmp = readl(port_mmio + PORT_IRQ_STAT);
665 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
667 writel(tmp, port_mmio + PORT_IRQ_STAT);
670 ahci_init_controller(host);
673 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
674 unsigned long deadline)
676 struct ata_port *ap = link->ap;
677 struct ahci_host_priv *hpriv = ap->host->private_data;
683 ahci_stop_engine(ap);
685 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
686 deadline, &online, NULL);
688 hpriv->start_engine(ap);
690 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
692 /* vt8251 doesn't clear BSY on signature FIS reception,
693 * request follow-up softreset.
695 return online ? -EAGAIN : rc;
698 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
699 unsigned long deadline)
701 struct ata_port *ap = link->ap;
702 struct ahci_port_priv *pp = ap->private_data;
703 struct ahci_host_priv *hpriv = ap->host->private_data;
704 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
705 struct ata_taskfile tf;
709 ahci_stop_engine(ap);
711 /* clear D2H reception area to properly wait for D2H FIS */
712 ata_tf_init(link->device, &tf);
713 tf.command = ATA_BUSY;
714 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
716 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
717 deadline, &online, NULL);
719 hpriv->start_engine(ap);
721 /* The pseudo configuration device on SIMG4726 attached to
722 * ASUS P5W-DH Deluxe doesn't send signature FIS after
723 * hardreset if no device is attached to the first downstream
724 * port && the pseudo device locks up on SRST w/ PMP==0. To
725 * work around this, wait for !BSY only briefly. If BSY isn't
726 * cleared, perform CLO and proceed to IDENTIFY (achieved by
727 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
729 * Wait for two seconds. Devices attached to downstream port
730 * which can't process the following IDENTIFY after this will
731 * have to be reset again. For most cases, this should
732 * suffice while making probing snappish enough.
735 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
738 ahci_kick_engine(ap);
744 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
746 * It has been observed with some SSDs that the timing of events in the
747 * link synchronization phase can leave the port in a state that can not
748 * be recovered by a SATA-hard-reset alone. The failing signature is
749 * SStatus.DET stuck at 1 ("Device presence detected but Phy
750 * communication not established"). It was found that unloading and
751 * reloading the driver when this problem occurs allows the drive
752 * connection to be recovered (DET advanced to 0x3). The critical
753 * component of reloading the driver is that the port state machines are
754 * reset by bouncing "port enable" in the AHCI PCS configuration
755 * register. So, reproduce that effect by bouncing a port whenever we
756 * see DET==1 after a reset.
758 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
759 unsigned long deadline)
761 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
762 struct ata_port *ap = link->ap;
763 struct ahci_port_priv *pp = ap->private_data;
764 struct ahci_host_priv *hpriv = ap->host->private_data;
765 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
766 unsigned long tmo = deadline - jiffies;
767 struct ata_taskfile tf;
773 ahci_stop_engine(ap);
775 for (i = 0; i < 2; i++) {
778 int port = ap->port_no;
779 struct ata_host *host = ap->host;
780 struct pci_dev *pdev = to_pci_dev(host->dev);
782 /* clear D2H reception area to properly wait for D2H FIS */
783 ata_tf_init(link->device, &tf);
784 tf.command = ATA_BUSY;
785 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
787 rc = sata_link_hardreset(link, timing, deadline, &online,
790 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
791 (sstatus & 0xf) != 1)
794 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
797 pci_read_config_word(pdev, 0x92, &val);
799 pci_write_config_word(pdev, 0x92, val);
800 ata_msleep(ap, 1000);
802 pci_write_config_word(pdev, 0x92, val);
806 hpriv->start_engine(ap);
809 *class = ahci_dev_classify(ap);
811 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
817 static void ahci_pci_disable_interrupts(struct ata_host *host)
819 struct ahci_host_priv *hpriv = host->private_data;
820 void __iomem *mmio = hpriv->mmio;
823 /* AHCI spec rev1.1 section 8.3.3:
824 * Software must disable interrupts prior to requesting a
825 * transition of the HBA to D3 state.
827 ctl = readl(mmio + HOST_CTL);
829 writel(ctl, mmio + HOST_CTL);
830 readl(mmio + HOST_CTL); /* flush */
833 static int ahci_pci_device_runtime_suspend(struct device *dev)
835 struct pci_dev *pdev = to_pci_dev(dev);
836 struct ata_host *host = pci_get_drvdata(pdev);
838 ahci_pci_disable_interrupts(host);
842 static int ahci_pci_device_runtime_resume(struct device *dev)
844 struct pci_dev *pdev = to_pci_dev(dev);
845 struct ata_host *host = pci_get_drvdata(pdev);
848 rc = ahci_pci_reset_controller(host);
851 ahci_pci_init_controller(host);
855 #ifdef CONFIG_PM_SLEEP
856 static int ahci_pci_device_suspend(struct device *dev)
858 struct pci_dev *pdev = to_pci_dev(dev);
859 struct ata_host *host = pci_get_drvdata(pdev);
860 struct ahci_host_priv *hpriv = host->private_data;
862 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
864 "BIOS update required for suspend/resume\n");
868 ahci_pci_disable_interrupts(host);
869 return ata_host_suspend(host, PMSG_SUSPEND);
872 static int ahci_pci_device_resume(struct device *dev)
874 struct pci_dev *pdev = to_pci_dev(dev);
875 struct ata_host *host = pci_get_drvdata(pdev);
878 /* Apple BIOS helpfully mangles the registers on resume */
879 if (is_mcp89_apple(pdev))
880 ahci_mcp89_apple_enable(pdev);
882 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
883 rc = ahci_pci_reset_controller(host);
887 ahci_pci_init_controller(host);
890 ata_host_resume(host);
896 #endif /* CONFIG_PM */
898 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
903 * If the device fixup already set the dma_mask to some non-standard
904 * value, don't extend it here. This happens on STA2X11, for example.
906 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
910 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
911 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
913 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
916 "64-bit DMA enable failed\n");
921 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
923 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
926 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
929 "32-bit consistent DMA enable failed\n");
936 static void ahci_pci_print_info(struct ata_host *host)
938 struct pci_dev *pdev = to_pci_dev(host->dev);
942 pci_read_config_word(pdev, 0x0a, &cc);
943 if (cc == PCI_CLASS_STORAGE_IDE)
945 else if (cc == PCI_CLASS_STORAGE_SATA)
947 else if (cc == PCI_CLASS_STORAGE_RAID)
952 ahci_print_info(host, scc_s);
955 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
956 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
957 * support PMP and the 4726 either directly exports the device
958 * attached to the first downstream port or acts as a hardware storage
959 * controller and emulate a single ATA device (can be RAID 0/1 or some
960 * other configuration).
962 * When there's no device attached to the first downstream port of the
963 * 4726, "Config Disk" appears, which is a pseudo ATA device to
964 * configure the 4726. However, ATA emulation of the device is very
965 * lame. It doesn't send signature D2H Reg FIS after the initial
966 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
968 * The following function works around the problem by always using
969 * hardreset on the port and not depending on receiving signature FIS
970 * afterward. If signature FIS isn't received soon, ATA class is
971 * assumed without follow-up softreset.
973 static void ahci_p5wdh_workaround(struct ata_host *host)
975 static const struct dmi_system_id sysids[] = {
977 .ident = "P5W DH Deluxe",
979 DMI_MATCH(DMI_SYS_VENDOR,
980 "ASUSTEK COMPUTER INC"),
981 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
986 struct pci_dev *pdev = to_pci_dev(host->dev);
988 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
989 dmi_check_system(sysids)) {
990 struct ata_port *ap = host->ports[1];
993 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
995 ap->ops = &ahci_p5wdh_ops;
996 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1001 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1002 * booting in BIOS compatibility mode. We restore the registers but not ID.
1004 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1008 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1010 pci_read_config_dword(pdev, 0xf8, &val);
1012 /* the following changes the device ID, but appears not to affect function */
1013 /* val = (val & ~0xf0000000) | 0x80000000; */
1014 pci_write_config_dword(pdev, 0xf8, val);
1016 pci_read_config_dword(pdev, 0x54c, &val);
1018 pci_write_config_dword(pdev, 0x54c, val);
1020 pci_read_config_dword(pdev, 0x4a4, &val);
1023 pci_write_config_dword(pdev, 0x4a4, val);
1025 pci_read_config_dword(pdev, 0x54c, &val);
1027 pci_write_config_dword(pdev, 0x54c, val);
1029 pci_read_config_dword(pdev, 0xf8, &val);
1030 val &= ~(1 << 0x1b);
1031 pci_write_config_dword(pdev, 0xf8, val);
1034 static bool is_mcp89_apple(struct pci_dev *pdev)
1036 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1037 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1038 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1039 pdev->subsystem_device == 0xcb89;
1042 /* only some SB600 ahci controllers can do 64bit DMA */
1043 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1045 static const struct dmi_system_id sysids[] = {
1047 * The oldest version known to be broken is 0901 and
1048 * working is 1501 which was released on 2007-10-26.
1049 * Enable 64bit DMA on 1501 and anything newer.
1051 * Please read bko#9412 for more info.
1054 .ident = "ASUS M2A-VM",
1056 DMI_MATCH(DMI_BOARD_VENDOR,
1057 "ASUSTeK Computer INC."),
1058 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1060 .driver_data = "20071026", /* yyyymmdd */
1063 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1064 * support 64bit DMA.
1066 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1067 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1068 * This spelling mistake was fixed in BIOS version 1.5, so
1069 * 1.5 and later have the Manufacturer as
1070 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1071 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1073 * BIOS versions earlier than 1.9 had a Board Product Name
1074 * DMI field of "MS-7376". This was changed to be
1075 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1076 * match on DMI_BOARD_NAME of "MS-7376".
1079 .ident = "MSI K9A2 Platinum",
1081 DMI_MATCH(DMI_BOARD_VENDOR,
1082 "MICRO-STAR INTER"),
1083 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1087 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1090 * This board also had the typo mentioned above in the
1091 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1092 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1095 .ident = "MSI K9AGM2",
1097 DMI_MATCH(DMI_BOARD_VENDOR,
1098 "MICRO-STAR INTER"),
1099 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1103 * All BIOS versions for the Asus M3A support 64bit DMA.
1104 * (all release versions from 0301 to 1206 were tested)
1107 .ident = "ASUS M3A",
1109 DMI_MATCH(DMI_BOARD_VENDOR,
1110 "ASUSTeK Computer INC."),
1111 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1116 const struct dmi_system_id *match;
1117 int year, month, date;
1120 match = dmi_first_match(sysids);
1121 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1125 if (!match->driver_data)
1128 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1129 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1131 if (strcmp(buf, match->driver_data) >= 0)
1134 dev_warn(&pdev->dev,
1135 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1141 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1145 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1147 static const struct dmi_system_id broken_systems[] = {
1149 .ident = "HP Compaq nx6310",
1151 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1152 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1154 /* PCI slot number of the controller */
1155 .driver_data = (void *)0x1FUL,
1158 .ident = "HP Compaq 6720s",
1160 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1161 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1163 /* PCI slot number of the controller */
1164 .driver_data = (void *)0x1FUL,
1167 { } /* terminate list */
1169 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1172 unsigned long slot = (unsigned long)dmi->driver_data;
1173 /* apply the quirk only to on-board controllers */
1174 return slot == PCI_SLOT(pdev->devfn);
1180 static bool ahci_broken_suspend(struct pci_dev *pdev)
1182 static const struct dmi_system_id sysids[] = {
1184 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1185 * to the harddisk doesn't become online after
1186 * resuming from STR. Warn and fail suspend.
1188 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1190 * Use dates instead of versions to match as HP is
1191 * apparently recycling both product and version
1194 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1199 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1200 DMI_MATCH(DMI_PRODUCT_NAME,
1201 "HP Pavilion dv4 Notebook PC"),
1203 .driver_data = "20090105", /* F.30 */
1208 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1209 DMI_MATCH(DMI_PRODUCT_NAME,
1210 "HP Pavilion dv5 Notebook PC"),
1212 .driver_data = "20090506", /* F.16 */
1217 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1218 DMI_MATCH(DMI_PRODUCT_NAME,
1219 "HP Pavilion dv6 Notebook PC"),
1221 .driver_data = "20090423", /* F.21 */
1226 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1227 DMI_MATCH(DMI_PRODUCT_NAME,
1228 "HP HDX18 Notebook PC"),
1230 .driver_data = "20090430", /* F.23 */
1233 * Acer eMachines G725 has the same problem. BIOS
1234 * V1.03 is known to be broken. V3.04 is known to
1235 * work. Between, there are V1.06, V2.06 and V3.03
1236 * that we don't have much idea about. For now,
1237 * blacklist anything older than V3.04.
1239 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1244 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1245 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1247 .driver_data = "20091216", /* V3.04 */
1249 { } /* terminate list */
1251 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1252 int year, month, date;
1255 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1258 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1259 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1261 return strcmp(buf, dmi->driver_data) < 0;
1264 static bool ahci_broken_online(struct pci_dev *pdev)
1266 #define ENCODE_BUSDEVFN(bus, slot, func) \
1267 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1268 static const struct dmi_system_id sysids[] = {
1270 * There are several gigabyte boards which use
1271 * SIMG5723s configured as hardware RAID. Certain
1272 * 5723 firmware revisions shipped there keep the link
1273 * online but fail to answer properly to SRST or
1274 * IDENTIFY when no device is attached downstream
1275 * causing libata to retry quite a few times leading
1276 * to excessive detection delay.
1278 * As these firmwares respond to the second reset try
1279 * with invalid device signature, considering unknown
1280 * sig as offline works around the problem acceptably.
1283 .ident = "EP45-DQ6",
1285 DMI_MATCH(DMI_BOARD_VENDOR,
1286 "Gigabyte Technology Co., Ltd."),
1287 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1289 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1292 .ident = "EP45-DS5",
1294 DMI_MATCH(DMI_BOARD_VENDOR,
1295 "Gigabyte Technology Co., Ltd."),
1296 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1298 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1300 { } /* terminate list */
1302 #undef ENCODE_BUSDEVFN
1303 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1309 val = (unsigned long)dmi->driver_data;
1311 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1314 static bool ahci_broken_devslp(struct pci_dev *pdev)
1316 /* device with broken DEVSLP but still showing SDS capability */
1317 static const struct pci_device_id ids[] = {
1318 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1322 return pci_match_id(ids, pdev);
1325 #ifdef CONFIG_ATA_ACPI
1326 static void ahci_gtf_filter_workaround(struct ata_host *host)
1328 static const struct dmi_system_id sysids[] = {
1330 * Aspire 3810T issues a bunch of SATA enable commands
1331 * via _GTF including an invalid one and one which is
1332 * rejected by the device. Among the successful ones
1333 * is FPDMA non-zero offset enable which when enabled
1334 * only on the drive side leads to NCQ command
1335 * failures. Filter it out.
1338 .ident = "Aspire 3810T",
1340 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1341 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1343 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1347 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1348 unsigned int filter;
1354 filter = (unsigned long)dmi->driver_data;
1355 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1356 filter, dmi->ident);
1358 for (i = 0; i < host->n_ports; i++) {
1359 struct ata_port *ap = host->ports[i];
1360 struct ata_link *link;
1361 struct ata_device *dev;
1363 ata_for_each_link(link, ap, EDGE)
1364 ata_for_each_dev(dev, link, ALL)
1365 dev->gtf_filter |= filter;
1369 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1374 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1375 * as DUMMY, or detected but eventually get a "link down" and never get up
1376 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1377 * port_map may hold a value of 0x00.
1379 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1380 * and can significantly reduce the occurrence of the problem.
1382 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1384 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1385 struct pci_dev *pdev)
1387 static const struct dmi_system_id sysids[] = {
1389 .ident = "Acer Switch Alpha 12",
1391 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1392 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1398 if (dmi_check_system(sysids)) {
1399 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1400 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1401 hpriv->port_map = 0x7;
1402 hpriv->cap = 0xC734FF02;
1409 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1410 * Workaround is to make sure all pending IRQs are served before leaving
1413 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1415 struct ata_host *host = dev_instance;
1416 struct ahci_host_priv *hpriv;
1417 unsigned int rc = 0;
1419 u32 irq_stat, irq_masked;
1420 unsigned int handled = 1;
1423 hpriv = host->private_data;
1425 irq_stat = readl(mmio + HOST_IRQ_STAT);
1430 irq_masked = irq_stat & hpriv->port_map;
1431 spin_lock(&host->lock);
1432 rc = ahci_handle_port_intr(host, irq_masked);
1435 writel(irq_stat, mmio + HOST_IRQ_STAT);
1436 irq_stat = readl(mmio + HOST_IRQ_STAT);
1437 spin_unlock(&host->lock);
1441 return IRQ_RETVAL(handled);
1445 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1446 struct ahci_host_priv *hpriv)
1452 * Check if this device might have remapped nvme devices.
1454 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1455 pci_resource_len(pdev, bar) < SZ_512K ||
1456 bar != AHCI_PCI_BAR_STANDARD ||
1457 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1460 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1461 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1462 if ((cap & (1 << i)) == 0)
1464 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1465 != PCI_CLASS_STORAGE_EXPRESS)
1468 /* We've found a remapped device */
1475 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1476 dev_warn(&pdev->dev,
1477 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1480 * Don't rely on the msi-x capability in the remap case,
1481 * share the legacy interrupt across ahci and remapped devices.
1483 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1486 static int ahci_get_irq_vector(struct ata_host *host, int port)
1488 return pci_irq_vector(to_pci_dev(host->dev), port);
1491 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1492 struct ahci_host_priv *hpriv)
1496 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1500 * If number of MSIs is less than number of ports then Sharing Last
1501 * Message mode could be enforced. In this case assume that advantage
1502 * of multipe MSIs is negated and use single MSI mode instead.
1505 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1506 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1508 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1509 hpriv->get_irq_vector = ahci_get_irq_vector;
1510 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1515 * Fallback to single MSI mode if the controller
1516 * enforced MRSM mode.
1519 "ahci: MRSM is on, fallback to single MSI\n");
1520 pci_free_irq_vectors(pdev);
1525 * If the host is not capable of supporting per-port vectors, fall
1526 * back to single MSI before finally attempting single MSI-X.
1528 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1531 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1534 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1536 unsigned int board_id = ent->driver_data;
1537 struct ata_port_info pi = ahci_port_info[board_id];
1538 const struct ata_port_info *ppi[] = { &pi, NULL };
1539 struct device *dev = &pdev->dev;
1540 struct ahci_host_priv *hpriv;
1541 struct ata_host *host;
1543 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1547 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1549 ata_print_version_once(&pdev->dev, DRV_VERSION);
1551 /* The AHCI driver can only drive the SATA ports, the PATA driver
1552 can drive them all so if both drivers are selected make sure
1553 AHCI stays out of the way */
1554 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1557 /* Apple BIOS on MCP89 prevents us using AHCI */
1558 if (is_mcp89_apple(pdev))
1559 ahci_mcp89_apple_enable(pdev);
1561 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1562 * At the moment, we can only use the AHCI mode. Let the users know
1563 * that for SAS drives they're out of luck.
1565 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1566 dev_info(&pdev->dev,
1567 "PDC42819 can only drive SATA devices with this driver\n");
1569 /* Some devices use non-standard BARs */
1570 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1571 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1572 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1573 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1574 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1575 if (pdev->device == 0xa01c)
1576 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1577 if (pdev->device == 0xa084)
1578 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1581 /* acquire resources */
1582 rc = pcim_enable_device(pdev);
1586 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1587 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1590 /* ICH6s share the same PCI ID for both piix and ahci
1591 * modes. Enabling ahci mode while MAP indicates
1592 * combined mode is a bad idea. Yield to ata_piix.
1594 pci_read_config_byte(pdev, ICH_MAP, &map);
1596 dev_info(&pdev->dev,
1597 "controller is in combined mode, can't enable AHCI mode\n");
1602 /* AHCI controllers often implement SFF compatible interface.
1603 * Grab all PCI BARs just in case.
1605 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1607 pcim_pin_device(pdev);
1611 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1614 hpriv->flags |= (unsigned long)pi.private_data;
1616 /* MCP65 revision A1 and A2 can't do MSI */
1617 if (board_id == board_ahci_mcp65 &&
1618 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1619 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1621 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1622 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1623 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1625 /* only some SB600s can do 64bit DMA */
1626 if (ahci_sb600_enable_64bit(pdev))
1627 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1629 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1631 /* detect remapped nvme devices */
1632 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1634 /* must set flag prior to save config in order to take effect */
1635 if (ahci_broken_devslp(pdev))
1636 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1639 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1640 hpriv->irq_handler = ahci_thunderx_irq_handler;
1643 /* save initial config */
1644 ahci_pci_save_initial_config(pdev, hpriv);
1647 if (hpriv->cap & HOST_CAP_NCQ) {
1648 pi.flags |= ATA_FLAG_NCQ;
1650 * Auto-activate optimization is supposed to be
1651 * supported on all AHCI controllers indicating NCQ
1652 * capability, but it seems to be broken on some
1653 * chipsets including NVIDIAs.
1655 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1656 pi.flags |= ATA_FLAG_FPDMA_AA;
1659 * All AHCI controllers should be forward-compatible
1660 * with the new auxiliary field. This code should be
1661 * conditionalized if any buggy AHCI controllers are
1664 pi.flags |= ATA_FLAG_FPDMA_AUX;
1667 if (hpriv->cap & HOST_CAP_PMP)
1668 pi.flags |= ATA_FLAG_PMP;
1670 ahci_set_em_messages(hpriv, &pi);
1672 if (ahci_broken_system_poweroff(pdev)) {
1673 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1674 dev_info(&pdev->dev,
1675 "quirky BIOS, skipping spindown on poweroff\n");
1678 if (ahci_broken_suspend(pdev)) {
1679 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1680 dev_warn(&pdev->dev,
1681 "BIOS update required for suspend/resume\n");
1684 if (ahci_broken_online(pdev)) {
1685 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1686 dev_info(&pdev->dev,
1687 "online status unreliable, applying workaround\n");
1691 /* Acer SA5-271 workaround modifies private_data */
1692 acer_sa5_271_workaround(hpriv, pdev);
1694 /* CAP.NP sometimes indicate the index of the last enabled
1695 * port, at other times, that of the last possible port, so
1696 * determining the maximum port number requires looking at
1697 * both CAP.NP and port_map.
1699 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1701 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1704 host->private_data = hpriv;
1706 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1707 /* legacy intx interrupts */
1710 hpriv->irq = pci_irq_vector(pdev, 0);
1712 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1713 host->flags |= ATA_HOST_PARALLEL_SCAN;
1715 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1717 if (pi.flags & ATA_FLAG_EM)
1718 ahci_reset_em(host);
1720 for (i = 0; i < host->n_ports; i++) {
1721 struct ata_port *ap = host->ports[i];
1723 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1724 ata_port_pbar_desc(ap, ahci_pci_bar,
1725 0x100 + ap->port_no * 0x80, "port");
1727 /* set enclosure management message type */
1728 if (ap->flags & ATA_FLAG_EM)
1729 ap->em_message_type = hpriv->em_msg_type;
1732 /* disabled/not-implemented port */
1733 if (!(hpriv->port_map & (1 << i)))
1734 ap->ops = &ata_dummy_port_ops;
1737 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1738 ahci_p5wdh_workaround(host);
1740 /* apply gtf filter quirk */
1741 ahci_gtf_filter_workaround(host);
1743 /* initialize adapter */
1744 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1748 rc = ahci_pci_reset_controller(host);
1752 ahci_pci_init_controller(host);
1753 ahci_pci_print_info(host);
1755 pci_set_master(pdev);
1757 rc = ahci_host_activate(host, &ahci_sht);
1761 pm_runtime_put_noidle(&pdev->dev);
1765 static void ahci_remove_one(struct pci_dev *pdev)
1767 pm_runtime_get_noresume(&pdev->dev);
1768 ata_pci_remove_one(pdev);
1771 module_pci_driver(ahci_pci_driver);
1773 MODULE_AUTHOR("Jeff Garzik");
1774 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1775 MODULE_LICENSE("GPL");
1776 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1777 MODULE_VERSION(DRV_VERSION);