drivers/acpi/processor_idle.c

   1 /*
   2  * processor_idle - idle state submodule to the ACPI processor driver
   3  *
   4  *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
   5  *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
   6  *  Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de>
   7  *  Copyright (C) 2004  Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
   8  *                      - Added processor hotplug support
   9  *  Copyright (C) 2005  Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
  10  *                      - Added support for C3 on SMP
  11  *
  12  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License as published by
  16  *  the Free Software Foundation; either version 2 of the License, or (at
  17  *  your option) any later version.
  18  *
  19  *  This program is distributed in the hope that it will be useful, but
  20  *  WITHOUT ANY WARRANTY; without even the implied warranty of
  21  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  22  *  General Public License for more details.
  23  *
  24  *  You should have received a copy of the GNU General Public License along
  25  *  with this program; if not, write to the Free Software Foundation, Inc.,
  26  *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  27  *
  28  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  29  */
  30
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/init.h>
  34 #include <linux/cpufreq.h>
  35 #include <linux/proc_fs.h>
  36 #include <linux/seq_file.h>
  37 #include <linux/acpi.h>
  38 #include <linux/dmi.h>
  39 #include <linux/moduleparam.h>
  40 #include <linux/sched.h>        /* need_resched() */
  41 #include <linux/pm_qos_params.h>
  42 #include <linux/clockchips.h>
  43 #include <linux/cpuidle.h>
  44 #include <linux/cpuidle.h>
  45
  46 /*
  47  * Include the apic definitions for x86 to have the APIC timer related defines
  48  * available also for UP (on SMP it gets magically included via linux/smp.h).
  49  * asm/acpi.h is not an option, as it would require more include magic. Also
  50  * creating an empty asm-ia64/apic.h would just trade pest vs. cholera.
  51  */
  52 #ifdef CONFIG_X86
  53 #include <asm/apic.h>
  54 #endif
  55
  56 #include <asm/io.h>
  57 #include <asm/uaccess.h>
  58
  59 #include <acpi/acpi_bus.h>
  60 #include <acpi/processor.h>
  61 #include <asm/processor.h>
  62
  63 #define ACPI_PROCESSOR_COMPONENT        0x01000000
  64 #define ACPI_PROCESSOR_CLASS            "processor"
  65 #define _COMPONENT              ACPI_PROCESSOR_COMPONENT
  66 ACPI_MODULE_NAME("processor_idle");
  67 #define ACPI_PROCESSOR_FILE_POWER       "power"
  68 #define US_TO_PM_TIMER_TICKS(t)         ((t * (PM_TIMER_FREQUENCY/1000)) / 1000)
  69 #define PM_TIMER_TICK_NS                (1000000000ULL/PM_TIMER_FREQUENCY)
  70 #ifndef CONFIG_CPU_IDLE
  71 #define C2_OVERHEAD                     4       /* 1us (3.579 ticks per us) */
  72 #define C3_OVERHEAD                     4       /* 1us (3.579 ticks per us) */
  73 static void (*pm_idle_save) (void) __read_mostly;
  74 #else
  75 #define C2_OVERHEAD                     1       /* 1us */
  76 #define C3_OVERHEAD                     1       /* 1us */
  77 #endif
  78 #define PM_TIMER_TICKS_TO_US(p)         (((p) * 1000)/(PM_TIMER_FREQUENCY/1000))
  79
  80 static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER;
  81 #ifdef CONFIG_CPU_IDLE
  82 module_param(max_cstate, uint, 0000);
  83 #else
  84 module_param(max_cstate, uint, 0644);
  85 #endif
  86 static unsigned int nocst __read_mostly;
  87 module_param(nocst, uint, 0000);
  88
  89 #ifndef CONFIG_CPU_IDLE
  90 /*
  91  * bm_history -- bit-mask with a bit per jiffy of bus-master activity
  92  * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms
  93  * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms
  94  * 100 HZ: 0x0000000F: 4 jiffies = 40ms
  95  * reduce history for more aggressive entry into C3
  96  */
  97 static unsigned int bm_history __read_mostly =
  98     (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1));
  99 module_param(bm_history, uint, 0644);
 100
 101 static int acpi_processor_set_power_policy(struct acpi_processor *pr);
 102
 103 #else   /* CONFIG_CPU_IDLE */
 104 static unsigned int latency_factor __read_mostly = 2;
 105 module_param(latency_factor, uint, 0644);
 106 #endif
 107
 108 /*
 109  * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3.
 110  * For now disable this. Probably a bug somewhere else.
 111  *
 112  * To skip this limit, boot/load with a large max_cstate limit.
 113  */
 114 static int set_max_cstate(const struct dmi_system_id *id)
 115 {
 116         if (max_cstate > ACPI_PROCESSOR_MAX_POWER)
 117                 return 0;
 118
 119         printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate."
 120                " Override with \"processor.max_cstate=%d\"\n", id->ident,
 121                (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1);
 122
 123         max_cstate = (long)id->driver_data;
 124
 125         return 0;
 126 }
 127
 128 /* Actually this shouldn't be __cpuinitdata, would be better to fix the
 129    callers to only run once -AK */
 130 static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = {
 131         { set_max_cstate, "IBM ThinkPad R40e", {
 132           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 133           DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1},
 134         { set_max_cstate, "IBM ThinkPad R40e", {
 135           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 136           DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1},
 137         { set_max_cstate, "IBM ThinkPad R40e", {
 138           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 139           DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1},
 140         { set_max_cstate, "IBM ThinkPad R40e", {
 141           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 142           DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1},
 143         { set_max_cstate, "IBM ThinkPad R40e", {
 144           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 145           DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1},
 146         { set_max_cstate, "IBM ThinkPad R40e", {
 147           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 148           DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1},
 149         { set_max_cstate, "IBM ThinkPad R40e", {
 150           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 151           DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1},
 152         { set_max_cstate, "IBM ThinkPad R40e", {
 153           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 154           DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1},
 155         { set_max_cstate, "IBM ThinkPad R40e", {
 156           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 157           DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1},
 158         { set_max_cstate, "IBM ThinkPad R40e", {
 159           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 160           DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1},
 161         { set_max_cstate, "IBM ThinkPad R40e", {
 162           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 163           DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1},
 164         { set_max_cstate, "IBM ThinkPad R40e", {
 165           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 166           DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1},
 167         { set_max_cstate, "IBM ThinkPad R40e", {
 168           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 169           DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1},
 170         { set_max_cstate, "IBM ThinkPad R40e", {
 171           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 172           DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1},
 173         { set_max_cstate, "IBM ThinkPad R40e", {
 174           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 175           DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1},
 176         { set_max_cstate, "IBM ThinkPad R40e", {
 177           DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
 178           DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1},
 179         { set_max_cstate, "Medion 41700", {
 180           DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
 181           DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1},
 182         { set_max_cstate, "Clevo 5600D", {
 183           DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
 184           DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")},
 185          (void *)2},
 186         {},
 187 };
 188
 189 static inline u32 ticks_elapsed(u32 t1, u32 t2)
 190 {
 191         if (t2 >= t1)
 192                 return (t2 - t1);
 193         else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER))
 194                 return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
 195         else
 196                 return ((0xFFFFFFFF - t1) + t2);
 197 }
 198
 199 static inline u32 ticks_elapsed_in_us(u32 t1, u32 t2)
 200 {
 201         if (t2 >= t1)
 202                 return PM_TIMER_TICKS_TO_US(t2 - t1);
 203         else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER))
 204                 return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
 205         else
 206                 return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1) + t2);
 207 }
 208
 209 /*
 210  * Callers should disable interrupts before the call and enable
 211  * interrupts after return.
 212  */
 213 static void acpi_safe_halt(void)
 214 {
 215         current_thread_info()->status &= ~TS_POLLING;
 216         /*
 217          * TS_POLLING-cleared state must be visible before we
 218          * test NEED_RESCHED:
 219          */
 220         smp_mb();
 221         if (!need_resched()) {
 222                 safe_halt();
 223                 local_irq_disable();
 224         }
 225         current_thread_info()->status |= TS_POLLING;
 226 }
 227
 228 #ifndef CONFIG_CPU_IDLE
 229
 230 static void
 231 acpi_processor_power_activate(struct acpi_processor *pr,
 232                               struct acpi_processor_cx *new)
 233 {
 234         struct acpi_processor_cx *old;
 235
 236         if (!pr || !new)
 237                 return;
 238
 239         old = pr->power.state;
 240
 241         if (old)
 242                 old->promotion.count = 0;
 243         new->demotion.count = 0;
 244
 245         /* Cleanup from old state. */
 246         if (old) {
 247                 switch (old->type) {
 248                 case ACPI_STATE_C3:
 249                         /* Disable bus master reload */
 250                         if (new->type != ACPI_STATE_C3 && pr->flags.bm_check)
 251                                 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
 252                         break;
 253                 }
 254         }
 255
 256         /* Prepare to use new state. */
 257         switch (new->type) {
 258         case ACPI_STATE_C3:
 259                 /* Enable bus master reload */
 260                 if (old->type != ACPI_STATE_C3 && pr->flags.bm_check)
 261                         acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
 262                 break;
 263         }
 264
 265         pr->power.state = new;
 266
 267         return;
 268 }
 269
 270 static atomic_t c3_cpu_count;
 271
 272 /* Common C-state entry for C2, C3, .. */
 273 static void acpi_cstate_enter(struct acpi_processor_cx *cstate)
 274 {
 275         if (cstate->entry_method == ACPI_CSTATE_FFH) {
 276                 /* Call into architectural FFH based C-state */
 277                 acpi_processor_ffh_cstate_enter(cstate);
 278         } else {
 279                 int unused;
 280                 /* IO port based C-state */
 281                 inb(cstate->address);
 282                 /* Dummy wait op - must do something useless after P_LVL2 read
 283                    because chipsets cannot guarantee that STPCLK# signal
 284                    gets asserted in time to freeze execution properly. */
 285                 unused = inl(acpi_gbl_FADT.xpm_timer_block.address);
 286         }
 287 }
 288 #endif /* !CONFIG_CPU_IDLE */
 289
 290 #ifdef ARCH_APICTIMER_STOPS_ON_C3
 291
 292 /*
 293  * Some BIOS implementations switch to C3 in the published C2 state.
 294  * This seems to be a common problem on AMD boxen, but other vendors
 295  * are affected too. We pick the most conservative approach: we assume
 296  * that the local APIC stops in both C2 and C3.
 297  */
 298 static void acpi_timer_check_state(int state, struct acpi_processor *pr,
 299                                    struct acpi_processor_cx *cx)
 300 {
 301         struct acpi_processor_power *pwr = &pr->power;
 302         u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2;
 303
 304         /*
 305          * Check, if one of the previous states already marked the lapic
 306          * unstable
 307          */
 308         if (pwr->timer_broadcast_on_state < state)
 309                 return;
 310
 311         if (cx->type >= type)
 312                 pr->power.timer_broadcast_on_state = state;
 313 }
 314
 315 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr)
 316 {
 317         unsigned long reason;
 318
 319         reason = pr->power.timer_broadcast_on_state < INT_MAX ?
 320                 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
 321
 322         clockevents_notify(reason, &pr->id);
 323 }
 324
 325 /* Power(C) State timer broadcast control */
 326 static void acpi_state_timer_broadcast(struct acpi_processor *pr,
 327                                        struct acpi_processor_cx *cx,
 328                                        int broadcast)
 329 {
 330         int state = cx - pr->power.states;
 331
 332         if (state >= pr->power.timer_broadcast_on_state) {
 333                 unsigned long reason;
 334
 335                 reason = broadcast ?  CLOCK_EVT_NOTIFY_BROADCAST_ENTER :
 336                         CLOCK_EVT_NOTIFY_BROADCAST_EXIT;
 337                 clockevents_notify(reason, &pr->id);
 338         }
 339 }
 340
 341 #else
 342
 343 static void acpi_timer_check_state(int state, struct acpi_processor *pr,
 344                                    struct acpi_processor_cx *cstate) { }
 345 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { }
 346 static void acpi_state_timer_broadcast(struct acpi_processor *pr,
 347                                        struct acpi_processor_cx *cx,
 348                                        int broadcast)
 349 {
 350 }
 351
 352 #endif
 353
 354 /*
 355  * Suspend / resume control
 356  */
 357 static int acpi_idle_suspend;
 358
 359 int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
 360 {
 361         acpi_idle_suspend = 1;
 362         return 0;
 363 }
 364
 365 int acpi_processor_resume(struct acpi_device * device)
 366 {
 367         acpi_idle_suspend = 0;
 368         return 0;
 369 }
 370
 371 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
 372 static int tsc_halts_in_c(int state)
 373 {
 374         switch (boot_cpu_data.x86_vendor) {
 375         case X86_VENDOR_AMD:
 376                 /*
 377                  * AMD Fam10h TSC will tick in all
 378                  * C/P/S0/S1 states when this bit is set.
 379                  */
 380                 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
 381                         return 0;
 382                 /*FALL THROUGH*/
 383         case X86_VENDOR_INTEL:
 384                 /* Several cases known where TSC halts in C2 too */
 385         default:
 386                 return state > ACPI_STATE_C1;
 387         }
 388 }
 389 #endif
 390
 391 #ifndef CONFIG_CPU_IDLE
 392 static void acpi_processor_idle(void)
 393 {
 394         struct acpi_processor *pr = NULL;
 395         struct acpi_processor_cx *cx = NULL;
 396         struct acpi_processor_cx *next_state = NULL;
 397         int sleep_ticks = 0;
 398         u32 t1, t2 = 0;
 399
 400         /*
 401          * Interrupts must be disabled during bus mastering calculations and
 402          * for C2/C3 transitions.
 403          */
 404         local_irq_disable();
 405
 406         pr = __get_cpu_var(processors);
 407         if (!pr) {
 408                 local_irq_enable();
 409                 return;
 410         }
 411
 412         /*
 413          * Check whether we truly need to go idle, or should
 414          * reschedule:
 415          */
 416         if (unlikely(need_resched())) {
 417                 local_irq_enable();
 418                 return;
 419         }
 420
 421         cx = pr->power.state;
 422         if (!cx || acpi_idle_suspend) {
 423                 if (pm_idle_save) {
 424                         pm_idle_save(); /* enables IRQs */
 425                 } else {
 426                         acpi_safe_halt();
 427                         local_irq_enable();
 428                 }
 429
 430                 return;
 431         }
 432
 433         /*
 434          * Check BM Activity
 435          * -----------------
 436          * Check for bus mastering activity (if required), record, and check
 437          * for demotion.
 438          */
 439         if (pr->flags.bm_check) {
 440                 u32 bm_status = 0;
 441                 unsigned long diff = jiffies - pr->power.bm_check_timestamp;
 442
 443                 if (diff > 31)
 444                         diff = 31;
 445
 446                 pr->power.bm_activity <<= diff;
 447
 448                 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
 449                 if (bm_status) {
 450                         pr->power.bm_activity |= 0x1;
 451                         acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
 452                 }
 453                 /*
 454                  * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
 455                  * the true state of bus mastering activity; forcing us to
 456                  * manually check the BMIDEA bit of each IDE channel.
 457                  */
 458                 else if (errata.piix4.bmisx) {
 459                         if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
 460                             || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
 461                                 pr->power.bm_activity |= 0x1;
 462                 }
 463
 464                 pr->power.bm_check_timestamp = jiffies;
 465
 466                 /*
 467                  * If bus mastering is or was active this jiffy, demote
 468                  * to avoid a faulty transition.  Note that the processor
 469                  * won't enter a low-power state during this call (to this
 470                  * function) but should upon the next.
 471                  *
 472                  * TBD: A better policy might be to fallback to the demotion
 473                  *      state (use it for this quantum only) istead of
 474                  *      demoting -- and rely on duration as our sole demotion
 475                  *      qualification.  This may, however, introduce DMA
 476                  *      issues (e.g. floppy DMA transfer overrun/underrun).
 477                  */
 478                 if ((pr->power.bm_activity & 0x1) &&
 479                     cx->demotion.threshold.bm) {
 480                         local_irq_enable();
 481                         next_state = cx->demotion.state;
 482                         goto end;
 483                 }
 484         }
 485
 486 #ifdef CONFIG_HOTPLUG_CPU
 487         /*
 488          * Check for P_LVL2_UP flag before entering C2 and above on
 489          * an SMP system. We do it here instead of doing it at _CST/P_LVL
 490          * detection phase, to work cleanly with logical CPU hotplug.
 491          */
 492         if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
 493             !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
 494                 cx = &pr->power.states[ACPI_STATE_C1];
 495 #endif
 496
 497         /*
 498          * Sleep:
 499          * ------
 500          * Invoke the current Cx state to put the processor to sleep.
 501          */
 502         if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) {
 503                 current_thread_info()->status &= ~TS_POLLING;
 504                 /*
 505                  * TS_POLLING-cleared state must be visible before we
 506                  * test NEED_RESCHED:
 507                  */
 508                 smp_mb();
 509                 if (need_resched()) {
 510                         current_thread_info()->status |= TS_POLLING;
 511                         local_irq_enable();
 512                         return;
 513                 }
 514         }
 515
 516         switch (cx->type) {
 517
 518         case ACPI_STATE_C1:
 519                 /*
 520                  * Invoke C1.
 521                  * Use the appropriate idle routine, the one that would
 522                  * be used without acpi C-states.
 523                  */
 524                 if (pm_idle_save) {
 525                         pm_idle_save(); /* enables IRQs */
 526                 } else {
 527                         acpi_safe_halt();
 528                         local_irq_enable();
 529                 }
 530
 531                 /*
 532                  * TBD: Can't get time duration while in C1, as resumes
 533                  *      go to an ISR rather than here.  Need to instrument
 534                  *      base interrupt handler.
 535                  *
 536                  * Note: the TSC better not stop in C1, sched_clock() will
 537                  *       skew otherwise.
 538                  */
 539                 sleep_ticks = 0xFFFFFFFF;
 540
 541                 break;
 542
 543         case ACPI_STATE_C2:
 544                 /* Get start time (ticks) */
 545                 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
 546                 /* Tell the scheduler that we are going deep-idle: */
 547                 sched_clock_idle_sleep_event();
 548                 /* Invoke C2 */
 549                 acpi_state_timer_broadcast(pr, cx, 1);
 550                 acpi_cstate_enter(cx);
 551                 /* Get end time (ticks) */
 552                 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
 553
 554 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
 555                 /* TSC halts in C2, so notify users */
 556                 if (tsc_halts_in_c(ACPI_STATE_C2))
 557                         mark_tsc_unstable("possible TSC halt in C2");
 558 #endif
 559                 /* Compute time (ticks) that we were actually asleep */
 560                 sleep_ticks = ticks_elapsed(t1, t2);
 561
 562                 /* Tell the scheduler how much we idled: */
 563                 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
 564
 565                 /* Re-enable interrupts */
 566                 local_irq_enable();
 567                 /* Do not account our idle-switching overhead: */
 568                 sleep_ticks -= cx->latency_ticks + C2_OVERHEAD;
 569
 570                 current_thread_info()->status |= TS_POLLING;
 571                 acpi_state_timer_broadcast(pr, cx, 0);
 572                 break;
 573
 574         case ACPI_STATE_C3:
 575                 acpi_unlazy_tlb(smp_processor_id());
 576                 /*
 577                  * Must be done before busmaster disable as we might
 578                  * need to access HPET !
 579                  */
 580                 acpi_state_timer_broadcast(pr, cx, 1);
 581                 /*
 582                  * disable bus master
 583                  * bm_check implies we need ARB_DIS
 584                  * !bm_check implies we need cache flush
 585                  * bm_control implies whether we can do ARB_DIS
 586                  *
 587                  * That leaves a case where bm_check is set and bm_control is
 588                  * not set. In that case we cannot do much, we enter C3
 589                  * without doing anything.
 590                  */
 591                 if (pr->flags.bm_check && pr->flags.bm_control) {
 592                         if (atomic_inc_return(&c3_cpu_count) ==
 593                             num_online_cpus()) {
 594                                 /*
 595                                  * All CPUs are trying to go to C3
 596                                  * Disable bus master arbitration
 597                                  */
 598                                 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
 599                         }
 600                 } else if (!pr->flags.bm_check) {
 601                         /* SMP with no shared cache... Invalidate cache  */
 602                         ACPI_FLUSH_CPU_CACHE();
 603                 }
 604
 605                 /* Get start time (ticks) */
 606                 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
 607                 /* Invoke C3 */
 608                 /* Tell the scheduler that we are going deep-idle: */
 609                 sched_clock_idle_sleep_event();
 610                 acpi_cstate_enter(cx);
 611                 /* Get end time (ticks) */
 612                 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
 613                 if (pr->flags.bm_check && pr->flags.bm_control) {
 614                         /* Enable bus master arbitration */
 615                         atomic_dec(&c3_cpu_count);
 616                         acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
 617                 }
 618
 619 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
 620                 /* TSC halts in C3, so notify users */
 621                 if (tsc_halts_in_c(ACPI_STATE_C3))
 622                         mark_tsc_unstable("TSC halts in C3");
 623 #endif
 624                 /* Compute time (ticks) that we were actually asleep */
 625                 sleep_ticks = ticks_elapsed(t1, t2);
 626                 /* Tell the scheduler how much we idled: */
 627                 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
 628
 629                 /* Re-enable interrupts */
 630                 local_irq_enable();
 631                 /* Do not account our idle-switching overhead: */
 632                 sleep_ticks -= cx->latency_ticks + C3_OVERHEAD;
 633
 634                 current_thread_info()->status |= TS_POLLING;
 635                 acpi_state_timer_broadcast(pr, cx, 0);
 636                 break;
 637
 638         default:
 639                 local_irq_enable();
 640                 return;
 641         }
 642         cx->usage++;
 643         if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0))
 644                 cx->time += sleep_ticks;
 645
 646         next_state = pr->power.state;
 647
 648 #ifdef CONFIG_HOTPLUG_CPU
 649         /* Don't do promotion/demotion */
 650         if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) &&
 651             !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) {
 652                 next_state = cx;
 653                 goto end;
 654         }
 655 #endif
 656
 657         /*
 658          * Promotion?
 659          * ----------
 660          * Track the number of longs (time asleep is greater than threshold)
 661          * and promote when the count threshold is reached.  Note that bus
 662          * mastering activity may prevent promotions.
 663          * Do not promote above max_cstate.
 664          */
 665         if (cx->promotion.state &&
 666             ((cx->promotion.state - pr->power.states) <= max_cstate)) {
 667                 if (sleep_ticks > cx->promotion.threshold.ticks &&
 668                   cx->promotion.state->latency <=
 669                                 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) {
 670                         cx->promotion.count++;
 671                         cx->demotion.count = 0;
 672                         if (cx->promotion.count >=
 673                             cx->promotion.threshold.count) {
 674                                 if (pr->flags.bm_check) {
 675                                         if (!
 676                                             (pr->power.bm_activity & cx->
 677                                              promotion.threshold.bm)) {
 678                                                 next_state =
 679                                                     cx->promotion.state;
 680                                                 goto end;
 681                                         }
 682                                 } else {
 683                                         next_state = cx->promotion.state;
 684                                         goto end;
 685                                 }
 686                         }
 687                 }
 688         }
 689
 690         /*
 691          * Demotion?
 692          * ---------
 693          * Track the number of shorts (time asleep is less than time threshold)
 694          * and demote when the usage threshold is reached.
 695          */
 696         if (cx->demotion.state) {
 697                 if (sleep_ticks < cx->demotion.threshold.ticks) {
 698                         cx->demotion.count++;
 699                         cx->promotion.count = 0;
 700                         if (cx->demotion.count >= cx->demotion.threshold.count) {
 701                                 next_state = cx->demotion.state;
 702                                 goto end;
 703                         }
 704                 }
 705         }
 706
 707       end:
 708         /*
 709          * Demote if current state exceeds max_cstate
 710          * or if the latency of the current state is unacceptable
 711          */
 712         if ((pr->power.state - pr->power.states) > max_cstate ||
 713                 pr->power.state->latency >
 714                                 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) {
 715                 if (cx->demotion.state)
 716                         next_state = cx->demotion.state;
 717         }
 718
 719         /*
 720          * New Cx State?
 721          * -------------
 722          * If we're going to start using a new Cx state we must clean up
 723          * from the previous and prepare to use the new.
 724          */
 725         if (next_state != pr->power.state)
 726                 acpi_processor_power_activate(pr, next_state);
 727 }
 728
 729 static int acpi_processor_set_power_policy(struct acpi_processor *pr)
 730 {
 731         unsigned int i;
 732         unsigned int state_is_set = 0;
 733         struct acpi_processor_cx *lower = NULL;
 734         struct acpi_processor_cx *higher = NULL;
 735         struct acpi_processor_cx *cx;
 736
 737
 738         if (!pr)
 739                 return -EINVAL;
 740
 741         /*
 742          * This function sets the default Cx state policy (OS idle handler).
 743          * Our scheme is to promote quickly to C2 but more conservatively
 744          * to C3.  We're favoring C2  for its characteristics of low latency
 745          * (quick response), good power savings, and ability to allow bus
 746          * mastering activity.  Note that the Cx state policy is completely
 747          * customizable and can be altered dynamically.
 748          */
 749
 750         /* startup state */
 751         for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
 752                 cx = &pr->power.states[i];
 753                 if (!cx->valid)
 754                         continue;
 755
 756                 if (!state_is_set)
 757                         pr->power.state = cx;
 758                 state_is_set++;
 759                 break;
 760         }
 761
 762         if (!state_is_set)
 763                 return -ENODEV;
 764
 765         /* demotion */
 766         for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
 767                 cx = &pr->power.states[i];
 768                 if (!cx->valid)
 769                         continue;
 770
 771                 if (lower) {
 772                         cx->demotion.state = lower;
 773                         cx->demotion.threshold.ticks = cx->latency_ticks;
 774                         cx->demotion.threshold.count = 1;
 775                         if (cx->type == ACPI_STATE_C3)
 776                                 cx->demotion.threshold.bm = bm_history;
 777                 }
 778
 779                 lower = cx;
 780         }
 781
 782         /* promotion */
 783         for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) {
 784                 cx = &pr->power.states[i];
 785                 if (!cx->valid)
 786                         continue;
 787
 788                 if (higher) {
 789                         cx->promotion.state = higher;
 790                         cx->promotion.threshold.ticks = cx->latency_ticks;
 791                         if (cx->type >= ACPI_STATE_C2)
 792                                 cx->promotion.threshold.count = 4;
 793                         else
 794                                 cx->promotion.threshold.count = 10;
 795                         if (higher->type == ACPI_STATE_C3)
 796                                 cx->promotion.threshold.bm = bm_history;
 797                 }
 798
 799                 higher = cx;
 800         }
 801
 802         return 0;
 803 }
 804 #endif /* !CONFIG_CPU_IDLE */
 805
 806 static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
 807 {
 808
 809         if (!pr)
 810                 return -EINVAL;
 811
 812         if (!pr->pblk)
 813                 return -ENODEV;
 814
 815         /* if info is obtained from pblk/fadt, type equals state */
 816         pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2;
 817         pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3;
 818
 819 #ifndef CONFIG_HOTPLUG_CPU
 820         /*
 821          * Check for P_LVL2_UP flag before entering C2 and above on
 822          * an SMP system.
 823          */
 824         if ((num_online_cpus() > 1) &&
 825             !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
 826                 return -ENODEV;
 827 #endif
 828
 829         /* determine C2 and C3 address from pblk */
 830         pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4;
 831         pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5;
 832
 833         /* determine latencies from FADT */
 834         pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency;
 835         pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency;
 836
 837         ACPI_DEBUG_PRINT((ACPI_DB_INFO,
 838                           "lvl2[0x%08x] lvl3[0x%08x]\n",
 839                           pr->power.states[ACPI_STATE_C2].address,
 840                           pr->power.states[ACPI_STATE_C3].address));
 841
 842         return 0;
 843 }
 844
 845 static int acpi_processor_get_power_info_default(struct acpi_processor *pr)
 846 {
 847         if (!pr->power.states[ACPI_STATE_C1].valid) {
 848                 /* set the first C-State to C1 */
 849                 /* all processors need to support C1 */
 850                 pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1;
 851                 pr->power.states[ACPI_STATE_C1].valid = 1;
 852                 pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT;
 853         }
 854         /* the C0 state only exists as a filler in our array */
 855         pr->power.states[ACPI_STATE_C0].valid = 1;
 856         return 0;
 857 }
 858
 859 static int acpi_processor_get_power_info_cst(struct acpi_processor *pr)
 860 {
 861         acpi_status status = 0;
 862         acpi_integer count;
 863         int current_count;
 864         int i;
 865         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
 866         union acpi_object *cst;
 867
 868
 869         if (nocst)
 870                 return -ENODEV;
 871
 872         current_count = 0;
 873
 874         status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer);
 875         if (ACPI_FAILURE(status)) {
 876                 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n"));
 877                 return -ENODEV;
 878         }
 879
 880         cst = buffer.pointer;
 881
 882         /* There must be at least 2 elements */
 883         if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) {
 884                 printk(KERN_ERR PREFIX "not enough elements in _CST\n");
 885                 status = -EFAULT;
 886                 goto end;
 887         }
 888
 889         count = cst->package.elements[0].integer.value;
 890
 891         /* Validate number of power states. */
 892         if (count < 1 || count != cst->package.count - 1) {
 893                 printk(KERN_ERR PREFIX "count given by _CST is not valid\n");
 894                 status = -EFAULT;
 895                 goto end;
 896         }
 897
 898         /* Tell driver that at least _CST is supported. */
 899         pr->flags.has_cst = 1;
 900
 901         for (i = 1; i <= count; i++) {
 902                 union acpi_object *element;
 903                 union acpi_object *obj;
 904                 struct acpi_power_register *reg;
 905                 struct acpi_processor_cx cx;
 906
 907                 memset(&cx, 0, sizeof(cx));
 908
 909                 element = &(cst->package.elements[i]);
 910                 if (element->type != ACPI_TYPE_PACKAGE)
 911                         continue;
 912
 913                 if (element->package.count != 4)
 914                         continue;
 915
 916                 obj = &(element->package.elements[0]);
 917
 918                 if (obj->type != ACPI_TYPE_BUFFER)
 919                         continue;
 920
 921                 reg = (struct acpi_power_register *)obj->buffer.pointer;
 922
 923                 if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO &&
 924                     (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE))
 925                         continue;
 926
 927                 /* There should be an easy way to extract an integer... */
 928                 obj = &(element->package.elements[1]);
 929                 if (obj->type != ACPI_TYPE_INTEGER)
 930                         continue;
 931
 932                 cx.type = obj->integer.value;
 933                 /*
 934                  * Some buggy BIOSes won't list C1 in _CST -
 935                  * Let acpi_processor_get_power_info_default() handle them later
 936                  */
 937                 if (i == 1 && cx.type != ACPI_STATE_C1)
 938                         current_count++;
 939
 940                 cx.address = reg->address;
 941                 cx.index = current_count + 1;
 942
 943                 cx.entry_method = ACPI_CSTATE_SYSTEMIO;
 944                 if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) {
 945                         if (acpi_processor_ffh_cstate_probe
 946                                         (pr->id, &cx, reg) == 0) {
 947                                 cx.entry_method = ACPI_CSTATE_FFH;
 948                         } else if (cx.type == ACPI_STATE_C1) {
 949                                 /*
 950                                  * C1 is a special case where FIXED_HARDWARE
 951                                  * can be handled in non-MWAIT way as well.
 952                                  * In that case, save this _CST entry info.
 953                                  * Otherwise, ignore this info and continue.
 954                                  */
 955                                 cx.entry_method = ACPI_CSTATE_HALT;
 956                                 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT");
 957                         } else {
 958                                 continue;
 959                         }
 960                         if (cx.type == ACPI_STATE_C1 && idle_halt) {
 961                                 /*
 962                                  * In most cases the C1 space_id obtained from
 963                                  * _CST object is FIXED_HARDWARE access mode.
 964                                  * But when the option of idle=halt is added,
 965                                  * the entry_method type should be changed from
 966                                  * CSTATE_FFH to CSTATE_HALT.
 967                                  */
 968                                 cx.entry_method = ACPI_CSTATE_HALT;
 969                                 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT");
 970                         }
 971                 } else {
 972                         snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x",
 973                                  cx.address);
 974                 }
 975
 976                 if (cx.type == ACPI_STATE_C1) {
 977                         cx.valid = 1;
 978                 }
 979
 980                 obj = &(element->package.elements[2]);
 981                 if (obj->type != ACPI_TYPE_INTEGER)
 982                         continue;
 983
 984                 cx.latency = obj->integer.value;
 985
 986                 obj = &(element->package.elements[3]);
 987                 if (obj->type != ACPI_TYPE_INTEGER)
 988                         continue;
 989
 990                 cx.power = obj->integer.value;
 991
 992                 current_count++;
 993                 memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx));
 994
 995                 /*
 996                  * We support total ACPI_PROCESSOR_MAX_POWER - 1
 997                  * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1)
 998                  */
 999                 if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) {
1000                         printk(KERN_WARNING
1001                                "Limiting number of power states to max (%d)\n",
1002                                ACPI_PROCESSOR_MAX_POWER);
1003                         printk(KERN_WARNING
1004                                "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n");
1005                         break;
1006                 }
1007         }
1008
1009         ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n",
1010                           current_count));
1011
1012         /* Validate number of power states discovered */
1013         if (current_count < 2)
1014                 status = -EFAULT;
1015
1016       end:
1017         kfree(buffer.pointer);
1018
1019         return status;
1020 }
1021
1022 static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx)
1023 {
1024
1025         if (!cx->address)
1026                 return;
1027
1028         /*
1029          * C2 latency must be less than or equal to 100
1030          * microseconds.
1031          */
1032         else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) {
1033                 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1034                                   "latency too large [%d]\n", cx->latency));
1035                 return;
1036         }
1037
1038         /*
1039          * Otherwise we've met all of our C2 requirements.
1040          * Normalize the C2 latency to expidite policy
1041          */
1042         cx->valid = 1;
1043
1044 #ifndef CONFIG_CPU_IDLE
1045         cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
1046 #else
1047         cx->latency_ticks = cx->latency;
1048 #endif
1049
1050         return;
1051 }
1052
1053 static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
1054                                            struct acpi_processor_cx *cx)
1055 {
1056         static int bm_check_flag;
1057
1058
1059         if (!cx->address)
1060                 return;
1061
1062         /*
1063          * C3 latency must be less than or equal to 1000
1064          * microseconds.
1065          */
1066         else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) {
1067                 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1068                                   "latency too large [%d]\n", cx->latency));
1069                 return;
1070         }
1071
1072         /*
1073          * PIIX4 Erratum #18: We don't support C3 when Type-F (fast)
1074          * DMA transfers are used by any ISA device to avoid livelock.
1075          * Note that we could disable Type-F DMA (as recommended by
1076          * the erratum), but this is known to disrupt certain ISA
1077          * devices thus we take the conservative approach.
1078          */
1079         else if (errata.piix4.fdma) {
1080                 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1081                                   "C3 not supported on PIIX4 with Type-F DMA\n"));
1082                 return;
1083         }
1084
1085         /* All the logic here assumes flags.bm_check is same across all CPUs */
1086         if (!bm_check_flag) {
1087                 /* Determine whether bm_check is needed based on CPU  */
1088                 acpi_processor_power_init_bm_check(&(pr->flags), pr->id);
1089                 bm_check_flag = pr->flags.bm_check;
1090         } else {
1091                 pr->flags.bm_check = bm_check_flag;
1092         }
1093
1094         if (pr->flags.bm_check) {
1095                 if (!pr->flags.bm_control) {
1096                         if (pr->flags.has_cst != 1) {
1097                                 /* bus mastering control is necessary */
1098                                 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1099                                         "C3 support requires BM control\n"));
1100                                 return;
1101                         } else {
1102                                 /* Here we enter C3 without bus mastering */
1103                                 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1104                                         "C3 support without BM control\n"));
1105                         }
1106                 }
1107         } else {
1108                 /*
1109                  * WBINVD should be set in fadt, for C3 state to be
1110                  * supported on when bm_check is not required.
1111                  */
1112                 if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) {
1113                         ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1114                                           "Cache invalidation should work properly"
1115                                           " for C3 to be enabled on SMP systems\n"));
1116                         return;
1117                 }
1118                 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
1119         }
1120
1121         /*
1122          * Otherwise we've met all of our C3 requirements.
1123          * Normalize the C3 latency to expidite policy.  Enable
1124          * checking of bus mastering status (bm_check) so we can
1125          * use this in our C3 policy
1126          */
1127         cx->valid = 1;
1128
1129 #ifndef CONFIG_CPU_IDLE
1130         cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
1131 #else
1132         cx->latency_ticks = cx->latency;
1133 #endif
1134
1135         return;
1136 }
1137
1138 static int acpi_processor_power_verify(struct acpi_processor *pr)
1139 {
1140         unsigned int i;
1141         unsigned int working = 0;
1142
1143         pr->power.timer_broadcast_on_state = INT_MAX;
1144
1145         for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
1146                 struct acpi_processor_cx *cx = &pr->power.states[i];
1147
1148                 switch (cx->type) {
1149                 case ACPI_STATE_C1:
1150                         cx->valid = 1;
1151                         break;
1152
1153                 case ACPI_STATE_C2:
1154                         acpi_processor_power_verify_c2(cx);
1155                         if (cx->valid)
1156                                 acpi_timer_check_state(i, pr, cx);
1157                         break;
1158
1159                 case ACPI_STATE_C3:
1160                         acpi_processor_power_verify_c3(pr, cx);
1161                         if (cx->valid)
1162                                 acpi_timer_check_state(i, pr, cx);
1163                         break;
1164                 }
1165
1166                 if (cx->valid)
1167                         working++;
1168         }
1169
1170         acpi_propagate_timer_broadcast(pr);
1171
1172         return (working);
1173 }
1174
1175 static int acpi_processor_get_power_info(struct acpi_processor *pr)
1176 {
1177         unsigned int i;
1178         int result;
1179
1180
1181         /* NOTE: the idle thread may not be running while calling
1182          * this function */
1183
1184         /* Zero initialize all the C-states info. */
1185         memset(pr->power.states, 0, sizeof(pr->power.states));
1186
1187         result = acpi_processor_get_power_info_cst(pr);
1188         if (result == -ENODEV)
1189                 result = acpi_processor_get_power_info_fadt(pr);
1190
1191         if (result)
1192                 return result;
1193
1194         acpi_processor_get_power_info_default(pr);
1195
1196         pr->power.count = acpi_processor_power_verify(pr);
1197
1198 #ifndef CONFIG_CPU_IDLE
1199         /*
1200          * Set Default Policy
1201          * ------------------
1202          * Now that we know which states are supported, set the default
1203          * policy.  Note that this policy can be changed dynamically
1204          * (e.g. encourage deeper sleeps to conserve battery life when
1205          * not on AC).
1206          */
1207         result = acpi_processor_set_power_policy(pr);
1208         if (result)
1209                 return result;
1210 #endif
1211
1212         /*
1213          * if one state of type C2 or C3 is available, mark this
1214          * CPU as being "idle manageable"
1215          */
1216         for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
1217                 if (pr->power.states[i].valid) {
1218                         pr->power.count = i;
1219                         if (pr->power.states[i].type >= ACPI_STATE_C2)
1220                                 pr->flags.power = 1;
1221                 }
1222         }
1223
1224         return 0;
1225 }
1226
1227 static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset)
1228 {
1229         struct acpi_processor *pr = seq->private;
1230         unsigned int i;
1231
1232
1233         if (!pr)
1234                 goto end;
1235
1236         seq_printf(seq, "active state:            C%zd\n"
1237                    "max_cstate:              C%d\n"
1238                    "bus master activity:     %08x\n"
1239                    "maximum allowed latency: %d usec\n",
1240                    pr->power.state ? pr->power.state - pr->power.states : 0,
1241                    max_cstate, (unsigned)pr->power.bm_activity,
1242                    pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY));
1243
1244         seq_puts(seq, "states:\n");
1245
1246         for (i = 1; i <= pr->power.count; i++) {
1247                 seq_printf(seq, "   %cC%d:                  ",
1248                            (&pr->power.states[i] ==
1249                             pr->power.state ? '*' : ' '), i);
1250
1251                 if (!pr->power.states[i].valid) {
1252                         seq_puts(seq, "<not supported>\n");
1253                         continue;
1254                 }
1255
1256                 switch (pr->power.states[i].type) {
1257                 case ACPI_STATE_C1:
1258                         seq_printf(seq, "type[C1] ");
1259                         break;
1260                 case ACPI_STATE_C2:
1261                         seq_printf(seq, "type[C2] ");
1262                         break;
1263                 case ACPI_STATE_C3:
1264                         seq_printf(seq, "type[C3] ");
1265                         break;
1266                 default:
1267                         seq_printf(seq, "type[--] ");
1268                         break;
1269                 }
1270
1271                 if (pr->power.states[i].promotion.state)
1272                         seq_printf(seq, "promotion[C%zd] ",
1273                                    (pr->power.states[i].promotion.state -
1274                                     pr->power.states));
1275                 else
1276                         seq_puts(seq, "promotion[--] ");
1277
1278                 if (pr->power.states[i].demotion.state)
1279                         seq_printf(seq, "demotion[C%zd] ",
1280                                    (pr->power.states[i].demotion.state -
1281                                     pr->power.states));
1282                 else
1283                         seq_puts(seq, "demotion[--] ");
1284
1285                 seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n",
1286                            pr->power.states[i].latency,
1287                            pr->power.states[i].usage,
1288                            (unsigned long long)pr->power.states[i].time);
1289         }
1290
1291       end:
1292         return 0;
1293 }
1294
1295 static int acpi_processor_power_open_fs(struct inode *inode, struct file *file)
1296 {
1297         return single_open(file, acpi_processor_power_seq_show,
1298                            PDE(inode)->data);
1299 }
1300
1301 static const struct file_operations acpi_processor_power_fops = {
1302         .owner = THIS_MODULE,
1303         .open = acpi_processor_power_open_fs,
1304         .read = seq_read,
1305         .llseek = seq_lseek,
1306         .release = single_release,
1307 };
1308
1309 #ifndef CONFIG_CPU_IDLE
1310
1311 int acpi_processor_cst_has_changed(struct acpi_processor *pr)
1312 {
1313         int result = 0;
1314
1315         if (boot_option_idle_override)
1316                 return 0;
1317
1318         if (!pr)
1319                 return -EINVAL;
1320
1321         if (nocst) {
1322                 return -ENODEV;
1323         }
1324
1325         if (!pr->flags.power_setup_done)
1326                 return -ENODEV;
1327
1328         /* Fall back to the default idle loop */
1329         pm_idle = pm_idle_save;
1330         synchronize_sched();    /* Relies on interrupts forcing exit from idle. */
1331
1332         pr->flags.power = 0;
1333         result = acpi_processor_get_power_info(pr);
1334         if ((pr->flags.power == 1) && (pr->flags.power_setup_done))
1335                 pm_idle = acpi_processor_idle;
1336
1337         return result;
1338 }
1339
1340 #ifdef CONFIG_SMP
1341 static void smp_callback(void *v)
1342 {
1343         /* we already woke the CPU up, nothing more to do */
1344 }
1345
1346 /*
1347  * This function gets called when a part of the kernel has a new latency
1348  * requirement.  This means we need to get all processors out of their C-state,
1349  * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that
1350  * wakes them all right up.
1351  */
1352 static int acpi_processor_latency_notify(struct notifier_block *b,
1353                 unsigned long l, void *v)
1354 {
1355         smp_call_function(smp_callback, NULL, 1);
1356         return NOTIFY_OK;
1357 }
1358
1359 static struct notifier_block acpi_processor_latency_notifier = {
1360         .notifier_call = acpi_processor_latency_notify,
1361 };
1362
1363 #endif
1364
1365 #else /* CONFIG_CPU_IDLE */
1366
1367 /**
1368  * acpi_idle_bm_check - checks if bus master activity was detected
1369  */
1370 static int acpi_idle_bm_check(void)
1371 {
1372         u32 bm_status = 0;
1373
1374         acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
1375         if (bm_status)
1376                 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
1377         /*
1378          * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
1379          * the true state of bus mastering activity; forcing us to
1380          * manually check the BMIDEA bit of each IDE channel.
1381          */
1382         else if (errata.piix4.bmisx) {
1383                 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
1384                     || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
1385                         bm_status = 1;
1386         }
1387         return bm_status;
1388 }
1389
1390 /**
1391  * acpi_idle_update_bm_rld - updates the BM_RLD bit depending on target state
1392  * @pr: the processor
1393  * @target: the new target state
1394  */
1395 static inline void acpi_idle_update_bm_rld(struct acpi_processor *pr,
1396                                            struct acpi_processor_cx *target)
1397 {
1398         if (pr->flags.bm_rld_set && target->type != ACPI_STATE_C3) {
1399                 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
1400                 pr->flags.bm_rld_set = 0;
1401         }
1402
1403         if (!pr->flags.bm_rld_set && target->type == ACPI_STATE_C3) {
1404                 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
1405                 pr->flags.bm_rld_set = 1;
1406         }
1407 }
1408
1409 /**
1410  * acpi_idle_do_entry - a helper function that does C2 and C3 type entry
1411  * @cx: cstate data
1412  *
1413  * Caller disables interrupt before call and enables interrupt after return.
1414  */
1415 static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx)
1416 {
1417         if (cx->entry_method == ACPI_CSTATE_FFH) {
1418                 /* Call into architectural FFH based C-state */
1419                 acpi_processor_ffh_cstate_enter(cx);
1420         } else if (cx->entry_method == ACPI_CSTATE_HALT) {
1421                 acpi_safe_halt();
1422         } else {
1423                 int unused;
1424                 /* IO port based C-state */
1425                 inb(cx->address);
1426                 /* Dummy wait op - must do something useless after P_LVL2 read
1427                    because chipsets cannot guarantee that STPCLK# signal
1428                    gets asserted in time to freeze execution properly. */
1429                 unused = inl(acpi_gbl_FADT.xpm_timer_block.address);
1430         }
1431 }
1432
1433 /**
1434  * acpi_idle_enter_c1 - enters an ACPI C1 state-type
1435  * @dev: the target CPU
1436  * @state: the state data
1437  *
1438  * This is equivalent to the HALT instruction.
1439  */
1440 static int acpi_idle_enter_c1(struct cpuidle_device *dev,
1441                               struct cpuidle_state *state)
1442 {
1443         u32 t1, t2;
1444         struct acpi_processor *pr;
1445         struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1446
1447         pr = __get_cpu_var(processors);
1448
1449         if (unlikely(!pr))
1450                 return 0;
1451
1452         local_irq_disable();
1453
1454         /* Do not access any ACPI IO ports in suspend path */
1455         if (acpi_idle_suspend) {
1456                 acpi_safe_halt();
1457                 local_irq_enable();
1458                 return 0;
1459         }
1460
1461         if (pr->flags.bm_check)
1462                 acpi_idle_update_bm_rld(pr, cx);
1463
1464         t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1465         acpi_idle_do_entry(cx);
1466         t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1467
1468         local_irq_enable();
1469         cx->usage++;
1470
1471         return ticks_elapsed_in_us(t1, t2);
1472 }
1473
1474 /**
1475  * acpi_idle_enter_simple - enters an ACPI state without BM handling
1476  * @dev: the target CPU
1477  * @state: the state data
1478  */
1479 static int acpi_idle_enter_simple(struct cpuidle_device *dev,
1480                                   struct cpuidle_state *state)
1481 {
1482         struct acpi_processor *pr;
1483         struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1484         u32 t1, t2;
1485         int sleep_ticks = 0;
1486
1487         pr = __get_cpu_var(processors);
1488
1489         if (unlikely(!pr))
1490                 return 0;
1491
1492         if (acpi_idle_suspend)
1493                 return(acpi_idle_enter_c1(dev, state));
1494
1495         local_irq_disable();
1496         current_thread_info()->status &= ~TS_POLLING;
1497         /*
1498          * TS_POLLING-cleared state must be visible before we test
1499          * NEED_RESCHED:
1500          */
1501         smp_mb();
1502
1503         if (unlikely(need_resched())) {
1504                 current_thread_info()->status |= TS_POLLING;
1505                 local_irq_enable();
1506                 return 0;
1507         }
1508
1509         /*
1510          * Must be done before busmaster disable as we might need to
1511          * access HPET !
1512          */
1513         acpi_state_timer_broadcast(pr, cx, 1);
1514
1515         if (pr->flags.bm_check)
1516                 acpi_idle_update_bm_rld(pr, cx);
1517
1518         if (cx->type == ACPI_STATE_C3)
1519                 ACPI_FLUSH_CPU_CACHE();
1520
1521         t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1522         /* Tell the scheduler that we are going deep-idle: */
1523         sched_clock_idle_sleep_event();
1524         acpi_idle_do_entry(cx);
1525         t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1526
1527 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
1528         /* TSC could halt in idle, so notify users */
1529         if (tsc_halts_in_c(cx->type))
1530                 mark_tsc_unstable("TSC halts in idle");;
1531 #endif
1532         sleep_ticks = ticks_elapsed(t1, t2);
1533
1534         /* Tell the scheduler how much we idled: */
1535         sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
1536
1537         local_irq_enable();
1538         current_thread_info()->status |= TS_POLLING;
1539
1540         cx->usage++;
1541
1542         acpi_state_timer_broadcast(pr, cx, 0);
1543         cx->time += sleep_ticks;
1544         return ticks_elapsed_in_us(t1, t2);
1545 }
1546
1547 static int c3_cpu_count;
1548 static DEFINE_SPINLOCK(c3_lock);
1549
1550 /**
1551  * acpi_idle_enter_bm - enters C3 with proper BM handling
1552  * @dev: the target CPU
1553  * @state: the state data
1554  *
1555  * If BM is detected, the deepest non-C3 idle state is entered instead.
1556  */
1557 static int acpi_idle_enter_bm(struct cpuidle_device *dev,
1558                               struct cpuidle_state *state)
1559 {
1560         struct acpi_processor *pr;
1561         struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1562         u32 t1, t2;
1563         int sleep_ticks = 0;
1564
1565         pr = __get_cpu_var(processors);
1566
1567         if (unlikely(!pr))
1568                 return 0;
1569
1570         if (acpi_idle_suspend)
1571                 return(acpi_idle_enter_c1(dev, state));
1572
1573         if (acpi_idle_bm_check()) {
1574                 if (dev->safe_state) {
1575                         return dev->safe_state->enter(dev, dev->safe_state);
1576                 } else {
1577                         local_irq_disable();
1578                         acpi_safe_halt();
1579                         local_irq_enable();
1580                         return 0;
1581                 }
1582         }
1583
1584         local_irq_disable();
1585         current_thread_info()->status &= ~TS_POLLING;
1586         /*
1587          * TS_POLLING-cleared state must be visible before we test
1588          * NEED_RESCHED:
1589          */
1590         smp_mb();
1591
1592         if (unlikely(need_resched())) {
1593                 current_thread_info()->status |= TS_POLLING;
1594                 local_irq_enable();
1595                 return 0;
1596         }
1597
1598         acpi_unlazy_tlb(smp_processor_id());
1599
1600         /* Tell the scheduler that we are going deep-idle: */
1601         sched_clock_idle_sleep_event();
1602         /*
1603          * Must be done before busmaster disable as we might need to
1604          * access HPET !
1605          */
1606         acpi_state_timer_broadcast(pr, cx, 1);
1607
1608         acpi_idle_update_bm_rld(pr, cx);
1609
1610         /*
1611          * disable bus master
1612          * bm_check implies we need ARB_DIS
1613          * !bm_check implies we need cache flush
1614          * bm_control implies whether we can do ARB_DIS
1615          *
1616          * That leaves a case where bm_check is set and bm_control is
1617          * not set. In that case we cannot do much, we enter C3
1618          * without doing anything.
1619          */
1620         if (pr->flags.bm_check && pr->flags.bm_control) {
1621                 spin_lock(&c3_lock);
1622                 c3_cpu_count++;
1623                 /* Disable bus master arbitration when all CPUs are in C3 */
1624                 if (c3_cpu_count == num_online_cpus())
1625                         acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
1626                 spin_unlock(&c3_lock);
1627         } else if (!pr->flags.bm_check) {
1628                 ACPI_FLUSH_CPU_CACHE();
1629         }
1630
1631         t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1632         acpi_idle_do_entry(cx);
1633         t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1634
1635         /* Re-enable bus master arbitration */
1636         if (pr->flags.bm_check && pr->flags.bm_control) {
1637                 spin_lock(&c3_lock);
1638                 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
1639                 c3_cpu_count--;
1640                 spin_unlock(&c3_lock);
1641         }
1642
1643 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
1644         /* TSC could halt in idle, so notify users */
1645         if (tsc_halts_in_c(ACPI_STATE_C3))
1646                 mark_tsc_unstable("TSC halts in idle");
1647 #endif
1648         sleep_ticks = ticks_elapsed(t1, t2);
1649         /* Tell the scheduler how much we idled: */
1650         sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
1651
1652         local_irq_enable();
1653         current_thread_info()->status |= TS_POLLING;
1654
1655         cx->usage++;
1656
1657         acpi_state_timer_broadcast(pr, cx, 0);
1658         cx->time += sleep_ticks;
1659         return ticks_elapsed_in_us(t1, t2);
1660 }
1661
1662 struct cpuidle_driver acpi_idle_driver = {
1663         .name =         "acpi_idle",
1664         .owner =        THIS_MODULE,
1665 };
1666
1667 /**
1668  * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE
1669  * @pr: the ACPI processor
1670  */
1671 static int acpi_processor_setup_cpuidle(struct acpi_processor *pr)
1672 {
1673         int i, count = CPUIDLE_DRIVER_STATE_START;
1674         struct acpi_processor_cx *cx;
1675         struct cpuidle_state *state;
1676         struct cpuidle_device *dev = &pr->power.dev;
1677
1678         if (!pr->flags.power_setup_done)
1679                 return -EINVAL;
1680
1681         if (pr->flags.power == 0) {
1682                 return -EINVAL;
1683         }
1684
1685         dev->cpu = pr->id;
1686         for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
1687                 dev->states[i].name[0] = '\0';
1688                 dev->states[i].desc[0] = '\0';
1689         }
1690
1691         for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) {
1692                 cx = &pr->power.states[i];
1693                 state = &dev->states[count];
1694
1695                 if (!cx->valid)
1696                         continue;
1697
1698 #ifdef CONFIG_HOTPLUG_CPU
1699                 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
1700                     !pr->flags.has_cst &&
1701                     !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
1702                         continue;
1703 #endif
1704                 cpuidle_set_statedata(state, cx);
1705
1706                 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i);
1707                 strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1708                 state->exit_latency = cx->latency;
1709                 state->target_residency = cx->latency * latency_factor;
1710                 state->power_usage = cx->power;
1711
1712                 state->flags = 0;
1713                 switch (cx->type) {
1714                         case ACPI_STATE_C1:
1715                         state->flags |= CPUIDLE_FLAG_SHALLOW;
1716                         if (cx->entry_method == ACPI_CSTATE_FFH)
1717                                 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1718
1719                         state->enter = acpi_idle_enter_c1;
1720                         dev->safe_state = state;
1721                         break;
1722
1723                         case ACPI_STATE_C2:
1724                         state->flags |= CPUIDLE_FLAG_BALANCED;
1725                         state->flags |= CPUIDLE_FLAG_TIME_VALID;
1726                         state->enter = acpi_idle_enter_simple;
1727                         dev->safe_state = state;
1728                         break;
1729
1730                         case ACPI_STATE_C3:
1731                         state->flags |= CPUIDLE_FLAG_DEEP;
1732                         state->flags |= CPUIDLE_FLAG_TIME_VALID;
1733                         state->flags |= CPUIDLE_FLAG_CHECK_BM;
1734                         state->enter = pr->flags.bm_check ?
1735                                         acpi_idle_enter_bm :
1736                                         acpi_idle_enter_simple;
1737                         break;
1738                 }
1739
1740                 count++;
1741                 if (count == CPUIDLE_STATE_MAX)
1742                         break;
1743         }
1744
1745         dev->state_count = count;
1746
1747         if (!count)
1748                 return -EINVAL;
1749
1750         return 0;
1751 }
1752
1753 int acpi_processor_cst_has_changed(struct acpi_processor *pr)
1754 {
1755         int ret = 0;
1756
1757         if (boot_option_idle_override)
1758                 return 0;
1759
1760         if (!pr)
1761                 return -EINVAL;
1762
1763         if (nocst) {
1764                 return -ENODEV;
1765         }
1766
1767         if (!pr->flags.power_setup_done)
1768                 return -ENODEV;
1769
1770         cpuidle_pause_and_lock();
1771         cpuidle_disable_device(&pr->power.dev);
1772         acpi_processor_get_power_info(pr);
1773         if (pr->flags.power) {
1774                 acpi_processor_setup_cpuidle(pr);
1775                 ret = cpuidle_enable_device(&pr->power.dev);
1776         }
1777         cpuidle_resume_and_unlock();
1778
1779         return ret;
1780 }
1781
1782 #endif /* CONFIG_CPU_IDLE */
1783
1784 int __cpuinit acpi_processor_power_init(struct acpi_processor *pr,
1785                               struct acpi_device *device)
1786 {
1787         acpi_status status = 0;
1788         static int first_run;
1789         struct proc_dir_entry *entry = NULL;
1790         unsigned int i;
1791
1792         if (boot_option_idle_override)
1793                 return 0;
1794
1795         if (!first_run) {
1796                 if (idle_halt) {
1797                         /*
1798                          * When the boot option of "idle=halt" is added, halt
1799                          * is used for CPU IDLE.
1800                          * In such case C2/C3 is meaningless. So the max_cstate
1801                          * is set to one.
1802                          */
1803                         max_cstate = 1;
1804                 }
1805                 dmi_check_system(processor_power_dmi_table);
1806                 max_cstate = acpi_processor_cstate_check(max_cstate);
1807                 if (max_cstate < ACPI_C_STATES_MAX)
1808                         printk(KERN_NOTICE
1809                                "ACPI: processor limited to max C-state %d\n",
1810                                max_cstate);
1811                 first_run++;
1812 #if !defined(CONFIG_CPU_IDLE) && defined(CONFIG_SMP)
1813                 pm_qos_add_notifier(PM_QOS_CPU_DMA_LATENCY,
1814                                 &acpi_processor_latency_notifier);
1815 #endif
1816         }
1817
1818         if (!pr)
1819                 return -EINVAL;
1820
1821         if (acpi_gbl_FADT.cst_control && !nocst) {
1822                 status =
1823                     acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8);
1824                 if (ACPI_FAILURE(status)) {
1825                         ACPI_EXCEPTION((AE_INFO, status,
1826                                         "Notifying BIOS of _CST ability failed"));
1827                 }
1828         }
1829
1830         acpi_processor_get_power_info(pr);
1831         pr->flags.power_setup_done = 1;
1832
1833         /*
1834          * Install the idle handler if processor power management is supported.
1835          * Note that we use previously set idle handler will be used on
1836          * platforms that only support C1.
1837          */
1838         if (pr->flags.power) {
1839 #ifdef CONFIG_CPU_IDLE
1840                 acpi_processor_setup_cpuidle(pr);
1841                 if (cpuidle_register_device(&pr->power.dev))
1842                         return -EIO;
1843 #endif
1844
1845                 printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id);
1846                 for (i = 1; i <= pr->power.count; i++)
1847                         if (pr->power.states[i].valid)
1848                                 printk(" C%d[C%d]", i,
1849                                        pr->power.states[i].type);
1850                 printk(")\n");
1851
1852 #ifndef CONFIG_CPU_IDLE
1853                 if (pr->id == 0) {
1854                         pm_idle_save = pm_idle;
1855                         pm_idle = acpi_processor_idle;
1856                 }
1857 #endif
1858         }
1859
1860         /* 'power' [R] */
1861         entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER,
1862                                  S_IRUGO, acpi_device_dir(device),
1863                                  &acpi_processor_power_fops,
1864                                  acpi_driver_data(device));
1865         if (!entry)
1866                 return -EIO;
1867         return 0;
1868 }
1869
1870 int acpi_processor_power_exit(struct acpi_processor *pr,
1871                               struct acpi_device *device)
1872 {
1873         if (boot_option_idle_override)
1874                 return 0;
1875
1876 #ifdef CONFIG_CPU_IDLE
1877         cpuidle_unregister_device(&pr->power.dev);
1878 #endif
1879         pr->flags.power_setup_done = 0;
1880
1881         if (acpi_device_dir(device))
1882                 remove_proc_entry(ACPI_PROCESSOR_FILE_POWER,
1883                                   acpi_device_dir(device));
1884
1885 #ifndef CONFIG_CPU_IDLE
1886
1887         /* Unregister the idle handler when processor #0 is removed. */
1888         if (pr->id == 0) {
1889                 pm_idle = pm_idle_save;
1890
1891                 /*
1892                  * We are about to unload the current idle thread pm callback
1893                  * (pm_idle), Wait for all processors to update cached/local
1894                  * copies of pm_idle before proceeding.
1895                  */
1896                 cpu_idle_wait();
1897 #ifdef CONFIG_SMP
1898                 pm_qos_remove_notifier(PM_QOS_CPU_DMA_LATENCY,
1899                                 &acpi_processor_latency_notifier);
1900 #endif
1901         }
1902 #endif
1903
1904         return 0;
1905 }