1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
5 * (C) Copyright 2014, 2015 Linaro Ltd.
6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
8 * CPPC describes a few methods for controlling CPU performance using
9 * information from a per CPU table called CPC. This table is described in
10 * the ACPI v5.0+ specification. The table consists of a list of
11 * registers which may be memory mapped or hardware registers and also may
12 * include some static integer values.
14 * CPU performance is on an abstract continuous scale as against a discretized
15 * P-state scale which is tied to CPU frequency only. In brief, the basic
18 * - OS makes a CPU performance request. (Can provide min and max bounds)
20 * - Platform (such as BMC) is free to optimize request within requested bounds
21 * depending on power/thermal budgets etc.
23 * - Platform conveys its decision back to OS
25 * The communication between OS and platform occurs through another medium
26 * called (PCC) Platform Communication Channel. This is a generic mailbox like
27 * mechanism which includes doorbell semantics to indicate register updates.
28 * See drivers/mailbox/pcc.c for details on PCC.
30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
31 * above specifications.
34 #define pr_fmt(fmt) "ACPI CPPC: " fmt
36 #include <linux/delay.h>
37 #include <linux/iopoll.h>
38 #include <linux/ktime.h>
39 #include <linux/rwsem.h>
40 #include <linux/wait.h>
41 #include <linux/topology.h>
42 #include <linux/dmi.h>
43 #include <linux/units.h>
44 #include <asm/unaligned.h>
46 #include <acpi/cppc_acpi.h>
48 struct cppc_pcc_data {
49 struct pcc_mbox_chan *pcc_channel;
50 void __iomem *pcc_comm_addr;
51 bool pcc_channel_acquired;
52 unsigned int deadline_us;
53 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
55 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
56 bool platform_owns_pcc; /* Ownership of PCC subspace */
57 unsigned int pcc_write_cnt; /* Running count of PCC write commands */
60 * Lock to provide controlled access to the PCC channel.
62 * For performance critical usecases(currently cppc_set_perf)
63 * We need to take read_lock and check if channel belongs to OSPM
64 * before reading or writing to PCC subspace
65 * We need to take write_lock before transferring the channel
66 * ownership to the platform via a Doorbell
67 * This allows us to batch a number of CPPC requests if they happen
68 * to originate in about the same time
70 * For non-performance critical usecases(init)
71 * Take write_lock for all purposes which gives exclusive access
73 struct rw_semaphore pcc_lock;
75 /* Wait queue for CPUs whose requests were batched */
76 wait_queue_head_t pcc_write_wait_q;
77 ktime_t last_cmd_cmpl_time;
78 ktime_t last_mpar_reset;
83 /* Array to represent the PCC channel per subspace ID */
84 static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
85 /* The cpu_pcc_subspace_idx contains per CPU subspace ID */
86 static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
89 * The cpc_desc structure contains the ACPI register details
90 * as described in the per CPU _CPC tables. The details
91 * include the type of register (e.g. PCC, System IO, FFH etc.)
92 * and destination addresses which lets us READ/WRITE CPU performance
93 * information using the appropriate I/O methods.
95 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
97 /* pcc mapped address + header size + offset within PCC subspace */
98 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
101 /* Check if a CPC register is in PCC */
102 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
103 (cpc)->cpc_entry.reg.space_id == \
104 ACPI_ADR_SPACE_PLATFORM_COMM)
106 /* Check if a CPC register is in SystemMemory */
107 #define CPC_IN_SYSTEM_MEMORY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
108 (cpc)->cpc_entry.reg.space_id == \
109 ACPI_ADR_SPACE_SYSTEM_MEMORY)
111 /* Check if a CPC register is in SystemIo */
112 #define CPC_IN_SYSTEM_IO(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
113 (cpc)->cpc_entry.reg.space_id == \
114 ACPI_ADR_SPACE_SYSTEM_IO)
116 /* Evaluates to True if reg is a NULL register descriptor */
117 #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
118 (reg)->address == 0 && \
119 (reg)->bit_width == 0 && \
120 (reg)->bit_offset == 0 && \
121 (reg)->access_width == 0)
123 /* Evaluates to True if an optional cpc field is supported */
124 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
125 !!(cpc)->cpc_entry.int_value : \
126 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
128 * Arbitrary Retries in case the remote processor is slow to respond
129 * to PCC commands. Keeping it high enough to cover emulators where
130 * the processors run painfully slow.
132 #define NUM_RETRIES 500ULL
134 #define OVER_16BTS_MASK ~0xFFFFULL
136 #define define_one_cppc_ro(_name) \
137 static struct kobj_attribute _name = \
138 __ATTR(_name, 0444, show_##_name, NULL)
140 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
142 #define show_cppc_data(access_fn, struct_name, member_name) \
143 static ssize_t show_##member_name(struct kobject *kobj, \
144 struct kobj_attribute *attr, char *buf) \
146 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
147 struct struct_name st_name = {0}; \
150 ret = access_fn(cpc_ptr->cpu_id, &st_name); \
154 return sysfs_emit(buf, "%llu\n", \
155 (u64)st_name.member_name); \
157 define_one_cppc_ro(member_name)
159 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
160 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
161 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
162 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
163 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
164 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
166 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
167 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
169 /* Check for valid access_width, otherwise, fallback to using bit_width */
170 #define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width)
172 /* Shift and apply the mask for CPC reads/writes */
173 #define MASK_VAL(reg, val) (((val) >> (reg)->bit_offset) & \
174 GENMASK(((reg)->bit_width) - 1, 0))
176 static ssize_t show_feedback_ctrs(struct kobject *kobj,
177 struct kobj_attribute *attr, char *buf)
179 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
180 struct cppc_perf_fb_ctrs fb_ctrs = {0};
183 ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
187 return sysfs_emit(buf, "ref:%llu del:%llu\n",
188 fb_ctrs.reference, fb_ctrs.delivered);
190 define_one_cppc_ro(feedback_ctrs);
192 static struct attribute *cppc_attrs[] = {
194 &reference_perf.attr,
195 &wraparound_time.attr,
198 &lowest_nonlinear_perf.attr,
204 ATTRIBUTE_GROUPS(cppc);
206 static const struct kobj_type cppc_ktype = {
207 .sysfs_ops = &kobj_sysfs_ops,
208 .default_groups = cppc_groups,
211 static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
214 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
215 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
216 pcc_ss_data->pcc_comm_addr;
218 if (!pcc_ss_data->platform_owns_pcc)
222 * Poll PCC status register every 3us(delay_us) for maximum of
223 * deadline_us(timeout_us) until PCC command complete bit is set(cond)
225 ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
226 status & PCC_CMD_COMPLETE_MASK, 3,
227 pcc_ss_data->deadline_us);
230 pcc_ss_data->platform_owns_pcc = false;
231 if (chk_err_bit && (status & PCC_ERROR_MASK))
236 pr_err("PCC check channel failed for ss: %d. ret=%d\n",
243 * This function transfers the ownership of the PCC to the platform
244 * So it must be called while holding write_lock(pcc_lock)
246 static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
249 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
250 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
251 pcc_ss_data->pcc_comm_addr;
252 unsigned int time_delta;
255 * For CMD_WRITE we know for a fact the caller should have checked
256 * the channel before writing to PCC space
258 if (cmd == CMD_READ) {
260 * If there are pending cpc_writes, then we stole the channel
261 * before write completion, so first send a WRITE command to
264 if (pcc_ss_data->pending_pcc_write_cmd)
265 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
267 ret = check_pcc_chan(pcc_ss_id, false);
270 } else /* CMD_WRITE */
271 pcc_ss_data->pending_pcc_write_cmd = FALSE;
274 * Handle the Minimum Request Turnaround Time(MRTT)
275 * "The minimum amount of time that OSPM must wait after the completion
276 * of a command before issuing the next command, in microseconds"
278 if (pcc_ss_data->pcc_mrtt) {
279 time_delta = ktime_us_delta(ktime_get(),
280 pcc_ss_data->last_cmd_cmpl_time);
281 if (pcc_ss_data->pcc_mrtt > time_delta)
282 udelay(pcc_ss_data->pcc_mrtt - time_delta);
286 * Handle the non-zero Maximum Periodic Access Rate(MPAR)
287 * "The maximum number of periodic requests that the subspace channel can
288 * support, reported in commands per minute. 0 indicates no limitation."
290 * This parameter should be ideally zero or large enough so that it can
291 * handle maximum number of requests that all the cores in the system can
292 * collectively generate. If it is not, we will follow the spec and just
293 * not send the request to the platform after hitting the MPAR limit in
296 if (pcc_ss_data->pcc_mpar) {
297 if (pcc_ss_data->mpar_count == 0) {
298 time_delta = ktime_ms_delta(ktime_get(),
299 pcc_ss_data->last_mpar_reset);
300 if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
301 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
306 pcc_ss_data->last_mpar_reset = ktime_get();
307 pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
309 pcc_ss_data->mpar_count--;
312 /* Write to the shared comm region. */
313 writew_relaxed(cmd, &generic_comm_base->command);
315 /* Flip CMD COMPLETE bit */
316 writew_relaxed(0, &generic_comm_base->status);
318 pcc_ss_data->platform_owns_pcc = true;
321 ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);
323 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
324 pcc_ss_id, cmd, ret);
328 /* wait for completion and check for PCC error bit */
329 ret = check_pcc_chan(pcc_ss_id, true);
331 if (pcc_ss_data->pcc_mrtt)
332 pcc_ss_data->last_cmd_cmpl_time = ktime_get();
334 if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)
335 mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);
337 mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
340 if (cmd == CMD_WRITE) {
342 for_each_possible_cpu(i) {
343 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
348 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
349 desc->write_cmd_status = ret;
352 pcc_ss_data->pcc_write_cnt++;
353 wake_up_all(&pcc_ss_data->pcc_write_wait_q);
359 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
362 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
365 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
369 static struct mbox_client cppc_mbox_cl = {
370 .tx_done = cppc_chan_tx_done,
371 .knows_txdone = true,
374 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
376 int result = -EFAULT;
377 acpi_status status = AE_OK;
378 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
379 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
380 struct acpi_buffer state = {0, NULL};
381 union acpi_object *psd = NULL;
382 struct acpi_psd_package *pdomain;
384 status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
385 &buffer, ACPI_TYPE_PACKAGE);
386 if (status == AE_NOT_FOUND) /* _PSD is optional */
388 if (ACPI_FAILURE(status))
391 psd = buffer.pointer;
392 if (!psd || psd->package.count != 1) {
393 pr_debug("Invalid _PSD data\n");
397 pdomain = &(cpc_ptr->domain_info);
399 state.length = sizeof(struct acpi_psd_package);
400 state.pointer = pdomain;
402 status = acpi_extract_package(&(psd->package.elements[0]),
404 if (ACPI_FAILURE(status)) {
405 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
409 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
410 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
414 if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
415 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
419 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
420 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
421 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
422 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
428 kfree(buffer.pointer);
432 bool acpi_cpc_valid(void)
434 struct cpc_desc *cpc_ptr;
440 for_each_present_cpu(cpu) {
441 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
448 EXPORT_SYMBOL_GPL(acpi_cpc_valid);
450 bool cppc_allow_fast_switch(void)
452 struct cpc_register_resource *desired_reg;
453 struct cpc_desc *cpc_ptr;
456 for_each_possible_cpu(cpu) {
457 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
458 desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF];
459 if (!CPC_IN_SYSTEM_MEMORY(desired_reg) &&
460 !CPC_IN_SYSTEM_IO(desired_reg))
466 EXPORT_SYMBOL_GPL(cppc_allow_fast_switch);
469 * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
470 * @cpu: Find all CPUs that share a domain with cpu.
471 * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
473 * Return: 0 for success or negative value for err.
475 int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
477 struct cpc_desc *cpc_ptr, *match_cpc_ptr;
478 struct acpi_psd_package *match_pdomain;
479 struct acpi_psd_package *pdomain;
483 * Now that we have _PSD data from all CPUs, let's setup P-state
486 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
490 pdomain = &(cpc_ptr->domain_info);
491 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
492 if (pdomain->num_processors <= 1)
495 /* Validate the Domain info */
496 count_target = pdomain->num_processors;
497 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
498 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
499 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
500 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
501 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
502 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
504 for_each_possible_cpu(i) {
508 match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
512 match_pdomain = &(match_cpc_ptr->domain_info);
513 if (match_pdomain->domain != pdomain->domain)
516 /* Here i and cpu are in the same domain */
517 if (match_pdomain->num_processors != count_target)
520 if (pdomain->coord_type != match_pdomain->coord_type)
523 cpumask_set_cpu(i, cpu_data->shared_cpu_map);
529 /* Assume no coordination on any error parsing domain info */
530 cpumask_clear(cpu_data->shared_cpu_map);
531 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
532 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
536 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
538 static int register_pcc_channel(int pcc_ss_idx)
540 struct pcc_mbox_chan *pcc_chan;
543 if (pcc_ss_idx >= 0) {
544 pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
546 if (IS_ERR(pcc_chan)) {
547 pr_err("Failed to find PCC channel for subspace %d\n",
552 pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
554 * cppc_ss->latency is just a Nominal value. In reality
555 * the remote processor could be much slower to reply.
556 * So add an arbitrary amount of wait on top of Nominal.
558 usecs_lat = NUM_RETRIES * pcc_chan->latency;
559 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
560 pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
561 pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
562 pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
564 pcc_data[pcc_ss_idx]->pcc_comm_addr =
565 acpi_os_ioremap(pcc_chan->shmem_base_addr,
566 pcc_chan->shmem_size);
567 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
568 pr_err("Failed to ioremap PCC comm region mem for %d\n",
573 /* Set flag so that we don't come here for each CPU. */
574 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
581 * cpc_ffh_supported() - check if FFH reading supported
583 * Check if the architecture has support for functional fixed hardware
584 * read/write capability.
586 * Return: true for supported, false for not supported
588 bool __weak cpc_ffh_supported(void)
594 * cpc_supported_by_cpu() - check if CPPC is supported by CPU
596 * Check if the architectural support for CPPC is present even
597 * if the _OSC hasn't prescribed it
599 * Return: true for supported, false for not supported
601 bool __weak cpc_supported_by_cpu(void)
607 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
608 * @pcc_ss_id: PCC Subspace index as in the PCC client ACPI package.
610 * Check and allocate the cppc_pcc_data memory.
611 * In some processor configurations it is possible that same subspace
612 * is shared between multiple CPUs. This is seen especially in CPUs
613 * with hardware multi-threading support.
615 * Return: 0 for success, errno for failure
617 static int pcc_data_alloc(int pcc_ss_id)
619 if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
622 if (pcc_data[pcc_ss_id]) {
623 pcc_data[pcc_ss_id]->refcount++;
625 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
627 if (!pcc_data[pcc_ss_id])
629 pcc_data[pcc_ss_id]->refcount++;
636 * An example CPC table looks like the following.
638 * Name (_CPC, Package() {
641 * ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance
642 * ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance
643 * ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance
644 * ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance
645 * ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register
646 * ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register
647 * ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)},
652 * Each Register() encodes how to access that specific register.
653 * e.g. a sample PCC entry has the following encoding:
656 * PCC, // AddressSpaceKeyword
657 * 8, // RegisterBitWidth
658 * 8, // RegisterBitOffset
659 * 0x30, // RegisterAddress
660 * 9, // AccessSize (subspace ID)
664 #ifndef arch_init_invariance_cppc
665 static inline void arch_init_invariance_cppc(void) { }
669 * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
670 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
672 * Return: 0 for success or negative value for err.
674 int acpi_cppc_processor_probe(struct acpi_processor *pr)
676 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
677 union acpi_object *out_obj, *cpc_obj;
678 struct cpc_desc *cpc_ptr;
679 struct cpc_reg *gas_t;
680 struct device *cpu_dev;
681 acpi_handle handle = pr->handle;
682 unsigned int num_ent, i, cpc_rev;
683 int pcc_subspace_id = -1;
687 if (!osc_sb_cppc2_support_acked) {
688 pr_debug("CPPC v2 _OSC not acked\n");
689 if (!cpc_supported_by_cpu()) {
690 pr_debug("CPPC is not supported by the CPU\n");
695 /* Parse the ACPI _CPC table for this CPU. */
696 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
698 if (ACPI_FAILURE(status)) {
703 out_obj = (union acpi_object *) output.pointer;
705 cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
711 /* First entry is NumEntries. */
712 cpc_obj = &out_obj->package.elements[0];
713 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
714 num_ent = cpc_obj->integer.value;
716 pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
721 pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n",
722 cpc_obj->type, pr->id);
726 /* Second entry should be revision. */
727 cpc_obj = &out_obj->package.elements[1];
728 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
729 cpc_rev = cpc_obj->integer.value;
731 pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n",
732 cpc_obj->type, pr->id);
736 if (cpc_rev < CPPC_V2_REV) {
737 pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev,
743 * Disregard _CPC if the number of entries in the return pachage is not
744 * as expected, but support future revisions being proper supersets of
745 * the v3 and only causing more entries to be returned by _CPC.
747 if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) ||
748 (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) ||
749 (cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) {
750 pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n",
754 if (cpc_rev > CPPC_V3_REV) {
755 num_ent = CPPC_V3_NUM_ENT;
756 cpc_rev = CPPC_V3_REV;
759 cpc_ptr->num_entries = num_ent;
760 cpc_ptr->version = cpc_rev;
762 /* Iterate through remaining entries in _CPC */
763 for (i = 2; i < num_ent; i++) {
764 cpc_obj = &out_obj->package.elements[i];
766 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
767 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
768 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
769 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
770 gas_t = (struct cpc_reg *)
771 cpc_obj->buffer.pointer;
774 * The PCC Subspace index is encoded inside
775 * the CPC table entries. The same PCC index
776 * will be used for all the PCC entries,
777 * so extract it only once.
779 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
780 if (pcc_subspace_id < 0) {
781 pcc_subspace_id = gas_t->access_width;
782 if (pcc_data_alloc(pcc_subspace_id))
784 } else if (pcc_subspace_id != gas_t->access_width) {
785 pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
789 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
790 if (gas_t->address) {
794 if (!osc_cpc_flexible_adr_space_confirmed) {
795 pr_debug("Flexible address space capability not supported\n");
796 if (!cpc_supported_by_cpu())
800 access_width = GET_BIT_WIDTH(gas_t) / 8;
801 addr = ioremap(gas_t->address, access_width);
804 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
806 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
807 if (gas_t->access_width < 1 || gas_t->access_width > 3) {
809 * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
810 * SystemIO doesn't implement 64-bit
813 pr_debug("Invalid access width %d for SystemIO register in _CPC\n",
814 gas_t->access_width);
817 if (gas_t->address & OVER_16BTS_MASK) {
818 /* SystemIO registers use 16-bit integer addresses */
819 pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n",
823 if (!osc_cpc_flexible_adr_space_confirmed) {
824 pr_debug("Flexible address space capability not supported\n");
825 if (!cpc_supported_by_cpu())
829 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
830 /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
831 pr_debug("Unsupported register type (%d) in _CPC\n",
837 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
838 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
840 pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n",
845 per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
848 * Initialize the remaining cpc_regs as unsupported.
849 * Example: In case FW exposes CPPC v2, the below loop will initialize
850 * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
852 for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
853 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
854 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
858 /* Store CPU Logical ID */
859 cpc_ptr->cpu_id = pr->id;
861 /* Parse PSD data for this CPU */
862 ret = acpi_get_psd(cpc_ptr, handle);
866 /* Register PCC channel once for all PCC subspace ID. */
867 if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
868 ret = register_pcc_channel(pcc_subspace_id);
872 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
873 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
876 /* Everything looks okay */
877 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
879 /* Add per logical CPU nodes for reading its feedback counters. */
880 cpu_dev = get_cpu_device(pr->id);
886 /* Plug PSD data into this CPU's CPC descriptor. */
887 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
889 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
892 per_cpu(cpc_desc_ptr, pr->id) = NULL;
893 kobject_put(&cpc_ptr->kobj);
897 arch_init_invariance_cppc();
899 kfree(output.pointer);
903 /* Free all the mapped sys mem areas for this CPU */
904 for (i = 2; i < cpc_ptr->num_entries; i++) {
905 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
913 kfree(output.pointer);
916 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
919 * acpi_cppc_processor_exit - Cleanup CPC structs.
920 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
924 void acpi_cppc_processor_exit(struct acpi_processor *pr)
926 struct cpc_desc *cpc_ptr;
929 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
931 if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
932 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
933 pcc_data[pcc_ss_id]->refcount--;
934 if (!pcc_data[pcc_ss_id]->refcount) {
935 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
936 kfree(pcc_data[pcc_ss_id]);
937 pcc_data[pcc_ss_id] = NULL;
942 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
946 /* Free all the mapped sys mem areas for this CPU */
947 for (i = 2; i < cpc_ptr->num_entries; i++) {
948 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
953 kobject_put(&cpc_ptr->kobj);
956 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
959 * cpc_read_ffh() - Read FFH register
960 * @cpunum: CPU number to read
961 * @reg: cppc register information
962 * @val: place holder for return value
964 * Read bit_width bits from a specified address and bit_offset
966 * Return: 0 for success and error code
968 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
974 * cpc_write_ffh() - Write FFH register
975 * @cpunum: CPU number to write
976 * @reg: cppc register information
977 * @val: value to write
979 * Write value of bit_width bits to a specified address and bit_offset
981 * Return: 0 for success and error code
983 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
989 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
990 * as fast as possible. We have already mapped the PCC subspace during init, so
991 * we can directly write to it.
994 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
996 void __iomem *vaddr = NULL;
998 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
999 struct cpc_reg *reg = ®_res->cpc_entry.reg;
1001 if (reg_res->type == ACPI_TYPE_INTEGER) {
1002 *val = reg_res->cpc_entry.int_value;
1007 size = GET_BIT_WIDTH(reg);
1009 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1013 status = acpi_os_read_port((acpi_io_address)reg->address,
1015 if (ACPI_FAILURE(status)) {
1016 pr_debug("Error: Failed to read SystemIO port %llx\n",
1023 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
1025 * For registers in PCC space, the register size is determined
1026 * by the bit width field; the access size is used to indicate
1027 * the PCC subspace id.
1029 size = reg->bit_width;
1030 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1032 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1033 vaddr = reg_res->sys_mem_vaddr;
1034 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1035 return cpc_read_ffh(cpu, reg, val);
1037 return acpi_os_read_memory((acpi_physical_address)reg->address,
1042 *val = readb_relaxed(vaddr);
1045 *val = readw_relaxed(vaddr);
1048 *val = readl_relaxed(vaddr);
1051 *val = readq_relaxed(vaddr);
1054 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1055 pr_debug("Error: Cannot read %u bit width from system memory: 0x%llx\n",
1056 size, reg->address);
1057 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1058 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
1064 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1065 *val = MASK_VAL(reg, *val);
1070 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
1074 void __iomem *vaddr = NULL;
1075 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1076 struct cpc_reg *reg = ®_res->cpc_entry.reg;
1078 size = GET_BIT_WIDTH(reg);
1080 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1083 status = acpi_os_write_port((acpi_io_address)reg->address,
1085 if (ACPI_FAILURE(status)) {
1086 pr_debug("Error: Failed to write SystemIO port %llx\n",
1092 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
1094 * For registers in PCC space, the register size is determined
1095 * by the bit width field; the access size is used to indicate
1096 * the PCC subspace id.
1098 size = reg->bit_width;
1099 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1101 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1102 vaddr = reg_res->sys_mem_vaddr;
1103 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1104 return cpc_write_ffh(cpu, reg, val);
1106 return acpi_os_write_memory((acpi_physical_address)reg->address,
1109 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1110 val = MASK_VAL(reg, val);
1114 writeb_relaxed(val, vaddr);
1117 writew_relaxed(val, vaddr);
1120 writel_relaxed(val, vaddr);
1123 writeq_relaxed(val, vaddr);
1126 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1127 pr_debug("Error: Cannot write %u bit width to system memory: 0x%llx\n",
1128 size, reg->address);
1129 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1130 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
1140 static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf)
1142 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1143 struct cpc_register_resource *reg;
1146 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1150 reg = &cpc_desc->cpc_regs[reg_idx];
1152 if (CPC_IN_PCC(reg)) {
1153 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1154 struct cppc_pcc_data *pcc_ss_data = NULL;
1160 pcc_ss_data = pcc_data[pcc_ss_id];
1162 down_write(&pcc_ss_data->pcc_lock);
1164 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
1165 cpc_read(cpunum, reg, perf);
1169 up_write(&pcc_ss_data->pcc_lock);
1174 cpc_read(cpunum, reg, perf);
1180 * cppc_get_desired_perf - Get the desired performance register value.
1181 * @cpunum: CPU from which to get desired performance.
1182 * @desired_perf: Return address.
1184 * Return: 0 for success, -EIO otherwise.
1186 int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
1188 return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf);
1190 EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
1193 * cppc_get_nominal_perf - Get the nominal performance register value.
1194 * @cpunum: CPU from which to get nominal performance.
1195 * @nominal_perf: Return address.
1197 * Return: 0 for success, -EIO otherwise.
1199 int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
1201 return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
1205 * cppc_get_highest_perf - Get the highest performance register value.
1206 * @cpunum: CPU from which to get highest performance.
1207 * @highest_perf: Return address.
1209 * Return: 0 for success, -EIO otherwise.
1211 int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
1213 return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf);
1215 EXPORT_SYMBOL_GPL(cppc_get_highest_perf);
1218 * cppc_get_epp_perf - Get the epp register value.
1219 * @cpunum: CPU from which to get epp preference value.
1220 * @epp_perf: Return address.
1222 * Return: 0 for success, -EIO otherwise.
1224 int cppc_get_epp_perf(int cpunum, u64 *epp_perf)
1226 return cppc_get_perf(cpunum, ENERGY_PERF, epp_perf);
1228 EXPORT_SYMBOL_GPL(cppc_get_epp_perf);
1231 * cppc_get_perf_caps - Get a CPU's performance capabilities.
1232 * @cpunum: CPU from which to get capabilities info.
1233 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1235 * Return: 0 for success with perf_caps populated else -ERRNO.
1237 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1239 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1240 struct cpc_register_resource *highest_reg, *lowest_reg,
1241 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
1242 *low_freq_reg = NULL, *nom_freq_reg = NULL;
1243 u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
1244 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1245 struct cppc_pcc_data *pcc_ss_data = NULL;
1246 int ret = 0, regs_in_pcc = 0;
1249 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1253 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1254 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1255 lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1256 nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1257 low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1258 nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1259 guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1261 /* Are any of the regs PCC ?*/
1262 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1263 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1264 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
1265 if (pcc_ss_id < 0) {
1266 pr_debug("Invalid pcc_ss_id\n");
1269 pcc_ss_data = pcc_data[pcc_ss_id];
1271 down_write(&pcc_ss_data->pcc_lock);
1272 /* Ring doorbell once to update PCC subspace */
1273 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1279 cpc_read(cpunum, highest_reg, &high);
1280 perf_caps->highest_perf = high;
1282 cpc_read(cpunum, lowest_reg, &low);
1283 perf_caps->lowest_perf = low;
1285 cpc_read(cpunum, nominal_reg, &nom);
1286 perf_caps->nominal_perf = nom;
1288 if (guaranteed_reg->type != ACPI_TYPE_BUFFER ||
1289 IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1290 perf_caps->guaranteed_perf = 0;
1292 cpc_read(cpunum, guaranteed_reg, &guaranteed);
1293 perf_caps->guaranteed_perf = guaranteed;
1296 cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1297 perf_caps->lowest_nonlinear_perf = min_nonlinear;
1299 if (!high || !low || !nom || !min_nonlinear)
1302 /* Read optional lowest and nominal frequencies if present */
1303 if (CPC_SUPPORTED(low_freq_reg))
1304 cpc_read(cpunum, low_freq_reg, &low_f);
1306 if (CPC_SUPPORTED(nom_freq_reg))
1307 cpc_read(cpunum, nom_freq_reg, &nom_f);
1309 perf_caps->lowest_freq = low_f;
1310 perf_caps->nominal_freq = nom_f;
1315 up_write(&pcc_ss_data->pcc_lock);
1318 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1321 * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region.
1323 * CPPC has flexibility about how CPU performance counters are accessed.
1324 * One of the choices is PCC regions, which can have a high access latency. This
1325 * routine allows callers of cppc_get_perf_ctrs() to know this ahead of time.
1327 * Return: true if any of the counters are in PCC regions, false otherwise
1329 bool cppc_perf_ctrs_in_pcc(void)
1333 for_each_present_cpu(cpu) {
1334 struct cpc_register_resource *ref_perf_reg;
1335 struct cpc_desc *cpc_desc;
1337 cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1339 if (CPC_IN_PCC(&cpc_desc->cpc_regs[DELIVERED_CTR]) ||
1340 CPC_IN_PCC(&cpc_desc->cpc_regs[REFERENCE_CTR]) ||
1341 CPC_IN_PCC(&cpc_desc->cpc_regs[CTR_WRAP_TIME]))
1345 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1348 * If reference perf register is not supported then we should
1349 * use the nominal perf value
1351 if (!CPC_SUPPORTED(ref_perf_reg))
1352 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1354 if (CPC_IN_PCC(ref_perf_reg))
1360 EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc);
1363 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1364 * @cpunum: CPU from which to read counters.
1365 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1367 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1369 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1371 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1372 struct cpc_register_resource *delivered_reg, *reference_reg,
1373 *ref_perf_reg, *ctr_wrap_reg;
1374 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1375 struct cppc_pcc_data *pcc_ss_data = NULL;
1376 u64 delivered, reference, ref_perf, ctr_wrap_time;
1377 int ret = 0, regs_in_pcc = 0;
1380 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1384 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1385 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1386 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1387 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1390 * If reference perf register is not supported then we should
1391 * use the nominal perf value
1393 if (!CPC_SUPPORTED(ref_perf_reg))
1394 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1396 /* Are any of the regs PCC ?*/
1397 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1398 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1399 if (pcc_ss_id < 0) {
1400 pr_debug("Invalid pcc_ss_id\n");
1403 pcc_ss_data = pcc_data[pcc_ss_id];
1404 down_write(&pcc_ss_data->pcc_lock);
1406 /* Ring doorbell once to update PCC subspace */
1407 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1413 cpc_read(cpunum, delivered_reg, &delivered);
1414 cpc_read(cpunum, reference_reg, &reference);
1415 cpc_read(cpunum, ref_perf_reg, &ref_perf);
1418 * Per spec, if ctr_wrap_time optional register is unsupported, then the
1419 * performance counters are assumed to never wrap during the lifetime of
1422 ctr_wrap_time = (u64)(~((u64)0));
1423 if (CPC_SUPPORTED(ctr_wrap_reg))
1424 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1426 if (!delivered || !reference || !ref_perf) {
1431 perf_fb_ctrs->delivered = delivered;
1432 perf_fb_ctrs->reference = reference;
1433 perf_fb_ctrs->reference_perf = ref_perf;
1434 perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1437 up_write(&pcc_ss_data->pcc_lock);
1440 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1443 * Set Energy Performance Preference Register value through
1444 * Performance Controls Interface
1446 int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
1448 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1449 struct cpc_register_resource *epp_set_reg;
1450 struct cpc_register_resource *auto_sel_reg;
1451 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1452 struct cppc_pcc_data *pcc_ss_data = NULL;
1456 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1460 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1461 epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
1463 if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) {
1464 if (pcc_ss_id < 0) {
1465 pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu);
1469 if (CPC_SUPPORTED(auto_sel_reg)) {
1470 ret = cpc_write(cpu, auto_sel_reg, enable);
1475 if (CPC_SUPPORTED(epp_set_reg)) {
1476 ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
1481 pcc_ss_data = pcc_data[pcc_ss_id];
1483 down_write(&pcc_ss_data->pcc_lock);
1484 /* after writing CPC, transfer the ownership of PCC to platform */
1485 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1486 up_write(&pcc_ss_data->pcc_lock);
1489 pr_debug("_CPC in PCC is not supported\n");
1494 EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
1497 * cppc_get_auto_sel_caps - Read autonomous selection register.
1498 * @cpunum : CPU from which to read register.
1499 * @perf_caps : struct where autonomous selection register value is updated.
1501 int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1503 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1504 struct cpc_register_resource *auto_sel_reg;
1508 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1512 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1514 if (!CPC_SUPPORTED(auto_sel_reg))
1515 pr_warn_once("Autonomous mode is not unsupported!\n");
1517 if (CPC_IN_PCC(auto_sel_reg)) {
1518 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1519 struct cppc_pcc_data *pcc_ss_data = NULL;
1525 pcc_ss_data = pcc_data[pcc_ss_id];
1527 down_write(&pcc_ss_data->pcc_lock);
1529 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
1530 cpc_read(cpunum, auto_sel_reg, &auto_sel);
1531 perf_caps->auto_sel = (bool)auto_sel;
1536 up_write(&pcc_ss_data->pcc_lock);
1543 EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps);
1546 * cppc_set_auto_sel - Write autonomous selection register.
1547 * @cpu : CPU to which to write register.
1548 * @enable : the desired value of autonomous selection resiter to be updated.
1550 int cppc_set_auto_sel(int cpu, bool enable)
1552 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1553 struct cpc_register_resource *auto_sel_reg;
1554 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1555 struct cppc_pcc_data *pcc_ss_data = NULL;
1559 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1563 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1565 if (CPC_IN_PCC(auto_sel_reg)) {
1566 if (pcc_ss_id < 0) {
1567 pr_debug("Invalid pcc_ss_id\n");
1571 if (CPC_SUPPORTED(auto_sel_reg)) {
1572 ret = cpc_write(cpu, auto_sel_reg, enable);
1577 pcc_ss_data = pcc_data[pcc_ss_id];
1579 down_write(&pcc_ss_data->pcc_lock);
1580 /* after writing CPC, transfer the ownership of PCC to platform */
1581 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1582 up_write(&pcc_ss_data->pcc_lock);
1585 pr_debug("_CPC in PCC is not supported\n");
1590 EXPORT_SYMBOL_GPL(cppc_set_auto_sel);
1593 * cppc_set_enable - Set to enable CPPC on the processor by writing the
1594 * Continuous Performance Control package EnableRegister field.
1595 * @cpu: CPU for which to enable CPPC register.
1596 * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
1598 * Return: 0 for success, -ERRNO or -EIO otherwise.
1600 int cppc_set_enable(int cpu, bool enable)
1602 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1603 struct cpc_register_resource *enable_reg;
1604 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1605 struct cppc_pcc_data *pcc_ss_data = NULL;
1609 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1613 enable_reg = &cpc_desc->cpc_regs[ENABLE];
1615 if (CPC_IN_PCC(enable_reg)) {
1620 ret = cpc_write(cpu, enable_reg, enable);
1624 pcc_ss_data = pcc_data[pcc_ss_id];
1626 down_write(&pcc_ss_data->pcc_lock);
1627 /* after writing CPC, transfer the ownership of PCC to platfrom */
1628 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1629 up_write(&pcc_ss_data->pcc_lock);
1633 return cpc_write(cpu, enable_reg, enable);
1635 EXPORT_SYMBOL_GPL(cppc_set_enable);
1638 * cppc_set_perf - Set a CPU's performance controls.
1639 * @cpu: CPU for which to set performance controls.
1640 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1642 * Return: 0 for success, -ERRNO otherwise.
1644 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1646 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1647 struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg;
1648 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1649 struct cppc_pcc_data *pcc_ss_data = NULL;
1653 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1657 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1658 min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
1659 max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
1662 * This is Phase-I where we want to write to CPC registers
1663 * -> We want all CPUs to be able to execute this phase in parallel
1665 * Since read_lock can be acquired by multiple CPUs simultaneously we
1666 * achieve that goal here
1668 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
1669 if (pcc_ss_id < 0) {
1670 pr_debug("Invalid pcc_ss_id\n");
1673 pcc_ss_data = pcc_data[pcc_ss_id];
1674 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
1675 if (pcc_ss_data->platform_owns_pcc) {
1676 ret = check_pcc_chan(pcc_ss_id, false);
1678 up_read(&pcc_ss_data->pcc_lock);
1683 * Update the pending_write to make sure a PCC CMD_READ will not
1684 * arrive and steal the channel during the switch to write lock
1686 pcc_ss_data->pending_pcc_write_cmd = true;
1687 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
1688 cpc_desc->write_cmd_status = 0;
1691 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1694 * Only write if min_perf and max_perf not zero. Some drivers pass zero
1695 * value to min and max perf, but they don't mean to set the zero value,
1696 * they just don't want to write to those registers.
1698 if (perf_ctrls->min_perf)
1699 cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
1700 if (perf_ctrls->max_perf)
1701 cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
1703 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg))
1704 up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */
1706 * This is Phase-II where we transfer the ownership of PCC to Platform
1708 * Short Summary: Basically if we think of a group of cppc_set_perf
1709 * requests that happened in short overlapping interval. The last CPU to
1710 * come out of Phase-I will enter Phase-II and ring the doorbell.
1712 * We have the following requirements for Phase-II:
1713 * 1. We want to execute Phase-II only when there are no CPUs
1714 * currently executing in Phase-I
1715 * 2. Once we start Phase-II we want to avoid all other CPUs from
1717 * 3. We want only one CPU among all those who went through Phase-I
1720 * If write_trylock fails to get the lock and doesn't transfer the
1721 * PCC ownership to the platform, then one of the following will be TRUE
1722 * 1. There is at-least one CPU in Phase-I which will later execute
1723 * write_trylock, so the CPUs in Phase-I will be responsible for
1724 * executing the Phase-II.
1725 * 2. Some other CPU has beaten this CPU to successfully execute the
1726 * write_trylock and has already acquired the write_lock. We know for a
1727 * fact it (other CPU acquiring the write_lock) couldn't have happened
1728 * before this CPU's Phase-I as we held the read_lock.
1729 * 3. Some other CPU executing pcc CMD_READ has stolen the
1730 * down_write, in which case, send_pcc_cmd will check for pending
1731 * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1732 * So this CPU can be certain that its request will be delivered
1733 * So in all cases, this CPU knows that its request will be delivered
1734 * by another CPU and can return
1736 * After getting the down_write we still need to check for
1737 * pending_pcc_write_cmd to take care of the following scenario
1738 * The thread running this code could be scheduled out between
1739 * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1740 * could have delivered the request to Platform by triggering the
1741 * doorbell and transferred the ownership of PCC to platform. So this
1742 * avoids triggering an unnecessary doorbell and more importantly before
1743 * triggering the doorbell it makes sure that the PCC channel ownership
1744 * is still with OSPM.
1745 * pending_pcc_write_cmd can also be cleared by a different CPU, if
1746 * there was a pcc CMD_READ waiting on down_write and it steals the lock
1747 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
1748 * case during a CMD_READ and if there are pending writes it delivers
1749 * the write command before servicing the read command
1751 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
1752 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
1753 /* Update only if there are pending write commands */
1754 if (pcc_ss_data->pending_pcc_write_cmd)
1755 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1756 up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */
1758 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1759 wait_event(pcc_ss_data->pcc_write_wait_q,
1760 cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
1762 /* send_pcc_cmd updates the status in case of failure */
1763 ret = cpc_desc->write_cmd_status;
1767 EXPORT_SYMBOL_GPL(cppc_set_perf);
1770 * cppc_get_transition_latency - returns frequency transition latency in ns
1771 * @cpu_num: CPU number for per_cpu().
1773 * ACPI CPPC does not explicitly specify how a platform can specify the
1774 * transition latency for performance change requests. The closest we have
1775 * is the timing information from the PCCT tables which provides the info
1776 * on the number and frequency of PCC commands the platform can handle.
1778 * If desired_reg is in the SystemMemory or SystemIo ACPI address space,
1779 * then assume there is no latency.
1781 unsigned int cppc_get_transition_latency(int cpu_num)
1784 * Expected transition latency is based on the PCCT timing values
1785 * Below are definition from ACPI spec:
1786 * pcc_nominal- Expected latency to process a command, in microseconds
1787 * pcc_mpar - The maximum number of periodic requests that the subspace
1788 * channel can support, reported in commands per minute. 0
1789 * indicates no limitation.
1790 * pcc_mrtt - The minimum amount of time that OSPM must wait after the
1791 * completion of a command before issuing the next command,
1794 unsigned int latency_ns = 0;
1795 struct cpc_desc *cpc_desc;
1796 struct cpc_register_resource *desired_reg;
1797 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
1798 struct cppc_pcc_data *pcc_ss_data;
1800 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1802 return CPUFREQ_ETERNAL;
1804 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1805 if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg))
1807 else if (!CPC_IN_PCC(desired_reg))
1808 return CPUFREQ_ETERNAL;
1811 return CPUFREQ_ETERNAL;
1813 pcc_ss_data = pcc_data[pcc_ss_id];
1814 if (pcc_ss_data->pcc_mpar)
1815 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1817 latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
1818 latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1822 EXPORT_SYMBOL_GPL(cppc_get_transition_latency);
1824 /* Minimum struct length needed for the DMI processor entry we want */
1825 #define DMI_ENTRY_PROCESSOR_MIN_LENGTH 48
1827 /* Offset in the DMI processor structure for the max frequency */
1828 #define DMI_PROCESSOR_MAX_SPEED 0x14
1830 /* Callback function used to retrieve the max frequency from DMI */
1831 static void cppc_find_dmi_mhz(const struct dmi_header *dm, void *private)
1833 const u8 *dmi_data = (const u8 *)dm;
1834 u16 *mhz = (u16 *)private;
1836 if (dm->type == DMI_ENTRY_PROCESSOR &&
1837 dm->length >= DMI_ENTRY_PROCESSOR_MIN_LENGTH) {
1838 u16 val = (u16)get_unaligned((const u16 *)
1839 (dmi_data + DMI_PROCESSOR_MAX_SPEED));
1840 *mhz = val > *mhz ? val : *mhz;
1844 /* Look up the max frequency in DMI */
1845 static u64 cppc_get_dmi_max_khz(void)
1849 dmi_walk(cppc_find_dmi_mhz, &mhz);
1852 * Real stupid fallback value, just in case there is no
1855 mhz = mhz ? mhz : 1;
1857 return KHZ_PER_MHZ * mhz;
1861 * If CPPC lowest_freq and nominal_freq registers are exposed then we can
1862 * use them to convert perf to freq and vice versa. The conversion is
1863 * extrapolated as an affine function passing by the 2 points:
1864 * - (Low perf, Low freq)
1865 * - (Nominal perf, Nominal freq)
1867 unsigned int cppc_perf_to_khz(struct cppc_perf_caps *caps, unsigned int perf)
1869 s64 retval, offset = 0;
1873 if (caps->lowest_freq && caps->nominal_freq) {
1874 mul = caps->nominal_freq - caps->lowest_freq;
1876 div = caps->nominal_perf - caps->lowest_perf;
1877 offset = caps->nominal_freq * KHZ_PER_MHZ -
1878 div64_u64(caps->nominal_perf * mul, div);
1881 max_khz = cppc_get_dmi_max_khz();
1883 div = caps->highest_perf;
1886 retval = offset + div64_u64(perf * mul, div);
1891 EXPORT_SYMBOL_GPL(cppc_perf_to_khz);
1893 unsigned int cppc_khz_to_perf(struct cppc_perf_caps *caps, unsigned int freq)
1895 s64 retval, offset = 0;
1899 if (caps->lowest_freq && caps->nominal_freq) {
1900 mul = caps->nominal_perf - caps->lowest_perf;
1901 div = caps->nominal_freq - caps->lowest_freq;
1903 * We don't need to convert to kHz for computing offset and can
1904 * directly use nominal_freq and lowest_freq as the div64_u64
1905 * will remove the frequency unit.
1907 offset = caps->nominal_perf -
1908 div64_u64(caps->nominal_freq * mul, div);
1909 /* But we need it for computing the perf level. */
1913 max_khz = cppc_get_dmi_max_khz();
1914 mul = caps->highest_perf;
1918 retval = offset + div64_u64(freq * mul, div);
1923 EXPORT_SYMBOL_GPL(cppc_khz_to_perf);