1 /*******************************************************************************
3 * Module Name: hwregs - Read/write access functions for the various ACPI
4 * control and status registers.
6 ******************************************************************************/
9 * Copyright (C) 2000 - 2016, Intel Corp.
10 * All rights reserved.
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13 * modification, are permitted provided that the following conditions
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45 #include <acpi/acpi.h>
49 #define _COMPONENT ACPI_HARDWARE
50 ACPI_MODULE_NAME("hwregs")
52 #if (!ACPI_REDUCED_HARDWARE)
53 /* Local Prototypes */
55 acpi_hw_get_access_bit_width(struct acpi_generic_address *reg,
59 acpi_hw_read_multiple(u32 *value,
60 struct acpi_generic_address *register_a,
61 struct acpi_generic_address *register_b);
64 acpi_hw_write_multiple(u32 value,
65 struct acpi_generic_address *register_a,
66 struct acpi_generic_address *register_b);
68 #endif /* !ACPI_REDUCED_HARDWARE */
70 /******************************************************************************
72 * FUNCTION: acpi_hw_get_access_bit_width
74 * PARAMETERS: reg - GAS register structure
75 * max_bit_width - Max bit_width supported (32 or 64)
79 * DESCRIPTION: Obtain optimal access bit width
81 ******************************************************************************/
84 acpi_hw_get_access_bit_width(struct acpi_generic_address *reg, u8 max_bit_width)
88 if (!reg->access_width) {
90 * Detect old register descriptors where only the bit_width field
91 * makes senses. The target address is copied to handle possible
94 ACPI_MOVE_64_TO_64(&address, ®->address);
95 if (!reg->bit_offset && reg->bit_width &&
96 ACPI_IS_POWER_OF_TWO(reg->bit_width) &&
97 ACPI_IS_ALIGNED(reg->bit_width, 8) &&
98 ACPI_IS_ALIGNED(address, reg->bit_width)) {
99 return (reg->bit_width);
101 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
104 return (max_bit_width);
108 return (1 << (reg->access_width + 2));
112 /******************************************************************************
114 * FUNCTION: acpi_hw_validate_register
116 * PARAMETERS: reg - GAS register structure
117 * max_bit_width - Max bit_width supported (32 or 64)
118 * address - Pointer to where the gas->address
123 * DESCRIPTION: Validate the contents of a GAS register. Checks the GAS
124 * pointer, Address, space_id, bit_width, and bit_offset.
126 ******************************************************************************/
129 acpi_hw_validate_register(struct acpi_generic_address *reg,
130 u8 max_bit_width, u64 *address)
135 /* Must have a valid pointer to a GAS structure */
138 return (AE_BAD_PARAMETER);
142 * Copy the target address. This handles possible alignment issues.
143 * Address must not be null. A null address also indicates an optional
144 * ACPI register that is not supported, so no error message.
146 ACPI_MOVE_64_TO_64(address, ®->address);
148 return (AE_BAD_ADDRESS);
151 /* Validate the space_ID */
153 if ((reg->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) &&
154 (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO)) {
156 "Unsupported address space: 0x%X", reg->space_id));
160 /* Validate the access_width */
162 if (reg->access_width > 4) {
164 "Unsupported register access width: 0x%X",
169 /* Validate the bit_width, convert access_width into number of bits */
171 access_width = acpi_hw_get_access_bit_width(reg, max_bit_width);
173 ACPI_ROUND_UP(reg->bit_offset + reg->bit_width, access_width);
174 if (max_bit_width < bit_width) {
175 ACPI_WARNING((AE_INFO,
176 "Requested bit width 0x%X is smaller than register bit width 0x%X",
177 max_bit_width, bit_width));
184 /******************************************************************************
186 * FUNCTION: acpi_hw_read
188 * PARAMETERS: value - Where the value is returned
189 * reg - GAS register structure
193 * DESCRIPTION: Read from either memory or IO space. This is a 32-bit max
194 * version of acpi_read, used internally since the overhead of
195 * 64-bit values is not needed.
197 * LIMITATIONS: <These limitations also apply to acpi_hw_write>
198 * space_ID must be system_memory or system_IO.
200 ******************************************************************************/
202 acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg)
213 ACPI_FUNCTION_NAME(hw_read);
215 /* Validate contents of the GAS register */
217 status = acpi_hw_validate_register(reg, 32, &address);
218 if (ACPI_FAILURE(status)) {
223 * Initialize entire 32-bit return value to zero, convert access_width
224 * into number of bits based
227 access_width = acpi_hw_get_access_bit_width(reg, 32);
228 bit_width = reg->bit_offset + reg->bit_width;
229 bit_offset = reg->bit_offset;
232 * Two address spaces supported: Memory or IO. PCI_Config is
233 * not supported here because the GAS structure is insufficient
237 if (bit_offset >= access_width) {
239 bit_offset -= access_width;
241 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
243 acpi_os_read_memory((acpi_physical_address)
248 &value64, access_width);
249 value32 = (u32)value64;
250 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
252 status = acpi_hw_read_port((acpi_io_address)
262 * Use offset style bit masks because:
263 * bit_offset < access_width/bit_width < access_width, and
264 * access_width is ensured to be less than 32-bits by
265 * acpi_hw_validate_register().
268 value32 &= ACPI_MASK_BITS_BELOW(bit_offset);
271 if (bit_width < access_width) {
272 value32 &= ACPI_MASK_BITS_ABOVE(bit_width);
277 * Use offset style bit writes because "Index * AccessWidth" is
278 * ensured to be less than 32-bits by acpi_hw_validate_register().
280 ACPI_SET_BITS(value, index * access_width,
281 ACPI_MASK_BITS_ABOVE_32(access_width), value32);
284 bit_width > access_width ? access_width : bit_width;
288 ACPI_DEBUG_PRINT((ACPI_DB_IO,
289 "Read: %8.8X width %2d from %8.8X%8.8X (%s)\n",
290 *value, access_width, ACPI_FORMAT_UINT64(address),
291 acpi_ut_get_region_name(reg->space_id)));
296 /******************************************************************************
298 * FUNCTION: acpi_hw_write
300 * PARAMETERS: value - Value to be written
301 * reg - GAS register structure
305 * DESCRIPTION: Write to either memory or IO space. This is a 32-bit max
306 * version of acpi_write, used internally since the overhead of
307 * 64-bit values is not needed.
309 ******************************************************************************/
311 acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg)
316 ACPI_FUNCTION_NAME(hw_write);
318 /* Validate contents of the GAS register */
320 status = acpi_hw_validate_register(reg, 32, &address);
321 if (ACPI_FAILURE(status)) {
326 * Two address spaces supported: Memory or IO. PCI_Config is
327 * not supported here because the GAS structure is insufficient
329 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
330 status = acpi_os_write_memory((acpi_physical_address)
333 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
335 status = acpi_hw_write_port((acpi_io_address)
336 address, value, reg->bit_width);
339 ACPI_DEBUG_PRINT((ACPI_DB_IO,
340 "Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n",
341 value, reg->bit_width, ACPI_FORMAT_UINT64(address),
342 acpi_ut_get_region_name(reg->space_id)));
347 #if (!ACPI_REDUCED_HARDWARE)
348 /*******************************************************************************
350 * FUNCTION: acpi_hw_clear_acpi_status
356 * DESCRIPTION: Clears all fixed and general purpose status bits
358 ******************************************************************************/
360 acpi_status acpi_hw_clear_acpi_status(void)
363 acpi_cpu_flags lock_flags = 0;
365 ACPI_FUNCTION_TRACE(hw_clear_acpi_status);
367 ACPI_DEBUG_PRINT((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n",
368 ACPI_BITMASK_ALL_FIXED_STATUS,
369 ACPI_FORMAT_UINT64(acpi_gbl_xpm1a_status.address)));
371 lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock);
373 /* Clear the fixed events in PM1 A/B */
375 status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS,
376 ACPI_BITMASK_ALL_FIXED_STATUS);
378 acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags);
380 if (ACPI_FAILURE(status)) {
384 /* Clear the GPE Bits in all GPE registers in all GPE blocks */
386 status = acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block, NULL);
389 return_ACPI_STATUS(status);
392 /*******************************************************************************
394 * FUNCTION: acpi_hw_get_bit_register_info
396 * PARAMETERS: register_id - Index of ACPI Register to access
398 * RETURN: The bitmask to be used when accessing the register
400 * DESCRIPTION: Map register_id into a register bitmask.
402 ******************************************************************************/
404 struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id)
406 ACPI_FUNCTION_ENTRY();
408 if (register_id > ACPI_BITREG_MAX) {
409 ACPI_ERROR((AE_INFO, "Invalid BitRegister ID: 0x%X",
414 return (&acpi_gbl_bit_register_info[register_id]);
417 /******************************************************************************
419 * FUNCTION: acpi_hw_write_pm1_control
421 * PARAMETERS: pm1a_control - Value to be written to PM1A control
422 * pm1b_control - Value to be written to PM1B control
426 * DESCRIPTION: Write the PM1 A/B control registers. These registers are
427 * different than than the PM1 A/B status and enable registers
428 * in that different values can be written to the A/B registers.
429 * Most notably, the SLP_TYP bits can be different, as per the
430 * values returned from the _Sx predefined methods.
432 ******************************************************************************/
434 acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control)
438 ACPI_FUNCTION_TRACE(hw_write_pm1_control);
441 acpi_hw_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block);
442 if (ACPI_FAILURE(status)) {
443 return_ACPI_STATUS(status);
446 if (acpi_gbl_FADT.xpm1b_control_block.address) {
448 acpi_hw_write(pm1b_control,
449 &acpi_gbl_FADT.xpm1b_control_block);
451 return_ACPI_STATUS(status);
454 /******************************************************************************
456 * FUNCTION: acpi_hw_register_read
458 * PARAMETERS: register_id - ACPI Register ID
459 * return_value - Where the register value is returned
461 * RETURN: Status and the value read.
463 * DESCRIPTION: Read from the specified ACPI register
465 ******************************************************************************/
466 acpi_status acpi_hw_register_read(u32 register_id, u32 *return_value)
471 ACPI_FUNCTION_TRACE(hw_register_read);
473 switch (register_id) {
474 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
476 status = acpi_hw_read_multiple(&value,
477 &acpi_gbl_xpm1a_status,
478 &acpi_gbl_xpm1b_status);
481 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
483 status = acpi_hw_read_multiple(&value,
484 &acpi_gbl_xpm1a_enable,
485 &acpi_gbl_xpm1b_enable);
488 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
490 status = acpi_hw_read_multiple(&value,
494 xpm1b_control_block);
497 * Zero the write-only bits. From the ACPI specification, "Hardware
498 * Write-Only Bits": "Upon reads to registers with write-only bits,
499 * software masks out all write-only bits."
501 value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS;
504 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
507 acpi_hw_read(&value, &acpi_gbl_FADT.xpm2_control_block);
510 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
512 status = acpi_hw_read(&value, &acpi_gbl_FADT.xpm_timer_block);
515 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
518 acpi_hw_read_port(acpi_gbl_FADT.smi_command, &value, 8);
523 ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id));
524 status = AE_BAD_PARAMETER;
528 if (ACPI_SUCCESS(status)) {
529 *return_value = value;
532 return_ACPI_STATUS(status);
535 /******************************************************************************
537 * FUNCTION: acpi_hw_register_write
539 * PARAMETERS: register_id - ACPI Register ID
540 * value - The value to write
544 * DESCRIPTION: Write to the specified ACPI register
546 * NOTE: In accordance with the ACPI specification, this function automatically
547 * preserves the value of the following bits, meaning that these bits cannot be
548 * changed via this interface:
550 * PM1_CONTROL[0] = SCI_EN
555 * 1) Hardware Ignored Bits: When software writes to a register with ignored
556 * bit fields, it preserves the ignored bit fields
557 * 2) SCI_EN: OSPM always preserves this bit position
559 ******************************************************************************/
561 acpi_status acpi_hw_register_write(u32 register_id, u32 value)
566 ACPI_FUNCTION_TRACE(hw_register_write);
568 switch (register_id) {
569 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
571 * Handle the "ignored" bit in PM1 Status. According to the ACPI
572 * specification, ignored bits are to be preserved when writing.
573 * Normally, this would mean a read/modify/write sequence. However,
574 * preserving a bit in the status register is different. Writing a
575 * one clears the status, and writing a zero preserves the status.
576 * Therefore, we must always write zero to the ignored bit.
578 * This behavior is clarified in the ACPI 4.0 specification.
580 value &= ~ACPI_PM1_STATUS_PRESERVED_BITS;
582 status = acpi_hw_write_multiple(value,
583 &acpi_gbl_xpm1a_status,
584 &acpi_gbl_xpm1b_status);
587 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
589 status = acpi_hw_write_multiple(value,
590 &acpi_gbl_xpm1a_enable,
591 &acpi_gbl_xpm1b_enable);
594 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
596 * Perform a read first to preserve certain bits (per ACPI spec)
597 * Note: This includes SCI_EN, we never want to change this bit
599 status = acpi_hw_read_multiple(&read_value,
603 xpm1b_control_block);
604 if (ACPI_FAILURE(status)) {
608 /* Insert the bits to be preserved */
610 ACPI_INSERT_BITS(value, ACPI_PM1_CONTROL_PRESERVED_BITS,
613 /* Now we can write the data */
615 status = acpi_hw_write_multiple(value,
619 xpm1b_control_block);
622 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
624 * For control registers, all reserved bits must be preserved,
625 * as per the ACPI spec.
628 acpi_hw_read(&read_value,
629 &acpi_gbl_FADT.xpm2_control_block);
630 if (ACPI_FAILURE(status)) {
634 /* Insert the bits to be preserved */
636 ACPI_INSERT_BITS(value, ACPI_PM2_CONTROL_PRESERVED_BITS,
640 acpi_hw_write(value, &acpi_gbl_FADT.xpm2_control_block);
643 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
645 status = acpi_hw_write(value, &acpi_gbl_FADT.xpm_timer_block);
648 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
650 /* SMI_CMD is currently always in IO space */
653 acpi_hw_write_port(acpi_gbl_FADT.smi_command, value, 8);
658 ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id));
659 status = AE_BAD_PARAMETER;
664 return_ACPI_STATUS(status);
667 /******************************************************************************
669 * FUNCTION: acpi_hw_read_multiple
671 * PARAMETERS: value - Where the register value is returned
672 * register_a - First ACPI register (required)
673 * register_b - Second ACPI register (optional)
677 * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
679 ******************************************************************************/
682 acpi_hw_read_multiple(u32 *value,
683 struct acpi_generic_address *register_a,
684 struct acpi_generic_address *register_b)
690 /* The first register is always required */
692 status = acpi_hw_read(&value_a, register_a);
693 if (ACPI_FAILURE(status)) {
697 /* Second register is optional */
699 if (register_b->address) {
700 status = acpi_hw_read(&value_b, register_b);
701 if (ACPI_FAILURE(status)) {
707 * OR the two return values together. No shifting or masking is necessary,
708 * because of how the PM1 registers are defined in the ACPI specification:
710 * "Although the bits can be split between the two register blocks (each
711 * register block has a unique pointer within the FADT), the bit positions
712 * are maintained. The register block with unimplemented bits (that is,
713 * those implemented in the other register block) always returns zeros,
714 * and writes have no side effects"
716 *value = (value_a | value_b);
720 /******************************************************************************
722 * FUNCTION: acpi_hw_write_multiple
724 * PARAMETERS: value - The value to write
725 * register_a - First ACPI register (required)
726 * register_b - Second ACPI register (optional)
730 * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
732 ******************************************************************************/
735 acpi_hw_write_multiple(u32 value,
736 struct acpi_generic_address *register_a,
737 struct acpi_generic_address *register_b)
741 /* The first register is always required */
743 status = acpi_hw_write(value, register_a);
744 if (ACPI_FAILURE(status)) {
749 * Second register is optional
751 * No bit shifting or clearing is necessary, because of how the PM1
752 * registers are defined in the ACPI specification:
754 * "Although the bits can be split between the two register blocks (each
755 * register block has a unique pointer within the FADT), the bit positions
756 * are maintained. The register block with unimplemented bits (that is,
757 * those implemented in the other register block) always returns zeros,
758 * and writes have no side effects"
760 if (register_b->address) {
761 status = acpi_hw_write(value, register_b);
767 #endif /* !ACPI_REDUCED_HARDWARE */