1 /*******************************************************************************
3 * Module Name: hwregs - Read/write access functions for the various ACPI
4 * control and status registers.
6 ******************************************************************************/
9 * Copyright (C) 2000 - 2016, Intel Corp.
10 * All rights reserved.
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13 * modification, are permitted provided that the following conditions
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24 * of any contributors may be used to endorse or promote products derived
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45 #include <acpi/acpi.h>
49 #define _COMPONENT ACPI_HARDWARE
50 ACPI_MODULE_NAME("hwregs")
52 #if (!ACPI_REDUCED_HARDWARE)
53 /* Local Prototypes */
55 acpi_hw_get_access_bit_width(struct acpi_generic_address *reg,
59 acpi_hw_read_multiple(u32 *value,
60 struct acpi_generic_address *register_a,
61 struct acpi_generic_address *register_b);
64 acpi_hw_write_multiple(u32 value,
65 struct acpi_generic_address *register_a,
66 struct acpi_generic_address *register_b);
68 #endif /* !ACPI_REDUCED_HARDWARE */
70 /******************************************************************************
72 * FUNCTION: acpi_hw_get_access_bit_width
74 * PARAMETERS: reg - GAS register structure
75 * max_bit_width - Max bit_width supported (32 or 64)
79 * DESCRIPTION: Obtain optimal access bit width
81 ******************************************************************************/
84 acpi_hw_get_access_bit_width(struct acpi_generic_address *reg, u8 max_bit_width)
86 if (!reg->access_width) {
87 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
92 * Detect old register descriptors where only the bit_width field
95 if (reg->bit_width < max_bit_width &&
96 !reg->bit_offset && reg->bit_width &&
97 ACPI_IS_POWER_OF_TWO(reg->bit_width) &&
98 ACPI_IS_ALIGNED(reg->bit_width, 8)) {
99 return (reg->bit_width);
101 return (max_bit_width);
103 return (1 << (reg->access_width + 2));
107 /******************************************************************************
109 * FUNCTION: acpi_hw_validate_register
111 * PARAMETERS: reg - GAS register structure
112 * max_bit_width - Max bit_width supported (32 or 64)
113 * address - Pointer to where the gas->address
118 * DESCRIPTION: Validate the contents of a GAS register. Checks the GAS
119 * pointer, Address, space_id, bit_width, and bit_offset.
121 ******************************************************************************/
124 acpi_hw_validate_register(struct acpi_generic_address *reg,
125 u8 max_bit_width, u64 *address)
130 /* Must have a valid pointer to a GAS structure */
133 return (AE_BAD_PARAMETER);
137 * Copy the target address. This handles possible alignment issues.
138 * Address must not be null. A null address also indicates an optional
139 * ACPI register that is not supported, so no error message.
141 ACPI_MOVE_64_TO_64(address, ®->address);
143 return (AE_BAD_ADDRESS);
146 /* Validate the space_ID */
148 if ((reg->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) &&
149 (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO)) {
151 "Unsupported address space: 0x%X", reg->space_id));
155 /* Validate the access_width */
157 if (reg->access_width > 4) {
159 "Unsupported register access width: 0x%X",
164 /* Validate the bit_width, convert access_width into number of bits */
166 access_width = acpi_hw_get_access_bit_width(reg, max_bit_width);
168 ACPI_ROUND_UP(reg->bit_offset + reg->bit_width, access_width);
169 if (max_bit_width < bit_width) {
170 ACPI_WARNING((AE_INFO,
171 "Requested bit width 0x%X is smaller than register bit width 0x%X",
172 max_bit_width, bit_width));
179 /******************************************************************************
181 * FUNCTION: acpi_hw_read
183 * PARAMETERS: value - Where the value is returned
184 * reg - GAS register structure
188 * DESCRIPTION: Read from either memory or IO space. This is a 32-bit max
189 * version of acpi_read, used internally since the overhead of
190 * 64-bit values is not needed.
192 * LIMITATIONS: <These limitations also apply to acpi_hw_write>
193 * space_ID must be system_memory or system_IO.
195 ******************************************************************************/
197 acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg)
208 ACPI_FUNCTION_NAME(hw_read);
210 /* Validate contents of the GAS register */
212 status = acpi_hw_validate_register(reg, 32, &address);
213 if (ACPI_FAILURE(status)) {
218 * Initialize entire 32-bit return value to zero, convert access_width
219 * into number of bits based
222 access_width = acpi_hw_get_access_bit_width(reg, 32);
223 bit_width = reg->bit_offset + reg->bit_width;
224 bit_offset = reg->bit_offset;
227 * Two address spaces supported: Memory or IO. PCI_Config is
228 * not supported here because the GAS structure is insufficient
232 if (bit_offset >= access_width) {
234 bit_offset -= access_width;
236 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
238 acpi_os_read_memory((acpi_physical_address)
243 &value64, access_width);
244 value32 = (u32)value64;
245 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
247 status = acpi_hw_read_port((acpi_io_address)
257 * Use offset style bit masks because:
258 * bit_offset < access_width/bit_width < access_width, and
259 * access_width is ensured to be less than 32-bits by
260 * acpi_hw_validate_register().
263 value32 &= ACPI_MASK_BITS_BELOW(bit_offset);
266 if (bit_width < access_width) {
267 value32 &= ACPI_MASK_BITS_ABOVE(bit_width);
272 * Use offset style bit writes because "Index * AccessWidth" is
273 * ensured to be less than 32-bits by acpi_hw_validate_register().
275 ACPI_SET_BITS(value, index * access_width,
276 ACPI_MASK_BITS_ABOVE_32(access_width), value32);
279 bit_width > access_width ? access_width : bit_width;
283 ACPI_DEBUG_PRINT((ACPI_DB_IO,
284 "Read: %8.8X width %2d from %8.8X%8.8X (%s)\n",
285 *value, access_width, ACPI_FORMAT_UINT64(address),
286 acpi_ut_get_region_name(reg->space_id)));
291 /******************************************************************************
293 * FUNCTION: acpi_hw_write
295 * PARAMETERS: value - Value to be written
296 * reg - GAS register structure
300 * DESCRIPTION: Write to either memory or IO space. This is a 32-bit max
301 * version of acpi_write, used internally since the overhead of
302 * 64-bit values is not needed.
304 ******************************************************************************/
306 acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg)
313 u32 new_value32, old_value32;
317 ACPI_FUNCTION_NAME(hw_write);
319 /* Validate contents of the GAS register */
321 status = acpi_hw_validate_register(reg, 32, &address);
322 if (ACPI_FAILURE(status)) {
326 /* Convert access_width into number of bits based */
328 access_width = acpi_hw_get_access_bit_width(reg, 32);
329 bit_width = reg->bit_offset + reg->bit_width;
330 bit_offset = reg->bit_offset;
333 * Two address spaces supported: Memory or IO. PCI_Config is
334 * not supported here because the GAS structure is insufficient
339 * Use offset style bit reads because "Index * AccessWidth" is
340 * ensured to be less than 32-bits by acpi_hw_validate_register().
342 new_value32 = ACPI_GET_BITS(&value, index * access_width,
343 ACPI_MASK_BITS_ABOVE_32
346 if (bit_offset >= access_width) {
347 bit_offset -= access_width;
350 * Use offset style bit masks because access_width is ensured
351 * to be less than 32-bits by acpi_hw_validate_register() and
352 * bit_offset/bit_width is less than access_width here.
355 new_value32 &= ACPI_MASK_BITS_BELOW(bit_offset);
357 if (bit_width < access_width) {
358 new_value32 &= ACPI_MASK_BITS_ABOVE(bit_width);
361 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
362 if (bit_offset || bit_width < access_width) {
364 * Read old values in order not to modify the bits that
365 * are beyond the register bit_width/bit_offset setting.
368 acpi_os_read_memory((acpi_physical_address)
375 old_value32 = (u32)value64;
378 * Use offset style bit masks because access_width is
379 * ensured to be less than 32-bits by
380 * acpi_hw_validate_register() and bit_offset/bit_width is
381 * less than access_width here.
389 if (bit_width < access_width) {
395 new_value32 |= old_value32;
398 value64 = (u64)new_value32;
400 acpi_os_write_memory((acpi_physical_address)
405 value64, access_width);
406 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
408 if (bit_offset || bit_width < access_width) {
410 * Read old values in order not to modify the bits that
411 * are beyond the register bit_width/bit_offset setting.
414 acpi_hw_read_port((acpi_io_address)
423 * Use offset style bit masks because access_width is
424 * ensured to be less than 32-bits by
425 * acpi_hw_validate_register() and bit_offset/bit_width is
426 * less than access_width here.
434 if (bit_width < access_width) {
440 new_value32 |= old_value32;
443 status = acpi_hw_write_port((acpi_io_address)
454 * Index * access_width is ensured to be less than 32-bits by
455 * acpi_hw_validate_register().
458 bit_width > access_width ? access_width : bit_width;
462 ACPI_DEBUG_PRINT((ACPI_DB_IO,
463 "Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n",
464 value, access_width, ACPI_FORMAT_UINT64(address),
465 acpi_ut_get_region_name(reg->space_id)));
470 #if (!ACPI_REDUCED_HARDWARE)
471 /*******************************************************************************
473 * FUNCTION: acpi_hw_clear_acpi_status
479 * DESCRIPTION: Clears all fixed and general purpose status bits
481 ******************************************************************************/
483 acpi_status acpi_hw_clear_acpi_status(void)
486 acpi_cpu_flags lock_flags = 0;
488 ACPI_FUNCTION_TRACE(hw_clear_acpi_status);
490 ACPI_DEBUG_PRINT((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n",
491 ACPI_BITMASK_ALL_FIXED_STATUS,
492 ACPI_FORMAT_UINT64(acpi_gbl_xpm1a_status.address)));
494 lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock);
496 /* Clear the fixed events in PM1 A/B */
498 status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS,
499 ACPI_BITMASK_ALL_FIXED_STATUS);
501 acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags);
503 if (ACPI_FAILURE(status)) {
507 /* Clear the GPE Bits in all GPE registers in all GPE blocks */
509 status = acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block, NULL);
512 return_ACPI_STATUS(status);
515 /*******************************************************************************
517 * FUNCTION: acpi_hw_get_bit_register_info
519 * PARAMETERS: register_id - Index of ACPI Register to access
521 * RETURN: The bitmask to be used when accessing the register
523 * DESCRIPTION: Map register_id into a register bitmask.
525 ******************************************************************************/
527 struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id)
529 ACPI_FUNCTION_ENTRY();
531 if (register_id > ACPI_BITREG_MAX) {
532 ACPI_ERROR((AE_INFO, "Invalid BitRegister ID: 0x%X",
537 return (&acpi_gbl_bit_register_info[register_id]);
540 /******************************************************************************
542 * FUNCTION: acpi_hw_write_pm1_control
544 * PARAMETERS: pm1a_control - Value to be written to PM1A control
545 * pm1b_control - Value to be written to PM1B control
549 * DESCRIPTION: Write the PM1 A/B control registers. These registers are
550 * different than than the PM1 A/B status and enable registers
551 * in that different values can be written to the A/B registers.
552 * Most notably, the SLP_TYP bits can be different, as per the
553 * values returned from the _Sx predefined methods.
555 ******************************************************************************/
557 acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control)
561 ACPI_FUNCTION_TRACE(hw_write_pm1_control);
564 acpi_hw_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block);
565 if (ACPI_FAILURE(status)) {
566 return_ACPI_STATUS(status);
569 if (acpi_gbl_FADT.xpm1b_control_block.address) {
571 acpi_hw_write(pm1b_control,
572 &acpi_gbl_FADT.xpm1b_control_block);
574 return_ACPI_STATUS(status);
577 /******************************************************************************
579 * FUNCTION: acpi_hw_register_read
581 * PARAMETERS: register_id - ACPI Register ID
582 * return_value - Where the register value is returned
584 * RETURN: Status and the value read.
586 * DESCRIPTION: Read from the specified ACPI register
588 ******************************************************************************/
589 acpi_status acpi_hw_register_read(u32 register_id, u32 *return_value)
594 ACPI_FUNCTION_TRACE(hw_register_read);
596 switch (register_id) {
597 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
599 status = acpi_hw_read_multiple(&value,
600 &acpi_gbl_xpm1a_status,
601 &acpi_gbl_xpm1b_status);
604 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
606 status = acpi_hw_read_multiple(&value,
607 &acpi_gbl_xpm1a_enable,
608 &acpi_gbl_xpm1b_enable);
611 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
613 status = acpi_hw_read_multiple(&value,
617 xpm1b_control_block);
620 * Zero the write-only bits. From the ACPI specification, "Hardware
621 * Write-Only Bits": "Upon reads to registers with write-only bits,
622 * software masks out all write-only bits."
624 value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS;
627 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
630 acpi_hw_read(&value, &acpi_gbl_FADT.xpm2_control_block);
633 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
635 status = acpi_hw_read(&value, &acpi_gbl_FADT.xpm_timer_block);
638 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
641 acpi_hw_read_port(acpi_gbl_FADT.smi_command, &value, 8);
646 ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id));
647 status = AE_BAD_PARAMETER;
651 if (ACPI_SUCCESS(status)) {
652 *return_value = value;
655 return_ACPI_STATUS(status);
658 /******************************************************************************
660 * FUNCTION: acpi_hw_register_write
662 * PARAMETERS: register_id - ACPI Register ID
663 * value - The value to write
667 * DESCRIPTION: Write to the specified ACPI register
669 * NOTE: In accordance with the ACPI specification, this function automatically
670 * preserves the value of the following bits, meaning that these bits cannot be
671 * changed via this interface:
673 * PM1_CONTROL[0] = SCI_EN
678 * 1) Hardware Ignored Bits: When software writes to a register with ignored
679 * bit fields, it preserves the ignored bit fields
680 * 2) SCI_EN: OSPM always preserves this bit position
682 ******************************************************************************/
684 acpi_status acpi_hw_register_write(u32 register_id, u32 value)
689 ACPI_FUNCTION_TRACE(hw_register_write);
691 switch (register_id) {
692 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
694 * Handle the "ignored" bit in PM1 Status. According to the ACPI
695 * specification, ignored bits are to be preserved when writing.
696 * Normally, this would mean a read/modify/write sequence. However,
697 * preserving a bit in the status register is different. Writing a
698 * one clears the status, and writing a zero preserves the status.
699 * Therefore, we must always write zero to the ignored bit.
701 * This behavior is clarified in the ACPI 4.0 specification.
703 value &= ~ACPI_PM1_STATUS_PRESERVED_BITS;
705 status = acpi_hw_write_multiple(value,
706 &acpi_gbl_xpm1a_status,
707 &acpi_gbl_xpm1b_status);
710 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
712 status = acpi_hw_write_multiple(value,
713 &acpi_gbl_xpm1a_enable,
714 &acpi_gbl_xpm1b_enable);
717 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
719 * Perform a read first to preserve certain bits (per ACPI spec)
720 * Note: This includes SCI_EN, we never want to change this bit
722 status = acpi_hw_read_multiple(&read_value,
726 xpm1b_control_block);
727 if (ACPI_FAILURE(status)) {
731 /* Insert the bits to be preserved */
733 ACPI_INSERT_BITS(value, ACPI_PM1_CONTROL_PRESERVED_BITS,
736 /* Now we can write the data */
738 status = acpi_hw_write_multiple(value,
742 xpm1b_control_block);
745 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
747 * For control registers, all reserved bits must be preserved,
748 * as per the ACPI spec.
751 acpi_hw_read(&read_value,
752 &acpi_gbl_FADT.xpm2_control_block);
753 if (ACPI_FAILURE(status)) {
757 /* Insert the bits to be preserved */
759 ACPI_INSERT_BITS(value, ACPI_PM2_CONTROL_PRESERVED_BITS,
763 acpi_hw_write(value, &acpi_gbl_FADT.xpm2_control_block);
766 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
768 status = acpi_hw_write(value, &acpi_gbl_FADT.xpm_timer_block);
771 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
773 /* SMI_CMD is currently always in IO space */
776 acpi_hw_write_port(acpi_gbl_FADT.smi_command, value, 8);
781 ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id));
782 status = AE_BAD_PARAMETER;
787 return_ACPI_STATUS(status);
790 /******************************************************************************
792 * FUNCTION: acpi_hw_read_multiple
794 * PARAMETERS: value - Where the register value is returned
795 * register_a - First ACPI register (required)
796 * register_b - Second ACPI register (optional)
800 * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
802 ******************************************************************************/
805 acpi_hw_read_multiple(u32 *value,
806 struct acpi_generic_address *register_a,
807 struct acpi_generic_address *register_b)
813 /* The first register is always required */
815 status = acpi_hw_read(&value_a, register_a);
816 if (ACPI_FAILURE(status)) {
820 /* Second register is optional */
822 if (register_b->address) {
823 status = acpi_hw_read(&value_b, register_b);
824 if (ACPI_FAILURE(status)) {
830 * OR the two return values together. No shifting or masking is necessary,
831 * because of how the PM1 registers are defined in the ACPI specification:
833 * "Although the bits can be split between the two register blocks (each
834 * register block has a unique pointer within the FADT), the bit positions
835 * are maintained. The register block with unimplemented bits (that is,
836 * those implemented in the other register block) always returns zeros,
837 * and writes have no side effects"
839 *value = (value_a | value_b);
843 /******************************************************************************
845 * FUNCTION: acpi_hw_write_multiple
847 * PARAMETERS: value - The value to write
848 * register_a - First ACPI register (required)
849 * register_b - Second ACPI register (optional)
853 * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
855 ******************************************************************************/
858 acpi_hw_write_multiple(u32 value,
859 struct acpi_generic_address *register_a,
860 struct acpi_generic_address *register_b)
864 /* The first register is always required */
866 status = acpi_hw_write(value, register_a);
867 if (ACPI_FAILURE(status)) {
872 * Second register is optional
874 * No bit shifting or clearing is necessary, because of how the PM1
875 * registers are defined in the ACPI specification:
877 * "Although the bits can be split between the two register blocks (each
878 * register block has a unique pointer within the FADT), the bit positions
879 * are maintained. The register block with unimplemented bits (that is,
880 * those implemented in the other register block) always returns zeros,
881 * and writes have no side effects"
883 if (register_b->address) {
884 status = acpi_hw_write(value, register_b);
890 #endif /* !ACPI_REDUCED_HARDWARE */