1 // SPDX-License-Identifier: GPL-2.0-only
3 * ACPI support for Intel Lynxpoint LPSS.
5 * Copyright (C) 2013, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
10 #include <linux/acpi.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/dmi.h>
14 #include <linux/err.h>
16 #include <linux/mutex.h>
17 #include <linux/pci.h>
18 #include <linux/platform_device.h>
19 #include <linux/platform_data/x86/clk-lpss.h>
20 #include <linux/platform_data/x86/pmc_atom.h>
21 #include <linux/pm_domain.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/pwm.h>
24 #include <linux/pxa2xx_ssp.h>
25 #include <linux/suspend.h>
26 #include <linux/delay.h>
30 #ifdef CONFIG_X86_INTEL_LPSS
32 #include <asm/cpu_device_id.h>
33 #include <asm/intel-family.h>
34 #include <asm/iosf_mbi.h>
36 #define LPSS_ADDR(desc) ((unsigned long)&desc)
38 #define LPSS_CLK_SIZE 0x04
39 #define LPSS_LTR_SIZE 0x18
41 /* Offsets relative to LPSS_PRIVATE_OFFSET */
42 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
43 #define LPSS_RESETS 0x04
44 #define LPSS_RESETS_RESET_FUNC BIT(0)
45 #define LPSS_RESETS_RESET_APB BIT(1)
46 #define LPSS_GENERAL 0x08
47 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
48 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
49 #define LPSS_SW_LTR 0x10
50 #define LPSS_AUTO_LTR 0x14
51 #define LPSS_LTR_SNOOP_REQ BIT(15)
52 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
53 #define LPSS_LTR_SNOOP_LAT_1US 0x800
54 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
55 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
56 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
57 #define LPSS_LTR_MAX_VAL 0x3FF
58 #define LPSS_TX_INT 0x20
59 #define LPSS_TX_INT_MASK BIT(1)
61 #define LPSS_PRV_REG_COUNT 9
64 #define LPSS_CLK BIT(0)
65 #define LPSS_CLK_GATE BIT(1)
66 #define LPSS_CLK_DIVIDER BIT(2)
67 #define LPSS_LTR BIT(3)
68 #define LPSS_SAVE_CTX BIT(4)
70 * For some devices the DSDT AML code for another device turns off the device
71 * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff)
72 * as ctx register values.
73 * Luckily these devices always use the same ctx register values, so we can
74 * work around this by saving the ctx registers once on activation.
76 #define LPSS_SAVE_CTX_ONCE BIT(5)
77 #define LPSS_NO_D3_DELAY BIT(6)
79 struct lpss_private_data;
81 struct lpss_device_desc {
83 const char *clk_con_id;
84 unsigned int prv_offset;
85 size_t prv_size_override;
86 const struct property_entry *properties;
87 void (*setup)(struct lpss_private_data *pdata);
88 bool resume_from_noirq;
91 static const struct lpss_device_desc lpss_dma_desc = {
95 struct lpss_private_data {
96 struct acpi_device *adev;
97 void __iomem *mmio_base;
98 resource_size_t mmio_size;
99 unsigned int fixed_clk_rate;
101 const struct lpss_device_desc *dev_desc;
102 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
105 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
106 static u32 pmc_atom_d3_mask = 0xfe000ffe;
108 /* LPSS run time quirks */
109 static unsigned int lpss_quirks;
112 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
114 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
115 * it can be powered off automatically whenever the last LPSS device goes down.
116 * In case of no power any access to the DMA controller will hang the system.
117 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
118 * well as on ASuS T100TA transformer.
120 * This quirk overrides power state of entire LPSS island to keep DMA powered
121 * on whenever we have at least one other device in use.
123 #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0)
125 /* UART Component Parameter Register */
126 #define LPSS_UART_CPR 0xF4
127 #define LPSS_UART_CPR_AFCE BIT(4)
129 static void lpss_uart_setup(struct lpss_private_data *pdata)
134 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
135 val = readl(pdata->mmio_base + offset);
136 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
138 val = readl(pdata->mmio_base + LPSS_UART_CPR);
139 if (!(val & LPSS_UART_CPR_AFCE)) {
140 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
141 val = readl(pdata->mmio_base + offset);
142 val |= LPSS_GENERAL_UART_RTS_OVRD;
143 writel(val, pdata->mmio_base + offset);
147 static void lpss_deassert_reset(struct lpss_private_data *pdata)
152 offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
153 val = readl(pdata->mmio_base + offset);
154 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
155 writel(val, pdata->mmio_base + offset);
159 * BYT PWM used for backlight control by the i915 driver on systems without
160 * the Crystal Cove PMIC.
162 static struct pwm_lookup byt_pwm_lookup[] = {
163 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
164 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
165 "pwm-lpss-platform"),
168 static void byt_pwm_setup(struct lpss_private_data *pdata)
172 /* Only call pwm_add_table for the first PWM controller */
173 if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1)
176 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
179 #define LPSS_I2C_ENABLE 0x6c
181 static void byt_i2c_setup(struct lpss_private_data *pdata)
183 acpi_handle handle = pdata->adev->handle;
184 unsigned long long shared_host = 0;
188 /* Expected to always be successfull, but better safe then sorry */
189 if (!acpi_dev_uid_to_integer(pdata->adev, &uid) && uid) {
190 /* Detect I2C bus shared with PUNIT and ignore its d3 status */
191 status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
192 if (ACPI_SUCCESS(status) && shared_host)
193 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
196 lpss_deassert_reset(pdata);
198 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
199 pdata->fixed_clk_rate = 133000000;
201 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
204 /* BSW PWM used for backlight control by the i915 driver */
205 static struct pwm_lookup bsw_pwm_lookup[] = {
206 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
207 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
208 "pwm-lpss-platform"),
211 static void bsw_pwm_setup(struct lpss_private_data *pdata)
215 /* Only call pwm_add_table for the first PWM controller */
216 if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1)
219 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
222 static const struct property_entry lpt_spi_properties[] = {
223 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP),
227 static const struct lpss_device_desc lpt_spi_dev_desc = {
228 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
231 .properties = lpt_spi_properties,
234 static const struct lpss_device_desc lpt_i2c_dev_desc = {
235 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX,
239 static struct property_entry uart_properties[] = {
240 PROPERTY_ENTRY_U32("reg-io-width", 4),
241 PROPERTY_ENTRY_U32("reg-shift", 2),
242 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
246 static const struct lpss_device_desc lpt_uart_dev_desc = {
247 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
249 .clk_con_id = "baudclk",
251 .setup = lpss_uart_setup,
252 .properties = uart_properties,
255 static const struct lpss_device_desc lpt_sdio_dev_desc = {
257 .prv_offset = 0x1000,
258 .prv_size_override = 0x1018,
261 static const struct lpss_device_desc byt_pwm_dev_desc = {
262 .flags = LPSS_SAVE_CTX,
264 .setup = byt_pwm_setup,
267 static const struct lpss_device_desc bsw_pwm_dev_desc = {
268 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
270 .setup = bsw_pwm_setup,
271 .resume_from_noirq = true,
274 static const struct lpss_device_desc bsw_pwm2_dev_desc = {
275 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
277 .resume_from_noirq = true,
280 static const struct lpss_device_desc byt_uart_dev_desc = {
281 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
282 .clk_con_id = "baudclk",
284 .setup = lpss_uart_setup,
285 .properties = uart_properties,
288 static const struct lpss_device_desc bsw_uart_dev_desc = {
289 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
291 .clk_con_id = "baudclk",
293 .setup = lpss_uart_setup,
294 .properties = uart_properties,
297 static const struct property_entry byt_spi_properties[] = {
298 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP),
302 static const struct lpss_device_desc byt_spi_dev_desc = {
303 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
305 .properties = byt_spi_properties,
308 static const struct lpss_device_desc byt_sdio_dev_desc = {
312 static const struct lpss_device_desc byt_i2c_dev_desc = {
313 .flags = LPSS_CLK | LPSS_SAVE_CTX,
315 .setup = byt_i2c_setup,
316 .resume_from_noirq = true,
319 static const struct lpss_device_desc bsw_i2c_dev_desc = {
320 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
322 .setup = byt_i2c_setup,
323 .resume_from_noirq = true,
326 static const struct property_entry bsw_spi_properties[] = {
327 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP),
331 static const struct lpss_device_desc bsw_spi_dev_desc = {
332 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
335 .setup = lpss_deassert_reset,
336 .properties = bsw_spi_properties,
339 static const struct x86_cpu_id lpss_cpu_ids[] = {
340 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
341 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
347 #define LPSS_ADDR(desc) (0UL)
349 #endif /* CONFIG_X86_INTEL_LPSS */
351 static const struct acpi_device_id acpi_lpss_device_ids[] = {
352 /* Generic LPSS devices */
353 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
355 /* Lynxpoint LPSS devices */
356 { "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) },
357 { "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) },
358 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
359 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
360 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
361 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
362 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
365 /* BayTrail LPSS devices */
366 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
367 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
368 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
369 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
370 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
374 /* Braswell LPSS devices */
375 { "80862286", LPSS_ADDR(lpss_dma_desc) },
376 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
377 { "80862289", LPSS_ADDR(bsw_pwm2_dev_desc) },
378 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
379 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
380 { "808622C0", LPSS_ADDR(lpss_dma_desc) },
381 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
383 /* Broadwell LPSS devices */
384 { "INT3430", LPSS_ADDR(lpt_spi_dev_desc) },
385 { "INT3431", LPSS_ADDR(lpt_spi_dev_desc) },
386 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
387 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
388 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
389 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
390 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
393 /* Wildcat Point LPSS devices */
394 { "INT3438", LPSS_ADDR(lpt_spi_dev_desc) },
399 #ifdef CONFIG_X86_INTEL_LPSS
401 /* LPSS main clock device. */
402 static struct platform_device *lpss_clk_dev;
404 static inline void lpt_register_clock_device(void)
406 lpss_clk_dev = platform_device_register_simple("clk-lpss-atom",
411 static int register_device_clock(struct acpi_device *adev,
412 struct lpss_private_data *pdata)
414 const struct lpss_device_desc *dev_desc = pdata->dev_desc;
415 const char *devname = dev_name(&adev->dev);
417 struct lpss_clk_data *clk_data;
418 const char *parent, *clk_name;
419 void __iomem *prv_base;
422 lpt_register_clock_device();
424 if (IS_ERR(lpss_clk_dev))
425 return PTR_ERR(lpss_clk_dev);
427 clk_data = platform_get_drvdata(lpss_clk_dev);
432 if (!pdata->mmio_base
433 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
436 parent = clk_data->name;
437 prv_base = pdata->mmio_base + dev_desc->prv_offset;
439 if (pdata->fixed_clk_rate) {
440 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
441 pdata->fixed_clk_rate);
445 if (dev_desc->flags & LPSS_CLK_GATE) {
446 clk = clk_register_gate(NULL, devname, parent, 0,
447 prv_base, 0, 0, NULL);
451 if (dev_desc->flags & LPSS_CLK_DIVIDER) {
452 /* Prevent division by zero */
453 if (!readl(prv_base))
454 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
456 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
459 clk = clk_register_fractional_divider(NULL, clk_name, parent,
460 CLK_FRAC_DIVIDER_POWER_OF_TWO_PS,
461 prv_base, 1, 15, 16, 15, 0, NULL);
464 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
469 clk = clk_register_gate(NULL, clk_name, parent,
470 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
471 prv_base, 31, 0, NULL);
480 clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
484 struct lpss_device_links {
485 const char *supplier_hid;
486 const char *supplier_uid;
487 const char *consumer_hid;
488 const char *consumer_uid;
490 const struct dmi_system_id *dep_missing_ids;
493 /* Please keep this list sorted alphabetically by vendor and model */
494 static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = {
497 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
498 DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"),
505 * The _DEP method is used to identify dependencies but instead of creating
506 * device links for every handle in _DEP, only links in the following list are
507 * created. That is necessary because, in the general case, _DEP can refer to
508 * devices that might not have drivers, or that are on different buses, or where
509 * the supplier is not enumerated until after the consumer is probed.
511 static const struct lpss_device_links lpss_device_links[] = {
512 /* CHT External sdcard slot controller depends on PMIC I2C ctrl */
513 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
514 /* CHT iGPU depends on PMIC I2C controller */
515 {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
516 /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */
517 {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME,
518 i2c1_dep_missing_dmi_ids},
519 /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */
520 {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
521 /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */
522 {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
525 static bool acpi_lpss_is_supplier(struct acpi_device *adev,
526 const struct lpss_device_links *link)
528 return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid);
531 static bool acpi_lpss_is_consumer(struct acpi_device *adev,
532 const struct lpss_device_links *link)
534 return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid);
542 static int match_hid_uid(struct device *dev, const void *data)
544 struct acpi_device *adev = ACPI_COMPANION(dev);
545 const struct hid_uid *id = data;
550 return acpi_dev_hid_uid_match(adev, id->hid, id->uid);
553 static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
557 struct hid_uid data = {
562 dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
566 return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid);
569 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)
571 struct acpi_handle_list dep_devices;
575 if (!acpi_has_method(adev->handle, "_DEP"))
578 status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
580 if (ACPI_FAILURE(status)) {
581 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
585 for (i = 0; i < dep_devices.count; i++) {
586 if (dep_devices.handles[i] == handle)
593 static void acpi_lpss_link_consumer(struct device *dev1,
594 const struct lpss_device_links *link)
598 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
602 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
603 || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))
604 device_link_add(dev2, dev1, link->flags);
609 static void acpi_lpss_link_supplier(struct device *dev1,
610 const struct lpss_device_links *link)
614 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
618 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
619 || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))
620 device_link_add(dev1, dev2, link->flags);
625 static void acpi_lpss_create_device_links(struct acpi_device *adev,
626 struct platform_device *pdev)
630 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
631 const struct lpss_device_links *link = &lpss_device_links[i];
633 if (acpi_lpss_is_supplier(adev, link))
634 acpi_lpss_link_consumer(&pdev->dev, link);
636 if (acpi_lpss_is_consumer(adev, link))
637 acpi_lpss_link_supplier(&pdev->dev, link);
641 static int acpi_lpss_create_device(struct acpi_device *adev,
642 const struct acpi_device_id *id)
644 const struct lpss_device_desc *dev_desc;
645 struct lpss_private_data *pdata;
646 struct resource_entry *rentry;
647 struct list_head resource_list;
648 struct platform_device *pdev;
651 dev_desc = (const struct lpss_device_desc *)id->driver_data;
653 pdev = acpi_create_platform_device(adev, NULL);
654 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
656 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
660 INIT_LIST_HEAD(&resource_list);
661 ret = acpi_dev_get_memory_resources(adev, &resource_list);
665 rentry = list_first_entry_or_null(&resource_list, struct resource_entry, node);
667 if (dev_desc->prv_size_override)
668 pdata->mmio_size = dev_desc->prv_size_override;
670 pdata->mmio_size = resource_size(rentry->res);
671 pdata->mmio_base = ioremap(rentry->res->start, pdata->mmio_size);
674 acpi_dev_free_resource_list(&resource_list);
676 if (!pdata->mmio_base) {
677 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
678 adev->pnp.type.platform_id = 0;
683 pdata->dev_desc = dev_desc;
686 dev_desc->setup(pdata);
688 if (dev_desc->flags & LPSS_CLK) {
689 ret = register_device_clock(adev, pdata);
695 * This works around a known issue in ACPI tables where LPSS devices
696 * have _PS0 and _PS3 without _PSC (and no power resources), so
697 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
699 acpi_device_fix_up_power(adev);
701 adev->driver_data = pdata;
702 pdev = acpi_create_platform_device(adev, dev_desc->properties);
703 if (IS_ERR_OR_NULL(pdev)) {
704 adev->driver_data = NULL;
709 acpi_lpss_create_device_links(adev, pdev);
713 /* Skip the device, but continue the namespace scan */
720 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
722 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
725 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
728 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
731 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
733 struct acpi_device *adev = ACPI_COMPANION(dev);
734 struct lpss_private_data *pdata;
741 spin_lock_irqsave(&dev->power.lock, flags);
742 if (pm_runtime_suspended(dev)) {
746 pdata = acpi_driver_data(adev);
747 if (WARN_ON(!pdata || !pdata->mmio_base)) {
751 *val = __lpss_reg_read(pdata, reg);
755 spin_unlock_irqrestore(&dev->power.lock, flags);
759 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
766 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
767 ret = lpss_reg_read(dev, reg, <r_value);
771 return sysfs_emit(buf, "%08x\n", ltr_value);
774 static ssize_t lpss_ltr_mode_show(struct device *dev,
775 struct device_attribute *attr, char *buf)
781 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode);
785 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
786 return sprintf(buf, "%s\n", outstr);
789 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
790 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
791 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
793 static struct attribute *lpss_attrs[] = {
794 &dev_attr_auto_ltr.attr,
795 &dev_attr_sw_ltr.attr,
796 &dev_attr_ltr_mode.attr,
800 static const struct attribute_group lpss_attr_group = {
805 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
807 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
808 u32 ltr_mode, ltr_val;
810 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
812 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
813 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
814 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
818 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
819 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
820 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
821 val = LPSS_LTR_MAX_VAL;
822 } else if (val > LPSS_LTR_MAX_VAL) {
823 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
824 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
826 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
829 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
830 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
831 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
832 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
838 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
840 * @pdata: pointer to the private data of the LPSS device
842 * Most LPSS devices have private registers which may loose their context when
843 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
846 static void acpi_lpss_save_ctx(struct device *dev,
847 struct lpss_private_data *pdata)
851 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
852 unsigned long offset = i * sizeof(u32);
854 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
855 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
856 pdata->prv_reg_ctx[i], offset);
861 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
863 * @pdata: pointer to the private data of the LPSS device
865 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
867 static void acpi_lpss_restore_ctx(struct device *dev,
868 struct lpss_private_data *pdata)
872 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
873 unsigned long offset = i * sizeof(u32);
875 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
876 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
877 pdata->prv_reg_ctx[i], offset);
881 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
884 * The following delay is needed or the subsequent write operations may
885 * fail. The LPSS devices are actually PCI devices and the PCI spec
886 * expects 10ms delay before the device can be accessed after D3 to D0
887 * transition. However some platforms like BSW does not need this delay.
889 unsigned int delay = 10; /* default 10ms delay */
891 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
897 static int acpi_lpss_activate(struct device *dev)
899 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
902 ret = acpi_dev_resume(dev);
906 acpi_lpss_d3_to_d0_delay(pdata);
909 * This is called only on ->probe() stage where a device is either in
910 * known state defined by BIOS or most likely powered off. Due to this
911 * we have to deassert reset line to be sure that ->probe() will
912 * recognize the device.
914 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
915 lpss_deassert_reset(pdata);
918 if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE)
919 acpi_lpss_save_ctx(dev, pdata);
925 static void acpi_lpss_dismiss(struct device *dev)
927 acpi_dev_suspend(dev, false);
930 /* IOSF SB for LPSS island */
931 #define LPSS_IOSF_UNIT_LPIOEP 0xA0
932 #define LPSS_IOSF_UNIT_LPIO1 0xAB
933 #define LPSS_IOSF_UNIT_LPIO2 0xAC
935 #define LPSS_IOSF_PMCSR 0x84
936 #define LPSS_PMCSR_D0 0
937 #define LPSS_PMCSR_D3hot 3
938 #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0)
940 #define LPSS_IOSF_GPIODEF0 0x154
941 #define LPSS_GPIODEF0_DMA1_D3 BIT(2)
942 #define LPSS_GPIODEF0_DMA2_D3 BIT(3)
943 #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2)
944 #define LPSS_GPIODEF0_DMA_LLP BIT(13)
946 static DEFINE_MUTEX(lpss_iosf_mutex);
947 static bool lpss_iosf_d3_entered = true;
949 static void lpss_iosf_enter_d3_state(void)
952 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
953 u32 value2 = LPSS_PMCSR_D3hot;
954 u32 mask2 = LPSS_PMCSR_Dx_MASK;
956 * PMC provides an information about actual status of the LPSS devices.
957 * Here we read the values related to LPSS power island, i.e. LPSS
958 * devices, excluding both LPSS DMA controllers, along with SCC domain.
960 u32 func_dis, d3_sts_0, pmc_status;
963 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
967 mutex_lock(&lpss_iosf_mutex);
969 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
974 * Get the status of entire LPSS power island per device basis.
975 * Shutdown both LPSS DMA controllers if and only if all other devices
976 * are already in D3hot.
978 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
982 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
983 LPSS_IOSF_PMCSR, value2, mask2);
985 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
986 LPSS_IOSF_PMCSR, value2, mask2);
988 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
989 LPSS_IOSF_GPIODEF0, value1, mask1);
991 lpss_iosf_d3_entered = true;
994 mutex_unlock(&lpss_iosf_mutex);
997 static void lpss_iosf_exit_d3_state(void)
999 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
1000 LPSS_GPIODEF0_DMA_LLP;
1001 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
1002 u32 value2 = LPSS_PMCSR_D0;
1003 u32 mask2 = LPSS_PMCSR_Dx_MASK;
1005 mutex_lock(&lpss_iosf_mutex);
1007 if (!lpss_iosf_d3_entered)
1010 lpss_iosf_d3_entered = false;
1012 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
1013 LPSS_IOSF_GPIODEF0, value1, mask1);
1015 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
1016 LPSS_IOSF_PMCSR, value2, mask2);
1018 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
1019 LPSS_IOSF_PMCSR, value2, mask2);
1022 mutex_unlock(&lpss_iosf_mutex);
1025 static int acpi_lpss_suspend(struct device *dev, bool wakeup)
1027 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1030 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
1031 acpi_lpss_save_ctx(dev, pdata);
1033 ret = acpi_dev_suspend(dev, wakeup);
1036 * This call must be last in the sequence, otherwise PMC will return
1037 * wrong status for devices being about to be powered off. See
1038 * lpss_iosf_enter_d3_state() for further information.
1040 if (acpi_target_system_state() == ACPI_STATE_S0 &&
1041 lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1042 lpss_iosf_enter_d3_state();
1047 static int acpi_lpss_resume(struct device *dev)
1049 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1053 * This call is kept first to be in symmetry with
1054 * acpi_lpss_runtime_suspend() one.
1056 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1057 lpss_iosf_exit_d3_state();
1059 ret = acpi_dev_resume(dev);
1063 acpi_lpss_d3_to_d0_delay(pdata);
1065 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
1066 acpi_lpss_restore_ctx(dev, pdata);
1071 #ifdef CONFIG_PM_SLEEP
1072 static int acpi_lpss_do_suspend_late(struct device *dev)
1076 if (dev_pm_skip_suspend(dev))
1079 ret = pm_generic_suspend_late(dev);
1080 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1083 static int acpi_lpss_suspend_late(struct device *dev)
1085 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1087 if (pdata->dev_desc->resume_from_noirq)
1090 return acpi_lpss_do_suspend_late(dev);
1093 static int acpi_lpss_suspend_noirq(struct device *dev)
1095 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1098 if (pdata->dev_desc->resume_from_noirq) {
1100 * The driver's ->suspend_late callback will be invoked by
1101 * acpi_lpss_do_suspend_late(), with the assumption that the
1102 * driver really wanted to run that code in ->suspend_noirq, but
1103 * it could not run after acpi_dev_suspend() and the driver
1104 * expected the latter to be called in the "late" phase.
1106 ret = acpi_lpss_do_suspend_late(dev);
1111 return acpi_subsys_suspend_noirq(dev);
1114 static int acpi_lpss_do_resume_early(struct device *dev)
1116 int ret = acpi_lpss_resume(dev);
1118 return ret ? ret : pm_generic_resume_early(dev);
1121 static int acpi_lpss_resume_early(struct device *dev)
1123 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1125 if (pdata->dev_desc->resume_from_noirq)
1128 if (dev_pm_skip_resume(dev))
1131 return acpi_lpss_do_resume_early(dev);
1134 static int acpi_lpss_resume_noirq(struct device *dev)
1136 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1139 /* Follow acpi_subsys_resume_noirq(). */
1140 if (dev_pm_skip_resume(dev))
1143 ret = pm_generic_resume_noirq(dev);
1147 if (!pdata->dev_desc->resume_from_noirq)
1151 * The driver's ->resume_early callback will be invoked by
1152 * acpi_lpss_do_resume_early(), with the assumption that the driver
1153 * really wanted to run that code in ->resume_noirq, but it could not
1154 * run before acpi_dev_resume() and the driver expected the latter to be
1155 * called in the "early" phase.
1157 return acpi_lpss_do_resume_early(dev);
1160 static int acpi_lpss_do_restore_early(struct device *dev)
1162 int ret = acpi_lpss_resume(dev);
1164 return ret ? ret : pm_generic_restore_early(dev);
1167 static int acpi_lpss_restore_early(struct device *dev)
1169 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1171 if (pdata->dev_desc->resume_from_noirq)
1174 return acpi_lpss_do_restore_early(dev);
1177 static int acpi_lpss_restore_noirq(struct device *dev)
1179 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1182 ret = pm_generic_restore_noirq(dev);
1186 if (!pdata->dev_desc->resume_from_noirq)
1189 /* This is analogous to what happens in acpi_lpss_resume_noirq(). */
1190 return acpi_lpss_do_restore_early(dev);
1193 static int acpi_lpss_do_poweroff_late(struct device *dev)
1195 int ret = pm_generic_poweroff_late(dev);
1197 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1200 static int acpi_lpss_poweroff_late(struct device *dev)
1202 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1204 if (dev_pm_skip_suspend(dev))
1207 if (pdata->dev_desc->resume_from_noirq)
1210 return acpi_lpss_do_poweroff_late(dev);
1213 static int acpi_lpss_poweroff_noirq(struct device *dev)
1215 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1217 if (dev_pm_skip_suspend(dev))
1220 if (pdata->dev_desc->resume_from_noirq) {
1221 /* This is analogous to the acpi_lpss_suspend_noirq() case. */
1222 int ret = acpi_lpss_do_poweroff_late(dev);
1228 return pm_generic_poweroff_noirq(dev);
1230 #endif /* CONFIG_PM_SLEEP */
1232 static int acpi_lpss_runtime_suspend(struct device *dev)
1234 int ret = pm_generic_runtime_suspend(dev);
1236 return ret ? ret : acpi_lpss_suspend(dev, true);
1239 static int acpi_lpss_runtime_resume(struct device *dev)
1241 int ret = acpi_lpss_resume(dev);
1243 return ret ? ret : pm_generic_runtime_resume(dev);
1245 #endif /* CONFIG_PM */
1247 static struct dev_pm_domain acpi_lpss_pm_domain = {
1249 .activate = acpi_lpss_activate,
1250 .dismiss = acpi_lpss_dismiss,
1254 #ifdef CONFIG_PM_SLEEP
1255 .prepare = acpi_subsys_prepare,
1256 .complete = acpi_subsys_complete,
1257 .suspend = acpi_subsys_suspend,
1258 .suspend_late = acpi_lpss_suspend_late,
1259 .suspend_noirq = acpi_lpss_suspend_noirq,
1260 .resume_noirq = acpi_lpss_resume_noirq,
1261 .resume_early = acpi_lpss_resume_early,
1262 .freeze = acpi_subsys_freeze,
1263 .poweroff = acpi_subsys_poweroff,
1264 .poweroff_late = acpi_lpss_poweroff_late,
1265 .poweroff_noirq = acpi_lpss_poweroff_noirq,
1266 .restore_noirq = acpi_lpss_restore_noirq,
1267 .restore_early = acpi_lpss_restore_early,
1269 .runtime_suspend = acpi_lpss_runtime_suspend,
1270 .runtime_resume = acpi_lpss_runtime_resume,
1275 static int acpi_lpss_platform_notify(struct notifier_block *nb,
1276 unsigned long action, void *data)
1278 struct platform_device *pdev = to_platform_device(data);
1279 struct lpss_private_data *pdata;
1280 struct acpi_device *adev;
1281 const struct acpi_device_id *id;
1283 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
1284 if (!id || !id->driver_data)
1287 adev = ACPI_COMPANION(&pdev->dev);
1291 pdata = acpi_driver_data(adev);
1295 if (pdata->mmio_base &&
1296 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
1297 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
1302 case BUS_NOTIFY_BIND_DRIVER:
1303 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1305 case BUS_NOTIFY_DRIVER_NOT_BOUND:
1306 case BUS_NOTIFY_UNBOUND_DRIVER:
1307 dev_pm_domain_set(&pdev->dev, NULL);
1309 case BUS_NOTIFY_ADD_DEVICE:
1310 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1311 if (pdata->dev_desc->flags & LPSS_LTR)
1312 return sysfs_create_group(&pdev->dev.kobj,
1315 case BUS_NOTIFY_DEL_DEVICE:
1316 if (pdata->dev_desc->flags & LPSS_LTR)
1317 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
1318 dev_pm_domain_set(&pdev->dev, NULL);
1327 static struct notifier_block acpi_lpss_nb = {
1328 .notifier_call = acpi_lpss_platform_notify,
1331 static void acpi_lpss_bind(struct device *dev)
1333 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1335 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
1338 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
1339 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
1341 dev_err(dev, "MMIO size insufficient to access LTR\n");
1344 static void acpi_lpss_unbind(struct device *dev)
1346 dev->power.set_latency_tolerance = NULL;
1349 static struct acpi_scan_handler lpss_handler = {
1350 .ids = acpi_lpss_device_ids,
1351 .attach = acpi_lpss_create_device,
1352 .bind = acpi_lpss_bind,
1353 .unbind = acpi_lpss_unbind,
1356 void __init acpi_lpss_init(void)
1358 const struct x86_cpu_id *id;
1361 ret = lpss_atom_clk_init();
1365 id = x86_match_cpu(lpss_cpu_ids);
1367 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
1369 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
1370 acpi_scan_add_handler(&lpss_handler);
1375 static struct acpi_scan_handler lpss_handler = {
1376 .ids = acpi_lpss_device_ids,
1379 void __init acpi_lpss_init(void)
1381 acpi_scan_add_handler(&lpss_handler);
1384 #endif /* CONFIG_X86_INTEL_LPSS */