1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2023 Intel Corporation
9 #include "ivpu_hw_40xx_reg.h"
10 #include "ivpu_hw_reg_io.h"
15 #include <linux/dmi.h>
17 #define TILE_MAX_NUM 6
18 #define TILE_MAX_MASK 0x3f
20 #define LNL_HW_ID 0x4040
22 #define SKU_TILE_SHIFT 0u
23 #define SKU_TILE_MASK 0x0000ffffu
24 #define SKU_HW_ID_SHIFT 16u
25 #define SKU_HW_ID_MASK 0xffff0000u
27 #define PLL_CONFIG_DEFAULT 0x1
28 #define PLL_CDYN_DEFAULT 0x80
29 #define PLL_EPP_DEFAULT 0x80
30 #define PLL_REF_CLK_FREQ (50 * 1000000)
31 #define PLL_RATIO_TO_FREQ(x) ((x) * PLL_REF_CLK_FREQ)
33 #define PLL_PROFILING_FREQ_DEFAULT 38400000
34 #define PLL_PROFILING_FREQ_HIGH 400000000
36 #define TIM_SAFE_ENABLE 0xf1d0dead
37 #define TIM_WATCHDOG_RESET_VALUE 0xffffffff
39 #define TIMEOUT_US (150 * USEC_PER_MSEC)
40 #define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC)
41 #define PLL_TIMEOUT_US (1500 * USEC_PER_MSEC)
42 #define IDLE_TIMEOUT_US (5 * USEC_PER_MSEC)
44 #define WEIGHTS_DEFAULT 0xf711f711u
45 #define WEIGHTS_ATS_DEFAULT 0x0000f711u
47 #define ICB_0_IRQ_MASK ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \
48 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \
49 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \
50 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \
51 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \
52 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \
53 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT)))
55 #define ICB_1_IRQ_MASK ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \
56 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \
57 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT)))
59 #define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK)
61 #define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \
62 (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR)) | \
63 (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR)) | \
64 (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR)) | \
65 (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR)) | \
66 (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR)))
68 #define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK)
69 #define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)
71 #define ITF_FIREWALL_VIOLATION_MASK ((REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \
72 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \
73 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \
74 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \
75 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \
76 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \
77 (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX)))
79 static char *ivpu_platform_to_str(u32 platform)
82 case IVPU_PLATFORM_SILICON:
83 return "IVPU_PLATFORM_SILICON";
84 case IVPU_PLATFORM_SIMICS:
85 return "IVPU_PLATFORM_SIMICS";
86 case IVPU_PLATFORM_FPGA:
87 return "IVPU_PLATFORM_FPGA";
89 return "Invalid platform";
93 static const struct dmi_system_id ivpu_dmi_platform_simulation[] = {
95 .ident = "Intel Simics",
97 DMI_MATCH(DMI_BOARD_NAME, "lnlrvp"),
98 DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
99 DMI_MATCH(DMI_BOARD_SERIAL, "123456789"),
103 .ident = "Intel Simics",
105 DMI_MATCH(DMI_BOARD_NAME, "Simics"),
111 static void ivpu_hw_read_platform(struct ivpu_device *vdev)
113 if (dmi_check_system(ivpu_dmi_platform_simulation))
114 vdev->platform = IVPU_PLATFORM_SIMICS;
116 vdev->platform = IVPU_PLATFORM_SILICON;
118 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n",
119 ivpu_platform_to_str(vdev->platform), vdev->platform);
122 static void ivpu_hw_wa_init(struct ivpu_device *vdev)
124 vdev->wa.punit_disabled = ivpu_is_fpga(vdev);
125 vdev->wa.clear_runtime_mem = false;
127 if (ivpu_hw_gen(vdev) == IVPU_HW_40XX)
128 vdev->wa.disable_clock_relinquish = true;
130 IVPU_PRINT_WA(punit_disabled);
131 IVPU_PRINT_WA(clear_runtime_mem);
132 IVPU_PRINT_WA(disable_clock_relinquish);
135 static void ivpu_hw_timeouts_init(struct ivpu_device *vdev)
137 if (ivpu_is_fpga(vdev)) {
138 vdev->timeout.boot = 100000;
139 vdev->timeout.jsm = 50000;
140 vdev->timeout.tdr = 2000000;
141 vdev->timeout.reschedule_suspend = 1000;
142 vdev->timeout.autosuspend = -1;
143 vdev->timeout.d0i3_entry_msg = 500;
144 } else if (ivpu_is_simics(vdev)) {
145 vdev->timeout.boot = 50;
146 vdev->timeout.jsm = 500;
147 vdev->timeout.tdr = 10000;
148 vdev->timeout.reschedule_suspend = 10;
149 vdev->timeout.autosuspend = -1;
150 vdev->timeout.d0i3_entry_msg = 100;
152 vdev->timeout.boot = 1000;
153 vdev->timeout.jsm = 500;
154 vdev->timeout.tdr = 2000;
155 vdev->timeout.reschedule_suspend = 10;
156 vdev->timeout.autosuspend = 10;
157 vdev->timeout.d0i3_entry_msg = 5;
161 static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev)
163 return REGB_POLL_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
166 static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ratio,
167 u16 target_ratio, u16 epp, u16 config, u16 cdyn)
172 ret = ivpu_pll_wait_for_cmd_send(vdev);
174 ivpu_err(vdev, "Failed to sync before WP request: %d\n", ret);
178 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0);
179 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val);
180 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val);
181 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, val);
183 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1);
184 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val);
185 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, epp, val);
186 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, val);
188 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2);
189 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val);
190 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CDYN, cdyn, val);
191 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, val);
193 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_CMD);
194 val = REG_SET_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, val);
195 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_CMD, val);
197 ret = ivpu_pll_wait_for_cmd_send(vdev);
199 ivpu_err(vdev, "Failed to sync after WP request: %d\n", ret);
204 static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev)
206 return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, READY, 1, PLL_TIMEOUT_US);
209 static int ivpu_wait_for_clock_own_resource_ack(struct ivpu_device *vdev)
211 if (ivpu_is_simics(vdev))
214 return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, CLOCK_RESOURCE_OWN_ACK, 1, TIMEOUT_US);
217 static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev)
219 struct ivpu_hw_info *hw = vdev->hw;
220 u8 fuse_min_ratio, fuse_pn_ratio, fuse_max_ratio;
221 u32 fmin_fuse, fmax_fuse;
223 fmin_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMIN_FUSE);
224 fuse_min_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMIN_FUSE, MIN_RATIO, fmin_fuse);
225 fuse_pn_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMIN_FUSE, PN_RATIO, fmin_fuse);
227 fmax_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMAX_FUSE);
228 fuse_max_ratio = REG_GET_FLD(VPU_40XX_BUTTRESS_FMAX_FUSE, MAX_RATIO, fmax_fuse);
230 hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, fuse_min_ratio, fuse_max_ratio);
231 hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, fuse_max_ratio);
232 hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
235 static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable)
237 u16 config = enable ? PLL_CONFIG_DEFAULT : 0;
238 u16 cdyn = enable ? PLL_CDYN_DEFAULT : 0;
239 u16 epp = enable ? PLL_EPP_DEFAULT : 0;
240 struct ivpu_hw_info *hw = vdev->hw;
241 u16 target_ratio = hw->pll.pn_ratio;
244 ivpu_dbg(vdev, PM, "PLL workpoint request: %u Hz, epp: 0x%x, config: 0x%x, cdyn: 0x%x\n",
245 PLL_RATIO_TO_FREQ(target_ratio), epp, config, cdyn);
247 ret = ivpu_pll_cmd_send(vdev, hw->pll.min_ratio, hw->pll.max_ratio,
248 target_ratio, epp, config, cdyn);
250 ivpu_err(vdev, "Failed to send PLL workpoint request: %d\n", ret);
255 ret = ivpu_pll_wait_for_status_ready(vdev);
257 ivpu_err(vdev, "Timed out waiting for PLL ready status\n");
265 static int ivpu_pll_enable(struct ivpu_device *vdev)
267 return ivpu_pll_drive(vdev, true);
270 static int ivpu_pll_disable(struct ivpu_device *vdev)
272 return ivpu_pll_drive(vdev, false);
275 static void ivpu_boot_host_ss_rst_drive(struct ivpu_device *vdev, bool enable)
277 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN);
280 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
281 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
282 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
284 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
285 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
286 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
289 REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val);
292 static void ivpu_boot_host_ss_clk_drive(struct ivpu_device *vdev, bool enable)
294 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN);
297 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
298 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
299 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
301 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
302 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
303 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
306 REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val);
309 static int ivpu_boot_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val)
311 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
313 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val))
319 static int ivpu_boot_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
321 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN);
323 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val))
329 static int ivpu_boot_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
331 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY);
333 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val))
339 static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val)
341 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
343 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) ||
344 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val))
350 static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
352 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN);
354 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
355 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
361 static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
363 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY);
365 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
366 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
372 static void ivpu_boot_idle_gen_drive(struct ivpu_device *vdev, bool enable)
374 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN);
377 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
379 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
381 REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val);
384 static int ivpu_boot_host_ss_check(struct ivpu_device *vdev)
388 ret = ivpu_boot_noc_qreqn_check(vdev, 0x0);
390 ivpu_err(vdev, "Failed qreqn check: %d\n", ret);
394 ret = ivpu_boot_noc_qacceptn_check(vdev, 0x0);
396 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
400 ret = ivpu_boot_noc_qdeny_check(vdev, 0x0);
402 ivpu_err(vdev, "Failed qdeny check %d\n", ret);
407 static int ivpu_boot_host_ss_axi_drive(struct ivpu_device *vdev, bool enable)
412 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
414 val = REG_SET_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
416 val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
417 REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val);
419 ret = ivpu_boot_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
421 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
425 ret = ivpu_boot_noc_qdeny_check(vdev, 0x0);
427 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
432 REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS, WEIGHTS_DEFAULT);
433 REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS_ATS, WEIGHTS_ATS_DEFAULT);
439 static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev)
441 return ivpu_boot_host_ss_axi_drive(vdev, true);
444 static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable)
449 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
451 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
452 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
454 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
455 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
457 REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val);
459 ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
461 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
465 ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0);
467 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
472 static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev)
474 return ivpu_boot_host_ss_top_noc_drive(vdev, true);
477 static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable)
479 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);
482 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
484 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
486 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
492 static void ivpu_boot_pwr_island_drive(struct ivpu_device *vdev, bool enable)
494 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);
497 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
499 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
501 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
507 static int ivpu_boot_wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val)
509 if (ivpu_is_fpga(vdev))
512 return REGV_POLL_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0, CSS_CPU,
513 exp_val, PWR_ISLAND_STATUS_TIMEOUT_US);
516 static void ivpu_boot_pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable)
518 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0);
521 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
523 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
525 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val);
528 static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)
530 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES);
532 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val);
533 val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val);
534 val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);
536 REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val);
539 static void ivpu_boot_tbu_mmu_enable(struct ivpu_device *vdev)
541 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV);
543 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val);
544 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val);
545 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val);
546 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val);
547 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val);
548 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val);
550 REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val);
553 static int ivpu_boot_cpu_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
555 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN);
557 if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN, TOP_MMIO, exp_val, val))
563 static int ivpu_boot_cpu_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
565 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY);
567 if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QDENY, TOP_MMIO, exp_val, val))
573 static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev)
577 ret = ivpu_wait_for_clock_own_resource_ack(vdev);
579 ivpu_err(vdev, "Timed out waiting for clock own resource ACK\n");
583 ivpu_boot_pwr_island_trickle_drive(vdev, true);
584 ivpu_boot_pwr_island_drive(vdev, true);
586 ret = ivpu_boot_wait_for_pwr_island_status(vdev, 0x1);
588 ivpu_err(vdev, "Timed out waiting for power island status\n");
592 ret = ivpu_boot_top_noc_qrenqn_check(vdev, 0x0);
594 ivpu_err(vdev, "Failed qrenqn check %d\n", ret);
598 ivpu_boot_host_ss_clk_drive(vdev, true);
599 ivpu_boot_host_ss_rst_drive(vdev, true);
600 ivpu_boot_pwr_island_isolation_drive(vdev, false);
605 static int ivpu_boot_soc_cpu_drive(struct ivpu_device *vdev, bool enable)
610 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN);
612 val = REG_SET_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
614 val = REG_CLR_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
615 REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val);
617 ret = ivpu_boot_cpu_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
619 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
623 ret = ivpu_boot_cpu_noc_qdeny_check(vdev, 0x0);
625 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
630 static int ivpu_boot_soc_cpu_enable(struct ivpu_device *vdev)
632 return ivpu_boot_soc_cpu_drive(vdev, true);
635 static int ivpu_boot_soc_cpu_boot(struct ivpu_device *vdev)
641 ret = ivpu_boot_soc_cpu_enable(vdev);
643 ivpu_err(vdev, "Failed to enable SOC CPU: %d\n", ret);
647 val64 = vdev->fw->entry_point;
648 val64 <<= ffs(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK) - 1;
649 REGV_WR64(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val64);
651 val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO);
652 val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val);
653 REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val);
655 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n",
656 ivpu_fw_is_cold_boot(vdev) ? "cold boot" : "resume");
661 static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable)
666 ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
668 ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
672 val = REGB_RD32(VPU_40XX_BUTTRESS_D0I3_CONTROL);
674 val = REG_SET_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val);
676 val = REG_CLR_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val);
677 REGB_WR32(VPU_40XX_BUTTRESS_D0I3_CONTROL, val);
679 ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
681 ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
688 static bool ivpu_tile_disable_check(u32 config)
690 /* Allowed values: 0 or one bit from range 0-5 (6 tiles) */
694 if (config > BIT(TILE_MAX_NUM - 1))
697 if ((config & (config - 1)) == 0)
703 static int ivpu_hw_40xx_info_init(struct ivpu_device *vdev)
705 struct ivpu_hw_info *hw = vdev->hw;
710 fuse = REGB_RD32(VPU_40XX_BUTTRESS_TILE_FUSE);
711 if (!REG_TEST_FLD(VPU_40XX_BUTTRESS_TILE_FUSE, VALID, fuse)) {
712 ivpu_err(vdev, "Fuse: invalid (0x%x)\n", fuse);
716 tile_disable = REG_GET_FLD(VPU_40XX_BUTTRESS_TILE_FUSE, CONFIG, fuse);
717 if (!ivpu_tile_disable_check(tile_disable)) {
718 ivpu_err(vdev, "Fuse: Invalid tile disable config (0x%x)\n", tile_disable);
723 ivpu_dbg(vdev, MISC, "Fuse: %d tiles enabled. Tile number %d disabled\n",
724 TILE_MAX_NUM - 1, ffs(tile_disable) - 1);
726 ivpu_dbg(vdev, MISC, "Fuse: All %d tiles enabled\n", TILE_MAX_NUM);
728 tile_enable = (~tile_disable) & TILE_MAX_MASK;
730 hw->sku = REG_SET_FLD_NUM(SKU, HW_ID, LNL_HW_ID, hw->sku);
731 hw->sku = REG_SET_FLD_NUM(SKU, TILE, tile_enable, hw->sku);
732 hw->tile_fuse = tile_disable;
733 hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
735 ivpu_pll_init_frequency_ratios(vdev);
737 ivpu_hw_init_range(&vdev->hw->ranges.global, 0x80000000, SZ_512M);
738 ivpu_hw_init_range(&vdev->hw->ranges.user, 0x80000000, SZ_256M);
739 ivpu_hw_init_range(&vdev->hw->ranges.shave, 0x80000000 + SZ_256M, SZ_2G - SZ_256M);
740 ivpu_hw_init_range(&vdev->hw->ranges.dma, 0x200000000, SZ_8G);
742 ivpu_hw_read_platform(vdev);
743 ivpu_hw_wa_init(vdev);
744 ivpu_hw_timeouts_init(vdev);
749 static int ivpu_hw_40xx_reset(struct ivpu_device *vdev)
754 ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, 0, TIMEOUT_US);
756 ivpu_err(vdev, "Wait for *_TRIGGER timed out\n");
760 val = REGB_RD32(VPU_40XX_BUTTRESS_IP_RESET);
761 val = REG_SET_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, val);
762 REGB_WR32(VPU_40XX_BUTTRESS_IP_RESET, val);
764 ret = REGB_POLL_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, 0, TIMEOUT_US);
766 ivpu_err(vdev, "Timed out waiting for RESET completion\n");
771 static int ivpu_hw_40xx_d0i3_enable(struct ivpu_device *vdev)
775 if (IVPU_WA(punit_disabled))
778 ret = ivpu_boot_d0i3_drive(vdev, true);
780 ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret);
782 udelay(5); /* VPU requires 5 us to complete the transition */
787 static int ivpu_hw_40xx_d0i3_disable(struct ivpu_device *vdev)
791 if (IVPU_WA(punit_disabled))
794 ret = ivpu_boot_d0i3_drive(vdev, false);
796 ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);
801 static void ivpu_hw_40xx_profiling_freq_reg_set(struct ivpu_device *vdev)
803 u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
805 if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT)
806 val = REG_CLR_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val);
808 val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val);
810 REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);
813 static void ivpu_hw_40xx_ats_print(struct ivpu_device *vdev)
815 ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n",
816 REGB_RD32(VPU_40XX_BUTTRESS_HM_ATS) ? "Enable" : "Disable");
819 static void ivpu_hw_40xx_clock_relinquish_disable(struct ivpu_device *vdev)
821 u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
823 val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, DISABLE_CLK_RELINQUISH, val);
824 REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);
827 static int ivpu_hw_40xx_power_up(struct ivpu_device *vdev)
831 ret = ivpu_hw_40xx_d0i3_disable(vdev);
833 ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret);
835 ret = ivpu_pll_enable(vdev);
837 ivpu_err(vdev, "Failed to enable PLL: %d\n", ret);
841 if (IVPU_WA(disable_clock_relinquish))
842 ivpu_hw_40xx_clock_relinquish_disable(vdev);
843 ivpu_hw_40xx_profiling_freq_reg_set(vdev);
844 ivpu_hw_40xx_ats_print(vdev);
846 ret = ivpu_boot_host_ss_check(vdev);
848 ivpu_err(vdev, "Failed to configure host SS: %d\n", ret);
852 ivpu_boot_idle_gen_drive(vdev, false);
854 ret = ivpu_boot_pwr_domain_enable(vdev);
856 ivpu_err(vdev, "Failed to enable power domain: %d\n", ret);
860 ret = ivpu_boot_host_ss_axi_enable(vdev);
862 ivpu_err(vdev, "Failed to enable AXI: %d\n", ret);
866 ret = ivpu_boot_host_ss_top_noc_enable(vdev);
868 ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret);
873 static int ivpu_hw_40xx_boot_fw(struct ivpu_device *vdev)
877 ivpu_boot_no_snoop_enable(vdev);
878 ivpu_boot_tbu_mmu_enable(vdev);
880 ret = ivpu_boot_soc_cpu_boot(vdev);
882 ivpu_err(vdev, "Failed to boot SOC CPU: %d\n", ret);
887 static bool ivpu_hw_40xx_is_idle(struct ivpu_device *vdev)
891 if (IVPU_WA(punit_disabled))
894 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
895 return REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, READY, val) &&
896 REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, IDLE, val);
899 static int ivpu_hw_40xx_wait_for_idle(struct ivpu_device *vdev)
901 return REGB_POLL_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
904 static void ivpu_hw_40xx_save_d0i3_entry_timestamp(struct ivpu_device *vdev)
906 vdev->hw->d0i3_entry_host_ts = ktime_get_boottime();
907 vdev->hw->d0i3_entry_vpu_ts = REGV_RD64(VPU_40XX_CPU_SS_TIM_PERF_EXT_FREE_CNT);
910 static int ivpu_hw_40xx_power_down(struct ivpu_device *vdev)
914 ivpu_hw_40xx_save_d0i3_entry_timestamp(vdev);
916 if (!ivpu_hw_40xx_is_idle(vdev) && ivpu_hw_40xx_reset(vdev))
917 ivpu_warn(vdev, "Failed to reset the VPU\n");
919 if (ivpu_pll_disable(vdev)) {
920 ivpu_err(vdev, "Failed to disable PLL\n");
924 if (ivpu_hw_40xx_d0i3_enable(vdev)) {
925 ivpu_err(vdev, "Failed to enter D0I3\n");
932 static void ivpu_hw_40xx_wdt_disable(struct ivpu_device *vdev)
936 REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
937 REGV_WR32(VPU_40XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE);
939 REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
940 REGV_WR32(VPU_40XX_CPU_SS_TIM_WDOG_EN, 0);
942 val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG);
943 val = REG_CLR_FLD(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);
944 REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val);
947 static u32 ivpu_hw_40xx_profiling_freq_get(struct ivpu_device *vdev)
949 return vdev->hw->pll.profiling_freq;
952 static void ivpu_hw_40xx_profiling_freq_drive(struct ivpu_device *vdev, bool enable)
955 vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_HIGH;
957 vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
960 /* Register indirect accesses */
961 static u32 ivpu_hw_40xx_reg_pll_freq_get(struct ivpu_device *vdev)
965 pll_curr_ratio = REGB_RD32(VPU_40XX_BUTTRESS_PLL_FREQ);
966 pll_curr_ratio &= VPU_40XX_BUTTRESS_PLL_FREQ_RATIO_MASK;
968 return PLL_RATIO_TO_FREQ(pll_curr_ratio);
971 static u32 ivpu_hw_40xx_reg_telemetry_offset_get(struct ivpu_device *vdev)
973 return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_OFFSET);
976 static u32 ivpu_hw_40xx_reg_telemetry_size_get(struct ivpu_device *vdev)
978 return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_SIZE);
981 static u32 ivpu_hw_40xx_reg_telemetry_enable_get(struct ivpu_device *vdev)
983 return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_ENABLE);
986 static void ivpu_hw_40xx_reg_db_set(struct ivpu_device *vdev, u32 db_id)
988 u32 reg_stride = VPU_40XX_CPU_SS_DOORBELL_1 - VPU_40XX_CPU_SS_DOORBELL_0;
989 u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET);
991 REGV_WR32I(VPU_40XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val);
994 static u32 ivpu_hw_40xx_reg_ipc_rx_addr_get(struct ivpu_device *vdev)
996 return REGV_RD32(VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM);
999 static u32 ivpu_hw_40xx_reg_ipc_rx_count_get(struct ivpu_device *vdev)
1001 u32 count = REGV_RD32_SILENT(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT);
1003 return REG_GET_FLD(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count);
1006 static void ivpu_hw_40xx_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
1008 REGV_WR32(VPU_40XX_CPU_SS_TIM_IPC_FIFO, vpu_addr);
1011 static void ivpu_hw_40xx_irq_clear(struct ivpu_device *vdev)
1013 REGV_WR64(VPU_40XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK);
1016 static void ivpu_hw_40xx_irq_enable(struct ivpu_device *vdev)
1018 REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK);
1019 REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK);
1020 REGB_WR32(VPU_40XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK);
1021 REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
1024 static void ivpu_hw_40xx_irq_disable(struct ivpu_device *vdev)
1026 REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
1027 REGB_WR32(VPU_40XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK);
1028 REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, 0x0ull);
1029 REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, 0x0ul);
1032 static void ivpu_hw_40xx_irq_wdt_nce_handler(struct ivpu_device *vdev)
1034 /* TODO: For LNN hang consider engine reset instead of full recovery */
1035 ivpu_pm_schedule_recovery(vdev);
1038 static void ivpu_hw_40xx_irq_wdt_mss_handler(struct ivpu_device *vdev)
1040 ivpu_hw_wdt_disable(vdev);
1041 ivpu_pm_schedule_recovery(vdev);
1044 static void ivpu_hw_40xx_irq_noc_firewall_handler(struct ivpu_device *vdev)
1046 ivpu_pm_schedule_recovery(vdev);
1049 /* Handler for IRQs from VPU core (irqV) */
1050 static bool ivpu_hw_40xx_irqv_handler(struct ivpu_device *vdev, int irq, bool *wake_thread)
1052 u32 status = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;
1057 REGV_WR32(VPU_40XX_HOST_SS_ICB_CLEAR_0, status);
1059 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status))
1060 ivpu_mmu_irq_evtq_handler(vdev);
1062 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status))
1063 ivpu_ipc_irq_handler(vdev, wake_thread);
1065 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status))
1066 ivpu_dbg(vdev, IRQ, "MMU sync complete\n");
1068 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status))
1069 ivpu_mmu_irq_gerr_handler(vdev);
1071 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status))
1072 ivpu_hw_40xx_irq_wdt_mss_handler(vdev);
1074 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status))
1075 ivpu_hw_40xx_irq_wdt_nce_handler(vdev);
1077 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status))
1078 ivpu_hw_40xx_irq_noc_firewall_handler(vdev);
1083 /* Handler for IRQs from Buttress core (irqB) */
1084 static bool ivpu_hw_40xx_irqb_handler(struct ivpu_device *vdev, int irq)
1086 bool schedule_recovery = false;
1087 u32 status = REGB_RD32(VPU_40XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
1092 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE, status))
1093 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE");
1095 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, status)) {
1096 ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
1097 REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG1),
1098 REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG2));
1099 REGB_WR32(VPU_40XX_BUTTRESS_ATS_ERR_CLEAR, 0x1);
1100 schedule_recovery = true;
1103 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR, status)) {
1104 ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG));
1105 REGB_WR32(VPU_40XX_BUTTRESS_CFI0_ERR_CLEAR, 0x1);
1106 schedule_recovery = true;
1109 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR, status)) {
1110 ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG));
1111 REGB_WR32(VPU_40XX_BUTTRESS_CFI1_ERR_CLEAR, 0x1);
1112 schedule_recovery = true;
1115 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR, status)) {
1116 ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x",
1117 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW),
1118 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH));
1119 REGB_WR32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_CLEAR, 0x1);
1120 schedule_recovery = true;
1123 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR, status)) {
1124 ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x",
1125 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW),
1126 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH));
1127 REGB_WR32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_CLEAR, 0x1);
1128 schedule_recovery = true;
1131 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR, status)) {
1132 ivpu_err(vdev, "Survivability error detected\n");
1133 schedule_recovery = true;
1136 /* This must be done after interrupts are cleared at the source. */
1137 REGB_WR32(VPU_40XX_BUTTRESS_INTERRUPT_STAT, status);
1139 if (schedule_recovery)
1140 ivpu_pm_schedule_recovery(vdev);
1145 static irqreturn_t ivpu_hw_40xx_irq_handler(int irq, void *ptr)
1147 bool irqv_handled, irqb_handled, wake_thread = false;
1148 struct ivpu_device *vdev = ptr;
1150 REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
1152 irqv_handled = ivpu_hw_40xx_irqv_handler(vdev, irq, &wake_thread);
1153 irqb_handled = ivpu_hw_40xx_irqb_handler(vdev, irq);
1155 /* Re-enable global interrupts to re-trigger MSI for pending interrupts */
1156 REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
1159 return IRQ_WAKE_THREAD;
1160 if (irqv_handled || irqb_handled)
1165 static void ivpu_hw_40xx_diagnose_failure(struct ivpu_device *vdev)
1167 u32 irqv = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;
1168 u32 irqb = REGB_RD32(VPU_40XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;
1170 if (ivpu_hw_40xx_reg_ipc_rx_count_get(vdev))
1171 ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
1173 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, irqv))
1174 ivpu_err(vdev, "WDT MSS timeout detected\n");
1176 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, irqv))
1177 ivpu_err(vdev, "WDT NCE timeout detected\n");
1179 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, irqv))
1180 ivpu_err(vdev, "NOC Firewall irq detected\n");
1182 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, irqb)) {
1183 ivpu_err(vdev, "ATS_ERR_LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
1184 REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG1),
1185 REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG2));
1188 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR, irqb))
1189 ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG));
1191 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR, irqb))
1192 ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG));
1194 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR, irqb))
1195 ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x\n",
1196 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW),
1197 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH));
1199 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR, irqb))
1200 ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x\n",
1201 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW),
1202 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH));
1204 if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR, irqb))
1205 ivpu_err(vdev, "Survivability error detected\n");
1208 const struct ivpu_hw_ops ivpu_hw_40xx_ops = {
1209 .info_init = ivpu_hw_40xx_info_init,
1210 .power_up = ivpu_hw_40xx_power_up,
1211 .is_idle = ivpu_hw_40xx_is_idle,
1212 .wait_for_idle = ivpu_hw_40xx_wait_for_idle,
1213 .power_down = ivpu_hw_40xx_power_down,
1214 .reset = ivpu_hw_40xx_reset,
1215 .boot_fw = ivpu_hw_40xx_boot_fw,
1216 .wdt_disable = ivpu_hw_40xx_wdt_disable,
1217 .diagnose_failure = ivpu_hw_40xx_diagnose_failure,
1218 .profiling_freq_get = ivpu_hw_40xx_profiling_freq_get,
1219 .profiling_freq_drive = ivpu_hw_40xx_profiling_freq_drive,
1220 .reg_pll_freq_get = ivpu_hw_40xx_reg_pll_freq_get,
1221 .reg_telemetry_offset_get = ivpu_hw_40xx_reg_telemetry_offset_get,
1222 .reg_telemetry_size_get = ivpu_hw_40xx_reg_telemetry_size_get,
1223 .reg_telemetry_enable_get = ivpu_hw_40xx_reg_telemetry_enable_get,
1224 .reg_db_set = ivpu_hw_40xx_reg_db_set,
1225 .reg_ipc_rx_addr_get = ivpu_hw_40xx_reg_ipc_rx_addr_get,
1226 .reg_ipc_rx_count_get = ivpu_hw_40xx_reg_ipc_rx_count_get,
1227 .reg_ipc_tx_set = ivpu_hw_40xx_reg_ipc_tx_set,
1228 .irq_clear = ivpu_hw_40xx_irq_clear,
1229 .irq_enable = ivpu_hw_40xx_irq_enable,
1230 .irq_disable = ivpu_hw_40xx_irq_disable,
1231 .irq_handler = ivpu_hw_40xx_irq_handler,