drivers/accel/ivpu/ivpu_fw.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2020-2023 Intel Corporation
   4  */
   5
   6 #include <linux/firmware.h>
   7 #include <linux/highmem.h>
   8 #include <linux/moduleparam.h>
   9 #include <linux/pci.h>
  10
  11 #include "vpu_boot_api.h"
  12 #include "ivpu_drv.h"
  13 #include "ivpu_fw.h"
  14 #include "ivpu_fw_log.h"
  15 #include "ivpu_gem.h"
  16 #include "ivpu_hw.h"
  17 #include "ivpu_ipc.h"
  18 #include "ivpu_pm.h"
  19
  20 #define FW_GLOBAL_MEM_START     (2ull * SZ_1G)
  21 #define FW_GLOBAL_MEM_END       (3ull * SZ_1G)
  22 #define FW_SHARED_MEM_SIZE      SZ_256M /* Must be aligned to FW_SHARED_MEM_ALIGNMENT */
  23 #define FW_SHARED_MEM_ALIGNMENT SZ_128K /* VPU MTRR limitation */
  24 #define FW_RUNTIME_MAX_SIZE     SZ_512M
  25 #define FW_SHAVE_NN_MAX_SIZE    SZ_2M
  26 #define FW_RUNTIME_MIN_ADDR     (FW_GLOBAL_MEM_START)
  27 #define FW_RUNTIME_MAX_ADDR     (FW_GLOBAL_MEM_END - FW_SHARED_MEM_SIZE)
  28 #define FW_VERSION_HEADER_SIZE  SZ_4K
  29 #define FW_FILE_IMAGE_OFFSET    (VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE)
  30
  31 #define WATCHDOG_MSS_REDIRECT   32
  32 #define WATCHDOG_NCE_REDIRECT   33
  33
  34 #define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31)
  35
  36 /* Check if FW API is compatible with the driver */
  37 #define IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, name, min_major) \
  38         ivpu_fw_check_api(vdev, fw_hdr, #name, \
  39                           VPU_##name##_API_VER_INDEX, \
  40                           VPU_##name##_API_VER_MAJOR, \
  41                           VPU_##name##_API_VER_MINOR, min_major)
  42
  43 /* Check if API version is lower that the given version */
  44 #define IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, name, major, minor) \
  45         ivpu_fw_check_api_ver_lt(vdev, fw_hdr, #name, VPU_##name##_API_VER_INDEX, major, minor)
  46
  47 static char *ivpu_firmware;
  48 module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644);
  49 MODULE_PARM_DESC(firmware, "VPU firmware binary in /lib/firmware/..");
  50
  51 /* TODO: Remove mtl_vpu.bin from names after transition to generation based FW names */
  52 static struct {
  53         int gen;
  54         const char *name;
  55 } fw_names[] = {
  56         { IVPU_HW_37XX, "vpu_37xx.bin" },
  57         { IVPU_HW_37XX, "mtl_vpu.bin" },
  58         { IVPU_HW_37XX, "intel/vpu/vpu_37xx_v0.0.bin" },
  59         { IVPU_HW_40XX, "vpu_40xx.bin" },
  60         { IVPU_HW_40XX, "intel/vpu/vpu_40xx_v0.0.bin" },
  61 };
  62
  63 static int ivpu_fw_request(struct ivpu_device *vdev)
  64 {
  65         int ret = -ENOENT;
  66         int i;
  67
  68         if (ivpu_firmware) {
  69                 ret = request_firmware(&vdev->fw->file, ivpu_firmware, vdev->drm.dev);
  70                 if (!ret)
  71                         vdev->fw->name = ivpu_firmware;
  72                 return ret;
  73         }
  74
  75         for (i = 0; i < ARRAY_SIZE(fw_names); i++) {
  76                 if (fw_names[i].gen != ivpu_hw_gen(vdev))
  77                         continue;
  78
  79                 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i].name, vdev->drm.dev);
  80                 if (!ret) {
  81                         vdev->fw->name = fw_names[i].name;
  82                         return 0;
  83                 }
  84         }
  85
  86         ivpu_err(vdev, "Failed to request firmware: %d\n", ret);
  87         return ret;
  88 }
  89
  90 static int
  91 ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr,
  92                   const char *str, int index, u16 expected_major, u16 expected_minor,
  93                   u16 min_major)
  94 {
  95         u16 major = (u16)(fw_hdr->api_version[index] >> 16);
  96         u16 minor = (u16)(fw_hdr->api_version[index]);
  97
  98         if (major < min_major) {
  99                 ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n",
 100                          str, major, minor, min_major);
 101                 return -EINVAL;
 102         }
 103         if (major != expected_major) {
 104                 ivpu_warn(vdev, "Major FW %s API version different: %d.%d (expected %d.%d)\n",
 105                           str, major, minor, expected_major, expected_minor);
 106         }
 107         ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n",
 108                  str, major, minor, expected_major, expected_minor);
 109
 110         return 0;
 111 }
 112
 113 static bool
 114 ivpu_fw_check_api_ver_lt(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr,
 115                          const char *str, int index, u16 major, u16 minor)
 116 {
 117         u16 fw_major = (u16)(fw_hdr->api_version[index] >> 16);
 118         u16 fw_minor = (u16)(fw_hdr->api_version[index]);
 119
 120         if (fw_major < major || (fw_major == major && fw_minor < minor))
 121                 return true;
 122
 123         return false;
 124 }
 125
 126 static int ivpu_fw_parse(struct ivpu_device *vdev)
 127 {
 128         struct ivpu_fw_info *fw = vdev->fw;
 129         const struct vpu_firmware_header *fw_hdr = (const void *)fw->file->data;
 130         u64 runtime_addr, image_load_addr, runtime_size, image_size;
 131
 132         if (fw->file->size <= FW_FILE_IMAGE_OFFSET) {
 133                 ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size);
 134                 return -EINVAL;
 135         }
 136
 137         if (fw_hdr->header_version != VPU_FW_HEADER_VERSION) {
 138                 ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version);
 139                 return -EINVAL;
 140         }
 141
 142         runtime_addr = fw_hdr->boot_params_load_address;
 143         runtime_size = fw_hdr->runtime_size;
 144         image_load_addr = fw_hdr->image_load_address;
 145         image_size = fw_hdr->image_size;
 146
 147         if (runtime_addr < FW_RUNTIME_MIN_ADDR || runtime_addr > FW_RUNTIME_MAX_ADDR) {
 148                 ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx\n", runtime_addr);
 149                 return -EINVAL;
 150         }
 151
 152         if (runtime_size < fw->file->size || runtime_size > FW_RUNTIME_MAX_SIZE) {
 153                 ivpu_err(vdev, "Invalid firmware runtime size: %llu\n", runtime_size);
 154                 return -EINVAL;
 155         }
 156
 157         if (FW_FILE_IMAGE_OFFSET + image_size > fw->file->size) {
 158                 ivpu_err(vdev, "Invalid image size: %llu\n", image_size);
 159                 return -EINVAL;
 160         }
 161
 162         if (image_load_addr < runtime_addr ||
 163             image_load_addr + image_size > runtime_addr + runtime_size) {
 164                 ivpu_err(vdev, "Invalid firmware load address size: 0x%llx and size %llu\n",
 165                          image_load_addr, image_size);
 166                 return -EINVAL;
 167         }
 168
 169         if (fw_hdr->shave_nn_fw_size > FW_SHAVE_NN_MAX_SIZE) {
 170                 ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size);
 171                 return -EINVAL;
 172         }
 173
 174         if (fw_hdr->entry_point < image_load_addr ||
 175             fw_hdr->entry_point >= image_load_addr + image_size) {
 176                 ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point);
 177                 return -EINVAL;
 178         }
 179         ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n",
 180                  fw_hdr->header_version, fw_hdr->image_format);
 181
 182         ivpu_info(vdev, "Firmware: %s, version: %s", fw->name,
 183                   (const char *)fw_hdr + VPU_FW_HEADER_SIZE);
 184
 185         if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, BOOT, 3))
 186                 return -EINVAL;
 187         if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, JSM, 3))
 188                 return -EINVAL;
 189
 190         fw->runtime_addr = runtime_addr;
 191         fw->runtime_size = runtime_size;
 192         fw->image_load_offset = image_load_addr - runtime_addr;
 193         fw->image_size = image_size;
 194         fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size);
 195
 196         fw->cold_boot_entry_point = fw_hdr->entry_point;
 197         fw->entry_point = fw->cold_boot_entry_point;
 198
 199         fw->trace_level = min_t(u32, ivpu_log_level, IVPU_FW_LOG_FATAL);
 200         fw->trace_destination_mask = VPU_TRACE_DESTINATION_VERBOSE_TRACING;
 201         fw->trace_hw_component_mask = -1;
 202
 203         fw->dvfs_mode = 0;
 204
 205         ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n",
 206                  fw->file->size, fw->image_size, fw->runtime_size, fw->shave_nn_size);
 207         ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n",
 208                  fw->runtime_addr, image_load_addr, fw->entry_point);
 209
 210         return 0;
 211 }
 212
 213 static void ivpu_fw_release(struct ivpu_device *vdev)
 214 {
 215         release_firmware(vdev->fw->file);
 216 }
 217
 218 /* Initialize workarounds that depend on FW version */
 219 static void
 220 ivpu_fw_init_wa(struct ivpu_device *vdev)
 221 {
 222         const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data;
 223
 224         if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) ||
 225             (ivpu_hw_gen(vdev) > IVPU_HW_37XX) ||
 226             (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE))
 227                 vdev->wa.disable_d0i3_msg = true;
 228
 229         /* Force enable the feature for testing purposes */
 230         if (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_ENABLE)
 231                 vdev->wa.disable_d0i3_msg = false;
 232
 233         IVPU_PRINT_WA(disable_d0i3_msg);
 234 }
 235
 236 static int ivpu_fw_update_global_range(struct ivpu_device *vdev)
 237 {
 238         struct ivpu_fw_info *fw = vdev->fw;
 239         u64 start = ALIGN(fw->runtime_addr + fw->runtime_size, FW_SHARED_MEM_ALIGNMENT);
 240         u64 size = FW_SHARED_MEM_SIZE;
 241
 242         if (start + size > FW_GLOBAL_MEM_END) {
 243                 ivpu_err(vdev, "No space for shared region, start %lld, size %lld\n", start, size);
 244                 return -EINVAL;
 245         }
 246
 247         ivpu_hw_init_range(&vdev->hw->ranges.global, start, size);
 248         return 0;
 249 }
 250
 251 static int ivpu_fw_mem_init(struct ivpu_device *vdev)
 252 {
 253         struct ivpu_fw_info *fw = vdev->fw;
 254         int log_verb_size;
 255         int ret;
 256
 257         ret = ivpu_fw_update_global_range(vdev);
 258         if (ret)
 259                 return ret;
 260
 261         fw->mem = ivpu_bo_alloc_internal(vdev, fw->runtime_addr, fw->runtime_size, DRM_IVPU_BO_WC);
 262         if (!fw->mem) {
 263                 ivpu_err(vdev, "Failed to allocate firmware runtime memory\n");
 264                 return -ENOMEM;
 265         }
 266
 267         fw->mem_log_crit = ivpu_bo_alloc_internal(vdev, 0, IVPU_FW_CRITICAL_BUFFER_SIZE,
 268                                                   DRM_IVPU_BO_CACHED);
 269         if (!fw->mem_log_crit) {
 270                 ivpu_err(vdev, "Failed to allocate critical log buffer\n");
 271                 ret = -ENOMEM;
 272                 goto err_free_fw_mem;
 273         }
 274
 275         if (ivpu_log_level <= IVPU_FW_LOG_INFO)
 276                 log_verb_size = IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE;
 277         else
 278                 log_verb_size = IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE;
 279
 280         fw->mem_log_verb = ivpu_bo_alloc_internal(vdev, 0, log_verb_size, DRM_IVPU_BO_CACHED);
 281         if (!fw->mem_log_verb) {
 282                 ivpu_err(vdev, "Failed to allocate verbose log buffer\n");
 283                 ret = -ENOMEM;
 284                 goto err_free_log_crit;
 285         }
 286
 287         if (fw->shave_nn_size) {
 288                 fw->mem_shave_nn = ivpu_bo_alloc_internal(vdev, vdev->hw->ranges.shave.start,
 289                                                           fw->shave_nn_size, DRM_IVPU_BO_WC);
 290                 if (!fw->mem_shave_nn) {
 291                         ivpu_err(vdev, "Failed to allocate shavenn buffer\n");
 292                         ret = -ENOMEM;
 293                         goto err_free_log_verb;
 294                 }
 295         }
 296
 297         return 0;
 298
 299 err_free_log_verb:
 300         ivpu_bo_free_internal(fw->mem_log_verb);
 301 err_free_log_crit:
 302         ivpu_bo_free_internal(fw->mem_log_crit);
 303 err_free_fw_mem:
 304         ivpu_bo_free_internal(fw->mem);
 305         return ret;
 306 }
 307
 308 static void ivpu_fw_mem_fini(struct ivpu_device *vdev)
 309 {
 310         struct ivpu_fw_info *fw = vdev->fw;
 311
 312         if (fw->mem_shave_nn) {
 313                 ivpu_bo_free_internal(fw->mem_shave_nn);
 314                 fw->mem_shave_nn = NULL;
 315         }
 316
 317         ivpu_bo_free_internal(fw->mem_log_verb);
 318         ivpu_bo_free_internal(fw->mem_log_crit);
 319         ivpu_bo_free_internal(fw->mem);
 320
 321         fw->mem_log_verb = NULL;
 322         fw->mem_log_crit = NULL;
 323         fw->mem = NULL;
 324 }
 325
 326 int ivpu_fw_init(struct ivpu_device *vdev)
 327 {
 328         int ret;
 329
 330         ret = ivpu_fw_request(vdev);
 331         if (ret)
 332                 return ret;
 333
 334         ret = ivpu_fw_parse(vdev);
 335         if (ret)
 336                 goto err_fw_release;
 337
 338         ivpu_fw_init_wa(vdev);
 339
 340         ret = ivpu_fw_mem_init(vdev);
 341         if (ret)
 342                 goto err_fw_release;
 343
 344         ivpu_fw_load(vdev);
 345
 346         return 0;
 347
 348 err_fw_release:
 349         ivpu_fw_release(vdev);
 350         return ret;
 351 }
 352
 353 void ivpu_fw_fini(struct ivpu_device *vdev)
 354 {
 355         ivpu_fw_mem_fini(vdev);
 356         ivpu_fw_release(vdev);
 357 }
 358
 359 void ivpu_fw_load(struct ivpu_device *vdev)
 360 {
 361         struct ivpu_fw_info *fw = vdev->fw;
 362         u64 image_end_offset = fw->image_load_offset + fw->image_size;
 363
 364         memset(ivpu_bo_vaddr(fw->mem), 0, fw->image_load_offset);
 365         memcpy(ivpu_bo_vaddr(fw->mem) + fw->image_load_offset,
 366                fw->file->data + FW_FILE_IMAGE_OFFSET, fw->image_size);
 367
 368         if (IVPU_WA(clear_runtime_mem)) {
 369                 u8 *start = ivpu_bo_vaddr(fw->mem) + image_end_offset;
 370                 u64 size = ivpu_bo_size(fw->mem) - image_end_offset;
 371
 372                 memset(start, 0, size);
 373         }
 374
 375         wmb(); /* Flush WC buffers after writing fw->mem */
 376 }
 377
 378 static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params)
 379 {
 380         ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n",
 381                  boot_params->magic);
 382         ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n",
 383                  boot_params->vpu_id);
 384         ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n",
 385                  boot_params->vpu_count);
 386         ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n",
 387                  boot_params->frequency);
 388         ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n",
 389                  boot_params->perf_clk_frequency);
 390
 391         ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n",
 392                  boot_params->ipc_header_area_start);
 393         ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n",
 394                  boot_params->ipc_header_area_size);
 395         ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n",
 396                  boot_params->shared_region_base);
 397         ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n",
 398                  boot_params->shared_region_size);
 399         ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n",
 400                  boot_params->ipc_payload_area_start);
 401         ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n",
 402                  boot_params->ipc_payload_area_size);
 403         ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n",
 404                  boot_params->global_aliased_pio_base);
 405         ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n",
 406                  boot_params->global_aliased_pio_size);
 407
 408         ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n",
 409                  boot_params->autoconfig);
 410
 411         ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n",
 412                  boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use);
 413         ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n",
 414                  boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg);
 415
 416         ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_base = 0x%llx\n",
 417                  boot_params->global_memory_allocator_base);
 418         ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_size = 0x%x\n",
 419                  boot_params->global_memory_allocator_size);
 420
 421         ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n",
 422                  boot_params->shave_nn_fw_base);
 423
 424         ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n",
 425                  boot_params->watchdog_irq_mss);
 426         ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n",
 427                  boot_params->watchdog_irq_nce);
 428         ivpu_dbg(vdev, FW_BOOT, "boot_params.host_to_vpu_irq = 0x%x\n",
 429                  boot_params->host_to_vpu_irq);
 430         ivpu_dbg(vdev, FW_BOOT, "boot_params.job_done_irq = 0x%x\n",
 431                  boot_params->job_done_irq);
 432
 433         ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n",
 434                  boot_params->host_version_id);
 435         ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n",
 436                  boot_params->si_stepping);
 437         ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n",
 438                  boot_params->device_id);
 439         ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n",
 440                  boot_params->feature_exclusion);
 441         ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n",
 442                  boot_params->sku);
 443         ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n",
 444                  boot_params->min_freq_pll_ratio);
 445         ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n",
 446                  boot_params->pn_freq_pll_ratio);
 447         ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n",
 448                  boot_params->max_freq_pll_ratio);
 449         ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n",
 450                  boot_params->default_trace_level);
 451         ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n",
 452                  boot_params->tracing_buff_message_format_mask);
 453         ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n",
 454                  boot_params->trace_destination_mask);
 455         ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n",
 456                  boot_params->trace_hw_component_mask);
 457         ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n",
 458                  boot_params->boot_type);
 459         ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n",
 460                  boot_params->punit_telemetry_sram_base);
 461         ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n",
 462                  boot_params->punit_telemetry_sram_size);
 463         ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n",
 464                  boot_params->vpu_telemetry_enable);
 465         ivpu_dbg(vdev, FW_BOOT, "boot_params.dvfs_mode = %u\n",
 466                  boot_params->dvfs_mode);
 467         ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_delayed_entry = %d\n",
 468                  boot_params->d0i3_delayed_entry);
 469         ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n",
 470                  boot_params->d0i3_residency_time_us);
 471         ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n",
 472                  boot_params->d0i3_entry_vpu_ts);
 473 }
 474
 475 void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params)
 476 {
 477         struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx;
 478
 479         /* In case of warm boot only update variable params */
 480         if (!ivpu_fw_is_cold_boot(vdev)) {
 481                 boot_params->d0i3_residency_time_us =
 482                         ktime_us_delta(ktime_get_boottime(), vdev->hw->d0i3_entry_host_ts);
 483                 boot_params->d0i3_entry_vpu_ts = vdev->hw->d0i3_entry_vpu_ts;
 484
 485                 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n",
 486                          boot_params->d0i3_residency_time_us);
 487                 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n",
 488                          boot_params->d0i3_entry_vpu_ts);
 489
 490                 boot_params->save_restore_ret_address = 0;
 491                 vdev->pm->is_warmboot = true;
 492                 return;
 493         }
 494
 495         vdev->pm->is_warmboot = false;
 496
 497         boot_params->magic = VPU_BOOT_PARAMS_MAGIC;
 498         boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number;
 499         boot_params->frequency = ivpu_hw_reg_pll_freq_get(vdev);
 500
 501         /*
 502          * This param is a debug firmware feature.  It switches default clock
 503          * to higher resolution one for fine-grained and more accurate firmware
 504          * task profiling.
 505          */
 506         boot_params->perf_clk_frequency = ivpu_hw_profiling_freq_get(vdev);
 507
 508         /*
 509          * Uncached region of VPU address space, covers IPC buffers, job queues
 510          * and log buffers, programmable to L2$ Uncached by VPU MTRR
 511          */
 512         boot_params->shared_region_base = vdev->hw->ranges.global.start;
 513         boot_params->shared_region_size = vdev->hw->ranges.global.end -
 514                                           vdev->hw->ranges.global.start;
 515
 516         boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr;
 517         boot_params->ipc_header_area_size = ivpu_bo_size(ipc_mem_rx) / 2;
 518
 519         boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ivpu_bo_size(ipc_mem_rx) / 2;
 520         boot_params->ipc_payload_area_size = ivpu_bo_size(ipc_mem_rx) / 2;
 521
 522         boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start;
 523         boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user);
 524
 525         /* Allow configuration for L2C_PAGE_TABLE with boot param value */
 526         boot_params->autoconfig = 1;
 527
 528         /* Enable L2 cache for first 2GB of high memory */
 529         boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1;
 530         boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg =
 531                 ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.shave.start);
 532
 533         if (vdev->fw->mem_shave_nn)
 534                 boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr;
 535
 536         boot_params->watchdog_irq_mss = WATCHDOG_MSS_REDIRECT;
 537         boot_params->watchdog_irq_nce = WATCHDOG_NCE_REDIRECT;
 538         boot_params->si_stepping = ivpu_revision(vdev);
 539         boot_params->device_id = ivpu_device_id(vdev);
 540         boot_params->feature_exclusion = vdev->hw->tile_fuse;
 541         boot_params->sku = vdev->hw->sku;
 542
 543         boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio;
 544         boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio;
 545         boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio;
 546
 547         boot_params->default_trace_level = vdev->fw->trace_level;
 548         boot_params->tracing_buff_message_format_mask = BIT(VPU_TRACING_FORMAT_STRING);
 549         boot_params->trace_destination_mask = vdev->fw->trace_destination_mask;
 550         boot_params->trace_hw_component_mask = vdev->fw->trace_hw_component_mask;
 551         boot_params->crit_tracing_buff_addr = vdev->fw->mem_log_crit->vpu_addr;
 552         boot_params->crit_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_crit);
 553         boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr;
 554         boot_params->verbose_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_verb);
 555
 556         boot_params->punit_telemetry_sram_base = ivpu_hw_reg_telemetry_offset_get(vdev);
 557         boot_params->punit_telemetry_sram_size = ivpu_hw_reg_telemetry_size_get(vdev);
 558         boot_params->vpu_telemetry_enable = ivpu_hw_reg_telemetry_enable_get(vdev);
 559         boot_params->dvfs_mode = vdev->fw->dvfs_mode;
 560         if (!IVPU_WA(disable_d0i3_msg))
 561                 boot_params->d0i3_delayed_entry = 1;
 562         boot_params->d0i3_residency_time_us = 0;
 563         boot_params->d0i3_entry_vpu_ts = 0;
 564
 565         wmb(); /* Flush WC buffers after writing bootparams */
 566
 567         ivpu_fw_boot_params_print(vdev, boot_params);
 568 }