1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2020-2023 Intel Corporation
9 #include <drm/drm_device.h>
10 #include <drm/drm_drv.h>
11 #include <drm/drm_managed.h>
12 #include <drm/drm_mm.h>
13 #include <drm/drm_print.h>
15 #include <linux/pci.h>
16 #include <linux/xarray.h>
17 #include <uapi/drm/ivpu_accel.h>
19 #include "ivpu_mmu_context.h"
21 #define DRIVER_NAME "intel_vpu"
22 #define DRIVER_DESC "Driver for Intel Versatile Processing Unit (VPU)"
23 #define DRIVER_DATE "20230117"
25 #define PCI_DEVICE_ID_MTL 0x7d1d
26 #define PCI_DEVICE_ID_LNL 0x643e
28 #define IVPU_HW_37XX 37
29 #define IVPU_HW_40XX 40
31 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
32 /* SSID 1 is used by the VPU to represent invalid context */
33 #define IVPU_USER_CONTEXT_MIN_SSID 2
34 #define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63)
36 #define IVPU_NUM_ENGINES 2
38 #define IVPU_PLATFORM_SILICON 0
39 #define IVPU_PLATFORM_SIMICS 2
40 #define IVPU_PLATFORM_FPGA 3
41 #define IVPU_PLATFORM_INVALID 8
43 #define IVPU_DBG_REG BIT(0)
44 #define IVPU_DBG_IRQ BIT(1)
45 #define IVPU_DBG_MMU BIT(2)
46 #define IVPU_DBG_FILE BIT(3)
47 #define IVPU_DBG_MISC BIT(4)
48 #define IVPU_DBG_FW_BOOT BIT(5)
49 #define IVPU_DBG_PM BIT(6)
50 #define IVPU_DBG_IPC BIT(7)
51 #define IVPU_DBG_BO BIT(8)
52 #define IVPU_DBG_JOB BIT(9)
53 #define IVPU_DBG_JSM BIT(10)
54 #define IVPU_DBG_KREF BIT(11)
55 #define IVPU_DBG_RPM BIT(12)
57 #define ivpu_err(vdev, fmt, ...) \
58 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
60 #define ivpu_err_ratelimited(vdev, fmt, ...) \
61 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
63 #define ivpu_warn(vdev, fmt, ...) \
64 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
66 #define ivpu_warn_ratelimited(vdev, fmt, ...) \
67 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
69 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
71 #define ivpu_dbg(vdev, type, fmt, args...) do { \
72 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \
73 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \
76 #define IVPU_WA(wa_name) (vdev->wa.wa_name)
78 struct ivpu_wa_table {
80 bool clear_runtime_mem;
81 bool d3hot_after_power_off;
82 bool interrupt_clear_with_0;
83 bool disable_clock_relinquish;
93 struct drm_device drm;
99 struct ivpu_wa_table wa;
100 struct ivpu_hw_info *hw;
101 struct ivpu_mmu_info *mmu;
102 struct ivpu_fw_info *fw;
103 struct ivpu_ipc_info *ipc;
104 struct ivpu_pm_info *pm;
106 struct ivpu_mmu_context gctx;
107 struct xarray context_xa;
108 struct xa_limit context_xa_limit;
110 struct xarray submitted_jobs_xa;
111 struct task_struct *job_done_thread;
113 atomic64_t unique_id_counter;
119 int reschedule_suspend;
124 * file_priv has its own refcount (ref) that allows user space to close the fd
125 * without blocking even if VPU is still processing some jobs.
127 struct ivpu_file_priv {
129 struct ivpu_device *vdev;
130 struct mutex lock; /* Protects cmdq */
131 struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES];
132 struct ivpu_mmu_context ctx;
137 extern int ivpu_dbg_mask;
138 extern u8 ivpu_pll_min_ratio;
139 extern u8 ivpu_pll_max_ratio;
140 extern bool ivpu_disable_mmu_cont_pages;
142 #define IVPU_TEST_MODE_DISABLED 0
143 #define IVPU_TEST_MODE_FW_TEST 1
144 #define IVPU_TEST_MODE_NULL_HW 2
145 extern int ivpu_test_mode;
147 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
148 struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id);
149 void ivpu_file_priv_put(struct ivpu_file_priv **link);
151 int ivpu_boot(struct ivpu_device *vdev);
152 int ivpu_shutdown(struct ivpu_device *vdev);
154 static inline u8 ivpu_revision(struct ivpu_device *vdev)
156 return to_pci_dev(vdev->drm.dev)->revision;
159 static inline u16 ivpu_device_id(struct ivpu_device *vdev)
161 return to_pci_dev(vdev->drm.dev)->device;
164 static inline int ivpu_hw_gen(struct ivpu_device *vdev)
166 switch (ivpu_device_id(vdev)) {
167 case PCI_DEVICE_ID_MTL:
169 case PCI_DEVICE_ID_LNL:
172 ivpu_err(vdev, "Unknown VPU device\n");
177 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
179 return container_of(dev, struct ivpu_device, drm);
182 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
184 struct xa_limit ctx_limit = vdev->context_xa_limit;
186 return (ctx_limit.max - ctx_limit.min + 1);
189 static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
191 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
192 return vdev->platform;
195 static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
197 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
200 static inline bool ivpu_is_simics(struct ivpu_device *vdev)
202 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
205 static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
207 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
210 #endif /* __IVPU_DRV_H__ */