1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2023 Intel Corporation
6 #include <linux/firmware.h>
7 #include <linux/module.h>
10 #include <drm/drm_accel.h>
11 #include <drm/drm_file.h>
12 #include <drm/drm_gem.h>
13 #include <drm/drm_ioctl.h>
14 #include <drm/drm_prime.h>
16 #include "vpu_boot_api.h"
17 #include "ivpu_debugfs.h"
24 #include "ivpu_jsm_msg.h"
26 #include "ivpu_mmu_context.h"
29 #ifndef DRIVER_VERSION_STR
30 #define DRIVER_VERSION_STR __stringify(DRM_IVPU_DRIVER_MAJOR) "." \
31 __stringify(DRM_IVPU_DRIVER_MINOR) "."
34 static struct lock_class_key submitted_jobs_xa_lock_class_key;
37 module_param_named(dbg_mask, ivpu_dbg_mask, int, 0644);
38 MODULE_PARM_DESC(dbg_mask, "Driver debug mask. See IVPU_DBG_* macros.");
41 module_param_named_unsafe(test_mode, ivpu_test_mode, int, 0644);
42 MODULE_PARM_DESC(test_mode, "Test mode mask. See IVPU_TEST_MODE_* macros.");
44 u8 ivpu_pll_min_ratio;
45 module_param_named(pll_min_ratio, ivpu_pll_min_ratio, byte, 0644);
46 MODULE_PARM_DESC(pll_min_ratio, "Minimum PLL ratio used to set VPU frequency");
48 u8 ivpu_pll_max_ratio = U8_MAX;
49 module_param_named(pll_max_ratio, ivpu_pll_max_ratio, byte, 0644);
50 MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set VPU frequency");
52 bool ivpu_disable_mmu_cont_pages;
53 module_param_named(disable_mmu_cont_pages, ivpu_disable_mmu_cont_pages, bool, 0644);
54 MODULE_PARM_DESC(disable_mmu_cont_pages, "Disable MMU contiguous pages optimization");
56 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv)
58 struct ivpu_device *vdev = file_priv->vdev;
60 kref_get(&file_priv->ref);
62 ivpu_dbg(vdev, KREF, "file_priv get: ctx %u refcount %u\n",
63 file_priv->ctx.id, kref_read(&file_priv->ref));
68 struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id)
70 struct ivpu_file_priv *file_priv;
72 xa_lock_irq(&vdev->context_xa);
73 file_priv = xa_load(&vdev->context_xa, id);
74 /* file_priv may still be in context_xa during file_priv_release() */
75 if (file_priv && !kref_get_unless_zero(&file_priv->ref))
77 xa_unlock_irq(&vdev->context_xa);
80 ivpu_dbg(vdev, KREF, "file_priv get by id: ctx %u refcount %u\n",
81 file_priv->ctx.id, kref_read(&file_priv->ref));
86 static void file_priv_release(struct kref *ref)
88 struct ivpu_file_priv *file_priv = container_of(ref, struct ivpu_file_priv, ref);
89 struct ivpu_device *vdev = file_priv->vdev;
91 ivpu_dbg(vdev, FILE, "file_priv release: ctx %u\n", file_priv->ctx.id);
93 ivpu_cmdq_release_all(file_priv);
94 ivpu_jsm_context_release(vdev, file_priv->ctx.id);
95 ivpu_bo_remove_all_bos_from_context(vdev, &file_priv->ctx);
96 ivpu_mmu_user_context_fini(vdev, &file_priv->ctx);
97 drm_WARN_ON(&vdev->drm, xa_erase_irq(&vdev->context_xa, file_priv->ctx.id) != file_priv);
98 mutex_destroy(&file_priv->lock);
102 void ivpu_file_priv_put(struct ivpu_file_priv **link)
104 struct ivpu_file_priv *file_priv = *link;
105 struct ivpu_device *vdev = file_priv->vdev;
107 drm_WARN_ON(&vdev->drm, !file_priv);
109 ivpu_dbg(vdev, KREF, "file_priv put: ctx %u refcount %u\n",
110 file_priv->ctx.id, kref_read(&file_priv->ref));
113 kref_put(&file_priv->ref, file_priv_release);
116 static int ivpu_get_capabilities(struct ivpu_device *vdev, struct drm_ivpu_param *args)
118 switch (args->index) {
119 case DRM_IVPU_CAP_METRIC_STREAMER:
122 case DRM_IVPU_CAP_DMA_MEMORY_RANGE:
132 static int ivpu_get_core_clock_rate(struct ivpu_device *vdev, u64 *clk_rate)
136 ret = ivpu_rpm_get_if_active(vdev);
140 *clk_rate = ret ? ivpu_hw_reg_pll_freq_get(vdev) : 0;
148 static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
150 struct ivpu_file_priv *file_priv = file->driver_priv;
151 struct ivpu_device *vdev = file_priv->vdev;
152 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
153 struct drm_ivpu_param *args = data;
157 if (!drm_dev_enter(dev, &idx))
160 switch (args->param) {
161 case DRM_IVPU_PARAM_DEVICE_ID:
162 args->value = pdev->device;
164 case DRM_IVPU_PARAM_DEVICE_REVISION:
165 args->value = pdev->revision;
167 case DRM_IVPU_PARAM_PLATFORM_TYPE:
168 args->value = vdev->platform;
170 case DRM_IVPU_PARAM_CORE_CLOCK_RATE:
171 ret = ivpu_get_core_clock_rate(vdev, &args->value);
173 case DRM_IVPU_PARAM_NUM_CONTEXTS:
174 args->value = ivpu_get_context_count(vdev);
176 case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
177 args->value = vdev->hw->ranges.user.start;
179 case DRM_IVPU_PARAM_CONTEXT_PRIORITY:
180 args->value = file_priv->priority;
182 case DRM_IVPU_PARAM_CONTEXT_ID:
183 args->value = file_priv->ctx.id;
185 case DRM_IVPU_PARAM_FW_API_VERSION:
186 if (args->index < VPU_FW_API_VER_NUM) {
187 struct vpu_firmware_header *fw_hdr;
189 fw_hdr = (struct vpu_firmware_header *)vdev->fw->file->data;
190 args->value = fw_hdr->api_version[args->index];
195 case DRM_IVPU_PARAM_ENGINE_HEARTBEAT:
196 ret = ivpu_jsm_get_heartbeat(vdev, args->index, &args->value);
198 case DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID:
199 args->value = (u64)atomic64_inc_return(&vdev->unique_id_counter);
201 case DRM_IVPU_PARAM_TILE_CONFIG:
202 args->value = vdev->hw->tile_fuse;
204 case DRM_IVPU_PARAM_SKU:
205 args->value = vdev->hw->sku;
207 case DRM_IVPU_PARAM_CAPABILITIES:
208 ret = ivpu_get_capabilities(vdev, args);
219 static int ivpu_set_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
221 struct ivpu_file_priv *file_priv = file->driver_priv;
222 struct drm_ivpu_param *args = data;
225 switch (args->param) {
226 case DRM_IVPU_PARAM_CONTEXT_PRIORITY:
227 if (args->value <= DRM_IVPU_CONTEXT_PRIORITY_REALTIME)
228 file_priv->priority = args->value;
239 static int ivpu_open(struct drm_device *dev, struct drm_file *file)
241 struct ivpu_device *vdev = to_ivpu_device(dev);
242 struct ivpu_file_priv *file_priv;
247 ret = xa_alloc_irq(&vdev->context_xa, &ctx_id, NULL, vdev->context_xa_limit, GFP_KERNEL);
249 ivpu_err(vdev, "Failed to allocate context id: %d\n", ret);
253 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
259 file_priv->vdev = vdev;
260 file_priv->priority = DRM_IVPU_CONTEXT_PRIORITY_NORMAL;
261 kref_init(&file_priv->ref);
262 mutex_init(&file_priv->lock);
264 ret = ivpu_mmu_user_context_init(vdev, &file_priv->ctx, ctx_id);
266 goto err_mutex_destroy;
268 old = xa_store_irq(&vdev->context_xa, ctx_id, file_priv, GFP_KERNEL);
269 if (xa_is_err(old)) {
271 ivpu_err(vdev, "Failed to store context %u: %d\n", ctx_id, ret);
275 ivpu_dbg(vdev, FILE, "file_priv create: ctx %u process %s pid %d\n",
276 ctx_id, current->comm, task_pid_nr(current));
278 file->driver_priv = file_priv;
282 ivpu_mmu_user_context_fini(vdev, &file_priv->ctx);
284 mutex_destroy(&file_priv->lock);
287 xa_erase_irq(&vdev->context_xa, ctx_id);
291 static void ivpu_postclose(struct drm_device *dev, struct drm_file *file)
293 struct ivpu_file_priv *file_priv = file->driver_priv;
294 struct ivpu_device *vdev = to_ivpu_device(dev);
296 ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n",
297 file_priv->ctx.id, current->comm, task_pid_nr(current));
299 ivpu_file_priv_put(&file_priv);
302 static const struct drm_ioctl_desc ivpu_drm_ioctls[] = {
303 DRM_IOCTL_DEF_DRV(IVPU_GET_PARAM, ivpu_get_param_ioctl, 0),
304 DRM_IOCTL_DEF_DRV(IVPU_SET_PARAM, ivpu_set_param_ioctl, 0),
305 DRM_IOCTL_DEF_DRV(IVPU_BO_CREATE, ivpu_bo_create_ioctl, 0),
306 DRM_IOCTL_DEF_DRV(IVPU_BO_INFO, ivpu_bo_info_ioctl, 0),
307 DRM_IOCTL_DEF_DRV(IVPU_SUBMIT, ivpu_submit_ioctl, 0),
308 DRM_IOCTL_DEF_DRV(IVPU_BO_WAIT, ivpu_bo_wait_ioctl, 0),
311 static int ivpu_wait_for_ready(struct ivpu_device *vdev)
313 struct ivpu_ipc_consumer cons;
314 struct ivpu_ipc_hdr ipc_hdr;
315 unsigned long timeout;
318 if (ivpu_test_mode & IVPU_TEST_MODE_FW_TEST)
321 ivpu_ipc_consumer_add(vdev, &cons, IVPU_IPC_CHAN_BOOT_MSG);
323 timeout = jiffies + msecs_to_jiffies(vdev->timeout.boot);
325 ret = ivpu_ipc_irq_handler(vdev);
328 ret = ivpu_ipc_receive(vdev, &cons, &ipc_hdr, NULL, 0);
329 if (ret != -ETIMEDOUT || time_after_eq(jiffies, timeout))
335 ivpu_ipc_consumer_del(vdev, &cons);
337 if (!ret && ipc_hdr.data_addr != IVPU_IPC_BOOT_MSG_DATA_ADDR) {
338 ivpu_err(vdev, "Invalid VPU ready message: 0x%x\n",
344 ivpu_info(vdev, "VPU ready message received successfully\n");
346 ivpu_hw_diagnose_failure(vdev);
352 * ivpu_boot() - Start VPU firmware
355 * This function is paired with ivpu_shutdown() but it doesn't power up the
356 * VPU because power up has to be called very early in ivpu_probe().
358 int ivpu_boot(struct ivpu_device *vdev)
362 /* Update boot params located at first 4KB of FW memory */
363 ivpu_fw_boot_params_setup(vdev, ivpu_bo_vaddr(vdev->fw->mem));
365 ret = ivpu_hw_boot_fw(vdev);
367 ivpu_err(vdev, "Failed to start the firmware: %d\n", ret);
371 ret = ivpu_wait_for_ready(vdev);
373 ivpu_err(vdev, "Failed to boot the firmware: %d\n", ret);
377 ivpu_hw_irq_clear(vdev);
378 enable_irq(vdev->irq);
379 ivpu_hw_irq_enable(vdev);
380 ivpu_ipc_enable(vdev);
381 ivpu_job_done_thread_enable(vdev);
385 int ivpu_shutdown(struct ivpu_device *vdev)
389 ivpu_hw_irq_disable(vdev);
390 disable_irq(vdev->irq);
391 ivpu_ipc_disable(vdev);
392 ivpu_mmu_disable(vdev);
393 ivpu_job_done_thread_disable(vdev);
395 ret = ivpu_hw_power_down(vdev);
397 ivpu_warn(vdev, "Failed to power down HW: %d\n", ret);
402 static const struct file_operations ivpu_fops = {
403 .owner = THIS_MODULE,
407 static const struct drm_driver driver = {
408 .driver_features = DRIVER_GEM | DRIVER_COMPUTE_ACCEL,
411 .postclose = ivpu_postclose,
413 .gem_create_object = ivpu_gem_create_object,
414 .gem_prime_import_sg_table = drm_gem_shmem_prime_import_sg_table,
416 .ioctls = ivpu_drm_ioctls,
417 .num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
423 .major = DRM_IVPU_DRIVER_MAJOR,
424 .minor = DRM_IVPU_DRIVER_MINOR,
427 static int ivpu_irq_init(struct ivpu_device *vdev)
429 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
432 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);
434 ivpu_err(vdev, "Failed to allocate a MSI IRQ: %d\n", ret);
438 vdev->irq = pci_irq_vector(pdev, 0);
440 ret = devm_request_irq(vdev->drm.dev, vdev->irq, vdev->hw->ops->irq_handler,
441 IRQF_NO_AUTOEN, DRIVER_NAME, vdev);
443 ivpu_err(vdev, "Failed to request an IRQ %d\n", ret);
448 static int ivpu_pci_init(struct ivpu_device *vdev)
450 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
451 struct resource *bar0 = &pdev->resource[0];
452 struct resource *bar4 = &pdev->resource[4];
455 ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0);
456 vdev->regv = devm_ioremap_resource(vdev->drm.dev, bar0);
457 if (IS_ERR(vdev->regv)) {
458 ivpu_err(vdev, "Failed to map bar 0: %pe\n", vdev->regv);
459 return PTR_ERR(vdev->regv);
462 ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4);
463 vdev->regb = devm_ioremap_resource(vdev->drm.dev, bar4);
464 if (IS_ERR(vdev->regb)) {
465 ivpu_err(vdev, "Failed to map bar 4: %pe\n", vdev->regb);
466 return PTR_ERR(vdev->regb);
469 ret = dma_set_mask_and_coherent(vdev->drm.dev, DMA_BIT_MASK(vdev->hw->dma_bits));
471 ivpu_err(vdev, "Failed to set DMA mask: %d\n", ret);
474 dma_set_max_seg_size(vdev->drm.dev, UINT_MAX);
476 /* Clear any pending errors */
477 pcie_capability_clear_word(pdev, PCI_EXP_DEVSTA, 0x3f);
479 /* VPU 37XX does not require 10m D3hot delay */
480 if (ivpu_hw_gen(vdev) == IVPU_HW_37XX)
481 pdev->d3hot_delay = 0;
483 ret = pcim_enable_device(pdev);
485 ivpu_err(vdev, "Failed to enable PCI device: %d\n", ret);
489 pci_set_master(pdev);
494 static int ivpu_dev_init(struct ivpu_device *vdev)
498 vdev->hw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->hw), GFP_KERNEL);
502 vdev->mmu = drmm_kzalloc(&vdev->drm, sizeof(*vdev->mmu), GFP_KERNEL);
506 vdev->fw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->fw), GFP_KERNEL);
510 vdev->ipc = drmm_kzalloc(&vdev->drm, sizeof(*vdev->ipc), GFP_KERNEL);
514 vdev->pm = drmm_kzalloc(&vdev->drm, sizeof(*vdev->pm), GFP_KERNEL);
518 if (ivpu_hw_gen(vdev) >= IVPU_HW_40XX) {
519 vdev->hw->ops = &ivpu_hw_40xx_ops;
520 vdev->hw->dma_bits = 48;
522 vdev->hw->ops = &ivpu_hw_37xx_ops;
523 vdev->hw->dma_bits = 38;
526 vdev->platform = IVPU_PLATFORM_INVALID;
527 vdev->context_xa_limit.min = IVPU_USER_CONTEXT_MIN_SSID;
528 vdev->context_xa_limit.max = IVPU_USER_CONTEXT_MAX_SSID;
529 atomic64_set(&vdev->unique_id_counter, 0);
530 xa_init_flags(&vdev->context_xa, XA_FLAGS_ALLOC);
531 xa_init_flags(&vdev->submitted_jobs_xa, XA_FLAGS_ALLOC1);
532 lockdep_set_class(&vdev->submitted_jobs_xa.xa_lock, &submitted_jobs_xa_lock_class_key);
533 INIT_LIST_HEAD(&vdev->bo_list);
535 ret = drmm_mutex_init(&vdev->drm, &vdev->bo_list_lock);
539 ret = ivpu_pci_init(vdev);
543 ret = ivpu_irq_init(vdev);
547 /* Init basic HW info based on buttress registers which are accessible before power up */
548 ret = ivpu_hw_info_init(vdev);
552 /* Power up early so the rest of init code can access VPU registers */
553 ret = ivpu_hw_power_up(vdev);
557 ret = ivpu_mmu_global_context_init(vdev);
561 ret = ivpu_mmu_init(vdev);
563 goto err_mmu_gctx_fini;
565 ret = ivpu_mmu_reserved_context_init(vdev);
567 goto err_mmu_gctx_fini;
569 ret = ivpu_fw_init(vdev);
571 goto err_mmu_rctx_fini;
573 ret = ivpu_ipc_init(vdev);
579 ret = ivpu_job_done_thread_init(vdev);
583 ret = ivpu_boot(vdev);
585 goto err_job_done_thread_fini;
587 ivpu_pm_enable(vdev);
591 err_job_done_thread_fini:
592 ivpu_job_done_thread_fini(vdev);
598 ivpu_mmu_reserved_context_fini(vdev);
600 ivpu_mmu_global_context_fini(vdev);
602 ivpu_hw_power_down(vdev);
603 if (IVPU_WA(d3hot_after_power_off))
604 pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot);
606 xa_destroy(&vdev->submitted_jobs_xa);
607 xa_destroy(&vdev->context_xa);
611 static void ivpu_dev_fini(struct ivpu_device *vdev)
613 ivpu_pm_disable(vdev);
615 if (IVPU_WA(d3hot_after_power_off))
616 pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot);
617 ivpu_job_done_thread_fini(vdev);
618 ivpu_pm_cancel_recovery(vdev);
622 ivpu_mmu_reserved_context_fini(vdev);
623 ivpu_mmu_global_context_fini(vdev);
625 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa));
626 xa_destroy(&vdev->submitted_jobs_xa);
627 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->context_xa));
628 xa_destroy(&vdev->context_xa);
631 static struct pci_device_id ivpu_pci_ids[] = {
632 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_MTL) },
633 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_LNL) },
636 MODULE_DEVICE_TABLE(pci, ivpu_pci_ids);
638 static int ivpu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
640 struct ivpu_device *vdev;
643 vdev = devm_drm_dev_alloc(&pdev->dev, &driver, struct ivpu_device, drm);
645 return PTR_ERR(vdev);
647 pci_set_drvdata(pdev, vdev);
649 ret = ivpu_dev_init(vdev);
653 ivpu_debugfs_init(vdev);
655 ret = drm_dev_register(&vdev->drm, 0);
657 dev_err(&pdev->dev, "Failed to register DRM device: %d\n", ret);
664 static void ivpu_remove(struct pci_dev *pdev)
666 struct ivpu_device *vdev = pci_get_drvdata(pdev);
668 drm_dev_unplug(&vdev->drm);
672 static const struct dev_pm_ops ivpu_drv_pci_pm = {
673 SET_SYSTEM_SLEEP_PM_OPS(ivpu_pm_suspend_cb, ivpu_pm_resume_cb)
674 SET_RUNTIME_PM_OPS(ivpu_pm_runtime_suspend_cb, ivpu_pm_runtime_resume_cb, NULL)
677 static const struct pci_error_handlers ivpu_drv_pci_err = {
678 .reset_prepare = ivpu_pm_reset_prepare_cb,
679 .reset_done = ivpu_pm_reset_done_cb,
682 static struct pci_driver ivpu_pci_driver = {
683 .name = KBUILD_MODNAME,
684 .id_table = ivpu_pci_ids,
686 .remove = ivpu_remove,
688 .pm = &ivpu_drv_pci_pm,
690 .err_handler = &ivpu_drv_pci_err,
693 module_pci_driver(ivpu_pci_driver);
695 MODULE_AUTHOR("Intel Corporation");
696 MODULE_DESCRIPTION(DRIVER_DESC);
697 MODULE_LICENSE("GPL and additional rights");
698 MODULE_VERSION(DRIVER_VERSION_STR);