1 # SPDX-License-Identifier: GPL-2.0
4 select ARCH_32BIT_OFF_T
5 select ARCH_HAS_BINFMT_FLAT if !MMU
6 select ARCH_HAS_CURRENT_STACK_POINTER
7 select ARCH_HAS_DEBUG_VM_PGTABLE
8 select ARCH_HAS_DMA_PREP_COHERENT if MMU
9 select ARCH_HAS_GCOV_PROFILE_ALL
11 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU
12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU
13 select ARCH_HAS_DMA_SET_UNCACHED if MMU
14 select ARCH_HAS_STRNCPY_FROM_USER if !KASAN
15 select ARCH_HAS_STRNLEN_USER
16 select ARCH_USE_MEMTEST
17 select ARCH_USE_QUEUED_RWLOCKS
18 select ARCH_USE_QUEUED_SPINLOCKS
19 select ARCH_WANT_IPC_PARSE_VERSION
20 select BUILDTIME_TABLE_SORT
21 select CLONE_BACKWARDS
23 select DMA_NONCOHERENT_MMAP if MMU
24 select GENERIC_ATOMIC64
25 select GENERIC_IRQ_SHOW
26 select GENERIC_LIB_CMPDI2
27 select GENERIC_LIB_MULDI3
28 select GENERIC_LIB_UCMPDI2
29 select GENERIC_PCI_IOMAP
30 select GENERIC_SCHED_CLOCK
31 select GENERIC_IOREMAP if MMU
32 select HAVE_ARCH_AUDITSYSCALL
33 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
34 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
35 select HAVE_ARCH_KCSAN
36 select HAVE_ARCH_SECCOMP_FILTER
37 select HAVE_ARCH_TRACEHOOK
38 select HAVE_ASM_MODVERSIONS
39 select HAVE_CONTEXT_TRACKING_USER
40 select HAVE_DEBUG_KMEMLEAK
41 select HAVE_DMA_CONTIGUOUS
42 select HAVE_EXIT_THREAD
43 select HAVE_FUNCTION_TRACER
44 select HAVE_GCC_PLUGINS if GCC_VERSION >= 120000
45 select HAVE_HW_BREAKPOINT if PERF_EVENTS
46 select HAVE_IRQ_TIME_ACCOUNTING
47 select HAVE_PAGE_SIZE_4KB
49 select HAVE_PERF_EVENTS
50 select HAVE_STACKPROTECTOR
51 select HAVE_SYSCALL_TRACEPOINTS
52 select HAVE_VIRT_CPU_ACCOUNTING_GEN
54 select LOCK_MM_AND_FIND_VMA
55 select MODULES_USE_ELF_RELA
56 select PERF_USE_VMALLOC
57 select TRACE_IRQFLAGS_SUPPORT
59 Xtensa processors are 32-bit RISC machines designed by Tensilica
60 primarily for embedded systems. These processors are both
61 configurable and extensible. The Linux port to the Xtensa
62 architecture supports all processor configurations and extensions,
63 with reasonable minimum requirements. The Xtensa Linux project has
64 a home page at <http://www.linux-xtensa.org/>.
66 config GENERIC_HWEIGHT
69 config ARCH_HAS_ILOG2_U32
72 config ARCH_HAS_ILOG2_U64
85 config LOCKDEP_SUPPORT
88 config STACKTRACE_SUPPORT
95 config HAVE_XTENSA_GPIO32
98 config KASAN_SHADOW_OFFSET
102 config CPU_BIG_ENDIAN
103 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
105 config CPU_LITTLE_ENDIAN
106 def_bool !CPU_BIG_ENDIAN
108 config CC_HAVE_CALL0_ABI
109 def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null)" = 1)
111 menu "Processor type and features"
114 prompt "Xtensa Processor Configuration"
115 default XTENSA_VARIANT_FSF
117 config XTENSA_VARIANT_FSF
118 bool "fsf - default (not generic) configuration"
121 config XTENSA_VARIANT_DC232B
122 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
124 select HAVE_XTENSA_GPIO32
126 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
128 config XTENSA_VARIANT_DC233C
129 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
131 select HAVE_XTENSA_GPIO32
133 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
135 config XTENSA_VARIANT_CUSTOM
136 bool "Custom Xtensa processor configuration"
137 select HAVE_XTENSA_GPIO32
139 Select this variant to use a custom Xtensa processor configuration.
140 You will be prompted for a processor variant CORENAME.
143 config XTENSA_VARIANT_CUSTOM_NAME
144 string "Xtensa Processor Custom Core Variant Name"
145 depends on XTENSA_VARIANT_CUSTOM
147 Provide the name of a custom Xtensa processor variant.
148 This CORENAME selects arch/xtensa/variants/CORENAME.
149 Don't forget you have to select MMU if you have one.
151 config XTENSA_VARIANT_NAME
153 default "dc232b" if XTENSA_VARIANT_DC232B
154 default "dc233c" if XTENSA_VARIANT_DC233C
155 default "fsf" if XTENSA_VARIANT_FSF
156 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM
158 config XTENSA_VARIANT_MMU
159 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
160 depends on XTENSA_VARIANT_CUSTOM
164 Build a Conventional Kernel with full MMU support,
165 ie: it supports a TLB with auto-loading, page protection.
167 config XTENSA_VARIANT_HAVE_PERF_EVENTS
168 bool "Core variant has Performance Monitor Module"
169 depends on XTENSA_VARIANT_CUSTOM
172 Enable if core variant has Performance Monitor Module with
173 External Registers Interface.
177 config XTENSA_FAKE_NMI
178 bool "Treat PMM IRQ as NMI"
179 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS
182 If PMM IRQ is the only IRQ at EXCM level it is safe to
183 treat it as NMI, which improves accuracy of profiling.
185 If there are other interrupts at or above PMM IRQ priority level
186 but not above the EXCM level, PMM IRQ still may be treated as NMI,
187 but only if these IRQs are not used. There will be a build warning
188 saying that this is not safe, and a bugcheck if one of these IRQs
194 bool "Handle protection faults" if EXPERT && !MMU
197 Handle protection faults. MMU configurations must enable it.
198 noMMU configurations may disable it if used memory map never
199 generates protection faults or faults are always fatal.
203 config XTENSA_UNALIGNED_USER
204 bool "Unaligned memory access in user space"
206 The Xtensa architecture currently does not handle unaligned
207 memory accesses in hardware but through an exception handler.
208 Per default, unaligned memory accesses are disabled in user space.
210 Say Y here to enable unaligned memory access in user space.
212 config XTENSA_LOAD_STORE
213 bool "Load/store exception handler for memory only readable with l32"
215 The Xtensa architecture only allows reading memory attached to its
216 instruction bus with l32r and l32i instructions, all other
217 instructions raise an exception with the LoadStoreErrorCause code.
218 This makes it hard to use some configurations, e.g. store string
219 literals in FLASH memory attached to the instruction bus.
221 Say Y here to enable exception handler that allows transparent
222 byte and 2-byte access to memory attached to instruction bus.
225 bool "System Supports SMP (MX)"
226 depends on XTENSA_VARIANT_CUSTOM
229 This option is used to indicate that the system-on-a-chip (SOC)
230 supports Multiprocessing. Multiprocessor support implemented above
231 the CPU core definition and currently needs to be selected manually.
233 Multiprocessor support is implemented with external cache and
234 interrupt controllers.
236 The MX interrupt distributer adds Interprocessor Interrupts
237 and causes the IRQ numbers to be increased by 4 for devices
238 like the open cores ethernet driver and the serial interface.
240 You still have to select "Enable SMP" to enable SMP on this SOC.
243 bool "Enable Symmetric multi-processing support"
245 select GENERIC_SMP_IDLE_THREAD
247 Enabled SMP Software; allows more than one CPU/CORE
248 to be activated during startup.
252 int "Maximum number of CPUs (2-32)"
257 bool "Enable CPU hotplug support"
260 Say Y here to allow turning CPUs off and on. CPUs can be
261 controlled through /sys/devices/system/cpu.
263 Say N if you want to disable CPU hotplug.
265 config SECONDARY_RESET_VECTOR
266 bool "Secondary cores use alternative reset vector"
270 Secondary cores may be configured to use alternative reset vector,
271 or all cores may use primary reset vector.
272 Say Y here to supply handler for the alternative reset location.
274 config FAST_SYSCALL_XTENSA
275 bool "Enable fast atomic syscalls"
278 fast_syscall_xtensa is a syscall that can make atomic operations
279 on UP kernel when processor has no s32c1i support.
281 This syscall is deprecated. It may have issues when called with
282 invalid arguments. It is provided only for backwards compatibility.
283 Only enable it if your userspace software requires it.
287 config FAST_SYSCALL_SPILL_REGISTERS
288 bool "Enable spill registers syscall"
291 fast_syscall_spill_registers is a syscall that spills all active
292 register windows of a calling userspace task onto its stack.
294 This syscall is deprecated. It may have issues when called with
295 invalid arguments. It is provided only for backwards compatibility.
296 Only enable it if your userspace software requires it.
302 default KERNEL_ABI_DEFAULT
304 Select ABI for the kernel code. This ABI is independent of the
305 supported userspace ABI and any combination of the
306 kernel/userspace ABI is possible and should work.
308 In case both kernel and userspace support only call0 ABI
309 all register windows support code will be omitted from the
312 If unsure, choose the default ABI.
314 config KERNEL_ABI_DEFAULT
317 Select this option to compile kernel code with the default ABI
318 selected for the toolchain.
319 Normally cores with windowed registers option use windowed ABI and
320 cores without it use call0 ABI.
322 config KERNEL_ABI_CALL0
323 bool "Call0 ABI" if CC_HAVE_CALL0_ABI
325 Select this option to compile kernel code with call0 ABI even with
326 toolchain that defaults to windowed ABI.
327 When this option is not selected the default toolchain ABI will
328 be used for the kernel code.
332 config USER_ABI_CALL0
336 prompt "Userspace ABI"
337 default USER_ABI_DEFAULT
339 Select supported userspace ABI.
341 If unsure, choose the default ABI.
343 config USER_ABI_DEFAULT
344 bool "Default ABI only"
346 Assume default userspace ABI. For XEA2 cores it is windowed ABI.
347 call0 ABI binaries may be run on such kernel, but signal delivery
348 will not work correctly for them.
350 config USER_ABI_CALL0_ONLY
351 bool "Call0 ABI only"
352 select USER_ABI_CALL0
354 Select this option to support only call0 ABI in userspace.
355 Windowed ABI binaries will crash with a segfault caused by
356 an illegal instruction exception on the first 'entry' opcode.
358 Choose this option if you're planning to run only user code
359 built with call0 ABI.
361 config USER_ABI_CALL0_PROBE
362 bool "Support both windowed and call0 ABI by probing"
363 select USER_ABI_CALL0
365 Select this option to support both windowed and call0 userspace
366 ABIs. When enabled all processes are started with PS.WOE disabled
367 and a fast user exception handler for an illegal instruction is
368 used to turn on PS.WOE bit on the first 'entry' opcode executed by
371 This option should be enabled for the kernel that must support
372 both call0 and windowed ABIs in userspace at the same time.
374 Note that Xtensa ISA does not guarantee that entry opcode will
375 raise an illegal instruction exception on cores with XEA2 when
376 PS.WOE is disabled, check whether the target core supports it.
382 config XTENSA_CALIBRATE_CCOUNT
385 On some platforms (XT2000, for example), the CPU clock rate can
386 vary. The frequency can be determined, however, by measuring
387 against a well known, fixed frequency, such as an UART oscillator.
389 config SERIAL_CONSOLE
392 config PLATFORM_HAVE_XIP
395 menu "Platform options"
398 prompt "Xtensa System Type"
399 default XTENSA_PLATFORM_ISS
401 config XTENSA_PLATFORM_ISS
403 select XTENSA_CALIBRATE_CCOUNT
404 select SERIAL_CONSOLE
406 ISS is an acronym for Tensilica's Instruction Set Simulator.
408 config XTENSA_PLATFORM_XT2000
411 XT2000 is the name of Tensilica's feature-rich emulation platform.
412 This hardware is capable of running a full Linux distribution.
414 config XTENSA_PLATFORM_XTFPGA
416 select ETHOC if ETHERNET
417 select PLATFORM_WANT_DEFAULT_MEM if !MMU
418 select SERIAL_CONSOLE
419 select XTENSA_CALIBRATE_CCOUNT
420 select PLATFORM_HAVE_XIP
422 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
423 This hardware is capable of running a full Linux distribution.
427 config PLATFORM_NR_IRQS
429 default 3 if XTENSA_PLATFORM_XT2000
432 config XTENSA_CPU_CLOCK
433 int "CPU clock rate [MHz]"
434 depends on !XTENSA_CALIBRATE_CCOUNT
437 config GENERIC_CALIBRATE_DELAY
438 bool "Auto calibration of the BogoMIPS value"
440 The BogoMIPS value can easily be derived from the CPU frequency.
443 bool "Default bootloader kernel arguments"
446 string "Initial kernel command string"
447 depends on CMDLINE_BOOL
448 default "console=ttyS0,38400 root=/dev/ram"
450 On some architectures (EBSA110 and CATS), there is currently no way
451 for the boot loader to pass arguments to the kernel. For these
452 architectures, you should supply some command-line options at build
453 time by entering them here. As a minimum, you should specify the
454 memory size and the root device (e.g., mem=64M root=/dev/nfs).
457 bool "Flattened Device Tree support"
459 select OF_EARLY_FLATTREE
461 Include support for flattened device tree machine descriptions.
463 config BUILTIN_DTB_SOURCE
464 string "DTB to build into the kernel image"
467 config PARSE_BOOTPARAM
468 bool "Parse bootparam block"
471 Parse parameters passed to the kernel from the bootloader. It may
472 be disabled if the kernel is known to run without the bootloader.
477 prompt "Semihosting interface"
478 default XTENSA_SIMCALL_ISS
479 depends on XTENSA_PLATFORM_ISS
481 Choose semihosting interface that will be used for serial port,
482 block device and networking.
484 config XTENSA_SIMCALL_ISS
487 Use simcall instruction. simcall is only available on simulators,
488 it does nothing on hardware.
490 config XTENSA_SIMCALL_GDBIO
493 Use break instruction. It is available on real hardware when GDB
494 is attached to it via JTAG.
498 config BLK_DEV_SIMDISK
499 tristate "Host file-based simulated block device support"
501 depends on XTENSA_PLATFORM_ISS && BLOCK
503 Create block devices that map to files in the host file system.
504 Device binding to host file may be changed at runtime via proc
505 interface provided the device is not in use.
507 config BLK_DEV_SIMDISK_COUNT
508 int "Number of host file-based simulated block devices"
510 depends on BLK_DEV_SIMDISK
513 This is the default minimal number of created block devices.
514 Kernel/module parameter 'simdisk_count' may be used to change this
515 value at runtime. More file names (but no more than 10) may be
516 specified as parameters, simdisk_count grows accordingly.
518 config SIMDISK0_FILENAME
519 string "Host filename for the first simulated device"
520 depends on BLK_DEV_SIMDISK = y
523 Attach a first simdisk to a host file. Conventionally, this file
524 contains a root file system.
526 config SIMDISK1_FILENAME
527 string "Host filename for the second simulated device"
528 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1
531 Another simulated disk in a host file for a buildroot-independent
535 bool "Enable XTFPGA LCD driver"
536 depends on XTENSA_PLATFORM_XTFPGA
539 There's a 2x16 LCD on most of XTFPGA boards, kernel may output
540 progress messages there during bootup/shutdown. It may be useful
541 during board bringup.
545 config XTFPGA_LCD_BASE_ADDR
546 hex "XTFPGA LCD base address"
547 depends on XTFPGA_LCD
550 Base address of the LCD controller inside KIO region.
551 Different boards from XTFPGA family have LCD controller at different
552 addresses. Please consult prototyping user guide for your board for
553 the correct address. Wrong address here may lead to hardware lockup.
555 config XTFPGA_LCD_8BIT_ACCESS
556 bool "Use 8-bit access to XTFPGA LCD"
557 depends on XTFPGA_LCD
560 LCD may be connected with 4- or 8-bit interface, 8-bit access may
561 only be used with 8-bit interface. Please consult prototyping user
562 guide for your board for the correct interface width.
564 comment "Kernel memory layout"
566 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
567 bool "Initialize Xtensa MMU inside the Linux kernel code"
568 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B
569 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM
571 Earlier version initialized the MMU in the exception vector
572 before jumping to _startup in head.S and had an advantage that
573 it was possible to place a software breakpoint at 'reset' and
574 then enter your normal kernel breakpoints once the MMU was mapped
575 to the kernel mappings (0XC0000000).
577 This unfortunately won't work for U-Boot and likely also won't
578 work for using KEXEC to have a hot kernel ready for doing a
581 So now the MMU is initialized in head.S but it's necessary to
582 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup.
583 xt-gdb can't place a Software Breakpoint in the 0XD region prior
584 to mapping the MMU and after mapping even if the area of low memory
585 was mapped gdb wouldn't remove the breakpoint on hitting it as the
586 PC wouldn't match. Since Hardware Breakpoints are recommended for
587 Linux configurations it seems reasonable to just assume they exist
588 and leave this older mechanism for unfortunate souls that choose
589 not to follow Tensilica's recommendation.
591 Selecting this will cause U-Boot to set the KERNEL Load and Entry
592 address at 0x00003000 instead of the mapped std of 0xD0003000.
597 bool "Kernel Execute-In-Place from ROM"
598 depends on PLATFORM_HAVE_XIP
600 Execute-In-Place allows the kernel to run from non-volatile storage
601 directly addressable by the CPU, such as NOR flash. This saves RAM
602 space since the text section of the kernel is not loaded from flash
603 to RAM. Read-write sections, such as the data section and stack,
604 are still copied to RAM. The XIP kernel is not compressed since
605 it has to run directly from flash, so it will take more space to
606 store it. The flash address used to link the kernel object files,
607 and for storing it, is configuration dependent. Therefore, if you
608 say Y here, you must know the proper physical address where to
609 store the kernel image depending on your own flash memory usage.
611 Also note that the make target becomes "make xipImage" rather than
612 "make Image" or "make uImage". The final kernel binary to put in
613 ROM memory will be arch/xtensa/boot/xipImage.
617 config MEMMAP_CACHEATTR
618 hex "Cache attributes for the memory address space"
622 These cache attributes are set up for noMMU systems. Each hex digit
623 specifies cache attributes for the corresponding 512MB memory
624 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
625 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
627 Cache attribute values are specific for the MMU type.
628 For region protection MMUs:
640 3: special (c and e are illegal, f is reserved).
644 2: WB, no-write-allocate cache,
649 hex "Physical address of the KSEG mapping"
650 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
653 This is the physical address where KSEG is mapped. Please refer to
654 the chosen KSEG layout help for the required address alignment.
655 Unpacked kernel image (including vectors) must be located completely
657 Physical memory below this address is not available to linux.
659 If unsure, leave the default value here.
661 config KERNEL_VIRTUAL_ADDRESS
662 hex "Kernel virtual address"
663 depends on MMU && XIP_KERNEL
666 This is the virtual address where the XIP kernel is mapped.
667 XIP kernel may be mapped into KSEG or KIO region, virtual address
668 provided here must match kernel load address provided in
671 config KERNEL_LOAD_ADDRESS
672 hex "Kernel load address"
673 default 0x60003000 if !MMU
674 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
675 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
677 This is the address where the kernel is loaded.
678 It is virtual address for MMUv2 configurations and physical address
679 for all other configurations.
681 If unsure, leave the default value here.
684 prompt "Relocatable vectors location"
685 default XTENSA_VECTORS_IN_TEXT
687 Choose whether relocatable vectors are merged into the kernel .text
688 or placed separately at runtime. This option does not affect
689 configurations without VECBASE register where vectors are always
690 placed at their hardware-defined locations.
692 config XTENSA_VECTORS_IN_TEXT
693 bool "Merge relocatable vectors into kernel text"
696 This option puts relocatable vectors into the kernel .text section
697 with proper alignment.
698 This is a safe choice for most configurations.
700 config XTENSA_VECTORS_SEPARATE
701 bool "Put relocatable vectors at fixed address"
703 This option puts relocatable vectors at specific virtual address.
704 Vectors are merged with the .init data in the kernel image and
705 are copied into their designated location during kernel startup.
706 Use it to put vectors into IRAM or out of FLASH on kernels with
707 XIP-aware MTD support.
712 hex "Kernel vectors virtual address"
714 depends on XTENSA_VECTORS_SEPARATE
716 This is the virtual address of the (relocatable) vectors base.
717 It must be within KSEG if MMU is used.
720 hex "XIP kernel data virtual address"
721 depends on XIP_KERNEL
724 This is the virtual address where XIP kernel data is copied.
725 It must be within KSEG if MMU is used.
727 config PLATFORM_WANT_DEFAULT_MEM
730 config DEFAULT_MEM_START
732 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM
733 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM
736 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET
737 in noMMU configurations.
739 If unsure, leave the default value here.
744 default XTENSA_KSEG_MMU_V2
746 config XTENSA_KSEG_MMU_V2
747 bool "MMUv2: 128MB cached + 128MB uncached"
749 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
750 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000
752 KSEG_PADDR must be aligned to 128MB.
754 config XTENSA_KSEG_256M
755 bool "256MB cached + 256MB uncached"
756 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
758 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
759 with cache and to 0xc0000000 without cache.
760 KSEG_PADDR must be aligned to 256MB.
762 config XTENSA_KSEG_512M
763 bool "512MB cached + 512MB uncached"
764 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
766 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
767 with cache and to 0xc0000000 without cache.
768 KSEG_PADDR must be aligned to 256MB.
773 bool "High Memory Support"
777 Linux can use the full amount of RAM in the system by
778 default. However, the default MMUv2 setup only maps the
779 lowermost 128 MB of memory linearly to the areas starting
780 at 0xd0000000 (cached) and 0xd8000000 (uncached).
781 When there are more than 128 MB memory in the system not
782 all of it can be "permanently mapped" by the kernel.
783 The physical memory that's not permanently mapped is called
786 If you are compiling a kernel which will never run on a
787 machine with more than 128 MB total physical RAM, answer
792 config ARCH_FORCE_MAX_ORDER
793 int "Order of maximal physically contiguous allocations"
796 The kernel page allocator limits the size of maximal physically
797 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
798 defines the maximal power of two of number of pages that can be
799 allocated as a single contiguous block. This option allows
800 overriding the default setting when ability to allocate very
801 large blocks of physically contiguous memory is required.
803 Don't change if unsure.
807 menu "Power management options"
809 config ARCH_HIBERNATION_POSSIBLE
812 source "kernel/power/Kconfig"