2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
6 * - known chipset handling
7 * - ACPI decoding and validation
9 * Per-architecture code takes care of the mappings and accesses
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/acpi.h>
16 #include <linux/bitmap.h>
17 #include <linux/sort.h>
19 #include <asm/pci_x86.h>
21 #define PREFIX "PCI: "
23 /* aperture is up to 256MB but BIOS may reserve less */
24 #define MMCONFIG_APER_MIN (2 * 1024*1024)
25 #define MMCONFIG_APER_MAX (256 * 1024*1024)
27 /* Indicate if the mmcfg resources have been placed into the resource table. */
28 static int __initdata pci_mmcfg_resources_inserted;
30 static __init int extend_mmcfg(int num)
32 struct acpi_mcfg_allocation *new;
33 int new_num = pci_mmcfg_config_num + num;
35 new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
39 if (pci_mmcfg_config) {
40 memcpy(new, pci_mmcfg_config,
41 sizeof(pci_mmcfg_config[0]) * new_num);
42 kfree(pci_mmcfg_config);
44 pci_mmcfg_config = new;
49 static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end)
51 int i = pci_mmcfg_config_num;
53 pci_mmcfg_config_num++;
54 pci_mmcfg_config[i].address = addr;
55 pci_mmcfg_config[i].pci_segment = segment;
56 pci_mmcfg_config[i].start_bus_number = start;
57 pci_mmcfg_config[i].end_bus_number = end;
60 static const char __init *pci_mmcfg_e7520(void)
63 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
66 if (win == 0x0000 || win == 0xf000)
69 if (extend_mmcfg(1) == -1)
72 fill_one_mmcfg(win << 16, 0, 0, 255);
74 return "Intel Corporation E7520 Memory Controller Hub";
77 static const char __init *pci_mmcfg_intel_945(void)
79 u32 pciexbar, mask = 0, len = 0;
81 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
88 switch ((pciexbar >> 1) & 3) {
105 /* Errata #2, things break when not aligned on a 256Mb boundary */
106 /* Can only happen in 64M/128M mode */
108 if ((pciexbar & mask) & 0x0fffffffU)
111 /* Don't hit the APIC registers and their friends */
112 if ((pciexbar & mask) >= 0xf0000000U)
115 if (extend_mmcfg(1) == -1)
118 fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1);
120 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
123 static const char __init *pci_mmcfg_amd_fam10h(void)
125 u32 low, high, address;
128 unsigned segnbits = 0, busnbits;
130 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
133 address = MSR_FAM10H_MMIO_CONF_BASE;
134 if (rdmsr_safe(address, &low, &high))
141 /* mmconfig is not enable */
142 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
145 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
147 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
148 FAM10H_MMIO_CONF_BUSRANGE_MASK;
151 * only handle bus 0 ?
158 segnbits = busnbits - 8;
162 if (extend_mmcfg(1 << segnbits) == -1)
165 for (i = 0; i < (1 << segnbits); i++)
166 fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1);
168 return "AMD Family 10h NB";
171 static bool __initdata mcp55_checked;
172 static const char __init *pci_mmcfg_nvidia_mcp55(void)
175 int mcp55_mmconf_found = 0;
177 static const u32 extcfg_regnum = 0x90;
178 static const u32 extcfg_regsize = 4;
179 static const u32 extcfg_enable_mask = 1<<31;
180 static const u32 extcfg_start_mask = 0xff<<16;
181 static const int extcfg_start_shift = 16;
182 static const u32 extcfg_size_mask = 0x3<<28;
183 static const int extcfg_size_shift = 28;
184 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
185 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
186 static const int extcfg_base_lshift = 25;
189 * do check if amd fam10h already took over
191 if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked)
194 mcp55_checked = true;
195 for (bus = 0; bus < 256; bus++) {
199 int start, size_index, end;
201 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
203 device = (l >> 16) & 0xffff;
205 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
208 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
209 extcfg_regsize, &extcfg);
211 if (!(extcfg & extcfg_enable_mask))
214 if (extend_mmcfg(1) == -1)
217 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
218 base = extcfg & extcfg_base_mask[size_index];
219 /* base could > 4G */
220 base <<= extcfg_base_lshift;
221 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
222 end = start + extcfg_sizebus[size_index] - 1;
223 fill_one_mmcfg(base, 0, start, end);
224 mcp55_mmconf_found++;
227 if (!mcp55_mmconf_found)
230 return "nVidia MCP55";
233 struct pci_mmcfg_hostbridge_probe {
238 const char *(*probe)(void);
241 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
242 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
243 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
244 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
245 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
246 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
247 0x1200, pci_mmcfg_amd_fam10h },
248 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
249 0x1200, pci_mmcfg_amd_fam10h },
250 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
251 0x0369, pci_mmcfg_nvidia_mcp55 },
254 static int __init cmp_mmcfg(const void *x1, const void *x2)
256 const typeof(pci_mmcfg_config[0]) *m1 = x1;
257 const typeof(pci_mmcfg_config[0]) *m2 = x2;
260 start1 = m1->start_bus_number;
261 start2 = m2->start_bus_number;
263 return start1 - start2;
266 static void __init pci_mmcfg_check_end_bus_number(void)
269 typeof(pci_mmcfg_config[0]) *cfg, *cfgx;
271 /* sort them at first */
272 sort(pci_mmcfg_config, pci_mmcfg_config_num,
273 sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);
276 if (pci_mmcfg_config_num > 0) {
277 i = pci_mmcfg_config_num - 1;
278 cfg = &pci_mmcfg_config[i];
279 if (cfg->end_bus_number < cfg->start_bus_number)
280 cfg->end_bus_number = 255;
283 /* don't overlap please */
284 for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
285 cfg = &pci_mmcfg_config[i];
286 cfgx = &pci_mmcfg_config[i+1];
288 if (cfg->end_bus_number < cfg->start_bus_number)
289 cfg->end_bus_number = 255;
291 if (cfg->end_bus_number >= cfgx->start_bus_number)
292 cfg->end_bus_number = cfgx->start_bus_number - 1;
296 static int __init pci_mmcfg_check_hostbridge(void)
307 pci_mmcfg_config_num = 0;
308 pci_mmcfg_config = NULL;
310 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
311 bus = pci_mmcfg_probes[i].bus;
312 devfn = pci_mmcfg_probes[i].devfn;
313 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
315 device = (l >> 16) & 0xffff;
318 if (pci_mmcfg_probes[i].vendor == vendor &&
319 pci_mmcfg_probes[i].device == device)
320 name = pci_mmcfg_probes[i].probe();
323 printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
327 /* some end_bus_number is crazy, fix it */
328 pci_mmcfg_check_end_bus_number();
330 return pci_mmcfg_config_num != 0;
333 static void __init pci_mmcfg_insert_resources(void)
335 #define PCI_MMCFG_RESOURCE_NAME_LEN 24
337 struct resource *res;
341 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
342 pci_mmcfg_config_num, GFP_KERNEL);
344 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
348 names = (void *)&res[pci_mmcfg_config_num];
349 for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
350 struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
351 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
353 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN,
354 "PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment,
355 cfg->start_bus_number, cfg->end_bus_number);
356 res->start = cfg->address + (cfg->start_bus_number << 20);
357 res->end = res->start + (num_buses << 20) - 1;
358 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
359 insert_resource(&iomem_resource, res);
360 names += PCI_MMCFG_RESOURCE_NAME_LEN;
363 /* Mark that the resources have been inserted. */
364 pci_mmcfg_resources_inserted = 1;
367 static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
370 struct resource *mcfg_res = data;
371 struct acpi_resource_address64 address;
374 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
375 struct acpi_resource_fixed_memory32 *fixmem32 =
376 &res->data.fixed_memory32;
379 if ((mcfg_res->start >= fixmem32->address) &&
380 (mcfg_res->end < (fixmem32->address +
381 fixmem32->address_length))) {
383 return AE_CTRL_TERMINATE;
386 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
387 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
390 status = acpi_resource_to_address64(res, &address);
391 if (ACPI_FAILURE(status) ||
392 (address.address_length <= 0) ||
393 (address.resource_type != ACPI_MEMORY_RANGE))
396 if ((mcfg_res->start >= address.minimum) &&
397 (mcfg_res->end < (address.minimum + address.address_length))) {
399 return AE_CTRL_TERMINATE;
404 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
405 void *context, void **rv)
407 struct resource *mcfg_res = context;
409 acpi_walk_resources(handle, METHOD_NAME__CRS,
410 check_mcfg_resource, context);
413 return AE_CTRL_TERMINATE;
418 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
420 struct resource mcfg_res;
422 mcfg_res.start = start;
423 mcfg_res.end = end - 1;
426 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
429 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
432 return mcfg_res.flags;
435 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
437 static int __init is_mmconf_reserved(check_reserved_t is_reserved,
438 u64 addr, u64 size, int i,
439 typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
444 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
446 if (size < (16UL<<20))
450 if (size >= (16UL<<20) || size == old_size) {
452 "PCI: MCFG area at %Lx reserved in %s\n",
453 addr, with_e820?"E820":"ACPI motherboard resources");
456 if (old_size != size) {
457 /* update end_bus_number */
458 cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
459 printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
460 "segment %hu buses %u - %u\n",
461 i, (unsigned long)cfg->address, cfg->pci_segment,
462 (unsigned int)cfg->start_bus_number,
463 (unsigned int)cfg->end_bus_number);
470 static void __init pci_mmcfg_reject_broken(int early)
472 typeof(pci_mmcfg_config[0]) *cfg;
475 if ((pci_mmcfg_config_num == 0) ||
476 (pci_mmcfg_config == NULL) ||
477 (pci_mmcfg_config[0].address == 0))
480 for (i = 0; i < pci_mmcfg_config_num; i++) {
484 cfg = &pci_mmcfg_config[i];
485 addr = cfg->start_bus_number;
487 addr += cfg->address;
488 size = cfg->end_bus_number + 1 - cfg->start_bus_number;
490 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
491 "segment %hu buses %u - %u\n",
492 i, (unsigned long)cfg->address, cfg->pci_segment,
493 (unsigned int)cfg->start_bus_number,
494 (unsigned int)cfg->end_bus_number);
497 valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);
503 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
504 " reserved in ACPI motherboard resources\n",
507 /* Don't try to do this check unless configuration
508 type 1 is available. how about type 2 ?*/
510 valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);
519 printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
520 pci_mmcfg_arch_free();
521 kfree(pci_mmcfg_config);
522 pci_mmcfg_config = NULL;
523 pci_mmcfg_config_num = 0;
526 static int __initdata known_bridge;
528 static int acpi_mcfg_64bit_base_addr __initdata = FALSE;
530 /* The physical address of the MMCONFIG aperture. Set from ACPI tables. */
531 struct acpi_mcfg_allocation *pci_mmcfg_config;
532 int pci_mmcfg_config_num;
534 static int __init acpi_mcfg_oem_check(struct acpi_table_mcfg *mcfg)
536 if (!strcmp(mcfg->header.oem_id, "SGI"))
537 acpi_mcfg_64bit_base_addr = TRUE;
542 static int __init pci_parse_mcfg(struct acpi_table_header *header)
544 struct acpi_table_mcfg *mcfg;
551 mcfg = (struct acpi_table_mcfg *)header;
553 /* how many config structures do we have */
554 pci_mmcfg_config_num = 0;
555 i = header->length - sizeof(struct acpi_table_mcfg);
556 while (i >= sizeof(struct acpi_mcfg_allocation)) {
557 ++pci_mmcfg_config_num;
558 i -= sizeof(struct acpi_mcfg_allocation);
560 if (pci_mmcfg_config_num == 0) {
561 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
565 config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config);
566 pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL);
567 if (!pci_mmcfg_config) {
568 printk(KERN_WARNING PREFIX
569 "No memory for MCFG config tables\n");
573 memcpy(pci_mmcfg_config, &mcfg[1], config_size);
575 acpi_mcfg_oem_check(mcfg);
577 for (i = 0; i < pci_mmcfg_config_num; ++i) {
578 if ((pci_mmcfg_config[i].address > 0xFFFFFFFF) &&
579 !acpi_mcfg_64bit_base_addr) {
580 printk(KERN_ERR PREFIX
581 "MMCONFIG not in low 4GB of memory\n");
582 kfree(pci_mmcfg_config);
583 pci_mmcfg_config_num = 0;
591 static void __init __pci_mmcfg_init(int early)
593 /* MMCONFIG disabled */
594 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
597 /* MMCONFIG already enabled */
598 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
601 /* for late to exit */
606 if (pci_mmcfg_check_hostbridge())
611 acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
613 pci_mmcfg_reject_broken(early);
615 if ((pci_mmcfg_config_num == 0) ||
616 (pci_mmcfg_config == NULL) ||
617 (pci_mmcfg_config[0].address == 0))
620 if (pci_mmcfg_arch_init())
621 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
624 * Signal not to attempt to insert mmcfg resources because
625 * the architecture mmcfg setup could not initialize.
627 pci_mmcfg_resources_inserted = 1;
631 void __init pci_mmcfg_early_init(void)
636 void __init pci_mmcfg_late_init(void)
641 static int __init pci_mmcfg_late_insert_resources(void)
644 * If resources are already inserted or we are not using MMCONFIG,
645 * don't insert the resources.
647 if ((pci_mmcfg_resources_inserted == 1) ||
648 (pci_probe & PCI_PROBE_MMCONF) == 0 ||
649 (pci_mmcfg_config_num == 0) ||
650 (pci_mmcfg_config == NULL) ||
651 (pci_mmcfg_config[0].address == 0))
655 * Attempt to insert the mmcfg resources but not with the busy flag
656 * marked so it won't cause request errors when __request_region is
659 pci_mmcfg_insert_resources();
665 * Perform MMCONFIG resource insertion after PCI initialization to allow for
666 * misprogrammed MCFG tables that state larger sizes but actually conflict
667 * with other system resources.
669 late_initcall(pci_mmcfg_late_insert_resources);