2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
10 #include <linux/interrupt.h>
11 #include <linux/seq_file.h>
12 #include <linux/debugfs.h>
13 #include <linux/pfn.h>
14 #include <linux/percpu.h>
15 #include <linux/gfp.h>
16 #include <linux/pci.h>
19 #include <asm/processor.h>
20 #include <asm/tlbflush.h>
21 #include <asm/sections.h>
22 #include <asm/setup.h>
23 #include <asm/uaccess.h>
24 #include <asm/pgalloc.h>
25 #include <asm/proto.h>
29 * The current flushing context - we pass it instead of 5 arguments:
39 unsigned force_split : 1;
45 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
46 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
47 * entries change the page attribute in parallel to some other cpu
48 * splitting a large page entry along with changing the attribute.
50 static DEFINE_SPINLOCK(cpa_lock);
52 #define CPA_FLUSHTLB 1
54 #define CPA_PAGES_ARRAY 4
57 static unsigned long direct_pages_count[PG_LEVEL_NUM];
59 void update_page_count(int level, unsigned long pages)
61 /* Protect against CPA */
63 direct_pages_count[level] += pages;
64 spin_unlock(&pgd_lock);
67 static void split_page_count(int level)
69 direct_pages_count[level]--;
70 direct_pages_count[level - 1] += PTRS_PER_PTE;
73 void arch_report_meminfo(struct seq_file *m)
75 seq_printf(m, "DirectMap4k: %8lu kB\n",
76 direct_pages_count[PG_LEVEL_4K] << 2);
77 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
78 seq_printf(m, "DirectMap2M: %8lu kB\n",
79 direct_pages_count[PG_LEVEL_2M] << 11);
81 seq_printf(m, "DirectMap4M: %8lu kB\n",
82 direct_pages_count[PG_LEVEL_2M] << 12);
86 seq_printf(m, "DirectMap1G: %8lu kB\n",
87 direct_pages_count[PG_LEVEL_1G] << 20);
91 static inline void split_page_count(int level) { }
96 static inline unsigned long highmap_start_pfn(void)
98 return __pa_symbol(_text) >> PAGE_SHIFT;
101 static inline unsigned long highmap_end_pfn(void)
103 return __pa_symbol(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
108 #ifdef CONFIG_DEBUG_PAGEALLOC
109 # define debug_pagealloc 1
111 # define debug_pagealloc 0
115 within(unsigned long addr, unsigned long start, unsigned long end)
117 return addr >= start && addr < end;
125 * clflush_cache_range - flush a cache range with clflush
126 * @vaddr: virtual start address
127 * @size: number of bytes to flush
129 * clflushopt is an unordered instruction which needs fencing with mfence or
130 * sfence to avoid ordering issues.
132 void clflush_cache_range(void *vaddr, unsigned int size)
134 void *vend = vaddr + size - 1;
138 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
141 * Flush any possible final partial cacheline:
147 EXPORT_SYMBOL_GPL(clflush_cache_range);
149 static void __cpa_flush_all(void *arg)
151 unsigned long cache = (unsigned long)arg;
154 * Flush all to work around Errata in early athlons regarding
155 * large page flushing.
159 if (cache && boot_cpu_data.x86 >= 4)
163 static void cpa_flush_all(unsigned long cache)
165 BUG_ON(irqs_disabled());
167 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
170 static void __cpa_flush_range(void *arg)
173 * We could optimize that further and do individual per page
174 * tlb invalidates for a low number of pages. Caveat: we must
175 * flush the high aliases on 64bit as well.
180 static void cpa_flush_range(unsigned long start, int numpages, int cache)
182 unsigned int i, level;
185 BUG_ON(irqs_disabled());
186 WARN_ON(PAGE_ALIGN(start) != start);
188 on_each_cpu(__cpa_flush_range, NULL, 1);
194 * We only need to flush on one CPU,
195 * clflush is a MESI-coherent instruction that
196 * will cause all other CPUs to flush the same
199 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
200 pte_t *pte = lookup_address(addr, &level);
203 * Only flush present addresses:
205 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
206 clflush_cache_range((void *) addr, PAGE_SIZE);
210 static void cpa_flush_array(unsigned long *start, int numpages, int cache,
211 int in_flags, struct page **pages)
213 unsigned int i, level;
214 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
216 BUG_ON(irqs_disabled());
218 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
220 if (!cache || do_wbinvd)
224 * We only need to flush on one CPU,
225 * clflush is a MESI-coherent instruction that
226 * will cause all other CPUs to flush the same
229 for (i = 0; i < numpages; i++) {
233 if (in_flags & CPA_PAGES_ARRAY)
234 addr = (unsigned long)page_address(pages[i]);
238 pte = lookup_address(addr, &level);
241 * Only flush present addresses:
243 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
244 clflush_cache_range((void *)addr, PAGE_SIZE);
249 * Certain areas of memory on x86 require very specific protection flags,
250 * for example the BIOS area or kernel text. Callers don't always get this
251 * right (again, ioremap() on BIOS memory is not uncommon) so this function
252 * checks and fixes these known static required protection bits.
254 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
257 pgprot_t forbidden = __pgprot(0);
260 * The BIOS area between 640k and 1Mb needs to be executable for
261 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
263 #ifdef CONFIG_PCI_BIOS
264 if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
265 pgprot_val(forbidden) |= _PAGE_NX;
269 * The kernel text needs to be executable for obvious reasons
270 * Does not cover __inittext since that is gone later on. On
271 * 64bit we do not enforce !NX on the low mapping
273 if (within(address, (unsigned long)_text, (unsigned long)_etext))
274 pgprot_val(forbidden) |= _PAGE_NX;
277 * The .rodata section needs to be read-only. Using the pfn
278 * catches all aliases.
280 if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT,
281 __pa_symbol(__end_rodata) >> PAGE_SHIFT))
282 pgprot_val(forbidden) |= _PAGE_RW;
284 #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
286 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
287 * kernel text mappings for the large page aligned text, rodata sections
288 * will be always read-only. For the kernel identity mappings covering
289 * the holes caused by this alignment can be anything that user asks.
291 * This will preserve the large page mappings for kernel text/data
294 if (kernel_set_to_readonly &&
295 within(address, (unsigned long)_text,
296 (unsigned long)__end_rodata_hpage_align)) {
300 * Don't enforce the !RW mapping for the kernel text mapping,
301 * if the current mapping is already using small page mapping.
302 * No need to work hard to preserve large page mappings in this
305 * This also fixes the Linux Xen paravirt guest boot failure
306 * (because of unexpected read-only mappings for kernel identity
307 * mappings). In this paravirt guest case, the kernel text
308 * mapping and the kernel identity mapping share the same
309 * page-table pages. Thus we can't really use different
310 * protections for the kernel text and identity mappings. Also,
311 * these shared mappings are made of small page mappings.
312 * Thus this don't enforce !RW mapping for small page kernel
313 * text mapping logic will help Linux Xen parvirt guest boot
316 if (lookup_address(address, &level) && (level != PG_LEVEL_4K))
317 pgprot_val(forbidden) |= _PAGE_RW;
321 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
327 * Lookup the page table entry for a virtual address in a specific pgd.
328 * Return a pointer to the entry and the level of the mapping.
330 pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address,
336 *level = PG_LEVEL_NONE;
341 pud = pud_offset(pgd, address);
345 *level = PG_LEVEL_1G;
346 if (pud_large(*pud) || !pud_present(*pud))
349 pmd = pmd_offset(pud, address);
353 *level = PG_LEVEL_2M;
354 if (pmd_large(*pmd) || !pmd_present(*pmd))
357 *level = PG_LEVEL_4K;
359 return pte_offset_kernel(pmd, address);
363 * Lookup the page table entry for a virtual address. Return a pointer
364 * to the entry and the level of the mapping.
366 * Note: We return pud and pmd either when the entry is marked large
367 * or when the present bit is not set. Otherwise we would return a
368 * pointer to a nonexisting mapping.
370 pte_t *lookup_address(unsigned long address, unsigned int *level)
372 return lookup_address_in_pgd(pgd_offset_k(address), address, level);
374 EXPORT_SYMBOL_GPL(lookup_address);
376 static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address,
380 return lookup_address_in_pgd(cpa->pgd + pgd_index(address),
383 return lookup_address(address, level);
387 * This is necessary because __pa() does not work on some
388 * kinds of memory, like vmalloc() or the alloc_remap()
389 * areas on 32-bit NUMA systems. The percpu areas can
390 * end up in this kind of memory, for instance.
392 * This could be optimized, but it is only intended to be
393 * used at inititalization time, and keeping it
394 * unoptimized should increase the testing coverage for
395 * the more obscure platforms.
397 phys_addr_t slow_virt_to_phys(void *__virt_addr)
399 unsigned long virt_addr = (unsigned long)__virt_addr;
400 phys_addr_t phys_addr;
401 unsigned long offset;
407 pte = lookup_address(virt_addr, &level);
409 psize = page_level_size(level);
410 pmask = page_level_mask(level);
411 offset = virt_addr & ~pmask;
412 phys_addr = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT;
413 return (phys_addr | offset);
415 EXPORT_SYMBOL_GPL(slow_virt_to_phys);
418 * Set the new pmd in all the pgds we know about:
420 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
423 set_pte_atomic(kpte, pte);
425 if (!SHARED_KERNEL_PMD) {
428 list_for_each_entry(page, &pgd_list, lru) {
433 pgd = (pgd_t *)page_address(page) + pgd_index(address);
434 pud = pud_offset(pgd, address);
435 pmd = pmd_offset(pud, address);
436 set_pte_atomic((pte_t *)pmd, pte);
443 try_preserve_large_page(pte_t *kpte, unsigned long address,
444 struct cpa_data *cpa)
446 unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn;
447 pte_t new_pte, old_pte, *tmp;
448 pgprot_t old_prot, new_prot, req_prot;
452 if (cpa->force_split)
455 spin_lock(&pgd_lock);
457 * Check for races, another CPU might have split this page
460 tmp = _lookup_address_cpa(cpa, address, &level);
469 psize = page_level_size(level);
470 pmask = page_level_mask(level);
478 * Calculate the number of pages, which fit into this large
479 * page starting at address:
481 nextpage_addr = (address + psize) & pmask;
482 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
483 if (numpages < cpa->numpages)
484 cpa->numpages = numpages;
487 * We are safe now. Check whether the new pgprot is the same:
488 * Convert protection attributes to 4k-format, as cpa->mask* are set
492 old_prot = req_prot = pgprot_large_2_4k(pte_pgprot(old_pte));
494 pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
495 pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
498 * req_prot is in format of 4k pages. It must be converted to large
499 * page format: the caching mode includes the PAT bit located at
500 * different bit positions in the two formats.
502 req_prot = pgprot_4k_2_large(req_prot);
505 * Set the PSE and GLOBAL flags only if the PRESENT flag is
506 * set otherwise pmd_present/pmd_huge will return true even on
507 * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL
508 * for the ancient hardware that doesn't support it.
510 if (pgprot_val(req_prot) & _PAGE_PRESENT)
511 pgprot_val(req_prot) |= _PAGE_PSE | _PAGE_GLOBAL;
513 pgprot_val(req_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL);
515 req_prot = canon_pgprot(req_prot);
518 * old_pte points to the large page base address. So we need
519 * to add the offset of the virtual address:
521 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
524 new_prot = static_protections(req_prot, address, pfn);
527 * We need to check the full range, whether
528 * static_protection() requires a different pgprot for one of
529 * the pages in the range we try to preserve:
531 addr = address & pmask;
532 pfn = pte_pfn(old_pte);
533 for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) {
534 pgprot_t chk_prot = static_protections(req_prot, addr, pfn);
536 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
541 * If there are no changes, return. maxpages has been updated
544 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
550 * We need to change the attributes. Check, whether we can
551 * change the large page in one go. We request a split, when
552 * the address is not aligned and the number of pages is
553 * smaller than the number of pages in the large page. Note
554 * that we limited the number of possible pages already to
555 * the number of pages in the large page.
557 if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) {
559 * The address is aligned and the number of pages
560 * covers the full page.
562 new_pte = pfn_pte(pte_pfn(old_pte), new_prot);
563 __set_pmd_pte(kpte, address, new_pte);
564 cpa->flags |= CPA_FLUSHTLB;
569 spin_unlock(&pgd_lock);
575 __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address,
578 pte_t *pbase = (pte_t *)page_address(base);
579 unsigned long pfn, pfninc = 1;
580 unsigned int i, level;
584 spin_lock(&pgd_lock);
586 * Check for races, another CPU might have split this page
589 tmp = _lookup_address_cpa(cpa, address, &level);
591 spin_unlock(&pgd_lock);
595 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
596 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
598 /* promote PAT bit to correct position */
599 if (level == PG_LEVEL_2M)
600 ref_prot = pgprot_large_2_4k(ref_prot);
603 if (level == PG_LEVEL_1G) {
604 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
606 * Set the PSE flags only if the PRESENT flag is set
607 * otherwise pmd_present/pmd_huge will return true
608 * even on a non present pmd.
610 if (pgprot_val(ref_prot) & _PAGE_PRESENT)
611 pgprot_val(ref_prot) |= _PAGE_PSE;
613 pgprot_val(ref_prot) &= ~_PAGE_PSE;
618 * Set the GLOBAL flags only if the PRESENT flag is set
619 * otherwise pmd/pte_present will return true even on a non
620 * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL
621 * for the ancient hardware that doesn't support it.
623 if (pgprot_val(ref_prot) & _PAGE_PRESENT)
624 pgprot_val(ref_prot) |= _PAGE_GLOBAL;
626 pgprot_val(ref_prot) &= ~_PAGE_GLOBAL;
629 * Get the target pfn from the original entry:
631 pfn = pte_pfn(*kpte);
632 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
633 set_pte(&pbase[i], pfn_pte(pfn, canon_pgprot(ref_prot)));
635 if (pfn_range_is_mapped(PFN_DOWN(__pa(address)),
636 PFN_DOWN(__pa(address)) + 1))
637 split_page_count(level);
640 * Install the new, split up pagetable.
642 * We use the standard kernel pagetable protections for the new
643 * pagetable protections, the actual ptes set above control the
644 * primary protection behavior:
646 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
649 * Intel Atom errata AAH41 workaround.
651 * The real fix should be in hw or in a microcode update, but
652 * we also probabilistically try to reduce the window of having
653 * a large TLB mixed with 4K TLBs while instruction fetches are
657 spin_unlock(&pgd_lock);
662 static int split_large_page(struct cpa_data *cpa, pte_t *kpte,
663 unsigned long address)
667 if (!debug_pagealloc)
668 spin_unlock(&cpa_lock);
669 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
670 if (!debug_pagealloc)
671 spin_lock(&cpa_lock);
675 if (__split_large_page(cpa, kpte, address, base))
681 static bool try_to_free_pte_page(pte_t *pte)
685 for (i = 0; i < PTRS_PER_PTE; i++)
686 if (!pte_none(pte[i]))
689 free_page((unsigned long)pte);
693 static bool try_to_free_pmd_page(pmd_t *pmd)
697 for (i = 0; i < PTRS_PER_PMD; i++)
698 if (!pmd_none(pmd[i]))
701 free_page((unsigned long)pmd);
705 static bool try_to_free_pud_page(pud_t *pud)
709 for (i = 0; i < PTRS_PER_PUD; i++)
710 if (!pud_none(pud[i]))
713 free_page((unsigned long)pud);
717 static bool unmap_pte_range(pmd_t *pmd, unsigned long start, unsigned long end)
719 pte_t *pte = pte_offset_kernel(pmd, start);
721 while (start < end) {
722 set_pte(pte, __pte(0));
728 if (try_to_free_pte_page((pte_t *)pmd_page_vaddr(*pmd))) {
735 static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd,
736 unsigned long start, unsigned long end)
738 if (unmap_pte_range(pmd, start, end))
739 if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud)))
743 static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end)
745 pmd_t *pmd = pmd_offset(pud, start);
748 * Not on a 2MB page boundary?
750 if (start & (PMD_SIZE - 1)) {
751 unsigned long next_page = (start + PMD_SIZE) & PMD_MASK;
752 unsigned long pre_end = min_t(unsigned long, end, next_page);
754 __unmap_pmd_range(pud, pmd, start, pre_end);
761 * Try to unmap in 2M chunks.
763 while (end - start >= PMD_SIZE) {
767 __unmap_pmd_range(pud, pmd, start, start + PMD_SIZE);
777 return __unmap_pmd_range(pud, pmd, start, end);
780 * Try again to free the PMD page if haven't succeeded above.
783 if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud)))
787 static void unmap_pud_range(pgd_t *pgd, unsigned long start, unsigned long end)
789 pud_t *pud = pud_offset(pgd, start);
792 * Not on a GB page boundary?
794 if (start & (PUD_SIZE - 1)) {
795 unsigned long next_page = (start + PUD_SIZE) & PUD_MASK;
796 unsigned long pre_end = min_t(unsigned long, end, next_page);
798 unmap_pmd_range(pud, start, pre_end);
805 * Try to unmap in 1G chunks?
807 while (end - start >= PUD_SIZE) {
812 unmap_pmd_range(pud, start, start + PUD_SIZE);
822 unmap_pmd_range(pud, start, end);
825 * No need to try to free the PUD page because we'll free it in
826 * populate_pgd's error path
830 static void unmap_pgd_range(pgd_t *root, unsigned long addr, unsigned long end)
832 pgd_t *pgd_entry = root + pgd_index(addr);
834 unmap_pud_range(pgd_entry, addr, end);
836 if (try_to_free_pud_page((pud_t *)pgd_page_vaddr(*pgd_entry)))
837 pgd_clear(pgd_entry);
840 static int alloc_pte_page(pmd_t *pmd)
842 pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK);
846 set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE));
850 static int alloc_pmd_page(pud_t *pud)
852 pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK);
856 set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
860 static void populate_pte(struct cpa_data *cpa,
861 unsigned long start, unsigned long end,
862 unsigned num_pages, pmd_t *pmd, pgprot_t pgprot)
866 pte = pte_offset_kernel(pmd, start);
868 while (num_pages-- && start < end) {
870 /* deal with the NX bit */
871 if (!(pgprot_val(pgprot) & _PAGE_NX))
872 cpa->pfn &= ~_PAGE_NX;
874 set_pte(pte, pfn_pte(cpa->pfn >> PAGE_SHIFT, pgprot));
877 cpa->pfn += PAGE_SIZE;
882 static int populate_pmd(struct cpa_data *cpa,
883 unsigned long start, unsigned long end,
884 unsigned num_pages, pud_t *pud, pgprot_t pgprot)
886 unsigned int cur_pages = 0;
891 * Not on a 2M boundary?
893 if (start & (PMD_SIZE - 1)) {
894 unsigned long pre_end = start + (num_pages << PAGE_SHIFT);
895 unsigned long next_page = (start + PMD_SIZE) & PMD_MASK;
897 pre_end = min_t(unsigned long, pre_end, next_page);
898 cur_pages = (pre_end - start) >> PAGE_SHIFT;
899 cur_pages = min_t(unsigned int, num_pages, cur_pages);
904 pmd = pmd_offset(pud, start);
906 if (alloc_pte_page(pmd))
909 populate_pte(cpa, start, pre_end, cur_pages, pmd, pgprot);
915 * We mapped them all?
917 if (num_pages == cur_pages)
920 pmd_pgprot = pgprot_4k_2_large(pgprot);
922 while (end - start >= PMD_SIZE) {
925 * We cannot use a 1G page so allocate a PMD page if needed.
928 if (alloc_pmd_page(pud))
931 pmd = pmd_offset(pud, start);
933 set_pmd(pmd, __pmd(cpa->pfn | _PAGE_PSE |
934 massage_pgprot(pmd_pgprot)));
937 cpa->pfn += PMD_SIZE;
938 cur_pages += PMD_SIZE >> PAGE_SHIFT;
942 * Map trailing 4K pages.
945 pmd = pmd_offset(pud, start);
947 if (alloc_pte_page(pmd))
950 populate_pte(cpa, start, end, num_pages - cur_pages,
956 static int populate_pud(struct cpa_data *cpa, unsigned long start, pgd_t *pgd,
964 end = start + (cpa->numpages << PAGE_SHIFT);
967 * Not on a Gb page boundary? => map everything up to it with
970 if (start & (PUD_SIZE - 1)) {
971 unsigned long pre_end;
972 unsigned long next_page = (start + PUD_SIZE) & PUD_MASK;
974 pre_end = min_t(unsigned long, end, next_page);
975 cur_pages = (pre_end - start) >> PAGE_SHIFT;
976 cur_pages = min_t(int, (int)cpa->numpages, cur_pages);
978 pud = pud_offset(pgd, start);
984 if (alloc_pmd_page(pud))
987 cur_pages = populate_pmd(cpa, start, pre_end, cur_pages,
995 /* We mapped them all? */
996 if (cpa->numpages == cur_pages)
999 pud = pud_offset(pgd, start);
1000 pud_pgprot = pgprot_4k_2_large(pgprot);
1003 * Map everything starting from the Gb boundary, possibly with 1G pages
1005 while (end - start >= PUD_SIZE) {
1006 set_pud(pud, __pud(cpa->pfn | _PAGE_PSE |
1007 massage_pgprot(pud_pgprot)));
1010 cpa->pfn += PUD_SIZE;
1011 cur_pages += PUD_SIZE >> PAGE_SHIFT;
1015 /* Map trailing leftover */
1019 pud = pud_offset(pgd, start);
1021 if (alloc_pmd_page(pud))
1024 tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages,
1035 * Restrictions for kernel page table do not necessarily apply when mapping in
1038 static int populate_pgd(struct cpa_data *cpa, unsigned long addr)
1040 pgprot_t pgprot = __pgprot(_KERNPG_TABLE);
1041 pud_t *pud = NULL; /* shut up gcc */
1045 pgd_entry = cpa->pgd + pgd_index(addr);
1048 * Allocate a PUD page and hand it down for mapping.
1050 if (pgd_none(*pgd_entry)) {
1051 pud = (pud_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK);
1055 set_pgd(pgd_entry, __pgd(__pa(pud) | _KERNPG_TABLE));
1058 pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr);
1059 pgprot_val(pgprot) |= pgprot_val(cpa->mask_set);
1061 ret = populate_pud(cpa, addr, pgd_entry, pgprot);
1063 unmap_pgd_range(cpa->pgd, addr,
1064 addr + (cpa->numpages << PAGE_SHIFT));
1068 cpa->numpages = ret;
1072 static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
1076 return populate_pgd(cpa, vaddr);
1079 * Ignore all non primary paths.
1085 * Ignore the NULL PTE for kernel identity mapping, as it is expected
1087 * Also set numpages to '1' indicating that we processed cpa req for
1088 * one virtual address page and its pfn. TBD: numpages can be set based
1089 * on the initial value and the level returned by lookup_address().
1091 if (within(vaddr, PAGE_OFFSET,
1092 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
1094 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
1097 WARN(1, KERN_WARNING "CPA: called for zero pte. "
1098 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
1105 static int __change_page_attr(struct cpa_data *cpa, int primary)
1107 unsigned long address;
1110 pte_t *kpte, old_pte;
1112 if (cpa->flags & CPA_PAGES_ARRAY) {
1113 struct page *page = cpa->pages[cpa->curpage];
1114 if (unlikely(PageHighMem(page)))
1116 address = (unsigned long)page_address(page);
1117 } else if (cpa->flags & CPA_ARRAY)
1118 address = cpa->vaddr[cpa->curpage];
1120 address = *cpa->vaddr;
1122 kpte = _lookup_address_cpa(cpa, address, &level);
1124 return __cpa_process_fault(cpa, address, primary);
1127 if (!pte_val(old_pte))
1128 return __cpa_process_fault(cpa, address, primary);
1130 if (level == PG_LEVEL_4K) {
1132 pgprot_t new_prot = pte_pgprot(old_pte);
1133 unsigned long pfn = pte_pfn(old_pte);
1135 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
1136 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
1138 new_prot = static_protections(new_prot, address, pfn);
1141 * Set the GLOBAL flags only if the PRESENT flag is
1142 * set otherwise pte_present will return true even on
1143 * a non present pte. The canon_pgprot will clear
1144 * _PAGE_GLOBAL for the ancient hardware that doesn't
1147 if (pgprot_val(new_prot) & _PAGE_PRESENT)
1148 pgprot_val(new_prot) |= _PAGE_GLOBAL;
1150 pgprot_val(new_prot) &= ~_PAGE_GLOBAL;
1153 * We need to keep the pfn from the existing PTE,
1154 * after all we're only going to change it's attributes
1155 * not the memory it points to
1157 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
1160 * Do we really change anything ?
1162 if (pte_val(old_pte) != pte_val(new_pte)) {
1163 set_pte_atomic(kpte, new_pte);
1164 cpa->flags |= CPA_FLUSHTLB;
1171 * Check, whether we can keep the large page intact
1172 * and just change the pte:
1174 do_split = try_preserve_large_page(kpte, address, cpa);
1176 * When the range fits into the existing large page,
1177 * return. cp->numpages and cpa->tlbflush have been updated in
1184 * We have to split the large page:
1186 err = split_large_page(cpa, kpte, address);
1189 * Do a global flush tlb after splitting the large page
1190 * and before we do the actual change page attribute in the PTE.
1192 * With out this, we violate the TLB application note, that says
1193 * "The TLBs may contain both ordinary and large-page
1194 * translations for a 4-KByte range of linear addresses. This
1195 * may occur if software modifies the paging structures so that
1196 * the page size used for the address range changes. If the two
1197 * translations differ with respect to page frame or attributes
1198 * (e.g., permissions), processor behavior is undefined and may
1199 * be implementation-specific."
1201 * We do this global tlb flush inside the cpa_lock, so that we
1202 * don't allow any other cpu, with stale tlb entries change the
1203 * page attribute in parallel, that also falls into the
1204 * just split large page entry.
1213 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
1215 static int cpa_process_alias(struct cpa_data *cpa)
1217 struct cpa_data alias_cpa;
1218 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
1219 unsigned long vaddr;
1222 if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1))
1226 * No need to redo, when the primary call touched the direct
1229 if (cpa->flags & CPA_PAGES_ARRAY) {
1230 struct page *page = cpa->pages[cpa->curpage];
1231 if (unlikely(PageHighMem(page)))
1233 vaddr = (unsigned long)page_address(page);
1234 } else if (cpa->flags & CPA_ARRAY)
1235 vaddr = cpa->vaddr[cpa->curpage];
1237 vaddr = *cpa->vaddr;
1239 if (!(within(vaddr, PAGE_OFFSET,
1240 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
1243 alias_cpa.vaddr = &laddr;
1244 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
1246 ret = __change_page_attr_set_clr(&alias_cpa, 0);
1251 #ifdef CONFIG_X86_64
1253 * If the primary call didn't touch the high mapping already
1254 * and the physical address is inside the kernel map, we need
1255 * to touch the high mapped kernel as well:
1257 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
1258 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
1259 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
1260 __START_KERNEL_map - phys_base;
1262 alias_cpa.vaddr = &temp_cpa_vaddr;
1263 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
1266 * The high mapping range is imprecise, so ignore the
1269 __change_page_attr_set_clr(&alias_cpa, 0);
1276 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
1278 int ret, numpages = cpa->numpages;
1282 * Store the remaining nr of pages for the large page
1283 * preservation check.
1285 cpa->numpages = numpages;
1286 /* for array changes, we can't use large page */
1287 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
1290 if (!debug_pagealloc)
1291 spin_lock(&cpa_lock);
1292 ret = __change_page_attr(cpa, checkalias);
1293 if (!debug_pagealloc)
1294 spin_unlock(&cpa_lock);
1299 ret = cpa_process_alias(cpa);
1305 * Adjust the number of pages with the result of the
1306 * CPA operation. Either a large page has been
1307 * preserved or a single page update happened.
1309 BUG_ON(cpa->numpages > numpages);
1310 numpages -= cpa->numpages;
1311 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
1314 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
1320 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
1321 pgprot_t mask_set, pgprot_t mask_clr,
1322 int force_split, int in_flag,
1323 struct page **pages)
1325 struct cpa_data cpa;
1326 int ret, cache, checkalias;
1327 unsigned long baddr = 0;
1329 memset(&cpa, 0, sizeof(cpa));
1332 * Check, if we are requested to change a not supported
1335 mask_set = canon_pgprot(mask_set);
1336 mask_clr = canon_pgprot(mask_clr);
1337 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
1340 /* Ensure we are PAGE_SIZE aligned */
1341 if (in_flag & CPA_ARRAY) {
1343 for (i = 0; i < numpages; i++) {
1344 if (addr[i] & ~PAGE_MASK) {
1345 addr[i] &= PAGE_MASK;
1349 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
1351 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
1352 * No need to cehck in that case
1354 if (*addr & ~PAGE_MASK) {
1357 * People should not be passing in unaligned addresses:
1362 * Save address for cache flush. *addr is modified in the call
1363 * to __change_page_attr_set_clr() below.
1368 /* Must avoid aliasing mappings in the highmem code */
1369 kmap_flush_unused();
1375 cpa.numpages = numpages;
1376 cpa.mask_set = mask_set;
1377 cpa.mask_clr = mask_clr;
1380 cpa.force_split = force_split;
1382 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
1383 cpa.flags |= in_flag;
1385 /* No alias checking for _NX bit modifications */
1386 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
1388 ret = __change_page_attr_set_clr(&cpa, checkalias);
1391 * Check whether we really changed something:
1393 if (!(cpa.flags & CPA_FLUSHTLB))
1397 * No need to flush, when we did not set any of the caching
1400 cache = !!pgprot2cachemode(mask_set);
1403 * On success we use CLFLUSH, when the CPU supports it to
1404 * avoid the WBINVD. If the CPU does not support it and in the
1405 * error case we fall back to cpa_flush_all (which uses
1408 if (!ret && cpu_has_clflush) {
1409 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
1410 cpa_flush_array(addr, numpages, cache,
1413 cpa_flush_range(baddr, numpages, cache);
1415 cpa_flush_all(cache);
1421 static inline int change_page_attr_set(unsigned long *addr, int numpages,
1422 pgprot_t mask, int array)
1424 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
1425 (array ? CPA_ARRAY : 0), NULL);
1428 static inline int change_page_attr_clear(unsigned long *addr, int numpages,
1429 pgprot_t mask, int array)
1431 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
1432 (array ? CPA_ARRAY : 0), NULL);
1435 static inline int cpa_set_pages_array(struct page **pages, int numpages,
1438 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
1439 CPA_PAGES_ARRAY, pages);
1442 static inline int cpa_clear_pages_array(struct page **pages, int numpages,
1445 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
1446 CPA_PAGES_ARRAY, pages);
1449 int _set_memory_uc(unsigned long addr, int numpages)
1452 * for now UC MINUS. see comments in ioremap_nocache()
1454 return change_page_attr_set(&addr, numpages,
1455 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
1459 int set_memory_uc(unsigned long addr, int numpages)
1464 * for now UC MINUS. see comments in ioremap_nocache()
1466 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1467 _PAGE_CACHE_MODE_UC_MINUS, NULL);
1471 ret = _set_memory_uc(addr, numpages);
1478 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1482 EXPORT_SYMBOL(set_memory_uc);
1484 static int _set_memory_array(unsigned long *addr, int addrinarray,
1485 enum page_cache_mode new_type)
1491 * for now UC MINUS. see comments in ioremap_nocache()
1493 for (i = 0; i < addrinarray; i++) {
1494 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
1500 ret = change_page_attr_set(addr, addrinarray,
1501 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
1504 if (!ret && new_type == _PAGE_CACHE_MODE_WC)
1505 ret = change_page_attr_set_clr(addr, addrinarray,
1507 _PAGE_CACHE_MODE_WC),
1508 __pgprot(_PAGE_CACHE_MASK),
1509 0, CPA_ARRAY, NULL);
1516 for (j = 0; j < i; j++)
1517 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1522 int set_memory_array_uc(unsigned long *addr, int addrinarray)
1524 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_UC_MINUS);
1526 EXPORT_SYMBOL(set_memory_array_uc);
1528 int set_memory_array_wc(unsigned long *addr, int addrinarray)
1530 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WC);
1532 EXPORT_SYMBOL(set_memory_array_wc);
1534 int _set_memory_wc(unsigned long addr, int numpages)
1537 unsigned long addr_copy = addr;
1539 ret = change_page_attr_set(&addr, numpages,
1540 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
1543 ret = change_page_attr_set_clr(&addr_copy, numpages,
1545 _PAGE_CACHE_MODE_WC),
1546 __pgprot(_PAGE_CACHE_MASK),
1552 int set_memory_wc(unsigned long addr, int numpages)
1557 return set_memory_uc(addr, numpages);
1559 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1560 _PAGE_CACHE_MODE_WC, NULL);
1564 ret = _set_memory_wc(addr, numpages);
1571 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1575 EXPORT_SYMBOL(set_memory_wc);
1577 int _set_memory_wb(unsigned long addr, int numpages)
1579 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1580 return change_page_attr_clear(&addr, numpages,
1581 __pgprot(_PAGE_CACHE_MASK), 0);
1584 int set_memory_wb(unsigned long addr, int numpages)
1588 ret = _set_memory_wb(addr, numpages);
1592 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1595 EXPORT_SYMBOL(set_memory_wb);
1597 int set_memory_array_wb(unsigned long *addr, int addrinarray)
1602 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1603 ret = change_page_attr_clear(addr, addrinarray,
1604 __pgprot(_PAGE_CACHE_MASK), 1);
1608 for (i = 0; i < addrinarray; i++)
1609 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1613 EXPORT_SYMBOL(set_memory_array_wb);
1615 int set_memory_x(unsigned long addr, int numpages)
1617 if (!(__supported_pte_mask & _PAGE_NX))
1620 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1622 EXPORT_SYMBOL(set_memory_x);
1624 int set_memory_nx(unsigned long addr, int numpages)
1626 if (!(__supported_pte_mask & _PAGE_NX))
1629 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1631 EXPORT_SYMBOL(set_memory_nx);
1633 int set_memory_ro(unsigned long addr, int numpages)
1635 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1637 EXPORT_SYMBOL_GPL(set_memory_ro);
1639 int set_memory_rw(unsigned long addr, int numpages)
1641 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1643 EXPORT_SYMBOL_GPL(set_memory_rw);
1645 int set_memory_np(unsigned long addr, int numpages)
1647 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1650 int set_memory_4k(unsigned long addr, int numpages)
1652 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1653 __pgprot(0), 1, 0, NULL);
1656 int set_pages_uc(struct page *page, int numpages)
1658 unsigned long addr = (unsigned long)page_address(page);
1660 return set_memory_uc(addr, numpages);
1662 EXPORT_SYMBOL(set_pages_uc);
1664 static int _set_pages_array(struct page **pages, int addrinarray,
1665 enum page_cache_mode new_type)
1667 unsigned long start;
1673 for (i = 0; i < addrinarray; i++) {
1674 if (PageHighMem(pages[i]))
1676 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1677 end = start + PAGE_SIZE;
1678 if (reserve_memtype(start, end, new_type, NULL))
1682 ret = cpa_set_pages_array(pages, addrinarray,
1683 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS));
1684 if (!ret && new_type == _PAGE_CACHE_MODE_WC)
1685 ret = change_page_attr_set_clr(NULL, addrinarray,
1687 _PAGE_CACHE_MODE_WC),
1688 __pgprot(_PAGE_CACHE_MASK),
1689 0, CPA_PAGES_ARRAY, pages);
1692 return 0; /* Success */
1695 for (i = 0; i < free_idx; i++) {
1696 if (PageHighMem(pages[i]))
1698 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1699 end = start + PAGE_SIZE;
1700 free_memtype(start, end);
1705 int set_pages_array_uc(struct page **pages, int addrinarray)
1707 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_UC_MINUS);
1709 EXPORT_SYMBOL(set_pages_array_uc);
1711 int set_pages_array_wc(struct page **pages, int addrinarray)
1713 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WC);
1715 EXPORT_SYMBOL(set_pages_array_wc);
1717 int set_pages_wb(struct page *page, int numpages)
1719 unsigned long addr = (unsigned long)page_address(page);
1721 return set_memory_wb(addr, numpages);
1723 EXPORT_SYMBOL(set_pages_wb);
1725 int set_pages_array_wb(struct page **pages, int addrinarray)
1728 unsigned long start;
1732 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1733 retval = cpa_clear_pages_array(pages, addrinarray,
1734 __pgprot(_PAGE_CACHE_MASK));
1738 for (i = 0; i < addrinarray; i++) {
1739 if (PageHighMem(pages[i]))
1741 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1742 end = start + PAGE_SIZE;
1743 free_memtype(start, end);
1748 EXPORT_SYMBOL(set_pages_array_wb);
1750 int set_pages_x(struct page *page, int numpages)
1752 unsigned long addr = (unsigned long)page_address(page);
1754 return set_memory_x(addr, numpages);
1756 EXPORT_SYMBOL(set_pages_x);
1758 int set_pages_nx(struct page *page, int numpages)
1760 unsigned long addr = (unsigned long)page_address(page);
1762 return set_memory_nx(addr, numpages);
1764 EXPORT_SYMBOL(set_pages_nx);
1766 int set_pages_ro(struct page *page, int numpages)
1768 unsigned long addr = (unsigned long)page_address(page);
1770 return set_memory_ro(addr, numpages);
1773 int set_pages_rw(struct page *page, int numpages)
1775 unsigned long addr = (unsigned long)page_address(page);
1777 return set_memory_rw(addr, numpages);
1780 #ifdef CONFIG_DEBUG_PAGEALLOC
1782 static int __set_pages_p(struct page *page, int numpages)
1784 unsigned long tempaddr = (unsigned long) page_address(page);
1785 struct cpa_data cpa = { .vaddr = &tempaddr,
1787 .numpages = numpages,
1788 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1789 .mask_clr = __pgprot(0),
1793 * No alias checking needed for setting present flag. otherwise,
1794 * we may need to break large pages for 64-bit kernel text
1795 * mappings (this adds to complexity if we want to do this from
1796 * atomic context especially). Let's keep it simple!
1798 return __change_page_attr_set_clr(&cpa, 0);
1801 static int __set_pages_np(struct page *page, int numpages)
1803 unsigned long tempaddr = (unsigned long) page_address(page);
1804 struct cpa_data cpa = { .vaddr = &tempaddr,
1806 .numpages = numpages,
1807 .mask_set = __pgprot(0),
1808 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1812 * No alias checking needed for setting not present flag. otherwise,
1813 * we may need to break large pages for 64-bit kernel text
1814 * mappings (this adds to complexity if we want to do this from
1815 * atomic context especially). Let's keep it simple!
1817 return __change_page_attr_set_clr(&cpa, 0);
1820 void kernel_map_pages(struct page *page, int numpages, int enable)
1822 if (PageHighMem(page))
1825 debug_check_no_locks_freed(page_address(page),
1826 numpages * PAGE_SIZE);
1830 * The return value is ignored as the calls cannot fail.
1831 * Large pages for identity mappings are not used at boot time
1832 * and hence no memory allocations during large page split.
1835 __set_pages_p(page, numpages);
1837 __set_pages_np(page, numpages);
1840 * We should perform an IPI and flush all tlbs,
1841 * but that can deadlock->flush only current cpu:
1845 arch_flush_lazy_mmu_mode();
1848 #ifdef CONFIG_HIBERNATION
1850 bool kernel_page_present(struct page *page)
1855 if (PageHighMem(page))
1858 pte = lookup_address((unsigned long)page_address(page), &level);
1859 return (pte_val(*pte) & _PAGE_PRESENT);
1862 #endif /* CONFIG_HIBERNATION */
1864 #endif /* CONFIG_DEBUG_PAGEALLOC */
1866 int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address,
1867 unsigned numpages, unsigned long page_flags)
1869 int retval = -EINVAL;
1871 struct cpa_data cpa = {
1875 .numpages = numpages,
1876 .mask_set = __pgprot(0),
1877 .mask_clr = __pgprot(0),
1881 if (!(__supported_pte_mask & _PAGE_NX))
1884 if (!(page_flags & _PAGE_NX))
1885 cpa.mask_clr = __pgprot(_PAGE_NX);
1887 cpa.mask_set = __pgprot(_PAGE_PRESENT | page_flags);
1889 retval = __change_page_attr_set_clr(&cpa, 0);
1896 void kernel_unmap_pages_in_pgd(pgd_t *root, unsigned long address,
1899 unmap_pgd_range(root, address, address + (numpages << PAGE_SHIFT));
1903 * The testcases use internal knowledge of the implementation that shouldn't
1904 * be exposed to the rest of the kernel. Include these directly here.
1906 #ifdef CONFIG_CPA_DEBUG
1907 #include "pageattr-test.c"