2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/seq_file.h>
13 #include <linux/debugfs.h>
14 #include <linux/pfn.h>
17 #include <asm/processor.h>
18 #include <asm/tlbflush.h>
19 #include <asm/sections.h>
20 #include <asm/setup.h>
21 #include <asm/uaccess.h>
22 #include <asm/pgalloc.h>
23 #include <asm/proto.h>
27 * The current flushing context - we pass it instead of 5 arguments:
36 unsigned force_split : 1;
42 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
43 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
44 * entries change the page attribute in parallel to some other cpu
45 * splitting a large page entry along with changing the attribute.
47 static DEFINE_SPINLOCK(cpa_lock);
49 #define CPA_FLUSHTLB 1
51 #define CPA_PAGES_ARRAY 4
54 static unsigned long direct_pages_count[PG_LEVEL_NUM];
56 void update_page_count(int level, unsigned long pages)
60 /* Protect against CPA */
61 spin_lock_irqsave(&pgd_lock, flags);
62 direct_pages_count[level] += pages;
63 spin_unlock_irqrestore(&pgd_lock, flags);
66 static void split_page_count(int level)
68 direct_pages_count[level]--;
69 direct_pages_count[level - 1] += PTRS_PER_PTE;
72 void arch_report_meminfo(struct seq_file *m)
74 seq_printf(m, "DirectMap4k: %8lu kB\n",
75 direct_pages_count[PG_LEVEL_4K] << 2);
76 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
77 seq_printf(m, "DirectMap2M: %8lu kB\n",
78 direct_pages_count[PG_LEVEL_2M] << 11);
80 seq_printf(m, "DirectMap4M: %8lu kB\n",
81 direct_pages_count[PG_LEVEL_2M] << 12);
85 seq_printf(m, "DirectMap1G: %8lu kB\n",
86 direct_pages_count[PG_LEVEL_1G] << 20);
90 static inline void split_page_count(int level) { }
95 static inline unsigned long highmap_start_pfn(void)
97 return __pa(_text) >> PAGE_SHIFT;
100 static inline unsigned long highmap_end_pfn(void)
102 return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
107 #ifdef CONFIG_DEBUG_PAGEALLOC
108 # define debug_pagealloc 1
110 # define debug_pagealloc 0
114 within(unsigned long addr, unsigned long start, unsigned long end)
116 return addr >= start && addr < end;
124 * clflush_cache_range - flush a cache range with clflush
125 * @addr: virtual start address
126 * @size: number of bytes to flush
128 * clflush is an unordered instruction which needs fencing with mfence
129 * to avoid ordering issues.
131 void clflush_cache_range(void *vaddr, unsigned int size)
133 void *vend = vaddr + size - 1;
137 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
140 * Flush any possible final partial cacheline:
147 static void __cpa_flush_all(void *arg)
149 unsigned long cache = (unsigned long)arg;
152 * Flush all to work around Errata in early athlons regarding
153 * large page flushing.
157 if (cache && boot_cpu_data.x86 >= 4)
161 static void cpa_flush_all(unsigned long cache)
163 BUG_ON(irqs_disabled());
165 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
168 static void __cpa_flush_range(void *arg)
171 * We could optimize that further and do individual per page
172 * tlb invalidates for a low number of pages. Caveat: we must
173 * flush the high aliases on 64bit as well.
178 static void cpa_flush_range(unsigned long start, int numpages, int cache)
180 unsigned int i, level;
183 BUG_ON(irqs_disabled());
184 WARN_ON(PAGE_ALIGN(start) != start);
186 on_each_cpu(__cpa_flush_range, NULL, 1);
192 * We only need to flush on one CPU,
193 * clflush is a MESI-coherent instruction that
194 * will cause all other CPUs to flush the same
197 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
198 pte_t *pte = lookup_address(addr, &level);
201 * Only flush present addresses:
203 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
204 clflush_cache_range((void *) addr, PAGE_SIZE);
208 static void cpa_flush_array(unsigned long *start, int numpages, int cache,
209 int in_flags, struct page **pages)
211 unsigned int i, level;
212 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
214 BUG_ON(irqs_disabled());
216 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
218 if (!cache || do_wbinvd)
222 * We only need to flush on one CPU,
223 * clflush is a MESI-coherent instruction that
224 * will cause all other CPUs to flush the same
227 for (i = 0; i < numpages; i++) {
231 if (in_flags & CPA_PAGES_ARRAY)
232 addr = (unsigned long)page_address(pages[i]);
236 pte = lookup_address(addr, &level);
239 * Only flush present addresses:
241 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
242 clflush_cache_range((void *)addr, PAGE_SIZE);
247 * Certain areas of memory on x86 require very specific protection flags,
248 * for example the BIOS area or kernel text. Callers don't always get this
249 * right (again, ioremap() on BIOS memory is not uncommon) so this function
250 * checks and fixes these known static required protection bits.
252 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
255 pgprot_t forbidden = __pgprot(0);
258 * The BIOS area between 640k and 1Mb needs to be executable for
259 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
261 if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
262 pgprot_val(forbidden) |= _PAGE_NX;
265 * The kernel text needs to be executable for obvious reasons
266 * Does not cover __inittext since that is gone later on. On
267 * 64bit we do not enforce !NX on the low mapping
269 if (within(address, (unsigned long)_text, (unsigned long)_etext))
270 pgprot_val(forbidden) |= _PAGE_NX;
273 * The .rodata section needs to be read-only. Using the pfn
274 * catches all aliases.
276 if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT,
277 __pa((unsigned long)__end_rodata) >> PAGE_SHIFT))
278 pgprot_val(forbidden) |= _PAGE_RW;
280 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
286 * Lookup the page table entry for a virtual address. Return a pointer
287 * to the entry and the level of the mapping.
289 * Note: We return pud and pmd either when the entry is marked large
290 * or when the present bit is not set. Otherwise we would return a
291 * pointer to a nonexisting mapping.
293 pte_t *lookup_address(unsigned long address, unsigned int *level)
295 pgd_t *pgd = pgd_offset_k(address);
299 *level = PG_LEVEL_NONE;
304 pud = pud_offset(pgd, address);
308 *level = PG_LEVEL_1G;
309 if (pud_large(*pud) || !pud_present(*pud))
312 pmd = pmd_offset(pud, address);
316 *level = PG_LEVEL_2M;
317 if (pmd_large(*pmd) || !pmd_present(*pmd))
320 *level = PG_LEVEL_4K;
322 return pte_offset_kernel(pmd, address);
324 EXPORT_SYMBOL_GPL(lookup_address);
327 * Set the new pmd in all the pgds we know about:
329 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
332 set_pte_atomic(kpte, pte);
334 if (!SHARED_KERNEL_PMD) {
337 list_for_each_entry(page, &pgd_list, lru) {
342 pgd = (pgd_t *)page_address(page) + pgd_index(address);
343 pud = pud_offset(pgd, address);
344 pmd = pmd_offset(pud, address);
345 set_pte_atomic((pte_t *)pmd, pte);
352 try_preserve_large_page(pte_t *kpte, unsigned long address,
353 struct cpa_data *cpa)
355 unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn;
356 pte_t new_pte, old_pte, *tmp;
357 pgprot_t old_prot, new_prot;
361 if (cpa->force_split)
364 spin_lock_irqsave(&pgd_lock, flags);
366 * Check for races, another CPU might have split this page
369 tmp = lookup_address(address, &level);
375 psize = PMD_PAGE_SIZE;
376 pmask = PMD_PAGE_MASK;
380 psize = PUD_PAGE_SIZE;
381 pmask = PUD_PAGE_MASK;
390 * Calculate the number of pages, which fit into this large
391 * page starting at address:
393 nextpage_addr = (address + psize) & pmask;
394 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
395 if (numpages < cpa->numpages)
396 cpa->numpages = numpages;
399 * We are safe now. Check whether the new pgprot is the same:
402 old_prot = new_prot = pte_pgprot(old_pte);
404 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
405 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
408 * old_pte points to the large page base address. So we need
409 * to add the offset of the virtual address:
411 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
414 new_prot = static_protections(new_prot, address, pfn);
417 * We need to check the full range, whether
418 * static_protection() requires a different pgprot for one of
419 * the pages in the range we try to preserve:
421 addr = address + PAGE_SIZE;
423 for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) {
424 pgprot_t chk_prot = static_protections(new_prot, addr, pfn);
426 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
431 * If there are no changes, return. maxpages has been updated
434 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
440 * We need to change the attributes. Check, whether we can
441 * change the large page in one go. We request a split, when
442 * the address is not aligned and the number of pages is
443 * smaller than the number of pages in the large page. Note
444 * that we limited the number of possible pages already to
445 * the number of pages in the large page.
447 if (address == (nextpage_addr - psize) && cpa->numpages == numpages) {
449 * The address is aligned and the number of pages
450 * covers the full page.
452 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
453 __set_pmd_pte(kpte, address, new_pte);
454 cpa->flags |= CPA_FLUSHTLB;
459 spin_unlock_irqrestore(&pgd_lock, flags);
464 static int split_large_page(pte_t *kpte, unsigned long address)
466 unsigned long flags, pfn, pfninc = 1;
467 unsigned int i, level;
472 if (!debug_pagealloc)
473 spin_unlock(&cpa_lock);
474 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
475 if (!debug_pagealloc)
476 spin_lock(&cpa_lock);
480 spin_lock_irqsave(&pgd_lock, flags);
482 * Check for races, another CPU might have split this page
485 tmp = lookup_address(address, &level);
489 pbase = (pte_t *)page_address(base);
490 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
491 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
493 * If we ever want to utilize the PAT bit, we need to
494 * update this function to make sure it's converted from
495 * bit 12 to bit 7 when we cross from the 2MB level to
498 WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
501 if (level == PG_LEVEL_1G) {
502 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
503 pgprot_val(ref_prot) |= _PAGE_PSE;
508 * Get the target pfn from the original entry:
510 pfn = pte_pfn(*kpte);
511 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
512 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
514 if (address >= (unsigned long)__va(0) &&
515 address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT))
516 split_page_count(level);
519 if (address >= (unsigned long)__va(1UL<<32) &&
520 address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT))
521 split_page_count(level);
525 * Install the new, split up pagetable.
527 * We use the standard kernel pagetable protections for the new
528 * pagetable protections, the actual ptes set above control the
529 * primary protection behavior:
531 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
534 * Intel Atom errata AAH41 workaround.
536 * The real fix should be in hw or in a microcode update, but
537 * we also probabilistically try to reduce the window of having
538 * a large TLB mixed with 4K TLBs while instruction fetches are
547 * If we dropped out via the lookup_address check under
548 * pgd_lock then stick the page back into the pool:
552 spin_unlock_irqrestore(&pgd_lock, flags);
557 static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
561 * Ignore all non primary paths.
567 * Ignore the NULL PTE for kernel identity mapping, as it is expected
569 * Also set numpages to '1' indicating that we processed cpa req for
570 * one virtual address page and its pfn. TBD: numpages can be set based
571 * on the initial value and the level returned by lookup_address().
573 if (within(vaddr, PAGE_OFFSET,
574 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
576 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
579 WARN(1, KERN_WARNING "CPA: called for zero pte. "
580 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
587 static int __change_page_attr(struct cpa_data *cpa, int primary)
589 unsigned long address;
592 pte_t *kpte, old_pte;
594 if (cpa->flags & CPA_PAGES_ARRAY)
595 address = (unsigned long)page_address(cpa->pages[cpa->curpage]);
596 else if (cpa->flags & CPA_ARRAY)
597 address = cpa->vaddr[cpa->curpage];
599 address = *cpa->vaddr;
601 kpte = lookup_address(address, &level);
603 return __cpa_process_fault(cpa, address, primary);
606 if (!pte_val(old_pte))
607 return __cpa_process_fault(cpa, address, primary);
609 if (level == PG_LEVEL_4K) {
611 pgprot_t new_prot = pte_pgprot(old_pte);
612 unsigned long pfn = pte_pfn(old_pte);
614 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
615 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
617 new_prot = static_protections(new_prot, address, pfn);
620 * We need to keep the pfn from the existing PTE,
621 * after all we're only going to change it's attributes
622 * not the memory it points to
624 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
627 * Do we really change anything ?
629 if (pte_val(old_pte) != pte_val(new_pte)) {
630 set_pte_atomic(kpte, new_pte);
631 cpa->flags |= CPA_FLUSHTLB;
638 * Check, whether we can keep the large page intact
639 * and just change the pte:
641 do_split = try_preserve_large_page(kpte, address, cpa);
643 * When the range fits into the existing large page,
644 * return. cp->numpages and cpa->tlbflush have been updated in
651 * We have to split the large page:
653 err = split_large_page(kpte, address);
656 * Do a global flush tlb after splitting the large page
657 * and before we do the actual change page attribute in the PTE.
659 * With out this, we violate the TLB application note, that says
660 * "The TLBs may contain both ordinary and large-page
661 * translations for a 4-KByte range of linear addresses. This
662 * may occur if software modifies the paging structures so that
663 * the page size used for the address range changes. If the two
664 * translations differ with respect to page frame or attributes
665 * (e.g., permissions), processor behavior is undefined and may
666 * be implementation-specific."
668 * We do this global tlb flush inside the cpa_lock, so that we
669 * don't allow any other cpu, with stale tlb entries change the
670 * page attribute in parallel, that also falls into the
671 * just split large page entry.
680 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
682 static int cpa_process_alias(struct cpa_data *cpa)
684 struct cpa_data alias_cpa;
685 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
686 unsigned long vaddr, remapped;
689 if (cpa->pfn >= max_pfn_mapped)
693 if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT)))
697 * No need to redo, when the primary call touched the direct
700 if (cpa->flags & CPA_PAGES_ARRAY)
701 vaddr = (unsigned long)page_address(cpa->pages[cpa->curpage]);
702 else if (cpa->flags & CPA_ARRAY)
703 vaddr = cpa->vaddr[cpa->curpage];
707 if (!(within(vaddr, PAGE_OFFSET,
708 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
711 alias_cpa.vaddr = &laddr;
712 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
714 ret = __change_page_attr_set_clr(&alias_cpa, 0);
721 * If the primary call didn't touch the high mapping already
722 * and the physical address is inside the kernel map, we need
723 * to touch the high mapped kernel as well:
725 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
726 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
727 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
728 __START_KERNEL_map - phys_base;
730 alias_cpa.vaddr = &temp_cpa_vaddr;
731 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
734 * The high mapping range is imprecise, so ignore the
737 __change_page_attr_set_clr(&alias_cpa, 0);
742 * If the PMD page was partially used for per-cpu remapping,
743 * the recycled area needs to be split and modified. Because
744 * the area is always proper subset of a PMD page
745 * cpa->numpages is guaranteed to be 1 for these areas, so
746 * there's no need to loop over and check for further remaps.
748 remapped = (unsigned long)pcpu_lpage_remapped((void *)laddr);
750 WARN_ON(cpa->numpages > 1);
752 alias_cpa.vaddr = &remapped;
753 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
754 ret = __change_page_attr_set_clr(&alias_cpa, 0);
762 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
764 int ret, numpages = cpa->numpages;
768 * Store the remaining nr of pages for the large page
769 * preservation check.
771 cpa->numpages = numpages;
772 /* for array changes, we can't use large page */
773 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
776 if (!debug_pagealloc)
777 spin_lock(&cpa_lock);
778 ret = __change_page_attr(cpa, checkalias);
779 if (!debug_pagealloc)
780 spin_unlock(&cpa_lock);
785 ret = cpa_process_alias(cpa);
791 * Adjust the number of pages with the result of the
792 * CPA operation. Either a large page has been
793 * preserved or a single page update happened.
795 BUG_ON(cpa->numpages > numpages);
796 numpages -= cpa->numpages;
797 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
800 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
806 static inline int cache_attr(pgprot_t attr)
808 return pgprot_val(attr) &
809 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
812 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
813 pgprot_t mask_set, pgprot_t mask_clr,
814 int force_split, int in_flag,
818 int ret, cache, checkalias;
821 * Check, if we are requested to change a not supported
824 mask_set = canon_pgprot(mask_set);
825 mask_clr = canon_pgprot(mask_clr);
826 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
829 /* Ensure we are PAGE_SIZE aligned */
830 if (in_flag & CPA_ARRAY) {
832 for (i = 0; i < numpages; i++) {
833 if (addr[i] & ~PAGE_MASK) {
834 addr[i] &= PAGE_MASK;
838 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
840 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
841 * No need to cehck in that case
843 if (*addr & ~PAGE_MASK) {
846 * People should not be passing in unaligned addresses:
852 /* Must avoid aliasing mappings in the highmem code */
859 cpa.numpages = numpages;
860 cpa.mask_set = mask_set;
861 cpa.mask_clr = mask_clr;
864 cpa.force_split = force_split;
866 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
867 cpa.flags |= in_flag;
869 /* No alias checking for _NX bit modifications */
870 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
872 ret = __change_page_attr_set_clr(&cpa, checkalias);
875 * Check whether we really changed something:
877 if (!(cpa.flags & CPA_FLUSHTLB))
881 * No need to flush, when we did not set any of the caching
884 cache = cache_attr(mask_set);
887 * On success we use clflush, when the CPU supports it to
888 * avoid the wbindv. If the CPU does not support it and in the
889 * error case we fall back to cpa_flush_all (which uses
892 if (!ret && cpu_has_clflush) {
893 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
894 cpa_flush_array(addr, numpages, cache,
897 cpa_flush_range(*addr, numpages, cache);
899 cpa_flush_all(cache);
905 static inline int change_page_attr_set(unsigned long *addr, int numpages,
906 pgprot_t mask, int array)
908 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
909 (array ? CPA_ARRAY : 0), NULL);
912 static inline int change_page_attr_clear(unsigned long *addr, int numpages,
913 pgprot_t mask, int array)
915 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
916 (array ? CPA_ARRAY : 0), NULL);
919 static inline int cpa_set_pages_array(struct page **pages, int numpages,
922 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
923 CPA_PAGES_ARRAY, pages);
926 static inline int cpa_clear_pages_array(struct page **pages, int numpages,
929 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
930 CPA_PAGES_ARRAY, pages);
933 int _set_memory_uc(unsigned long addr, int numpages)
936 * for now UC MINUS. see comments in ioremap_nocache()
938 return change_page_attr_set(&addr, numpages,
939 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
942 int set_memory_uc(unsigned long addr, int numpages)
947 * for now UC MINUS. see comments in ioremap_nocache()
949 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
950 _PAGE_CACHE_UC_MINUS, NULL);
954 ret = _set_memory_uc(addr, numpages);
961 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
965 EXPORT_SYMBOL(set_memory_uc);
967 int set_memory_array_uc(unsigned long *addr, int addrinarray)
973 * for now UC MINUS. see comments in ioremap_nocache()
975 for (i = 0; i < addrinarray; i++) {
976 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
977 _PAGE_CACHE_UC_MINUS, NULL);
982 ret = change_page_attr_set(addr, addrinarray,
983 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
990 for (j = 0; j < i; j++)
991 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
995 EXPORT_SYMBOL(set_memory_array_uc);
997 int _set_memory_wc(unsigned long addr, int numpages)
1000 ret = change_page_attr_set(&addr, numpages,
1001 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
1004 ret = change_page_attr_set(&addr, numpages,
1005 __pgprot(_PAGE_CACHE_WC), 0);
1010 int set_memory_wc(unsigned long addr, int numpages)
1015 return set_memory_uc(addr, numpages);
1017 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1018 _PAGE_CACHE_WC, NULL);
1022 ret = _set_memory_wc(addr, numpages);
1029 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1033 EXPORT_SYMBOL(set_memory_wc);
1035 int _set_memory_wb(unsigned long addr, int numpages)
1037 return change_page_attr_clear(&addr, numpages,
1038 __pgprot(_PAGE_CACHE_MASK), 0);
1041 int set_memory_wb(unsigned long addr, int numpages)
1045 ret = _set_memory_wb(addr, numpages);
1049 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1052 EXPORT_SYMBOL(set_memory_wb);
1054 int set_memory_array_wb(unsigned long *addr, int addrinarray)
1059 ret = change_page_attr_clear(addr, addrinarray,
1060 __pgprot(_PAGE_CACHE_MASK), 1);
1064 for (i = 0; i < addrinarray; i++)
1065 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1069 EXPORT_SYMBOL(set_memory_array_wb);
1071 int set_memory_x(unsigned long addr, int numpages)
1073 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1075 EXPORT_SYMBOL(set_memory_x);
1077 int set_memory_nx(unsigned long addr, int numpages)
1079 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1081 EXPORT_SYMBOL(set_memory_nx);
1083 int set_memory_ro(unsigned long addr, int numpages)
1085 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1087 EXPORT_SYMBOL_GPL(set_memory_ro);
1089 int set_memory_rw(unsigned long addr, int numpages)
1091 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1093 EXPORT_SYMBOL_GPL(set_memory_rw);
1095 int set_memory_np(unsigned long addr, int numpages)
1097 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1100 int set_memory_4k(unsigned long addr, int numpages)
1102 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1103 __pgprot(0), 1, 0, NULL);
1106 int set_pages_uc(struct page *page, int numpages)
1108 unsigned long addr = (unsigned long)page_address(page);
1110 return set_memory_uc(addr, numpages);
1112 EXPORT_SYMBOL(set_pages_uc);
1114 int set_pages_array_uc(struct page **pages, int addrinarray)
1116 unsigned long start;
1121 for (i = 0; i < addrinarray; i++) {
1122 start = (unsigned long)page_address(pages[i]);
1123 end = start + PAGE_SIZE;
1124 if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL))
1128 if (cpa_set_pages_array(pages, addrinarray,
1129 __pgprot(_PAGE_CACHE_UC_MINUS)) == 0) {
1130 return 0; /* Success */
1134 for (i = 0; i < free_idx; i++) {
1135 start = (unsigned long)page_address(pages[i]);
1136 end = start + PAGE_SIZE;
1137 free_memtype(start, end);
1141 EXPORT_SYMBOL(set_pages_array_uc);
1143 int set_pages_wb(struct page *page, int numpages)
1145 unsigned long addr = (unsigned long)page_address(page);
1147 return set_memory_wb(addr, numpages);
1149 EXPORT_SYMBOL(set_pages_wb);
1151 int set_pages_array_wb(struct page **pages, int addrinarray)
1154 unsigned long start;
1158 retval = cpa_clear_pages_array(pages, addrinarray,
1159 __pgprot(_PAGE_CACHE_MASK));
1163 for (i = 0; i < addrinarray; i++) {
1164 start = (unsigned long)page_address(pages[i]);
1165 end = start + PAGE_SIZE;
1166 free_memtype(start, end);
1171 EXPORT_SYMBOL(set_pages_array_wb);
1173 int set_pages_x(struct page *page, int numpages)
1175 unsigned long addr = (unsigned long)page_address(page);
1177 return set_memory_x(addr, numpages);
1179 EXPORT_SYMBOL(set_pages_x);
1181 int set_pages_nx(struct page *page, int numpages)
1183 unsigned long addr = (unsigned long)page_address(page);
1185 return set_memory_nx(addr, numpages);
1187 EXPORT_SYMBOL(set_pages_nx);
1189 int set_pages_ro(struct page *page, int numpages)
1191 unsigned long addr = (unsigned long)page_address(page);
1193 return set_memory_ro(addr, numpages);
1196 int set_pages_rw(struct page *page, int numpages)
1198 unsigned long addr = (unsigned long)page_address(page);
1200 return set_memory_rw(addr, numpages);
1203 #ifdef CONFIG_DEBUG_PAGEALLOC
1205 static int __set_pages_p(struct page *page, int numpages)
1207 unsigned long tempaddr = (unsigned long) page_address(page);
1208 struct cpa_data cpa = { .vaddr = &tempaddr,
1209 .numpages = numpages,
1210 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1211 .mask_clr = __pgprot(0),
1215 * No alias checking needed for setting present flag. otherwise,
1216 * we may need to break large pages for 64-bit kernel text
1217 * mappings (this adds to complexity if we want to do this from
1218 * atomic context especially). Let's keep it simple!
1220 return __change_page_attr_set_clr(&cpa, 0);
1223 static int __set_pages_np(struct page *page, int numpages)
1225 unsigned long tempaddr = (unsigned long) page_address(page);
1226 struct cpa_data cpa = { .vaddr = &tempaddr,
1227 .numpages = numpages,
1228 .mask_set = __pgprot(0),
1229 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1233 * No alias checking needed for setting not present flag. otherwise,
1234 * we may need to break large pages for 64-bit kernel text
1235 * mappings (this adds to complexity if we want to do this from
1236 * atomic context especially). Let's keep it simple!
1238 return __change_page_attr_set_clr(&cpa, 0);
1241 void kernel_map_pages(struct page *page, int numpages, int enable)
1243 if (PageHighMem(page))
1246 debug_check_no_locks_freed(page_address(page),
1247 numpages * PAGE_SIZE);
1251 * If page allocator is not up yet then do not call c_p_a():
1253 if (!debug_pagealloc_enabled)
1257 * The return value is ignored as the calls cannot fail.
1258 * Large pages for identity mappings are not used at boot time
1259 * and hence no memory allocations during large page split.
1262 __set_pages_p(page, numpages);
1264 __set_pages_np(page, numpages);
1267 * We should perform an IPI and flush all tlbs,
1268 * but that can deadlock->flush only current cpu:
1273 #ifdef CONFIG_HIBERNATION
1275 bool kernel_page_present(struct page *page)
1280 if (PageHighMem(page))
1283 pte = lookup_address((unsigned long)page_address(page), &level);
1284 return (pte_val(*pte) & _PAGE_PRESENT);
1287 #endif /* CONFIG_HIBERNATION */
1289 #endif /* CONFIG_DEBUG_PAGEALLOC */
1292 * The testcases use internal knowledge of the implementation that shouldn't
1293 * be exposed to the rest of the kernel. Include these directly here.
1295 #ifdef CONFIG_CPA_DEBUG
1296 #include "pageattr-test.c"