1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 instruction analysis
5 * Copyright (C) IBM Corporation, 2002, 2004, 2009
8 #include <linux/kernel.h>
10 #include <linux/string.h>
17 #include <asm/emulate_prefix.h>
19 #define leXX_to_cpu(t, r) \
22 switch (sizeof(t)) { \
23 case 4: v = le32_to_cpu(r); break; \
24 case 2: v = le16_to_cpu(r); break; \
25 case 1: v = r; break; \
32 /* Verify next sizeof(t) bytes can be on the same instruction */
33 #define validate_next(t, insn, n) \
34 ((insn)->next_byte + sizeof(t) + n <= (insn)->end_kaddr)
36 #define __get_next(t, insn) \
37 ({ t r = *(t*)insn->next_byte; insn->next_byte += sizeof(t); leXX_to_cpu(t, r); })
39 #define __peek_nbyte_next(t, insn, n) \
40 ({ t r = *(t*)((insn)->next_byte + n); leXX_to_cpu(t, r); })
42 #define get_next(t, insn) \
43 ({ if (unlikely(!validate_next(t, insn, 0))) goto err_out; __get_next(t, insn); })
45 #define peek_nbyte_next(t, insn, n) \
46 ({ if (unlikely(!validate_next(t, insn, n))) goto err_out; __peek_nbyte_next(t, insn, n); })
48 #define peek_next(t, insn) peek_nbyte_next(t, insn, 0)
51 * insn_init() - initialize struct insn
52 * @insn: &struct insn to be initialized
53 * @kaddr: address (in kernel memory) of instruction (or copy thereof)
54 * @x86_64: !0 for 64-bit kernel or 64-bit app
56 void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64)
59 * Instructions longer than MAX_INSN_SIZE (15 bytes) are invalid
60 * even if the input buffer is long enough to hold them.
62 if (buf_len > MAX_INSN_SIZE)
63 buf_len = MAX_INSN_SIZE;
65 memset(insn, 0, sizeof(*insn));
67 insn->end_kaddr = kaddr + buf_len;
68 insn->next_byte = kaddr;
69 insn->x86_64 = x86_64 ? 1 : 0;
77 static const insn_byte_t xen_prefix[] = { __XEN_EMULATE_PREFIX };
78 static const insn_byte_t kvm_prefix[] = { __KVM_EMULATE_PREFIX };
80 static int __insn_get_emulate_prefix(struct insn *insn,
81 const insn_byte_t *prefix, size_t len)
85 for (i = 0; i < len; i++) {
86 if (peek_nbyte_next(insn_byte_t, insn, i) != prefix[i])
90 insn->emulate_prefix_size = len;
91 insn->next_byte += len;
99 static void insn_get_emulate_prefix(struct insn *insn)
101 if (__insn_get_emulate_prefix(insn, xen_prefix, sizeof(xen_prefix)))
104 __insn_get_emulate_prefix(insn, kvm_prefix, sizeof(kvm_prefix));
108 * insn_get_prefixes - scan x86 instruction prefix bytes
109 * @insn: &struct insn containing instruction
111 * Populates the @insn->prefixes bitmap, and updates @insn->next_byte
112 * to point to the (first) opcode. No effect if @insn->prefixes.got
115 void insn_get_prefixes(struct insn *insn)
117 struct insn_field *prefixes = &insn->prefixes;
125 insn_get_emulate_prefix(insn);
129 b = peek_next(insn_byte_t, insn);
130 attr = inat_get_opcode_attribute(b);
131 while (inat_is_legacy_prefix(attr)) {
132 /* Skip if same prefix */
133 for (i = 0; i < nb; i++)
134 if (prefixes->bytes[i] == b)
137 /* Invalid instruction */
139 prefixes->bytes[nb++] = b;
140 if (inat_is_address_size_prefix(attr)) {
141 /* address size switches 2/4 or 4/8 */
143 insn->addr_bytes ^= 12;
145 insn->addr_bytes ^= 6;
146 } else if (inat_is_operand_size_prefix(attr)) {
147 /* oprand size switches 2/4 */
148 insn->opnd_bytes ^= 6;
154 b = peek_next(insn_byte_t, insn);
155 attr = inat_get_opcode_attribute(b);
157 /* Set the last prefix */
158 if (lb && lb != insn->prefixes.bytes[3]) {
159 if (unlikely(insn->prefixes.bytes[3])) {
160 /* Swap the last prefix */
161 b = insn->prefixes.bytes[3];
162 for (i = 0; i < nb; i++)
163 if (prefixes->bytes[i] == lb)
164 insn_set_byte(prefixes, i, b);
166 insn_set_byte(&insn->prefixes, 3, lb);
169 /* Decode REX prefix */
171 b = peek_next(insn_byte_t, insn);
172 attr = inat_get_opcode_attribute(b);
173 if (inat_is_rex_prefix(attr)) {
174 insn_field_set(&insn->rex_prefix, b, 1);
177 /* REX.W overrides opnd_size */
178 insn->opnd_bytes = 8;
181 insn->rex_prefix.got = 1;
183 /* Decode VEX prefix */
184 b = peek_next(insn_byte_t, insn);
185 attr = inat_get_opcode_attribute(b);
186 if (inat_is_vex_prefix(attr)) {
187 insn_byte_t b2 = peek_nbyte_next(insn_byte_t, insn, 1);
190 * In 32-bits mode, if the [7:6] bits (mod bits of
191 * ModRM) on the second byte are not 11b, it is
192 * LDS or LES or BOUND.
194 if (X86_MODRM_MOD(b2) != 3)
197 insn_set_byte(&insn->vex_prefix, 0, b);
198 insn_set_byte(&insn->vex_prefix, 1, b2);
199 if (inat_is_evex_prefix(attr)) {
200 b2 = peek_nbyte_next(insn_byte_t, insn, 2);
201 insn_set_byte(&insn->vex_prefix, 2, b2);
202 b2 = peek_nbyte_next(insn_byte_t, insn, 3);
203 insn_set_byte(&insn->vex_prefix, 3, b2);
204 insn->vex_prefix.nbytes = 4;
205 insn->next_byte += 4;
206 if (insn->x86_64 && X86_VEX_W(b2))
207 /* VEX.W overrides opnd_size */
208 insn->opnd_bytes = 8;
209 } else if (inat_is_vex3_prefix(attr)) {
210 b2 = peek_nbyte_next(insn_byte_t, insn, 2);
211 insn_set_byte(&insn->vex_prefix, 2, b2);
212 insn->vex_prefix.nbytes = 3;
213 insn->next_byte += 3;
214 if (insn->x86_64 && X86_VEX_W(b2))
215 /* VEX.W overrides opnd_size */
216 insn->opnd_bytes = 8;
219 * For VEX2, fake VEX3-like byte#2.
220 * Makes it easier to decode vex.W, vex.vvvv,
221 * vex.L and vex.pp. Masking with 0x7f sets vex.W == 0.
223 insn_set_byte(&insn->vex_prefix, 2, b2 & 0x7f);
224 insn->vex_prefix.nbytes = 2;
225 insn->next_byte += 2;
229 insn->vex_prefix.got = 1;
238 * insn_get_opcode - collect opcode(s)
239 * @insn: &struct insn containing instruction
241 * Populates @insn->opcode, updates @insn->next_byte to point past the
242 * opcode byte(s), and set @insn->attr (except for groups).
243 * If necessary, first collects any preceding (prefix) bytes.
244 * Sets @insn->opcode.value = opcode1. No effect if @insn->opcode.got
247 void insn_get_opcode(struct insn *insn)
249 struct insn_field *opcode = &insn->opcode;
254 if (!insn->prefixes.got)
255 insn_get_prefixes(insn);
257 /* Get first opcode */
258 op = get_next(insn_byte_t, insn);
259 insn_set_byte(opcode, 0, op);
262 /* Check if there is VEX prefix or not */
263 if (insn_is_avx(insn)) {
265 m = insn_vex_m_bits(insn);
266 p = insn_vex_p_bits(insn);
267 insn->attr = inat_get_avx_attribute(op, m, p);
268 if ((inat_must_evex(insn->attr) && !insn_is_evex(insn)) ||
269 (!inat_accept_vex(insn->attr) &&
270 !inat_is_group(insn->attr)))
271 insn->attr = 0; /* This instruction is bad */
272 goto end; /* VEX has only 1 byte for opcode */
275 insn->attr = inat_get_opcode_attribute(op);
276 while (inat_is_escape(insn->attr)) {
277 /* Get escaped opcode */
278 op = get_next(insn_byte_t, insn);
279 opcode->bytes[opcode->nbytes++] = op;
280 pfx_id = insn_last_prefix_id(insn);
281 insn->attr = inat_get_escape_attribute(op, pfx_id, insn->attr);
283 if (inat_must_vex(insn->attr))
284 insn->attr = 0; /* This instruction is bad */
293 * insn_get_modrm - collect ModRM byte, if any
294 * @insn: &struct insn containing instruction
296 * Populates @insn->modrm and updates @insn->next_byte to point past the
297 * ModRM byte, if any. If necessary, first collects the preceding bytes
298 * (prefixes and opcode(s)). No effect if @insn->modrm.got is already 1.
300 void insn_get_modrm(struct insn *insn)
302 struct insn_field *modrm = &insn->modrm;
303 insn_byte_t pfx_id, mod;
306 if (!insn->opcode.got)
307 insn_get_opcode(insn);
309 if (inat_has_modrm(insn->attr)) {
310 mod = get_next(insn_byte_t, insn);
311 insn_field_set(modrm, mod, 1);
312 if (inat_is_group(insn->attr)) {
313 pfx_id = insn_last_prefix_id(insn);
314 insn->attr = inat_get_group_attribute(mod, pfx_id,
316 if (insn_is_avx(insn) && !inat_accept_vex(insn->attr))
317 insn->attr = 0; /* This is bad */
321 if (insn->x86_64 && inat_is_force64(insn->attr))
322 insn->opnd_bytes = 8;
331 * insn_rip_relative() - Does instruction use RIP-relative addressing mode?
332 * @insn: &struct insn containing instruction
334 * If necessary, first collects the instruction up to and including the
335 * ModRM byte. No effect if @insn->x86_64 is 0.
337 int insn_rip_relative(struct insn *insn)
339 struct insn_field *modrm = &insn->modrm;
344 insn_get_modrm(insn);
346 * For rip-relative instructions, the mod field (top 2 bits)
347 * is zero and the r/m field (bottom 3 bits) is 0x5.
349 return (modrm->nbytes && (modrm->bytes[0] & 0xc7) == 0x5);
353 * insn_get_sib() - Get the SIB byte of instruction
354 * @insn: &struct insn containing instruction
356 * If necessary, first collects the instruction up to and including the
359 void insn_get_sib(struct insn *insn)
365 if (!insn->modrm.got)
366 insn_get_modrm(insn);
367 if (insn->modrm.nbytes) {
368 modrm = insn->modrm.bytes[0];
369 if (insn->addr_bytes != 2 &&
370 X86_MODRM_MOD(modrm) != 3 && X86_MODRM_RM(modrm) == 4) {
371 insn_field_set(&insn->sib,
372 get_next(insn_byte_t, insn), 1);
383 * insn_get_displacement() - Get the displacement of instruction
384 * @insn: &struct insn containing instruction
386 * If necessary, first collects the instruction up to and including the
388 * Displacement value is sign-expanded.
390 void insn_get_displacement(struct insn *insn)
392 insn_byte_t mod, rm, base;
394 if (insn->displacement.got)
398 if (insn->modrm.nbytes) {
400 * Interpreting the modrm byte:
401 * mod = 00 - no displacement fields (exceptions below)
402 * mod = 01 - 1-byte displacement field
403 * mod = 10 - displacement field is 4 bytes, or 2 bytes if
404 * address size = 2 (0x67 prefix in 32-bit mode)
405 * mod = 11 - no memory operand
407 * If address size = 2...
408 * mod = 00, r/m = 110 - displacement field is 2 bytes
410 * If address size != 2...
411 * mod != 11, r/m = 100 - SIB byte exists
412 * mod = 00, SIB base = 101 - displacement field is 4 bytes
413 * mod = 00, r/m = 101 - rip-relative addressing, displacement
416 mod = X86_MODRM_MOD(insn->modrm.value);
417 rm = X86_MODRM_RM(insn->modrm.value);
418 base = X86_SIB_BASE(insn->sib.value);
422 insn_field_set(&insn->displacement,
423 get_next(signed char, insn), 1);
424 } else if (insn->addr_bytes == 2) {
425 if ((mod == 0 && rm == 6) || mod == 2) {
426 insn_field_set(&insn->displacement,
427 get_next(short, insn), 2);
430 if ((mod == 0 && rm == 5) || mod == 2 ||
431 (mod == 0 && base == 5)) {
432 insn_field_set(&insn->displacement,
433 get_next(int, insn), 4);
438 insn->displacement.got = 1;
444 /* Decode moffset16/32/64. Return 0 if failed */
445 static int __get_moffset(struct insn *insn)
447 switch (insn->addr_bytes) {
449 insn_field_set(&insn->moffset1, get_next(short, insn), 2);
452 insn_field_set(&insn->moffset1, get_next(int, insn), 4);
455 insn_field_set(&insn->moffset1, get_next(int, insn), 4);
456 insn_field_set(&insn->moffset2, get_next(int, insn), 4);
458 default: /* opnd_bytes must be modified manually */
461 insn->moffset1.got = insn->moffset2.got = 1;
469 /* Decode imm v32(Iz). Return 0 if failed */
470 static int __get_immv32(struct insn *insn)
472 switch (insn->opnd_bytes) {
474 insn_field_set(&insn->immediate, get_next(short, insn), 2);
478 insn_field_set(&insn->immediate, get_next(int, insn), 4);
480 default: /* opnd_bytes must be modified manually */
490 /* Decode imm v64(Iv/Ov), Return 0 if failed */
491 static int __get_immv(struct insn *insn)
493 switch (insn->opnd_bytes) {
495 insn_field_set(&insn->immediate1, get_next(short, insn), 2);
498 insn_field_set(&insn->immediate1, get_next(int, insn), 4);
499 insn->immediate1.nbytes = 4;
502 insn_field_set(&insn->immediate1, get_next(int, insn), 4);
503 insn_field_set(&insn->immediate2, get_next(int, insn), 4);
505 default: /* opnd_bytes must be modified manually */
508 insn->immediate1.got = insn->immediate2.got = 1;
515 /* Decode ptr16:16/32(Ap) */
516 static int __get_immptr(struct insn *insn)
518 switch (insn->opnd_bytes) {
520 insn_field_set(&insn->immediate1, get_next(short, insn), 2);
523 insn_field_set(&insn->immediate1, get_next(int, insn), 4);
526 /* ptr16:64 is not exist (no segment) */
528 default: /* opnd_bytes must be modified manually */
531 insn_field_set(&insn->immediate2, get_next(unsigned short, insn), 2);
532 insn->immediate1.got = insn->immediate2.got = 1;
540 * insn_get_immediate() - Get the immediates of instruction
541 * @insn: &struct insn containing instruction
543 * If necessary, first collects the instruction up to and including the
544 * displacement bytes.
545 * Basically, most of immediates are sign-expanded. Unsigned-value can be
546 * get by bit masking with ((1 << (nbytes * 8)) - 1)
548 void insn_get_immediate(struct insn *insn)
550 if (insn->immediate.got)
552 if (!insn->displacement.got)
553 insn_get_displacement(insn);
555 if (inat_has_moffset(insn->attr)) {
556 if (!__get_moffset(insn))
561 if (!inat_has_immediate(insn->attr))
565 switch (inat_immediate_size(insn->attr)) {
567 insn_field_set(&insn->immediate, get_next(signed char, insn), 1);
570 insn_field_set(&insn->immediate, get_next(short, insn), 2);
573 insn_field_set(&insn->immediate, get_next(int, insn), 4);
576 insn_field_set(&insn->immediate1, get_next(int, insn), 4);
577 insn_field_set(&insn->immediate2, get_next(int, insn), 4);
580 if (!__get_immptr(insn))
583 case INAT_IMM_VWORD32:
584 if (!__get_immv32(insn))
588 if (!__get_immv(insn))
592 /* Here, insn must have an immediate, but failed */
595 if (inat_has_second_immediate(insn->attr)) {
596 insn_field_set(&insn->immediate2, get_next(signed char, insn), 1);
599 insn->immediate.got = 1;
606 * insn_get_length() - Get the length of instruction
607 * @insn: &struct insn containing instruction
609 * If necessary, first collects the instruction up to and including the
612 void insn_get_length(struct insn *insn)
616 if (!insn->immediate.got)
617 insn_get_immediate(insn);
618 insn->length = (unsigned char)((unsigned long)insn->next_byte
619 - (unsigned long)insn->kaddr);