1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/sched/isolation.h>
58 #include <linux/mem_encrypt.h>
59 #include <linux/entry-kvm.h>
60 #include <linux/suspend.h>
62 #include <trace/events/kvm.h>
64 #include <asm/debugreg.h>
69 #include <linux/kernel_stat.h>
70 #include <asm/fpu/api.h>
71 #include <asm/fpu/xcr.h>
72 #include <asm/fpu/xstate.h>
73 #include <asm/pvclock.h>
74 #include <asm/div64.h>
75 #include <asm/irq_remapping.h>
76 #include <asm/mshyperv.h>
77 #include <asm/hypervisor.h>
78 #include <asm/tlbflush.h>
79 #include <asm/intel_pt.h>
80 #include <asm/emulate_prefix.h>
82 #include <clocksource/hyperv_timer.h>
84 #define CREATE_TRACE_POINTS
87 #define MAX_IO_MSRS 256
88 #define KVM_MAX_MCE_BANKS 32
90 struct kvm_caps kvm_caps __read_mostly = {
91 .supported_mce_cap = MCG_CTL_P | MCG_SER_P,
93 EXPORT_SYMBOL_GPL(kvm_caps);
95 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
97 #define emul_to_vcpu(ctxt) \
98 ((struct kvm_vcpu *)(ctxt)->vcpu)
101 * - enable syscall per default because its emulated by KVM
102 * - enable LME and LMA per default on 64 bit KVM
106 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
108 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
111 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
113 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
115 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
117 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
118 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
120 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
121 static void process_nmi(struct kvm_vcpu *vcpu);
122 static void process_smi(struct kvm_vcpu *vcpu);
123 static void enter_smm(struct kvm_vcpu *vcpu);
124 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
125 static void store_regs(struct kvm_vcpu *vcpu);
126 static int sync_regs(struct kvm_vcpu *vcpu);
127 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
129 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
130 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
132 struct kvm_x86_ops kvm_x86_ops __read_mostly;
134 #define KVM_X86_OP(func) \
135 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
136 *(((struct kvm_x86_ops *)0)->func));
137 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
138 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
139 #include <asm/kvm-x86-ops.h>
140 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
141 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
143 static bool __read_mostly ignore_msrs = 0;
144 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
146 bool __read_mostly report_ignored_msrs = true;
147 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
148 EXPORT_SYMBOL_GPL(report_ignored_msrs);
150 unsigned int min_timer_period_us = 200;
151 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
153 static bool __read_mostly kvmclock_periodic_sync = true;
154 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
156 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
157 static u32 __read_mostly tsc_tolerance_ppm = 250;
158 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
161 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
162 * adaptive tuning starting from default advancement of 1000ns. '0' disables
163 * advancement entirely. Any other value is used as-is and disables adaptive
164 * tuning, i.e. allows privileged userspace to set an exact advancement time.
166 static int __read_mostly lapic_timer_advance_ns = -1;
167 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
169 static bool __read_mostly vector_hashing = true;
170 module_param(vector_hashing, bool, S_IRUGO);
172 bool __read_mostly enable_vmware_backdoor = false;
173 module_param(enable_vmware_backdoor, bool, S_IRUGO);
174 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
176 static bool __read_mostly force_emulation_prefix = false;
177 module_param(force_emulation_prefix, bool, S_IRUGO);
179 int __read_mostly pi_inject_timer = -1;
180 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
182 /* Enable/disable PMU virtualization */
183 bool __read_mostly enable_pmu = true;
184 EXPORT_SYMBOL_GPL(enable_pmu);
185 module_param(enable_pmu, bool, 0444);
187 bool __read_mostly eager_page_split = true;
188 module_param(eager_page_split, bool, 0644);
191 * Restoring the host value for MSRs that are only consumed when running in
192 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
193 * returns to userspace, i.e. the kernel can run with the guest's value.
195 #define KVM_MAX_NR_USER_RETURN_MSRS 16
197 struct kvm_user_return_msrs {
198 struct user_return_notifier urn;
200 struct kvm_user_return_msr_values {
203 } values[KVM_MAX_NR_USER_RETURN_MSRS];
206 u32 __read_mostly kvm_nr_uret_msrs;
207 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
208 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
209 static struct kvm_user_return_msrs __percpu *user_return_msrs;
211 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
212 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
213 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
214 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
216 u64 __read_mostly host_efer;
217 EXPORT_SYMBOL_GPL(host_efer);
219 bool __read_mostly allow_smaller_maxphyaddr = 0;
220 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
222 bool __read_mostly enable_apicv = true;
223 EXPORT_SYMBOL_GPL(enable_apicv);
225 u64 __read_mostly host_xss;
226 EXPORT_SYMBOL_GPL(host_xss);
228 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
229 KVM_GENERIC_VM_STATS(),
230 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
231 STATS_DESC_COUNTER(VM, mmu_pte_write),
232 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
233 STATS_DESC_COUNTER(VM, mmu_flooded),
234 STATS_DESC_COUNTER(VM, mmu_recycled),
235 STATS_DESC_COUNTER(VM, mmu_cache_miss),
236 STATS_DESC_ICOUNTER(VM, mmu_unsync),
237 STATS_DESC_ICOUNTER(VM, pages_4k),
238 STATS_DESC_ICOUNTER(VM, pages_2m),
239 STATS_DESC_ICOUNTER(VM, pages_1g),
240 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
241 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
242 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
245 const struct kvm_stats_header kvm_vm_stats_header = {
246 .name_size = KVM_STATS_NAME_SIZE,
247 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
248 .id_offset = sizeof(struct kvm_stats_header),
249 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
250 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
251 sizeof(kvm_vm_stats_desc),
254 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
255 KVM_GENERIC_VCPU_STATS(),
256 STATS_DESC_COUNTER(VCPU, pf_taken),
257 STATS_DESC_COUNTER(VCPU, pf_fixed),
258 STATS_DESC_COUNTER(VCPU, pf_emulate),
259 STATS_DESC_COUNTER(VCPU, pf_spurious),
260 STATS_DESC_COUNTER(VCPU, pf_fast),
261 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created),
262 STATS_DESC_COUNTER(VCPU, pf_guest),
263 STATS_DESC_COUNTER(VCPU, tlb_flush),
264 STATS_DESC_COUNTER(VCPU, invlpg),
265 STATS_DESC_COUNTER(VCPU, exits),
266 STATS_DESC_COUNTER(VCPU, io_exits),
267 STATS_DESC_COUNTER(VCPU, mmio_exits),
268 STATS_DESC_COUNTER(VCPU, signal_exits),
269 STATS_DESC_COUNTER(VCPU, irq_window_exits),
270 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
271 STATS_DESC_COUNTER(VCPU, l1d_flush),
272 STATS_DESC_COUNTER(VCPU, halt_exits),
273 STATS_DESC_COUNTER(VCPU, request_irq_exits),
274 STATS_DESC_COUNTER(VCPU, irq_exits),
275 STATS_DESC_COUNTER(VCPU, host_state_reload),
276 STATS_DESC_COUNTER(VCPU, fpu_reload),
277 STATS_DESC_COUNTER(VCPU, insn_emulation),
278 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
279 STATS_DESC_COUNTER(VCPU, hypercalls),
280 STATS_DESC_COUNTER(VCPU, irq_injections),
281 STATS_DESC_COUNTER(VCPU, nmi_injections),
282 STATS_DESC_COUNTER(VCPU, req_event),
283 STATS_DESC_COUNTER(VCPU, nested_run),
284 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
285 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
286 STATS_DESC_COUNTER(VCPU, preemption_reported),
287 STATS_DESC_COUNTER(VCPU, preemption_other),
288 STATS_DESC_IBOOLEAN(VCPU, guest_mode),
289 STATS_DESC_COUNTER(VCPU, notify_window_exits),
292 const struct kvm_stats_header kvm_vcpu_stats_header = {
293 .name_size = KVM_STATS_NAME_SIZE,
294 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
295 .id_offset = sizeof(struct kvm_stats_header),
296 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
297 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
298 sizeof(kvm_vcpu_stats_desc),
301 u64 __read_mostly host_xcr0;
303 static struct kmem_cache *x86_emulator_cache;
306 * When called, it means the previous get/set msr reached an invalid msr.
307 * Return true if we want to ignore/silent this failed msr access.
309 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
311 const char *op = write ? "wrmsr" : "rdmsr";
314 if (report_ignored_msrs)
315 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
320 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
326 static struct kmem_cache *kvm_alloc_emulator_cache(void)
328 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
329 unsigned int size = sizeof(struct x86_emulate_ctxt);
331 return kmem_cache_create_usercopy("x86_emulator", size,
332 __alignof__(struct x86_emulate_ctxt),
333 SLAB_ACCOUNT, useroffset,
334 size - useroffset, NULL);
337 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
339 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
342 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
343 vcpu->arch.apf.gfns[i] = ~0;
346 static void kvm_on_user_return(struct user_return_notifier *urn)
349 struct kvm_user_return_msrs *msrs
350 = container_of(urn, struct kvm_user_return_msrs, urn);
351 struct kvm_user_return_msr_values *values;
355 * Disabling irqs at this point since the following code could be
356 * interrupted and executed through kvm_arch_hardware_disable()
358 local_irq_save(flags);
359 if (msrs->registered) {
360 msrs->registered = false;
361 user_return_notifier_unregister(urn);
363 local_irq_restore(flags);
364 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
365 values = &msrs->values[slot];
366 if (values->host != values->curr) {
367 wrmsrl(kvm_uret_msrs_list[slot], values->host);
368 values->curr = values->host;
373 static int kvm_probe_user_return_msr(u32 msr)
379 ret = rdmsrl_safe(msr, &val);
382 ret = wrmsrl_safe(msr, val);
388 int kvm_add_user_return_msr(u32 msr)
390 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
392 if (kvm_probe_user_return_msr(msr))
395 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
396 return kvm_nr_uret_msrs++;
398 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
400 int kvm_find_user_return_msr(u32 msr)
404 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
405 if (kvm_uret_msrs_list[i] == msr)
410 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
412 static void kvm_user_return_msr_cpu_online(void)
414 unsigned int cpu = smp_processor_id();
415 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
419 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
420 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
421 msrs->values[i].host = value;
422 msrs->values[i].curr = value;
426 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
428 unsigned int cpu = smp_processor_id();
429 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
432 value = (value & mask) | (msrs->values[slot].host & ~mask);
433 if (value == msrs->values[slot].curr)
435 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
439 msrs->values[slot].curr = value;
440 if (!msrs->registered) {
441 msrs->urn.on_user_return = kvm_on_user_return;
442 user_return_notifier_register(&msrs->urn);
443 msrs->registered = true;
447 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
449 static void drop_user_return_notifiers(void)
451 unsigned int cpu = smp_processor_id();
452 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
454 if (msrs->registered)
455 kvm_on_user_return(&msrs->urn);
458 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
460 return vcpu->arch.apic_base;
462 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
464 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
466 return kvm_apic_mode(kvm_get_apic_base(vcpu));
468 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
470 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
472 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
473 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
474 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
475 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
477 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
479 if (!msr_info->host_initiated) {
480 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
482 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
486 kvm_lapic_set_base(vcpu, msr_info->data);
487 kvm_recalculate_apic_map(vcpu->kvm);
490 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
493 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
495 * Hardware virtualization extension instructions may fault if a reboot turns
496 * off virtualization while processes are running. Usually after catching the
497 * fault we just panic; during reboot instead the instruction is ignored.
499 noinstr void kvm_spurious_fault(void)
501 /* Fault while not rebooting. We want the trace. */
502 BUG_ON(!kvm_rebooting);
504 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
506 #define EXCPT_BENIGN 0
507 #define EXCPT_CONTRIBUTORY 1
510 static int exception_class(int vector)
520 return EXCPT_CONTRIBUTORY;
527 #define EXCPT_FAULT 0
529 #define EXCPT_ABORT 2
530 #define EXCPT_INTERRUPT 3
532 static int exception_type(int vector)
536 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
537 return EXCPT_INTERRUPT;
541 /* #DB is trap, as instruction watchpoints are handled elsewhere */
542 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
545 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
548 /* Reserved exceptions will result in fault */
552 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
554 unsigned nr = vcpu->arch.exception.nr;
555 bool has_payload = vcpu->arch.exception.has_payload;
556 unsigned long payload = vcpu->arch.exception.payload;
564 * "Certain debug exceptions may clear bit 0-3. The
565 * remaining contents of the DR6 register are never
566 * cleared by the processor".
568 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
570 * In order to reflect the #DB exception payload in guest
571 * dr6, three components need to be considered: active low
572 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
574 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
575 * In the target guest dr6:
576 * FIXED_1 bits should always be set.
577 * Active low bits should be cleared if 1-setting in payload.
578 * Active high bits should be set if 1-setting in payload.
580 * Note, the payload is compatible with the pending debug
581 * exceptions/exit qualification under VMX, that active_low bits
582 * are active high in payload.
583 * So they need to be flipped for DR6.
585 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
586 vcpu->arch.dr6 |= payload;
587 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW;
590 * The #DB payload is defined as compatible with the 'pending
591 * debug exceptions' field under VMX, not DR6. While bit 12 is
592 * defined in the 'pending debug exceptions' field (enabled
593 * breakpoint), it is reserved and must be zero in DR6.
595 vcpu->arch.dr6 &= ~BIT(12);
598 vcpu->arch.cr2 = payload;
602 vcpu->arch.exception.has_payload = false;
603 vcpu->arch.exception.payload = 0;
605 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
607 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
608 unsigned nr, bool has_error, u32 error_code,
609 bool has_payload, unsigned long payload, bool reinject)
614 kvm_make_request(KVM_REQ_EVENT, vcpu);
616 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
620 * On vmentry, vcpu->arch.exception.pending is only
621 * true if an event injection was blocked by
622 * nested_run_pending. In that case, however,
623 * vcpu_enter_guest requests an immediate exit,
624 * and the guest shouldn't proceed far enough to
627 WARN_ON_ONCE(vcpu->arch.exception.pending);
628 vcpu->arch.exception.injected = true;
629 if (WARN_ON_ONCE(has_payload)) {
631 * A reinjected event has already
632 * delivered its payload.
638 vcpu->arch.exception.pending = true;
639 vcpu->arch.exception.injected = false;
641 vcpu->arch.exception.has_error_code = has_error;
642 vcpu->arch.exception.nr = nr;
643 vcpu->arch.exception.error_code = error_code;
644 vcpu->arch.exception.has_payload = has_payload;
645 vcpu->arch.exception.payload = payload;
646 if (!is_guest_mode(vcpu))
647 kvm_deliver_exception_payload(vcpu);
651 /* to check exception */
652 prev_nr = vcpu->arch.exception.nr;
653 if (prev_nr == DF_VECTOR) {
654 /* triple fault -> shutdown */
655 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
658 class1 = exception_class(prev_nr);
659 class2 = exception_class(nr);
660 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
661 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
663 * Generate double fault per SDM Table 5-5. Set
664 * exception.pending = true so that the double fault
665 * can trigger a nested vmexit.
667 vcpu->arch.exception.pending = true;
668 vcpu->arch.exception.injected = false;
669 vcpu->arch.exception.has_error_code = true;
670 vcpu->arch.exception.nr = DF_VECTOR;
671 vcpu->arch.exception.error_code = 0;
672 vcpu->arch.exception.has_payload = false;
673 vcpu->arch.exception.payload = 0;
675 /* replace previous exception with a new one in a hope
676 that instruction re-execution will regenerate lost
681 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
683 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
685 EXPORT_SYMBOL_GPL(kvm_queue_exception);
687 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
689 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
691 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
693 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
694 unsigned long payload)
696 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
698 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
700 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
701 u32 error_code, unsigned long payload)
703 kvm_multiple_exception(vcpu, nr, true, error_code,
704 true, payload, false);
707 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
710 kvm_inject_gp(vcpu, 0);
712 return kvm_skip_emulated_instruction(vcpu);
716 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
718 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
721 kvm_inject_gp(vcpu, 0);
725 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
726 EMULTYPE_COMPLETE_USER_EXIT);
729 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
731 ++vcpu->stat.pf_guest;
732 vcpu->arch.exception.nested_apf =
733 is_guest_mode(vcpu) && fault->async_page_fault;
734 if (vcpu->arch.exception.nested_apf) {
735 vcpu->arch.apf.nested_apf_token = fault->address;
736 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
738 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
742 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
744 /* Returns true if the page fault was immediately morphed into a VM-Exit. */
745 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
746 struct x86_exception *fault)
748 struct kvm_mmu *fault_mmu;
749 WARN_ON_ONCE(fault->vector != PF_VECTOR);
751 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
755 * Invalidate the TLB entry for the faulting address, if it exists,
756 * else the access will fault indefinitely (and to emulate hardware).
758 if ((fault->error_code & PFERR_PRESENT_MASK) &&
759 !(fault->error_code & PFERR_RSVD_MASK))
760 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
761 fault_mmu->root.hpa);
764 * A workaround for KVM's bad exception handling. If KVM injected an
765 * exception into L2, and L2 encountered a #PF while vectoring the
766 * injected exception, manually check to see if L1 wants to intercept
767 * #PF, otherwise queuing the #PF will lead to #DF or a lost exception.
768 * In all other cases, defer the check to nested_ops->check_events(),
769 * which will correctly handle priority (this does not). Note, other
770 * exceptions, e.g. #GP, are theoretically affected, #PF is simply the
771 * most problematic, e.g. when L0 and L1 are both intercepting #PF for
774 * TODO: Rewrite exception handling to track injected and pending
775 * (VM-Exit) exceptions separately.
777 if (unlikely(vcpu->arch.exception.injected && is_guest_mode(vcpu)) &&
778 kvm_x86_ops.nested_ops->handle_page_fault_workaround(vcpu, fault))
781 fault_mmu->inject_page_fault(vcpu, fault);
784 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
786 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
788 atomic_inc(&vcpu->arch.nmi_queued);
789 kvm_make_request(KVM_REQ_NMI, vcpu);
791 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
793 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
795 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
797 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
799 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
801 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
803 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
806 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
807 * a #GP and return false.
809 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
811 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
813 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
816 EXPORT_SYMBOL_GPL(kvm_require_cpl);
818 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
820 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
823 kvm_queue_exception(vcpu, UD_VECTOR);
826 EXPORT_SYMBOL_GPL(kvm_require_dr);
828 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
830 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
834 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
836 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
838 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
839 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
843 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
846 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
849 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
850 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
851 if (real_gpa == INVALID_GPA)
854 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
855 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
856 cr3 & GENMASK(11, 5), sizeof(pdpte));
860 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
861 if ((pdpte[i] & PT_PRESENT_MASK) &&
862 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
868 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
869 * Shadow page roots need to be reconstructed instead.
871 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
872 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
874 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
875 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
876 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
877 vcpu->arch.pdptrs_from_userspace = false;
881 EXPORT_SYMBOL_GPL(load_pdptrs);
883 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
885 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
886 kvm_clear_async_pf_completion_queue(vcpu);
887 kvm_async_pf_hash_reset(vcpu);
890 * Clearing CR0.PG is defined to flush the TLB from the guest's
893 if (!(cr0 & X86_CR0_PG))
894 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
897 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
898 kvm_mmu_reset_context(vcpu);
900 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
901 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
902 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
903 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
905 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
907 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
909 unsigned long old_cr0 = kvm_read_cr0(vcpu);
914 if (cr0 & 0xffffffff00000000UL)
918 cr0 &= ~CR0_RESERVED_BITS;
920 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
923 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
927 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
928 (cr0 & X86_CR0_PG)) {
933 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
938 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
939 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
940 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
943 if (!(cr0 & X86_CR0_PG) &&
944 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)))
947 static_call(kvm_x86_set_cr0)(vcpu, cr0);
949 kvm_post_set_cr0(vcpu, old_cr0, cr0);
953 EXPORT_SYMBOL_GPL(kvm_set_cr0);
955 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
957 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
959 EXPORT_SYMBOL_GPL(kvm_lmsw);
961 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
963 if (vcpu->arch.guest_state_protected)
966 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
968 if (vcpu->arch.xcr0 != host_xcr0)
969 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
971 if (vcpu->arch.xsaves_enabled &&
972 vcpu->arch.ia32_xss != host_xss)
973 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
976 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
977 if (static_cpu_has(X86_FEATURE_PKU) &&
978 vcpu->arch.pkru != vcpu->arch.host_pkru &&
979 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
980 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)))
981 write_pkru(vcpu->arch.pkru);
982 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
984 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
986 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
988 if (vcpu->arch.guest_state_protected)
991 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
992 if (static_cpu_has(X86_FEATURE_PKU) &&
993 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
994 kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) {
995 vcpu->arch.pkru = rdpkru();
996 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
997 write_pkru(vcpu->arch.host_pkru);
999 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
1001 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
1003 if (vcpu->arch.xcr0 != host_xcr0)
1004 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
1006 if (vcpu->arch.xsaves_enabled &&
1007 vcpu->arch.ia32_xss != host_xss)
1008 wrmsrl(MSR_IA32_XSS, host_xss);
1012 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
1014 #ifdef CONFIG_X86_64
1015 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1017 return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC;
1021 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1024 u64 old_xcr0 = vcpu->arch.xcr0;
1027 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1028 if (index != XCR_XFEATURE_ENABLED_MASK)
1030 if (!(xcr0 & XFEATURE_MASK_FP))
1032 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1036 * Do not allow the guest to set bits that we do not support
1037 * saving. However, xcr0 bit 0 is always set, even if the
1038 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1040 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
1041 if (xcr0 & ~valid_bits)
1044 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1045 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1048 if (xcr0 & XFEATURE_MASK_AVX512) {
1049 if (!(xcr0 & XFEATURE_MASK_YMM))
1051 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1055 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1056 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1059 vcpu->arch.xcr0 = xcr0;
1061 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1062 kvm_update_cpuid_runtime(vcpu);
1066 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1068 /* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
1069 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1070 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1071 kvm_inject_gp(vcpu, 0);
1075 return kvm_skip_emulated_instruction(vcpu);
1077 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1079 bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1081 if (cr4 & cr4_reserved_bits)
1084 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1089 EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4);
1091 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1093 return __kvm_is_valid_cr4(vcpu, cr4) &&
1094 static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1097 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1099 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1100 kvm_mmu_reset_context(vcpu);
1103 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1104 * according to the SDM; however, stale prev_roots could be reused
1105 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1106 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1107 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1111 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1112 kvm_mmu_unload(vcpu);
1115 * The TLB has to be flushed for all PCIDs if any of the following
1116 * (architecturally required) changes happen:
1117 * - CR4.PCIDE is changed from 1 to 0
1118 * - CR4.PGE is toggled
1120 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1122 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1123 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1124 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1127 * The TLB has to be flushed for the current PCID if any of the
1128 * following (architecturally required) changes happen:
1129 * - CR4.SMEP is changed from 0 to 1
1130 * - CR4.PAE is toggled
1132 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1133 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1134 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1137 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1139 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1141 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1143 if (!kvm_is_valid_cr4(vcpu, cr4))
1146 if (is_long_mode(vcpu)) {
1147 if (!(cr4 & X86_CR4_PAE))
1149 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1151 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1152 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1153 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1156 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1157 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1160 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1161 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1165 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1167 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1171 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1173 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1175 struct kvm_mmu *mmu = vcpu->arch.mmu;
1176 unsigned long roots_to_free = 0;
1180 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1181 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1182 * also via the emulator. KVM's TDP page tables are not in the scope of
1183 * the invalidation, but the guest's TLB entries need to be flushed as
1184 * the CPU may have cached entries in its TLB for the target PCID.
1186 if (unlikely(tdp_enabled)) {
1187 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1192 * If neither the current CR3 nor any of the prev_roots use the given
1193 * PCID, then nothing needs to be done here because a resync will
1194 * happen anyway before switching to any other CR3.
1196 if (kvm_get_active_pcid(vcpu) == pcid) {
1197 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1198 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1202 * If PCID is disabled, there is no need to free prev_roots even if the
1203 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1206 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
1209 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1210 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1211 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1213 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1216 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1218 bool skip_tlb_flush = false;
1219 unsigned long pcid = 0;
1220 #ifdef CONFIG_X86_64
1221 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1224 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1225 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1226 pcid = cr3 & X86_CR3_PCID_MASK;
1230 /* PDPTRs are always reloaded for PAE paging. */
1231 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1232 goto handle_tlb_flush;
1235 * Do not condition the GPA check on long mode, this helper is used to
1236 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1237 * the current vCPU mode is accurate.
1239 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1242 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1245 if (cr3 != kvm_read_cr3(vcpu))
1246 kvm_mmu_new_pgd(vcpu, cr3);
1248 vcpu->arch.cr3 = cr3;
1249 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1250 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1254 * A load of CR3 that flushes the TLB flushes only the current PCID,
1255 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1256 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1257 * and it's impossible to use a non-zero PCID when PCID is disabled,
1258 * i.e. only PCID=0 can be relevant.
1260 if (!skip_tlb_flush)
1261 kvm_invalidate_pcid(vcpu, pcid);
1265 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1267 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1269 if (cr8 & CR8_RESERVED_BITS)
1271 if (lapic_in_kernel(vcpu))
1272 kvm_lapic_set_tpr(vcpu, cr8);
1274 vcpu->arch.cr8 = cr8;
1277 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1279 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1281 if (lapic_in_kernel(vcpu))
1282 return kvm_lapic_get_cr8(vcpu);
1284 return vcpu->arch.cr8;
1286 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1288 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1292 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1293 for (i = 0; i < KVM_NR_DB_REGS; i++)
1294 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1298 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1302 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1303 dr7 = vcpu->arch.guest_debug_dr7;
1305 dr7 = vcpu->arch.dr7;
1306 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1307 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1308 if (dr7 & DR7_BP_EN_MASK)
1309 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1311 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1313 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1315 u64 fixed = DR6_FIXED_1;
1317 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1320 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1321 fixed |= DR6_BUS_LOCK;
1325 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1327 size_t size = ARRAY_SIZE(vcpu->arch.db);
1331 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1332 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1333 vcpu->arch.eff_db[dr] = val;
1337 if (!kvm_dr6_valid(val))
1339 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1343 if (!kvm_dr7_valid(val))
1345 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1346 kvm_update_dr7(vcpu);
1352 EXPORT_SYMBOL_GPL(kvm_set_dr);
1354 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1356 size_t size = ARRAY_SIZE(vcpu->arch.db);
1360 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1364 *val = vcpu->arch.dr6;
1368 *val = vcpu->arch.dr7;
1372 EXPORT_SYMBOL_GPL(kvm_get_dr);
1374 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1376 u32 ecx = kvm_rcx_read(vcpu);
1379 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1380 kvm_inject_gp(vcpu, 0);
1384 kvm_rax_write(vcpu, (u32)data);
1385 kvm_rdx_write(vcpu, data >> 32);
1386 return kvm_skip_emulated_instruction(vcpu);
1388 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1391 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1392 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1394 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1395 * extract the supported MSRs from the related const lists.
1396 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1397 * capabilities of the host cpu. This capabilities test skips MSRs that are
1398 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1399 * may depend on host virtualization features rather than host cpu features.
1402 static const u32 msrs_to_save_all[] = {
1403 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1405 #ifdef CONFIG_X86_64
1406 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1408 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1409 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1411 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1412 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1413 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1414 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1415 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1416 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1417 MSR_IA32_UMWAIT_CONTROL,
1419 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1420 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1421 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1422 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1423 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1424 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1425 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1426 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1427 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1428 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1429 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1430 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1431 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1432 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1433 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1434 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1435 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1436 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1437 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1438 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1439 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1440 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1441 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
1443 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1444 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1445 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1446 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1447 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1448 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1449 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1452 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1453 static unsigned num_msrs_to_save;
1455 static const u32 emulated_msrs_all[] = {
1456 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1457 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1458 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1459 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1460 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1461 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1462 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1464 HV_X64_MSR_VP_INDEX,
1465 HV_X64_MSR_VP_RUNTIME,
1466 HV_X64_MSR_SCONTROL,
1467 HV_X64_MSR_STIMER0_CONFIG,
1468 HV_X64_MSR_VP_ASSIST_PAGE,
1469 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1470 HV_X64_MSR_TSC_EMULATION_STATUS,
1471 HV_X64_MSR_SYNDBG_OPTIONS,
1472 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1473 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1474 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1476 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1477 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1479 MSR_IA32_TSC_ADJUST,
1480 MSR_IA32_TSC_DEADLINE,
1481 MSR_IA32_ARCH_CAPABILITIES,
1482 MSR_IA32_PERF_CAPABILITIES,
1483 MSR_IA32_MISC_ENABLE,
1484 MSR_IA32_MCG_STATUS,
1486 MSR_IA32_MCG_EXT_CTL,
1490 MSR_MISC_FEATURES_ENABLES,
1491 MSR_AMD64_VIRT_SPEC_CTRL,
1492 MSR_AMD64_TSC_RATIO,
1497 * The following list leaves out MSRs whose values are determined
1498 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1499 * We always support the "true" VMX control MSRs, even if the host
1500 * processor does not, so I am putting these registers here rather
1501 * than in msrs_to_save_all.
1504 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1505 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1506 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1507 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1509 MSR_IA32_VMX_CR0_FIXED0,
1510 MSR_IA32_VMX_CR4_FIXED0,
1511 MSR_IA32_VMX_VMCS_ENUM,
1512 MSR_IA32_VMX_PROCBASED_CTLS2,
1513 MSR_IA32_VMX_EPT_VPID_CAP,
1514 MSR_IA32_VMX_VMFUNC,
1517 MSR_KVM_POLL_CONTROL,
1520 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1521 static unsigned num_emulated_msrs;
1524 * List of msr numbers which are used to expose MSR-based features that
1525 * can be used by a hypervisor to validate requested CPU features.
1527 static const u32 msr_based_features_all[] = {
1529 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1530 MSR_IA32_VMX_PINBASED_CTLS,
1531 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1532 MSR_IA32_VMX_PROCBASED_CTLS,
1533 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1534 MSR_IA32_VMX_EXIT_CTLS,
1535 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1536 MSR_IA32_VMX_ENTRY_CTLS,
1538 MSR_IA32_VMX_CR0_FIXED0,
1539 MSR_IA32_VMX_CR0_FIXED1,
1540 MSR_IA32_VMX_CR4_FIXED0,
1541 MSR_IA32_VMX_CR4_FIXED1,
1542 MSR_IA32_VMX_VMCS_ENUM,
1543 MSR_IA32_VMX_PROCBASED_CTLS2,
1544 MSR_IA32_VMX_EPT_VPID_CAP,
1545 MSR_IA32_VMX_VMFUNC,
1549 MSR_IA32_ARCH_CAPABILITIES,
1550 MSR_IA32_PERF_CAPABILITIES,
1553 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1554 static unsigned int num_msr_based_features;
1557 * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM
1558 * does not yet virtualize. These include:
1559 * 10 - MISC_PACKAGE_CTRLS
1560 * 11 - ENERGY_FILTERING_CTL
1562 * 18 - FB_CLEAR_CTRL
1563 * 21 - XAPIC_DISABLE_STATUS
1564 * 23 - OVERCLOCKING_STATUS
1567 #define KVM_SUPPORTED_ARCH_CAP \
1568 (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \
1569 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \
1570 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \
1571 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \
1572 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO)
1574 static u64 kvm_get_arch_capabilities(void)
1578 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
1579 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1580 data &= KVM_SUPPORTED_ARCH_CAP;
1584 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1585 * the nested hypervisor runs with NX huge pages. If it is not,
1586 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1587 * L1 guests, so it need not worry about its own (L2) guests.
1589 data |= ARCH_CAP_PSCHANGE_MC_NO;
1592 * If we're doing cache flushes (either "always" or "cond")
1593 * we will do one whenever the guest does a vmlaunch/vmresume.
1594 * If an outer hypervisor is doing the cache flush for us
1595 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1596 * capability to the guest too, and if EPT is disabled we're not
1597 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1598 * require a nested hypervisor to do a flush of its own.
1600 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1601 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1603 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1604 data |= ARCH_CAP_RDCL_NO;
1605 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1606 data |= ARCH_CAP_SSB_NO;
1607 if (!boot_cpu_has_bug(X86_BUG_MDS))
1608 data |= ARCH_CAP_MDS_NO;
1610 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1612 * If RTM=0 because the kernel has disabled TSX, the host might
1613 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1614 * and therefore knows that there cannot be TAA) but keep
1615 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1616 * and we want to allow migrating those guests to tsx=off hosts.
1618 data &= ~ARCH_CAP_TAA_NO;
1619 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1620 data |= ARCH_CAP_TAA_NO;
1623 * Nothing to do here; we emulate TSX_CTRL if present on the
1624 * host so the guest can choose between disabling TSX or
1625 * using VERW to clear CPU buffers.
1632 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1634 switch (msr->index) {
1635 case MSR_IA32_ARCH_CAPABILITIES:
1636 msr->data = kvm_get_arch_capabilities();
1638 case MSR_IA32_UCODE_REV:
1639 rdmsrl_safe(msr->index, &msr->data);
1642 return static_call(kvm_x86_get_msr_feature)(msr);
1647 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1649 struct kvm_msr_entry msr;
1653 r = kvm_get_msr_feature(&msr);
1655 if (r == KVM_MSR_RET_INVALID) {
1656 /* Unconditionally clear the output for simplicity */
1658 if (kvm_msr_ignored_check(index, 0, false))
1670 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1672 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1675 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1678 if (efer & (EFER_LME | EFER_LMA) &&
1679 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1682 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1688 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1690 if (efer & efer_reserved_bits)
1693 return __kvm_valid_efer(vcpu, efer);
1695 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1697 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1699 u64 old_efer = vcpu->arch.efer;
1700 u64 efer = msr_info->data;
1703 if (efer & efer_reserved_bits)
1706 if (!msr_info->host_initiated) {
1707 if (!__kvm_valid_efer(vcpu, efer))
1710 if (is_paging(vcpu) &&
1711 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1716 efer |= vcpu->arch.efer & EFER_LMA;
1718 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1724 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1725 kvm_mmu_reset_context(vcpu);
1730 void kvm_enable_efer_bits(u64 mask)
1732 efer_reserved_bits &= ~mask;
1734 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1736 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1738 struct kvm_x86_msr_filter *msr_filter;
1739 struct msr_bitmap_range *ranges;
1740 struct kvm *kvm = vcpu->kvm;
1745 /* x2APIC MSRs do not support filtering. */
1746 if (index >= 0x800 && index <= 0x8ff)
1749 idx = srcu_read_lock(&kvm->srcu);
1751 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1757 allowed = msr_filter->default_allow;
1758 ranges = msr_filter->ranges;
1760 for (i = 0; i < msr_filter->count; i++) {
1761 u32 start = ranges[i].base;
1762 u32 end = start + ranges[i].nmsrs;
1763 u32 flags = ranges[i].flags;
1764 unsigned long *bitmap = ranges[i].bitmap;
1766 if ((index >= start) && (index < end) && (flags & type)) {
1767 allowed = !!test_bit(index - start, bitmap);
1773 srcu_read_unlock(&kvm->srcu, idx);
1777 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1780 * Write @data into the MSR specified by @index. Select MSR specific fault
1781 * checks are bypassed if @host_initiated is %true.
1782 * Returns 0 on success, non-0 otherwise.
1783 * Assumes vcpu_load() was already called.
1785 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1786 bool host_initiated)
1788 struct msr_data msr;
1793 case MSR_KERNEL_GS_BASE:
1796 if (is_noncanonical_address(data, vcpu))
1799 case MSR_IA32_SYSENTER_EIP:
1800 case MSR_IA32_SYSENTER_ESP:
1802 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1803 * non-canonical address is written on Intel but not on
1804 * AMD (which ignores the top 32-bits, because it does
1805 * not implement 64-bit SYSENTER).
1807 * 64-bit code should hence be able to write a non-canonical
1808 * value on AMD. Making the address canonical ensures that
1809 * vmentry does not fail on Intel after writing a non-canonical
1810 * value, and that something deterministic happens if the guest
1811 * invokes 64-bit SYSENTER.
1813 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1816 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1819 if (!host_initiated &&
1820 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1821 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1825 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1826 * incomplete and conflicting architectural behavior. Current
1827 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1828 * reserved and always read as zeros. Enforce Intel's reserved
1829 * bits check if and only if the guest CPU is Intel, and clear
1830 * the bits in all other cases. This ensures cross-vendor
1831 * migration will provide consistent behavior for the guest.
1833 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1842 msr.host_initiated = host_initiated;
1844 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1847 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1848 u32 index, u64 data, bool host_initiated)
1850 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1852 if (ret == KVM_MSR_RET_INVALID)
1853 if (kvm_msr_ignored_check(index, data, true))
1860 * Read the MSR specified by @index into @data. Select MSR specific fault
1861 * checks are bypassed if @host_initiated is %true.
1862 * Returns 0 on success, non-0 otherwise.
1863 * Assumes vcpu_load() was already called.
1865 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1866 bool host_initiated)
1868 struct msr_data msr;
1873 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1876 if (!host_initiated &&
1877 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1878 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1884 msr.host_initiated = host_initiated;
1886 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1892 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1893 u32 index, u64 *data, bool host_initiated)
1895 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1897 if (ret == KVM_MSR_RET_INVALID) {
1898 /* Unconditionally clear *data for simplicity */
1900 if (kvm_msr_ignored_check(index, 0, false))
1907 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1909 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1910 return KVM_MSR_RET_FILTERED;
1911 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1914 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1916 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1917 return KVM_MSR_RET_FILTERED;
1918 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1921 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1923 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1925 EXPORT_SYMBOL_GPL(kvm_get_msr);
1927 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1929 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1931 EXPORT_SYMBOL_GPL(kvm_set_msr);
1933 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1935 if (!vcpu->run->msr.error) {
1936 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1937 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1941 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
1943 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
1946 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1948 complete_userspace_rdmsr(vcpu);
1949 return complete_emulated_msr_access(vcpu);
1952 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
1954 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
1957 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
1959 complete_userspace_rdmsr(vcpu);
1960 return complete_fast_msr_access(vcpu);
1963 static u64 kvm_msr_reason(int r)
1966 case KVM_MSR_RET_INVALID:
1967 return KVM_MSR_EXIT_REASON_UNKNOWN;
1968 case KVM_MSR_RET_FILTERED:
1969 return KVM_MSR_EXIT_REASON_FILTER;
1971 return KVM_MSR_EXIT_REASON_INVAL;
1975 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1976 u32 exit_reason, u64 data,
1977 int (*completion)(struct kvm_vcpu *vcpu),
1980 u64 msr_reason = kvm_msr_reason(r);
1982 /* Check if the user wanted to know about this MSR fault */
1983 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1986 vcpu->run->exit_reason = exit_reason;
1987 vcpu->run->msr.error = 0;
1988 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1989 vcpu->run->msr.reason = msr_reason;
1990 vcpu->run->msr.index = index;
1991 vcpu->run->msr.data = data;
1992 vcpu->arch.complete_userspace_io = completion;
1997 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1999 u32 ecx = kvm_rcx_read(vcpu);
2003 r = kvm_get_msr_with_filter(vcpu, ecx, &data);
2006 trace_kvm_msr_read(ecx, data);
2008 kvm_rax_write(vcpu, data & -1u);
2009 kvm_rdx_write(vcpu, (data >> 32) & -1u);
2011 /* MSR read failed? See if we should ask user space */
2012 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
2013 complete_fast_rdmsr, r))
2015 trace_kvm_msr_read_ex(ecx);
2018 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2020 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
2022 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
2024 u32 ecx = kvm_rcx_read(vcpu);
2025 u64 data = kvm_read_edx_eax(vcpu);
2028 r = kvm_set_msr_with_filter(vcpu, ecx, data);
2031 trace_kvm_msr_write(ecx, data);
2033 /* MSR write failed? See if we should ask user space */
2034 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
2035 complete_fast_msr_access, r))
2037 /* Signal all other negative errors to userspace */
2040 trace_kvm_msr_write_ex(ecx, data);
2043 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2045 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2047 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2049 return kvm_skip_emulated_instruction(vcpu);
2051 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop);
2053 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2055 /* Treat an INVD instruction as a NOP and just skip it. */
2056 return kvm_emulate_as_nop(vcpu);
2058 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2060 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2062 kvm_queue_exception(vcpu, UD_VECTOR);
2065 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2068 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn)
2070 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) &&
2071 !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT))
2072 return kvm_handle_invalid_op(vcpu);
2074 pr_warn_once("kvm: %s instruction emulated as NOP!\n", insn);
2075 return kvm_emulate_as_nop(vcpu);
2077 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2079 return kvm_emulate_monitor_mwait(vcpu, "MWAIT");
2081 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2083 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2085 return kvm_emulate_monitor_mwait(vcpu, "MONITOR");
2087 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2089 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2091 xfer_to_guest_mode_prepare();
2092 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2093 xfer_to_guest_mode_work_pending();
2097 * The fast path for frequent and performance sensitive wrmsr emulation,
2098 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2099 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2100 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2101 * other cases which must be called after interrupts are enabled on the host.
2103 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2105 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2108 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2109 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2110 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2111 ((u32)(data >> 32) != X2APIC_BROADCAST))
2112 return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2117 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2119 if (!kvm_can_use_hv_timer(vcpu))
2122 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2126 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2128 u32 msr = kvm_rcx_read(vcpu);
2130 fastpath_t ret = EXIT_FASTPATH_NONE;
2133 case APIC_BASE_MSR + (APIC_ICR >> 4):
2134 data = kvm_read_edx_eax(vcpu);
2135 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2136 kvm_skip_emulated_instruction(vcpu);
2137 ret = EXIT_FASTPATH_EXIT_HANDLED;
2140 case MSR_IA32_TSC_DEADLINE:
2141 data = kvm_read_edx_eax(vcpu);
2142 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2143 kvm_skip_emulated_instruction(vcpu);
2144 ret = EXIT_FASTPATH_REENTER_GUEST;
2151 if (ret != EXIT_FASTPATH_NONE)
2152 trace_kvm_msr_write(msr, data);
2156 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2159 * Adapt set_msr() to msr_io()'s calling convention
2161 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2163 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2166 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2168 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2171 #ifdef CONFIG_X86_64
2172 struct pvclock_clock {
2182 struct pvclock_gtod_data {
2185 struct pvclock_clock clock; /* extract of a clocksource struct */
2186 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2192 static struct pvclock_gtod_data pvclock_gtod_data;
2194 static void update_pvclock_gtod(struct timekeeper *tk)
2196 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2198 write_seqcount_begin(&vdata->seq);
2200 /* copy pvclock gtod data */
2201 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2202 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2203 vdata->clock.mask = tk->tkr_mono.mask;
2204 vdata->clock.mult = tk->tkr_mono.mult;
2205 vdata->clock.shift = tk->tkr_mono.shift;
2206 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2207 vdata->clock.offset = tk->tkr_mono.base;
2209 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2210 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2211 vdata->raw_clock.mask = tk->tkr_raw.mask;
2212 vdata->raw_clock.mult = tk->tkr_raw.mult;
2213 vdata->raw_clock.shift = tk->tkr_raw.shift;
2214 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2215 vdata->raw_clock.offset = tk->tkr_raw.base;
2217 vdata->wall_time_sec = tk->xtime_sec;
2219 vdata->offs_boot = tk->offs_boot;
2221 write_seqcount_end(&vdata->seq);
2224 static s64 get_kvmclock_base_ns(void)
2226 /* Count up from boot time, but with the frequency of the raw clock. */
2227 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2230 static s64 get_kvmclock_base_ns(void)
2232 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2233 return ktime_get_boottime_ns();
2237 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2241 struct pvclock_wall_clock wc;
2248 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2253 ++version; /* first time write, random junk */
2257 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2261 * The guest calculates current wall clock time by adding
2262 * system time (updated by kvm_guest_time_update below) to the
2263 * wall clock specified here. We do the reverse here.
2265 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
2267 wc.nsec = do_div(wall_nsec, 1000000000);
2268 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2269 wc.version = version;
2271 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2274 wc_sec_hi = wall_nsec >> 32;
2275 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2276 &wc_sec_hi, sizeof(wc_sec_hi));
2280 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2283 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2284 bool old_msr, bool host_initiated)
2286 struct kvm_arch *ka = &vcpu->kvm->arch;
2288 if (vcpu->vcpu_id == 0 && !host_initiated) {
2289 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2290 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2292 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2295 vcpu->arch.time = system_time;
2296 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2298 /* we verify if the enable bit is set... */
2299 if (system_time & 1) {
2300 kvm_gfn_to_pfn_cache_init(vcpu->kvm, &vcpu->arch.pv_time, vcpu,
2301 KVM_HOST_USES_PFN, system_time & ~1ULL,
2302 sizeof(struct pvclock_vcpu_time_info));
2304 kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time);
2310 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2312 do_shl32_div32(dividend, divisor);
2316 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2317 s8 *pshift, u32 *pmultiplier)
2325 scaled64 = scaled_hz;
2326 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2331 tps32 = (uint32_t)tps64;
2332 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2333 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2341 *pmultiplier = div_frac(scaled64, tps32);
2344 #ifdef CONFIG_X86_64
2345 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2348 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2349 static unsigned long max_tsc_khz;
2351 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2353 u64 v = (u64)khz * (1000000 + ppm);
2358 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2360 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2364 /* Guest TSC same frequency as host TSC? */
2366 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2370 /* TSC scaling supported? */
2371 if (!kvm_caps.has_tsc_control) {
2372 if (user_tsc_khz > tsc_khz) {
2373 vcpu->arch.tsc_catchup = 1;
2374 vcpu->arch.tsc_always_catchup = 1;
2377 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2382 /* TSC scaling required - calculate ratio */
2383 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,
2384 user_tsc_khz, tsc_khz);
2386 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) {
2387 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2392 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2396 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2398 u32 thresh_lo, thresh_hi;
2399 int use_scaling = 0;
2401 /* tsc_khz can be zero if TSC calibration fails */
2402 if (user_tsc_khz == 0) {
2403 /* set tsc_scaling_ratio to a safe value */
2404 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2408 /* Compute a scale to convert nanoseconds in TSC cycles */
2409 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2410 &vcpu->arch.virtual_tsc_shift,
2411 &vcpu->arch.virtual_tsc_mult);
2412 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2415 * Compute the variation in TSC rate which is acceptable
2416 * within the range of tolerance and decide if the
2417 * rate being applied is within that bounds of the hardware
2418 * rate. If so, no scaling or compensation need be done.
2420 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2421 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2422 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2423 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2426 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2429 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2431 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2432 vcpu->arch.virtual_tsc_mult,
2433 vcpu->arch.virtual_tsc_shift);
2434 tsc += vcpu->arch.this_tsc_write;
2438 #ifdef CONFIG_X86_64
2439 static inline int gtod_is_based_on_tsc(int mode)
2441 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2445 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2447 #ifdef CONFIG_X86_64
2449 struct kvm_arch *ka = &vcpu->kvm->arch;
2450 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2452 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2453 atomic_read(&vcpu->kvm->online_vcpus));
2456 * Once the masterclock is enabled, always perform request in
2457 * order to update it.
2459 * In order to enable masterclock, the host clocksource must be TSC
2460 * and the vcpus need to have matched TSCs. When that happens,
2461 * perform request to enable masterclock.
2463 if (ka->use_master_clock ||
2464 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2465 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2467 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2468 atomic_read(&vcpu->kvm->online_vcpus),
2469 ka->use_master_clock, gtod->clock.vclock_mode);
2474 * Multiply tsc by a fixed point number represented by ratio.
2476 * The most significant 64-N bits (mult) of ratio represent the
2477 * integral part of the fixed point number; the remaining N bits
2478 * (frac) represent the fractional part, ie. ratio represents a fixed
2479 * point number (mult + frac * 2^(-N)).
2481 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
2483 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2485 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
2488 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2492 if (ratio != kvm_caps.default_tsc_scaling_ratio)
2493 _tsc = __scale_tsc(ratio, tsc);
2497 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2499 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2503 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2505 return target_tsc - tsc;
2508 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2510 return vcpu->arch.l1_tsc_offset +
2511 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2513 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2515 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2519 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio)
2520 nested_offset = l1_offset;
2522 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2523 kvm_caps.tsc_scaling_ratio_frac_bits);
2525 nested_offset += l2_offset;
2526 return nested_offset;
2528 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2530 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2532 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
2533 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2534 kvm_caps.tsc_scaling_ratio_frac_bits);
2536 return l1_multiplier;
2538 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2540 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2542 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2543 vcpu->arch.l1_tsc_offset,
2546 vcpu->arch.l1_tsc_offset = l1_offset;
2549 * If we are here because L1 chose not to trap WRMSR to TSC then
2550 * according to the spec this should set L1's TSC (as opposed to
2551 * setting L1's offset for L2).
2553 if (is_guest_mode(vcpu))
2554 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2556 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2557 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2559 vcpu->arch.tsc_offset = l1_offset;
2561 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset);
2564 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2566 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2568 /* Userspace is changing the multiplier while L2 is active */
2569 if (is_guest_mode(vcpu))
2570 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2572 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2574 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2576 if (kvm_caps.has_tsc_control)
2577 static_call(kvm_x86_write_tsc_multiplier)(
2578 vcpu, vcpu->arch.tsc_scaling_ratio);
2581 static inline bool kvm_check_tsc_unstable(void)
2583 #ifdef CONFIG_X86_64
2585 * TSC is marked unstable when we're running on Hyper-V,
2586 * 'TSC page' clocksource is good.
2588 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2591 return check_tsc_unstable();
2595 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2596 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2599 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2600 u64 ns, bool matched)
2602 struct kvm *kvm = vcpu->kvm;
2604 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2607 * We also track th most recent recorded KHZ, write and time to
2608 * allow the matching interval to be extended at each write.
2610 kvm->arch.last_tsc_nsec = ns;
2611 kvm->arch.last_tsc_write = tsc;
2612 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2613 kvm->arch.last_tsc_offset = offset;
2615 vcpu->arch.last_guest_tsc = tsc;
2617 kvm_vcpu_write_tsc_offset(vcpu, offset);
2621 * We split periods of matched TSC writes into generations.
2622 * For each generation, we track the original measured
2623 * nanosecond time, offset, and write, so if TSCs are in
2624 * sync, we can match exact offset, and if not, we can match
2625 * exact software computation in compute_guest_tsc()
2627 * These values are tracked in kvm->arch.cur_xxx variables.
2629 kvm->arch.cur_tsc_generation++;
2630 kvm->arch.cur_tsc_nsec = ns;
2631 kvm->arch.cur_tsc_write = tsc;
2632 kvm->arch.cur_tsc_offset = offset;
2633 kvm->arch.nr_vcpus_matched_tsc = 0;
2634 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2635 kvm->arch.nr_vcpus_matched_tsc++;
2638 /* Keep track of which generation this VCPU has synchronized to */
2639 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2640 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2641 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2643 kvm_track_tsc_matching(vcpu);
2646 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2648 struct kvm *kvm = vcpu->kvm;
2649 u64 offset, ns, elapsed;
2650 unsigned long flags;
2651 bool matched = false;
2652 bool synchronizing = false;
2654 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2655 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2656 ns = get_kvmclock_base_ns();
2657 elapsed = ns - kvm->arch.last_tsc_nsec;
2659 if (vcpu->arch.virtual_tsc_khz) {
2662 * detection of vcpu initialization -- need to sync
2663 * with other vCPUs. This particularly helps to keep
2664 * kvm_clock stable after CPU hotplug
2666 synchronizing = true;
2668 u64 tsc_exp = kvm->arch.last_tsc_write +
2669 nsec_to_cycles(vcpu, elapsed);
2670 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2672 * Special case: TSC write with a small delta (1 second)
2673 * of virtual cycle time against real time is
2674 * interpreted as an attempt to synchronize the CPU.
2676 synchronizing = data < tsc_exp + tsc_hz &&
2677 data + tsc_hz > tsc_exp;
2682 * For a reliable TSC, we can match TSC offsets, and for an unstable
2683 * TSC, we add elapsed time in this computation. We could let the
2684 * compensation code attempt to catch up if we fall behind, but
2685 * it's better to try to match offsets from the beginning.
2687 if (synchronizing &&
2688 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2689 if (!kvm_check_tsc_unstable()) {
2690 offset = kvm->arch.cur_tsc_offset;
2692 u64 delta = nsec_to_cycles(vcpu, elapsed);
2694 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2699 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2700 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2703 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2706 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2707 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2710 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2712 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
2713 WARN_ON(adjustment < 0);
2714 adjustment = kvm_scale_tsc((u64) adjustment,
2715 vcpu->arch.l1_tsc_scaling_ratio);
2716 adjust_tsc_offset_guest(vcpu, adjustment);
2719 #ifdef CONFIG_X86_64
2721 static u64 read_tsc(void)
2723 u64 ret = (u64)rdtsc_ordered();
2724 u64 last = pvclock_gtod_data.clock.cycle_last;
2726 if (likely(ret >= last))
2730 * GCC likes to generate cmov here, but this branch is extremely
2731 * predictable (it's just a function of time and the likely is
2732 * very likely) and there's a data dependence, so force GCC
2733 * to generate a branch instead. I don't barrier() because
2734 * we don't actually need a barrier, and if this function
2735 * ever gets inlined it will generate worse code.
2741 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2747 switch (clock->vclock_mode) {
2748 case VDSO_CLOCKMODE_HVCLOCK:
2749 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2751 if (tsc_pg_val != U64_MAX) {
2752 /* TSC page valid */
2753 *mode = VDSO_CLOCKMODE_HVCLOCK;
2754 v = (tsc_pg_val - clock->cycle_last) &
2757 /* TSC page invalid */
2758 *mode = VDSO_CLOCKMODE_NONE;
2761 case VDSO_CLOCKMODE_TSC:
2762 *mode = VDSO_CLOCKMODE_TSC;
2763 *tsc_timestamp = read_tsc();
2764 v = (*tsc_timestamp - clock->cycle_last) &
2768 *mode = VDSO_CLOCKMODE_NONE;
2771 if (*mode == VDSO_CLOCKMODE_NONE)
2772 *tsc_timestamp = v = 0;
2774 return v * clock->mult;
2777 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2779 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2785 seq = read_seqcount_begin(>od->seq);
2786 ns = gtod->raw_clock.base_cycles;
2787 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2788 ns >>= gtod->raw_clock.shift;
2789 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2790 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2796 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2798 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2804 seq = read_seqcount_begin(>od->seq);
2805 ts->tv_sec = gtod->wall_time_sec;
2806 ns = gtod->clock.base_cycles;
2807 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2808 ns >>= gtod->clock.shift;
2809 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2811 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2817 /* returns true if host is using TSC based clocksource */
2818 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2820 /* checked again under seqlock below */
2821 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2824 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2828 /* returns true if host is using TSC based clocksource */
2829 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2832 /* checked again under seqlock below */
2833 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2836 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2842 * Assuming a stable TSC across physical CPUS, and a stable TSC
2843 * across virtual CPUs, the following condition is possible.
2844 * Each numbered line represents an event visible to both
2845 * CPUs at the next numbered event.
2847 * "timespecX" represents host monotonic time. "tscX" represents
2850 * VCPU0 on CPU0 | VCPU1 on CPU1
2852 * 1. read timespec0,tsc0
2853 * 2. | timespec1 = timespec0 + N
2855 * 3. transition to guest | transition to guest
2856 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2857 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2858 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2860 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2863 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2865 * - 0 < N - M => M < N
2867 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2868 * always the case (the difference between two distinct xtime instances
2869 * might be smaller then the difference between corresponding TSC reads,
2870 * when updating guest vcpus pvclock areas).
2872 * To avoid that problem, do not allow visibility of distinct
2873 * system_timestamp/tsc_timestamp values simultaneously: use a master
2874 * copy of host monotonic time values. Update that master copy
2877 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2881 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2883 #ifdef CONFIG_X86_64
2884 struct kvm_arch *ka = &kvm->arch;
2886 bool host_tsc_clocksource, vcpus_matched;
2888 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2889 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2890 atomic_read(&kvm->online_vcpus));
2893 * If the host uses TSC clock, then passthrough TSC as stable
2896 host_tsc_clocksource = kvm_get_time_and_clockread(
2897 &ka->master_kernel_ns,
2898 &ka->master_cycle_now);
2900 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2901 && !ka->backwards_tsc_observed
2902 && !ka->boot_vcpu_runs_old_kvmclock;
2904 if (ka->use_master_clock)
2905 atomic_set(&kvm_guest_has_master_clock, 1);
2907 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2908 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2913 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2915 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2918 static void __kvm_start_pvclock_update(struct kvm *kvm)
2920 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
2921 write_seqcount_begin(&kvm->arch.pvclock_sc);
2924 static void kvm_start_pvclock_update(struct kvm *kvm)
2926 kvm_make_mclock_inprogress_request(kvm);
2928 /* no guest entries from this point */
2929 __kvm_start_pvclock_update(kvm);
2932 static void kvm_end_pvclock_update(struct kvm *kvm)
2934 struct kvm_arch *ka = &kvm->arch;
2935 struct kvm_vcpu *vcpu;
2938 write_seqcount_end(&ka->pvclock_sc);
2939 raw_spin_unlock_irq(&ka->tsc_write_lock);
2940 kvm_for_each_vcpu(i, vcpu, kvm)
2941 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2943 /* guest entries allowed */
2944 kvm_for_each_vcpu(i, vcpu, kvm)
2945 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2948 static void kvm_update_masterclock(struct kvm *kvm)
2950 kvm_hv_request_tsc_page_update(kvm);
2951 kvm_start_pvclock_update(kvm);
2952 pvclock_update_vm_gtod_copy(kvm);
2953 kvm_end_pvclock_update(kvm);
2956 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
2957 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2959 struct kvm_arch *ka = &kvm->arch;
2960 struct pvclock_vcpu_time_info hv_clock;
2962 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2966 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) {
2967 #ifdef CONFIG_X86_64
2968 struct timespec64 ts;
2970 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
2971 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
2972 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
2975 data->host_tsc = rdtsc();
2977 data->flags |= KVM_CLOCK_TSC_STABLE;
2978 hv_clock.tsc_timestamp = ka->master_cycle_now;
2979 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2980 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2981 &hv_clock.tsc_shift,
2982 &hv_clock.tsc_to_system_mul);
2983 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
2985 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
2991 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2993 struct kvm_arch *ka = &kvm->arch;
2997 seq = read_seqcount_begin(&ka->pvclock_sc);
2998 __get_kvmclock(kvm, data);
2999 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3002 u64 get_kvmclock_ns(struct kvm *kvm)
3004 struct kvm_clock_data data;
3006 get_kvmclock(kvm, &data);
3010 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v,
3011 struct gfn_to_pfn_cache *gpc,
3012 unsigned int offset)
3014 struct kvm_vcpu_arch *vcpu = &v->arch;
3015 struct pvclock_vcpu_time_info *guest_hv_clock;
3016 unsigned long flags;
3018 read_lock_irqsave(&gpc->lock, flags);
3019 while (!kvm_gfn_to_pfn_cache_check(v->kvm, gpc, gpc->gpa,
3020 offset + sizeof(*guest_hv_clock))) {
3021 read_unlock_irqrestore(&gpc->lock, flags);
3023 if (kvm_gfn_to_pfn_cache_refresh(v->kvm, gpc, gpc->gpa,
3024 offset + sizeof(*guest_hv_clock)))
3027 read_lock_irqsave(&gpc->lock, flags);
3030 guest_hv_clock = (void *)(gpc->khva + offset);
3033 * This VCPU is paused, but it's legal for a guest to read another
3034 * VCPU's kvmclock, so we really have to follow the specification where
3035 * it says that version is odd if data is being modified, and even after
3039 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1;
3042 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3043 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
3045 if (vcpu->pvclock_set_guest_stopped_request) {
3046 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3047 vcpu->pvclock_set_guest_stopped_request = false;
3050 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock));
3053 guest_hv_clock->version = ++vcpu->hv_clock.version;
3055 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT);
3056 read_unlock_irqrestore(&gpc->lock, flags);
3058 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3061 static int kvm_guest_time_update(struct kvm_vcpu *v)
3063 unsigned long flags, tgt_tsc_khz;
3065 struct kvm_vcpu_arch *vcpu = &v->arch;
3066 struct kvm_arch *ka = &v->kvm->arch;
3068 u64 tsc_timestamp, host_tsc;
3070 bool use_master_clock;
3076 * If the host uses TSC clock, then passthrough TSC as stable
3080 seq = read_seqcount_begin(&ka->pvclock_sc);
3081 use_master_clock = ka->use_master_clock;
3082 if (use_master_clock) {
3083 host_tsc = ka->master_cycle_now;
3084 kernel_ns = ka->master_kernel_ns;
3086 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3088 /* Keep irq disabled to prevent changes to the clock */
3089 local_irq_save(flags);
3090 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
3091 if (unlikely(tgt_tsc_khz == 0)) {
3092 local_irq_restore(flags);
3093 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3096 if (!use_master_clock) {
3098 kernel_ns = get_kvmclock_base_ns();
3101 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3104 * We may have to catch up the TSC to match elapsed wall clock
3105 * time for two reasons, even if kvmclock is used.
3106 * 1) CPU could have been running below the maximum TSC rate
3107 * 2) Broken TSC compensation resets the base at each VCPU
3108 * entry to avoid unknown leaps of TSC even when running
3109 * again on the same CPU. This may cause apparent elapsed
3110 * time to disappear, and the guest to stand still or run
3113 if (vcpu->tsc_catchup) {
3114 u64 tsc = compute_guest_tsc(v, kernel_ns);
3115 if (tsc > tsc_timestamp) {
3116 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3117 tsc_timestamp = tsc;
3121 local_irq_restore(flags);
3123 /* With all the info we got, fill in the values */
3125 if (kvm_caps.has_tsc_control)
3126 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3127 v->arch.l1_tsc_scaling_ratio);
3129 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3130 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3131 &vcpu->hv_clock.tsc_shift,
3132 &vcpu->hv_clock.tsc_to_system_mul);
3133 vcpu->hw_tsc_khz = tgt_tsc_khz;
3136 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3137 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3138 vcpu->last_guest_tsc = tsc_timestamp;
3140 /* If the host uses TSC clocksource, then it is stable */
3142 if (use_master_clock)
3143 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3145 vcpu->hv_clock.flags = pvclock_flags;
3147 if (vcpu->pv_time.active)
3148 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0);
3149 if (vcpu->xen.vcpu_info_cache.active)
3150 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache,
3151 offsetof(struct compat_vcpu_info, time));
3152 if (vcpu->xen.vcpu_time_info_cache.active)
3153 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0);
3154 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3159 * kvmclock updates which are isolated to a given vcpu, such as
3160 * vcpu->cpu migration, should not allow system_timestamp from
3161 * the rest of the vcpus to remain static. Otherwise ntp frequency
3162 * correction applies to one vcpu's system_timestamp but not
3165 * So in those cases, request a kvmclock update for all vcpus.
3166 * We need to rate-limit these requests though, as they can
3167 * considerably slow guests that have a large number of vcpus.
3168 * The time for a remote vcpu to update its kvmclock is bound
3169 * by the delay we use to rate-limit the updates.
3172 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3174 static void kvmclock_update_fn(struct work_struct *work)
3177 struct delayed_work *dwork = to_delayed_work(work);
3178 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3179 kvmclock_update_work);
3180 struct kvm *kvm = container_of(ka, struct kvm, arch);
3181 struct kvm_vcpu *vcpu;
3183 kvm_for_each_vcpu(i, vcpu, kvm) {
3184 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3185 kvm_vcpu_kick(vcpu);
3189 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3191 struct kvm *kvm = v->kvm;
3193 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3194 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3195 KVMCLOCK_UPDATE_DELAY);
3198 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3200 static void kvmclock_sync_fn(struct work_struct *work)
3202 struct delayed_work *dwork = to_delayed_work(work);
3203 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3204 kvmclock_sync_work);
3205 struct kvm *kvm = container_of(ka, struct kvm, arch);
3207 if (!kvmclock_periodic_sync)
3210 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3211 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3212 KVMCLOCK_SYNC_PERIOD);
3215 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */
3216 static bool is_mci_control_msr(u32 msr)
3218 return (msr & 3) == 0;
3220 static bool is_mci_status_msr(u32 msr)
3222 return (msr & 3) == 1;
3226 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3228 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3230 /* McStatusWrEn enabled? */
3231 if (guest_cpuid_is_amd_or_hygon(vcpu))
3232 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3237 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3239 u64 mcg_cap = vcpu->arch.mcg_cap;
3240 unsigned bank_num = mcg_cap & 0xff;
3241 u32 msr = msr_info->index;
3242 u64 data = msr_info->data;
3243 u32 offset, last_msr;
3246 case MSR_IA32_MCG_STATUS:
3247 vcpu->arch.mcg_status = data;
3249 case MSR_IA32_MCG_CTL:
3250 if (!(mcg_cap & MCG_CTL_P) &&
3251 (data || !msr_info->host_initiated))
3253 if (data != 0 && data != ~(u64)0)
3255 vcpu->arch.mcg_ctl = data;
3257 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3258 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3262 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
3264 /* An attempt to write a 1 to a reserved bit raises #GP */
3265 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
3267 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3268 last_msr + 1 - MSR_IA32_MC0_CTL2);
3269 vcpu->arch.mci_ctl2_banks[offset] = data;
3271 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3272 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3277 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other
3278 * values are architecturally undefined. But, some Linux
3279 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
3280 * issue on AMD K8s, allow bit 10 to be clear when setting all
3281 * other bits in order to avoid an uncaught #GP in the guest.
3283 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable,
3284 * single-bit ECC data errors.
3286 if (is_mci_control_msr(msr) &&
3287 data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
3291 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR.
3292 * AMD-based CPUs allow non-zero values, but if and only if
3293 * HWCR[McStatusWrEn] is set.
3295 if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
3296 data != 0 && !can_set_mci_status(vcpu))
3299 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3300 last_msr + 1 - MSR_IA32_MC0_CTL);
3301 vcpu->arch.mce_banks[offset] = data;
3309 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3311 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3313 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3316 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3318 gpa_t gpa = data & ~0x3f;
3320 /* Bits 4:5 are reserved, Should be zero */
3324 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3325 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3328 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3329 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3332 if (!lapic_in_kernel(vcpu))
3333 return data ? 1 : 0;
3335 vcpu->arch.apf.msr_en_val = data;
3337 if (!kvm_pv_async_pf_enabled(vcpu)) {
3338 kvm_clear_async_pf_completion_queue(vcpu);
3339 kvm_async_pf_hash_reset(vcpu);
3343 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3347 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3348 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3350 kvm_async_pf_wakeup_all(vcpu);
3355 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3357 /* Bits 8-63 are reserved */
3361 if (!lapic_in_kernel(vcpu))
3364 vcpu->arch.apf.msr_int_val = data;
3366 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3371 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3373 kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time);
3374 vcpu->arch.time = 0;
3377 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3379 ++vcpu->stat.tlb_flush;
3380 static_call(kvm_x86_flush_tlb_all)(vcpu);
3383 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3385 ++vcpu->stat.tlb_flush;
3389 * A TLB flush on behalf of the guest is equivalent to
3390 * INVPCID(all), toggling CR4.PGE, etc., which requires
3391 * a forced sync of the shadow page tables. Ensure all the
3392 * roots are synced and the guest TLB in hardware is clean.
3394 kvm_mmu_sync_roots(vcpu);
3395 kvm_mmu_sync_prev_roots(vcpu);
3398 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3402 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3404 ++vcpu->stat.tlb_flush;
3405 static_call(kvm_x86_flush_tlb_current)(vcpu);
3409 * Service "local" TLB flush requests, which are specific to the current MMU
3410 * context. In addition to the generic event handling in vcpu_enter_guest(),
3411 * TLB flushes that are targeted at an MMU context also need to be serviced
3412 * prior before nested VM-Enter/VM-Exit.
3414 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3416 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3417 kvm_vcpu_flush_tlb_current(vcpu);
3419 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3420 kvm_vcpu_flush_tlb_guest(vcpu);
3422 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3424 static void record_steal_time(struct kvm_vcpu *vcpu)
3426 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3427 struct kvm_steal_time __user *st;
3428 struct kvm_memslots *slots;
3429 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3433 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3434 kvm_xen_runstate_set_running(vcpu);
3438 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3441 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3444 slots = kvm_memslots(vcpu->kvm);
3446 if (unlikely(slots->generation != ghc->generation ||
3448 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3449 /* We rely on the fact that it fits in a single page. */
3450 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3452 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) ||
3453 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3457 st = (struct kvm_steal_time __user *)ghc->hva;
3459 * Doing a TLB flush here, on the guest's behalf, can avoid
3462 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3463 u8 st_preempted = 0;
3466 if (!user_access_begin(st, sizeof(*st)))
3469 asm volatile("1: xchgb %0, %2\n"
3472 _ASM_EXTABLE_UA(1b, 2b)
3473 : "+q" (st_preempted),
3475 "+m" (st->preempted));
3481 vcpu->arch.st.preempted = 0;
3483 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3484 st_preempted & KVM_VCPU_FLUSH_TLB);
3485 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3486 kvm_vcpu_flush_tlb_guest(vcpu);
3488 if (!user_access_begin(st, sizeof(*st)))
3491 if (!user_access_begin(st, sizeof(*st)))
3494 unsafe_put_user(0, &st->preempted, out);
3495 vcpu->arch.st.preempted = 0;
3498 unsafe_get_user(version, &st->version, out);
3500 version += 1; /* first time write, random junk */
3503 unsafe_put_user(version, &st->version, out);
3507 unsafe_get_user(steal, &st->steal, out);
3508 steal += current->sched_info.run_delay -
3509 vcpu->arch.st.last_steal;
3510 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3511 unsafe_put_user(steal, &st->steal, out);
3514 unsafe_put_user(version, &st->version, out);
3519 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3522 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3525 u32 msr = msr_info->index;
3526 u64 data = msr_info->data;
3528 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3529 return kvm_xen_write_hypercall_page(vcpu, data);
3532 case MSR_AMD64_NB_CFG:
3533 case MSR_IA32_UCODE_WRITE:
3534 case MSR_VM_HSAVE_PA:
3535 case MSR_AMD64_PATCH_LOADER:
3536 case MSR_AMD64_BU_CFG2:
3537 case MSR_AMD64_DC_CFG:
3538 case MSR_F15H_EX_CFG:
3541 case MSR_IA32_UCODE_REV:
3542 if (msr_info->host_initiated)
3543 vcpu->arch.microcode_version = data;
3545 case MSR_IA32_ARCH_CAPABILITIES:
3546 if (!msr_info->host_initiated)
3548 vcpu->arch.arch_capabilities = data;
3550 case MSR_IA32_PERF_CAPABILITIES: {
3551 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3553 if (!msr_info->host_initiated)
3555 if (kvm_get_msr_feature(&msr_ent))
3557 if (data & ~msr_ent.data)
3560 vcpu->arch.perf_capabilities = data;
3561 kvm_pmu_refresh(vcpu);
3565 return set_efer(vcpu, msr_info);
3567 data &= ~(u64)0x40; /* ignore flush filter disable */
3568 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3569 data &= ~(u64)0x8; /* ignore TLB cache disable */
3571 /* Handle McStatusWrEn */
3572 if (data == BIT_ULL(18)) {
3573 vcpu->arch.msr_hwcr = data;
3574 } else if (data != 0) {
3575 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3580 case MSR_FAM10H_MMIO_CONF_BASE:
3582 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3587 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
3588 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
3589 return kvm_mtrr_set_msr(vcpu, msr, data);
3590 case MSR_IA32_APICBASE:
3591 return kvm_set_apic_base(vcpu, msr_info);
3592 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3593 return kvm_x2apic_msr_write(vcpu, msr, data);
3594 case MSR_IA32_TSC_DEADLINE:
3595 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3597 case MSR_IA32_TSC_ADJUST:
3598 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3599 if (!msr_info->host_initiated) {
3600 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3601 adjust_tsc_offset_guest(vcpu, adj);
3602 /* Before back to guest, tsc_timestamp must be adjusted
3603 * as well, otherwise guest's percpu pvclock time could jump.
3605 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3607 vcpu->arch.ia32_tsc_adjust_msr = data;
3610 case MSR_IA32_MISC_ENABLE: {
3611 u64 old_val = vcpu->arch.ia32_misc_enable_msr;
3613 if (!msr_info->host_initiated) {
3615 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK)
3618 /* R bits, i.e. writes are ignored, but don't fault. */
3619 data = data & ~MSR_IA32_MISC_ENABLE_EMON;
3620 data |= old_val & MSR_IA32_MISC_ENABLE_EMON;
3623 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3624 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3625 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3627 vcpu->arch.ia32_misc_enable_msr = data;
3628 kvm_update_cpuid_runtime(vcpu);
3630 vcpu->arch.ia32_misc_enable_msr = data;
3634 case MSR_IA32_SMBASE:
3635 if (!msr_info->host_initiated)
3637 vcpu->arch.smbase = data;
3639 case MSR_IA32_POWER_CTL:
3640 vcpu->arch.msr_ia32_power_ctl = data;
3643 if (msr_info->host_initiated) {
3644 kvm_synchronize_tsc(vcpu, data);
3646 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3647 adjust_tsc_offset_guest(vcpu, adj);
3648 vcpu->arch.ia32_tsc_adjust_msr += adj;
3652 if (!msr_info->host_initiated &&
3653 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3656 * KVM supports exposing PT to the guest, but does not support
3657 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3658 * XSAVES/XRSTORS to save/restore PT MSRs.
3660 if (data & ~kvm_caps.supported_xss)
3662 vcpu->arch.ia32_xss = data;
3663 kvm_update_cpuid_runtime(vcpu);
3666 if (!msr_info->host_initiated)
3668 vcpu->arch.smi_count = data;
3670 case MSR_KVM_WALL_CLOCK_NEW:
3671 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3674 vcpu->kvm->arch.wall_clock = data;
3675 kvm_write_wall_clock(vcpu->kvm, data, 0);
3677 case MSR_KVM_WALL_CLOCK:
3678 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3681 vcpu->kvm->arch.wall_clock = data;
3682 kvm_write_wall_clock(vcpu->kvm, data, 0);
3684 case MSR_KVM_SYSTEM_TIME_NEW:
3685 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3688 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3690 case MSR_KVM_SYSTEM_TIME:
3691 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3694 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3696 case MSR_KVM_ASYNC_PF_EN:
3697 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3700 if (kvm_pv_enable_async_pf(vcpu, data))
3703 case MSR_KVM_ASYNC_PF_INT:
3704 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3707 if (kvm_pv_enable_async_pf_int(vcpu, data))
3710 case MSR_KVM_ASYNC_PF_ACK:
3711 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3714 vcpu->arch.apf.pageready_pending = false;
3715 kvm_check_async_pf_completion(vcpu);
3718 case MSR_KVM_STEAL_TIME:
3719 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3722 if (unlikely(!sched_info_on()))
3725 if (data & KVM_STEAL_RESERVED_MASK)
3728 vcpu->arch.st.msr_val = data;
3730 if (!(data & KVM_MSR_ENABLED))
3733 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3736 case MSR_KVM_PV_EOI_EN:
3737 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3740 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
3744 case MSR_KVM_POLL_CONTROL:
3745 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3748 /* only enable bit supported */
3749 if (data & (-1ULL << 1))
3752 vcpu->arch.msr_kvm_poll_control = data;
3755 case MSR_IA32_MCG_CTL:
3756 case MSR_IA32_MCG_STATUS:
3757 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3758 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3759 return set_msr_mce(vcpu, msr_info);
3761 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3762 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3765 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3766 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3767 if (kvm_pmu_is_valid_msr(vcpu, msr))
3768 return kvm_pmu_set_msr(vcpu, msr_info);
3770 if (pr || data != 0)
3771 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3772 "0x%x data 0x%llx\n", msr, data);
3774 case MSR_K7_CLK_CTL:
3776 * Ignore all writes to this no longer documented MSR.
3777 * Writes are only relevant for old K7 processors,
3778 * all pre-dating SVM, but a recommended workaround from
3779 * AMD for these chips. It is possible to specify the
3780 * affected processor models on the command line, hence
3781 * the need to ignore the workaround.
3784 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3785 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3786 case HV_X64_MSR_SYNDBG_OPTIONS:
3787 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3788 case HV_X64_MSR_CRASH_CTL:
3789 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3790 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3791 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3792 case HV_X64_MSR_TSC_EMULATION_STATUS:
3793 return kvm_hv_set_msr_common(vcpu, msr, data,
3794 msr_info->host_initiated);
3795 case MSR_IA32_BBL_CR_CTL3:
3796 /* Drop writes to this legacy MSR -- see rdmsr
3797 * counterpart for further detail.
3799 if (report_ignored_msrs)
3800 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3803 case MSR_AMD64_OSVW_ID_LENGTH:
3804 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3806 vcpu->arch.osvw.length = data;
3808 case MSR_AMD64_OSVW_STATUS:
3809 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3811 vcpu->arch.osvw.status = data;
3813 case MSR_PLATFORM_INFO:
3814 if (!msr_info->host_initiated ||
3815 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3816 cpuid_fault_enabled(vcpu)))
3818 vcpu->arch.msr_platform_info = data;
3820 case MSR_MISC_FEATURES_ENABLES:
3821 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3822 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3823 !supports_cpuid_fault(vcpu)))
3825 vcpu->arch.msr_misc_features_enables = data;
3827 #ifdef CONFIG_X86_64
3829 if (!msr_info->host_initiated &&
3830 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3833 if (data & ~kvm_guest_supported_xfd(vcpu))
3836 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
3838 case MSR_IA32_XFD_ERR:
3839 if (!msr_info->host_initiated &&
3840 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3843 if (data & ~kvm_guest_supported_xfd(vcpu))
3846 vcpu->arch.guest_fpu.xfd_err = data;
3849 case MSR_IA32_PEBS_ENABLE:
3850 case MSR_IA32_DS_AREA:
3851 case MSR_PEBS_DATA_CFG:
3852 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3853 if (kvm_pmu_is_valid_msr(vcpu, msr))
3854 return kvm_pmu_set_msr(vcpu, msr_info);
3856 * Userspace is allowed to write '0' to MSRs that KVM reports
3857 * as to-be-saved, even if an MSRs isn't fully supported.
3859 return !msr_info->host_initiated || data;
3861 if (kvm_pmu_is_valid_msr(vcpu, msr))
3862 return kvm_pmu_set_msr(vcpu, msr_info);
3863 return KVM_MSR_RET_INVALID;
3867 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3869 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3872 u64 mcg_cap = vcpu->arch.mcg_cap;
3873 unsigned bank_num = mcg_cap & 0xff;
3874 u32 offset, last_msr;
3877 case MSR_IA32_P5_MC_ADDR:
3878 case MSR_IA32_P5_MC_TYPE:
3881 case MSR_IA32_MCG_CAP:
3882 data = vcpu->arch.mcg_cap;
3884 case MSR_IA32_MCG_CTL:
3885 if (!(mcg_cap & MCG_CTL_P) && !host)
3887 data = vcpu->arch.mcg_ctl;
3889 case MSR_IA32_MCG_STATUS:
3890 data = vcpu->arch.mcg_status;
3892 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3893 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3897 if (!(mcg_cap & MCG_CMCI_P) && !host)
3899 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3900 last_msr + 1 - MSR_IA32_MC0_CTL2);
3901 data = vcpu->arch.mci_ctl2_banks[offset];
3903 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3904 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3908 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3909 last_msr + 1 - MSR_IA32_MC0_CTL);
3910 data = vcpu->arch.mce_banks[offset];
3919 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3921 switch (msr_info->index) {
3922 case MSR_IA32_PLATFORM_ID:
3923 case MSR_IA32_EBL_CR_POWERON:
3924 case MSR_IA32_LASTBRANCHFROMIP:
3925 case MSR_IA32_LASTBRANCHTOIP:
3926 case MSR_IA32_LASTINTFROMIP:
3927 case MSR_IA32_LASTINTTOIP:
3928 case MSR_AMD64_SYSCFG:
3929 case MSR_K8_TSEG_ADDR:
3930 case MSR_K8_TSEG_MASK:
3931 case MSR_VM_HSAVE_PA:
3932 case MSR_K8_INT_PENDING_MSG:
3933 case MSR_AMD64_NB_CFG:
3934 case MSR_FAM10H_MMIO_CONF_BASE:
3935 case MSR_AMD64_BU_CFG2:
3936 case MSR_IA32_PERF_CTL:
3937 case MSR_AMD64_DC_CFG:
3938 case MSR_F15H_EX_CFG:
3940 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3941 * limit) MSRs. Just return 0, as we do not want to expose the host
3942 * data here. Do not conditionalize this on CPUID, as KVM does not do
3943 * so for existing CPU-specific MSRs.
3945 case MSR_RAPL_POWER_UNIT:
3946 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3947 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3948 case MSR_PKG_ENERGY_STATUS: /* Total package */
3949 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3952 case MSR_IA32_PEBS_ENABLE:
3953 case MSR_IA32_DS_AREA:
3954 case MSR_PEBS_DATA_CFG:
3955 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3956 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3957 return kvm_pmu_get_msr(vcpu, msr_info);
3959 * Userspace is allowed to read MSRs that KVM reports as
3960 * to-be-saved, even if an MSR isn't fully supported.
3962 if (!msr_info->host_initiated)
3966 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3967 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3968 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3969 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3970 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3971 return kvm_pmu_get_msr(vcpu, msr_info);
3974 case MSR_IA32_UCODE_REV:
3975 msr_info->data = vcpu->arch.microcode_version;
3977 case MSR_IA32_ARCH_CAPABILITIES:
3978 if (!msr_info->host_initiated &&
3979 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3981 msr_info->data = vcpu->arch.arch_capabilities;
3983 case MSR_IA32_PERF_CAPABILITIES:
3984 if (!msr_info->host_initiated &&
3985 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3987 msr_info->data = vcpu->arch.perf_capabilities;
3989 case MSR_IA32_POWER_CTL:
3990 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3992 case MSR_IA32_TSC: {
3994 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3995 * even when not intercepted. AMD manual doesn't explicitly
3996 * state this but appears to behave the same.
3998 * On userspace reads and writes, however, we unconditionally
3999 * return L1's TSC value to ensure backwards-compatible
4000 * behavior for migration.
4004 if (msr_info->host_initiated) {
4005 offset = vcpu->arch.l1_tsc_offset;
4006 ratio = vcpu->arch.l1_tsc_scaling_ratio;
4008 offset = vcpu->arch.tsc_offset;
4009 ratio = vcpu->arch.tsc_scaling_ratio;
4012 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
4016 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
4017 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
4018 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
4019 case 0xcd: /* fsb frequency */
4023 * MSR_EBC_FREQUENCY_ID
4024 * Conservative value valid for even the basic CPU models.
4025 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
4026 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
4027 * and 266MHz for model 3, or 4. Set Core Clock
4028 * Frequency to System Bus Frequency Ratio to 1 (bits
4029 * 31:24) even though these are only valid for CPU
4030 * models > 2, however guests may end up dividing or
4031 * multiplying by zero otherwise.
4033 case MSR_EBC_FREQUENCY_ID:
4034 msr_info->data = 1 << 24;
4036 case MSR_IA32_APICBASE:
4037 msr_info->data = kvm_get_apic_base(vcpu);
4039 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
4040 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
4041 case MSR_IA32_TSC_DEADLINE:
4042 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
4044 case MSR_IA32_TSC_ADJUST:
4045 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
4047 case MSR_IA32_MISC_ENABLE:
4048 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
4050 case MSR_IA32_SMBASE:
4051 if (!msr_info->host_initiated)
4053 msr_info->data = vcpu->arch.smbase;
4056 msr_info->data = vcpu->arch.smi_count;
4058 case MSR_IA32_PERF_STATUS:
4059 /* TSC increment by tick */
4060 msr_info->data = 1000ULL;
4061 /* CPU multiplier */
4062 msr_info->data |= (((uint64_t)4ULL) << 40);
4065 msr_info->data = vcpu->arch.efer;
4067 case MSR_KVM_WALL_CLOCK:
4068 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4071 msr_info->data = vcpu->kvm->arch.wall_clock;
4073 case MSR_KVM_WALL_CLOCK_NEW:
4074 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4077 msr_info->data = vcpu->kvm->arch.wall_clock;
4079 case MSR_KVM_SYSTEM_TIME:
4080 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4083 msr_info->data = vcpu->arch.time;
4085 case MSR_KVM_SYSTEM_TIME_NEW:
4086 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4089 msr_info->data = vcpu->arch.time;
4091 case MSR_KVM_ASYNC_PF_EN:
4092 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
4095 msr_info->data = vcpu->arch.apf.msr_en_val;
4097 case MSR_KVM_ASYNC_PF_INT:
4098 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4101 msr_info->data = vcpu->arch.apf.msr_int_val;
4103 case MSR_KVM_ASYNC_PF_ACK:
4104 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4109 case MSR_KVM_STEAL_TIME:
4110 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
4113 msr_info->data = vcpu->arch.st.msr_val;
4115 case MSR_KVM_PV_EOI_EN:
4116 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4119 msr_info->data = vcpu->arch.pv_eoi.msr_val;
4121 case MSR_KVM_POLL_CONTROL:
4122 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4125 msr_info->data = vcpu->arch.msr_kvm_poll_control;
4127 case MSR_IA32_P5_MC_ADDR:
4128 case MSR_IA32_P5_MC_TYPE:
4129 case MSR_IA32_MCG_CAP:
4130 case MSR_IA32_MCG_CTL:
4131 case MSR_IA32_MCG_STATUS:
4132 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4133 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4134 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4135 msr_info->host_initiated);
4137 if (!msr_info->host_initiated &&
4138 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4140 msr_info->data = vcpu->arch.ia32_xss;
4142 case MSR_K7_CLK_CTL:
4144 * Provide expected ramp-up count for K7. All other
4145 * are set to zero, indicating minimum divisors for
4148 * This prevents guest kernels on AMD host with CPU
4149 * type 6, model 8 and higher from exploding due to
4150 * the rdmsr failing.
4152 msr_info->data = 0x20000000;
4154 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4155 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4156 case HV_X64_MSR_SYNDBG_OPTIONS:
4157 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4158 case HV_X64_MSR_CRASH_CTL:
4159 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4160 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4161 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4162 case HV_X64_MSR_TSC_EMULATION_STATUS:
4163 return kvm_hv_get_msr_common(vcpu,
4164 msr_info->index, &msr_info->data,
4165 msr_info->host_initiated);
4166 case MSR_IA32_BBL_CR_CTL3:
4167 /* This legacy MSR exists but isn't fully documented in current
4168 * silicon. It is however accessed by winxp in very narrow
4169 * scenarios where it sets bit #19, itself documented as
4170 * a "reserved" bit. Best effort attempt to source coherent
4171 * read data here should the balance of the register be
4172 * interpreted by the guest:
4174 * L2 cache control register 3: 64GB range, 256KB size,
4175 * enabled, latency 0x1, configured
4177 msr_info->data = 0xbe702111;
4179 case MSR_AMD64_OSVW_ID_LENGTH:
4180 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4182 msr_info->data = vcpu->arch.osvw.length;
4184 case MSR_AMD64_OSVW_STATUS:
4185 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4187 msr_info->data = vcpu->arch.osvw.status;
4189 case MSR_PLATFORM_INFO:
4190 if (!msr_info->host_initiated &&
4191 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4193 msr_info->data = vcpu->arch.msr_platform_info;
4195 case MSR_MISC_FEATURES_ENABLES:
4196 msr_info->data = vcpu->arch.msr_misc_features_enables;
4199 msr_info->data = vcpu->arch.msr_hwcr;
4201 #ifdef CONFIG_X86_64
4203 if (!msr_info->host_initiated &&
4204 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4207 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4209 case MSR_IA32_XFD_ERR:
4210 if (!msr_info->host_initiated &&
4211 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4214 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4218 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4219 return kvm_pmu_get_msr(vcpu, msr_info);
4220 return KVM_MSR_RET_INVALID;
4224 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4227 * Read or write a bunch of msrs. All parameters are kernel addresses.
4229 * @return number of msrs set successfully.
4231 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4232 struct kvm_msr_entry *entries,
4233 int (*do_msr)(struct kvm_vcpu *vcpu,
4234 unsigned index, u64 *data))
4238 for (i = 0; i < msrs->nmsrs; ++i)
4239 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4246 * Read or write a bunch of msrs. Parameters are user addresses.
4248 * @return number of msrs set successfully.
4250 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4251 int (*do_msr)(struct kvm_vcpu *vcpu,
4252 unsigned index, u64 *data),
4255 struct kvm_msrs msrs;
4256 struct kvm_msr_entry *entries;
4261 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4265 if (msrs.nmsrs >= MAX_IO_MSRS)
4268 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4269 entries = memdup_user(user_msrs->entries, size);
4270 if (IS_ERR(entries)) {
4271 r = PTR_ERR(entries);
4275 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
4280 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4291 static inline bool kvm_can_mwait_in_guest(void)
4293 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4294 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4295 boot_cpu_has(X86_FEATURE_ARAT);
4298 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4299 struct kvm_cpuid2 __user *cpuid_arg)
4301 struct kvm_cpuid2 cpuid;
4305 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4308 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4313 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4319 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4324 case KVM_CAP_IRQCHIP:
4326 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4327 case KVM_CAP_SET_TSS_ADDR:
4328 case KVM_CAP_EXT_CPUID:
4329 case KVM_CAP_EXT_EMUL_CPUID:
4330 case KVM_CAP_CLOCKSOURCE:
4332 case KVM_CAP_NOP_IO_DELAY:
4333 case KVM_CAP_MP_STATE:
4334 case KVM_CAP_SYNC_MMU:
4335 case KVM_CAP_USER_NMI:
4336 case KVM_CAP_REINJECT_CONTROL:
4337 case KVM_CAP_IRQ_INJECT_STATUS:
4338 case KVM_CAP_IOEVENTFD:
4339 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4341 case KVM_CAP_PIT_STATE2:
4342 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4343 case KVM_CAP_VCPU_EVENTS:
4344 case KVM_CAP_HYPERV:
4345 case KVM_CAP_HYPERV_VAPIC:
4346 case KVM_CAP_HYPERV_SPIN:
4347 case KVM_CAP_HYPERV_SYNIC:
4348 case KVM_CAP_HYPERV_SYNIC2:
4349 case KVM_CAP_HYPERV_VP_INDEX:
4350 case KVM_CAP_HYPERV_EVENTFD:
4351 case KVM_CAP_HYPERV_TLBFLUSH:
4352 case KVM_CAP_HYPERV_SEND_IPI:
4353 case KVM_CAP_HYPERV_CPUID:
4354 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4355 case KVM_CAP_SYS_HYPERV_CPUID:
4356 case KVM_CAP_PCI_SEGMENT:
4357 case KVM_CAP_DEBUGREGS:
4358 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4360 case KVM_CAP_ASYNC_PF:
4361 case KVM_CAP_ASYNC_PF_INT:
4362 case KVM_CAP_GET_TSC_KHZ:
4363 case KVM_CAP_KVMCLOCK_CTRL:
4364 case KVM_CAP_READONLY_MEM:
4365 case KVM_CAP_HYPERV_TIME:
4366 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4367 case KVM_CAP_TSC_DEADLINE_TIMER:
4368 case KVM_CAP_DISABLE_QUIRKS:
4369 case KVM_CAP_SET_BOOT_CPU_ID:
4370 case KVM_CAP_SPLIT_IRQCHIP:
4371 case KVM_CAP_IMMEDIATE_EXIT:
4372 case KVM_CAP_PMU_EVENT_FILTER:
4373 case KVM_CAP_GET_MSR_FEATURES:
4374 case KVM_CAP_MSR_PLATFORM_INFO:
4375 case KVM_CAP_EXCEPTION_PAYLOAD:
4376 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
4377 case KVM_CAP_SET_GUEST_DEBUG:
4378 case KVM_CAP_LAST_CPU:
4379 case KVM_CAP_X86_USER_SPACE_MSR:
4380 case KVM_CAP_X86_MSR_FILTER:
4381 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4382 #ifdef CONFIG_X86_SGX_KVM
4383 case KVM_CAP_SGX_ATTRIBUTE:
4385 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4386 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4387 case KVM_CAP_SREGS2:
4388 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4389 case KVM_CAP_VCPU_ATTRIBUTES:
4390 case KVM_CAP_SYS_ATTRIBUTES:
4392 case KVM_CAP_ENABLE_CAP:
4393 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
4396 case KVM_CAP_EXIT_HYPERCALL:
4397 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4399 case KVM_CAP_SET_GUEST_DEBUG2:
4400 return KVM_GUESTDBG_VALID_MASK;
4401 #ifdef CONFIG_KVM_XEN
4402 case KVM_CAP_XEN_HVM:
4403 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4404 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4405 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4406 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL |
4407 KVM_XEN_HVM_CONFIG_EVTCHN_SEND;
4408 if (sched_info_on())
4409 r |= KVM_XEN_HVM_CONFIG_RUNSTATE;
4412 case KVM_CAP_SYNC_REGS:
4413 r = KVM_SYNC_X86_VALID_FIELDS;
4415 case KVM_CAP_ADJUST_CLOCK:
4416 r = KVM_CLOCK_VALID_FLAGS;
4418 case KVM_CAP_X86_DISABLE_EXITS:
4419 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
4420 KVM_X86_DISABLE_EXITS_CSTATE;
4421 if(kvm_can_mwait_in_guest())
4422 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4424 case KVM_CAP_X86_SMM:
4425 /* SMBASE is usually relocated above 1M on modern chipsets,
4426 * and SMM handlers might indeed rely on 4G segment limits,
4427 * so do not report SMM to be available if real mode is
4428 * emulated via vm86 mode. Still, do not go to great lengths
4429 * to avoid userspace's usage of the feature, because it is a
4430 * fringe case that is not enabled except via specific settings
4431 * of the module parameters.
4433 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4435 case KVM_CAP_NR_VCPUS:
4436 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4438 case KVM_CAP_MAX_VCPUS:
4441 case KVM_CAP_MAX_VCPU_ID:
4442 r = KVM_MAX_VCPU_IDS;
4444 case KVM_CAP_PV_MMU: /* obsolete */
4448 r = KVM_MAX_MCE_BANKS;
4451 r = boot_cpu_has(X86_FEATURE_XSAVE);
4453 case KVM_CAP_TSC_CONTROL:
4454 case KVM_CAP_VM_TSC_CONTROL:
4455 r = kvm_caps.has_tsc_control;
4457 case KVM_CAP_X2APIC_API:
4458 r = KVM_X2APIC_API_VALID_FLAGS;
4460 case KVM_CAP_NESTED_STATE:
4461 r = kvm_x86_ops.nested_ops->get_state ?
4462 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4464 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4465 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
4467 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4468 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4470 case KVM_CAP_SMALLER_MAXPHYADDR:
4471 r = (int) allow_smaller_maxphyaddr;
4473 case KVM_CAP_STEAL_TIME:
4474 r = sched_info_on();
4476 case KVM_CAP_X86_BUS_LOCK_EXIT:
4477 if (kvm_caps.has_bus_lock_exit)
4478 r = KVM_BUS_LOCK_DETECTION_OFF |
4479 KVM_BUS_LOCK_DETECTION_EXIT;
4483 case KVM_CAP_XSAVE2: {
4484 u64 guest_perm = xstate_get_guest_group_perm();
4486 r = xstate_required_size(kvm_caps.supported_xcr0 & guest_perm, false);
4487 if (r < sizeof(struct kvm_xsave))
4488 r = sizeof(struct kvm_xsave);
4491 case KVM_CAP_PMU_CAPABILITY:
4492 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4494 case KVM_CAP_DISABLE_QUIRKS2:
4495 r = KVM_X86_VALID_QUIRKS;
4497 case KVM_CAP_X86_NOTIFY_VMEXIT:
4498 r = kvm_caps.has_notify_vmexit;
4506 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4508 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4510 if ((u64)(unsigned long)uaddr != attr->addr)
4511 return ERR_PTR_USR(-EFAULT);
4515 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4517 u64 __user *uaddr = kvm_get_attr_addr(attr);
4523 return PTR_ERR(uaddr);
4525 switch (attr->attr) {
4526 case KVM_X86_XCOMP_GUEST_SUPP:
4527 if (put_user(kvm_caps.supported_xcr0, uaddr))
4536 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4541 switch (attr->attr) {
4542 case KVM_X86_XCOMP_GUEST_SUPP:
4549 long kvm_arch_dev_ioctl(struct file *filp,
4550 unsigned int ioctl, unsigned long arg)
4552 void __user *argp = (void __user *)arg;
4556 case KVM_GET_MSR_INDEX_LIST: {
4557 struct kvm_msr_list __user *user_msr_list = argp;
4558 struct kvm_msr_list msr_list;
4562 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4565 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4566 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4569 if (n < msr_list.nmsrs)
4572 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4573 num_msrs_to_save * sizeof(u32)))
4575 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4577 num_emulated_msrs * sizeof(u32)))
4582 case KVM_GET_SUPPORTED_CPUID:
4583 case KVM_GET_EMULATED_CPUID: {
4584 struct kvm_cpuid2 __user *cpuid_arg = argp;
4585 struct kvm_cpuid2 cpuid;
4588 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4591 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4597 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4602 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4604 if (copy_to_user(argp, &kvm_caps.supported_mce_cap,
4605 sizeof(kvm_caps.supported_mce_cap)))
4609 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4610 struct kvm_msr_list __user *user_msr_list = argp;
4611 struct kvm_msr_list msr_list;
4615 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4618 msr_list.nmsrs = num_msr_based_features;
4619 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4622 if (n < msr_list.nmsrs)
4625 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4626 num_msr_based_features * sizeof(u32)))
4632 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4634 case KVM_GET_SUPPORTED_HV_CPUID:
4635 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4637 case KVM_GET_DEVICE_ATTR: {
4638 struct kvm_device_attr attr;
4640 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4642 r = kvm_x86_dev_get_attr(&attr);
4645 case KVM_HAS_DEVICE_ATTR: {
4646 struct kvm_device_attr attr;
4648 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4650 r = kvm_x86_dev_has_attr(&attr);
4661 static void wbinvd_ipi(void *garbage)
4666 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4668 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4671 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4673 /* Address WBINVD may be executed by guest */
4674 if (need_emulate_wbinvd(vcpu)) {
4675 if (static_call(kvm_x86_has_wbinvd_exit)())
4676 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4677 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4678 smp_call_function_single(vcpu->cpu,
4679 wbinvd_ipi, NULL, 1);
4682 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4684 /* Save host pkru register if supported */
4685 vcpu->arch.host_pkru = read_pkru();
4687 /* Apply any externally detected TSC adjustments (due to suspend) */
4688 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4689 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4690 vcpu->arch.tsc_offset_adjustment = 0;
4691 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4694 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4695 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4696 rdtsc() - vcpu->arch.last_host_tsc;
4698 mark_tsc_unstable("KVM discovered backwards TSC");
4700 if (kvm_check_tsc_unstable()) {
4701 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4702 vcpu->arch.last_guest_tsc);
4703 kvm_vcpu_write_tsc_offset(vcpu, offset);
4704 vcpu->arch.tsc_catchup = 1;
4707 if (kvm_lapic_hv_timer_in_use(vcpu))
4708 kvm_lapic_restart_hv_timer(vcpu);
4711 * On a host with synchronized TSC, there is no need to update
4712 * kvmclock on vcpu->cpu migration
4714 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4715 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4716 if (vcpu->cpu != cpu)
4717 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4721 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4724 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4726 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
4727 struct kvm_steal_time __user *st;
4728 struct kvm_memslots *slots;
4729 static const u8 preempted = KVM_VCPU_PREEMPTED;
4730 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
4733 * The vCPU can be marked preempted if and only if the VM-Exit was on
4734 * an instruction boundary and will not trigger guest emulation of any
4735 * kind (see vcpu_run). Vendor specific code controls (conservatively)
4736 * when this is true, for example allowing the vCPU to be marked
4737 * preempted if and only if the VM-Exit was due to a host interrupt.
4739 if (!vcpu->arch.at_instruction_boundary) {
4740 vcpu->stat.preemption_other++;
4744 vcpu->stat.preemption_reported++;
4745 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4748 if (vcpu->arch.st.preempted)
4751 /* This happens on process exit */
4752 if (unlikely(current->mm != vcpu->kvm->mm))
4755 slots = kvm_memslots(vcpu->kvm);
4757 if (unlikely(slots->generation != ghc->generation ||
4759 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
4762 st = (struct kvm_steal_time __user *)ghc->hva;
4763 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
4765 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
4766 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4768 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
4771 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4775 if (vcpu->preempted) {
4776 if (!vcpu->arch.guest_state_protected)
4777 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4780 * Take the srcu lock as memslots will be accessed to check the gfn
4781 * cache generation against the memslots generation.
4783 idx = srcu_read_lock(&vcpu->kvm->srcu);
4784 if (kvm_xen_msr_enabled(vcpu->kvm))
4785 kvm_xen_runstate_set_preempted(vcpu);
4787 kvm_steal_time_set_preempted(vcpu);
4788 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4791 static_call(kvm_x86_vcpu_put)(vcpu);
4792 vcpu->arch.last_host_tsc = rdtsc();
4795 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4796 struct kvm_lapic_state *s)
4798 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
4800 return kvm_apic_get_state(vcpu, s);
4803 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4804 struct kvm_lapic_state *s)
4808 r = kvm_apic_set_state(vcpu, s);
4811 update_cr8_intercept(vcpu);
4816 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4819 * We can accept userspace's request for interrupt injection
4820 * as long as we have a place to store the interrupt number.
4821 * The actual injection will happen when the CPU is able to
4822 * deliver the interrupt.
4824 if (kvm_cpu_has_extint(vcpu))
4827 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4828 return (!lapic_in_kernel(vcpu) ||
4829 kvm_apic_accept_pic_intr(vcpu));
4832 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4835 * Do not cause an interrupt window exit if an exception
4836 * is pending or an event needs reinjection; userspace
4837 * might want to inject the interrupt manually using KVM_SET_REGS
4838 * or KVM_SET_SREGS. For that to work, we must be at an
4839 * instruction boundary and with no events half-injected.
4841 return (kvm_arch_interrupt_allowed(vcpu) &&
4842 kvm_cpu_accept_dm_intr(vcpu) &&
4843 !kvm_event_needs_reinjection(vcpu) &&
4844 !vcpu->arch.exception.pending);
4847 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4848 struct kvm_interrupt *irq)
4850 if (irq->irq >= KVM_NR_INTERRUPTS)
4853 if (!irqchip_in_kernel(vcpu->kvm)) {
4854 kvm_queue_interrupt(vcpu, irq->irq, false);
4855 kvm_make_request(KVM_REQ_EVENT, vcpu);
4860 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4861 * fail for in-kernel 8259.
4863 if (pic_in_kernel(vcpu->kvm))
4866 if (vcpu->arch.pending_external_vector != -1)
4869 vcpu->arch.pending_external_vector = irq->irq;
4870 kvm_make_request(KVM_REQ_EVENT, vcpu);
4874 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4876 kvm_inject_nmi(vcpu);
4881 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4883 kvm_make_request(KVM_REQ_SMI, vcpu);
4888 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4889 struct kvm_tpr_access_ctl *tac)
4893 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4897 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4901 unsigned bank_num = mcg_cap & 0xff, bank;
4904 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4906 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000))
4909 vcpu->arch.mcg_cap = mcg_cap;
4910 /* Init IA32_MCG_CTL to all 1s */
4911 if (mcg_cap & MCG_CTL_P)
4912 vcpu->arch.mcg_ctl = ~(u64)0;
4913 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */
4914 for (bank = 0; bank < bank_num; bank++) {
4915 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4916 if (mcg_cap & MCG_CMCI_P)
4917 vcpu->arch.mci_ctl2_banks[bank] = 0;
4920 kvm_apic_after_set_mcg_cap(vcpu);
4922 static_call(kvm_x86_setup_mce)(vcpu);
4928 * Validate this is an UCNA (uncorrectable no action) error by checking the
4929 * MCG_STATUS and MCi_STATUS registers:
4930 * - none of the bits for Machine Check Exceptions are set
4931 * - both the VAL (valid) and UC (uncorrectable) bits are set
4932 * MCI_STATUS_PCC - Processor Context Corrupted
4933 * MCI_STATUS_S - Signaled as a Machine Check Exception
4934 * MCI_STATUS_AR - Software recoverable Action Required
4936 static bool is_ucna(struct kvm_x86_mce *mce)
4938 return !mce->mcg_status &&
4939 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) &&
4940 (mce->status & MCI_STATUS_VAL) &&
4941 (mce->status & MCI_STATUS_UC);
4944 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks)
4946 u64 mcg_cap = vcpu->arch.mcg_cap;
4948 banks[1] = mce->status;
4949 banks[2] = mce->addr;
4950 banks[3] = mce->misc;
4951 vcpu->arch.mcg_status = mce->mcg_status;
4953 if (!(mcg_cap & MCG_CMCI_P) ||
4954 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))
4957 if (lapic_in_kernel(vcpu))
4958 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI);
4963 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4964 struct kvm_x86_mce *mce)
4966 u64 mcg_cap = vcpu->arch.mcg_cap;
4967 unsigned bank_num = mcg_cap & 0xff;
4968 u64 *banks = vcpu->arch.mce_banks;
4970 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4973 banks += array_index_nospec(4 * mce->bank, 4 * bank_num);
4976 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks);
4979 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4980 * reporting is disabled
4982 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4983 vcpu->arch.mcg_ctl != ~(u64)0)
4986 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4987 * reporting is disabled for the bank
4989 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4991 if (mce->status & MCI_STATUS_UC) {
4992 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4993 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4994 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4997 if (banks[1] & MCI_STATUS_VAL)
4998 mce->status |= MCI_STATUS_OVER;
4999 banks[2] = mce->addr;
5000 banks[3] = mce->misc;
5001 vcpu->arch.mcg_status = mce->mcg_status;
5002 banks[1] = mce->status;
5003 kvm_queue_exception(vcpu, MC_VECTOR);
5004 } else if (!(banks[1] & MCI_STATUS_VAL)
5005 || !(banks[1] & MCI_STATUS_UC)) {
5006 if (banks[1] & MCI_STATUS_VAL)
5007 mce->status |= MCI_STATUS_OVER;
5008 banks[2] = mce->addr;
5009 banks[3] = mce->misc;
5010 banks[1] = mce->status;
5012 banks[1] |= MCI_STATUS_OVER;
5016 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
5017 struct kvm_vcpu_events *events)
5021 if (kvm_check_request(KVM_REQ_SMI, vcpu))
5025 * In guest mode, payload delivery should be deferred,
5026 * so that the L1 hypervisor can intercept #PF before
5027 * CR2 is modified (or intercept #DB before DR6 is
5028 * modified under nVMX). Unless the per-VM capability,
5029 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
5030 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
5031 * opportunistically defer the exception payload, deliver it if the
5032 * capability hasn't been requested before processing a
5033 * KVM_GET_VCPU_EVENTS.
5035 if (!vcpu->kvm->arch.exception_payload_enabled &&
5036 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
5037 kvm_deliver_exception_payload(vcpu);
5040 * The API doesn't provide the instruction length for software
5041 * exceptions, so don't report them. As long as the guest RIP
5042 * isn't advanced, we should expect to encounter the exception
5045 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
5046 events->exception.injected = 0;
5047 events->exception.pending = 0;
5049 events->exception.injected = vcpu->arch.exception.injected;
5050 events->exception.pending = vcpu->arch.exception.pending;
5052 * For ABI compatibility, deliberately conflate
5053 * pending and injected exceptions when
5054 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
5056 if (!vcpu->kvm->arch.exception_payload_enabled)
5057 events->exception.injected |=
5058 vcpu->arch.exception.pending;
5060 events->exception.nr = vcpu->arch.exception.nr;
5061 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
5062 events->exception.error_code = vcpu->arch.exception.error_code;
5063 events->exception_has_payload = vcpu->arch.exception.has_payload;
5064 events->exception_payload = vcpu->arch.exception.payload;
5066 events->interrupt.injected =
5067 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
5068 events->interrupt.nr = vcpu->arch.interrupt.nr;
5069 events->interrupt.soft = 0;
5070 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
5072 events->nmi.injected = vcpu->arch.nmi_injected;
5073 events->nmi.pending = vcpu->arch.nmi_pending != 0;
5074 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
5075 events->nmi.pad = 0;
5077 events->sipi_vector = 0; /* never valid when reporting to user space */
5079 events->smi.smm = is_smm(vcpu);
5080 events->smi.pending = vcpu->arch.smi_pending;
5081 events->smi.smm_inside_nmi =
5082 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
5083 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
5085 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
5086 | KVM_VCPUEVENT_VALID_SHADOW
5087 | KVM_VCPUEVENT_VALID_SMM);
5088 if (vcpu->kvm->arch.exception_payload_enabled)
5089 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5090 if (vcpu->kvm->arch.triple_fault_event) {
5091 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5092 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5095 memset(&events->reserved, 0, sizeof(events->reserved));
5098 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm);
5100 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
5101 struct kvm_vcpu_events *events)
5103 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
5104 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
5105 | KVM_VCPUEVENT_VALID_SHADOW
5106 | KVM_VCPUEVENT_VALID_SMM
5107 | KVM_VCPUEVENT_VALID_PAYLOAD
5108 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT))
5111 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5112 if (!vcpu->kvm->arch.exception_payload_enabled)
5114 if (events->exception.pending)
5115 events->exception.injected = 0;
5117 events->exception_has_payload = 0;
5119 events->exception.pending = 0;
5120 events->exception_has_payload = 0;
5123 if ((events->exception.injected || events->exception.pending) &&
5124 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
5127 /* INITs are latched while in SMM */
5128 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
5129 (events->smi.smm || events->smi.pending) &&
5130 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
5134 vcpu->arch.exception.injected = events->exception.injected;
5135 vcpu->arch.exception.pending = events->exception.pending;
5136 vcpu->arch.exception.nr = events->exception.nr;
5137 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
5138 vcpu->arch.exception.error_code = events->exception.error_code;
5139 vcpu->arch.exception.has_payload = events->exception_has_payload;
5140 vcpu->arch.exception.payload = events->exception_payload;
5142 vcpu->arch.interrupt.injected = events->interrupt.injected;
5143 vcpu->arch.interrupt.nr = events->interrupt.nr;
5144 vcpu->arch.interrupt.soft = events->interrupt.soft;
5145 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
5146 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
5147 events->interrupt.shadow);
5149 vcpu->arch.nmi_injected = events->nmi.injected;
5150 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
5151 vcpu->arch.nmi_pending = events->nmi.pending;
5152 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
5154 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
5155 lapic_in_kernel(vcpu))
5156 vcpu->arch.apic->sipi_vector = events->sipi_vector;
5158 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
5159 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
5160 kvm_x86_ops.nested_ops->leave_nested(vcpu);
5161 kvm_smm_changed(vcpu, events->smi.smm);
5164 vcpu->arch.smi_pending = events->smi.pending;
5166 if (events->smi.smm) {
5167 if (events->smi.smm_inside_nmi)
5168 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
5170 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
5173 if (lapic_in_kernel(vcpu)) {
5174 if (events->smi.latched_init)
5175 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5177 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5181 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5182 if (!vcpu->kvm->arch.triple_fault_event)
5184 if (events->triple_fault.pending)
5185 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5187 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5190 kvm_make_request(KVM_REQ_EVENT, vcpu);
5195 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
5196 struct kvm_debugregs *dbgregs)
5200 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
5201 kvm_get_dr(vcpu, 6, &val);
5203 dbgregs->dr7 = vcpu->arch.dr7;
5205 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
5208 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5209 struct kvm_debugregs *dbgregs)
5214 if (!kvm_dr6_valid(dbgregs->dr6))
5216 if (!kvm_dr7_valid(dbgregs->dr7))
5219 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5220 kvm_update_dr0123(vcpu);
5221 vcpu->arch.dr6 = dbgregs->dr6;
5222 vcpu->arch.dr7 = dbgregs->dr7;
5223 kvm_update_dr7(vcpu);
5228 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5229 struct kvm_xsave *guest_xsave)
5231 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5234 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5235 guest_xsave->region,
5236 sizeof(guest_xsave->region),
5240 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5241 u8 *state, unsigned int size)
5243 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5246 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5247 state, size, vcpu->arch.pkru);
5250 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5251 struct kvm_xsave *guest_xsave)
5253 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5256 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5257 guest_xsave->region,
5258 kvm_caps.supported_xcr0,
5262 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5263 struct kvm_xcrs *guest_xcrs)
5265 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5266 guest_xcrs->nr_xcrs = 0;
5270 guest_xcrs->nr_xcrs = 1;
5271 guest_xcrs->flags = 0;
5272 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5273 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5276 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5277 struct kvm_xcrs *guest_xcrs)
5281 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5284 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5287 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5288 /* Only support XCR0 currently */
5289 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5290 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5291 guest_xcrs->xcrs[i].value);
5300 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5301 * stopped by the hypervisor. This function will be called from the host only.
5302 * EINVAL is returned when the host attempts to set the flag for a guest that
5303 * does not support pv clocks.
5305 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5307 if (!vcpu->arch.pv_time.active)
5309 vcpu->arch.pvclock_set_guest_stopped_request = true;
5310 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5314 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5315 struct kvm_device_attr *attr)
5319 switch (attr->attr) {
5320 case KVM_VCPU_TSC_OFFSET:
5330 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5331 struct kvm_device_attr *attr)
5333 u64 __user *uaddr = kvm_get_attr_addr(attr);
5337 return PTR_ERR(uaddr);
5339 switch (attr->attr) {
5340 case KVM_VCPU_TSC_OFFSET:
5342 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5353 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5354 struct kvm_device_attr *attr)
5356 u64 __user *uaddr = kvm_get_attr_addr(attr);
5357 struct kvm *kvm = vcpu->kvm;
5361 return PTR_ERR(uaddr);
5363 switch (attr->attr) {
5364 case KVM_VCPU_TSC_OFFSET: {
5365 u64 offset, tsc, ns;
5366 unsigned long flags;
5370 if (get_user(offset, uaddr))
5373 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5375 matched = (vcpu->arch.virtual_tsc_khz &&
5376 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5377 kvm->arch.last_tsc_offset == offset);
5379 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5380 ns = get_kvmclock_base_ns();
5382 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5383 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5395 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5399 struct kvm_device_attr attr;
5402 if (copy_from_user(&attr, argp, sizeof(attr)))
5405 if (attr.group != KVM_VCPU_TSC_CTRL)
5409 case KVM_HAS_DEVICE_ATTR:
5410 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5412 case KVM_GET_DEVICE_ATTR:
5413 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5415 case KVM_SET_DEVICE_ATTR:
5416 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5423 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5424 struct kvm_enable_cap *cap)
5427 uint16_t vmcs_version;
5428 void __user *user_ptr;
5434 case KVM_CAP_HYPERV_SYNIC2:
5439 case KVM_CAP_HYPERV_SYNIC:
5440 if (!irqchip_in_kernel(vcpu->kvm))
5442 return kvm_hv_activate_synic(vcpu, cap->cap ==
5443 KVM_CAP_HYPERV_SYNIC2);
5444 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5445 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5447 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5449 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5450 if (copy_to_user(user_ptr, &vmcs_version,
5451 sizeof(vmcs_version)))
5455 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5456 if (!kvm_x86_ops.enable_direct_tlbflush)
5459 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu);
5461 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5462 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5464 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5465 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5466 if (vcpu->arch.pv_cpuid.enforce)
5467 kvm_update_pv_runtime(vcpu);
5475 long kvm_arch_vcpu_ioctl(struct file *filp,
5476 unsigned int ioctl, unsigned long arg)
5478 struct kvm_vcpu *vcpu = filp->private_data;
5479 void __user *argp = (void __user *)arg;
5482 struct kvm_sregs2 *sregs2;
5483 struct kvm_lapic_state *lapic;
5484 struct kvm_xsave *xsave;
5485 struct kvm_xcrs *xcrs;
5493 case KVM_GET_LAPIC: {
5495 if (!lapic_in_kernel(vcpu))
5497 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5498 GFP_KERNEL_ACCOUNT);
5503 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5507 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5512 case KVM_SET_LAPIC: {
5514 if (!lapic_in_kernel(vcpu))
5516 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5517 if (IS_ERR(u.lapic)) {
5518 r = PTR_ERR(u.lapic);
5522 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5525 case KVM_INTERRUPT: {
5526 struct kvm_interrupt irq;
5529 if (copy_from_user(&irq, argp, sizeof(irq)))
5531 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5535 r = kvm_vcpu_ioctl_nmi(vcpu);
5539 r = kvm_vcpu_ioctl_smi(vcpu);
5542 case KVM_SET_CPUID: {
5543 struct kvm_cpuid __user *cpuid_arg = argp;
5544 struct kvm_cpuid cpuid;
5547 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5549 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5552 case KVM_SET_CPUID2: {
5553 struct kvm_cpuid2 __user *cpuid_arg = argp;
5554 struct kvm_cpuid2 cpuid;
5557 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5559 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5560 cpuid_arg->entries);
5563 case KVM_GET_CPUID2: {
5564 struct kvm_cpuid2 __user *cpuid_arg = argp;
5565 struct kvm_cpuid2 cpuid;
5568 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5570 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5571 cpuid_arg->entries);
5575 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5580 case KVM_GET_MSRS: {
5581 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5582 r = msr_io(vcpu, argp, do_get_msr, 1);
5583 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5586 case KVM_SET_MSRS: {
5587 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5588 r = msr_io(vcpu, argp, do_set_msr, 0);
5589 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5592 case KVM_TPR_ACCESS_REPORTING: {
5593 struct kvm_tpr_access_ctl tac;
5596 if (copy_from_user(&tac, argp, sizeof(tac)))
5598 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5602 if (copy_to_user(argp, &tac, sizeof(tac)))
5607 case KVM_SET_VAPIC_ADDR: {
5608 struct kvm_vapic_addr va;
5612 if (!lapic_in_kernel(vcpu))
5615 if (copy_from_user(&va, argp, sizeof(va)))
5617 idx = srcu_read_lock(&vcpu->kvm->srcu);
5618 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5619 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5622 case KVM_X86_SETUP_MCE: {
5626 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5628 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5631 case KVM_X86_SET_MCE: {
5632 struct kvm_x86_mce mce;
5635 if (copy_from_user(&mce, argp, sizeof(mce)))
5637 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5640 case KVM_GET_VCPU_EVENTS: {
5641 struct kvm_vcpu_events events;
5643 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5646 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5651 case KVM_SET_VCPU_EVENTS: {
5652 struct kvm_vcpu_events events;
5655 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5658 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5661 case KVM_GET_DEBUGREGS: {
5662 struct kvm_debugregs dbgregs;
5664 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5667 if (copy_to_user(argp, &dbgregs,
5668 sizeof(struct kvm_debugregs)))
5673 case KVM_SET_DEBUGREGS: {
5674 struct kvm_debugregs dbgregs;
5677 if (copy_from_user(&dbgregs, argp,
5678 sizeof(struct kvm_debugregs)))
5681 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
5684 case KVM_GET_XSAVE: {
5686 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
5689 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
5694 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
5697 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
5702 case KVM_SET_XSAVE: {
5703 int size = vcpu->arch.guest_fpu.uabi_size;
5705 u.xsave = memdup_user(argp, size);
5706 if (IS_ERR(u.xsave)) {
5707 r = PTR_ERR(u.xsave);
5711 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
5715 case KVM_GET_XSAVE2: {
5716 int size = vcpu->arch.guest_fpu.uabi_size;
5718 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
5723 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
5726 if (copy_to_user(argp, u.xsave, size))
5733 case KVM_GET_XCRS: {
5734 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
5739 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
5742 if (copy_to_user(argp, u.xcrs,
5743 sizeof(struct kvm_xcrs)))
5748 case KVM_SET_XCRS: {
5749 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
5750 if (IS_ERR(u.xcrs)) {
5751 r = PTR_ERR(u.xcrs);
5755 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
5758 case KVM_SET_TSC_KHZ: {
5762 user_tsc_khz = (u32)arg;
5764 if (kvm_caps.has_tsc_control &&
5765 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
5768 if (user_tsc_khz == 0)
5769 user_tsc_khz = tsc_khz;
5771 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
5776 case KVM_GET_TSC_KHZ: {
5777 r = vcpu->arch.virtual_tsc_khz;
5780 case KVM_KVMCLOCK_CTRL: {
5781 r = kvm_set_guest_paused(vcpu);
5784 case KVM_ENABLE_CAP: {
5785 struct kvm_enable_cap cap;
5788 if (copy_from_user(&cap, argp, sizeof(cap)))
5790 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
5793 case KVM_GET_NESTED_STATE: {
5794 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5798 if (!kvm_x86_ops.nested_ops->get_state)
5801 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
5803 if (get_user(user_data_size, &user_kvm_nested_state->size))
5806 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
5811 if (r > user_data_size) {
5812 if (put_user(r, &user_kvm_nested_state->size))
5822 case KVM_SET_NESTED_STATE: {
5823 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5824 struct kvm_nested_state kvm_state;
5828 if (!kvm_x86_ops.nested_ops->set_state)
5832 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5836 if (kvm_state.size < sizeof(kvm_state))
5839 if (kvm_state.flags &
5840 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5841 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5842 | KVM_STATE_NESTED_GIF_SET))
5845 /* nested_run_pending implies guest_mode. */
5846 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5847 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5850 idx = srcu_read_lock(&vcpu->kvm->srcu);
5851 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5852 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5855 case KVM_GET_SUPPORTED_HV_CPUID:
5856 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5858 #ifdef CONFIG_KVM_XEN
5859 case KVM_XEN_VCPU_GET_ATTR: {
5860 struct kvm_xen_vcpu_attr xva;
5863 if (copy_from_user(&xva, argp, sizeof(xva)))
5865 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
5866 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
5870 case KVM_XEN_VCPU_SET_ATTR: {
5871 struct kvm_xen_vcpu_attr xva;
5874 if (copy_from_user(&xva, argp, sizeof(xva)))
5876 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
5880 case KVM_GET_SREGS2: {
5881 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
5885 __get_sregs2(vcpu, u.sregs2);
5887 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
5892 case KVM_SET_SREGS2: {
5893 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
5894 if (IS_ERR(u.sregs2)) {
5895 r = PTR_ERR(u.sregs2);
5899 r = __set_sregs2(vcpu, u.sregs2);
5902 case KVM_HAS_DEVICE_ATTR:
5903 case KVM_GET_DEVICE_ATTR:
5904 case KVM_SET_DEVICE_ATTR:
5905 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
5917 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5919 return VM_FAULT_SIGBUS;
5922 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5926 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5928 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
5932 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5935 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
5938 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5939 unsigned long kvm_nr_mmu_pages)
5941 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5944 mutex_lock(&kvm->slots_lock);
5946 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5947 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5949 mutex_unlock(&kvm->slots_lock);
5953 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5955 return kvm->arch.n_max_mmu_pages;
5958 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5960 struct kvm_pic *pic = kvm->arch.vpic;
5964 switch (chip->chip_id) {
5965 case KVM_IRQCHIP_PIC_MASTER:
5966 memcpy(&chip->chip.pic, &pic->pics[0],
5967 sizeof(struct kvm_pic_state));
5969 case KVM_IRQCHIP_PIC_SLAVE:
5970 memcpy(&chip->chip.pic, &pic->pics[1],
5971 sizeof(struct kvm_pic_state));
5973 case KVM_IRQCHIP_IOAPIC:
5974 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5983 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5985 struct kvm_pic *pic = kvm->arch.vpic;
5989 switch (chip->chip_id) {
5990 case KVM_IRQCHIP_PIC_MASTER:
5991 spin_lock(&pic->lock);
5992 memcpy(&pic->pics[0], &chip->chip.pic,
5993 sizeof(struct kvm_pic_state));
5994 spin_unlock(&pic->lock);
5996 case KVM_IRQCHIP_PIC_SLAVE:
5997 spin_lock(&pic->lock);
5998 memcpy(&pic->pics[1], &chip->chip.pic,
5999 sizeof(struct kvm_pic_state));
6000 spin_unlock(&pic->lock);
6002 case KVM_IRQCHIP_IOAPIC:
6003 kvm_set_ioapic(kvm, &chip->chip.ioapic);
6009 kvm_pic_update_irq(pic);
6013 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6015 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
6017 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
6019 mutex_lock(&kps->lock);
6020 memcpy(ps, &kps->channels, sizeof(*ps));
6021 mutex_unlock(&kps->lock);
6025 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6028 struct kvm_pit *pit = kvm->arch.vpit;
6030 mutex_lock(&pit->pit_state.lock);
6031 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
6032 for (i = 0; i < 3; i++)
6033 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
6034 mutex_unlock(&pit->pit_state.lock);
6038 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6040 mutex_lock(&kvm->arch.vpit->pit_state.lock);
6041 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
6042 sizeof(ps->channels));
6043 ps->flags = kvm->arch.vpit->pit_state.flags;
6044 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
6045 memset(&ps->reserved, 0, sizeof(ps->reserved));
6049 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6053 u32 prev_legacy, cur_legacy;
6054 struct kvm_pit *pit = kvm->arch.vpit;
6056 mutex_lock(&pit->pit_state.lock);
6057 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
6058 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
6059 if (!prev_legacy && cur_legacy)
6061 memcpy(&pit->pit_state.channels, &ps->channels,
6062 sizeof(pit->pit_state.channels));
6063 pit->pit_state.flags = ps->flags;
6064 for (i = 0; i < 3; i++)
6065 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
6067 mutex_unlock(&pit->pit_state.lock);
6071 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
6072 struct kvm_reinject_control *control)
6074 struct kvm_pit *pit = kvm->arch.vpit;
6076 /* pit->pit_state.lock was overloaded to prevent userspace from getting
6077 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
6078 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
6080 mutex_lock(&pit->pit_state.lock);
6081 kvm_pit_set_reinject(pit, control->pit_reinject);
6082 mutex_unlock(&pit->pit_state.lock);
6087 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
6091 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
6092 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
6093 * on all VM-Exits, thus we only need to kick running vCPUs to force a
6096 struct kvm_vcpu *vcpu;
6099 kvm_for_each_vcpu(i, vcpu, kvm)
6100 kvm_vcpu_kick(vcpu);
6103 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
6106 if (!irqchip_in_kernel(kvm))
6109 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
6110 irq_event->irq, irq_event->level,
6115 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
6116 struct kvm_enable_cap *cap)
6124 case KVM_CAP_DISABLE_QUIRKS2:
6126 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
6129 case KVM_CAP_DISABLE_QUIRKS:
6130 kvm->arch.disabled_quirks = cap->args[0];
6133 case KVM_CAP_SPLIT_IRQCHIP: {
6134 mutex_lock(&kvm->lock);
6136 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
6137 goto split_irqchip_unlock;
6139 if (irqchip_in_kernel(kvm))
6140 goto split_irqchip_unlock;
6141 if (kvm->created_vcpus)
6142 goto split_irqchip_unlock;
6143 r = kvm_setup_empty_irq_routing(kvm);
6145 goto split_irqchip_unlock;
6146 /* Pairs with irqchip_in_kernel. */
6148 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
6149 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
6150 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6152 split_irqchip_unlock:
6153 mutex_unlock(&kvm->lock);
6156 case KVM_CAP_X2APIC_API:
6158 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
6161 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
6162 kvm->arch.x2apic_format = true;
6163 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
6164 kvm->arch.x2apic_broadcast_quirk_disabled = true;
6168 case KVM_CAP_X86_DISABLE_EXITS:
6170 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
6173 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
6174 kvm_can_mwait_in_guest())
6175 kvm->arch.mwait_in_guest = true;
6176 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
6177 kvm->arch.hlt_in_guest = true;
6178 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
6179 kvm->arch.pause_in_guest = true;
6180 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
6181 kvm->arch.cstate_in_guest = true;
6184 case KVM_CAP_MSR_PLATFORM_INFO:
6185 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
6188 case KVM_CAP_EXCEPTION_PAYLOAD:
6189 kvm->arch.exception_payload_enabled = cap->args[0];
6192 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
6193 kvm->arch.triple_fault_event = cap->args[0];
6196 case KVM_CAP_X86_USER_SPACE_MSR:
6198 if (cap->args[0] & ~(KVM_MSR_EXIT_REASON_INVAL |
6199 KVM_MSR_EXIT_REASON_UNKNOWN |
6200 KVM_MSR_EXIT_REASON_FILTER))
6202 kvm->arch.user_space_msr_mask = cap->args[0];
6205 case KVM_CAP_X86_BUS_LOCK_EXIT:
6207 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
6210 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6211 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6214 if (kvm_caps.has_bus_lock_exit &&
6215 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6216 kvm->arch.bus_lock_detection_enabled = true;
6219 #ifdef CONFIG_X86_SGX_KVM
6220 case KVM_CAP_SGX_ATTRIBUTE: {
6221 unsigned long allowed_attributes = 0;
6223 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6227 /* KVM only supports the PROVISIONKEY privileged attribute. */
6228 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6229 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6230 kvm->arch.sgx_provisioning_allowed = true;
6236 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6238 if (!kvm_x86_ops.vm_copy_enc_context_from)
6241 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6243 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6245 if (!kvm_x86_ops.vm_move_enc_context_from)
6248 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6250 case KVM_CAP_EXIT_HYPERCALL:
6251 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6255 kvm->arch.hypercall_exit_enabled = cap->args[0];
6258 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6260 if (cap->args[0] & ~1)
6262 kvm->arch.exit_on_emulation_error = cap->args[0];
6265 case KVM_CAP_PMU_CAPABILITY:
6267 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6270 mutex_lock(&kvm->lock);
6271 if (!kvm->created_vcpus) {
6272 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6275 mutex_unlock(&kvm->lock);
6277 case KVM_CAP_MAX_VCPU_ID:
6279 if (cap->args[0] > KVM_MAX_VCPU_IDS)
6282 mutex_lock(&kvm->lock);
6283 if (kvm->arch.max_vcpu_ids == cap->args[0]) {
6285 } else if (!kvm->arch.max_vcpu_ids) {
6286 kvm->arch.max_vcpu_ids = cap->args[0];
6289 mutex_unlock(&kvm->lock);
6291 case KVM_CAP_X86_NOTIFY_VMEXIT:
6293 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS)
6295 if (!kvm_caps.has_notify_vmexit)
6297 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED))
6299 mutex_lock(&kvm->lock);
6300 if (!kvm->created_vcpus) {
6301 kvm->arch.notify_window = cap->args[0] >> 32;
6302 kvm->arch.notify_vmexit_flags = (u32)cap->args[0];
6305 mutex_unlock(&kvm->lock);
6307 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
6311 * Since the risk of disabling NX hugepages is a guest crashing
6312 * the system, ensure the userspace process has permission to
6313 * reboot the system.
6315 * Note that unlike the reboot() syscall, the process must have
6316 * this capability in the root namespace because exposing
6317 * /dev/kvm into a container does not limit the scope of the
6318 * iTLB multihit bug to that container. In other words,
6319 * this must use capable(), not ns_capable().
6321 if (!capable(CAP_SYS_BOOT)) {
6329 mutex_lock(&kvm->lock);
6330 if (!kvm->created_vcpus) {
6331 kvm->arch.disable_nx_huge_pages = true;
6334 mutex_unlock(&kvm->lock);
6343 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6345 struct kvm_x86_msr_filter *msr_filter;
6347 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6351 msr_filter->default_allow = default_allow;
6355 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6362 for (i = 0; i < msr_filter->count; i++)
6363 kfree(msr_filter->ranges[i].bitmap);
6368 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6369 struct kvm_msr_filter_range *user_range)
6371 unsigned long *bitmap = NULL;
6374 if (!user_range->nmsrs)
6377 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE))
6380 if (!user_range->flags)
6383 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6384 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6387 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6389 return PTR_ERR(bitmap);
6391 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6392 .flags = user_range->flags,
6393 .base = user_range->base,
6394 .nmsrs = user_range->nmsrs,
6398 msr_filter->count++;
6402 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
6404 struct kvm_msr_filter __user *user_msr_filter = argp;
6405 struct kvm_x86_msr_filter *new_filter, *old_filter;
6406 struct kvm_msr_filter filter;
6412 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
6415 if (filter.flags & ~KVM_MSR_FILTER_DEFAULT_DENY)
6418 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
6419 empty &= !filter.ranges[i].nmsrs;
6421 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
6422 if (empty && !default_allow)
6425 new_filter = kvm_alloc_msr_filter(default_allow);
6429 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6430 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]);
6432 kvm_free_msr_filter(new_filter);
6437 mutex_lock(&kvm->lock);
6439 /* The per-VM filter is protected by kvm->lock... */
6440 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1);
6442 rcu_assign_pointer(kvm->arch.msr_filter, new_filter);
6443 synchronize_srcu(&kvm->srcu);
6445 kvm_free_msr_filter(old_filter);
6447 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6448 mutex_unlock(&kvm->lock);
6453 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6454 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6456 struct kvm_vcpu *vcpu;
6460 mutex_lock(&kvm->lock);
6461 kvm_for_each_vcpu(i, vcpu, kvm) {
6462 if (!vcpu->arch.pv_time.active)
6465 ret = kvm_set_guest_paused(vcpu);
6467 kvm_err("Failed to pause guest VCPU%d: %d\n",
6468 vcpu->vcpu_id, ret);
6472 mutex_unlock(&kvm->lock);
6474 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6477 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6480 case PM_HIBERNATION_PREPARE:
6481 case PM_SUSPEND_PREPARE:
6482 return kvm_arch_suspend_notifier(kvm);
6487 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6489 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6491 struct kvm_clock_data data = { 0 };
6493 get_kvmclock(kvm, &data);
6494 if (copy_to_user(argp, &data, sizeof(data)))
6500 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6502 struct kvm_arch *ka = &kvm->arch;
6503 struct kvm_clock_data data;
6506 if (copy_from_user(&data, argp, sizeof(data)))
6510 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6511 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6513 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6516 kvm_hv_request_tsc_page_update(kvm);
6517 kvm_start_pvclock_update(kvm);
6518 pvclock_update_vm_gtod_copy(kvm);
6521 * This pairs with kvm_guest_time_update(): when masterclock is
6522 * in use, we use master_kernel_ns + kvmclock_offset to set
6523 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6524 * is slightly ahead) here we risk going negative on unsigned
6525 * 'system_time' when 'data.clock' is very small.
6527 if (data.flags & KVM_CLOCK_REALTIME) {
6528 u64 now_real_ns = ktime_get_real_ns();
6531 * Avoid stepping the kvmclock backwards.
6533 if (now_real_ns > data.realtime)
6534 data.clock += now_real_ns - data.realtime;
6537 if (ka->use_master_clock)
6538 now_raw_ns = ka->master_kernel_ns;
6540 now_raw_ns = get_kvmclock_base_ns();
6541 ka->kvmclock_offset = data.clock - now_raw_ns;
6542 kvm_end_pvclock_update(kvm);
6546 long kvm_arch_vm_ioctl(struct file *filp,
6547 unsigned int ioctl, unsigned long arg)
6549 struct kvm *kvm = filp->private_data;
6550 void __user *argp = (void __user *)arg;
6553 * This union makes it completely explicit to gcc-3.x
6554 * that these two variables' stack usage should be
6555 * combined, not added together.
6558 struct kvm_pit_state ps;
6559 struct kvm_pit_state2 ps2;
6560 struct kvm_pit_config pit_config;
6564 case KVM_SET_TSS_ADDR:
6565 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6567 case KVM_SET_IDENTITY_MAP_ADDR: {
6570 mutex_lock(&kvm->lock);
6572 if (kvm->created_vcpus)
6573 goto set_identity_unlock;
6575 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6576 goto set_identity_unlock;
6577 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6578 set_identity_unlock:
6579 mutex_unlock(&kvm->lock);
6582 case KVM_SET_NR_MMU_PAGES:
6583 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6585 case KVM_GET_NR_MMU_PAGES:
6586 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
6588 case KVM_CREATE_IRQCHIP: {
6589 mutex_lock(&kvm->lock);
6592 if (irqchip_in_kernel(kvm))
6593 goto create_irqchip_unlock;
6596 if (kvm->created_vcpus)
6597 goto create_irqchip_unlock;
6599 r = kvm_pic_init(kvm);
6601 goto create_irqchip_unlock;
6603 r = kvm_ioapic_init(kvm);
6605 kvm_pic_destroy(kvm);
6606 goto create_irqchip_unlock;
6609 r = kvm_setup_default_irq_routing(kvm);
6611 kvm_ioapic_destroy(kvm);
6612 kvm_pic_destroy(kvm);
6613 goto create_irqchip_unlock;
6615 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6617 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
6618 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6619 create_irqchip_unlock:
6620 mutex_unlock(&kvm->lock);
6623 case KVM_CREATE_PIT:
6624 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
6626 case KVM_CREATE_PIT2:
6628 if (copy_from_user(&u.pit_config, argp,
6629 sizeof(struct kvm_pit_config)))
6632 mutex_lock(&kvm->lock);
6635 goto create_pit_unlock;
6637 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
6641 mutex_unlock(&kvm->lock);
6643 case KVM_GET_IRQCHIP: {
6644 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6645 struct kvm_irqchip *chip;
6647 chip = memdup_user(argp, sizeof(*chip));
6654 if (!irqchip_kernel(kvm))
6655 goto get_irqchip_out;
6656 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
6658 goto get_irqchip_out;
6660 if (copy_to_user(argp, chip, sizeof(*chip)))
6661 goto get_irqchip_out;
6667 case KVM_SET_IRQCHIP: {
6668 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6669 struct kvm_irqchip *chip;
6671 chip = memdup_user(argp, sizeof(*chip));
6678 if (!irqchip_kernel(kvm))
6679 goto set_irqchip_out;
6680 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
6687 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
6690 if (!kvm->arch.vpit)
6692 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
6696 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
6703 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
6705 mutex_lock(&kvm->lock);
6707 if (!kvm->arch.vpit)
6709 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
6711 mutex_unlock(&kvm->lock);
6714 case KVM_GET_PIT2: {
6716 if (!kvm->arch.vpit)
6718 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
6722 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
6727 case KVM_SET_PIT2: {
6729 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
6731 mutex_lock(&kvm->lock);
6733 if (!kvm->arch.vpit)
6735 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
6737 mutex_unlock(&kvm->lock);
6740 case KVM_REINJECT_CONTROL: {
6741 struct kvm_reinject_control control;
6743 if (copy_from_user(&control, argp, sizeof(control)))
6746 if (!kvm->arch.vpit)
6748 r = kvm_vm_ioctl_reinject(kvm, &control);
6751 case KVM_SET_BOOT_CPU_ID:
6753 mutex_lock(&kvm->lock);
6754 if (kvm->created_vcpus)
6757 kvm->arch.bsp_vcpu_id = arg;
6758 mutex_unlock(&kvm->lock);
6760 #ifdef CONFIG_KVM_XEN
6761 case KVM_XEN_HVM_CONFIG: {
6762 struct kvm_xen_hvm_config xhc;
6764 if (copy_from_user(&xhc, argp, sizeof(xhc)))
6766 r = kvm_xen_hvm_config(kvm, &xhc);
6769 case KVM_XEN_HVM_GET_ATTR: {
6770 struct kvm_xen_hvm_attr xha;
6773 if (copy_from_user(&xha, argp, sizeof(xha)))
6775 r = kvm_xen_hvm_get_attr(kvm, &xha);
6776 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
6780 case KVM_XEN_HVM_SET_ATTR: {
6781 struct kvm_xen_hvm_attr xha;
6784 if (copy_from_user(&xha, argp, sizeof(xha)))
6786 r = kvm_xen_hvm_set_attr(kvm, &xha);
6789 case KVM_XEN_HVM_EVTCHN_SEND: {
6790 struct kvm_irq_routing_xen_evtchn uxe;
6793 if (copy_from_user(&uxe, argp, sizeof(uxe)))
6795 r = kvm_xen_hvm_evtchn_send(kvm, &uxe);
6800 r = kvm_vm_ioctl_set_clock(kvm, argp);
6803 r = kvm_vm_ioctl_get_clock(kvm, argp);
6805 case KVM_SET_TSC_KHZ: {
6809 user_tsc_khz = (u32)arg;
6811 if (kvm_caps.has_tsc_control &&
6812 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
6815 if (user_tsc_khz == 0)
6816 user_tsc_khz = tsc_khz;
6818 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz);
6823 case KVM_GET_TSC_KHZ: {
6824 r = READ_ONCE(kvm->arch.default_tsc_khz);
6827 case KVM_MEMORY_ENCRYPT_OP: {
6829 if (!kvm_x86_ops.mem_enc_ioctl)
6832 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
6835 case KVM_MEMORY_ENCRYPT_REG_REGION: {
6836 struct kvm_enc_region region;
6839 if (copy_from_user(®ion, argp, sizeof(region)))
6843 if (!kvm_x86_ops.mem_enc_register_region)
6846 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
6849 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
6850 struct kvm_enc_region region;
6853 if (copy_from_user(®ion, argp, sizeof(region)))
6857 if (!kvm_x86_ops.mem_enc_unregister_region)
6860 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
6863 case KVM_HYPERV_EVENTFD: {
6864 struct kvm_hyperv_eventfd hvevfd;
6867 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
6869 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
6872 case KVM_SET_PMU_EVENT_FILTER:
6873 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
6875 case KVM_X86_SET_MSR_FILTER:
6876 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
6885 static void kvm_init_msr_list(void)
6890 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
6891 "Please update the fixed PMCs in msrs_to_saved_all[]");
6893 num_msrs_to_save = 0;
6894 num_emulated_msrs = 0;
6895 num_msr_based_features = 0;
6897 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
6898 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
6902 * Even MSRs that are valid in the host may not be exposed
6903 * to the guests in some cases.
6905 switch (msrs_to_save_all[i]) {
6906 case MSR_IA32_BNDCFGS:
6907 if (!kvm_mpx_supported())
6911 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
6912 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
6915 case MSR_IA32_UMWAIT_CONTROL:
6916 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
6919 case MSR_IA32_RTIT_CTL:
6920 case MSR_IA32_RTIT_STATUS:
6921 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
6924 case MSR_IA32_RTIT_CR3_MATCH:
6925 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6926 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
6929 case MSR_IA32_RTIT_OUTPUT_BASE:
6930 case MSR_IA32_RTIT_OUTPUT_MASK:
6931 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6932 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
6933 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
6936 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
6937 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6938 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
6939 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
6942 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
6943 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
6944 min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
6947 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
6948 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
6949 min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
6953 case MSR_IA32_XFD_ERR:
6954 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
6961 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
6964 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
6965 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
6968 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
6971 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
6972 struct kvm_msr_entry msr;
6974 msr.index = msr_based_features_all[i];
6975 if (kvm_get_msr_feature(&msr))
6978 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
6982 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
6990 if (!(lapic_in_kernel(vcpu) &&
6991 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
6992 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
7003 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
7010 if (!(lapic_in_kernel(vcpu) &&
7011 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
7013 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
7015 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
7025 static void kvm_set_segment(struct kvm_vcpu *vcpu,
7026 struct kvm_segment *var, int seg)
7028 static_call(kvm_x86_set_segment)(vcpu, var, seg);
7031 void kvm_get_segment(struct kvm_vcpu *vcpu,
7032 struct kvm_segment *var, int seg)
7034 static_call(kvm_x86_get_segment)(vcpu, var, seg);
7037 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
7038 struct x86_exception *exception)
7040 struct kvm_mmu *mmu = vcpu->arch.mmu;
7043 BUG_ON(!mmu_is_nested(vcpu));
7045 /* NPT walks are always user-walks */
7046 access |= PFERR_USER_MASK;
7047 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
7052 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
7053 struct x86_exception *exception)
7055 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7057 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7058 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7060 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
7062 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
7063 struct x86_exception *exception)
7065 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7067 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7068 access |= PFERR_FETCH_MASK;
7069 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7072 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
7073 struct x86_exception *exception)
7075 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7077 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7078 access |= PFERR_WRITE_MASK;
7079 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7081 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
7083 /* uses this to access any guest's mapped memory without checking CPL */
7084 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
7085 struct x86_exception *exception)
7087 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7089 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
7092 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7093 struct kvm_vcpu *vcpu, u64 access,
7094 struct x86_exception *exception)
7096 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7098 int r = X86EMUL_CONTINUE;
7101 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7102 unsigned offset = addr & (PAGE_SIZE-1);
7103 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
7106 if (gpa == INVALID_GPA)
7107 return X86EMUL_PROPAGATE_FAULT;
7108 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
7111 r = X86EMUL_IO_NEEDED;
7123 /* used for instruction fetching */
7124 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
7125 gva_t addr, void *val, unsigned int bytes,
7126 struct x86_exception *exception)
7128 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7129 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7130 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7134 /* Inline kvm_read_guest_virt_helper for speed. */
7135 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
7137 if (unlikely(gpa == INVALID_GPA))
7138 return X86EMUL_PROPAGATE_FAULT;
7140 offset = addr & (PAGE_SIZE-1);
7141 if (WARN_ON(offset + bytes > PAGE_SIZE))
7142 bytes = (unsigned)PAGE_SIZE - offset;
7143 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
7145 if (unlikely(ret < 0))
7146 return X86EMUL_IO_NEEDED;
7148 return X86EMUL_CONTINUE;
7151 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
7152 gva_t addr, void *val, unsigned int bytes,
7153 struct x86_exception *exception)
7155 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7158 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
7159 * is returned, but our callers are not ready for that and they blindly
7160 * call kvm_inject_page_fault. Ensure that they at least do not leak
7161 * uninitialized kernel stack memory into cr2 and error code.
7163 memset(exception, 0, sizeof(*exception));
7164 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
7167 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
7169 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
7170 gva_t addr, void *val, unsigned int bytes,
7171 struct x86_exception *exception, bool system)
7173 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7177 access |= PFERR_IMPLICIT_ACCESS;
7178 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7179 access |= PFERR_USER_MASK;
7181 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
7184 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
7185 unsigned long addr, void *val, unsigned int bytes)
7187 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7188 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
7190 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
7193 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7194 struct kvm_vcpu *vcpu, u64 access,
7195 struct x86_exception *exception)
7197 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7199 int r = X86EMUL_CONTINUE;
7202 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7203 unsigned offset = addr & (PAGE_SIZE-1);
7204 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
7207 if (gpa == INVALID_GPA)
7208 return X86EMUL_PROPAGATE_FAULT;
7209 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
7211 r = X86EMUL_IO_NEEDED;
7223 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
7224 unsigned int bytes, struct x86_exception *exception,
7227 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7228 u64 access = PFERR_WRITE_MASK;
7231 access |= PFERR_IMPLICIT_ACCESS;
7232 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7233 access |= PFERR_USER_MASK;
7235 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7239 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
7240 unsigned int bytes, struct x86_exception *exception)
7242 /* kvm_write_guest_virt_system can pull in tons of pages. */
7243 vcpu->arch.l1tf_flush_l1d = true;
7245 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7246 PFERR_WRITE_MASK, exception);
7248 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
7250 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
7251 void *insn, int insn_len)
7253 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type,
7257 int handle_ud(struct kvm_vcpu *vcpu)
7259 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
7260 int emul_type = EMULTYPE_TRAP_UD;
7261 char sig[5]; /* ud2; .ascii "kvm" */
7262 struct x86_exception e;
7264 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0)))
7267 if (force_emulation_prefix &&
7268 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
7269 sig, sizeof(sig), &e) == 0 &&
7270 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
7271 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
7272 emul_type = EMULTYPE_TRAP_UD_FORCED;
7275 return kvm_emulate_instruction(vcpu, emul_type);
7277 EXPORT_SYMBOL_GPL(handle_ud);
7279 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7280 gpa_t gpa, bool write)
7282 /* For APIC access vmexit */
7283 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7286 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
7287 trace_vcpu_match_mmio(gva, gpa, write, true);
7294 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7295 gpa_t *gpa, struct x86_exception *exception,
7298 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7299 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7300 | (write ? PFERR_WRITE_MASK : 0);
7303 * currently PKRU is only applied to ept enabled guest so
7304 * there is no pkey in EPT page table for L1 guest or EPT
7305 * shadow page table for L2 guest.
7307 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7308 !permission_fault(vcpu, vcpu->arch.walk_mmu,
7309 vcpu->arch.mmio_access, 0, access))) {
7310 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7311 (gva & (PAGE_SIZE - 1));
7312 trace_vcpu_match_mmio(gva, *gpa, write, false);
7316 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7318 if (*gpa == INVALID_GPA)
7321 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7324 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7325 const void *val, int bytes)
7329 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7332 kvm_page_track_write(vcpu, gpa, val, bytes);
7336 struct read_write_emulator_ops {
7337 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7339 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7340 void *val, int bytes);
7341 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7342 int bytes, void *val);
7343 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7344 void *val, int bytes);
7348 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7350 if (vcpu->mmio_read_completed) {
7351 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7352 vcpu->mmio_fragments[0].gpa, val);
7353 vcpu->mmio_read_completed = 0;
7360 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7361 void *val, int bytes)
7363 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7366 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7367 void *val, int bytes)
7369 return emulator_write_phys(vcpu, gpa, val, bytes);
7372 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7374 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7375 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7378 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7379 void *val, int bytes)
7381 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7382 return X86EMUL_IO_NEEDED;
7385 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7386 void *val, int bytes)
7388 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7390 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7391 return X86EMUL_CONTINUE;
7394 static const struct read_write_emulator_ops read_emultor = {
7395 .read_write_prepare = read_prepare,
7396 .read_write_emulate = read_emulate,
7397 .read_write_mmio = vcpu_mmio_read,
7398 .read_write_exit_mmio = read_exit_mmio,
7401 static const struct read_write_emulator_ops write_emultor = {
7402 .read_write_emulate = write_emulate,
7403 .read_write_mmio = write_mmio,
7404 .read_write_exit_mmio = write_exit_mmio,
7408 static int emulator_read_write_onepage(unsigned long addr, void *val,
7410 struct x86_exception *exception,
7411 struct kvm_vcpu *vcpu,
7412 const struct read_write_emulator_ops *ops)
7416 bool write = ops->write;
7417 struct kvm_mmio_fragment *frag;
7418 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7421 * If the exit was due to a NPF we may already have a GPA.
7422 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7423 * Note, this cannot be used on string operations since string
7424 * operation using rep will only have the initial GPA from the NPF
7427 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7428 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7429 gpa = ctxt->gpa_val;
7430 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7432 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7434 return X86EMUL_PROPAGATE_FAULT;
7437 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7438 return X86EMUL_CONTINUE;
7441 * Is this MMIO handled locally?
7443 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7444 if (handled == bytes)
7445 return X86EMUL_CONTINUE;
7451 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7452 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7456 return X86EMUL_CONTINUE;
7459 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7461 void *val, unsigned int bytes,
7462 struct x86_exception *exception,
7463 const struct read_write_emulator_ops *ops)
7465 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7469 if (ops->read_write_prepare &&
7470 ops->read_write_prepare(vcpu, val, bytes))
7471 return X86EMUL_CONTINUE;
7473 vcpu->mmio_nr_fragments = 0;
7475 /* Crossing a page boundary? */
7476 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7479 now = -addr & ~PAGE_MASK;
7480 rc = emulator_read_write_onepage(addr, val, now, exception,
7483 if (rc != X86EMUL_CONTINUE)
7486 if (ctxt->mode != X86EMUL_MODE_PROT64)
7492 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7494 if (rc != X86EMUL_CONTINUE)
7497 if (!vcpu->mmio_nr_fragments)
7500 gpa = vcpu->mmio_fragments[0].gpa;
7502 vcpu->mmio_needed = 1;
7503 vcpu->mmio_cur_fragment = 0;
7505 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7506 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7507 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7508 vcpu->run->mmio.phys_addr = gpa;
7510 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7513 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7517 struct x86_exception *exception)
7519 return emulator_read_write(ctxt, addr, val, bytes,
7520 exception, &read_emultor);
7523 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7527 struct x86_exception *exception)
7529 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7530 exception, &write_emultor);
7533 #define emulator_try_cmpxchg_user(t, ptr, old, new) \
7534 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t))
7536 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7541 struct x86_exception *exception)
7543 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7549 /* guests cmpxchg8b have to be emulated atomically */
7550 if (bytes > 8 || (bytes & (bytes - 1)))
7553 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7555 if (gpa == INVALID_GPA ||
7556 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7560 * Emulate the atomic as a straight write to avoid #AC if SLD is
7561 * enabled in the host and the access splits a cache line.
7563 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7564 page_line_mask = ~(cache_line_size() - 1);
7566 page_line_mask = PAGE_MASK;
7568 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7571 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa));
7572 if (kvm_is_error_hva(hva))
7575 hva += offset_in_page(gpa);
7579 r = emulator_try_cmpxchg_user(u8, hva, old, new);
7582 r = emulator_try_cmpxchg_user(u16, hva, old, new);
7585 r = emulator_try_cmpxchg_user(u32, hva, old, new);
7588 r = emulator_try_cmpxchg_user(u64, hva, old, new);
7595 return X86EMUL_UNHANDLEABLE;
7597 return X86EMUL_CMPXCHG_FAILED;
7599 kvm_page_track_write(vcpu, gpa, new, bytes);
7601 return X86EMUL_CONTINUE;
7604 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
7606 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
7609 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
7610 unsigned short port, void *data,
7611 unsigned int count, bool in)
7616 WARN_ON_ONCE(vcpu->arch.pio.count);
7617 for (i = 0; i < count; i++) {
7619 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data);
7621 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data);
7628 * Userspace must have unregistered the device while PIO
7629 * was running. Drop writes / read as 0.
7632 memset(data, 0, size * (count - i));
7641 vcpu->arch.pio.port = port;
7642 vcpu->arch.pio.in = in;
7643 vcpu->arch.pio.count = count;
7644 vcpu->arch.pio.size = size;
7647 memset(vcpu->arch.pio_data, 0, size * count);
7649 memcpy(vcpu->arch.pio_data, data, size * count);
7651 vcpu->run->exit_reason = KVM_EXIT_IO;
7652 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
7653 vcpu->run->io.size = size;
7654 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
7655 vcpu->run->io.count = count;
7656 vcpu->run->io.port = port;
7660 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7661 unsigned short port, void *val, unsigned int count)
7663 int r = emulator_pio_in_out(vcpu, size, port, val, count, true);
7665 trace_kvm_pio(KVM_PIO_IN, port, size, count, val);
7670 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
7672 int size = vcpu->arch.pio.size;
7673 unsigned int count = vcpu->arch.pio.count;
7674 memcpy(val, vcpu->arch.pio_data, size * count);
7675 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
7676 vcpu->arch.pio.count = 0;
7679 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
7680 int size, unsigned short port, void *val,
7683 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7684 if (vcpu->arch.pio.count) {
7686 * Complete a previous iteration that required userspace I/O.
7687 * Note, @count isn't guaranteed to match pio.count as userspace
7688 * can modify ECX before rerunning the vCPU. Ignore any such
7689 * shenanigans as KVM doesn't support modifying the rep count,
7690 * and the emulator ensures @count doesn't overflow the buffer.
7692 complete_emulator_pio_in(vcpu, val);
7696 return emulator_pio_in(vcpu, size, port, val, count);
7699 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
7700 unsigned short port, const void *val,
7703 trace_kvm_pio(KVM_PIO_OUT, port, size, count, val);
7704 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
7707 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
7708 int size, unsigned short port,
7709 const void *val, unsigned int count)
7711 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
7714 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
7716 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
7719 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
7721 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
7724 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
7726 if (!need_emulate_wbinvd(vcpu))
7727 return X86EMUL_CONTINUE;
7729 if (static_call(kvm_x86_has_wbinvd_exit)()) {
7730 int cpu = get_cpu();
7732 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
7733 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
7734 wbinvd_ipi, NULL, 1);
7736 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
7739 return X86EMUL_CONTINUE;
7742 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
7744 kvm_emulate_wbinvd_noskip(vcpu);
7745 return kvm_skip_emulated_instruction(vcpu);
7747 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
7751 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
7753 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
7756 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
7757 unsigned long *dest)
7759 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
7762 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
7763 unsigned long value)
7766 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
7769 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
7771 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
7774 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
7776 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7777 unsigned long value;
7781 value = kvm_read_cr0(vcpu);
7784 value = vcpu->arch.cr2;
7787 value = kvm_read_cr3(vcpu);
7790 value = kvm_read_cr4(vcpu);
7793 value = kvm_get_cr8(vcpu);
7796 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7803 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
7805 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7810 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
7813 vcpu->arch.cr2 = val;
7816 res = kvm_set_cr3(vcpu, val);
7819 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
7822 res = kvm_set_cr8(vcpu, val);
7825 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7832 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
7834 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
7837 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7839 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
7842 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7844 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
7847 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7849 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
7852 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7854 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
7857 static unsigned long emulator_get_cached_segment_base(
7858 struct x86_emulate_ctxt *ctxt, int seg)
7860 return get_segment_base(emul_to_vcpu(ctxt), seg);
7863 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
7864 struct desc_struct *desc, u32 *base3,
7867 struct kvm_segment var;
7869 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
7870 *selector = var.selector;
7873 memset(desc, 0, sizeof(*desc));
7881 set_desc_limit(desc, var.limit);
7882 set_desc_base(desc, (unsigned long)var.base);
7883 #ifdef CONFIG_X86_64
7885 *base3 = var.base >> 32;
7887 desc->type = var.type;
7889 desc->dpl = var.dpl;
7890 desc->p = var.present;
7891 desc->avl = var.avl;
7899 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
7900 struct desc_struct *desc, u32 base3,
7903 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7904 struct kvm_segment var;
7906 var.selector = selector;
7907 var.base = get_desc_base(desc);
7908 #ifdef CONFIG_X86_64
7909 var.base |= ((u64)base3) << 32;
7911 var.limit = get_desc_limit(desc);
7913 var.limit = (var.limit << 12) | 0xfff;
7914 var.type = desc->type;
7915 var.dpl = desc->dpl;
7920 var.avl = desc->avl;
7921 var.present = desc->p;
7922 var.unusable = !var.present;
7925 kvm_set_segment(vcpu, &var, seg);
7929 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
7930 u32 msr_index, u64 *pdata)
7932 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7935 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
7937 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
7938 complete_emulated_rdmsr, r)) {
7939 /* Bounce to user space */
7940 return X86EMUL_IO_NEEDED;
7946 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
7947 u32 msr_index, u64 data)
7949 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7952 r = kvm_set_msr_with_filter(vcpu, msr_index, data);
7954 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
7955 complete_emulated_msr_access, r)) {
7956 /* Bounce to user space */
7957 return X86EMUL_IO_NEEDED;
7963 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
7964 u32 msr_index, u64 *pdata)
7966 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
7969 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
7970 u32 msr_index, u64 data)
7972 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
7975 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
7977 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7979 return vcpu->arch.smbase;
7982 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
7984 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7986 vcpu->arch.smbase = smbase;
7989 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
7992 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
7997 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
7998 u32 pmc, u64 *pdata)
8000 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
8003 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
8005 emul_to_vcpu(ctxt)->arch.halt_request = 1;
8008 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8009 struct x86_instruction_info *info,
8010 enum x86_intercept_stage stage)
8012 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
8016 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
8017 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
8020 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
8023 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
8025 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
8028 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
8030 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
8033 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
8035 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
8038 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
8040 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
8043 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
8045 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
8048 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
8050 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
8053 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
8055 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
8058 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
8060 return emul_to_vcpu(ctxt)->arch.hflags;
8063 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt)
8065 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8067 kvm_smm_changed(vcpu, false);
8070 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt,
8071 const char *smstate)
8073 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate);
8076 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
8078 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
8081 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
8083 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
8086 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt)
8088 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm;
8090 if (!kvm->vm_bugged)
8094 static const struct x86_emulate_ops emulate_ops = {
8095 .vm_bugged = emulator_vm_bugged,
8096 .read_gpr = emulator_read_gpr,
8097 .write_gpr = emulator_write_gpr,
8098 .read_std = emulator_read_std,
8099 .write_std = emulator_write_std,
8100 .read_phys = kvm_read_guest_phys_system,
8101 .fetch = kvm_fetch_guest_virt,
8102 .read_emulated = emulator_read_emulated,
8103 .write_emulated = emulator_write_emulated,
8104 .cmpxchg_emulated = emulator_cmpxchg_emulated,
8105 .invlpg = emulator_invlpg,
8106 .pio_in_emulated = emulator_pio_in_emulated,
8107 .pio_out_emulated = emulator_pio_out_emulated,
8108 .get_segment = emulator_get_segment,
8109 .set_segment = emulator_set_segment,
8110 .get_cached_segment_base = emulator_get_cached_segment_base,
8111 .get_gdt = emulator_get_gdt,
8112 .get_idt = emulator_get_idt,
8113 .set_gdt = emulator_set_gdt,
8114 .set_idt = emulator_set_idt,
8115 .get_cr = emulator_get_cr,
8116 .set_cr = emulator_set_cr,
8117 .cpl = emulator_get_cpl,
8118 .get_dr = emulator_get_dr,
8119 .set_dr = emulator_set_dr,
8120 .get_smbase = emulator_get_smbase,
8121 .set_smbase = emulator_set_smbase,
8122 .set_msr_with_filter = emulator_set_msr_with_filter,
8123 .get_msr_with_filter = emulator_get_msr_with_filter,
8124 .set_msr = emulator_set_msr,
8125 .get_msr = emulator_get_msr,
8126 .check_pmc = emulator_check_pmc,
8127 .read_pmc = emulator_read_pmc,
8128 .halt = emulator_halt,
8129 .wbinvd = emulator_wbinvd,
8130 .fix_hypercall = emulator_fix_hypercall,
8131 .intercept = emulator_intercept,
8132 .get_cpuid = emulator_get_cpuid,
8133 .guest_has_long_mode = emulator_guest_has_long_mode,
8134 .guest_has_movbe = emulator_guest_has_movbe,
8135 .guest_has_fxsr = emulator_guest_has_fxsr,
8136 .guest_has_rdpid = emulator_guest_has_rdpid,
8137 .set_nmi_mask = emulator_set_nmi_mask,
8138 .get_hflags = emulator_get_hflags,
8139 .exiting_smm = emulator_exiting_smm,
8140 .leave_smm = emulator_leave_smm,
8141 .triple_fault = emulator_triple_fault,
8142 .set_xcr = emulator_set_xcr,
8145 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
8147 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8149 * an sti; sti; sequence only disable interrupts for the first
8150 * instruction. So, if the last instruction, be it emulated or
8151 * not, left the system with the INT_STI flag enabled, it
8152 * means that the last instruction is an sti. We should not
8153 * leave the flag on in this case. The same goes for mov ss
8155 if (int_shadow & mask)
8157 if (unlikely(int_shadow || mask)) {
8158 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
8160 kvm_make_request(KVM_REQ_EVENT, vcpu);
8164 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
8166 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8167 if (ctxt->exception.vector == PF_VECTOR)
8168 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
8170 if (ctxt->exception.error_code_valid)
8171 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
8172 ctxt->exception.error_code);
8174 kvm_queue_exception(vcpu, ctxt->exception.vector);
8178 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
8180 struct x86_emulate_ctxt *ctxt;
8182 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
8184 pr_err("kvm: failed to allocate vcpu's emulator\n");
8189 ctxt->ops = &emulate_ops;
8190 vcpu->arch.emulate_ctxt = ctxt;
8195 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
8197 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8200 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
8202 ctxt->gpa_available = false;
8203 ctxt->eflags = kvm_get_rflags(vcpu);
8204 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
8206 ctxt->eip = kvm_rip_read(vcpu);
8207 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
8208 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
8209 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
8210 cs_db ? X86EMUL_MODE_PROT32 :
8211 X86EMUL_MODE_PROT16;
8212 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
8213 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
8214 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
8216 ctxt->interruptibility = 0;
8217 ctxt->have_exception = false;
8218 ctxt->exception.vector = -1;
8219 ctxt->perm_ok = false;
8221 init_decode_cache(ctxt);
8222 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8225 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
8227 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8230 init_emulate_ctxt(vcpu);
8234 ctxt->_eip = ctxt->eip + inc_eip;
8235 ret = emulate_int_real(ctxt, irq);
8237 if (ret != X86EMUL_CONTINUE) {
8238 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8240 ctxt->eip = ctxt->_eip;
8241 kvm_rip_write(vcpu, ctxt->eip);
8242 kvm_set_rflags(vcpu, ctxt->eflags);
8245 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
8247 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8248 u8 ndata, u8 *insn_bytes, u8 insn_size)
8250 struct kvm_run *run = vcpu->run;
8255 * Zero the whole array used to retrieve the exit info, as casting to
8256 * u32 for select entries will leave some chunks uninitialized.
8258 memset(&info, 0, sizeof(info));
8260 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
8261 &info[2], (u32 *)&info[3],
8264 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8265 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
8268 * There's currently space for 13 entries, but 5 are used for the exit
8269 * reason and info. Restrict to 4 to reduce the maintenance burden
8270 * when expanding kvm_run.emulation_failure in the future.
8272 if (WARN_ON_ONCE(ndata > 4))
8275 /* Always include the flags as a 'data' entry. */
8277 run->emulation_failure.flags = 0;
8280 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
8281 sizeof(run->emulation_failure.insn_bytes) != 16));
8283 run->emulation_failure.flags |=
8284 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
8285 run->emulation_failure.insn_size = insn_size;
8286 memset(run->emulation_failure.insn_bytes, 0x90,
8287 sizeof(run->emulation_failure.insn_bytes));
8288 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
8291 memcpy(&run->internal.data[info_start], info, sizeof(info));
8292 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
8293 ndata * sizeof(data[0]));
8295 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8298 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8300 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8302 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8303 ctxt->fetch.end - ctxt->fetch.data);
8306 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8309 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8311 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8313 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8315 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8317 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8319 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8321 struct kvm *kvm = vcpu->kvm;
8323 ++vcpu->stat.insn_emulation_fail;
8324 trace_kvm_emulate_insn_failed(vcpu);
8326 if (emulation_type & EMULTYPE_VMWARE_GP) {
8327 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8331 if (kvm->arch.exit_on_emulation_error ||
8332 (emulation_type & EMULTYPE_SKIP)) {
8333 prepare_emulation_ctxt_failure_exit(vcpu);
8337 kvm_queue_exception(vcpu, UD_VECTOR);
8339 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8340 prepare_emulation_ctxt_failure_exit(vcpu);
8347 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8348 bool write_fault_to_shadow_pgtable,
8351 gpa_t gpa = cr2_or_gpa;
8354 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8357 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8358 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8361 if (!vcpu->arch.mmu->root_role.direct) {
8363 * Write permission should be allowed since only
8364 * write access need to be emulated.
8366 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8369 * If the mapping is invalid in guest, let cpu retry
8370 * it to generate fault.
8372 if (gpa == INVALID_GPA)
8377 * Do not retry the unhandleable instruction if it faults on the
8378 * readonly host memory, otherwise it will goto a infinite loop:
8379 * retry instruction -> write #PF -> emulation fail -> retry
8380 * instruction -> ...
8382 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8385 * If the instruction failed on the error pfn, it can not be fixed,
8386 * report the error to userspace.
8388 if (is_error_noslot_pfn(pfn))
8391 kvm_release_pfn_clean(pfn);
8393 /* The instructions are well-emulated on direct mmu. */
8394 if (vcpu->arch.mmu->root_role.direct) {
8395 unsigned int indirect_shadow_pages;
8397 write_lock(&vcpu->kvm->mmu_lock);
8398 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8399 write_unlock(&vcpu->kvm->mmu_lock);
8401 if (indirect_shadow_pages)
8402 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8408 * if emulation was due to access to shadowed page table
8409 * and it failed try to unshadow page and re-enter the
8410 * guest to let CPU execute the instruction.
8412 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8415 * If the access faults on its page table, it can not
8416 * be fixed by unprotecting shadow page and it should
8417 * be reported to userspace.
8419 return !write_fault_to_shadow_pgtable;
8422 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8423 gpa_t cr2_or_gpa, int emulation_type)
8425 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8426 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8428 last_retry_eip = vcpu->arch.last_retry_eip;
8429 last_retry_addr = vcpu->arch.last_retry_addr;
8432 * If the emulation is caused by #PF and it is non-page_table
8433 * writing instruction, it means the VM-EXIT is caused by shadow
8434 * page protected, we can zap the shadow page and retry this
8435 * instruction directly.
8437 * Note: if the guest uses a non-page-table modifying instruction
8438 * on the PDE that points to the instruction, then we will unmap
8439 * the instruction and go to an infinite loop. So, we cache the
8440 * last retried eip and the last fault address, if we meet the eip
8441 * and the address again, we can break out of the potential infinite
8444 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8446 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8449 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8450 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8453 if (x86_page_table_writing_insn(ctxt))
8456 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8459 vcpu->arch.last_retry_eip = ctxt->eip;
8460 vcpu->arch.last_retry_addr = cr2_or_gpa;
8462 if (!vcpu->arch.mmu->root_role.direct)
8463 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8465 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8470 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8471 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8473 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm)
8475 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm);
8478 vcpu->arch.hflags |= HF_SMM_MASK;
8480 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK);
8482 /* Process a latched INIT or SMI, if any. */
8483 kvm_make_request(KVM_REQ_EVENT, vcpu);
8486 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band,
8487 * on SMM exit we still need to reload them from
8490 vcpu->arch.pdptrs_from_userspace = false;
8493 kvm_mmu_reset_context(vcpu);
8496 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8505 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8506 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8511 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8513 struct kvm_run *kvm_run = vcpu->run;
8515 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8516 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8517 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8518 kvm_run->debug.arch.exception = DB_VECTOR;
8519 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8522 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8526 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8528 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8531 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8535 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8538 * rflags is the old, "raw" value of the flags. The new value has
8539 * not been saved yet.
8541 * This is correct even for TF set by the guest, because "the
8542 * processor will not generate this exception after the instruction
8543 * that sets the TF flag".
8545 if (unlikely(rflags & X86_EFLAGS_TF))
8546 r = kvm_vcpu_do_singlestep(vcpu);
8549 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8551 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu, int *r)
8553 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8554 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8555 struct kvm_run *kvm_run = vcpu->run;
8556 unsigned long eip = kvm_get_linear_rip(vcpu);
8557 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8558 vcpu->arch.guest_debug_dr7,
8562 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8563 kvm_run->debug.arch.pc = eip;
8564 kvm_run->debug.arch.exception = DB_VECTOR;
8565 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8571 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8572 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
8573 unsigned long eip = kvm_get_linear_rip(vcpu);
8574 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8579 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
8588 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
8590 switch (ctxt->opcode_len) {
8597 case 0xe6: /* OUT */
8601 case 0x6c: /* INS */
8603 case 0x6e: /* OUTS */
8610 case 0x33: /* RDPMC */
8620 * Decode an instruction for emulation. The caller is responsible for handling
8621 * code breakpoints. Note, manually detecting code breakpoints is unnecessary
8622 * (and wrong) when emulating on an intercepted fault-like exception[*], as
8623 * code breakpoints have higher priority and thus have already been done by
8626 * [*] Except #MC, which is higher priority, but KVM should never emulate in
8627 * response to a machine check.
8629 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
8630 void *insn, int insn_len)
8632 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8635 init_emulate_ctxt(vcpu);
8637 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
8639 trace_kvm_emulate_insn_start(vcpu);
8640 ++vcpu->stat.insn_emulation;
8644 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
8646 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8647 int emulation_type, void *insn, int insn_len)
8650 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8651 bool writeback = true;
8652 bool write_fault_to_spt;
8654 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len)))
8657 vcpu->arch.l1tf_flush_l1d = true;
8660 * Clear write_fault_to_shadow_pgtable here to ensure it is
8663 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
8664 vcpu->arch.write_fault_to_shadow_pgtable = false;
8666 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8667 kvm_clear_exception_queue(vcpu);
8670 * Return immediately if RIP hits a code breakpoint, such #DBs
8671 * are fault-like and are higher priority than any faults on
8672 * the code fetch itself.
8674 if (!(emulation_type & EMULTYPE_SKIP) &&
8675 kvm_vcpu_check_code_breakpoint(vcpu, &r))
8678 r = x86_decode_emulated_instruction(vcpu, emulation_type,
8680 if (r != EMULATION_OK) {
8681 if ((emulation_type & EMULTYPE_TRAP_UD) ||
8682 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
8683 kvm_queue_exception(vcpu, UD_VECTOR);
8686 if (reexecute_instruction(vcpu, cr2_or_gpa,
8690 if (ctxt->have_exception) {
8692 * #UD should result in just EMULATION_FAILED, and trap-like
8693 * exception should not be encountered during decode.
8695 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
8696 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8697 inject_emulated_exception(vcpu);
8700 return handle_emulation_failure(vcpu, emulation_type);
8704 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
8705 !is_vmware_backdoor_opcode(ctxt)) {
8706 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8711 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
8712 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
8713 * The caller is responsible for updating interruptibility state and
8714 * injecting single-step #DBs.
8716 if (emulation_type & EMULTYPE_SKIP) {
8717 if (ctxt->mode != X86EMUL_MODE_PROT64)
8718 ctxt->eip = (u32)ctxt->_eip;
8720 ctxt->eip = ctxt->_eip;
8722 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
8727 kvm_rip_write(vcpu, ctxt->eip);
8728 if (ctxt->eflags & X86_EFLAGS_RF)
8729 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
8733 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
8736 /* this is needed for vmware backdoor interface to work since it
8737 changes registers values during IO operation */
8738 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
8739 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8740 emulator_invalidate_register_cache(ctxt);
8744 if (emulation_type & EMULTYPE_PF) {
8745 /* Save the faulting GPA (cr2) in the address field */
8746 ctxt->exception.address = cr2_or_gpa;
8748 /* With shadow page tables, cr2 contains a GVA or nGPA. */
8749 if (vcpu->arch.mmu->root_role.direct) {
8750 ctxt->gpa_available = true;
8751 ctxt->gpa_val = cr2_or_gpa;
8754 /* Sanitize the address out of an abundance of paranoia. */
8755 ctxt->exception.address = 0;
8758 r = x86_emulate_insn(ctxt);
8760 if (r == EMULATION_INTERCEPTED)
8763 if (r == EMULATION_FAILED) {
8764 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
8768 return handle_emulation_failure(vcpu, emulation_type);
8771 if (ctxt->have_exception) {
8773 if (inject_emulated_exception(vcpu))
8775 } else if (vcpu->arch.pio.count) {
8776 if (!vcpu->arch.pio.in) {
8777 /* FIXME: return into emulator if single-stepping. */
8778 vcpu->arch.pio.count = 0;
8781 vcpu->arch.complete_userspace_io = complete_emulated_pio;
8784 } else if (vcpu->mmio_needed) {
8785 ++vcpu->stat.mmio_exits;
8787 if (!vcpu->mmio_is_write)
8790 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8791 } else if (vcpu->arch.complete_userspace_io) {
8794 } else if (r == EMULATION_RESTART)
8801 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8802 toggle_interruptibility(vcpu, ctxt->interruptibility);
8803 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8804 if (!ctxt->have_exception ||
8805 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
8806 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8807 if (ctxt->is_branch)
8808 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
8809 kvm_rip_write(vcpu, ctxt->eip);
8810 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
8811 r = kvm_vcpu_do_singlestep(vcpu);
8812 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
8813 __kvm_set_rflags(vcpu, ctxt->eflags);
8817 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
8818 * do nothing, and it will be requested again as soon as
8819 * the shadow expires. But we still need to check here,
8820 * because POPF has no interrupt shadow.
8822 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
8823 kvm_make_request(KVM_REQ_EVENT, vcpu);
8825 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
8830 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
8832 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
8834 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
8836 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
8837 void *insn, int insn_len)
8839 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
8841 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
8843 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
8845 vcpu->arch.pio.count = 0;
8849 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
8851 vcpu->arch.pio.count = 0;
8853 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
8856 return kvm_skip_emulated_instruction(vcpu);
8859 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
8860 unsigned short port)
8862 unsigned long val = kvm_rax_read(vcpu);
8863 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
8869 * Workaround userspace that relies on old KVM behavior of %rip being
8870 * incremented prior to exiting to userspace to handle "OUT 0x7e".
8873 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
8874 vcpu->arch.complete_userspace_io =
8875 complete_fast_pio_out_port_0x7e;
8876 kvm_skip_emulated_instruction(vcpu);
8878 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8879 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
8884 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
8888 /* We should only ever be called with arch.pio.count equal to 1 */
8889 BUG_ON(vcpu->arch.pio.count != 1);
8891 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
8892 vcpu->arch.pio.count = 0;
8896 /* For size less than 4 we merge, else we zero extend */
8897 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8899 complete_emulator_pio_in(vcpu, &val);
8900 kvm_rax_write(vcpu, val);
8902 return kvm_skip_emulated_instruction(vcpu);
8905 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
8906 unsigned short port)
8911 /* For size less than 4 we merge, else we zero extend */
8912 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8914 ret = emulator_pio_in(vcpu, size, port, &val, 1);
8916 kvm_rax_write(vcpu, val);
8920 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8921 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
8926 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
8931 ret = kvm_fast_pio_in(vcpu, size, port);
8933 ret = kvm_fast_pio_out(vcpu, size, port);
8934 return ret && kvm_skip_emulated_instruction(vcpu);
8936 EXPORT_SYMBOL_GPL(kvm_fast_pio);
8938 static int kvmclock_cpu_down_prep(unsigned int cpu)
8940 __this_cpu_write(cpu_tsc_khz, 0);
8944 static void tsc_khz_changed(void *data)
8946 struct cpufreq_freqs *freq = data;
8947 unsigned long khz = 0;
8951 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
8952 khz = cpufreq_quick_get(raw_smp_processor_id());
8955 __this_cpu_write(cpu_tsc_khz, khz);
8958 #ifdef CONFIG_X86_64
8959 static void kvm_hyperv_tsc_notifier(void)
8964 mutex_lock(&kvm_lock);
8965 list_for_each_entry(kvm, &vm_list, vm_list)
8966 kvm_make_mclock_inprogress_request(kvm);
8968 /* no guest entries from this point */
8969 hyperv_stop_tsc_emulation();
8971 /* TSC frequency always matches when on Hyper-V */
8972 for_each_present_cpu(cpu)
8973 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
8974 kvm_caps.max_guest_tsc_khz = tsc_khz;
8976 list_for_each_entry(kvm, &vm_list, vm_list) {
8977 __kvm_start_pvclock_update(kvm);
8978 pvclock_update_vm_gtod_copy(kvm);
8979 kvm_end_pvclock_update(kvm);
8982 mutex_unlock(&kvm_lock);
8986 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
8989 struct kvm_vcpu *vcpu;
8994 * We allow guests to temporarily run on slowing clocks,
8995 * provided we notify them after, or to run on accelerating
8996 * clocks, provided we notify them before. Thus time never
8999 * However, we have a problem. We can't atomically update
9000 * the frequency of a given CPU from this function; it is
9001 * merely a notifier, which can be called from any CPU.
9002 * Changing the TSC frequency at arbitrary points in time
9003 * requires a recomputation of local variables related to
9004 * the TSC for each VCPU. We must flag these local variables
9005 * to be updated and be sure the update takes place with the
9006 * new frequency before any guests proceed.
9008 * Unfortunately, the combination of hotplug CPU and frequency
9009 * change creates an intractable locking scenario; the order
9010 * of when these callouts happen is undefined with respect to
9011 * CPU hotplug, and they can race with each other. As such,
9012 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
9013 * undefined; you can actually have a CPU frequency change take
9014 * place in between the computation of X and the setting of the
9015 * variable. To protect against this problem, all updates of
9016 * the per_cpu tsc_khz variable are done in an interrupt
9017 * protected IPI, and all callers wishing to update the value
9018 * must wait for a synchronous IPI to complete (which is trivial
9019 * if the caller is on the CPU already). This establishes the
9020 * necessary total order on variable updates.
9022 * Note that because a guest time update may take place
9023 * anytime after the setting of the VCPU's request bit, the
9024 * correct TSC value must be set before the request. However,
9025 * to ensure the update actually makes it to any guest which
9026 * starts running in hardware virtualization between the set
9027 * and the acquisition of the spinlock, we must also ping the
9028 * CPU after setting the request bit.
9032 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9034 mutex_lock(&kvm_lock);
9035 list_for_each_entry(kvm, &vm_list, vm_list) {
9036 kvm_for_each_vcpu(i, vcpu, kvm) {
9037 if (vcpu->cpu != cpu)
9039 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9040 if (vcpu->cpu != raw_smp_processor_id())
9044 mutex_unlock(&kvm_lock);
9046 if (freq->old < freq->new && send_ipi) {
9048 * We upscale the frequency. Must make the guest
9049 * doesn't see old kvmclock values while running with
9050 * the new frequency, otherwise we risk the guest sees
9051 * time go backwards.
9053 * In case we update the frequency for another cpu
9054 * (which might be in guest context) send an interrupt
9055 * to kick the cpu out of guest context. Next time
9056 * guest context is entered kvmclock will be updated,
9057 * so the guest will not see stale values.
9059 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9063 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
9066 struct cpufreq_freqs *freq = data;
9069 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
9071 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
9074 for_each_cpu(cpu, freq->policy->cpus)
9075 __kvmclock_cpufreq_notifier(freq, cpu);
9080 static struct notifier_block kvmclock_cpufreq_notifier_block = {
9081 .notifier_call = kvmclock_cpufreq_notifier
9084 static int kvmclock_cpu_online(unsigned int cpu)
9086 tsc_khz_changed(NULL);
9090 static void kvm_timer_init(void)
9092 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9093 max_tsc_khz = tsc_khz;
9095 if (IS_ENABLED(CONFIG_CPU_FREQ)) {
9096 struct cpufreq_policy *policy;
9100 policy = cpufreq_cpu_get(cpu);
9102 if (policy->cpuinfo.max_freq)
9103 max_tsc_khz = policy->cpuinfo.max_freq;
9104 cpufreq_cpu_put(policy);
9108 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
9109 CPUFREQ_TRANSITION_NOTIFIER);
9112 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
9113 kvmclock_cpu_online, kvmclock_cpu_down_prep);
9116 #ifdef CONFIG_X86_64
9117 static void pvclock_gtod_update_fn(struct work_struct *work)
9120 struct kvm_vcpu *vcpu;
9123 mutex_lock(&kvm_lock);
9124 list_for_each_entry(kvm, &vm_list, vm_list)
9125 kvm_for_each_vcpu(i, vcpu, kvm)
9126 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9127 atomic_set(&kvm_guest_has_master_clock, 0);
9128 mutex_unlock(&kvm_lock);
9131 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
9134 * Indirection to move queue_work() out of the tk_core.seq write held
9135 * region to prevent possible deadlocks against time accessors which
9136 * are invoked with work related locks held.
9138 static void pvclock_irq_work_fn(struct irq_work *w)
9140 queue_work(system_long_wq, &pvclock_gtod_work);
9143 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
9146 * Notification about pvclock gtod data update.
9148 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
9151 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
9152 struct timekeeper *tk = priv;
9154 update_pvclock_gtod(tk);
9157 * Disable master clock if host does not trust, or does not use,
9158 * TSC based clocksource. Delegate queue_work() to irq_work as
9159 * this is invoked with tk_core.seq write held.
9161 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
9162 atomic_read(&kvm_guest_has_master_clock) != 0)
9163 irq_work_queue(&pvclock_irq_work);
9167 static struct notifier_block pvclock_gtod_notifier = {
9168 .notifier_call = pvclock_gtod_notify,
9172 int kvm_arch_init(void *opaque)
9174 struct kvm_x86_init_ops *ops = opaque;
9178 if (kvm_x86_ops.hardware_enable) {
9179 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name);
9183 if (!ops->cpu_has_kvm_support()) {
9184 pr_err_ratelimited("kvm: no hardware support for '%s'\n",
9185 ops->runtime_ops->name);
9188 if (ops->disabled_by_bios()) {
9189 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n",
9190 ops->runtime_ops->name);
9195 * KVM explicitly assumes that the guest has an FPU and
9196 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
9197 * vCPU's FPU state as a fxregs_state struct.
9199 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
9200 printk(KERN_ERR "kvm: inadequate fpu\n");
9204 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9205 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
9210 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes
9211 * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something
9212 * other than WB. Note, EPT doesn't utilize the PAT, but don't bother
9213 * with an exception. PAT[0] is set to WB on RESET and also by the
9214 * kernel, i.e. failure indicates a kernel bug or broken firmware.
9216 if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) ||
9217 (host_pat & GENMASK(2, 0)) != 6) {
9218 pr_err("kvm: host PAT[0] is not WB\n");
9222 x86_emulator_cache = kvm_alloc_emulator_cache();
9223 if (!x86_emulator_cache) {
9224 pr_err("kvm: failed to allocate cache for x86 emulator\n");
9228 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
9229 if (!user_return_msrs) {
9230 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
9232 goto out_free_x86_emulator_cache;
9234 kvm_nr_uret_msrs = 0;
9236 r = kvm_mmu_vendor_module_init();
9238 goto out_free_percpu;
9242 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
9243 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
9244 kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
9247 if (pi_inject_timer == -1)
9248 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
9249 #ifdef CONFIG_X86_64
9250 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
9252 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9253 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
9259 free_percpu(user_return_msrs);
9260 out_free_x86_emulator_cache:
9261 kmem_cache_destroy(x86_emulator_cache);
9265 void kvm_arch_exit(void)
9267 #ifdef CONFIG_X86_64
9268 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9269 clear_hv_tscchange_cb();
9273 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
9274 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
9275 CPUFREQ_TRANSITION_NOTIFIER);
9276 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
9277 #ifdef CONFIG_X86_64
9278 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
9279 irq_work_sync(&pvclock_irq_work);
9280 cancel_work_sync(&pvclock_gtod_work);
9282 kvm_x86_ops.hardware_enable = NULL;
9283 kvm_mmu_vendor_module_exit();
9284 free_percpu(user_return_msrs);
9285 kmem_cache_destroy(x86_emulator_cache);
9286 #ifdef CONFIG_KVM_XEN
9287 static_key_deferred_flush(&kvm_xen_enabled);
9288 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
9292 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
9295 * The vCPU has halted, e.g. executed HLT. Update the run state if the
9296 * local APIC is in-kernel, the run loop will detect the non-runnable
9297 * state and halt the vCPU. Exit to userspace if the local APIC is
9298 * managed by userspace, in which case userspace is responsible for
9299 * handling wake events.
9301 ++vcpu->stat.halt_exits;
9302 if (lapic_in_kernel(vcpu)) {
9303 vcpu->arch.mp_state = state;
9306 vcpu->run->exit_reason = reason;
9311 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9313 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9315 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9317 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9319 int ret = kvm_skip_emulated_instruction(vcpu);
9321 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9322 * KVM_EXIT_DEBUG here.
9324 return kvm_emulate_halt_noskip(vcpu) && ret;
9326 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9328 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9330 int ret = kvm_skip_emulated_instruction(vcpu);
9332 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9333 KVM_EXIT_AP_RESET_HOLD) && ret;
9335 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9337 #ifdef CONFIG_X86_64
9338 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9339 unsigned long clock_type)
9341 struct kvm_clock_pairing clock_pairing;
9342 struct timespec64 ts;
9346 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9347 return -KVM_EOPNOTSUPP;
9350 * When tsc is in permanent catchup mode guests won't be able to use
9351 * pvclock_read_retry loop to get consistent view of pvclock
9353 if (vcpu->arch.tsc_always_catchup)
9354 return -KVM_EOPNOTSUPP;
9356 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9357 return -KVM_EOPNOTSUPP;
9359 clock_pairing.sec = ts.tv_sec;
9360 clock_pairing.nsec = ts.tv_nsec;
9361 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9362 clock_pairing.flags = 0;
9363 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9366 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9367 sizeof(struct kvm_clock_pairing)))
9375 * kvm_pv_kick_cpu_op: Kick a vcpu.
9377 * @apicid - apicid of vcpu to be kicked.
9379 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9382 * All other fields are unused for APIC_DM_REMRD, but may be consumed by
9383 * common code, e.g. for tracing. Defer initialization to the compiler.
9385 struct kvm_lapic_irq lapic_irq = {
9386 .delivery_mode = APIC_DM_REMRD,
9387 .dest_mode = APIC_DEST_PHYSICAL,
9388 .shorthand = APIC_DEST_NOSHORT,
9392 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9395 bool kvm_apicv_activated(struct kvm *kvm)
9397 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9399 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9401 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu)
9403 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons);
9404 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu);
9406 return (vm_reasons | vcpu_reasons) == 0;
9408 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated);
9410 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9411 enum kvm_apicv_inhibit reason, bool set)
9414 __set_bit(reason, inhibits);
9416 __clear_bit(reason, inhibits);
9418 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9421 static void kvm_apicv_init(struct kvm *kvm)
9423 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9425 init_rwsem(&kvm->arch.apicv_update_lock);
9427 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9430 set_or_clear_apicv_inhibit(inhibits,
9431 APICV_INHIBIT_REASON_DISABLE, true);
9434 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9436 struct kvm_vcpu *target = NULL;
9437 struct kvm_apic_map *map;
9439 vcpu->stat.directed_yield_attempted++;
9441 if (single_task_running())
9445 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9447 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9448 target = map->phys_map[dest_id]->vcpu;
9452 if (!target || !READ_ONCE(target->ready))
9455 /* Ignore requests to yield to self */
9459 if (kvm_vcpu_yield_to(target) <= 0)
9462 vcpu->stat.directed_yield_successful++;
9468 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
9470 u64 ret = vcpu->run->hypercall.ret;
9472 if (!is_64_bit_mode(vcpu))
9474 kvm_rax_write(vcpu, ret);
9475 ++vcpu->stat.hypercalls;
9476 return kvm_skip_emulated_instruction(vcpu);
9479 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
9481 unsigned long nr, a0, a1, a2, a3, ret;
9484 if (kvm_xen_hypercall_enabled(vcpu->kvm))
9485 return kvm_xen_hypercall(vcpu);
9487 if (kvm_hv_hypercall_enabled(vcpu))
9488 return kvm_hv_hypercall(vcpu);
9490 nr = kvm_rax_read(vcpu);
9491 a0 = kvm_rbx_read(vcpu);
9492 a1 = kvm_rcx_read(vcpu);
9493 a2 = kvm_rdx_read(vcpu);
9494 a3 = kvm_rsi_read(vcpu);
9496 trace_kvm_hypercall(nr, a0, a1, a2, a3);
9498 op_64_bit = is_64_bit_hypercall(vcpu);
9507 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
9515 case KVM_HC_VAPIC_POLL_IRQ:
9518 case KVM_HC_KICK_CPU:
9519 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
9522 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
9523 kvm_sched_yield(vcpu, a1);
9526 #ifdef CONFIG_X86_64
9527 case KVM_HC_CLOCK_PAIRING:
9528 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
9531 case KVM_HC_SEND_IPI:
9532 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
9535 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
9537 case KVM_HC_SCHED_YIELD:
9538 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
9541 kvm_sched_yield(vcpu, a0);
9544 case KVM_HC_MAP_GPA_RANGE: {
9545 u64 gpa = a0, npages = a1, attrs = a2;
9548 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
9551 if (!PAGE_ALIGNED(gpa) || !npages ||
9552 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
9557 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
9558 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
9559 vcpu->run->hypercall.args[0] = gpa;
9560 vcpu->run->hypercall.args[1] = npages;
9561 vcpu->run->hypercall.args[2] = attrs;
9562 vcpu->run->hypercall.longmode = op_64_bit;
9563 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
9573 kvm_rax_write(vcpu, ret);
9575 ++vcpu->stat.hypercalls;
9576 return kvm_skip_emulated_instruction(vcpu);
9578 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
9580 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
9582 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
9583 char instruction[3];
9584 unsigned long rip = kvm_rip_read(vcpu);
9587 * If the quirk is disabled, synthesize a #UD and let the guest pick up
9590 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) {
9591 ctxt->exception.error_code_valid = false;
9592 ctxt->exception.vector = UD_VECTOR;
9593 ctxt->have_exception = true;
9594 return X86EMUL_PROPAGATE_FAULT;
9597 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
9599 return emulator_write_emulated(ctxt, rip, instruction, 3,
9603 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
9605 return vcpu->run->request_interrupt_window &&
9606 likely(!pic_in_kernel(vcpu->kvm));
9609 /* Called within kvm->srcu read side. */
9610 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
9612 struct kvm_run *kvm_run = vcpu->run;
9614 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
9615 kvm_run->cr8 = kvm_get_cr8(vcpu);
9616 kvm_run->apic_base = kvm_get_apic_base(vcpu);
9618 kvm_run->ready_for_interrupt_injection =
9619 pic_in_kernel(vcpu->kvm) ||
9620 kvm_vcpu_ready_for_interrupt_injection(vcpu);
9623 kvm_run->flags |= KVM_RUN_X86_SMM;
9626 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
9630 if (!kvm_x86_ops.update_cr8_intercept)
9633 if (!lapic_in_kernel(vcpu))
9636 if (vcpu->arch.apic->apicv_active)
9639 if (!vcpu->arch.apic->vapic_addr)
9640 max_irr = kvm_lapic_find_highest_irr(vcpu);
9647 tpr = kvm_lapic_get_cr8(vcpu);
9649 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
9653 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
9655 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9656 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9660 return kvm_x86_ops.nested_ops->check_events(vcpu);
9663 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
9665 trace_kvm_inj_exception(vcpu->arch.exception.nr,
9666 vcpu->arch.exception.has_error_code,
9667 vcpu->arch.exception.error_code,
9668 vcpu->arch.exception.injected);
9670 if (vcpu->arch.exception.error_code && !is_protmode(vcpu))
9671 vcpu->arch.exception.error_code = false;
9672 static_call(kvm_x86_queue_exception)(vcpu);
9675 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
9678 bool can_inject = true;
9680 /* try to reinject previous events if any */
9682 if (vcpu->arch.exception.injected) {
9683 kvm_inject_exception(vcpu);
9687 * Do not inject an NMI or interrupt if there is a pending
9688 * exception. Exceptions and interrupts are recognized at
9689 * instruction boundaries, i.e. the start of an instruction.
9690 * Trap-like exceptions, e.g. #DB, have higher priority than
9691 * NMIs and interrupts, i.e. traps are recognized before an
9692 * NMI/interrupt that's pending on the same instruction.
9693 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
9694 * priority, but are only generated (pended) during instruction
9695 * execution, i.e. a pending fault-like exception means the
9696 * fault occurred on the *previous* instruction and must be
9697 * serviced prior to recognizing any new events in order to
9698 * fully complete the previous instruction.
9700 else if (!vcpu->arch.exception.pending) {
9701 if (vcpu->arch.nmi_injected) {
9702 static_call(kvm_x86_inject_nmi)(vcpu);
9704 } else if (vcpu->arch.interrupt.injected) {
9705 static_call(kvm_x86_inject_irq)(vcpu, true);
9710 WARN_ON_ONCE(vcpu->arch.exception.injected &&
9711 vcpu->arch.exception.pending);
9714 * Call check_nested_events() even if we reinjected a previous event
9715 * in order for caller to determine if it should require immediate-exit
9716 * from L2 to L1 due to pending L1 events which require exit
9719 if (is_guest_mode(vcpu)) {
9720 r = kvm_check_nested_events(vcpu);
9725 /* try to inject new event if pending */
9726 if (vcpu->arch.exception.pending) {
9727 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
9728 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
9731 if (vcpu->arch.exception.nr == DB_VECTOR) {
9732 kvm_deliver_exception_payload(vcpu);
9733 if (vcpu->arch.dr7 & DR7_GD) {
9734 vcpu->arch.dr7 &= ~DR7_GD;
9735 kvm_update_dr7(vcpu);
9739 kvm_inject_exception(vcpu);
9741 vcpu->arch.exception.pending = false;
9742 vcpu->arch.exception.injected = true;
9747 /* Don't inject interrupts if the user asked to avoid doing so */
9748 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
9752 * Finally, inject interrupt events. If an event cannot be injected
9753 * due to architectural conditions (e.g. IF=0) a window-open exit
9754 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
9755 * and can architecturally be injected, but we cannot do it right now:
9756 * an interrupt could have arrived just now and we have to inject it
9757 * as a vmexit, or there could already an event in the queue, which is
9758 * indicated by can_inject. In that case we request an immediate exit
9759 * in order to make progress and get back here for another iteration.
9760 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
9762 if (vcpu->arch.smi_pending) {
9763 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
9767 vcpu->arch.smi_pending = false;
9768 ++vcpu->arch.smi_count;
9772 static_call(kvm_x86_enable_smi_window)(vcpu);
9775 if (vcpu->arch.nmi_pending) {
9776 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
9780 --vcpu->arch.nmi_pending;
9781 vcpu->arch.nmi_injected = true;
9782 static_call(kvm_x86_inject_nmi)(vcpu);
9784 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
9786 if (vcpu->arch.nmi_pending)
9787 static_call(kvm_x86_enable_nmi_window)(vcpu);
9790 if (kvm_cpu_has_injectable_intr(vcpu)) {
9791 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
9795 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
9796 static_call(kvm_x86_inject_irq)(vcpu, false);
9797 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
9799 if (kvm_cpu_has_injectable_intr(vcpu))
9800 static_call(kvm_x86_enable_irq_window)(vcpu);
9803 if (is_guest_mode(vcpu) &&
9804 kvm_x86_ops.nested_ops->hv_timer_pending &&
9805 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
9806 *req_immediate_exit = true;
9808 WARN_ON(vcpu->arch.exception.pending);
9813 *req_immediate_exit = true;
9819 static void process_nmi(struct kvm_vcpu *vcpu)
9824 * x86 is limited to one NMI running, and one NMI pending after it.
9825 * If an NMI is already in progress, limit further NMIs to just one.
9826 * Otherwise, allow two (and we'll inject the first one immediately).
9828 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
9831 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
9832 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
9833 kvm_make_request(KVM_REQ_EVENT, vcpu);
9836 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
9839 flags |= seg->g << 23;
9840 flags |= seg->db << 22;
9841 flags |= seg->l << 21;
9842 flags |= seg->avl << 20;
9843 flags |= seg->present << 15;
9844 flags |= seg->dpl << 13;
9845 flags |= seg->s << 12;
9846 flags |= seg->type << 8;
9850 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
9852 struct kvm_segment seg;
9855 kvm_get_segment(vcpu, &seg, n);
9856 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
9859 offset = 0x7f84 + n * 12;
9861 offset = 0x7f2c + (n - 3) * 12;
9863 put_smstate(u32, buf, offset + 8, seg.base);
9864 put_smstate(u32, buf, offset + 4, seg.limit);
9865 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
9868 #ifdef CONFIG_X86_64
9869 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
9871 struct kvm_segment seg;
9875 kvm_get_segment(vcpu, &seg, n);
9876 offset = 0x7e00 + n * 16;
9878 flags = enter_smm_get_segment_flags(&seg) >> 8;
9879 put_smstate(u16, buf, offset, seg.selector);
9880 put_smstate(u16, buf, offset + 2, flags);
9881 put_smstate(u32, buf, offset + 4, seg.limit);
9882 put_smstate(u64, buf, offset + 8, seg.base);
9886 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
9889 struct kvm_segment seg;
9893 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
9894 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
9895 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
9896 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
9898 for (i = 0; i < 8; i++)
9899 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i));
9901 kvm_get_dr(vcpu, 6, &val);
9902 put_smstate(u32, buf, 0x7fcc, (u32)val);
9903 kvm_get_dr(vcpu, 7, &val);
9904 put_smstate(u32, buf, 0x7fc8, (u32)val);
9906 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
9907 put_smstate(u32, buf, 0x7fc4, seg.selector);
9908 put_smstate(u32, buf, 0x7f64, seg.base);
9909 put_smstate(u32, buf, 0x7f60, seg.limit);
9910 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
9912 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
9913 put_smstate(u32, buf, 0x7fc0, seg.selector);
9914 put_smstate(u32, buf, 0x7f80, seg.base);
9915 put_smstate(u32, buf, 0x7f7c, seg.limit);
9916 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
9918 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9919 put_smstate(u32, buf, 0x7f74, dt.address);
9920 put_smstate(u32, buf, 0x7f70, dt.size);
9922 static_call(kvm_x86_get_idt)(vcpu, &dt);
9923 put_smstate(u32, buf, 0x7f58, dt.address);
9924 put_smstate(u32, buf, 0x7f54, dt.size);
9926 for (i = 0; i < 6; i++)
9927 enter_smm_save_seg_32(vcpu, buf, i);
9929 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
9932 put_smstate(u32, buf, 0x7efc, 0x00020000);
9933 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
9936 #ifdef CONFIG_X86_64
9937 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
9940 struct kvm_segment seg;
9944 for (i = 0; i < 16; i++)
9945 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i));
9947 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
9948 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
9950 kvm_get_dr(vcpu, 6, &val);
9951 put_smstate(u64, buf, 0x7f68, val);
9952 kvm_get_dr(vcpu, 7, &val);
9953 put_smstate(u64, buf, 0x7f60, val);
9955 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
9956 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
9957 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
9959 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
9962 put_smstate(u32, buf, 0x7efc, 0x00020064);
9964 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
9966 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
9967 put_smstate(u16, buf, 0x7e90, seg.selector);
9968 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
9969 put_smstate(u32, buf, 0x7e94, seg.limit);
9970 put_smstate(u64, buf, 0x7e98, seg.base);
9972 static_call(kvm_x86_get_idt)(vcpu, &dt);
9973 put_smstate(u32, buf, 0x7e84, dt.size);
9974 put_smstate(u64, buf, 0x7e88, dt.address);
9976 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
9977 put_smstate(u16, buf, 0x7e70, seg.selector);
9978 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
9979 put_smstate(u32, buf, 0x7e74, seg.limit);
9980 put_smstate(u64, buf, 0x7e78, seg.base);
9982 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9983 put_smstate(u32, buf, 0x7e64, dt.size);
9984 put_smstate(u64, buf, 0x7e68, dt.address);
9986 for (i = 0; i < 6; i++)
9987 enter_smm_save_seg_64(vcpu, buf, i);
9991 static void enter_smm(struct kvm_vcpu *vcpu)
9993 struct kvm_segment cs, ds;
9998 memset(buf, 0, 512);
9999 #ifdef CONFIG_X86_64
10000 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
10001 enter_smm_save_state_64(vcpu, buf);
10004 enter_smm_save_state_32(vcpu, buf);
10007 * Give enter_smm() a chance to make ISA-specific changes to the vCPU
10008 * state (e.g. leave guest mode) after we've saved the state into the
10009 * SMM state-save area.
10011 static_call(kvm_x86_enter_smm)(vcpu, buf);
10013 kvm_smm_changed(vcpu, true);
10014 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
10016 if (static_call(kvm_x86_get_nmi_mask)(vcpu))
10017 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
10019 static_call(kvm_x86_set_nmi_mask)(vcpu, true);
10021 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
10022 kvm_rip_write(vcpu, 0x8000);
10024 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
10025 static_call(kvm_x86_set_cr0)(vcpu, cr0);
10026 vcpu->arch.cr0 = cr0;
10028 static_call(kvm_x86_set_cr4)(vcpu, 0);
10030 /* Undocumented: IDT limit is set to zero on entry to SMM. */
10031 dt.address = dt.size = 0;
10032 static_call(kvm_x86_set_idt)(vcpu, &dt);
10034 kvm_set_dr(vcpu, 7, DR7_FIXED_1);
10036 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
10037 cs.base = vcpu->arch.smbase;
10042 cs.limit = ds.limit = 0xffffffff;
10043 cs.type = ds.type = 0x3;
10044 cs.dpl = ds.dpl = 0;
10049 cs.avl = ds.avl = 0;
10050 cs.present = ds.present = 1;
10051 cs.unusable = ds.unusable = 0;
10052 cs.padding = ds.padding = 0;
10054 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
10055 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
10056 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
10057 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
10058 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
10059 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
10061 #ifdef CONFIG_X86_64
10062 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
10063 static_call(kvm_x86_set_efer)(vcpu, 0);
10066 kvm_update_cpuid_runtime(vcpu);
10067 kvm_mmu_reset_context(vcpu);
10070 static void process_smi(struct kvm_vcpu *vcpu)
10072 vcpu->arch.smi_pending = true;
10073 kvm_make_request(KVM_REQ_EVENT, vcpu);
10076 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
10077 unsigned long *vcpu_bitmap)
10079 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
10082 void kvm_make_scan_ioapic_request(struct kvm *kvm)
10084 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
10087 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10089 struct kvm_lapic *apic = vcpu->arch.apic;
10092 if (!lapic_in_kernel(vcpu))
10095 down_read(&vcpu->kvm->arch.apicv_update_lock);
10098 /* Do not activate APICV when APIC is disabled */
10099 activate = kvm_vcpu_apicv_activated(vcpu) &&
10100 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED);
10102 if (apic->apicv_active == activate)
10105 apic->apicv_active = activate;
10106 kvm_apic_update_apicv(vcpu);
10107 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
10110 * When APICv gets disabled, we may still have injected interrupts
10111 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
10112 * still active when the interrupt got accepted. Make sure
10113 * inject_pending_event() is called to check for that.
10115 if (!apic->apicv_active)
10116 kvm_make_request(KVM_REQ_EVENT, vcpu);
10120 up_read(&vcpu->kvm->arch.apicv_update_lock);
10122 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
10124 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10125 enum kvm_apicv_inhibit reason, bool set)
10127 unsigned long old, new;
10129 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
10131 if (!static_call(kvm_x86_check_apicv_inhibit_reasons)(reason))
10134 old = new = kvm->arch.apicv_inhibit_reasons;
10136 set_or_clear_apicv_inhibit(&new, reason, set);
10138 if (!!old != !!new) {
10140 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
10141 * false positives in the sanity check WARN in svm_vcpu_run().
10142 * This task will wait for all vCPUs to ack the kick IRQ before
10143 * updating apicv_inhibit_reasons, and all other vCPUs will
10144 * block on acquiring apicv_update_lock so that vCPUs can't
10145 * redo svm_vcpu_run() without seeing the new inhibit state.
10147 * Note, holding apicv_update_lock and taking it in the read
10148 * side (handling the request) also prevents other vCPUs from
10149 * servicing the request with a stale apicv_inhibit_reasons.
10151 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
10152 kvm->arch.apicv_inhibit_reasons = new;
10154 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
10155 kvm_zap_gfn_range(kvm, gfn, gfn+1);
10158 kvm->arch.apicv_inhibit_reasons = new;
10162 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10163 enum kvm_apicv_inhibit reason, bool set)
10168 down_write(&kvm->arch.apicv_update_lock);
10169 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
10170 up_write(&kvm->arch.apicv_update_lock);
10172 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
10174 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
10176 if (!kvm_apic_present(vcpu))
10179 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
10181 if (irqchip_split(vcpu->kvm))
10182 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
10184 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10185 if (ioapic_in_kernel(vcpu->kvm))
10186 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
10189 if (is_guest_mode(vcpu))
10190 vcpu->arch.load_eoi_exitmap_pending = true;
10192 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
10195 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
10197 u64 eoi_exit_bitmap[4];
10199 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
10202 if (to_hv_vcpu(vcpu)) {
10203 bitmap_or((ulong *)eoi_exit_bitmap,
10204 vcpu->arch.ioapic_handled_vectors,
10205 to_hv_synic(vcpu)->vec_bitmap, 256);
10206 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
10210 static_call_cond(kvm_x86_load_eoi_exitmap)(
10211 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
10214 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
10215 unsigned long start, unsigned long end)
10217 unsigned long apic_address;
10220 * The physical address of apic access page is stored in the VMCS.
10221 * Update it when it becomes invalid.
10223 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
10224 if (start <= apic_address && apic_address < end)
10225 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
10228 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
10230 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm);
10233 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
10235 if (!lapic_in_kernel(vcpu))
10238 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
10241 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
10243 smp_send_reschedule(vcpu->cpu);
10245 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
10248 * Called within kvm->srcu read side.
10249 * Returns 1 to let vcpu_run() continue the guest execution loop without
10250 * exiting to the userspace. Otherwise, the value will be returned to the
10253 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
10257 dm_request_for_irq_injection(vcpu) &&
10258 kvm_cpu_accept_dm_intr(vcpu);
10259 fastpath_t exit_fastpath;
10261 bool req_immediate_exit = false;
10263 /* Forbid vmenter if vcpu dirty ring is soft-full */
10264 if (unlikely(vcpu->kvm->dirty_ring_size &&
10265 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
10266 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
10267 trace_kvm_dirty_ring_exit(vcpu);
10272 if (kvm_request_pending(vcpu)) {
10273 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
10277 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
10278 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
10283 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
10284 kvm_mmu_free_obsolete_roots(vcpu);
10285 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
10286 __kvm_migrate_timers(vcpu);
10287 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
10288 kvm_update_masterclock(vcpu->kvm);
10289 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
10290 kvm_gen_kvmclock_update(vcpu);
10291 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
10292 r = kvm_guest_time_update(vcpu);
10296 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
10297 kvm_mmu_sync_roots(vcpu);
10298 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
10299 kvm_mmu_load_pgd(vcpu);
10300 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
10301 kvm_vcpu_flush_tlb_all(vcpu);
10303 /* Flushing all ASIDs flushes the current ASID... */
10304 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
10306 kvm_service_local_tlb_flush_requests(vcpu);
10308 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
10309 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
10313 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10314 if (is_guest_mode(vcpu)) {
10315 kvm_x86_ops.nested_ops->triple_fault(vcpu);
10317 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
10318 vcpu->mmio_needed = 0;
10323 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
10324 /* Page is swapped out. Do synthetic halt */
10325 vcpu->arch.apf.halted = true;
10329 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
10330 record_steal_time(vcpu);
10331 if (kvm_check_request(KVM_REQ_SMI, vcpu))
10333 if (kvm_check_request(KVM_REQ_NMI, vcpu))
10335 if (kvm_check_request(KVM_REQ_PMU, vcpu))
10336 kvm_pmu_handle_event(vcpu);
10337 if (kvm_check_request(KVM_REQ_PMI, vcpu))
10338 kvm_pmu_deliver_pmi(vcpu);
10339 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10340 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10341 if (test_bit(vcpu->arch.pending_ioapic_eoi,
10342 vcpu->arch.ioapic_handled_vectors)) {
10343 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10344 vcpu->run->eoi.vector =
10345 vcpu->arch.pending_ioapic_eoi;
10350 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10351 vcpu_scan_ioapic(vcpu);
10352 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10353 vcpu_load_eoi_exitmap(vcpu);
10354 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10355 kvm_vcpu_reload_apic_access_page(vcpu);
10356 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10357 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10358 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10359 vcpu->run->system_event.ndata = 0;
10363 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10364 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10365 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10366 vcpu->run->system_event.ndata = 0;
10370 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10371 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10373 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10374 vcpu->run->hyperv = hv_vcpu->exit;
10380 * KVM_REQ_HV_STIMER has to be processed after
10381 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10382 * depend on the guest clock being up-to-date
10384 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10385 kvm_hv_process_stimers(vcpu);
10386 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10387 kvm_vcpu_update_apicv(vcpu);
10388 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10389 kvm_check_async_pf_completion(vcpu);
10390 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10391 static_call(kvm_x86_msr_filter_changed)(vcpu);
10393 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10394 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10397 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10398 kvm_xen_has_interrupt(vcpu)) {
10399 ++vcpu->stat.req_event;
10400 r = kvm_apic_accept_events(vcpu);
10405 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10410 r = inject_pending_event(vcpu, &req_immediate_exit);
10416 static_call(kvm_x86_enable_irq_window)(vcpu);
10418 if (kvm_lapic_enabled(vcpu)) {
10419 update_cr8_intercept(vcpu);
10420 kvm_lapic_sync_to_vapic(vcpu);
10424 r = kvm_mmu_reload(vcpu);
10426 goto cancel_injection;
10431 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10434 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10435 * IPI are then delayed after guest entry, which ensures that they
10436 * result in virtual interrupt delivery.
10438 local_irq_disable();
10440 /* Store vcpu->apicv_active before vcpu->mode. */
10441 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10443 kvm_vcpu_srcu_read_unlock(vcpu);
10446 * 1) We should set ->mode before checking ->requests. Please see
10447 * the comment in kvm_vcpu_exiting_guest_mode().
10449 * 2) For APICv, we should set ->mode before checking PID.ON. This
10450 * pairs with the memory barrier implicit in pi_test_and_set_on
10451 * (see vmx_deliver_posted_interrupt).
10453 * 3) This also orders the write to mode from any reads to the page
10454 * tables done while the VCPU is running. Please see the comment
10455 * in kvm_flush_remote_tlbs.
10457 smp_mb__after_srcu_read_unlock();
10460 * Process pending posted interrupts to handle the case where the
10461 * notification IRQ arrived in the host, or was never sent (because the
10462 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10463 * status, KVM doesn't update assigned devices when APICv is inhibited,
10464 * i.e. they can post interrupts even if APICv is temporarily disabled.
10466 if (kvm_lapic_enabled(vcpu))
10467 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10469 if (kvm_vcpu_exit_request(vcpu)) {
10470 vcpu->mode = OUTSIDE_GUEST_MODE;
10472 local_irq_enable();
10474 kvm_vcpu_srcu_read_lock(vcpu);
10476 goto cancel_injection;
10479 if (req_immediate_exit) {
10480 kvm_make_request(KVM_REQ_EVENT, vcpu);
10481 static_call(kvm_x86_request_immediate_exit)(vcpu);
10484 fpregs_assert_state_consistent();
10485 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10486 switch_fpu_return();
10488 if (vcpu->arch.guest_fpu.xfd_err)
10489 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10491 if (unlikely(vcpu->arch.switch_db_regs)) {
10492 set_debugreg(0, 7);
10493 set_debugreg(vcpu->arch.eff_db[0], 0);
10494 set_debugreg(vcpu->arch.eff_db[1], 1);
10495 set_debugreg(vcpu->arch.eff_db[2], 2);
10496 set_debugreg(vcpu->arch.eff_db[3], 3);
10497 } else if (unlikely(hw_breakpoint_active())) {
10498 set_debugreg(0, 7);
10501 guest_timing_enter_irqoff();
10505 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10506 * update must kick and wait for all vCPUs before toggling the
10507 * per-VM state, and responsing vCPUs must wait for the update
10508 * to complete before servicing KVM_REQ_APICV_UPDATE.
10510 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) &&
10511 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED));
10513 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10514 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10517 if (kvm_lapic_enabled(vcpu))
10518 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10520 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10521 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10527 * Do this here before restoring debug registers on the host. And
10528 * since we do this before handling the vmexit, a DR access vmexit
10529 * can (a) read the correct value of the debug registers, (b) set
10530 * KVM_DEBUGREG_WONT_EXIT again.
10532 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
10533 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
10534 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
10535 kvm_update_dr0123(vcpu);
10536 kvm_update_dr7(vcpu);
10540 * If the guest has used debug registers, at least dr7
10541 * will be disabled while returning to the host.
10542 * If we don't have active breakpoints in the host, we don't
10543 * care about the messed up debug address registers. But if
10544 * we have some of them active, restore the old state.
10546 if (hw_breakpoint_active())
10547 hw_breakpoint_restore();
10549 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
10550 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
10552 vcpu->mode = OUTSIDE_GUEST_MODE;
10556 * Sync xfd before calling handle_exit_irqoff() which may
10557 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
10558 * in #NM irqoff handler).
10560 if (vcpu->arch.xfd_no_write_intercept)
10561 fpu_sync_guest_vmexit_xfd_state();
10563 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
10565 if (vcpu->arch.guest_fpu.xfd_err)
10566 wrmsrl(MSR_IA32_XFD_ERR, 0);
10569 * Consume any pending interrupts, including the possible source of
10570 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
10571 * An instruction is required after local_irq_enable() to fully unblock
10572 * interrupts on processors that implement an interrupt shadow, the
10573 * stat.exits increment will do nicely.
10575 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
10576 local_irq_enable();
10577 ++vcpu->stat.exits;
10578 local_irq_disable();
10579 kvm_after_interrupt(vcpu);
10582 * Wait until after servicing IRQs to account guest time so that any
10583 * ticks that occurred while running the guest are properly accounted
10584 * to the guest. Waiting until IRQs are enabled degrades the accuracy
10585 * of accounting via context tracking, but the loss of accuracy is
10586 * acceptable for all known use cases.
10588 guest_timing_exit_irqoff();
10590 local_irq_enable();
10593 kvm_vcpu_srcu_read_lock(vcpu);
10596 * Profile KVM exit RIPs:
10598 if (unlikely(prof_on == KVM_PROFILING)) {
10599 unsigned long rip = kvm_rip_read(vcpu);
10600 profile_hit(KVM_PROFILING, (void *)rip);
10603 if (unlikely(vcpu->arch.tsc_always_catchup))
10604 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10606 if (vcpu->arch.apic_attention)
10607 kvm_lapic_sync_from_vapic(vcpu);
10609 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
10613 if (req_immediate_exit)
10614 kvm_make_request(KVM_REQ_EVENT, vcpu);
10615 static_call(kvm_x86_cancel_injection)(vcpu);
10616 if (unlikely(vcpu->arch.apic_attention))
10617 kvm_lapic_sync_from_vapic(vcpu);
10622 /* Called within kvm->srcu read side. */
10623 static inline int vcpu_block(struct kvm_vcpu *vcpu)
10627 if (!kvm_arch_vcpu_runnable(vcpu)) {
10629 * Switch to the software timer before halt-polling/blocking as
10630 * the guest's timer may be a break event for the vCPU, and the
10631 * hypervisor timer runs only when the CPU is in guest mode.
10632 * Switch before halt-polling so that KVM recognizes an expired
10633 * timer before blocking.
10635 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
10637 kvm_lapic_switch_to_sw_timer(vcpu);
10639 kvm_vcpu_srcu_read_unlock(vcpu);
10640 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10641 kvm_vcpu_halt(vcpu);
10643 kvm_vcpu_block(vcpu);
10644 kvm_vcpu_srcu_read_lock(vcpu);
10647 kvm_lapic_switch_to_hv_timer(vcpu);
10649 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
10653 if (kvm_apic_accept_events(vcpu) < 0)
10655 switch(vcpu->arch.mp_state) {
10656 case KVM_MP_STATE_HALTED:
10657 case KVM_MP_STATE_AP_RESET_HOLD:
10658 vcpu->arch.pv.pv_unhalted = false;
10659 vcpu->arch.mp_state =
10660 KVM_MP_STATE_RUNNABLE;
10662 case KVM_MP_STATE_RUNNABLE:
10663 vcpu->arch.apf.halted = false;
10665 case KVM_MP_STATE_INIT_RECEIVED:
10674 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
10676 if (is_guest_mode(vcpu))
10677 kvm_check_nested_events(vcpu);
10679 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
10680 !vcpu->arch.apf.halted);
10683 /* Called within kvm->srcu read side. */
10684 static int vcpu_run(struct kvm_vcpu *vcpu)
10688 vcpu->arch.l1tf_flush_l1d = true;
10692 * If another guest vCPU requests a PV TLB flush in the middle
10693 * of instruction emulation, the rest of the emulation could
10694 * use a stale page translation. Assume that any code after
10695 * this point can start executing an instruction.
10697 vcpu->arch.at_instruction_boundary = false;
10698 if (kvm_vcpu_running(vcpu)) {
10699 r = vcpu_enter_guest(vcpu);
10701 r = vcpu_block(vcpu);
10707 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
10708 if (kvm_xen_has_pending_events(vcpu))
10709 kvm_xen_inject_pending_events(vcpu);
10711 if (kvm_cpu_has_pending_timer(vcpu))
10712 kvm_inject_pending_timer_irqs(vcpu);
10714 if (dm_request_for_irq_injection(vcpu) &&
10715 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
10717 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
10718 ++vcpu->stat.request_irq_exits;
10722 if (__xfer_to_guest_mode_work_pending()) {
10723 kvm_vcpu_srcu_read_unlock(vcpu);
10724 r = xfer_to_guest_mode_handle_work(vcpu);
10725 kvm_vcpu_srcu_read_lock(vcpu);
10734 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
10736 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
10739 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
10741 BUG_ON(!vcpu->arch.pio.count);
10743 return complete_emulated_io(vcpu);
10747 * Implements the following, as a state machine:
10750 * for each fragment
10751 * for each mmio piece in the fragment
10758 * for each fragment
10759 * for each mmio piece in the fragment
10764 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
10766 struct kvm_run *run = vcpu->run;
10767 struct kvm_mmio_fragment *frag;
10770 BUG_ON(!vcpu->mmio_needed);
10772 /* Complete previous fragment */
10773 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
10774 len = min(8u, frag->len);
10775 if (!vcpu->mmio_is_write)
10776 memcpy(frag->data, run->mmio.data, len);
10778 if (frag->len <= 8) {
10779 /* Switch to the next fragment. */
10781 vcpu->mmio_cur_fragment++;
10783 /* Go forward to the next mmio piece. */
10789 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
10790 vcpu->mmio_needed = 0;
10792 /* FIXME: return into emulator if single-stepping. */
10793 if (vcpu->mmio_is_write)
10795 vcpu->mmio_read_completed = 1;
10796 return complete_emulated_io(vcpu);
10799 run->exit_reason = KVM_EXIT_MMIO;
10800 run->mmio.phys_addr = frag->gpa;
10801 if (vcpu->mmio_is_write)
10802 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
10803 run->mmio.len = min(8u, frag->len);
10804 run->mmio.is_write = vcpu->mmio_is_write;
10805 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
10809 /* Swap (qemu) user FPU context for the guest FPU context. */
10810 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
10812 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
10813 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
10817 /* When vcpu_run ends, restore user space FPU context. */
10818 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
10820 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
10821 ++vcpu->stat.fpu_reload;
10825 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
10827 struct kvm_run *kvm_run = vcpu->run;
10831 kvm_sigset_activate(vcpu);
10832 kvm_run->flags = 0;
10833 kvm_load_guest_fpu(vcpu);
10835 kvm_vcpu_srcu_read_lock(vcpu);
10836 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
10837 if (kvm_run->immediate_exit) {
10842 * It should be impossible for the hypervisor timer to be in
10843 * use before KVM has ever run the vCPU.
10845 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu));
10847 kvm_vcpu_srcu_read_unlock(vcpu);
10848 kvm_vcpu_block(vcpu);
10849 kvm_vcpu_srcu_read_lock(vcpu);
10851 if (kvm_apic_accept_events(vcpu) < 0) {
10855 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
10857 if (signal_pending(current)) {
10859 kvm_run->exit_reason = KVM_EXIT_INTR;
10860 ++vcpu->stat.signal_exits;
10865 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
10866 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
10871 if (kvm_run->kvm_dirty_regs) {
10872 r = sync_regs(vcpu);
10877 /* re-sync apic's tpr */
10878 if (!lapic_in_kernel(vcpu)) {
10879 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
10885 if (unlikely(vcpu->arch.complete_userspace_io)) {
10886 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
10887 vcpu->arch.complete_userspace_io = NULL;
10892 WARN_ON_ONCE(vcpu->arch.pio.count);
10893 WARN_ON_ONCE(vcpu->mmio_needed);
10896 if (kvm_run->immediate_exit) {
10901 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
10905 r = vcpu_run(vcpu);
10908 kvm_put_guest_fpu(vcpu);
10909 if (kvm_run->kvm_valid_regs)
10911 post_kvm_run_save(vcpu);
10912 kvm_vcpu_srcu_read_unlock(vcpu);
10914 kvm_sigset_deactivate(vcpu);
10919 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10921 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
10923 * We are here if userspace calls get_regs() in the middle of
10924 * instruction emulation. Registers state needs to be copied
10925 * back from emulation context to vcpu. Userspace shouldn't do
10926 * that usually, but some bad designed PV devices (vmware
10927 * backdoor interface) need this to work
10929 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
10930 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10932 regs->rax = kvm_rax_read(vcpu);
10933 regs->rbx = kvm_rbx_read(vcpu);
10934 regs->rcx = kvm_rcx_read(vcpu);
10935 regs->rdx = kvm_rdx_read(vcpu);
10936 regs->rsi = kvm_rsi_read(vcpu);
10937 regs->rdi = kvm_rdi_read(vcpu);
10938 regs->rsp = kvm_rsp_read(vcpu);
10939 regs->rbp = kvm_rbp_read(vcpu);
10940 #ifdef CONFIG_X86_64
10941 regs->r8 = kvm_r8_read(vcpu);
10942 regs->r9 = kvm_r9_read(vcpu);
10943 regs->r10 = kvm_r10_read(vcpu);
10944 regs->r11 = kvm_r11_read(vcpu);
10945 regs->r12 = kvm_r12_read(vcpu);
10946 regs->r13 = kvm_r13_read(vcpu);
10947 regs->r14 = kvm_r14_read(vcpu);
10948 regs->r15 = kvm_r15_read(vcpu);
10951 regs->rip = kvm_rip_read(vcpu);
10952 regs->rflags = kvm_get_rflags(vcpu);
10955 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10958 __get_regs(vcpu, regs);
10963 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10965 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
10966 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10968 kvm_rax_write(vcpu, regs->rax);
10969 kvm_rbx_write(vcpu, regs->rbx);
10970 kvm_rcx_write(vcpu, regs->rcx);
10971 kvm_rdx_write(vcpu, regs->rdx);
10972 kvm_rsi_write(vcpu, regs->rsi);
10973 kvm_rdi_write(vcpu, regs->rdi);
10974 kvm_rsp_write(vcpu, regs->rsp);
10975 kvm_rbp_write(vcpu, regs->rbp);
10976 #ifdef CONFIG_X86_64
10977 kvm_r8_write(vcpu, regs->r8);
10978 kvm_r9_write(vcpu, regs->r9);
10979 kvm_r10_write(vcpu, regs->r10);
10980 kvm_r11_write(vcpu, regs->r11);
10981 kvm_r12_write(vcpu, regs->r12);
10982 kvm_r13_write(vcpu, regs->r13);
10983 kvm_r14_write(vcpu, regs->r14);
10984 kvm_r15_write(vcpu, regs->r15);
10987 kvm_rip_write(vcpu, regs->rip);
10988 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
10990 vcpu->arch.exception.pending = false;
10992 kvm_make_request(KVM_REQ_EVENT, vcpu);
10995 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10998 __set_regs(vcpu, regs);
11003 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11005 struct desc_ptr dt;
11007 if (vcpu->arch.guest_state_protected)
11008 goto skip_protected_regs;
11010 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11011 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11012 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11013 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11014 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11015 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11017 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11018 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11020 static_call(kvm_x86_get_idt)(vcpu, &dt);
11021 sregs->idt.limit = dt.size;
11022 sregs->idt.base = dt.address;
11023 static_call(kvm_x86_get_gdt)(vcpu, &dt);
11024 sregs->gdt.limit = dt.size;
11025 sregs->gdt.base = dt.address;
11027 sregs->cr2 = vcpu->arch.cr2;
11028 sregs->cr3 = kvm_read_cr3(vcpu);
11030 skip_protected_regs:
11031 sregs->cr0 = kvm_read_cr0(vcpu);
11032 sregs->cr4 = kvm_read_cr4(vcpu);
11033 sregs->cr8 = kvm_get_cr8(vcpu);
11034 sregs->efer = vcpu->arch.efer;
11035 sregs->apic_base = kvm_get_apic_base(vcpu);
11038 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11040 __get_sregs_common(vcpu, sregs);
11042 if (vcpu->arch.guest_state_protected)
11045 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
11046 set_bit(vcpu->arch.interrupt.nr,
11047 (unsigned long *)sregs->interrupt_bitmap);
11050 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11054 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
11056 if (vcpu->arch.guest_state_protected)
11059 if (is_pae_paging(vcpu)) {
11060 for (i = 0 ; i < 4 ; i++)
11061 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
11062 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
11066 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
11067 struct kvm_sregs *sregs)
11070 __get_sregs(vcpu, sregs);
11075 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
11076 struct kvm_mp_state *mp_state)
11081 if (kvm_mpx_supported())
11082 kvm_load_guest_fpu(vcpu);
11084 r = kvm_apic_accept_events(vcpu);
11089 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
11090 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
11091 vcpu->arch.pv.pv_unhalted)
11092 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
11094 mp_state->mp_state = vcpu->arch.mp_state;
11097 if (kvm_mpx_supported())
11098 kvm_put_guest_fpu(vcpu);
11103 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
11104 struct kvm_mp_state *mp_state)
11110 switch (mp_state->mp_state) {
11111 case KVM_MP_STATE_UNINITIALIZED:
11112 case KVM_MP_STATE_HALTED:
11113 case KVM_MP_STATE_AP_RESET_HOLD:
11114 case KVM_MP_STATE_INIT_RECEIVED:
11115 case KVM_MP_STATE_SIPI_RECEIVED:
11116 if (!lapic_in_kernel(vcpu))
11120 case KVM_MP_STATE_RUNNABLE:
11128 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
11129 * INIT state; latched init should be reported using
11130 * KVM_SET_VCPU_EVENTS, so reject it here.
11132 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
11133 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
11134 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
11137 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
11138 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
11139 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
11141 vcpu->arch.mp_state = mp_state->mp_state;
11142 kvm_make_request(KVM_REQ_EVENT, vcpu);
11150 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
11151 int reason, bool has_error_code, u32 error_code)
11153 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
11156 init_emulate_ctxt(vcpu);
11158 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
11159 has_error_code, error_code);
11161 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11162 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11163 vcpu->run->internal.ndata = 0;
11167 kvm_rip_write(vcpu, ctxt->eip);
11168 kvm_set_rflags(vcpu, ctxt->eflags);
11171 EXPORT_SYMBOL_GPL(kvm_task_switch);
11173 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11175 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
11177 * When EFER.LME and CR0.PG are set, the processor is in
11178 * 64-bit mode (though maybe in a 32-bit code segment).
11179 * CR4.PAE and EFER.LMA must be set.
11181 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
11183 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
11187 * Not in 64-bit mode: EFER.LMA is clear and the code
11188 * segment cannot be 64-bit.
11190 if (sregs->efer & EFER_LMA || sregs->cs.l)
11194 return kvm_is_valid_cr4(vcpu, sregs->cr4);
11197 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
11198 int *mmu_reset_needed, bool update_pdptrs)
11200 struct msr_data apic_base_msr;
11202 struct desc_ptr dt;
11204 if (!kvm_is_valid_sregs(vcpu, sregs))
11207 apic_base_msr.data = sregs->apic_base;
11208 apic_base_msr.host_initiated = true;
11209 if (kvm_set_apic_base(vcpu, &apic_base_msr))
11212 if (vcpu->arch.guest_state_protected)
11215 dt.size = sregs->idt.limit;
11216 dt.address = sregs->idt.base;
11217 static_call(kvm_x86_set_idt)(vcpu, &dt);
11218 dt.size = sregs->gdt.limit;
11219 dt.address = sregs->gdt.base;
11220 static_call(kvm_x86_set_gdt)(vcpu, &dt);
11222 vcpu->arch.cr2 = sregs->cr2;
11223 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
11224 vcpu->arch.cr3 = sregs->cr3;
11225 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11226 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
11228 kvm_set_cr8(vcpu, sregs->cr8);
11230 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
11231 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
11233 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
11234 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
11235 vcpu->arch.cr0 = sregs->cr0;
11237 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
11238 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
11240 if (update_pdptrs) {
11241 idx = srcu_read_lock(&vcpu->kvm->srcu);
11242 if (is_pae_paging(vcpu)) {
11243 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
11244 *mmu_reset_needed = 1;
11246 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11249 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11250 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11251 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11252 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11253 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11254 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11256 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11257 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11259 update_cr8_intercept(vcpu);
11261 /* Older userspace won't unhalt the vcpu on reset. */
11262 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
11263 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
11264 !is_protmode(vcpu))
11265 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11270 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11272 int pending_vec, max_bits;
11273 int mmu_reset_needed = 0;
11274 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
11279 if (mmu_reset_needed)
11280 kvm_mmu_reset_context(vcpu);
11282 max_bits = KVM_NR_INTERRUPTS;
11283 pending_vec = find_first_bit(
11284 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
11286 if (pending_vec < max_bits) {
11287 kvm_queue_interrupt(vcpu, pending_vec, false);
11288 pr_debug("Set back pending irq %d\n", pending_vec);
11289 kvm_make_request(KVM_REQ_EVENT, vcpu);
11294 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11296 int mmu_reset_needed = 0;
11297 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
11298 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
11299 !(sregs2->efer & EFER_LMA);
11302 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
11305 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
11308 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
11309 &mmu_reset_needed, !valid_pdptrs);
11313 if (valid_pdptrs) {
11314 for (i = 0; i < 4 ; i++)
11315 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
11317 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
11318 mmu_reset_needed = 1;
11319 vcpu->arch.pdptrs_from_userspace = true;
11321 if (mmu_reset_needed)
11322 kvm_mmu_reset_context(vcpu);
11326 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
11327 struct kvm_sregs *sregs)
11332 ret = __set_sregs(vcpu, sregs);
11337 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
11340 struct kvm_vcpu *vcpu;
11346 down_write(&kvm->arch.apicv_update_lock);
11348 kvm_for_each_vcpu(i, vcpu, kvm) {
11349 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
11354 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11355 up_write(&kvm->arch.apicv_update_lock);
11358 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11359 struct kvm_guest_debug *dbg)
11361 unsigned long rflags;
11364 if (vcpu->arch.guest_state_protected)
11369 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11371 if (vcpu->arch.exception.pending)
11373 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11374 kvm_queue_exception(vcpu, DB_VECTOR);
11376 kvm_queue_exception(vcpu, BP_VECTOR);
11380 * Read rflags as long as potentially injected trace flags are still
11383 rflags = kvm_get_rflags(vcpu);
11385 vcpu->guest_debug = dbg->control;
11386 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11387 vcpu->guest_debug = 0;
11389 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11390 for (i = 0; i < KVM_NR_DB_REGS; ++i)
11391 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11392 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11394 for (i = 0; i < KVM_NR_DB_REGS; i++)
11395 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11397 kvm_update_dr7(vcpu);
11399 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11400 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11403 * Trigger an rflags update that will inject or remove the trace
11406 kvm_set_rflags(vcpu, rflags);
11408 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11410 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11420 * Translate a guest virtual address to a guest physical address.
11422 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11423 struct kvm_translation *tr)
11425 unsigned long vaddr = tr->linear_address;
11431 idx = srcu_read_lock(&vcpu->kvm->srcu);
11432 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11433 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11434 tr->physical_address = gpa;
11435 tr->valid = gpa != INVALID_GPA;
11443 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11445 struct fxregs_state *fxsave;
11447 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11452 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11453 memcpy(fpu->fpr, fxsave->st_space, 128);
11454 fpu->fcw = fxsave->cwd;
11455 fpu->fsw = fxsave->swd;
11456 fpu->ftwx = fxsave->twd;
11457 fpu->last_opcode = fxsave->fop;
11458 fpu->last_ip = fxsave->rip;
11459 fpu->last_dp = fxsave->rdp;
11460 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11466 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11468 struct fxregs_state *fxsave;
11470 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11475 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11477 memcpy(fxsave->st_space, fpu->fpr, 128);
11478 fxsave->cwd = fpu->fcw;
11479 fxsave->swd = fpu->fsw;
11480 fxsave->twd = fpu->ftwx;
11481 fxsave->fop = fpu->last_opcode;
11482 fxsave->rip = fpu->last_ip;
11483 fxsave->rdp = fpu->last_dp;
11484 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11490 static void store_regs(struct kvm_vcpu *vcpu)
11492 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
11494 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
11495 __get_regs(vcpu, &vcpu->run->s.regs.regs);
11497 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
11498 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
11500 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
11501 kvm_vcpu_ioctl_x86_get_vcpu_events(
11502 vcpu, &vcpu->run->s.regs.events);
11505 static int sync_regs(struct kvm_vcpu *vcpu)
11507 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
11508 __set_regs(vcpu, &vcpu->run->s.regs.regs);
11509 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
11511 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
11512 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
11514 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
11516 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
11517 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
11518 vcpu, &vcpu->run->s.regs.events))
11520 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
11526 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
11528 if (kvm_check_tsc_unstable() && kvm->created_vcpus)
11529 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
11530 "guest TSC will not be reliable\n");
11532 if (!kvm->arch.max_vcpu_ids)
11533 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS;
11535 if (id >= kvm->arch.max_vcpu_ids)
11538 return static_call(kvm_x86_vcpu_precreate)(kvm);
11541 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
11546 vcpu->arch.last_vmentry_cpu = -1;
11547 vcpu->arch.regs_avail = ~0;
11548 vcpu->arch.regs_dirty = ~0;
11550 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
11551 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11553 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
11555 r = kvm_mmu_create(vcpu);
11559 if (irqchip_in_kernel(vcpu->kvm)) {
11560 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
11562 goto fail_mmu_destroy;
11565 * Defer evaluating inhibits until the vCPU is first run, as
11566 * this vCPU will not get notified of any changes until this
11567 * vCPU is visible to other vCPUs (marked online and added to
11568 * the set of vCPUs). Opportunistically mark APICv active as
11569 * VMX in particularly is highly unlikely to have inhibits.
11570 * Ignore the current per-VM APICv state so that vCPU creation
11571 * is guaranteed to run with a deterministic value, the request
11572 * will ensure the vCPU gets the correct state before VM-Entry.
11574 if (enable_apicv) {
11575 vcpu->arch.apic->apicv_active = true;
11576 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
11579 static_branch_inc(&kvm_has_noapic_vcpu);
11583 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
11585 goto fail_free_lapic;
11586 vcpu->arch.pio_data = page_address(page);
11588 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64),
11589 GFP_KERNEL_ACCOUNT);
11590 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64),
11591 GFP_KERNEL_ACCOUNT);
11592 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks)
11593 goto fail_free_mce_banks;
11594 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
11596 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
11597 GFP_KERNEL_ACCOUNT))
11598 goto fail_free_mce_banks;
11600 if (!alloc_emulate_ctxt(vcpu))
11601 goto free_wbinvd_dirty_mask;
11603 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
11604 pr_err("kvm: failed to allocate vcpu's fpu\n");
11605 goto free_emulate_ctxt;
11608 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
11609 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
11611 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
11613 kvm_async_pf_hash_reset(vcpu);
11614 kvm_pmu_init(vcpu);
11616 vcpu->arch.pending_external_vector = -1;
11617 vcpu->arch.preempted_in_kernel = false;
11619 #if IS_ENABLED(CONFIG_HYPERV)
11620 vcpu->arch.hv_root_tdp = INVALID_PAGE;
11623 r = static_call(kvm_x86_vcpu_create)(vcpu);
11625 goto free_guest_fpu;
11627 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
11628 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
11629 kvm_xen_init_vcpu(vcpu);
11630 kvm_vcpu_mtrr_init(vcpu);
11632 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz);
11633 kvm_vcpu_reset(vcpu, false);
11634 kvm_init_mmu(vcpu);
11639 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11641 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11642 free_wbinvd_dirty_mask:
11643 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11644 fail_free_mce_banks:
11645 kfree(vcpu->arch.mce_banks);
11646 kfree(vcpu->arch.mci_ctl2_banks);
11647 free_page((unsigned long)vcpu->arch.pio_data);
11649 kvm_free_lapic(vcpu);
11651 kvm_mmu_destroy(vcpu);
11655 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
11657 struct kvm *kvm = vcpu->kvm;
11659 if (mutex_lock_killable(&vcpu->mutex))
11662 kvm_synchronize_tsc(vcpu, 0);
11665 /* poll control enabled by default */
11666 vcpu->arch.msr_kvm_poll_control = 1;
11668 mutex_unlock(&vcpu->mutex);
11670 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
11671 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
11672 KVMCLOCK_SYNC_PERIOD);
11675 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
11679 kvmclock_reset(vcpu);
11681 static_call(kvm_x86_vcpu_free)(vcpu);
11683 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11684 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11685 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11687 kvm_xen_destroy_vcpu(vcpu);
11688 kvm_hv_vcpu_uninit(vcpu);
11689 kvm_pmu_destroy(vcpu);
11690 kfree(vcpu->arch.mce_banks);
11691 kfree(vcpu->arch.mci_ctl2_banks);
11692 kvm_free_lapic(vcpu);
11693 idx = srcu_read_lock(&vcpu->kvm->srcu);
11694 kvm_mmu_destroy(vcpu);
11695 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11696 free_page((unsigned long)vcpu->arch.pio_data);
11697 kvfree(vcpu->arch.cpuid_entries);
11698 if (!lapic_in_kernel(vcpu))
11699 static_branch_dec(&kvm_has_noapic_vcpu);
11702 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
11704 struct kvm_cpuid_entry2 *cpuid_0x1;
11705 unsigned long old_cr0 = kvm_read_cr0(vcpu);
11706 unsigned long new_cr0;
11709 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
11710 * to handle side effects. RESET emulation hits those flows and relies
11711 * on emulated/virtualized registers, including those that are loaded
11712 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
11713 * to detect improper or missing initialization.
11715 WARN_ON_ONCE(!init_event &&
11716 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
11718 kvm_lapic_reset(vcpu, init_event);
11720 vcpu->arch.hflags = 0;
11722 vcpu->arch.smi_pending = 0;
11723 vcpu->arch.smi_count = 0;
11724 atomic_set(&vcpu->arch.nmi_queued, 0);
11725 vcpu->arch.nmi_pending = 0;
11726 vcpu->arch.nmi_injected = false;
11727 kvm_clear_interrupt_queue(vcpu);
11728 kvm_clear_exception_queue(vcpu);
11730 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
11731 kvm_update_dr0123(vcpu);
11732 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
11733 vcpu->arch.dr7 = DR7_FIXED_1;
11734 kvm_update_dr7(vcpu);
11736 vcpu->arch.cr2 = 0;
11738 kvm_make_request(KVM_REQ_EVENT, vcpu);
11739 vcpu->arch.apf.msr_en_val = 0;
11740 vcpu->arch.apf.msr_int_val = 0;
11741 vcpu->arch.st.msr_val = 0;
11743 kvmclock_reset(vcpu);
11745 kvm_clear_async_pf_completion_queue(vcpu);
11746 kvm_async_pf_hash_reset(vcpu);
11747 vcpu->arch.apf.halted = false;
11749 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
11750 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
11753 * To avoid have the INIT path from kvm_apic_has_events() that be
11754 * called with loaded FPU and does not let userspace fix the state.
11757 kvm_put_guest_fpu(vcpu);
11759 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
11760 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
11763 kvm_load_guest_fpu(vcpu);
11767 kvm_pmu_reset(vcpu);
11768 vcpu->arch.smbase = 0x30000;
11770 vcpu->arch.msr_misc_features_enables = 0;
11771 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
11772 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
11774 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
11775 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
11778 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
11779 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
11780 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
11783 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
11784 * if no CPUID match is found. Note, it's impossible to get a match at
11785 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
11786 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
11787 * on RESET. But, go through the motions in case that's ever remedied.
11789 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1);
11790 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
11792 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
11794 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
11795 kvm_rip_write(vcpu, 0xfff0);
11797 vcpu->arch.cr3 = 0;
11798 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11801 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
11802 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
11803 * (or qualify) that with a footnote stating that CD/NW are preserved.
11805 new_cr0 = X86_CR0_ET;
11807 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
11809 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
11811 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
11812 static_call(kvm_x86_set_cr4)(vcpu, 0);
11813 static_call(kvm_x86_set_efer)(vcpu, 0);
11814 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11817 * On the standard CR0/CR4/EFER modification paths, there are several
11818 * complex conditions determining whether the MMU has to be reset and/or
11819 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
11820 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
11821 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
11822 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
11824 if (old_cr0 & X86_CR0_PG) {
11825 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11826 kvm_mmu_reset_context(vcpu);
11830 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
11831 * APM states the TLBs are untouched by INIT, but it also states that
11832 * the TLBs are flushed on "External initialization of the processor."
11833 * Flush the guest TLB regardless of vendor, there is no meaningful
11834 * benefit in relying on the guest to flush the TLB immediately after
11835 * INIT. A spurious TLB flush is benign and likely negligible from a
11836 * performance perspective.
11839 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11841 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
11843 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
11845 struct kvm_segment cs;
11847 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
11848 cs.selector = vector << 8;
11849 cs.base = vector << 12;
11850 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
11851 kvm_rip_write(vcpu, 0);
11853 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
11855 int kvm_arch_hardware_enable(void)
11858 struct kvm_vcpu *vcpu;
11863 bool stable, backwards_tsc = false;
11865 kvm_user_return_msr_cpu_online();
11866 ret = static_call(kvm_x86_hardware_enable)();
11870 local_tsc = rdtsc();
11871 stable = !kvm_check_tsc_unstable();
11872 list_for_each_entry(kvm, &vm_list, vm_list) {
11873 kvm_for_each_vcpu(i, vcpu, kvm) {
11874 if (!stable && vcpu->cpu == smp_processor_id())
11875 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
11876 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
11877 backwards_tsc = true;
11878 if (vcpu->arch.last_host_tsc > max_tsc)
11879 max_tsc = vcpu->arch.last_host_tsc;
11885 * Sometimes, even reliable TSCs go backwards. This happens on
11886 * platforms that reset TSC during suspend or hibernate actions, but
11887 * maintain synchronization. We must compensate. Fortunately, we can
11888 * detect that condition here, which happens early in CPU bringup,
11889 * before any KVM threads can be running. Unfortunately, we can't
11890 * bring the TSCs fully up to date with real time, as we aren't yet far
11891 * enough into CPU bringup that we know how much real time has actually
11892 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
11893 * variables that haven't been updated yet.
11895 * So we simply find the maximum observed TSC above, then record the
11896 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
11897 * the adjustment will be applied. Note that we accumulate
11898 * adjustments, in case multiple suspend cycles happen before some VCPU
11899 * gets a chance to run again. In the event that no KVM threads get a
11900 * chance to run, we will miss the entire elapsed period, as we'll have
11901 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
11902 * loose cycle time. This isn't too big a deal, since the loss will be
11903 * uniform across all VCPUs (not to mention the scenario is extremely
11904 * unlikely). It is possible that a second hibernate recovery happens
11905 * much faster than a first, causing the observed TSC here to be
11906 * smaller; this would require additional padding adjustment, which is
11907 * why we set last_host_tsc to the local tsc observed here.
11909 * N.B. - this code below runs only on platforms with reliable TSC,
11910 * as that is the only way backwards_tsc is set above. Also note
11911 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
11912 * have the same delta_cyc adjustment applied if backwards_tsc
11913 * is detected. Note further, this adjustment is only done once,
11914 * as we reset last_host_tsc on all VCPUs to stop this from being
11915 * called multiple times (one for each physical CPU bringup).
11917 * Platforms with unreliable TSCs don't have to deal with this, they
11918 * will be compensated by the logic in vcpu_load, which sets the TSC to
11919 * catchup mode. This will catchup all VCPUs to real time, but cannot
11920 * guarantee that they stay in perfect synchronization.
11922 if (backwards_tsc) {
11923 u64 delta_cyc = max_tsc - local_tsc;
11924 list_for_each_entry(kvm, &vm_list, vm_list) {
11925 kvm->arch.backwards_tsc_observed = true;
11926 kvm_for_each_vcpu(i, vcpu, kvm) {
11927 vcpu->arch.tsc_offset_adjustment += delta_cyc;
11928 vcpu->arch.last_host_tsc = local_tsc;
11929 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
11933 * We have to disable TSC offset matching.. if you were
11934 * booting a VM while issuing an S4 host suspend....
11935 * you may have some problem. Solving this issue is
11936 * left as an exercise to the reader.
11938 kvm->arch.last_tsc_nsec = 0;
11939 kvm->arch.last_tsc_write = 0;
11946 void kvm_arch_hardware_disable(void)
11948 static_call(kvm_x86_hardware_disable)();
11949 drop_user_return_notifiers();
11952 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops)
11954 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
11956 #define __KVM_X86_OP(func) \
11957 static_call_update(kvm_x86_##func, kvm_x86_ops.func);
11958 #define KVM_X86_OP(func) \
11959 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func)
11960 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP
11961 #define KVM_X86_OP_OPTIONAL_RET0(func) \
11962 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \
11963 (void *)__static_call_return0);
11964 #include <asm/kvm-x86-ops.h>
11965 #undef __KVM_X86_OP
11967 kvm_pmu_ops_update(ops->pmu_ops);
11970 int kvm_arch_hardware_setup(void *opaque)
11972 struct kvm_x86_init_ops *ops = opaque;
11975 rdmsrl_safe(MSR_EFER, &host_efer);
11977 if (boot_cpu_has(X86_FEATURE_XSAVES))
11978 rdmsrl(MSR_IA32_XSS, host_xss);
11980 kvm_init_pmu_capability();
11982 r = ops->hardware_setup();
11986 kvm_ops_update(ops);
11988 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
11990 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
11991 kvm_caps.supported_xss = 0;
11993 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
11994 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
11995 #undef __kvm_cpu_cap_has
11997 if (kvm_caps.has_tsc_control) {
11999 * Make sure the user can only configure tsc_khz values that
12000 * fit into a signed integer.
12001 * A min value is not calculated because it will always
12002 * be 1 on all machines.
12004 u64 max = min(0x7fffffffULL,
12005 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz));
12006 kvm_caps.max_guest_tsc_khz = max;
12008 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits;
12009 kvm_init_msr_list();
12013 void kvm_arch_hardware_unsetup(void)
12015 kvm_unregister_perf_callbacks();
12017 static_call(kvm_x86_hardware_unsetup)();
12020 int kvm_arch_check_processor_compat(void *opaque)
12022 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
12023 struct kvm_x86_init_ops *ops = opaque;
12025 WARN_ON(!irqs_disabled());
12027 if (__cr4_reserved_bits(cpu_has, c) !=
12028 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
12031 return ops->check_processor_compatibility();
12034 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
12036 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
12038 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
12040 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
12042 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
12045 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
12046 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
12048 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
12050 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
12052 vcpu->arch.l1tf_flush_l1d = true;
12053 if (pmu->version && unlikely(pmu->event_count)) {
12054 pmu->need_cleanup = true;
12055 kvm_make_request(KVM_REQ_PMU, vcpu);
12057 static_call(kvm_x86_sched_in)(vcpu, cpu);
12060 void kvm_arch_free_vm(struct kvm *kvm)
12062 kfree(to_kvm_hv(kvm)->hv_pa_pg);
12063 __kvm_arch_free_vm(kvm);
12067 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
12070 unsigned long flags;
12075 ret = kvm_page_track_init(kvm);
12079 ret = kvm_mmu_init_vm(kvm);
12081 goto out_page_track;
12083 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
12084 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
12085 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
12087 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
12088 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
12089 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
12090 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
12091 &kvm->arch.irq_sources_bitmap);
12093 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
12094 mutex_init(&kvm->arch.apic_map_lock);
12095 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
12096 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
12098 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
12099 pvclock_update_vm_gtod_copy(kvm);
12100 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
12102 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz;
12103 kvm->arch.guest_can_read_msr_platform_info = true;
12104 kvm->arch.enable_pmu = enable_pmu;
12106 #if IS_ENABLED(CONFIG_HYPERV)
12107 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
12108 kvm->arch.hv_root_tdp = INVALID_PAGE;
12111 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
12112 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
12114 kvm_apicv_init(kvm);
12115 kvm_hv_init_vm(kvm);
12116 kvm_xen_init_vm(kvm);
12118 return static_call(kvm_x86_vm_init)(kvm);
12121 kvm_page_track_cleanup(kvm);
12126 int kvm_arch_post_init_vm(struct kvm *kvm)
12128 return kvm_mmu_post_init_vm(kvm);
12131 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
12134 kvm_mmu_unload(vcpu);
12138 static void kvm_unload_vcpu_mmus(struct kvm *kvm)
12141 struct kvm_vcpu *vcpu;
12143 kvm_for_each_vcpu(i, vcpu, kvm) {
12144 kvm_clear_async_pf_completion_queue(vcpu);
12145 kvm_unload_vcpu_mmu(vcpu);
12149 void kvm_arch_sync_events(struct kvm *kvm)
12151 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
12152 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
12157 * __x86_set_memory_region: Setup KVM internal memory slot
12159 * @kvm: the kvm pointer to the VM.
12160 * @id: the slot ID to setup.
12161 * @gpa: the GPA to install the slot (unused when @size == 0).
12162 * @size: the size of the slot. Set to zero to uninstall a slot.
12164 * This function helps to setup a KVM internal memory slot. Specify
12165 * @size > 0 to install a new slot, while @size == 0 to uninstall a
12166 * slot. The return code can be one of the following:
12168 * HVA: on success (uninstall will return a bogus HVA)
12171 * The caller should always use IS_ERR() to check the return value
12172 * before use. Note, the KVM internal memory slots are guaranteed to
12173 * remain valid and unchanged until the VM is destroyed, i.e., the
12174 * GPA->HVA translation will not change. However, the HVA is a user
12175 * address, i.e. its accessibility is not guaranteed, and must be
12176 * accessed via __copy_{to,from}_user().
12178 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
12182 unsigned long hva, old_npages;
12183 struct kvm_memslots *slots = kvm_memslots(kvm);
12184 struct kvm_memory_slot *slot;
12186 /* Called with kvm->slots_lock held. */
12187 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
12188 return ERR_PTR_USR(-EINVAL);
12190 slot = id_to_memslot(slots, id);
12192 if (slot && slot->npages)
12193 return ERR_PTR_USR(-EEXIST);
12196 * MAP_SHARED to prevent internal slot pages from being moved
12199 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
12200 MAP_SHARED | MAP_ANONYMOUS, 0);
12201 if (IS_ERR((void *)hva))
12202 return (void __user *)hva;
12204 if (!slot || !slot->npages)
12207 old_npages = slot->npages;
12208 hva = slot->userspace_addr;
12211 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
12212 struct kvm_userspace_memory_region m;
12214 m.slot = id | (i << 16);
12216 m.guest_phys_addr = gpa;
12217 m.userspace_addr = hva;
12218 m.memory_size = size;
12219 r = __kvm_set_memory_region(kvm, &m);
12221 return ERR_PTR_USR(r);
12225 vm_munmap(hva, old_npages * PAGE_SIZE);
12227 return (void __user *)hva;
12229 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
12231 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
12233 kvm_mmu_pre_destroy_vm(kvm);
12236 void kvm_arch_destroy_vm(struct kvm *kvm)
12238 if (current->mm == kvm->mm) {
12240 * Free memory regions allocated on behalf of userspace,
12241 * unless the memory map has changed due to process exit
12244 mutex_lock(&kvm->slots_lock);
12245 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
12247 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
12249 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
12250 mutex_unlock(&kvm->slots_lock);
12252 kvm_unload_vcpu_mmus(kvm);
12253 static_call_cond(kvm_x86_vm_destroy)(kvm);
12254 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
12255 kvm_pic_destroy(kvm);
12256 kvm_ioapic_destroy(kvm);
12257 kvm_destroy_vcpus(kvm);
12258 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
12259 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
12260 kvm_mmu_uninit_vm(kvm);
12261 kvm_page_track_cleanup(kvm);
12262 kvm_xen_destroy_vm(kvm);
12263 kvm_hv_destroy_vm(kvm);
12266 static void memslot_rmap_free(struct kvm_memory_slot *slot)
12270 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12271 kvfree(slot->arch.rmap[i]);
12272 slot->arch.rmap[i] = NULL;
12276 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
12280 memslot_rmap_free(slot);
12282 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12283 kvfree(slot->arch.lpage_info[i - 1]);
12284 slot->arch.lpage_info[i - 1] = NULL;
12287 kvm_page_track_free_memslot(slot);
12290 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
12292 const int sz = sizeof(*slot->arch.rmap[0]);
12295 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12297 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12299 if (slot->arch.rmap[i])
12302 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
12303 if (!slot->arch.rmap[i]) {
12304 memslot_rmap_free(slot);
12312 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
12313 struct kvm_memory_slot *slot)
12315 unsigned long npages = slot->npages;
12319 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
12320 * old arrays will be freed by __kvm_set_memory_region() if installing
12321 * the new memslot is successful.
12323 memset(&slot->arch, 0, sizeof(slot->arch));
12325 if (kvm_memslots_have_rmaps(kvm)) {
12326 r = memslot_rmap_alloc(slot, npages);
12331 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12332 struct kvm_lpage_info *linfo;
12333 unsigned long ugfn;
12337 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12339 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
12343 slot->arch.lpage_info[i - 1] = linfo;
12345 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
12346 linfo[0].disallow_lpage = 1;
12347 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
12348 linfo[lpages - 1].disallow_lpage = 1;
12349 ugfn = slot->userspace_addr >> PAGE_SHIFT;
12351 * If the gfn and userspace address are not aligned wrt each
12352 * other, disable large page support for this slot.
12354 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
12357 for (j = 0; j < lpages; ++j)
12358 linfo[j].disallow_lpage = 1;
12362 if (kvm_page_track_create_memslot(kvm, slot, npages))
12368 memslot_rmap_free(slot);
12370 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12371 kvfree(slot->arch.lpage_info[i - 1]);
12372 slot->arch.lpage_info[i - 1] = NULL;
12377 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
12379 struct kvm_vcpu *vcpu;
12383 * memslots->generation has been incremented.
12384 * mmio generation may have reached its maximum value.
12386 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
12388 /* Force re-initialization of steal_time cache */
12389 kvm_for_each_vcpu(i, vcpu, kvm)
12390 kvm_vcpu_kick(vcpu);
12393 int kvm_arch_prepare_memory_region(struct kvm *kvm,
12394 const struct kvm_memory_slot *old,
12395 struct kvm_memory_slot *new,
12396 enum kvm_mr_change change)
12398 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
12399 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
12402 return kvm_alloc_memslot_metadata(kvm, new);
12405 if (change == KVM_MR_FLAGS_ONLY)
12406 memcpy(&new->arch, &old->arch, sizeof(old->arch));
12407 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12414 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12416 struct kvm_arch *ka = &kvm->arch;
12418 if (!kvm_x86_ops.cpu_dirty_log_size)
12421 if ((enable && ++ka->cpu_dirty_logging_count == 1) ||
12422 (!enable && --ka->cpu_dirty_logging_count == 0))
12423 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12425 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0);
12428 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12429 struct kvm_memory_slot *old,
12430 const struct kvm_memory_slot *new,
12431 enum kvm_mr_change change)
12433 u32 old_flags = old ? old->flags : 0;
12434 u32 new_flags = new ? new->flags : 0;
12435 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12438 * Update CPU dirty logging if dirty logging is being toggled. This
12439 * applies to all operations.
12441 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12442 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12445 * Nothing more to do for RO slots (which can't be dirtied and can't be
12446 * made writable) or CREATE/MOVE/DELETE of a slot.
12448 * For a memslot with dirty logging disabled:
12449 * CREATE: No dirty mappings will already exist.
12450 * MOVE/DELETE: The old mappings will already have been cleaned up by
12451 * kvm_arch_flush_shadow_memslot()
12453 * For a memslot with dirty logging enabled:
12454 * CREATE: No shadow pages exist, thus nothing to write-protect
12455 * and no dirty bits to clear.
12456 * MOVE/DELETE: The old mappings will already have been cleaned up by
12457 * kvm_arch_flush_shadow_memslot().
12459 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12463 * READONLY and non-flags changes were filtered out above, and the only
12464 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12465 * logging isn't being toggled on or off.
12467 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12470 if (!log_dirty_pages) {
12472 * Dirty logging tracks sptes in 4k granularity, meaning that
12473 * large sptes have to be split. If live migration succeeds,
12474 * the guest in the source machine will be destroyed and large
12475 * sptes will be created in the destination. However, if the
12476 * guest continues to run in the source machine (for example if
12477 * live migration fails), small sptes will remain around and
12478 * cause bad performance.
12480 * Scan sptes if dirty logging has been stopped, dropping those
12481 * which can be collapsed into a single large-page spte. Later
12482 * page faults will create the large-page sptes.
12484 kvm_mmu_zap_collapsible_sptes(kvm, new);
12487 * Initially-all-set does not require write protecting any page,
12488 * because they're all assumed to be dirty.
12490 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12493 if (READ_ONCE(eager_page_split))
12494 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12496 if (kvm_x86_ops.cpu_dirty_log_size) {
12497 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12498 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12500 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12504 * Unconditionally flush the TLBs after enabling dirty logging.
12505 * A flush is almost always going to be necessary (see below),
12506 * and unconditionally flushing allows the helpers to omit
12507 * the subtly complex checks when removing write access.
12509 * Do the flush outside of mmu_lock to reduce the amount of
12510 * time mmu_lock is held. Flushing after dropping mmu_lock is
12511 * safe as KVM only needs to guarantee the slot is fully
12512 * write-protected before returning to userspace, i.e. before
12513 * userspace can consume the dirty status.
12515 * Flushing outside of mmu_lock requires KVM to be careful when
12516 * making decisions based on writable status of an SPTE, e.g. a
12517 * !writable SPTE doesn't guarantee a CPU can't perform writes.
12519 * Specifically, KVM also write-protects guest page tables to
12520 * monitor changes when using shadow paging, and must guarantee
12521 * no CPUs can write to those page before mmu_lock is dropped.
12522 * Because CPUs may have stale TLB entries at this point, a
12523 * !writable SPTE doesn't guarantee CPUs can't perform writes.
12525 * KVM also allows making SPTES writable outside of mmu_lock,
12526 * e.g. to allow dirty logging without taking mmu_lock.
12528 * To handle these scenarios, KVM uses a separate software-only
12529 * bit (MMU-writable) to track if a SPTE is !writable due to
12530 * a guest page table being write-protected (KVM clears the
12531 * MMU-writable flag when write-protecting for shadow paging).
12533 * The use of MMU-writable is also the primary motivation for
12534 * the unconditional flush. Because KVM must guarantee that a
12535 * CPU doesn't contain stale, writable TLB entries for a
12536 * !MMU-writable SPTE, KVM must flush if it encounters any
12537 * MMU-writable SPTE regardless of whether the actual hardware
12538 * writable bit was set. I.e. KVM is almost guaranteed to need
12539 * to flush, while unconditionally flushing allows the "remove
12540 * write access" helpers to ignore MMU-writable entirely.
12542 * See is_writable_pte() for more details (the case involving
12543 * access-tracked SPTEs is particularly relevant).
12545 kvm_arch_flush_remote_tlbs_memslot(kvm, new);
12549 void kvm_arch_commit_memory_region(struct kvm *kvm,
12550 struct kvm_memory_slot *old,
12551 const struct kvm_memory_slot *new,
12552 enum kvm_mr_change change)
12554 if (!kvm->arch.n_requested_mmu_pages &&
12555 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
12556 unsigned long nr_mmu_pages;
12558 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
12559 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
12560 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
12563 kvm_mmu_slot_apply_flags(kvm, old, new, change);
12565 /* Free the arrays associated with the old memslot. */
12566 if (change == KVM_MR_MOVE)
12567 kvm_arch_free_memslot(kvm, old);
12570 void kvm_arch_flush_shadow_all(struct kvm *kvm)
12572 kvm_mmu_zap_all(kvm);
12575 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
12576 struct kvm_memory_slot *slot)
12578 kvm_page_track_flush_slot(kvm, slot);
12581 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
12583 return (is_guest_mode(vcpu) &&
12584 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
12587 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
12589 if (!list_empty_careful(&vcpu->async_pf.done))
12592 if (kvm_apic_has_events(vcpu))
12595 if (vcpu->arch.pv.pv_unhalted)
12598 if (vcpu->arch.exception.pending)
12601 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12602 (vcpu->arch.nmi_pending &&
12603 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
12606 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
12607 (vcpu->arch.smi_pending &&
12608 static_call(kvm_x86_smi_allowed)(vcpu, false)))
12611 if (kvm_arch_interrupt_allowed(vcpu) &&
12612 (kvm_cpu_has_interrupt(vcpu) ||
12613 kvm_guest_apic_has_interrupt(vcpu)))
12616 if (kvm_hv_has_stimer_pending(vcpu))
12619 if (is_guest_mode(vcpu) &&
12620 kvm_x86_ops.nested_ops->hv_timer_pending &&
12621 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
12624 if (kvm_xen_has_pending_events(vcpu))
12627 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu))
12633 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
12635 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
12638 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
12640 if (kvm_vcpu_apicv_active(vcpu) &&
12641 static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
12647 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
12649 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
12652 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12653 kvm_test_request(KVM_REQ_SMI, vcpu) ||
12654 kvm_test_request(KVM_REQ_EVENT, vcpu))
12657 return kvm_arch_dy_has_pending_interrupt(vcpu);
12660 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
12662 if (vcpu->arch.guest_state_protected)
12665 return vcpu->arch.preempted_in_kernel;
12668 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
12670 return kvm_rip_read(vcpu);
12673 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
12675 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
12678 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
12680 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
12683 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
12685 /* Can't read the RIP when guest state is protected, just return 0 */
12686 if (vcpu->arch.guest_state_protected)
12689 if (is_64_bit_mode(vcpu))
12690 return kvm_rip_read(vcpu);
12691 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
12692 kvm_rip_read(vcpu));
12694 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
12696 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
12698 return kvm_get_linear_rip(vcpu) == linear_rip;
12700 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
12702 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
12704 unsigned long rflags;
12706 rflags = static_call(kvm_x86_get_rflags)(vcpu);
12707 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
12708 rflags &= ~X86_EFLAGS_TF;
12711 EXPORT_SYMBOL_GPL(kvm_get_rflags);
12713 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12715 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
12716 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
12717 rflags |= X86_EFLAGS_TF;
12718 static_call(kvm_x86_set_rflags)(vcpu, rflags);
12721 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12723 __kvm_set_rflags(vcpu, rflags);
12724 kvm_make_request(KVM_REQ_EVENT, vcpu);
12726 EXPORT_SYMBOL_GPL(kvm_set_rflags);
12728 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
12730 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
12732 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
12735 static inline u32 kvm_async_pf_next_probe(u32 key)
12737 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
12740 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12742 u32 key = kvm_async_pf_hash_fn(gfn);
12744 while (vcpu->arch.apf.gfns[key] != ~0)
12745 key = kvm_async_pf_next_probe(key);
12747 vcpu->arch.apf.gfns[key] = gfn;
12750 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
12753 u32 key = kvm_async_pf_hash_fn(gfn);
12755 for (i = 0; i < ASYNC_PF_PER_VCPU &&
12756 (vcpu->arch.apf.gfns[key] != gfn &&
12757 vcpu->arch.apf.gfns[key] != ~0); i++)
12758 key = kvm_async_pf_next_probe(key);
12763 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12765 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
12768 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12772 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
12774 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
12778 vcpu->arch.apf.gfns[i] = ~0;
12780 j = kvm_async_pf_next_probe(j);
12781 if (vcpu->arch.apf.gfns[j] == ~0)
12783 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
12785 * k lies cyclically in ]i,j]
12787 * |....j i.k.| or |.k..j i...|
12789 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
12790 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
12795 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
12797 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
12799 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
12803 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
12805 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12807 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12808 &token, offset, sizeof(token));
12811 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
12813 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12816 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12817 &val, offset, sizeof(val)))
12823 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
12826 if (!kvm_pv_async_pf_enabled(vcpu))
12829 if (vcpu->arch.apf.send_user_only &&
12830 static_call(kvm_x86_get_cpl)(vcpu) == 0)
12833 if (is_guest_mode(vcpu)) {
12835 * L1 needs to opt into the special #PF vmexits that are
12836 * used to deliver async page faults.
12838 return vcpu->arch.apf.delivery_as_pf_vmexit;
12841 * Play it safe in case the guest temporarily disables paging.
12842 * The real mode IDT in particular is unlikely to have a #PF
12845 return is_paging(vcpu);
12849 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
12851 if (unlikely(!lapic_in_kernel(vcpu) ||
12852 kvm_event_needs_reinjection(vcpu) ||
12853 vcpu->arch.exception.pending))
12856 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
12860 * If interrupts are off we cannot even use an artificial
12863 return kvm_arch_interrupt_allowed(vcpu);
12866 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
12867 struct kvm_async_pf *work)
12869 struct x86_exception fault;
12871 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
12872 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
12874 if (kvm_can_deliver_async_pf(vcpu) &&
12875 !apf_put_user_notpresent(vcpu)) {
12876 fault.vector = PF_VECTOR;
12877 fault.error_code_valid = true;
12878 fault.error_code = 0;
12879 fault.nested_page_fault = false;
12880 fault.address = work->arch.token;
12881 fault.async_page_fault = true;
12882 kvm_inject_page_fault(vcpu, &fault);
12886 * It is not possible to deliver a paravirtualized asynchronous
12887 * page fault, but putting the guest in an artificial halt state
12888 * can be beneficial nevertheless: if an interrupt arrives, we
12889 * can deliver it timely and perhaps the guest will schedule
12890 * another process. When the instruction that triggered a page
12891 * fault is retried, hopefully the page will be ready in the host.
12893 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
12898 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
12899 struct kvm_async_pf *work)
12901 struct kvm_lapic_irq irq = {
12902 .delivery_mode = APIC_DM_FIXED,
12903 .vector = vcpu->arch.apf.vec
12906 if (work->wakeup_all)
12907 work->arch.token = ~0; /* broadcast wakeup */
12909 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
12910 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
12912 if ((work->wakeup_all || work->notpresent_injected) &&
12913 kvm_pv_async_pf_enabled(vcpu) &&
12914 !apf_put_user_ready(vcpu, work->arch.token)) {
12915 vcpu->arch.apf.pageready_pending = true;
12916 kvm_apic_set_irq(vcpu, &irq, NULL);
12919 vcpu->arch.apf.halted = false;
12920 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12923 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
12925 kvm_make_request(KVM_REQ_APF_READY, vcpu);
12926 if (!vcpu->arch.apf.pageready_pending)
12927 kvm_vcpu_kick(vcpu);
12930 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
12932 if (!kvm_pv_async_pf_enabled(vcpu))
12935 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
12938 void kvm_arch_start_assignment(struct kvm *kvm)
12940 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
12941 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
12943 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
12945 void kvm_arch_end_assignment(struct kvm *kvm)
12947 atomic_dec(&kvm->arch.assigned_device_count);
12949 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
12951 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm)
12953 return arch_atomic_read(&kvm->arch.assigned_device_count);
12955 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
12957 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
12959 atomic_inc(&kvm->arch.noncoherent_dma_count);
12961 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
12963 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
12965 atomic_dec(&kvm->arch.noncoherent_dma_count);
12967 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
12969 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
12971 return atomic_read(&kvm->arch.noncoherent_dma_count);
12973 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
12975 bool kvm_arch_has_irq_bypass(void)
12980 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
12981 struct irq_bypass_producer *prod)
12983 struct kvm_kernel_irqfd *irqfd =
12984 container_of(cons, struct kvm_kernel_irqfd, consumer);
12987 irqfd->producer = prod;
12988 kvm_arch_start_assignment(irqfd->kvm);
12989 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
12990 prod->irq, irqfd->gsi, 1);
12993 kvm_arch_end_assignment(irqfd->kvm);
12998 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
12999 struct irq_bypass_producer *prod)
13002 struct kvm_kernel_irqfd *irqfd =
13003 container_of(cons, struct kvm_kernel_irqfd, consumer);
13005 WARN_ON(irqfd->producer != prod);
13006 irqfd->producer = NULL;
13009 * When producer of consumer is unregistered, we change back to
13010 * remapped mode, so we can re-use the current implementation
13011 * when the irq is masked/disabled or the consumer side (KVM
13012 * int this case doesn't want to receive the interrupts.
13014 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
13016 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
13017 " fails: %d\n", irqfd->consumer.token, ret);
13019 kvm_arch_end_assignment(irqfd->kvm);
13022 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
13023 uint32_t guest_irq, bool set)
13025 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
13028 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
13029 struct kvm_kernel_irq_routing_entry *new)
13031 if (new->type != KVM_IRQ_ROUTING_MSI)
13034 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
13037 bool kvm_vector_hashing_enabled(void)
13039 return vector_hashing;
13042 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
13044 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
13046 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
13049 int kvm_spec_ctrl_test_value(u64 value)
13052 * test that setting IA32_SPEC_CTRL to given value
13053 * is allowed by the host processor
13057 unsigned long flags;
13060 local_irq_save(flags);
13062 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
13064 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
13067 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
13069 local_irq_restore(flags);
13073 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
13075 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
13077 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
13078 struct x86_exception fault;
13079 u64 access = error_code &
13080 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
13082 if (!(error_code & PFERR_PRESENT_MASK) ||
13083 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) {
13085 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
13086 * tables probably do not match the TLB. Just proceed
13087 * with the error code that the processor gave.
13089 fault.vector = PF_VECTOR;
13090 fault.error_code_valid = true;
13091 fault.error_code = error_code;
13092 fault.nested_page_fault = false;
13093 fault.address = gva;
13094 fault.async_page_fault = false;
13096 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
13098 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
13101 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
13102 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
13103 * indicates whether exit to userspace is needed.
13105 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
13106 struct x86_exception *e)
13108 if (r == X86EMUL_PROPAGATE_FAULT) {
13109 kvm_inject_emulated_page_fault(vcpu, e);
13114 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
13115 * while handling a VMX instruction KVM could've handled the request
13116 * correctly by exiting to userspace and performing I/O but there
13117 * doesn't seem to be a real use-case behind such requests, just return
13118 * KVM_EXIT_INTERNAL_ERROR for now.
13120 kvm_prepare_emulation_failure_exit(vcpu);
13124 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
13126 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
13129 struct x86_exception e;
13136 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
13137 if (r != X86EMUL_CONTINUE)
13138 return kvm_handle_memory_failure(vcpu, r, &e);
13140 if (operand.pcid >> 12 != 0) {
13141 kvm_inject_gp(vcpu, 0);
13145 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
13148 case INVPCID_TYPE_INDIV_ADDR:
13149 if ((!pcid_enabled && (operand.pcid != 0)) ||
13150 is_noncanonical_address(operand.gla, vcpu)) {
13151 kvm_inject_gp(vcpu, 0);
13154 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
13155 return kvm_skip_emulated_instruction(vcpu);
13157 case INVPCID_TYPE_SINGLE_CTXT:
13158 if (!pcid_enabled && (operand.pcid != 0)) {
13159 kvm_inject_gp(vcpu, 0);
13163 kvm_invalidate_pcid(vcpu, operand.pcid);
13164 return kvm_skip_emulated_instruction(vcpu);
13166 case INVPCID_TYPE_ALL_NON_GLOBAL:
13168 * Currently, KVM doesn't mark global entries in the shadow
13169 * page tables, so a non-global flush just degenerates to a
13170 * global flush. If needed, we could optimize this later by
13171 * keeping track of global entries in shadow page tables.
13175 case INVPCID_TYPE_ALL_INCL_GLOBAL:
13176 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
13177 return kvm_skip_emulated_instruction(vcpu);
13180 kvm_inject_gp(vcpu, 0);
13184 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
13186 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
13188 struct kvm_run *run = vcpu->run;
13189 struct kvm_mmio_fragment *frag;
13192 BUG_ON(!vcpu->mmio_needed);
13194 /* Complete previous fragment */
13195 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
13196 len = min(8u, frag->len);
13197 if (!vcpu->mmio_is_write)
13198 memcpy(frag->data, run->mmio.data, len);
13200 if (frag->len <= 8) {
13201 /* Switch to the next fragment. */
13203 vcpu->mmio_cur_fragment++;
13205 /* Go forward to the next mmio piece. */
13211 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
13212 vcpu->mmio_needed = 0;
13214 // VMG change, at this point, we're always done
13215 // RIP has already been advanced
13219 // More MMIO is needed
13220 run->mmio.phys_addr = frag->gpa;
13221 run->mmio.len = min(8u, frag->len);
13222 run->mmio.is_write = vcpu->mmio_is_write;
13223 if (run->mmio.is_write)
13224 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
13225 run->exit_reason = KVM_EXIT_MMIO;
13227 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13232 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13236 struct kvm_mmio_fragment *frag;
13241 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13242 if (handled == bytes)
13249 /*TODO: Check if need to increment number of frags */
13250 frag = vcpu->mmio_fragments;
13251 vcpu->mmio_nr_fragments = 1;
13256 vcpu->mmio_needed = 1;
13257 vcpu->mmio_cur_fragment = 0;
13259 vcpu->run->mmio.phys_addr = gpa;
13260 vcpu->run->mmio.len = min(8u, frag->len);
13261 vcpu->run->mmio.is_write = 1;
13262 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
13263 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13265 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13269 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
13271 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13275 struct kvm_mmio_fragment *frag;
13280 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13281 if (handled == bytes)
13288 /*TODO: Check if need to increment number of frags */
13289 frag = vcpu->mmio_fragments;
13290 vcpu->mmio_nr_fragments = 1;
13295 vcpu->mmio_needed = 1;
13296 vcpu->mmio_cur_fragment = 0;
13298 vcpu->run->mmio.phys_addr = gpa;
13299 vcpu->run->mmio.len = min(8u, frag->len);
13300 vcpu->run->mmio.is_write = 0;
13301 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13303 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13307 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
13309 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size)
13311 vcpu->arch.sev_pio_count -= count;
13312 vcpu->arch.sev_pio_data += count * size;
13315 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13316 unsigned int port);
13318 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
13320 int size = vcpu->arch.pio.size;
13321 int port = vcpu->arch.pio.port;
13323 vcpu->arch.pio.count = 0;
13324 if (vcpu->arch.sev_pio_count)
13325 return kvm_sev_es_outs(vcpu, size, port);
13329 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13333 unsigned int count =
13334 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13335 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
13337 /* memcpy done already by emulator_pio_out. */
13338 advance_sev_es_emulated_pio(vcpu, count, size);
13342 /* Emulation done by the kernel. */
13343 if (!vcpu->arch.sev_pio_count)
13347 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
13351 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13352 unsigned int port);
13354 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
13356 unsigned count = vcpu->arch.pio.count;
13357 int size = vcpu->arch.pio.size;
13358 int port = vcpu->arch.pio.port;
13360 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
13361 advance_sev_es_emulated_pio(vcpu, count, size);
13362 if (vcpu->arch.sev_pio_count)
13363 return kvm_sev_es_ins(vcpu, size, port);
13367 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13371 unsigned int count =
13372 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13373 if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count))
13376 /* Emulation done by the kernel. */
13377 advance_sev_es_emulated_pio(vcpu, count, size);
13378 if (!vcpu->arch.sev_pio_count)
13382 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
13386 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
13387 unsigned int port, void *data, unsigned int count,
13390 vcpu->arch.sev_pio_data = data;
13391 vcpu->arch.sev_pio_count = count;
13392 return in ? kvm_sev_es_ins(vcpu, size, port)
13393 : kvm_sev_es_outs(vcpu, size, port);
13395 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
13397 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
13398 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
13399 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
13400 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
13401 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
13402 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
13403 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
13404 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
13405 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
13406 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
13407 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
13408 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
13409 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
13410 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
13411 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
13412 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
13413 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
13414 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
13415 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
13416 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
13417 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
13418 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
13419 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath);
13420 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell);
13421 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
13422 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
13423 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
13424 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
13425 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
13427 static int __init kvm_x86_init(void)
13429 kvm_mmu_x86_module_init();
13432 module_init(kvm_x86_init);
13434 static void __exit kvm_x86_exit(void)
13437 * If module_init() is implemented, module_exit() must also be
13438 * implemented to allow module unload.
13441 module_exit(kvm_x86_exit);