2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
58 #include <trace/events/kvm.h>
60 #include <asm/debugreg.h>
64 #include <linux/kernel_stat.h>
65 #include <asm/fpu/internal.h> /* Ugh! */
66 #include <asm/pvclock.h>
67 #include <asm/div64.h>
68 #include <asm/irq_remapping.h>
70 #define CREATE_TRACE_POINTS
73 #define MAX_IO_MSRS 256
74 #define KVM_MAX_MCE_BANKS 32
75 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
78 #define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
87 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
89 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
92 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
95 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
98 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
99 static void process_nmi(struct kvm_vcpu *vcpu);
100 static void enter_smm(struct kvm_vcpu *vcpu);
101 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
103 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
104 EXPORT_SYMBOL_GPL(kvm_x86_ops);
106 static bool __read_mostly ignore_msrs = 0;
107 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
109 unsigned int min_timer_period_us = 500;
110 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
112 static bool __read_mostly kvmclock_periodic_sync = true;
113 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
115 bool __read_mostly kvm_has_tsc_control;
116 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
117 u32 __read_mostly kvm_max_guest_tsc_khz;
118 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
119 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121 u64 __read_mostly kvm_max_tsc_scaling_ratio;
122 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
123 u64 __read_mostly kvm_default_tsc_scaling_ratio;
124 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
126 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
127 static u32 __read_mostly tsc_tolerance_ppm = 250;
128 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
130 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
131 unsigned int __read_mostly lapic_timer_advance_ns = 0;
132 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
134 static bool __read_mostly vector_hashing = true;
135 module_param(vector_hashing, bool, S_IRUGO);
137 #define KVM_NR_SHARED_MSRS 16
139 struct kvm_shared_msrs_global {
141 u32 msrs[KVM_NR_SHARED_MSRS];
144 struct kvm_shared_msrs {
145 struct user_return_notifier urn;
147 struct kvm_shared_msr_values {
150 } values[KVM_NR_SHARED_MSRS];
153 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
154 static struct kvm_shared_msrs __percpu *shared_msrs;
156 struct kvm_stats_debugfs_item debugfs_entries[] = {
157 { "pf_fixed", VCPU_STAT(pf_fixed) },
158 { "pf_guest", VCPU_STAT(pf_guest) },
159 { "tlb_flush", VCPU_STAT(tlb_flush) },
160 { "invlpg", VCPU_STAT(invlpg) },
161 { "exits", VCPU_STAT(exits) },
162 { "io_exits", VCPU_STAT(io_exits) },
163 { "mmio_exits", VCPU_STAT(mmio_exits) },
164 { "signal_exits", VCPU_STAT(signal_exits) },
165 { "irq_window", VCPU_STAT(irq_window_exits) },
166 { "nmi_window", VCPU_STAT(nmi_window_exits) },
167 { "halt_exits", VCPU_STAT(halt_exits) },
168 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
169 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
170 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
171 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
172 { "hypercalls", VCPU_STAT(hypercalls) },
173 { "request_irq", VCPU_STAT(request_irq_exits) },
174 { "irq_exits", VCPU_STAT(irq_exits) },
175 { "host_state_reload", VCPU_STAT(host_state_reload) },
176 { "efer_reload", VCPU_STAT(efer_reload) },
177 { "fpu_reload", VCPU_STAT(fpu_reload) },
178 { "insn_emulation", VCPU_STAT(insn_emulation) },
179 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
180 { "irq_injections", VCPU_STAT(irq_injections) },
181 { "nmi_injections", VCPU_STAT(nmi_injections) },
182 { "req_event", VCPU_STAT(req_event) },
183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
190 { "mmu_unsync", VM_STAT(mmu_unsync) },
191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
192 { "largepages", VM_STAT(lpages) },
193 { "max_mmu_page_hash_collisions",
194 VM_STAT(max_mmu_page_hash_collisions) },
198 u64 __read_mostly host_xcr0;
200 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
202 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
205 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
206 vcpu->arch.apf.gfns[i] = ~0;
209 static void kvm_on_user_return(struct user_return_notifier *urn)
212 struct kvm_shared_msrs *locals
213 = container_of(urn, struct kvm_shared_msrs, urn);
214 struct kvm_shared_msr_values *values;
218 * Disabling irqs at this point since the following code could be
219 * interrupted and executed through kvm_arch_hardware_disable()
221 local_irq_save(flags);
222 if (locals->registered) {
223 locals->registered = false;
224 user_return_notifier_unregister(urn);
226 local_irq_restore(flags);
227 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
228 values = &locals->values[slot];
229 if (values->host != values->curr) {
230 wrmsrl(shared_msrs_global.msrs[slot], values->host);
231 values->curr = values->host;
236 static void shared_msr_update(unsigned slot, u32 msr)
239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
242 /* only read, and nobody should modify it at this time,
243 * so don't need lock */
244 if (slot >= shared_msrs_global.nr) {
245 printk(KERN_ERR "kvm: invalid MSR slot!");
248 rdmsrl_safe(msr, &value);
249 smsr->values[slot].host = value;
250 smsr->values[slot].curr = value;
253 void kvm_define_shared_msr(unsigned slot, u32 msr)
255 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
256 shared_msrs_global.msrs[slot] = msr;
257 if (slot >= shared_msrs_global.nr)
258 shared_msrs_global.nr = slot + 1;
260 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
262 static void kvm_shared_msr_cpu_online(void)
266 for (i = 0; i < shared_msrs_global.nr; ++i)
267 shared_msr_update(i, shared_msrs_global.msrs[i]);
270 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
276 if (((value ^ smsr->values[slot].curr) & mask) == 0)
278 smsr->values[slot].curr = value;
279 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
283 if (!smsr->registered) {
284 smsr->urn.on_user_return = kvm_on_user_return;
285 user_return_notifier_register(&smsr->urn);
286 smsr->registered = true;
290 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
292 static void drop_user_return_notifiers(void)
294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
297 if (smsr->registered)
298 kvm_on_user_return(&smsr->urn);
301 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
303 return vcpu->arch.apic_base;
305 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
307 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
309 u64 old_state = vcpu->arch.apic_base &
310 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
311 u64 new_state = msr_info->data &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
314 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
316 if (!msr_info->host_initiated &&
317 ((msr_info->data & reserved_bits) != 0 ||
318 new_state == X2APIC_ENABLE ||
319 (new_state == MSR_IA32_APICBASE_ENABLE &&
320 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
321 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
325 kvm_lapic_set_base(vcpu, msr_info->data);
328 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
330 asmlinkage __visible void kvm_spurious_fault(void)
332 /* Fault while not rebooting. We want the trace. */
335 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
337 #define EXCPT_BENIGN 0
338 #define EXCPT_CONTRIBUTORY 1
341 static int exception_class(int vector)
351 return EXCPT_CONTRIBUTORY;
358 #define EXCPT_FAULT 0
360 #define EXCPT_ABORT 2
361 #define EXCPT_INTERRUPT 3
363 static int exception_type(int vector)
367 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
368 return EXCPT_INTERRUPT;
372 /* #DB is trap, as instruction watchpoints are handled elsewhere */
373 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
376 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
379 /* Reserved exceptions will result in fault */
383 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
384 unsigned nr, bool has_error, u32 error_code,
390 kvm_make_request(KVM_REQ_EVENT, vcpu);
392 if (!vcpu->arch.exception.pending) {
394 if (has_error && !is_protmode(vcpu))
396 vcpu->arch.exception.pending = true;
397 vcpu->arch.exception.has_error_code = has_error;
398 vcpu->arch.exception.nr = nr;
399 vcpu->arch.exception.error_code = error_code;
400 vcpu->arch.exception.reinject = reinject;
404 /* to check exception */
405 prev_nr = vcpu->arch.exception.nr;
406 if (prev_nr == DF_VECTOR) {
407 /* triple fault -> shutdown */
408 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
411 class1 = exception_class(prev_nr);
412 class2 = exception_class(nr);
413 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
414 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
415 /* generate double fault per SDM Table 5-5 */
416 vcpu->arch.exception.pending = true;
417 vcpu->arch.exception.has_error_code = true;
418 vcpu->arch.exception.nr = DF_VECTOR;
419 vcpu->arch.exception.error_code = 0;
421 /* replace previous exception with a new one in a hope
422 that instruction re-execution will regenerate lost
427 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
429 kvm_multiple_exception(vcpu, nr, false, 0, false);
431 EXPORT_SYMBOL_GPL(kvm_queue_exception);
433 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
435 kvm_multiple_exception(vcpu, nr, false, 0, true);
437 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
439 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
442 kvm_inject_gp(vcpu, 0);
444 return kvm_skip_emulated_instruction(vcpu);
448 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
450 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
452 ++vcpu->stat.pf_guest;
453 vcpu->arch.exception.nested_apf =
454 is_guest_mode(vcpu) && fault->async_page_fault;
455 if (vcpu->arch.exception.nested_apf)
456 vcpu->arch.apf.nested_apf_token = fault->address;
458 vcpu->arch.cr2 = fault->address;
459 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
461 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
463 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
465 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
466 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
468 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
470 return fault->nested_page_fault;
473 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
475 atomic_inc(&vcpu->arch.nmi_queued);
476 kvm_make_request(KVM_REQ_NMI, vcpu);
478 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
480 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
482 kvm_multiple_exception(vcpu, nr, true, error_code, false);
484 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
486 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
488 kvm_multiple_exception(vcpu, nr, true, error_code, true);
490 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
493 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
494 * a #GP and return false.
496 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
498 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
500 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
503 EXPORT_SYMBOL_GPL(kvm_require_cpl);
505 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
507 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
510 kvm_queue_exception(vcpu, UD_VECTOR);
513 EXPORT_SYMBOL_GPL(kvm_require_dr);
516 * This function will be used to read from the physical memory of the currently
517 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
518 * can read from guest physical or from the guest's guest physical memory.
520 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
521 gfn_t ngfn, void *data, int offset, int len,
524 struct x86_exception exception;
528 ngpa = gfn_to_gpa(ngfn);
529 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
530 if (real_gfn == UNMAPPED_GVA)
533 real_gfn = gpa_to_gfn(real_gfn);
535 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
537 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
539 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
540 void *data, int offset, int len, u32 access)
542 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
543 data, offset, len, access);
547 * Load the pae pdptrs. Return true is they are all valid.
549 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
551 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
552 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
555 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
557 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
558 offset * sizeof(u64), sizeof(pdpte),
559 PFERR_USER_MASK|PFERR_WRITE_MASK);
564 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
565 if ((pdpte[i] & PT_PRESENT_MASK) &&
567 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
574 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
575 __set_bit(VCPU_EXREG_PDPTR,
576 (unsigned long *)&vcpu->arch.regs_avail);
577 __set_bit(VCPU_EXREG_PDPTR,
578 (unsigned long *)&vcpu->arch.regs_dirty);
583 EXPORT_SYMBOL_GPL(load_pdptrs);
585 bool pdptrs_changed(struct kvm_vcpu *vcpu)
587 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
593 if (is_long_mode(vcpu) || !is_pae(vcpu))
596 if (!test_bit(VCPU_EXREG_PDPTR,
597 (unsigned long *)&vcpu->arch.regs_avail))
600 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
601 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
602 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
603 PFERR_USER_MASK | PFERR_WRITE_MASK);
606 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
611 EXPORT_SYMBOL_GPL(pdptrs_changed);
613 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
615 unsigned long old_cr0 = kvm_read_cr0(vcpu);
616 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
621 if (cr0 & 0xffffffff00000000UL)
625 cr0 &= ~CR0_RESERVED_BITS;
627 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
630 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
633 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
635 if ((vcpu->arch.efer & EFER_LME)) {
640 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
645 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
650 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
653 kvm_x86_ops->set_cr0(vcpu, cr0);
655 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
656 kvm_clear_async_pf_completion_queue(vcpu);
657 kvm_async_pf_hash_reset(vcpu);
660 if ((cr0 ^ old_cr0) & update_bits)
661 kvm_mmu_reset_context(vcpu);
663 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
664 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
665 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
666 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
670 EXPORT_SYMBOL_GPL(kvm_set_cr0);
672 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
674 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
676 EXPORT_SYMBOL_GPL(kvm_lmsw);
678 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
680 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
681 !vcpu->guest_xcr0_loaded) {
682 /* kvm_set_xcr() also depends on this */
683 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
684 vcpu->guest_xcr0_loaded = 1;
688 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
690 if (vcpu->guest_xcr0_loaded) {
691 if (vcpu->arch.xcr0 != host_xcr0)
692 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
693 vcpu->guest_xcr0_loaded = 0;
697 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
700 u64 old_xcr0 = vcpu->arch.xcr0;
703 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
704 if (index != XCR_XFEATURE_ENABLED_MASK)
706 if (!(xcr0 & XFEATURE_MASK_FP))
708 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
712 * Do not allow the guest to set bits that we do not support
713 * saving. However, xcr0 bit 0 is always set, even if the
714 * emulated CPU does not support XSAVE (see fx_init).
716 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
717 if (xcr0 & ~valid_bits)
720 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
721 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
724 if (xcr0 & XFEATURE_MASK_AVX512) {
725 if (!(xcr0 & XFEATURE_MASK_YMM))
727 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
730 vcpu->arch.xcr0 = xcr0;
732 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
733 kvm_update_cpuid(vcpu);
737 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
739 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
740 __kvm_set_xcr(vcpu, index, xcr)) {
741 kvm_inject_gp(vcpu, 0);
746 EXPORT_SYMBOL_GPL(kvm_set_xcr);
748 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
750 unsigned long old_cr4 = kvm_read_cr4(vcpu);
751 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
752 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
754 if (cr4 & CR4_RESERVED_BITS)
757 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
760 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
763 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
766 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
769 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
772 if (is_long_mode(vcpu)) {
773 if (!(cr4 & X86_CR4_PAE))
775 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
776 && ((cr4 ^ old_cr4) & pdptr_bits)
777 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
781 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
782 if (!guest_cpuid_has_pcid(vcpu))
785 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
786 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
790 if (kvm_x86_ops->set_cr4(vcpu, cr4))
793 if (((cr4 ^ old_cr4) & pdptr_bits) ||
794 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
795 kvm_mmu_reset_context(vcpu);
797 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
798 kvm_update_cpuid(vcpu);
802 EXPORT_SYMBOL_GPL(kvm_set_cr4);
804 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
807 cr3 &= ~CR3_PCID_INVD;
810 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
811 kvm_mmu_sync_roots(vcpu);
812 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
816 if (is_long_mode(vcpu)) {
817 if (cr3 & CR3_L_MODE_RESERVED_BITS)
819 } else if (is_pae(vcpu) && is_paging(vcpu) &&
820 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
823 vcpu->arch.cr3 = cr3;
824 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
825 kvm_mmu_new_cr3(vcpu);
828 EXPORT_SYMBOL_GPL(kvm_set_cr3);
830 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
832 if (cr8 & CR8_RESERVED_BITS)
834 if (lapic_in_kernel(vcpu))
835 kvm_lapic_set_tpr(vcpu, cr8);
837 vcpu->arch.cr8 = cr8;
840 EXPORT_SYMBOL_GPL(kvm_set_cr8);
842 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
844 if (lapic_in_kernel(vcpu))
845 return kvm_lapic_get_cr8(vcpu);
847 return vcpu->arch.cr8;
849 EXPORT_SYMBOL_GPL(kvm_get_cr8);
851 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
855 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
856 for (i = 0; i < KVM_NR_DB_REGS; i++)
857 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
858 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
862 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
868 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
872 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
873 dr7 = vcpu->arch.guest_debug_dr7;
875 dr7 = vcpu->arch.dr7;
876 kvm_x86_ops->set_dr7(vcpu, dr7);
877 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
878 if (dr7 & DR7_BP_EN_MASK)
879 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
882 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
884 u64 fixed = DR6_FIXED_1;
886 if (!guest_cpuid_has_rtm(vcpu))
891 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
895 vcpu->arch.db[dr] = val;
896 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
897 vcpu->arch.eff_db[dr] = val;
902 if (val & 0xffffffff00000000ULL)
904 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
905 kvm_update_dr6(vcpu);
910 if (val & 0xffffffff00000000ULL)
912 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
913 kvm_update_dr7(vcpu);
920 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
922 if (__kvm_set_dr(vcpu, dr, val)) {
923 kvm_inject_gp(vcpu, 0);
928 EXPORT_SYMBOL_GPL(kvm_set_dr);
930 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
934 *val = vcpu->arch.db[dr];
939 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
940 *val = vcpu->arch.dr6;
942 *val = kvm_x86_ops->get_dr6(vcpu);
947 *val = vcpu->arch.dr7;
952 EXPORT_SYMBOL_GPL(kvm_get_dr);
954 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
956 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
960 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
963 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
964 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
967 EXPORT_SYMBOL_GPL(kvm_rdpmc);
970 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
971 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
973 * This list is modified at module load time to reflect the
974 * capabilities of the host cpu. This capabilities test skips MSRs that are
975 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
976 * may depend on host virtualization features rather than host cpu features.
979 static u32 msrs_to_save[] = {
980 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
983 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
985 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
986 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
989 static unsigned num_msrs_to_save;
991 static u32 emulated_msrs[] = {
992 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
993 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
994 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
995 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
996 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
997 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
998 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1000 HV_X64_MSR_VP_INDEX,
1001 HV_X64_MSR_VP_RUNTIME,
1002 HV_X64_MSR_SCONTROL,
1003 HV_X64_MSR_STIMER0_CONFIG,
1004 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1007 MSR_IA32_TSC_ADJUST,
1008 MSR_IA32_TSCDEADLINE,
1009 MSR_IA32_MISC_ENABLE,
1010 MSR_IA32_MCG_STATUS,
1012 MSR_IA32_MCG_EXT_CTL,
1015 MSR_MISC_FEATURES_ENABLES,
1018 static unsigned num_emulated_msrs;
1020 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1022 if (efer & efer_reserved_bits)
1025 if (efer & EFER_FFXSR) {
1026 struct kvm_cpuid_entry2 *feat;
1028 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1029 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1033 if (efer & EFER_SVME) {
1034 struct kvm_cpuid_entry2 *feat;
1036 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1037 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1043 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1045 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1047 u64 old_efer = vcpu->arch.efer;
1049 if (!kvm_valid_efer(vcpu, efer))
1053 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1057 efer |= vcpu->arch.efer & EFER_LMA;
1059 kvm_x86_ops->set_efer(vcpu, efer);
1061 /* Update reserved bits */
1062 if ((efer ^ old_efer) & EFER_NX)
1063 kvm_mmu_reset_context(vcpu);
1068 void kvm_enable_efer_bits(u64 mask)
1070 efer_reserved_bits &= ~mask;
1072 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1075 * Writes msr value into into the appropriate "register".
1076 * Returns 0 on success, non-0 otherwise.
1077 * Assumes vcpu_load() was already called.
1079 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1081 switch (msr->index) {
1084 case MSR_KERNEL_GS_BASE:
1087 if (is_noncanonical_address(msr->data))
1090 case MSR_IA32_SYSENTER_EIP:
1091 case MSR_IA32_SYSENTER_ESP:
1093 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1094 * non-canonical address is written on Intel but not on
1095 * AMD (which ignores the top 32-bits, because it does
1096 * not implement 64-bit SYSENTER).
1098 * 64-bit code should hence be able to write a non-canonical
1099 * value on AMD. Making the address canonical ensures that
1100 * vmentry does not fail on Intel after writing a non-canonical
1101 * value, and that something deterministic happens if the guest
1102 * invokes 64-bit SYSENTER.
1104 msr->data = get_canonical(msr->data);
1106 return kvm_x86_ops->set_msr(vcpu, msr);
1108 EXPORT_SYMBOL_GPL(kvm_set_msr);
1111 * Adapt set_msr() to msr_io()'s calling convention
1113 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1115 struct msr_data msr;
1119 msr.host_initiated = true;
1120 r = kvm_get_msr(vcpu, &msr);
1128 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1130 struct msr_data msr;
1134 msr.host_initiated = true;
1135 return kvm_set_msr(vcpu, &msr);
1138 #ifdef CONFIG_X86_64
1139 struct pvclock_gtod_data {
1142 struct { /* extract of a clocksource struct */
1155 static struct pvclock_gtod_data pvclock_gtod_data;
1157 static void update_pvclock_gtod(struct timekeeper *tk)
1159 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1162 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1164 write_seqcount_begin(&vdata->seq);
1166 /* copy pvclock gtod data */
1167 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1168 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1169 vdata->clock.mask = tk->tkr_mono.mask;
1170 vdata->clock.mult = tk->tkr_mono.mult;
1171 vdata->clock.shift = tk->tkr_mono.shift;
1173 vdata->boot_ns = boot_ns;
1174 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1176 vdata->wall_time_sec = tk->xtime_sec;
1178 write_seqcount_end(&vdata->seq);
1182 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1185 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1186 * vcpu_enter_guest. This function is only called from
1187 * the physical CPU that is running vcpu.
1189 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1192 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1196 struct pvclock_wall_clock wc;
1197 struct timespec64 boot;
1202 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1207 ++version; /* first time write, random junk */
1211 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1215 * The guest calculates current wall clock time by adding
1216 * system time (updated by kvm_guest_time_update below) to the
1217 * wall clock specified here. guest system time equals host
1218 * system time for us, thus we must fill in host boot time here.
1220 getboottime64(&boot);
1222 if (kvm->arch.kvmclock_offset) {
1223 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1224 boot = timespec64_sub(boot, ts);
1226 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1227 wc.nsec = boot.tv_nsec;
1228 wc.version = version;
1230 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1233 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1236 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1238 do_shl32_div32(dividend, divisor);
1242 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1243 s8 *pshift, u32 *pmultiplier)
1251 scaled64 = scaled_hz;
1252 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1257 tps32 = (uint32_t)tps64;
1258 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1259 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1267 *pmultiplier = div_frac(scaled64, tps32);
1269 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1270 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1273 #ifdef CONFIG_X86_64
1274 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1277 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1278 static unsigned long max_tsc_khz;
1280 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1282 u64 v = (u64)khz * (1000000 + ppm);
1287 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1291 /* Guest TSC same frequency as host TSC? */
1293 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1297 /* TSC scaling supported? */
1298 if (!kvm_has_tsc_control) {
1299 if (user_tsc_khz > tsc_khz) {
1300 vcpu->arch.tsc_catchup = 1;
1301 vcpu->arch.tsc_always_catchup = 1;
1304 WARN(1, "user requested TSC rate below hardware speed\n");
1309 /* TSC scaling required - calculate ratio */
1310 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1311 user_tsc_khz, tsc_khz);
1313 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1314 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1319 vcpu->arch.tsc_scaling_ratio = ratio;
1323 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1325 u32 thresh_lo, thresh_hi;
1326 int use_scaling = 0;
1328 /* tsc_khz can be zero if TSC calibration fails */
1329 if (user_tsc_khz == 0) {
1330 /* set tsc_scaling_ratio to a safe value */
1331 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1335 /* Compute a scale to convert nanoseconds in TSC cycles */
1336 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1337 &vcpu->arch.virtual_tsc_shift,
1338 &vcpu->arch.virtual_tsc_mult);
1339 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1342 * Compute the variation in TSC rate which is acceptable
1343 * within the range of tolerance and decide if the
1344 * rate being applied is within that bounds of the hardware
1345 * rate. If so, no scaling or compensation need be done.
1347 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1348 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1349 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1350 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1353 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1356 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1358 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1359 vcpu->arch.virtual_tsc_mult,
1360 vcpu->arch.virtual_tsc_shift);
1361 tsc += vcpu->arch.this_tsc_write;
1365 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1367 #ifdef CONFIG_X86_64
1369 struct kvm_arch *ka = &vcpu->kvm->arch;
1370 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1372 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1373 atomic_read(&vcpu->kvm->online_vcpus));
1376 * Once the masterclock is enabled, always perform request in
1377 * order to update it.
1379 * In order to enable masterclock, the host clocksource must be TSC
1380 * and the vcpus need to have matched TSCs. When that happens,
1381 * perform request to enable masterclock.
1383 if (ka->use_master_clock ||
1384 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1385 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1387 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1388 atomic_read(&vcpu->kvm->online_vcpus),
1389 ka->use_master_clock, gtod->clock.vclock_mode);
1393 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1395 u64 curr_offset = vcpu->arch.tsc_offset;
1396 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1400 * Multiply tsc by a fixed point number represented by ratio.
1402 * The most significant 64-N bits (mult) of ratio represent the
1403 * integral part of the fixed point number; the remaining N bits
1404 * (frac) represent the fractional part, ie. ratio represents a fixed
1405 * point number (mult + frac * 2^(-N)).
1407 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1409 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1411 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1414 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1417 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1419 if (ratio != kvm_default_tsc_scaling_ratio)
1420 _tsc = __scale_tsc(ratio, tsc);
1424 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1426 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1430 tsc = kvm_scale_tsc(vcpu, rdtsc());
1432 return target_tsc - tsc;
1435 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1437 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1439 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1441 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1443 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1444 vcpu->arch.tsc_offset = offset;
1447 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1449 struct kvm *kvm = vcpu->kvm;
1450 u64 offset, ns, elapsed;
1451 unsigned long flags;
1453 bool already_matched;
1454 u64 data = msr->data;
1455 bool synchronizing = false;
1457 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1458 offset = kvm_compute_tsc_offset(vcpu, data);
1459 ns = ktime_get_boot_ns();
1460 elapsed = ns - kvm->arch.last_tsc_nsec;
1462 if (vcpu->arch.virtual_tsc_khz) {
1463 if (data == 0 && msr->host_initiated) {
1465 * detection of vcpu initialization -- need to sync
1466 * with other vCPUs. This particularly helps to keep
1467 * kvm_clock stable after CPU hotplug
1469 synchronizing = true;
1471 u64 tsc_exp = kvm->arch.last_tsc_write +
1472 nsec_to_cycles(vcpu, elapsed);
1473 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1475 * Special case: TSC write with a small delta (1 second)
1476 * of virtual cycle time against real time is
1477 * interpreted as an attempt to synchronize the CPU.
1479 synchronizing = data < tsc_exp + tsc_hz &&
1480 data + tsc_hz > tsc_exp;
1485 * For a reliable TSC, we can match TSC offsets, and for an unstable
1486 * TSC, we add elapsed time in this computation. We could let the
1487 * compensation code attempt to catch up if we fall behind, but
1488 * it's better to try to match offsets from the beginning.
1490 if (synchronizing &&
1491 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1492 if (!check_tsc_unstable()) {
1493 offset = kvm->arch.cur_tsc_offset;
1494 pr_debug("kvm: matched tsc offset for %llu\n", data);
1496 u64 delta = nsec_to_cycles(vcpu, elapsed);
1498 offset = kvm_compute_tsc_offset(vcpu, data);
1499 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1502 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1505 * We split periods of matched TSC writes into generations.
1506 * For each generation, we track the original measured
1507 * nanosecond time, offset, and write, so if TSCs are in
1508 * sync, we can match exact offset, and if not, we can match
1509 * exact software computation in compute_guest_tsc()
1511 * These values are tracked in kvm->arch.cur_xxx variables.
1513 kvm->arch.cur_tsc_generation++;
1514 kvm->arch.cur_tsc_nsec = ns;
1515 kvm->arch.cur_tsc_write = data;
1516 kvm->arch.cur_tsc_offset = offset;
1518 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1519 kvm->arch.cur_tsc_generation, data);
1523 * We also track th most recent recorded KHZ, write and time to
1524 * allow the matching interval to be extended at each write.
1526 kvm->arch.last_tsc_nsec = ns;
1527 kvm->arch.last_tsc_write = data;
1528 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1530 vcpu->arch.last_guest_tsc = data;
1532 /* Keep track of which generation this VCPU has synchronized to */
1533 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1534 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1535 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1537 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1538 update_ia32_tsc_adjust_msr(vcpu, offset);
1539 kvm_vcpu_write_tsc_offset(vcpu, offset);
1540 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1542 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1544 kvm->arch.nr_vcpus_matched_tsc = 0;
1545 } else if (!already_matched) {
1546 kvm->arch.nr_vcpus_matched_tsc++;
1549 kvm_track_tsc_matching(vcpu);
1550 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1553 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1555 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1558 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1561 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1563 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1564 WARN_ON(adjustment < 0);
1565 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1566 adjust_tsc_offset_guest(vcpu, adjustment);
1569 #ifdef CONFIG_X86_64
1571 static u64 read_tsc(void)
1573 u64 ret = (u64)rdtsc_ordered();
1574 u64 last = pvclock_gtod_data.clock.cycle_last;
1576 if (likely(ret >= last))
1580 * GCC likes to generate cmov here, but this branch is extremely
1581 * predictable (it's just a function of time and the likely is
1582 * very likely) and there's a data dependence, so force GCC
1583 * to generate a branch instead. I don't barrier() because
1584 * we don't actually need a barrier, and if this function
1585 * ever gets inlined it will generate worse code.
1591 static inline u64 vgettsc(u64 *cycle_now)
1594 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1596 *cycle_now = read_tsc();
1598 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1599 return v * gtod->clock.mult;
1602 static int do_monotonic_boot(s64 *t, u64 *cycle_now)
1604 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1610 seq = read_seqcount_begin(>od->seq);
1611 mode = gtod->clock.vclock_mode;
1612 ns = gtod->nsec_base;
1613 ns += vgettsc(cycle_now);
1614 ns >>= gtod->clock.shift;
1615 ns += gtod->boot_ns;
1616 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1622 static int do_realtime(struct timespec *ts, u64 *cycle_now)
1624 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1630 seq = read_seqcount_begin(>od->seq);
1631 mode = gtod->clock.vclock_mode;
1632 ts->tv_sec = gtod->wall_time_sec;
1633 ns = gtod->nsec_base;
1634 ns += vgettsc(cycle_now);
1635 ns >>= gtod->clock.shift;
1636 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1638 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1644 /* returns true if host is using tsc clocksource */
1645 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
1647 /* checked again under seqlock below */
1648 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1651 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1654 /* returns true if host is using tsc clocksource */
1655 static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1658 /* checked again under seqlock below */
1659 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1662 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1668 * Assuming a stable TSC across physical CPUS, and a stable TSC
1669 * across virtual CPUs, the following condition is possible.
1670 * Each numbered line represents an event visible to both
1671 * CPUs at the next numbered event.
1673 * "timespecX" represents host monotonic time. "tscX" represents
1676 * VCPU0 on CPU0 | VCPU1 on CPU1
1678 * 1. read timespec0,tsc0
1679 * 2. | timespec1 = timespec0 + N
1681 * 3. transition to guest | transition to guest
1682 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1683 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1684 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1686 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1689 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1691 * - 0 < N - M => M < N
1693 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1694 * always the case (the difference between two distinct xtime instances
1695 * might be smaller then the difference between corresponding TSC reads,
1696 * when updating guest vcpus pvclock areas).
1698 * To avoid that problem, do not allow visibility of distinct
1699 * system_timestamp/tsc_timestamp values simultaneously: use a master
1700 * copy of host monotonic time values. Update that master copy
1703 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1707 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1709 #ifdef CONFIG_X86_64
1710 struct kvm_arch *ka = &kvm->arch;
1712 bool host_tsc_clocksource, vcpus_matched;
1714 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1715 atomic_read(&kvm->online_vcpus));
1718 * If the host uses TSC clock, then passthrough TSC as stable
1721 host_tsc_clocksource = kvm_get_time_and_clockread(
1722 &ka->master_kernel_ns,
1723 &ka->master_cycle_now);
1725 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1726 && !ka->backwards_tsc_observed
1727 && !ka->boot_vcpu_runs_old_kvmclock;
1729 if (ka->use_master_clock)
1730 atomic_set(&kvm_guest_has_master_clock, 1);
1732 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1733 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1738 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1740 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1743 static void kvm_gen_update_masterclock(struct kvm *kvm)
1745 #ifdef CONFIG_X86_64
1747 struct kvm_vcpu *vcpu;
1748 struct kvm_arch *ka = &kvm->arch;
1750 spin_lock(&ka->pvclock_gtod_sync_lock);
1751 kvm_make_mclock_inprogress_request(kvm);
1752 /* no guest entries from this point */
1753 pvclock_update_vm_gtod_copy(kvm);
1755 kvm_for_each_vcpu(i, vcpu, kvm)
1756 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1758 /* guest entries allowed */
1759 kvm_for_each_vcpu(i, vcpu, kvm)
1760 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
1762 spin_unlock(&ka->pvclock_gtod_sync_lock);
1766 u64 get_kvmclock_ns(struct kvm *kvm)
1768 struct kvm_arch *ka = &kvm->arch;
1769 struct pvclock_vcpu_time_info hv_clock;
1772 spin_lock(&ka->pvclock_gtod_sync_lock);
1773 if (!ka->use_master_clock) {
1774 spin_unlock(&ka->pvclock_gtod_sync_lock);
1775 return ktime_get_boot_ns() + ka->kvmclock_offset;
1778 hv_clock.tsc_timestamp = ka->master_cycle_now;
1779 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1780 spin_unlock(&ka->pvclock_gtod_sync_lock);
1782 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1785 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1786 &hv_clock.tsc_shift,
1787 &hv_clock.tsc_to_system_mul);
1788 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1795 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1797 struct kvm_vcpu_arch *vcpu = &v->arch;
1798 struct pvclock_vcpu_time_info guest_hv_clock;
1800 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1801 &guest_hv_clock, sizeof(guest_hv_clock))))
1804 /* This VCPU is paused, but it's legal for a guest to read another
1805 * VCPU's kvmclock, so we really have to follow the specification where
1806 * it says that version is odd if data is being modified, and even after
1809 * Version field updates must be kept separate. This is because
1810 * kvm_write_guest_cached might use a "rep movs" instruction, and
1811 * writes within a string instruction are weakly ordered. So there
1812 * are three writes overall.
1814 * As a small optimization, only write the version field in the first
1815 * and third write. The vcpu->pv_time cache is still valid, because the
1816 * version field is the first in the struct.
1818 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1820 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1821 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1823 sizeof(vcpu->hv_clock.version));
1827 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1828 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1830 if (vcpu->pvclock_set_guest_stopped_request) {
1831 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1832 vcpu->pvclock_set_guest_stopped_request = false;
1835 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1837 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1839 sizeof(vcpu->hv_clock));
1843 vcpu->hv_clock.version++;
1844 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1846 sizeof(vcpu->hv_clock.version));
1849 static int kvm_guest_time_update(struct kvm_vcpu *v)
1851 unsigned long flags, tgt_tsc_khz;
1852 struct kvm_vcpu_arch *vcpu = &v->arch;
1853 struct kvm_arch *ka = &v->kvm->arch;
1855 u64 tsc_timestamp, host_tsc;
1857 bool use_master_clock;
1863 * If the host uses TSC clock, then passthrough TSC as stable
1866 spin_lock(&ka->pvclock_gtod_sync_lock);
1867 use_master_clock = ka->use_master_clock;
1868 if (use_master_clock) {
1869 host_tsc = ka->master_cycle_now;
1870 kernel_ns = ka->master_kernel_ns;
1872 spin_unlock(&ka->pvclock_gtod_sync_lock);
1874 /* Keep irq disabled to prevent changes to the clock */
1875 local_irq_save(flags);
1876 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1877 if (unlikely(tgt_tsc_khz == 0)) {
1878 local_irq_restore(flags);
1879 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1882 if (!use_master_clock) {
1884 kernel_ns = ktime_get_boot_ns();
1887 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1890 * We may have to catch up the TSC to match elapsed wall clock
1891 * time for two reasons, even if kvmclock is used.
1892 * 1) CPU could have been running below the maximum TSC rate
1893 * 2) Broken TSC compensation resets the base at each VCPU
1894 * entry to avoid unknown leaps of TSC even when running
1895 * again on the same CPU. This may cause apparent elapsed
1896 * time to disappear, and the guest to stand still or run
1899 if (vcpu->tsc_catchup) {
1900 u64 tsc = compute_guest_tsc(v, kernel_ns);
1901 if (tsc > tsc_timestamp) {
1902 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1903 tsc_timestamp = tsc;
1907 local_irq_restore(flags);
1909 /* With all the info we got, fill in the values */
1911 if (kvm_has_tsc_control)
1912 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1914 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1915 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1916 &vcpu->hv_clock.tsc_shift,
1917 &vcpu->hv_clock.tsc_to_system_mul);
1918 vcpu->hw_tsc_khz = tgt_tsc_khz;
1921 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1922 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1923 vcpu->last_guest_tsc = tsc_timestamp;
1925 /* If the host uses TSC clocksource, then it is stable */
1927 if (use_master_clock)
1928 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1930 vcpu->hv_clock.flags = pvclock_flags;
1932 if (vcpu->pv_time_enabled)
1933 kvm_setup_pvclock_page(v);
1934 if (v == kvm_get_vcpu(v->kvm, 0))
1935 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
1940 * kvmclock updates which are isolated to a given vcpu, such as
1941 * vcpu->cpu migration, should not allow system_timestamp from
1942 * the rest of the vcpus to remain static. Otherwise ntp frequency
1943 * correction applies to one vcpu's system_timestamp but not
1946 * So in those cases, request a kvmclock update for all vcpus.
1947 * We need to rate-limit these requests though, as they can
1948 * considerably slow guests that have a large number of vcpus.
1949 * The time for a remote vcpu to update its kvmclock is bound
1950 * by the delay we use to rate-limit the updates.
1953 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1955 static void kvmclock_update_fn(struct work_struct *work)
1958 struct delayed_work *dwork = to_delayed_work(work);
1959 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1960 kvmclock_update_work);
1961 struct kvm *kvm = container_of(ka, struct kvm, arch);
1962 struct kvm_vcpu *vcpu;
1964 kvm_for_each_vcpu(i, vcpu, kvm) {
1965 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1966 kvm_vcpu_kick(vcpu);
1970 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1972 struct kvm *kvm = v->kvm;
1974 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1975 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1976 KVMCLOCK_UPDATE_DELAY);
1979 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1981 static void kvmclock_sync_fn(struct work_struct *work)
1983 struct delayed_work *dwork = to_delayed_work(work);
1984 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1985 kvmclock_sync_work);
1986 struct kvm *kvm = container_of(ka, struct kvm, arch);
1988 if (!kvmclock_periodic_sync)
1991 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1992 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1993 KVMCLOCK_SYNC_PERIOD);
1996 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1998 u64 mcg_cap = vcpu->arch.mcg_cap;
1999 unsigned bank_num = mcg_cap & 0xff;
2002 case MSR_IA32_MCG_STATUS:
2003 vcpu->arch.mcg_status = data;
2005 case MSR_IA32_MCG_CTL:
2006 if (!(mcg_cap & MCG_CTL_P))
2008 if (data != 0 && data != ~(u64)0)
2010 vcpu->arch.mcg_ctl = data;
2013 if (msr >= MSR_IA32_MC0_CTL &&
2014 msr < MSR_IA32_MCx_CTL(bank_num)) {
2015 u32 offset = msr - MSR_IA32_MC0_CTL;
2016 /* only 0 or all 1s can be written to IA32_MCi_CTL
2017 * some Linux kernels though clear bit 10 in bank 4 to
2018 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2019 * this to avoid an uncatched #GP in the guest
2021 if ((offset & 0x3) == 0 &&
2022 data != 0 && (data | (1 << 10)) != ~(u64)0)
2024 vcpu->arch.mce_banks[offset] = data;
2032 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2034 struct kvm *kvm = vcpu->kvm;
2035 int lm = is_long_mode(vcpu);
2036 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2037 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2038 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2039 : kvm->arch.xen_hvm_config.blob_size_32;
2040 u32 page_num = data & ~PAGE_MASK;
2041 u64 page_addr = data & PAGE_MASK;
2046 if (page_num >= blob_size)
2049 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2054 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2063 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2065 gpa_t gpa = data & ~0x3f;
2067 /* Bits 3:5 are reserved, Should be zero */
2071 vcpu->arch.apf.msr_val = data;
2073 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2074 kvm_clear_async_pf_completion_queue(vcpu);
2075 kvm_async_pf_hash_reset(vcpu);
2079 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2083 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2084 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2085 kvm_async_pf_wakeup_all(vcpu);
2089 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2091 vcpu->arch.pv_time_enabled = false;
2094 static void record_steal_time(struct kvm_vcpu *vcpu)
2096 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2099 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2100 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2103 vcpu->arch.st.steal.preempted = 0;
2105 if (vcpu->arch.st.steal.version & 1)
2106 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2108 vcpu->arch.st.steal.version += 1;
2110 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2111 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2115 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2116 vcpu->arch.st.last_steal;
2117 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2119 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2120 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2124 vcpu->arch.st.steal.version += 1;
2126 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2127 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2130 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2133 u32 msr = msr_info->index;
2134 u64 data = msr_info->data;
2137 case MSR_AMD64_NB_CFG:
2138 case MSR_IA32_UCODE_REV:
2139 case MSR_IA32_UCODE_WRITE:
2140 case MSR_VM_HSAVE_PA:
2141 case MSR_AMD64_PATCH_LOADER:
2142 case MSR_AMD64_BU_CFG2:
2143 case MSR_AMD64_DC_CFG:
2147 return set_efer(vcpu, data);
2149 data &= ~(u64)0x40; /* ignore flush filter disable */
2150 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2151 data &= ~(u64)0x8; /* ignore TLB cache disable */
2152 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2154 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2159 case MSR_FAM10H_MMIO_CONF_BASE:
2161 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2166 case MSR_IA32_DEBUGCTLMSR:
2168 /* We support the non-activated case already */
2170 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2171 /* Values other than LBR and BTF are vendor-specific,
2172 thus reserved and should throw a #GP */
2175 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2178 case 0x200 ... 0x2ff:
2179 return kvm_mtrr_set_msr(vcpu, msr, data);
2180 case MSR_IA32_APICBASE:
2181 return kvm_set_apic_base(vcpu, msr_info);
2182 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2183 return kvm_x2apic_msr_write(vcpu, msr, data);
2184 case MSR_IA32_TSCDEADLINE:
2185 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2187 case MSR_IA32_TSC_ADJUST:
2188 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2189 if (!msr_info->host_initiated) {
2190 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2191 adjust_tsc_offset_guest(vcpu, adj);
2193 vcpu->arch.ia32_tsc_adjust_msr = data;
2196 case MSR_IA32_MISC_ENABLE:
2197 vcpu->arch.ia32_misc_enable_msr = data;
2199 case MSR_IA32_SMBASE:
2200 if (!msr_info->host_initiated)
2202 vcpu->arch.smbase = data;
2204 case MSR_KVM_WALL_CLOCK_NEW:
2205 case MSR_KVM_WALL_CLOCK:
2206 vcpu->kvm->arch.wall_clock = data;
2207 kvm_write_wall_clock(vcpu->kvm, data);
2209 case MSR_KVM_SYSTEM_TIME_NEW:
2210 case MSR_KVM_SYSTEM_TIME: {
2211 struct kvm_arch *ka = &vcpu->kvm->arch;
2213 kvmclock_reset(vcpu);
2215 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2216 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2218 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2219 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2221 ka->boot_vcpu_runs_old_kvmclock = tmp;
2224 vcpu->arch.time = data;
2225 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2227 /* we verify if the enable bit is set... */
2231 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2232 &vcpu->arch.pv_time, data & ~1ULL,
2233 sizeof(struct pvclock_vcpu_time_info)))
2234 vcpu->arch.pv_time_enabled = false;
2236 vcpu->arch.pv_time_enabled = true;
2240 case MSR_KVM_ASYNC_PF_EN:
2241 if (kvm_pv_enable_async_pf(vcpu, data))
2244 case MSR_KVM_STEAL_TIME:
2246 if (unlikely(!sched_info_on()))
2249 if (data & KVM_STEAL_RESERVED_MASK)
2252 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2253 data & KVM_STEAL_VALID_BITS,
2254 sizeof(struct kvm_steal_time)))
2257 vcpu->arch.st.msr_val = data;
2259 if (!(data & KVM_MSR_ENABLED))
2262 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2265 case MSR_KVM_PV_EOI_EN:
2266 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2270 case MSR_IA32_MCG_CTL:
2271 case MSR_IA32_MCG_STATUS:
2272 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2273 return set_msr_mce(vcpu, msr, data);
2275 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2276 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2277 pr = true; /* fall through */
2278 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2279 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2280 if (kvm_pmu_is_valid_msr(vcpu, msr))
2281 return kvm_pmu_set_msr(vcpu, msr_info);
2283 if (pr || data != 0)
2284 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2285 "0x%x data 0x%llx\n", msr, data);
2287 case MSR_K7_CLK_CTL:
2289 * Ignore all writes to this no longer documented MSR.
2290 * Writes are only relevant for old K7 processors,
2291 * all pre-dating SVM, but a recommended workaround from
2292 * AMD for these chips. It is possible to specify the
2293 * affected processor models on the command line, hence
2294 * the need to ignore the workaround.
2297 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2298 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2299 case HV_X64_MSR_CRASH_CTL:
2300 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2301 return kvm_hv_set_msr_common(vcpu, msr, data,
2302 msr_info->host_initiated);
2303 case MSR_IA32_BBL_CR_CTL3:
2304 /* Drop writes to this legacy MSR -- see rdmsr
2305 * counterpart for further detail.
2307 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
2309 case MSR_AMD64_OSVW_ID_LENGTH:
2310 if (!guest_cpuid_has_osvw(vcpu))
2312 vcpu->arch.osvw.length = data;
2314 case MSR_AMD64_OSVW_STATUS:
2315 if (!guest_cpuid_has_osvw(vcpu))
2317 vcpu->arch.osvw.status = data;
2319 case MSR_PLATFORM_INFO:
2320 if (!msr_info->host_initiated ||
2321 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2322 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2323 cpuid_fault_enabled(vcpu)))
2325 vcpu->arch.msr_platform_info = data;
2327 case MSR_MISC_FEATURES_ENABLES:
2328 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2329 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2330 !supports_cpuid_fault(vcpu)))
2332 vcpu->arch.msr_misc_features_enables = data;
2335 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2336 return xen_hvm_config(vcpu, data);
2337 if (kvm_pmu_is_valid_msr(vcpu, msr))
2338 return kvm_pmu_set_msr(vcpu, msr_info);
2340 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2344 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2351 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2355 * Reads an msr value (of 'msr_index') into 'pdata'.
2356 * Returns 0 on success, non-0 otherwise.
2357 * Assumes vcpu_load() was already called.
2359 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2361 return kvm_x86_ops->get_msr(vcpu, msr);
2363 EXPORT_SYMBOL_GPL(kvm_get_msr);
2365 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2368 u64 mcg_cap = vcpu->arch.mcg_cap;
2369 unsigned bank_num = mcg_cap & 0xff;
2372 case MSR_IA32_P5_MC_ADDR:
2373 case MSR_IA32_P5_MC_TYPE:
2376 case MSR_IA32_MCG_CAP:
2377 data = vcpu->arch.mcg_cap;
2379 case MSR_IA32_MCG_CTL:
2380 if (!(mcg_cap & MCG_CTL_P))
2382 data = vcpu->arch.mcg_ctl;
2384 case MSR_IA32_MCG_STATUS:
2385 data = vcpu->arch.mcg_status;
2388 if (msr >= MSR_IA32_MC0_CTL &&
2389 msr < MSR_IA32_MCx_CTL(bank_num)) {
2390 u32 offset = msr - MSR_IA32_MC0_CTL;
2391 data = vcpu->arch.mce_banks[offset];
2400 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2402 switch (msr_info->index) {
2403 case MSR_IA32_PLATFORM_ID:
2404 case MSR_IA32_EBL_CR_POWERON:
2405 case MSR_IA32_DEBUGCTLMSR:
2406 case MSR_IA32_LASTBRANCHFROMIP:
2407 case MSR_IA32_LASTBRANCHTOIP:
2408 case MSR_IA32_LASTINTFROMIP:
2409 case MSR_IA32_LASTINTTOIP:
2411 case MSR_K8_TSEG_ADDR:
2412 case MSR_K8_TSEG_MASK:
2414 case MSR_VM_HSAVE_PA:
2415 case MSR_K8_INT_PENDING_MSG:
2416 case MSR_AMD64_NB_CFG:
2417 case MSR_FAM10H_MMIO_CONF_BASE:
2418 case MSR_AMD64_BU_CFG2:
2419 case MSR_IA32_PERF_CTL:
2420 case MSR_AMD64_DC_CFG:
2423 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2424 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2425 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2426 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2427 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2428 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2431 case MSR_IA32_UCODE_REV:
2432 msr_info->data = 0x100000000ULL;
2435 case 0x200 ... 0x2ff:
2436 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2437 case 0xcd: /* fsb frequency */
2441 * MSR_EBC_FREQUENCY_ID
2442 * Conservative value valid for even the basic CPU models.
2443 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2444 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2445 * and 266MHz for model 3, or 4. Set Core Clock
2446 * Frequency to System Bus Frequency Ratio to 1 (bits
2447 * 31:24) even though these are only valid for CPU
2448 * models > 2, however guests may end up dividing or
2449 * multiplying by zero otherwise.
2451 case MSR_EBC_FREQUENCY_ID:
2452 msr_info->data = 1 << 24;
2454 case MSR_IA32_APICBASE:
2455 msr_info->data = kvm_get_apic_base(vcpu);
2457 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2458 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2460 case MSR_IA32_TSCDEADLINE:
2461 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2463 case MSR_IA32_TSC_ADJUST:
2464 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2466 case MSR_IA32_MISC_ENABLE:
2467 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2469 case MSR_IA32_SMBASE:
2470 if (!msr_info->host_initiated)
2472 msr_info->data = vcpu->arch.smbase;
2474 case MSR_IA32_PERF_STATUS:
2475 /* TSC increment by tick */
2476 msr_info->data = 1000ULL;
2477 /* CPU multiplier */
2478 msr_info->data |= (((uint64_t)4ULL) << 40);
2481 msr_info->data = vcpu->arch.efer;
2483 case MSR_KVM_WALL_CLOCK:
2484 case MSR_KVM_WALL_CLOCK_NEW:
2485 msr_info->data = vcpu->kvm->arch.wall_clock;
2487 case MSR_KVM_SYSTEM_TIME:
2488 case MSR_KVM_SYSTEM_TIME_NEW:
2489 msr_info->data = vcpu->arch.time;
2491 case MSR_KVM_ASYNC_PF_EN:
2492 msr_info->data = vcpu->arch.apf.msr_val;
2494 case MSR_KVM_STEAL_TIME:
2495 msr_info->data = vcpu->arch.st.msr_val;
2497 case MSR_KVM_PV_EOI_EN:
2498 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2500 case MSR_IA32_P5_MC_ADDR:
2501 case MSR_IA32_P5_MC_TYPE:
2502 case MSR_IA32_MCG_CAP:
2503 case MSR_IA32_MCG_CTL:
2504 case MSR_IA32_MCG_STATUS:
2505 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2506 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2507 case MSR_K7_CLK_CTL:
2509 * Provide expected ramp-up count for K7. All other
2510 * are set to zero, indicating minimum divisors for
2513 * This prevents guest kernels on AMD host with CPU
2514 * type 6, model 8 and higher from exploding due to
2515 * the rdmsr failing.
2517 msr_info->data = 0x20000000;
2519 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2520 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2521 case HV_X64_MSR_CRASH_CTL:
2522 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2523 return kvm_hv_get_msr_common(vcpu,
2524 msr_info->index, &msr_info->data);
2526 case MSR_IA32_BBL_CR_CTL3:
2527 /* This legacy MSR exists but isn't fully documented in current
2528 * silicon. It is however accessed by winxp in very narrow
2529 * scenarios where it sets bit #19, itself documented as
2530 * a "reserved" bit. Best effort attempt to source coherent
2531 * read data here should the balance of the register be
2532 * interpreted by the guest:
2534 * L2 cache control register 3: 64GB range, 256KB size,
2535 * enabled, latency 0x1, configured
2537 msr_info->data = 0xbe702111;
2539 case MSR_AMD64_OSVW_ID_LENGTH:
2540 if (!guest_cpuid_has_osvw(vcpu))
2542 msr_info->data = vcpu->arch.osvw.length;
2544 case MSR_AMD64_OSVW_STATUS:
2545 if (!guest_cpuid_has_osvw(vcpu))
2547 msr_info->data = vcpu->arch.osvw.status;
2549 case MSR_PLATFORM_INFO:
2550 msr_info->data = vcpu->arch.msr_platform_info;
2552 case MSR_MISC_FEATURES_ENABLES:
2553 msr_info->data = vcpu->arch.msr_misc_features_enables;
2556 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2557 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2559 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2563 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2570 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2573 * Read or write a bunch of msrs. All parameters are kernel addresses.
2575 * @return number of msrs set successfully.
2577 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2578 struct kvm_msr_entry *entries,
2579 int (*do_msr)(struct kvm_vcpu *vcpu,
2580 unsigned index, u64 *data))
2584 idx = srcu_read_lock(&vcpu->kvm->srcu);
2585 for (i = 0; i < msrs->nmsrs; ++i)
2586 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2588 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2594 * Read or write a bunch of msrs. Parameters are user addresses.
2596 * @return number of msrs set successfully.
2598 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2599 int (*do_msr)(struct kvm_vcpu *vcpu,
2600 unsigned index, u64 *data),
2603 struct kvm_msrs msrs;
2604 struct kvm_msr_entry *entries;
2609 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2613 if (msrs.nmsrs >= MAX_IO_MSRS)
2616 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2617 entries = memdup_user(user_msrs->entries, size);
2618 if (IS_ERR(entries)) {
2619 r = PTR_ERR(entries);
2623 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2628 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2639 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2644 case KVM_CAP_IRQCHIP:
2646 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2647 case KVM_CAP_SET_TSS_ADDR:
2648 case KVM_CAP_EXT_CPUID:
2649 case KVM_CAP_EXT_EMUL_CPUID:
2650 case KVM_CAP_CLOCKSOURCE:
2652 case KVM_CAP_NOP_IO_DELAY:
2653 case KVM_CAP_MP_STATE:
2654 case KVM_CAP_SYNC_MMU:
2655 case KVM_CAP_USER_NMI:
2656 case KVM_CAP_REINJECT_CONTROL:
2657 case KVM_CAP_IRQ_INJECT_STATUS:
2658 case KVM_CAP_IOEVENTFD:
2659 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2661 case KVM_CAP_PIT_STATE2:
2662 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2663 case KVM_CAP_XEN_HVM:
2664 case KVM_CAP_VCPU_EVENTS:
2665 case KVM_CAP_HYPERV:
2666 case KVM_CAP_HYPERV_VAPIC:
2667 case KVM_CAP_HYPERV_SPIN:
2668 case KVM_CAP_HYPERV_SYNIC:
2669 case KVM_CAP_HYPERV_SYNIC2:
2670 case KVM_CAP_HYPERV_VP_INDEX:
2671 case KVM_CAP_PCI_SEGMENT:
2672 case KVM_CAP_DEBUGREGS:
2673 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2675 case KVM_CAP_ASYNC_PF:
2676 case KVM_CAP_GET_TSC_KHZ:
2677 case KVM_CAP_KVMCLOCK_CTRL:
2678 case KVM_CAP_READONLY_MEM:
2679 case KVM_CAP_HYPERV_TIME:
2680 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2681 case KVM_CAP_TSC_DEADLINE_TIMER:
2682 case KVM_CAP_ENABLE_CAP_VM:
2683 case KVM_CAP_DISABLE_QUIRKS:
2684 case KVM_CAP_SET_BOOT_CPU_ID:
2685 case KVM_CAP_SPLIT_IRQCHIP:
2686 case KVM_CAP_IMMEDIATE_EXIT:
2689 case KVM_CAP_ADJUST_CLOCK:
2690 r = KVM_CLOCK_TSC_STABLE;
2692 case KVM_CAP_X86_GUEST_MWAIT:
2693 r = kvm_mwait_in_guest();
2695 case KVM_CAP_X86_SMM:
2696 /* SMBASE is usually relocated above 1M on modern chipsets,
2697 * and SMM handlers might indeed rely on 4G segment limits,
2698 * so do not report SMM to be available if real mode is
2699 * emulated via vm86 mode. Still, do not go to great lengths
2700 * to avoid userspace's usage of the feature, because it is a
2701 * fringe case that is not enabled except via specific settings
2702 * of the module parameters.
2704 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2707 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2709 case KVM_CAP_NR_VCPUS:
2710 r = KVM_SOFT_MAX_VCPUS;
2712 case KVM_CAP_MAX_VCPUS:
2715 case KVM_CAP_NR_MEMSLOTS:
2716 r = KVM_USER_MEM_SLOTS;
2718 case KVM_CAP_PV_MMU: /* obsolete */
2722 r = KVM_MAX_MCE_BANKS;
2725 r = boot_cpu_has(X86_FEATURE_XSAVE);
2727 case KVM_CAP_TSC_CONTROL:
2728 r = kvm_has_tsc_control;
2730 case KVM_CAP_X2APIC_API:
2731 r = KVM_X2APIC_API_VALID_FLAGS;
2741 long kvm_arch_dev_ioctl(struct file *filp,
2742 unsigned int ioctl, unsigned long arg)
2744 void __user *argp = (void __user *)arg;
2748 case KVM_GET_MSR_INDEX_LIST: {
2749 struct kvm_msr_list __user *user_msr_list = argp;
2750 struct kvm_msr_list msr_list;
2754 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2757 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2758 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2761 if (n < msr_list.nmsrs)
2764 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2765 num_msrs_to_save * sizeof(u32)))
2767 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2769 num_emulated_msrs * sizeof(u32)))
2774 case KVM_GET_SUPPORTED_CPUID:
2775 case KVM_GET_EMULATED_CPUID: {
2776 struct kvm_cpuid2 __user *cpuid_arg = argp;
2777 struct kvm_cpuid2 cpuid;
2780 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2783 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2789 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2794 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2796 if (copy_to_user(argp, &kvm_mce_cap_supported,
2797 sizeof(kvm_mce_cap_supported)))
2809 static void wbinvd_ipi(void *garbage)
2814 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2816 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2819 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2821 /* Address WBINVD may be executed by guest */
2822 if (need_emulate_wbinvd(vcpu)) {
2823 if (kvm_x86_ops->has_wbinvd_exit())
2824 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2825 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2826 smp_call_function_single(vcpu->cpu,
2827 wbinvd_ipi, NULL, 1);
2830 kvm_x86_ops->vcpu_load(vcpu, cpu);
2832 /* Apply any externally detected TSC adjustments (due to suspend) */
2833 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2834 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2835 vcpu->arch.tsc_offset_adjustment = 0;
2836 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2839 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2840 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2841 rdtsc() - vcpu->arch.last_host_tsc;
2843 mark_tsc_unstable("KVM discovered backwards TSC");
2845 if (check_tsc_unstable()) {
2846 u64 offset = kvm_compute_tsc_offset(vcpu,
2847 vcpu->arch.last_guest_tsc);
2848 kvm_vcpu_write_tsc_offset(vcpu, offset);
2849 vcpu->arch.tsc_catchup = 1;
2852 if (kvm_lapic_hv_timer_in_use(vcpu))
2853 kvm_lapic_restart_hv_timer(vcpu);
2856 * On a host with synchronized TSC, there is no need to update
2857 * kvmclock on vcpu->cpu migration
2859 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2860 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2861 if (vcpu->cpu != cpu)
2862 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
2866 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2869 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2871 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2874 vcpu->arch.st.steal.preempted = 1;
2876 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
2877 &vcpu->arch.st.steal.preempted,
2878 offsetof(struct kvm_steal_time, preempted),
2879 sizeof(vcpu->arch.st.steal.preempted));
2882 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2886 * Disable page faults because we're in atomic context here.
2887 * kvm_write_guest_offset_cached() would call might_fault()
2888 * that relies on pagefault_disable() to tell if there's a
2889 * bug. NOTE: the write to guest memory may not go through if
2890 * during postcopy live migration or if there's heavy guest
2893 pagefault_disable();
2895 * kvm_memslots() will be called by
2896 * kvm_write_guest_offset_cached() so take the srcu lock.
2898 idx = srcu_read_lock(&vcpu->kvm->srcu);
2899 kvm_steal_time_set_preempted(vcpu);
2900 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2902 kvm_x86_ops->vcpu_put(vcpu);
2903 kvm_put_guest_fpu(vcpu);
2904 vcpu->arch.last_host_tsc = rdtsc();
2907 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2908 struct kvm_lapic_state *s)
2910 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
2911 kvm_x86_ops->sync_pir_to_irr(vcpu);
2913 return kvm_apic_get_state(vcpu, s);
2916 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2917 struct kvm_lapic_state *s)
2921 r = kvm_apic_set_state(vcpu, s);
2924 update_cr8_intercept(vcpu);
2929 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2931 return (!lapic_in_kernel(vcpu) ||
2932 kvm_apic_accept_pic_intr(vcpu));
2936 * if userspace requested an interrupt window, check that the
2937 * interrupt window is open.
2939 * No need to exit to userspace if we already have an interrupt queued.
2941 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2943 return kvm_arch_interrupt_allowed(vcpu) &&
2944 !kvm_cpu_has_interrupt(vcpu) &&
2945 !kvm_event_needs_reinjection(vcpu) &&
2946 kvm_cpu_accept_dm_intr(vcpu);
2949 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2950 struct kvm_interrupt *irq)
2952 if (irq->irq >= KVM_NR_INTERRUPTS)
2955 if (!irqchip_in_kernel(vcpu->kvm)) {
2956 kvm_queue_interrupt(vcpu, irq->irq, false);
2957 kvm_make_request(KVM_REQ_EVENT, vcpu);
2962 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2963 * fail for in-kernel 8259.
2965 if (pic_in_kernel(vcpu->kvm))
2968 if (vcpu->arch.pending_external_vector != -1)
2971 vcpu->arch.pending_external_vector = irq->irq;
2972 kvm_make_request(KVM_REQ_EVENT, vcpu);
2976 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2978 kvm_inject_nmi(vcpu);
2983 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2985 kvm_make_request(KVM_REQ_SMI, vcpu);
2990 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2991 struct kvm_tpr_access_ctl *tac)
2995 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2999 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3003 unsigned bank_num = mcg_cap & 0xff, bank;
3006 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3008 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3011 vcpu->arch.mcg_cap = mcg_cap;
3012 /* Init IA32_MCG_CTL to all 1s */
3013 if (mcg_cap & MCG_CTL_P)
3014 vcpu->arch.mcg_ctl = ~(u64)0;
3015 /* Init IA32_MCi_CTL to all 1s */
3016 for (bank = 0; bank < bank_num; bank++)
3017 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3019 if (kvm_x86_ops->setup_mce)
3020 kvm_x86_ops->setup_mce(vcpu);
3025 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3026 struct kvm_x86_mce *mce)
3028 u64 mcg_cap = vcpu->arch.mcg_cap;
3029 unsigned bank_num = mcg_cap & 0xff;
3030 u64 *banks = vcpu->arch.mce_banks;
3032 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3035 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3036 * reporting is disabled
3038 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3039 vcpu->arch.mcg_ctl != ~(u64)0)
3041 banks += 4 * mce->bank;
3043 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3044 * reporting is disabled for the bank
3046 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3048 if (mce->status & MCI_STATUS_UC) {
3049 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3050 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3051 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3054 if (banks[1] & MCI_STATUS_VAL)
3055 mce->status |= MCI_STATUS_OVER;
3056 banks[2] = mce->addr;
3057 banks[3] = mce->misc;
3058 vcpu->arch.mcg_status = mce->mcg_status;
3059 banks[1] = mce->status;
3060 kvm_queue_exception(vcpu, MC_VECTOR);
3061 } else if (!(banks[1] & MCI_STATUS_VAL)
3062 || !(banks[1] & MCI_STATUS_UC)) {
3063 if (banks[1] & MCI_STATUS_VAL)
3064 mce->status |= MCI_STATUS_OVER;
3065 banks[2] = mce->addr;
3066 banks[3] = mce->misc;
3067 banks[1] = mce->status;
3069 banks[1] |= MCI_STATUS_OVER;
3073 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3074 struct kvm_vcpu_events *events)
3077 events->exception.injected =
3078 vcpu->arch.exception.pending &&
3079 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3080 events->exception.nr = vcpu->arch.exception.nr;
3081 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3082 events->exception.pad = 0;
3083 events->exception.error_code = vcpu->arch.exception.error_code;
3085 events->interrupt.injected =
3086 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3087 events->interrupt.nr = vcpu->arch.interrupt.nr;
3088 events->interrupt.soft = 0;
3089 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3091 events->nmi.injected = vcpu->arch.nmi_injected;
3092 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3093 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3094 events->nmi.pad = 0;
3096 events->sipi_vector = 0; /* never valid when reporting to user space */
3098 events->smi.smm = is_smm(vcpu);
3099 events->smi.pending = vcpu->arch.smi_pending;
3100 events->smi.smm_inside_nmi =
3101 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3102 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3104 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3105 | KVM_VCPUEVENT_VALID_SHADOW
3106 | KVM_VCPUEVENT_VALID_SMM);
3107 memset(&events->reserved, 0, sizeof(events->reserved));
3110 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3112 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3113 struct kvm_vcpu_events *events)
3115 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3116 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3117 | KVM_VCPUEVENT_VALID_SHADOW
3118 | KVM_VCPUEVENT_VALID_SMM))
3121 if (events->exception.injected &&
3122 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3123 is_guest_mode(vcpu)))
3126 /* INITs are latched while in SMM */
3127 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3128 (events->smi.smm || events->smi.pending) &&
3129 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3133 vcpu->arch.exception.pending = events->exception.injected;
3134 vcpu->arch.exception.nr = events->exception.nr;
3135 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3136 vcpu->arch.exception.error_code = events->exception.error_code;
3138 vcpu->arch.interrupt.pending = events->interrupt.injected;
3139 vcpu->arch.interrupt.nr = events->interrupt.nr;
3140 vcpu->arch.interrupt.soft = events->interrupt.soft;
3141 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3142 kvm_x86_ops->set_interrupt_shadow(vcpu,
3143 events->interrupt.shadow);
3145 vcpu->arch.nmi_injected = events->nmi.injected;
3146 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3147 vcpu->arch.nmi_pending = events->nmi.pending;
3148 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3150 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3151 lapic_in_kernel(vcpu))
3152 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3154 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3155 u32 hflags = vcpu->arch.hflags;
3156 if (events->smi.smm)
3157 hflags |= HF_SMM_MASK;
3159 hflags &= ~HF_SMM_MASK;
3160 kvm_set_hflags(vcpu, hflags);
3162 vcpu->arch.smi_pending = events->smi.pending;
3164 if (events->smi.smm) {
3165 if (events->smi.smm_inside_nmi)
3166 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3168 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3169 if (lapic_in_kernel(vcpu)) {
3170 if (events->smi.latched_init)
3171 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3173 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3178 kvm_make_request(KVM_REQ_EVENT, vcpu);
3183 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3184 struct kvm_debugregs *dbgregs)
3188 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3189 kvm_get_dr(vcpu, 6, &val);
3191 dbgregs->dr7 = vcpu->arch.dr7;
3193 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3196 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3197 struct kvm_debugregs *dbgregs)
3202 if (dbgregs->dr6 & ~0xffffffffull)
3204 if (dbgregs->dr7 & ~0xffffffffull)
3207 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3208 kvm_update_dr0123(vcpu);
3209 vcpu->arch.dr6 = dbgregs->dr6;
3210 kvm_update_dr6(vcpu);
3211 vcpu->arch.dr7 = dbgregs->dr7;
3212 kvm_update_dr7(vcpu);
3217 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3219 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3221 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3222 u64 xstate_bv = xsave->header.xfeatures;
3226 * Copy legacy XSAVE area, to avoid complications with CPUID
3227 * leaves 0 and 1 in the loop below.
3229 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3232 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3233 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3236 * Copy each region from the possibly compacted offset to the
3237 * non-compacted offset.
3239 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3241 u64 feature = valid & -valid;
3242 int index = fls64(feature) - 1;
3243 void *src = get_xsave_addr(xsave, feature);
3246 u32 size, offset, ecx, edx;
3247 cpuid_count(XSTATE_CPUID, index,
3248 &size, &offset, &ecx, &edx);
3249 memcpy(dest + offset, src, size);
3256 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3258 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3259 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3263 * Copy legacy XSAVE area, to avoid complications with CPUID
3264 * leaves 0 and 1 in the loop below.
3266 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3268 /* Set XSTATE_BV and possibly XCOMP_BV. */
3269 xsave->header.xfeatures = xstate_bv;
3270 if (boot_cpu_has(X86_FEATURE_XSAVES))
3271 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3274 * Copy each region from the non-compacted offset to the
3275 * possibly compacted offset.
3277 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3279 u64 feature = valid & -valid;
3280 int index = fls64(feature) - 1;
3281 void *dest = get_xsave_addr(xsave, feature);
3284 u32 size, offset, ecx, edx;
3285 cpuid_count(XSTATE_CPUID, index,
3286 &size, &offset, &ecx, &edx);
3287 memcpy(dest, src + offset, size);
3294 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3295 struct kvm_xsave *guest_xsave)
3297 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3298 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3299 fill_xsave((u8 *) guest_xsave->region, vcpu);
3301 memcpy(guest_xsave->region,
3302 &vcpu->arch.guest_fpu.state.fxsave,
3303 sizeof(struct fxregs_state));
3304 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3305 XFEATURE_MASK_FPSSE;
3309 #define XSAVE_MXCSR_OFFSET 24
3311 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3312 struct kvm_xsave *guest_xsave)
3315 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3316 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3318 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3320 * Here we allow setting states that are not present in
3321 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3322 * with old userspace.
3324 if (xstate_bv & ~kvm_supported_xcr0() ||
3325 mxcsr & ~mxcsr_feature_mask)
3327 load_xsave(vcpu, (u8 *)guest_xsave->region);
3329 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3330 mxcsr & ~mxcsr_feature_mask)
3332 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3333 guest_xsave->region, sizeof(struct fxregs_state));
3338 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3339 struct kvm_xcrs *guest_xcrs)
3341 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3342 guest_xcrs->nr_xcrs = 0;
3346 guest_xcrs->nr_xcrs = 1;
3347 guest_xcrs->flags = 0;
3348 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3349 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3352 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3353 struct kvm_xcrs *guest_xcrs)
3357 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3360 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3363 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3364 /* Only support XCR0 currently */
3365 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3366 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3367 guest_xcrs->xcrs[i].value);
3376 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3377 * stopped by the hypervisor. This function will be called from the host only.
3378 * EINVAL is returned when the host attempts to set the flag for a guest that
3379 * does not support pv clocks.
3381 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3383 if (!vcpu->arch.pv_time_enabled)
3385 vcpu->arch.pvclock_set_guest_stopped_request = true;
3386 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3390 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3391 struct kvm_enable_cap *cap)
3397 case KVM_CAP_HYPERV_SYNIC2:
3400 case KVM_CAP_HYPERV_SYNIC:
3401 if (!irqchip_in_kernel(vcpu->kvm))
3403 return kvm_hv_activate_synic(vcpu, cap->cap ==
3404 KVM_CAP_HYPERV_SYNIC2);
3410 long kvm_arch_vcpu_ioctl(struct file *filp,
3411 unsigned int ioctl, unsigned long arg)
3413 struct kvm_vcpu *vcpu = filp->private_data;
3414 void __user *argp = (void __user *)arg;
3417 struct kvm_lapic_state *lapic;
3418 struct kvm_xsave *xsave;
3419 struct kvm_xcrs *xcrs;
3425 case KVM_GET_LAPIC: {
3427 if (!lapic_in_kernel(vcpu))
3429 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3434 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3438 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3443 case KVM_SET_LAPIC: {
3445 if (!lapic_in_kernel(vcpu))
3447 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3448 if (IS_ERR(u.lapic))
3449 return PTR_ERR(u.lapic);
3451 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3454 case KVM_INTERRUPT: {
3455 struct kvm_interrupt irq;
3458 if (copy_from_user(&irq, argp, sizeof irq))
3460 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3464 r = kvm_vcpu_ioctl_nmi(vcpu);
3468 r = kvm_vcpu_ioctl_smi(vcpu);
3471 case KVM_SET_CPUID: {
3472 struct kvm_cpuid __user *cpuid_arg = argp;
3473 struct kvm_cpuid cpuid;
3476 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3478 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3481 case KVM_SET_CPUID2: {
3482 struct kvm_cpuid2 __user *cpuid_arg = argp;
3483 struct kvm_cpuid2 cpuid;
3486 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3488 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3489 cpuid_arg->entries);
3492 case KVM_GET_CPUID2: {
3493 struct kvm_cpuid2 __user *cpuid_arg = argp;
3494 struct kvm_cpuid2 cpuid;
3497 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3499 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3500 cpuid_arg->entries);
3504 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3510 r = msr_io(vcpu, argp, do_get_msr, 1);
3513 r = msr_io(vcpu, argp, do_set_msr, 0);
3515 case KVM_TPR_ACCESS_REPORTING: {
3516 struct kvm_tpr_access_ctl tac;
3519 if (copy_from_user(&tac, argp, sizeof tac))
3521 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3525 if (copy_to_user(argp, &tac, sizeof tac))
3530 case KVM_SET_VAPIC_ADDR: {
3531 struct kvm_vapic_addr va;
3535 if (!lapic_in_kernel(vcpu))
3538 if (copy_from_user(&va, argp, sizeof va))
3540 idx = srcu_read_lock(&vcpu->kvm->srcu);
3541 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3542 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3545 case KVM_X86_SETUP_MCE: {
3549 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3551 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3554 case KVM_X86_SET_MCE: {
3555 struct kvm_x86_mce mce;
3558 if (copy_from_user(&mce, argp, sizeof mce))
3560 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3563 case KVM_GET_VCPU_EVENTS: {
3564 struct kvm_vcpu_events events;
3566 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3569 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3574 case KVM_SET_VCPU_EVENTS: {
3575 struct kvm_vcpu_events events;
3578 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3581 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3584 case KVM_GET_DEBUGREGS: {
3585 struct kvm_debugregs dbgregs;
3587 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3590 if (copy_to_user(argp, &dbgregs,
3591 sizeof(struct kvm_debugregs)))
3596 case KVM_SET_DEBUGREGS: {
3597 struct kvm_debugregs dbgregs;
3600 if (copy_from_user(&dbgregs, argp,
3601 sizeof(struct kvm_debugregs)))
3604 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3607 case KVM_GET_XSAVE: {
3608 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3613 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3616 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3621 case KVM_SET_XSAVE: {
3622 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3623 if (IS_ERR(u.xsave))
3624 return PTR_ERR(u.xsave);
3626 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3629 case KVM_GET_XCRS: {
3630 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3635 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3638 if (copy_to_user(argp, u.xcrs,
3639 sizeof(struct kvm_xcrs)))
3644 case KVM_SET_XCRS: {
3645 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3647 return PTR_ERR(u.xcrs);
3649 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3652 case KVM_SET_TSC_KHZ: {
3656 user_tsc_khz = (u32)arg;
3658 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3661 if (user_tsc_khz == 0)
3662 user_tsc_khz = tsc_khz;
3664 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3669 case KVM_GET_TSC_KHZ: {
3670 r = vcpu->arch.virtual_tsc_khz;
3673 case KVM_KVMCLOCK_CTRL: {
3674 r = kvm_set_guest_paused(vcpu);
3677 case KVM_ENABLE_CAP: {
3678 struct kvm_enable_cap cap;
3681 if (copy_from_user(&cap, argp, sizeof(cap)))
3683 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3694 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3696 return VM_FAULT_SIGBUS;
3699 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3703 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3705 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3709 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3712 kvm->arch.ept_identity_map_addr = ident_addr;
3716 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3717 u32 kvm_nr_mmu_pages)
3719 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3722 mutex_lock(&kvm->slots_lock);
3724 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3725 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3727 mutex_unlock(&kvm->slots_lock);
3731 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3733 return kvm->arch.n_max_mmu_pages;
3736 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3738 struct kvm_pic *pic = kvm->arch.vpic;
3742 switch (chip->chip_id) {
3743 case KVM_IRQCHIP_PIC_MASTER:
3744 memcpy(&chip->chip.pic, &pic->pics[0],
3745 sizeof(struct kvm_pic_state));
3747 case KVM_IRQCHIP_PIC_SLAVE:
3748 memcpy(&chip->chip.pic, &pic->pics[1],
3749 sizeof(struct kvm_pic_state));
3751 case KVM_IRQCHIP_IOAPIC:
3752 kvm_get_ioapic(kvm, &chip->chip.ioapic);
3761 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3763 struct kvm_pic *pic = kvm->arch.vpic;
3767 switch (chip->chip_id) {
3768 case KVM_IRQCHIP_PIC_MASTER:
3769 spin_lock(&pic->lock);
3770 memcpy(&pic->pics[0], &chip->chip.pic,
3771 sizeof(struct kvm_pic_state));
3772 spin_unlock(&pic->lock);
3774 case KVM_IRQCHIP_PIC_SLAVE:
3775 spin_lock(&pic->lock);
3776 memcpy(&pic->pics[1], &chip->chip.pic,
3777 sizeof(struct kvm_pic_state));
3778 spin_unlock(&pic->lock);
3780 case KVM_IRQCHIP_IOAPIC:
3781 kvm_set_ioapic(kvm, &chip->chip.ioapic);
3787 kvm_pic_update_irq(pic);
3791 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3793 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3795 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3797 mutex_lock(&kps->lock);
3798 memcpy(ps, &kps->channels, sizeof(*ps));
3799 mutex_unlock(&kps->lock);
3803 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3806 struct kvm_pit *pit = kvm->arch.vpit;
3808 mutex_lock(&pit->pit_state.lock);
3809 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3810 for (i = 0; i < 3; i++)
3811 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3812 mutex_unlock(&pit->pit_state.lock);
3816 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3818 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3819 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3820 sizeof(ps->channels));
3821 ps->flags = kvm->arch.vpit->pit_state.flags;
3822 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3823 memset(&ps->reserved, 0, sizeof(ps->reserved));
3827 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3831 u32 prev_legacy, cur_legacy;
3832 struct kvm_pit *pit = kvm->arch.vpit;
3834 mutex_lock(&pit->pit_state.lock);
3835 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3836 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3837 if (!prev_legacy && cur_legacy)
3839 memcpy(&pit->pit_state.channels, &ps->channels,
3840 sizeof(pit->pit_state.channels));
3841 pit->pit_state.flags = ps->flags;
3842 for (i = 0; i < 3; i++)
3843 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3845 mutex_unlock(&pit->pit_state.lock);
3849 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3850 struct kvm_reinject_control *control)
3852 struct kvm_pit *pit = kvm->arch.vpit;
3857 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3858 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3859 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3861 mutex_lock(&pit->pit_state.lock);
3862 kvm_pit_set_reinject(pit, control->pit_reinject);
3863 mutex_unlock(&pit->pit_state.lock);
3869 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3870 * @kvm: kvm instance
3871 * @log: slot id and address to which we copy the log
3873 * Steps 1-4 below provide general overview of dirty page logging. See
3874 * kvm_get_dirty_log_protect() function description for additional details.
3876 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3877 * always flush the TLB (step 4) even if previous step failed and the dirty
3878 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3879 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3880 * writes will be marked dirty for next log read.
3882 * 1. Take a snapshot of the bit and clear it if needed.
3883 * 2. Write protect the corresponding page.
3884 * 3. Copy the snapshot to the userspace.
3885 * 4. Flush TLB's if needed.
3887 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3889 bool is_dirty = false;
3892 mutex_lock(&kvm->slots_lock);
3895 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3897 if (kvm_x86_ops->flush_log_dirty)
3898 kvm_x86_ops->flush_log_dirty(kvm);
3900 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3903 * All the TLBs can be flushed out of mmu lock, see the comments in
3904 * kvm_mmu_slot_remove_write_access().
3906 lockdep_assert_held(&kvm->slots_lock);
3908 kvm_flush_remote_tlbs(kvm);
3910 mutex_unlock(&kvm->slots_lock);
3914 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3917 if (!irqchip_in_kernel(kvm))
3920 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3921 irq_event->irq, irq_event->level,
3926 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3927 struct kvm_enable_cap *cap)
3935 case KVM_CAP_DISABLE_QUIRKS:
3936 kvm->arch.disabled_quirks = cap->args[0];
3939 case KVM_CAP_SPLIT_IRQCHIP: {
3940 mutex_lock(&kvm->lock);
3942 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3943 goto split_irqchip_unlock;
3945 if (irqchip_in_kernel(kvm))
3946 goto split_irqchip_unlock;
3947 if (kvm->created_vcpus)
3948 goto split_irqchip_unlock;
3949 r = kvm_setup_empty_irq_routing(kvm);
3951 goto split_irqchip_unlock;
3952 /* Pairs with irqchip_in_kernel. */
3954 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
3955 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3957 split_irqchip_unlock:
3958 mutex_unlock(&kvm->lock);
3961 case KVM_CAP_X2APIC_API:
3963 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3966 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3967 kvm->arch.x2apic_format = true;
3968 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3969 kvm->arch.x2apic_broadcast_quirk_disabled = true;
3980 long kvm_arch_vm_ioctl(struct file *filp,
3981 unsigned int ioctl, unsigned long arg)
3983 struct kvm *kvm = filp->private_data;
3984 void __user *argp = (void __user *)arg;
3987 * This union makes it completely explicit to gcc-3.x
3988 * that these two variables' stack usage should be
3989 * combined, not added together.
3992 struct kvm_pit_state ps;
3993 struct kvm_pit_state2 ps2;
3994 struct kvm_pit_config pit_config;
3998 case KVM_SET_TSS_ADDR:
3999 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4001 case KVM_SET_IDENTITY_MAP_ADDR: {
4005 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4007 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4010 case KVM_SET_NR_MMU_PAGES:
4011 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4013 case KVM_GET_NR_MMU_PAGES:
4014 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4016 case KVM_CREATE_IRQCHIP: {
4017 mutex_lock(&kvm->lock);
4020 if (irqchip_in_kernel(kvm))
4021 goto create_irqchip_unlock;
4024 if (kvm->created_vcpus)
4025 goto create_irqchip_unlock;
4027 r = kvm_pic_init(kvm);
4029 goto create_irqchip_unlock;
4031 r = kvm_ioapic_init(kvm);
4033 kvm_pic_destroy(kvm);
4034 goto create_irqchip_unlock;
4037 r = kvm_setup_default_irq_routing(kvm);
4039 kvm_ioapic_destroy(kvm);
4040 kvm_pic_destroy(kvm);
4041 goto create_irqchip_unlock;
4043 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4045 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4046 create_irqchip_unlock:
4047 mutex_unlock(&kvm->lock);
4050 case KVM_CREATE_PIT:
4051 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4053 case KVM_CREATE_PIT2:
4055 if (copy_from_user(&u.pit_config, argp,
4056 sizeof(struct kvm_pit_config)))
4059 mutex_lock(&kvm->lock);
4062 goto create_pit_unlock;
4064 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4068 mutex_unlock(&kvm->lock);
4070 case KVM_GET_IRQCHIP: {
4071 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4072 struct kvm_irqchip *chip;
4074 chip = memdup_user(argp, sizeof(*chip));
4081 if (!irqchip_kernel(kvm))
4082 goto get_irqchip_out;
4083 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4085 goto get_irqchip_out;
4087 if (copy_to_user(argp, chip, sizeof *chip))
4088 goto get_irqchip_out;
4094 case KVM_SET_IRQCHIP: {
4095 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4096 struct kvm_irqchip *chip;
4098 chip = memdup_user(argp, sizeof(*chip));
4105 if (!irqchip_kernel(kvm))
4106 goto set_irqchip_out;
4107 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4109 goto set_irqchip_out;
4117 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4120 if (!kvm->arch.vpit)
4122 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4126 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4133 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4136 if (!kvm->arch.vpit)
4138 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4141 case KVM_GET_PIT2: {
4143 if (!kvm->arch.vpit)
4145 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4149 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4154 case KVM_SET_PIT2: {
4156 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4159 if (!kvm->arch.vpit)
4161 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4164 case KVM_REINJECT_CONTROL: {
4165 struct kvm_reinject_control control;
4167 if (copy_from_user(&control, argp, sizeof(control)))
4169 r = kvm_vm_ioctl_reinject(kvm, &control);
4172 case KVM_SET_BOOT_CPU_ID:
4174 mutex_lock(&kvm->lock);
4175 if (kvm->created_vcpus)
4178 kvm->arch.bsp_vcpu_id = arg;
4179 mutex_unlock(&kvm->lock);
4181 case KVM_XEN_HVM_CONFIG: {
4183 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4184 sizeof(struct kvm_xen_hvm_config)))
4187 if (kvm->arch.xen_hvm_config.flags)
4192 case KVM_SET_CLOCK: {
4193 struct kvm_clock_data user_ns;
4197 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4206 * TODO: userspace has to take care of races with VCPU_RUN, so
4207 * kvm_gen_update_masterclock() can be cut down to locked
4208 * pvclock_update_vm_gtod_copy().
4210 kvm_gen_update_masterclock(kvm);
4211 now_ns = get_kvmclock_ns(kvm);
4212 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4213 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4216 case KVM_GET_CLOCK: {
4217 struct kvm_clock_data user_ns;
4220 now_ns = get_kvmclock_ns(kvm);
4221 user_ns.clock = now_ns;
4222 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4223 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4226 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4231 case KVM_ENABLE_CAP: {
4232 struct kvm_enable_cap cap;
4235 if (copy_from_user(&cap, argp, sizeof(cap)))
4237 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4247 static void kvm_init_msr_list(void)
4252 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4253 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4257 * Even MSRs that are valid in the host may not be exposed
4258 * to the guests in some cases.
4260 switch (msrs_to_save[i]) {
4261 case MSR_IA32_BNDCFGS:
4262 if (!kvm_x86_ops->mpx_supported())
4266 if (!kvm_x86_ops->rdtscp_supported())
4274 msrs_to_save[j] = msrs_to_save[i];
4277 num_msrs_to_save = j;
4279 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4280 switch (emulated_msrs[i]) {
4281 case MSR_IA32_SMBASE:
4282 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4290 emulated_msrs[j] = emulated_msrs[i];
4293 num_emulated_msrs = j;
4296 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4304 if (!(lapic_in_kernel(vcpu) &&
4305 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4306 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4317 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4324 if (!(lapic_in_kernel(vcpu) &&
4325 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4327 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4329 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4339 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4340 struct kvm_segment *var, int seg)
4342 kvm_x86_ops->set_segment(vcpu, var, seg);
4345 void kvm_get_segment(struct kvm_vcpu *vcpu,
4346 struct kvm_segment *var, int seg)
4348 kvm_x86_ops->get_segment(vcpu, var, seg);
4351 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4352 struct x86_exception *exception)
4356 BUG_ON(!mmu_is_nested(vcpu));
4358 /* NPT walks are always user-walks */
4359 access |= PFERR_USER_MASK;
4360 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4365 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4366 struct x86_exception *exception)
4368 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4369 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4372 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4373 struct x86_exception *exception)
4375 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4376 access |= PFERR_FETCH_MASK;
4377 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4380 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4381 struct x86_exception *exception)
4383 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4384 access |= PFERR_WRITE_MASK;
4385 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4388 /* uses this to access any guest's mapped memory without checking CPL */
4389 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4390 struct x86_exception *exception)
4392 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4395 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4396 struct kvm_vcpu *vcpu, u32 access,
4397 struct x86_exception *exception)
4400 int r = X86EMUL_CONTINUE;
4403 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4405 unsigned offset = addr & (PAGE_SIZE-1);
4406 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4409 if (gpa == UNMAPPED_GVA)
4410 return X86EMUL_PROPAGATE_FAULT;
4411 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4414 r = X86EMUL_IO_NEEDED;
4426 /* used for instruction fetching */
4427 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4428 gva_t addr, void *val, unsigned int bytes,
4429 struct x86_exception *exception)
4431 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4432 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4436 /* Inline kvm_read_guest_virt_helper for speed. */
4437 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4439 if (unlikely(gpa == UNMAPPED_GVA))
4440 return X86EMUL_PROPAGATE_FAULT;
4442 offset = addr & (PAGE_SIZE-1);
4443 if (WARN_ON(offset + bytes > PAGE_SIZE))
4444 bytes = (unsigned)PAGE_SIZE - offset;
4445 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4447 if (unlikely(ret < 0))
4448 return X86EMUL_IO_NEEDED;
4450 return X86EMUL_CONTINUE;
4453 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4454 gva_t addr, void *val, unsigned int bytes,
4455 struct x86_exception *exception)
4457 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4458 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4460 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4463 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4465 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4466 gva_t addr, void *val, unsigned int bytes,
4467 struct x86_exception *exception)
4469 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4470 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4473 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4474 unsigned long addr, void *val, unsigned int bytes)
4476 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4477 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4479 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4482 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4483 gva_t addr, void *val,
4485 struct x86_exception *exception)
4487 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4489 int r = X86EMUL_CONTINUE;
4492 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4495 unsigned offset = addr & (PAGE_SIZE-1);
4496 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4499 if (gpa == UNMAPPED_GVA)
4500 return X86EMUL_PROPAGATE_FAULT;
4501 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4503 r = X86EMUL_IO_NEEDED;
4514 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4516 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4517 gpa_t gpa, bool write)
4519 /* For APIC access vmexit */
4520 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4523 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4524 trace_vcpu_match_mmio(gva, gpa, write, true);
4531 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4532 gpa_t *gpa, struct x86_exception *exception,
4535 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4536 | (write ? PFERR_WRITE_MASK : 0);
4539 * currently PKRU is only applied to ept enabled guest so
4540 * there is no pkey in EPT page table for L1 guest or EPT
4541 * shadow page table for L2 guest.
4543 if (vcpu_match_mmio_gva(vcpu, gva)
4544 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4545 vcpu->arch.access, 0, access)) {
4546 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4547 (gva & (PAGE_SIZE - 1));
4548 trace_vcpu_match_mmio(gva, *gpa, write, false);
4552 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4554 if (*gpa == UNMAPPED_GVA)
4557 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4560 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4561 const void *val, int bytes)
4565 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4568 kvm_page_track_write(vcpu, gpa, val, bytes);
4572 struct read_write_emulator_ops {
4573 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4575 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4576 void *val, int bytes);
4577 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4578 int bytes, void *val);
4579 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4580 void *val, int bytes);
4584 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4586 if (vcpu->mmio_read_completed) {
4587 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4588 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4589 vcpu->mmio_read_completed = 0;
4596 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4597 void *val, int bytes)
4599 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4602 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4603 void *val, int bytes)
4605 return emulator_write_phys(vcpu, gpa, val, bytes);
4608 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4610 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4611 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4614 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4615 void *val, int bytes)
4617 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4618 return X86EMUL_IO_NEEDED;
4621 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4622 void *val, int bytes)
4624 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4626 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4627 return X86EMUL_CONTINUE;
4630 static const struct read_write_emulator_ops read_emultor = {
4631 .read_write_prepare = read_prepare,
4632 .read_write_emulate = read_emulate,
4633 .read_write_mmio = vcpu_mmio_read,
4634 .read_write_exit_mmio = read_exit_mmio,
4637 static const struct read_write_emulator_ops write_emultor = {
4638 .read_write_emulate = write_emulate,
4639 .read_write_mmio = write_mmio,
4640 .read_write_exit_mmio = write_exit_mmio,
4644 static int emulator_read_write_onepage(unsigned long addr, void *val,
4646 struct x86_exception *exception,
4647 struct kvm_vcpu *vcpu,
4648 const struct read_write_emulator_ops *ops)
4652 bool write = ops->write;
4653 struct kvm_mmio_fragment *frag;
4654 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4657 * If the exit was due to a NPF we may already have a GPA.
4658 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4659 * Note, this cannot be used on string operations since string
4660 * operation using rep will only have the initial GPA from the NPF
4663 if (vcpu->arch.gpa_available &&
4664 emulator_can_use_gpa(ctxt) &&
4665 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4666 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4667 gpa = exception->address;
4671 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4674 return X86EMUL_PROPAGATE_FAULT;
4676 /* For APIC access vmexit */
4680 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4681 return X86EMUL_CONTINUE;
4685 * Is this MMIO handled locally?
4687 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4688 if (handled == bytes)
4689 return X86EMUL_CONTINUE;
4695 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4696 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4700 return X86EMUL_CONTINUE;
4703 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4705 void *val, unsigned int bytes,
4706 struct x86_exception *exception,
4707 const struct read_write_emulator_ops *ops)
4709 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4713 if (ops->read_write_prepare &&
4714 ops->read_write_prepare(vcpu, val, bytes))
4715 return X86EMUL_CONTINUE;
4717 vcpu->mmio_nr_fragments = 0;
4719 /* Crossing a page boundary? */
4720 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4723 now = -addr & ~PAGE_MASK;
4724 rc = emulator_read_write_onepage(addr, val, now, exception,
4727 if (rc != X86EMUL_CONTINUE)
4730 if (ctxt->mode != X86EMUL_MODE_PROT64)
4736 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4738 if (rc != X86EMUL_CONTINUE)
4741 if (!vcpu->mmio_nr_fragments)
4744 gpa = vcpu->mmio_fragments[0].gpa;
4746 vcpu->mmio_needed = 1;
4747 vcpu->mmio_cur_fragment = 0;
4749 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4750 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4751 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4752 vcpu->run->mmio.phys_addr = gpa;
4754 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4757 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4761 struct x86_exception *exception)
4763 return emulator_read_write(ctxt, addr, val, bytes,
4764 exception, &read_emultor);
4767 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4771 struct x86_exception *exception)
4773 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4774 exception, &write_emultor);
4777 #define CMPXCHG_TYPE(t, ptr, old, new) \
4778 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4780 #ifdef CONFIG_X86_64
4781 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4783 # define CMPXCHG64(ptr, old, new) \
4784 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4787 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4792 struct x86_exception *exception)
4794 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4800 /* guests cmpxchg8b have to be emulated atomically */
4801 if (bytes > 8 || (bytes & (bytes - 1)))
4804 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4806 if (gpa == UNMAPPED_GVA ||
4807 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4810 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4813 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4814 if (is_error_page(page))
4817 kaddr = kmap_atomic(page);
4818 kaddr += offset_in_page(gpa);
4821 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4824 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4827 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4830 exchanged = CMPXCHG64(kaddr, old, new);
4835 kunmap_atomic(kaddr);
4836 kvm_release_page_dirty(page);
4839 return X86EMUL_CMPXCHG_FAILED;
4841 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4842 kvm_page_track_write(vcpu, gpa, new, bytes);
4844 return X86EMUL_CONTINUE;
4847 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4849 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4852 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4856 for (i = 0; i < vcpu->arch.pio.count; i++) {
4857 if (vcpu->arch.pio.in)
4858 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4859 vcpu->arch.pio.size, pd);
4861 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4862 vcpu->arch.pio.port, vcpu->arch.pio.size,
4866 pd += vcpu->arch.pio.size;
4871 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4872 unsigned short port, void *val,
4873 unsigned int count, bool in)
4875 vcpu->arch.pio.port = port;
4876 vcpu->arch.pio.in = in;
4877 vcpu->arch.pio.count = count;
4878 vcpu->arch.pio.size = size;
4880 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4881 vcpu->arch.pio.count = 0;
4885 vcpu->run->exit_reason = KVM_EXIT_IO;
4886 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4887 vcpu->run->io.size = size;
4888 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4889 vcpu->run->io.count = count;
4890 vcpu->run->io.port = port;
4895 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4896 int size, unsigned short port, void *val,
4899 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4902 if (vcpu->arch.pio.count)
4905 memset(vcpu->arch.pio_data, 0, size * count);
4907 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4910 memcpy(val, vcpu->arch.pio_data, size * count);
4911 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4912 vcpu->arch.pio.count = 0;
4919 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4920 int size, unsigned short port,
4921 const void *val, unsigned int count)
4923 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4925 memcpy(vcpu->arch.pio_data, val, size * count);
4926 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4927 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4930 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4932 return kvm_x86_ops->get_segment_base(vcpu, seg);
4935 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4937 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4940 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4942 if (!need_emulate_wbinvd(vcpu))
4943 return X86EMUL_CONTINUE;
4945 if (kvm_x86_ops->has_wbinvd_exit()) {
4946 int cpu = get_cpu();
4948 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4949 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4950 wbinvd_ipi, NULL, 1);
4952 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4955 return X86EMUL_CONTINUE;
4958 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4960 kvm_emulate_wbinvd_noskip(vcpu);
4961 return kvm_skip_emulated_instruction(vcpu);
4963 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4967 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4969 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4972 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4973 unsigned long *dest)
4975 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4978 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4979 unsigned long value)
4982 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4985 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4987 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4990 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4992 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4993 unsigned long value;
4997 value = kvm_read_cr0(vcpu);
5000 value = vcpu->arch.cr2;
5003 value = kvm_read_cr3(vcpu);
5006 value = kvm_read_cr4(vcpu);
5009 value = kvm_get_cr8(vcpu);
5012 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5019 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5021 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5026 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5029 vcpu->arch.cr2 = val;
5032 res = kvm_set_cr3(vcpu, val);
5035 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5038 res = kvm_set_cr8(vcpu, val);
5041 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5048 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5050 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5053 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5055 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5058 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5060 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5063 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5065 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5068 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5070 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5073 static unsigned long emulator_get_cached_segment_base(
5074 struct x86_emulate_ctxt *ctxt, int seg)
5076 return get_segment_base(emul_to_vcpu(ctxt), seg);
5079 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5080 struct desc_struct *desc, u32 *base3,
5083 struct kvm_segment var;
5085 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5086 *selector = var.selector;
5089 memset(desc, 0, sizeof(*desc));
5097 set_desc_limit(desc, var.limit);
5098 set_desc_base(desc, (unsigned long)var.base);
5099 #ifdef CONFIG_X86_64
5101 *base3 = var.base >> 32;
5103 desc->type = var.type;
5105 desc->dpl = var.dpl;
5106 desc->p = var.present;
5107 desc->avl = var.avl;
5115 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5116 struct desc_struct *desc, u32 base3,
5119 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5120 struct kvm_segment var;
5122 var.selector = selector;
5123 var.base = get_desc_base(desc);
5124 #ifdef CONFIG_X86_64
5125 var.base |= ((u64)base3) << 32;
5127 var.limit = get_desc_limit(desc);
5129 var.limit = (var.limit << 12) | 0xfff;
5130 var.type = desc->type;
5131 var.dpl = desc->dpl;
5136 var.avl = desc->avl;
5137 var.present = desc->p;
5138 var.unusable = !var.present;
5141 kvm_set_segment(vcpu, &var, seg);
5145 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5146 u32 msr_index, u64 *pdata)
5148 struct msr_data msr;
5151 msr.index = msr_index;
5152 msr.host_initiated = false;
5153 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5161 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5162 u32 msr_index, u64 data)
5164 struct msr_data msr;
5167 msr.index = msr_index;
5168 msr.host_initiated = false;
5169 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5172 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5174 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5176 return vcpu->arch.smbase;
5179 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5181 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5183 vcpu->arch.smbase = smbase;
5186 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5189 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5192 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5193 u32 pmc, u64 *pdata)
5195 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5198 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5200 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5203 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5206 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5209 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5214 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5215 struct x86_instruction_info *info,
5216 enum x86_intercept_stage stage)
5218 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5221 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5222 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5224 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5227 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5229 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5232 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5234 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5237 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5239 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5242 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5244 return emul_to_vcpu(ctxt)->arch.hflags;
5247 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5249 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5252 static const struct x86_emulate_ops emulate_ops = {
5253 .read_gpr = emulator_read_gpr,
5254 .write_gpr = emulator_write_gpr,
5255 .read_std = kvm_read_guest_virt_system,
5256 .write_std = kvm_write_guest_virt_system,
5257 .read_phys = kvm_read_guest_phys_system,
5258 .fetch = kvm_fetch_guest_virt,
5259 .read_emulated = emulator_read_emulated,
5260 .write_emulated = emulator_write_emulated,
5261 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5262 .invlpg = emulator_invlpg,
5263 .pio_in_emulated = emulator_pio_in_emulated,
5264 .pio_out_emulated = emulator_pio_out_emulated,
5265 .get_segment = emulator_get_segment,
5266 .set_segment = emulator_set_segment,
5267 .get_cached_segment_base = emulator_get_cached_segment_base,
5268 .get_gdt = emulator_get_gdt,
5269 .get_idt = emulator_get_idt,
5270 .set_gdt = emulator_set_gdt,
5271 .set_idt = emulator_set_idt,
5272 .get_cr = emulator_get_cr,
5273 .set_cr = emulator_set_cr,
5274 .cpl = emulator_get_cpl,
5275 .get_dr = emulator_get_dr,
5276 .set_dr = emulator_set_dr,
5277 .get_smbase = emulator_get_smbase,
5278 .set_smbase = emulator_set_smbase,
5279 .set_msr = emulator_set_msr,
5280 .get_msr = emulator_get_msr,
5281 .check_pmc = emulator_check_pmc,
5282 .read_pmc = emulator_read_pmc,
5283 .halt = emulator_halt,
5284 .wbinvd = emulator_wbinvd,
5285 .fix_hypercall = emulator_fix_hypercall,
5286 .get_fpu = emulator_get_fpu,
5287 .put_fpu = emulator_put_fpu,
5288 .intercept = emulator_intercept,
5289 .get_cpuid = emulator_get_cpuid,
5290 .set_nmi_mask = emulator_set_nmi_mask,
5291 .get_hflags = emulator_get_hflags,
5292 .set_hflags = emulator_set_hflags,
5295 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5297 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5299 * an sti; sti; sequence only disable interrupts for the first
5300 * instruction. So, if the last instruction, be it emulated or
5301 * not, left the system with the INT_STI flag enabled, it
5302 * means that the last instruction is an sti. We should not
5303 * leave the flag on in this case. The same goes for mov ss
5305 if (int_shadow & mask)
5307 if (unlikely(int_shadow || mask)) {
5308 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5310 kvm_make_request(KVM_REQ_EVENT, vcpu);
5314 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5316 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5317 if (ctxt->exception.vector == PF_VECTOR)
5318 return kvm_propagate_fault(vcpu, &ctxt->exception);
5320 if (ctxt->exception.error_code_valid)
5321 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5322 ctxt->exception.error_code);
5324 kvm_queue_exception(vcpu, ctxt->exception.vector);
5328 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5330 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5333 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5335 ctxt->eflags = kvm_get_rflags(vcpu);
5336 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5338 ctxt->eip = kvm_rip_read(vcpu);
5339 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5340 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5341 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5342 cs_db ? X86EMUL_MODE_PROT32 :
5343 X86EMUL_MODE_PROT16;
5344 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5345 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5346 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5348 init_decode_cache(ctxt);
5349 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5352 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5354 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5357 init_emulate_ctxt(vcpu);
5361 ctxt->_eip = ctxt->eip + inc_eip;
5362 ret = emulate_int_real(ctxt, irq);
5364 if (ret != X86EMUL_CONTINUE)
5365 return EMULATE_FAIL;
5367 ctxt->eip = ctxt->_eip;
5368 kvm_rip_write(vcpu, ctxt->eip);
5369 kvm_set_rflags(vcpu, ctxt->eflags);
5371 if (irq == NMI_VECTOR)
5372 vcpu->arch.nmi_pending = 0;
5374 vcpu->arch.interrupt.pending = false;
5376 return EMULATE_DONE;
5378 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5380 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5382 int r = EMULATE_DONE;
5384 ++vcpu->stat.insn_emulation_fail;
5385 trace_kvm_emulate_insn_failed(vcpu);
5386 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5387 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5388 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5389 vcpu->run->internal.ndata = 0;
5392 kvm_queue_exception(vcpu, UD_VECTOR);
5397 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5398 bool write_fault_to_shadow_pgtable,
5404 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5407 if (!vcpu->arch.mmu.direct_map) {
5409 * Write permission should be allowed since only
5410 * write access need to be emulated.
5412 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5415 * If the mapping is invalid in guest, let cpu retry
5416 * it to generate fault.
5418 if (gpa == UNMAPPED_GVA)
5423 * Do not retry the unhandleable instruction if it faults on the
5424 * readonly host memory, otherwise it will goto a infinite loop:
5425 * retry instruction -> write #PF -> emulation fail -> retry
5426 * instruction -> ...
5428 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5431 * If the instruction failed on the error pfn, it can not be fixed,
5432 * report the error to userspace.
5434 if (is_error_noslot_pfn(pfn))
5437 kvm_release_pfn_clean(pfn);
5439 /* The instructions are well-emulated on direct mmu. */
5440 if (vcpu->arch.mmu.direct_map) {
5441 unsigned int indirect_shadow_pages;
5443 spin_lock(&vcpu->kvm->mmu_lock);
5444 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5445 spin_unlock(&vcpu->kvm->mmu_lock);
5447 if (indirect_shadow_pages)
5448 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5454 * if emulation was due to access to shadowed page table
5455 * and it failed try to unshadow page and re-enter the
5456 * guest to let CPU execute the instruction.
5458 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5461 * If the access faults on its page table, it can not
5462 * be fixed by unprotecting shadow page and it should
5463 * be reported to userspace.
5465 return !write_fault_to_shadow_pgtable;
5468 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5469 unsigned long cr2, int emulation_type)
5471 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5472 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5474 last_retry_eip = vcpu->arch.last_retry_eip;
5475 last_retry_addr = vcpu->arch.last_retry_addr;
5478 * If the emulation is caused by #PF and it is non-page_table
5479 * writing instruction, it means the VM-EXIT is caused by shadow
5480 * page protected, we can zap the shadow page and retry this
5481 * instruction directly.
5483 * Note: if the guest uses a non-page-table modifying instruction
5484 * on the PDE that points to the instruction, then we will unmap
5485 * the instruction and go to an infinite loop. So, we cache the
5486 * last retried eip and the last fault address, if we meet the eip
5487 * and the address again, we can break out of the potential infinite
5490 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5492 if (!(emulation_type & EMULTYPE_RETRY))
5495 if (x86_page_table_writing_insn(ctxt))
5498 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5501 vcpu->arch.last_retry_eip = ctxt->eip;
5502 vcpu->arch.last_retry_addr = cr2;
5504 if (!vcpu->arch.mmu.direct_map)
5505 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5507 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5512 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5513 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5515 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5517 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5518 /* This is a good place to trace that we are exiting SMM. */
5519 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5521 /* Process a latched INIT or SMI, if any. */
5522 kvm_make_request(KVM_REQ_EVENT, vcpu);
5525 kvm_mmu_reset_context(vcpu);
5528 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5530 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5532 vcpu->arch.hflags = emul_flags;
5534 if (changed & HF_SMM_MASK)
5535 kvm_smm_changed(vcpu);
5538 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5547 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5548 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5553 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
5555 struct kvm_run *kvm_run = vcpu->run;
5557 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5558 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5559 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5560 kvm_run->debug.arch.exception = DB_VECTOR;
5561 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5562 *r = EMULATE_USER_EXIT;
5565 * "Certain debug exceptions may clear bit 0-3. The
5566 * remaining contents of the DR6 register are never
5567 * cleared by the processor".
5569 vcpu->arch.dr6 &= ~15;
5570 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5571 kvm_queue_exception(vcpu, DB_VECTOR);
5575 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5577 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5578 int r = EMULATE_DONE;
5580 kvm_x86_ops->skip_emulated_instruction(vcpu);
5583 * rflags is the old, "raw" value of the flags. The new value has
5584 * not been saved yet.
5586 * This is correct even for TF set by the guest, because "the
5587 * processor will not generate this exception after the instruction
5588 * that sets the TF flag".
5590 if (unlikely(rflags & X86_EFLAGS_TF))
5591 kvm_vcpu_do_singlestep(vcpu, &r);
5592 return r == EMULATE_DONE;
5594 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5596 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5598 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5599 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5600 struct kvm_run *kvm_run = vcpu->run;
5601 unsigned long eip = kvm_get_linear_rip(vcpu);
5602 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5603 vcpu->arch.guest_debug_dr7,
5607 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5608 kvm_run->debug.arch.pc = eip;
5609 kvm_run->debug.arch.exception = DB_VECTOR;
5610 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5611 *r = EMULATE_USER_EXIT;
5616 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5617 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5618 unsigned long eip = kvm_get_linear_rip(vcpu);
5619 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5624 vcpu->arch.dr6 &= ~15;
5625 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5626 kvm_queue_exception(vcpu, DB_VECTOR);
5635 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5642 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5643 bool writeback = true;
5644 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5647 * Clear write_fault_to_shadow_pgtable here to ensure it is
5650 vcpu->arch.write_fault_to_shadow_pgtable = false;
5651 kvm_clear_exception_queue(vcpu);
5653 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5654 init_emulate_ctxt(vcpu);
5657 * We will reenter on the same instruction since
5658 * we do not set complete_userspace_io. This does not
5659 * handle watchpoints yet, those would be handled in
5662 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5665 ctxt->interruptibility = 0;
5666 ctxt->have_exception = false;
5667 ctxt->exception.vector = -1;
5668 ctxt->perm_ok = false;
5670 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5672 r = x86_decode_insn(ctxt, insn, insn_len);
5674 trace_kvm_emulate_insn_start(vcpu);
5675 ++vcpu->stat.insn_emulation;
5676 if (r != EMULATION_OK) {
5677 if (emulation_type & EMULTYPE_TRAP_UD)
5678 return EMULATE_FAIL;
5679 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5681 return EMULATE_DONE;
5682 if (emulation_type & EMULTYPE_SKIP)
5683 return EMULATE_FAIL;
5684 return handle_emulation_failure(vcpu);
5688 if (emulation_type & EMULTYPE_SKIP) {
5689 kvm_rip_write(vcpu, ctxt->_eip);
5690 if (ctxt->eflags & X86_EFLAGS_RF)
5691 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5692 return EMULATE_DONE;
5695 if (retry_instruction(ctxt, cr2, emulation_type))
5696 return EMULATE_DONE;
5698 /* this is needed for vmware backdoor interface to work since it
5699 changes registers values during IO operation */
5700 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5701 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5702 emulator_invalidate_register_cache(ctxt);
5706 /* Save the faulting GPA (cr2) in the address field */
5707 ctxt->exception.address = cr2;
5709 r = x86_emulate_insn(ctxt);
5711 if (r == EMULATION_INTERCEPTED)
5712 return EMULATE_DONE;
5714 if (r == EMULATION_FAILED) {
5715 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5717 return EMULATE_DONE;
5719 return handle_emulation_failure(vcpu);
5722 if (ctxt->have_exception) {
5724 if (inject_emulated_exception(vcpu))
5726 } else if (vcpu->arch.pio.count) {
5727 if (!vcpu->arch.pio.in) {
5728 /* FIXME: return into emulator if single-stepping. */
5729 vcpu->arch.pio.count = 0;
5732 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5734 r = EMULATE_USER_EXIT;
5735 } else if (vcpu->mmio_needed) {
5736 if (!vcpu->mmio_is_write)
5738 r = EMULATE_USER_EXIT;
5739 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5740 } else if (r == EMULATION_RESTART)
5746 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5747 toggle_interruptibility(vcpu, ctxt->interruptibility);
5748 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5749 kvm_rip_write(vcpu, ctxt->eip);
5750 if (r == EMULATE_DONE &&
5751 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5752 kvm_vcpu_do_singlestep(vcpu, &r);
5753 if (!ctxt->have_exception ||
5754 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5755 __kvm_set_rflags(vcpu, ctxt->eflags);
5758 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5759 * do nothing, and it will be requested again as soon as
5760 * the shadow expires. But we still need to check here,
5761 * because POPF has no interrupt shadow.
5763 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5764 kvm_make_request(KVM_REQ_EVENT, vcpu);
5766 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5770 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5772 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5774 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5775 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5776 size, port, &val, 1);
5777 /* do not return to emulator after return from userspace */
5778 vcpu->arch.pio.count = 0;
5781 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5783 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5787 /* We should only ever be called with arch.pio.count equal to 1 */
5788 BUG_ON(vcpu->arch.pio.count != 1);
5790 /* For size less than 4 we merge, else we zero extend */
5791 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5795 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5796 * the copy and tracing
5798 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5799 vcpu->arch.pio.port, &val, 1);
5800 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5805 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5810 /* For size less than 4 we merge, else we zero extend */
5811 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5813 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5816 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5820 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5824 EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5826 static int kvmclock_cpu_down_prep(unsigned int cpu)
5828 __this_cpu_write(cpu_tsc_khz, 0);
5832 static void tsc_khz_changed(void *data)
5834 struct cpufreq_freqs *freq = data;
5835 unsigned long khz = 0;
5839 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5840 khz = cpufreq_quick_get(raw_smp_processor_id());
5843 __this_cpu_write(cpu_tsc_khz, khz);
5846 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5849 struct cpufreq_freqs *freq = data;
5851 struct kvm_vcpu *vcpu;
5852 int i, send_ipi = 0;
5855 * We allow guests to temporarily run on slowing clocks,
5856 * provided we notify them after, or to run on accelerating
5857 * clocks, provided we notify them before. Thus time never
5860 * However, we have a problem. We can't atomically update
5861 * the frequency of a given CPU from this function; it is
5862 * merely a notifier, which can be called from any CPU.
5863 * Changing the TSC frequency at arbitrary points in time
5864 * requires a recomputation of local variables related to
5865 * the TSC for each VCPU. We must flag these local variables
5866 * to be updated and be sure the update takes place with the
5867 * new frequency before any guests proceed.
5869 * Unfortunately, the combination of hotplug CPU and frequency
5870 * change creates an intractable locking scenario; the order
5871 * of when these callouts happen is undefined with respect to
5872 * CPU hotplug, and they can race with each other. As such,
5873 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5874 * undefined; you can actually have a CPU frequency change take
5875 * place in between the computation of X and the setting of the
5876 * variable. To protect against this problem, all updates of
5877 * the per_cpu tsc_khz variable are done in an interrupt
5878 * protected IPI, and all callers wishing to update the value
5879 * must wait for a synchronous IPI to complete (which is trivial
5880 * if the caller is on the CPU already). This establishes the
5881 * necessary total order on variable updates.
5883 * Note that because a guest time update may take place
5884 * anytime after the setting of the VCPU's request bit, the
5885 * correct TSC value must be set before the request. However,
5886 * to ensure the update actually makes it to any guest which
5887 * starts running in hardware virtualization between the set
5888 * and the acquisition of the spinlock, we must also ping the
5889 * CPU after setting the request bit.
5893 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5895 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5898 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5900 spin_lock(&kvm_lock);
5901 list_for_each_entry(kvm, &vm_list, vm_list) {
5902 kvm_for_each_vcpu(i, vcpu, kvm) {
5903 if (vcpu->cpu != freq->cpu)
5905 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5906 if (vcpu->cpu != smp_processor_id())
5910 spin_unlock(&kvm_lock);
5912 if (freq->old < freq->new && send_ipi) {
5914 * We upscale the frequency. Must make the guest
5915 * doesn't see old kvmclock values while running with
5916 * the new frequency, otherwise we risk the guest sees
5917 * time go backwards.
5919 * In case we update the frequency for another cpu
5920 * (which might be in guest context) send an interrupt
5921 * to kick the cpu out of guest context. Next time
5922 * guest context is entered kvmclock will be updated,
5923 * so the guest will not see stale values.
5925 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5930 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5931 .notifier_call = kvmclock_cpufreq_notifier
5934 static int kvmclock_cpu_online(unsigned int cpu)
5936 tsc_khz_changed(NULL);
5940 static void kvm_timer_init(void)
5942 max_tsc_khz = tsc_khz;
5944 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5945 #ifdef CONFIG_CPU_FREQ
5946 struct cpufreq_policy policy;
5949 memset(&policy, 0, sizeof(policy));
5951 cpufreq_get_policy(&policy, cpu);
5952 if (policy.cpuinfo.max_freq)
5953 max_tsc_khz = policy.cpuinfo.max_freq;
5956 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5957 CPUFREQ_TRANSITION_NOTIFIER);
5959 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5961 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
5962 kvmclock_cpu_online, kvmclock_cpu_down_prep);
5965 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5967 int kvm_is_in_guest(void)
5969 return __this_cpu_read(current_vcpu) != NULL;
5972 static int kvm_is_user_mode(void)
5976 if (__this_cpu_read(current_vcpu))
5977 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5979 return user_mode != 0;
5982 static unsigned long kvm_get_guest_ip(void)
5984 unsigned long ip = 0;
5986 if (__this_cpu_read(current_vcpu))
5987 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5992 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5993 .is_in_guest = kvm_is_in_guest,
5994 .is_user_mode = kvm_is_user_mode,
5995 .get_guest_ip = kvm_get_guest_ip,
5998 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6000 __this_cpu_write(current_vcpu, vcpu);
6002 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6004 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6006 __this_cpu_write(current_vcpu, NULL);
6008 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6010 static void kvm_set_mmio_spte_mask(void)
6013 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6016 * Set the reserved bits and the present bit of an paging-structure
6017 * entry to generate page fault with PFER.RSV = 1.
6019 /* Mask the reserved physical address bits. */
6020 mask = rsvd_bits(maxphyaddr, 51);
6022 /* Set the present bit. */
6025 #ifdef CONFIG_X86_64
6027 * If reserved bit is not supported, clear the present bit to disable
6030 if (maxphyaddr == 52)
6034 kvm_mmu_set_mmio_spte_mask(mask, mask);
6037 #ifdef CONFIG_X86_64
6038 static void pvclock_gtod_update_fn(struct work_struct *work)
6042 struct kvm_vcpu *vcpu;
6045 spin_lock(&kvm_lock);
6046 list_for_each_entry(kvm, &vm_list, vm_list)
6047 kvm_for_each_vcpu(i, vcpu, kvm)
6048 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6049 atomic_set(&kvm_guest_has_master_clock, 0);
6050 spin_unlock(&kvm_lock);
6053 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6056 * Notification about pvclock gtod data update.
6058 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6061 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6062 struct timekeeper *tk = priv;
6064 update_pvclock_gtod(tk);
6066 /* disable master clock if host does not trust, or does not
6067 * use, TSC clocksource
6069 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6070 atomic_read(&kvm_guest_has_master_clock) != 0)
6071 queue_work(system_long_wq, &pvclock_gtod_work);
6076 static struct notifier_block pvclock_gtod_notifier = {
6077 .notifier_call = pvclock_gtod_notify,
6081 int kvm_arch_init(void *opaque)
6084 struct kvm_x86_ops *ops = opaque;
6087 printk(KERN_ERR "kvm: already loaded the other module\n");
6092 if (!ops->cpu_has_kvm_support()) {
6093 printk(KERN_ERR "kvm: no hardware support\n");
6097 if (ops->disabled_by_bios()) {
6098 printk(KERN_ERR "kvm: disabled by bios\n");
6104 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6106 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6110 r = kvm_mmu_module_init();
6112 goto out_free_percpu;
6114 kvm_set_mmio_spte_mask();
6118 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6119 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6120 PT_PRESENT_MASK, 0);
6123 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6125 if (boot_cpu_has(X86_FEATURE_XSAVE))
6126 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6129 #ifdef CONFIG_X86_64
6130 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6136 free_percpu(shared_msrs);
6141 void kvm_arch_exit(void)
6144 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6146 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6147 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6148 CPUFREQ_TRANSITION_NOTIFIER);
6149 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6150 #ifdef CONFIG_X86_64
6151 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6154 kvm_mmu_module_exit();
6155 free_percpu(shared_msrs);
6158 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6160 ++vcpu->stat.halt_exits;
6161 if (lapic_in_kernel(vcpu)) {
6162 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6165 vcpu->run->exit_reason = KVM_EXIT_HLT;
6169 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6171 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6173 int ret = kvm_skip_emulated_instruction(vcpu);
6175 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6176 * KVM_EXIT_DEBUG here.
6178 return kvm_vcpu_halt(vcpu) && ret;
6180 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6182 #ifdef CONFIG_X86_64
6183 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6184 unsigned long clock_type)
6186 struct kvm_clock_pairing clock_pairing;
6191 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6192 return -KVM_EOPNOTSUPP;
6194 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6195 return -KVM_EOPNOTSUPP;
6197 clock_pairing.sec = ts.tv_sec;
6198 clock_pairing.nsec = ts.tv_nsec;
6199 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6200 clock_pairing.flags = 0;
6203 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6204 sizeof(struct kvm_clock_pairing)))
6212 * kvm_pv_kick_cpu_op: Kick a vcpu.
6214 * @apicid - apicid of vcpu to be kicked.
6216 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6218 struct kvm_lapic_irq lapic_irq;
6220 lapic_irq.shorthand = 0;
6221 lapic_irq.dest_mode = 0;
6222 lapic_irq.level = 0;
6223 lapic_irq.dest_id = apicid;
6224 lapic_irq.msi_redir_hint = false;
6226 lapic_irq.delivery_mode = APIC_DM_REMRD;
6227 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6230 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6232 vcpu->arch.apicv_active = false;
6233 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6236 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6238 unsigned long nr, a0, a1, a2, a3, ret;
6241 r = kvm_skip_emulated_instruction(vcpu);
6243 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6244 return kvm_hv_hypercall(vcpu);
6246 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6247 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6248 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6249 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6250 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6252 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6254 op_64_bit = is_64_bit_mode(vcpu);
6263 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6269 case KVM_HC_VAPIC_POLL_IRQ:
6272 case KVM_HC_KICK_CPU:
6273 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6276 #ifdef CONFIG_X86_64
6277 case KVM_HC_CLOCK_PAIRING:
6278 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6288 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6289 ++vcpu->stat.hypercalls;
6292 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6294 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6296 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6297 char instruction[3];
6298 unsigned long rip = kvm_rip_read(vcpu);
6300 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6302 return emulator_write_emulated(ctxt, rip, instruction, 3,
6306 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6308 return vcpu->run->request_interrupt_window &&
6309 likely(!pic_in_kernel(vcpu->kvm));
6312 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6314 struct kvm_run *kvm_run = vcpu->run;
6316 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6317 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6318 kvm_run->cr8 = kvm_get_cr8(vcpu);
6319 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6320 kvm_run->ready_for_interrupt_injection =
6321 pic_in_kernel(vcpu->kvm) ||
6322 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6325 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6329 if (!kvm_x86_ops->update_cr8_intercept)
6332 if (!lapic_in_kernel(vcpu))
6335 if (vcpu->arch.apicv_active)
6338 if (!vcpu->arch.apic->vapic_addr)
6339 max_irr = kvm_lapic_find_highest_irr(vcpu);
6346 tpr = kvm_lapic_get_cr8(vcpu);
6348 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6351 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6355 /* try to reinject previous events if any */
6356 if (vcpu->arch.exception.pending) {
6357 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6358 vcpu->arch.exception.has_error_code,
6359 vcpu->arch.exception.error_code);
6361 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6362 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6365 if (vcpu->arch.exception.nr == DB_VECTOR &&
6366 (vcpu->arch.dr7 & DR7_GD)) {
6367 vcpu->arch.dr7 &= ~DR7_GD;
6368 kvm_update_dr7(vcpu);
6371 kvm_x86_ops->queue_exception(vcpu);
6375 if (vcpu->arch.nmi_injected) {
6376 kvm_x86_ops->set_nmi(vcpu);
6380 if (vcpu->arch.interrupt.pending) {
6381 kvm_x86_ops->set_irq(vcpu);
6385 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6386 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6391 /* try to inject new event if pending */
6392 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6393 vcpu->arch.smi_pending = false;
6395 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6396 --vcpu->arch.nmi_pending;
6397 vcpu->arch.nmi_injected = true;
6398 kvm_x86_ops->set_nmi(vcpu);
6399 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6401 * Because interrupts can be injected asynchronously, we are
6402 * calling check_nested_events again here to avoid a race condition.
6403 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6404 * proposal and current concerns. Perhaps we should be setting
6405 * KVM_REQ_EVENT only on certain events and not unconditionally?
6407 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6408 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6412 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6413 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6415 kvm_x86_ops->set_irq(vcpu);
6422 static void process_nmi(struct kvm_vcpu *vcpu)
6427 * x86 is limited to one NMI running, and one NMI pending after it.
6428 * If an NMI is already in progress, limit further NMIs to just one.
6429 * Otherwise, allow two (and we'll inject the first one immediately).
6431 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6434 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6435 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6436 kvm_make_request(KVM_REQ_EVENT, vcpu);
6439 #define put_smstate(type, buf, offset, val) \
6440 *(type *)((buf) + (offset) - 0x7e00) = val
6442 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6445 flags |= seg->g << 23;
6446 flags |= seg->db << 22;
6447 flags |= seg->l << 21;
6448 flags |= seg->avl << 20;
6449 flags |= seg->present << 15;
6450 flags |= seg->dpl << 13;
6451 flags |= seg->s << 12;
6452 flags |= seg->type << 8;
6456 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6458 struct kvm_segment seg;
6461 kvm_get_segment(vcpu, &seg, n);
6462 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6465 offset = 0x7f84 + n * 12;
6467 offset = 0x7f2c + (n - 3) * 12;
6469 put_smstate(u32, buf, offset + 8, seg.base);
6470 put_smstate(u32, buf, offset + 4, seg.limit);
6471 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6474 #ifdef CONFIG_X86_64
6475 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6477 struct kvm_segment seg;
6481 kvm_get_segment(vcpu, &seg, n);
6482 offset = 0x7e00 + n * 16;
6484 flags = enter_smm_get_segment_flags(&seg) >> 8;
6485 put_smstate(u16, buf, offset, seg.selector);
6486 put_smstate(u16, buf, offset + 2, flags);
6487 put_smstate(u32, buf, offset + 4, seg.limit);
6488 put_smstate(u64, buf, offset + 8, seg.base);
6492 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6495 struct kvm_segment seg;
6499 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6500 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6501 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6502 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6504 for (i = 0; i < 8; i++)
6505 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6507 kvm_get_dr(vcpu, 6, &val);
6508 put_smstate(u32, buf, 0x7fcc, (u32)val);
6509 kvm_get_dr(vcpu, 7, &val);
6510 put_smstate(u32, buf, 0x7fc8, (u32)val);
6512 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6513 put_smstate(u32, buf, 0x7fc4, seg.selector);
6514 put_smstate(u32, buf, 0x7f64, seg.base);
6515 put_smstate(u32, buf, 0x7f60, seg.limit);
6516 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6518 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6519 put_smstate(u32, buf, 0x7fc0, seg.selector);
6520 put_smstate(u32, buf, 0x7f80, seg.base);
6521 put_smstate(u32, buf, 0x7f7c, seg.limit);
6522 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6524 kvm_x86_ops->get_gdt(vcpu, &dt);
6525 put_smstate(u32, buf, 0x7f74, dt.address);
6526 put_smstate(u32, buf, 0x7f70, dt.size);
6528 kvm_x86_ops->get_idt(vcpu, &dt);
6529 put_smstate(u32, buf, 0x7f58, dt.address);
6530 put_smstate(u32, buf, 0x7f54, dt.size);
6532 for (i = 0; i < 6; i++)
6533 enter_smm_save_seg_32(vcpu, buf, i);
6535 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6538 put_smstate(u32, buf, 0x7efc, 0x00020000);
6539 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6542 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6544 #ifdef CONFIG_X86_64
6546 struct kvm_segment seg;
6550 for (i = 0; i < 16; i++)
6551 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6553 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6554 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6556 kvm_get_dr(vcpu, 6, &val);
6557 put_smstate(u64, buf, 0x7f68, val);
6558 kvm_get_dr(vcpu, 7, &val);
6559 put_smstate(u64, buf, 0x7f60, val);
6561 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6562 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6563 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6565 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6568 put_smstate(u32, buf, 0x7efc, 0x00020064);
6570 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6572 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6573 put_smstate(u16, buf, 0x7e90, seg.selector);
6574 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6575 put_smstate(u32, buf, 0x7e94, seg.limit);
6576 put_smstate(u64, buf, 0x7e98, seg.base);
6578 kvm_x86_ops->get_idt(vcpu, &dt);
6579 put_smstate(u32, buf, 0x7e84, dt.size);
6580 put_smstate(u64, buf, 0x7e88, dt.address);
6582 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6583 put_smstate(u16, buf, 0x7e70, seg.selector);
6584 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6585 put_smstate(u32, buf, 0x7e74, seg.limit);
6586 put_smstate(u64, buf, 0x7e78, seg.base);
6588 kvm_x86_ops->get_gdt(vcpu, &dt);
6589 put_smstate(u32, buf, 0x7e64, dt.size);
6590 put_smstate(u64, buf, 0x7e68, dt.address);
6592 for (i = 0; i < 6; i++)
6593 enter_smm_save_seg_64(vcpu, buf, i);
6599 static void enter_smm(struct kvm_vcpu *vcpu)
6601 struct kvm_segment cs, ds;
6606 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6607 vcpu->arch.hflags |= HF_SMM_MASK;
6608 memset(buf, 0, 512);
6609 if (guest_cpuid_has_longmode(vcpu))
6610 enter_smm_save_state_64(vcpu, buf);
6612 enter_smm_save_state_32(vcpu, buf);
6614 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6616 if (kvm_x86_ops->get_nmi_mask(vcpu))
6617 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6619 kvm_x86_ops->set_nmi_mask(vcpu, true);
6621 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6622 kvm_rip_write(vcpu, 0x8000);
6624 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6625 kvm_x86_ops->set_cr0(vcpu, cr0);
6626 vcpu->arch.cr0 = cr0;
6628 kvm_x86_ops->set_cr4(vcpu, 0);
6630 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6631 dt.address = dt.size = 0;
6632 kvm_x86_ops->set_idt(vcpu, &dt);
6634 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6636 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6637 cs.base = vcpu->arch.smbase;
6642 cs.limit = ds.limit = 0xffffffff;
6643 cs.type = ds.type = 0x3;
6644 cs.dpl = ds.dpl = 0;
6649 cs.avl = ds.avl = 0;
6650 cs.present = ds.present = 1;
6651 cs.unusable = ds.unusable = 0;
6652 cs.padding = ds.padding = 0;
6654 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6655 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6656 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6657 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6658 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6659 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6661 if (guest_cpuid_has_longmode(vcpu))
6662 kvm_x86_ops->set_efer(vcpu, 0);
6664 kvm_update_cpuid(vcpu);
6665 kvm_mmu_reset_context(vcpu);
6668 static void process_smi(struct kvm_vcpu *vcpu)
6670 vcpu->arch.smi_pending = true;
6671 kvm_make_request(KVM_REQ_EVENT, vcpu);
6674 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6676 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6679 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6681 u64 eoi_exit_bitmap[4];
6683 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6686 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6688 if (irqchip_split(vcpu->kvm))
6689 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6691 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6692 kvm_x86_ops->sync_pir_to_irr(vcpu);
6693 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6695 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6696 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6697 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6700 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6702 ++vcpu->stat.tlb_flush;
6703 kvm_x86_ops->tlb_flush(vcpu);
6706 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6708 struct page *page = NULL;
6710 if (!lapic_in_kernel(vcpu))
6713 if (!kvm_x86_ops->set_apic_access_page_addr)
6716 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6717 if (is_error_page(page))
6719 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6722 * Do not pin apic access page in memory, the MMU notifier
6723 * will call us again if it is migrated or swapped out.
6727 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6729 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6730 unsigned long address)
6733 * The physical address of apic access page is stored in the VMCS.
6734 * Update it when it becomes invalid.
6736 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6737 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6741 * Returns 1 to let vcpu_run() continue the guest execution loop without
6742 * exiting to the userspace. Otherwise, the value will be returned to the
6745 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6749 dm_request_for_irq_injection(vcpu) &&
6750 kvm_cpu_accept_dm_intr(vcpu);
6752 bool req_immediate_exit = false;
6754 if (kvm_request_pending(vcpu)) {
6755 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6756 kvm_mmu_unload(vcpu);
6757 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6758 __kvm_migrate_timers(vcpu);
6759 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6760 kvm_gen_update_masterclock(vcpu->kvm);
6761 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6762 kvm_gen_kvmclock_update(vcpu);
6763 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6764 r = kvm_guest_time_update(vcpu);
6768 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6769 kvm_mmu_sync_roots(vcpu);
6770 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6771 kvm_vcpu_flush_tlb(vcpu);
6772 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6773 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6777 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6778 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6782 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6783 /* Page is swapped out. Do synthetic halt */
6784 vcpu->arch.apf.halted = true;
6788 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6789 record_steal_time(vcpu);
6790 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6792 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6794 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6795 kvm_pmu_handle_event(vcpu);
6796 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6797 kvm_pmu_deliver_pmi(vcpu);
6798 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6799 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6800 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6801 vcpu->arch.ioapic_handled_vectors)) {
6802 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6803 vcpu->run->eoi.vector =
6804 vcpu->arch.pending_ioapic_eoi;
6809 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6810 vcpu_scan_ioapic(vcpu);
6811 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6812 kvm_vcpu_reload_apic_access_page(vcpu);
6813 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6814 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6815 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6819 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6820 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6821 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6825 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6826 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6827 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6833 * KVM_REQ_HV_STIMER has to be processed after
6834 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6835 * depend on the guest clock being up-to-date
6837 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6838 kvm_hv_process_stimers(vcpu);
6841 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6842 ++vcpu->stat.req_event;
6843 kvm_apic_accept_events(vcpu);
6844 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6849 if (inject_pending_event(vcpu, req_int_win) != 0)
6850 req_immediate_exit = true;
6852 /* Enable NMI/IRQ window open exits if needed.
6854 * SMIs have two cases: 1) they can be nested, and
6855 * then there is nothing to do here because RSM will
6856 * cause a vmexit anyway; 2) or the SMI can be pending
6857 * because inject_pending_event has completed the
6858 * injection of an IRQ or NMI from the previous vmexit,
6859 * and then we request an immediate exit to inject the SMI.
6861 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6862 req_immediate_exit = true;
6863 if (vcpu->arch.nmi_pending)
6864 kvm_x86_ops->enable_nmi_window(vcpu);
6865 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6866 kvm_x86_ops->enable_irq_window(vcpu);
6869 if (kvm_lapic_enabled(vcpu)) {
6870 update_cr8_intercept(vcpu);
6871 kvm_lapic_sync_to_vapic(vcpu);
6875 r = kvm_mmu_reload(vcpu);
6877 goto cancel_injection;
6882 kvm_x86_ops->prepare_guest_switch(vcpu);
6883 kvm_load_guest_fpu(vcpu);
6886 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6887 * IPI are then delayed after guest entry, which ensures that they
6888 * result in virtual interrupt delivery.
6890 local_irq_disable();
6891 vcpu->mode = IN_GUEST_MODE;
6893 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6896 * 1) We should set ->mode before checking ->requests. Please see
6897 * the comment in kvm_vcpu_exiting_guest_mode().
6899 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6900 * pairs with the memory barrier implicit in pi_test_and_set_on
6901 * (see vmx_deliver_posted_interrupt).
6903 * 3) This also orders the write to mode from any reads to the page
6904 * tables done while the VCPU is running. Please see the comment
6905 * in kvm_flush_remote_tlbs.
6907 smp_mb__after_srcu_read_unlock();
6910 * This handles the case where a posted interrupt was
6911 * notified with kvm_vcpu_kick.
6913 if (kvm_lapic_enabled(vcpu)) {
6914 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6915 kvm_x86_ops->sync_pir_to_irr(vcpu);
6918 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
6919 || need_resched() || signal_pending(current)) {
6920 vcpu->mode = OUTSIDE_GUEST_MODE;
6924 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6926 goto cancel_injection;
6929 kvm_load_guest_xcr0(vcpu);
6931 if (req_immediate_exit) {
6932 kvm_make_request(KVM_REQ_EVENT, vcpu);
6933 smp_send_reschedule(vcpu->cpu);
6936 trace_kvm_entry(vcpu->vcpu_id);
6937 wait_lapic_expire(vcpu);
6938 guest_enter_irqoff();
6940 if (unlikely(vcpu->arch.switch_db_regs)) {
6942 set_debugreg(vcpu->arch.eff_db[0], 0);
6943 set_debugreg(vcpu->arch.eff_db[1], 1);
6944 set_debugreg(vcpu->arch.eff_db[2], 2);
6945 set_debugreg(vcpu->arch.eff_db[3], 3);
6946 set_debugreg(vcpu->arch.dr6, 6);
6947 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6950 kvm_x86_ops->run(vcpu);
6953 * Do this here before restoring debug registers on the host. And
6954 * since we do this before handling the vmexit, a DR access vmexit
6955 * can (a) read the correct value of the debug registers, (b) set
6956 * KVM_DEBUGREG_WONT_EXIT again.
6958 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6959 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6960 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6961 kvm_update_dr0123(vcpu);
6962 kvm_update_dr6(vcpu);
6963 kvm_update_dr7(vcpu);
6964 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6968 * If the guest has used debug registers, at least dr7
6969 * will be disabled while returning to the host.
6970 * If we don't have active breakpoints in the host, we don't
6971 * care about the messed up debug address registers. But if
6972 * we have some of them active, restore the old state.
6974 if (hw_breakpoint_active())
6975 hw_breakpoint_restore();
6977 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6979 vcpu->mode = OUTSIDE_GUEST_MODE;
6982 kvm_put_guest_xcr0(vcpu);
6984 kvm_x86_ops->handle_external_intr(vcpu);
6988 guest_exit_irqoff();
6993 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6996 * Profile KVM exit RIPs:
6998 if (unlikely(prof_on == KVM_PROFILING)) {
6999 unsigned long rip = kvm_rip_read(vcpu);
7000 profile_hit(KVM_PROFILING, (void *)rip);
7003 if (unlikely(vcpu->arch.tsc_always_catchup))
7004 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7006 if (vcpu->arch.apic_attention)
7007 kvm_lapic_sync_from_vapic(vcpu);
7009 r = kvm_x86_ops->handle_exit(vcpu);
7013 kvm_x86_ops->cancel_injection(vcpu);
7014 if (unlikely(vcpu->arch.apic_attention))
7015 kvm_lapic_sync_from_vapic(vcpu);
7020 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7022 if (!kvm_arch_vcpu_runnable(vcpu) &&
7023 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7024 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7025 kvm_vcpu_block(vcpu);
7026 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7028 if (kvm_x86_ops->post_block)
7029 kvm_x86_ops->post_block(vcpu);
7031 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7035 kvm_apic_accept_events(vcpu);
7036 switch(vcpu->arch.mp_state) {
7037 case KVM_MP_STATE_HALTED:
7038 vcpu->arch.pv.pv_unhalted = false;
7039 vcpu->arch.mp_state =
7040 KVM_MP_STATE_RUNNABLE;
7041 case KVM_MP_STATE_RUNNABLE:
7042 vcpu->arch.apf.halted = false;
7044 case KVM_MP_STATE_INIT_RECEIVED:
7053 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7055 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7056 kvm_x86_ops->check_nested_events(vcpu, false);
7058 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7059 !vcpu->arch.apf.halted);
7062 static int vcpu_run(struct kvm_vcpu *vcpu)
7065 struct kvm *kvm = vcpu->kvm;
7067 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7070 if (kvm_vcpu_running(vcpu)) {
7071 r = vcpu_enter_guest(vcpu);
7073 r = vcpu_block(kvm, vcpu);
7079 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
7080 if (kvm_cpu_has_pending_timer(vcpu))
7081 kvm_inject_pending_timer_irqs(vcpu);
7083 if (dm_request_for_irq_injection(vcpu) &&
7084 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7086 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7087 ++vcpu->stat.request_irq_exits;
7091 kvm_check_async_pf_completion(vcpu);
7093 if (signal_pending(current)) {
7095 vcpu->run->exit_reason = KVM_EXIT_INTR;
7096 ++vcpu->stat.signal_exits;
7099 if (need_resched()) {
7100 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7102 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7106 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7111 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7114 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7115 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7116 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7117 if (r != EMULATE_DONE)
7122 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7124 BUG_ON(!vcpu->arch.pio.count);
7126 return complete_emulated_io(vcpu);
7130 * Implements the following, as a state machine:
7134 * for each mmio piece in the fragment
7142 * for each mmio piece in the fragment
7147 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7149 struct kvm_run *run = vcpu->run;
7150 struct kvm_mmio_fragment *frag;
7153 BUG_ON(!vcpu->mmio_needed);
7155 /* Complete previous fragment */
7156 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7157 len = min(8u, frag->len);
7158 if (!vcpu->mmio_is_write)
7159 memcpy(frag->data, run->mmio.data, len);
7161 if (frag->len <= 8) {
7162 /* Switch to the next fragment. */
7164 vcpu->mmio_cur_fragment++;
7166 /* Go forward to the next mmio piece. */
7172 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7173 vcpu->mmio_needed = 0;
7175 /* FIXME: return into emulator if single-stepping. */
7176 if (vcpu->mmio_is_write)
7178 vcpu->mmio_read_completed = 1;
7179 return complete_emulated_io(vcpu);
7182 run->exit_reason = KVM_EXIT_MMIO;
7183 run->mmio.phys_addr = frag->gpa;
7184 if (vcpu->mmio_is_write)
7185 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7186 run->mmio.len = min(8u, frag->len);
7187 run->mmio.is_write = vcpu->mmio_is_write;
7188 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7193 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7195 struct fpu *fpu = ¤t->thread.fpu;
7199 fpu__activate_curr(fpu);
7201 if (vcpu->sigset_active)
7202 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7204 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7205 kvm_vcpu_block(vcpu);
7206 kvm_apic_accept_events(vcpu);
7207 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
7212 /* re-sync apic's tpr */
7213 if (!lapic_in_kernel(vcpu)) {
7214 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7220 if (unlikely(vcpu->arch.complete_userspace_io)) {
7221 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7222 vcpu->arch.complete_userspace_io = NULL;
7227 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7229 if (kvm_run->immediate_exit)
7235 post_kvm_run_save(vcpu);
7236 if (vcpu->sigset_active)
7237 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7242 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7244 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7246 * We are here if userspace calls get_regs() in the middle of
7247 * instruction emulation. Registers state needs to be copied
7248 * back from emulation context to vcpu. Userspace shouldn't do
7249 * that usually, but some bad designed PV devices (vmware
7250 * backdoor interface) need this to work
7252 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7253 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7255 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7256 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7257 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7258 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7259 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7260 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7261 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7262 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7263 #ifdef CONFIG_X86_64
7264 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7265 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7266 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7267 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7268 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7269 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7270 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7271 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7274 regs->rip = kvm_rip_read(vcpu);
7275 regs->rflags = kvm_get_rflags(vcpu);
7280 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7282 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7283 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7285 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7286 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7287 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7288 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7289 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7290 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7291 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7292 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7293 #ifdef CONFIG_X86_64
7294 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7295 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7296 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7297 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7298 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7299 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7300 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7301 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7304 kvm_rip_write(vcpu, regs->rip);
7305 kvm_set_rflags(vcpu, regs->rflags);
7307 vcpu->arch.exception.pending = false;
7309 kvm_make_request(KVM_REQ_EVENT, vcpu);
7314 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7316 struct kvm_segment cs;
7318 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7322 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7324 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7325 struct kvm_sregs *sregs)
7329 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7330 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7331 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7332 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7333 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7334 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7336 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7337 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7339 kvm_x86_ops->get_idt(vcpu, &dt);
7340 sregs->idt.limit = dt.size;
7341 sregs->idt.base = dt.address;
7342 kvm_x86_ops->get_gdt(vcpu, &dt);
7343 sregs->gdt.limit = dt.size;
7344 sregs->gdt.base = dt.address;
7346 sregs->cr0 = kvm_read_cr0(vcpu);
7347 sregs->cr2 = vcpu->arch.cr2;
7348 sregs->cr3 = kvm_read_cr3(vcpu);
7349 sregs->cr4 = kvm_read_cr4(vcpu);
7350 sregs->cr8 = kvm_get_cr8(vcpu);
7351 sregs->efer = vcpu->arch.efer;
7352 sregs->apic_base = kvm_get_apic_base(vcpu);
7354 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7356 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7357 set_bit(vcpu->arch.interrupt.nr,
7358 (unsigned long *)sregs->interrupt_bitmap);
7363 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7364 struct kvm_mp_state *mp_state)
7366 kvm_apic_accept_events(vcpu);
7367 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7368 vcpu->arch.pv.pv_unhalted)
7369 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7371 mp_state->mp_state = vcpu->arch.mp_state;
7376 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7377 struct kvm_mp_state *mp_state)
7379 if (!lapic_in_kernel(vcpu) &&
7380 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7383 /* INITs are latched while in SMM */
7384 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7385 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7386 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7389 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7390 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7391 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7393 vcpu->arch.mp_state = mp_state->mp_state;
7394 kvm_make_request(KVM_REQ_EVENT, vcpu);
7398 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7399 int reason, bool has_error_code, u32 error_code)
7401 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7404 init_emulate_ctxt(vcpu);
7406 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7407 has_error_code, error_code);
7410 return EMULATE_FAIL;
7412 kvm_rip_write(vcpu, ctxt->eip);
7413 kvm_set_rflags(vcpu, ctxt->eflags);
7414 kvm_make_request(KVM_REQ_EVENT, vcpu);
7415 return EMULATE_DONE;
7417 EXPORT_SYMBOL_GPL(kvm_task_switch);
7419 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7420 struct kvm_sregs *sregs)
7422 struct msr_data apic_base_msr;
7423 int mmu_reset_needed = 0;
7424 int pending_vec, max_bits, idx;
7427 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7430 dt.size = sregs->idt.limit;
7431 dt.address = sregs->idt.base;
7432 kvm_x86_ops->set_idt(vcpu, &dt);
7433 dt.size = sregs->gdt.limit;
7434 dt.address = sregs->gdt.base;
7435 kvm_x86_ops->set_gdt(vcpu, &dt);
7437 vcpu->arch.cr2 = sregs->cr2;
7438 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7439 vcpu->arch.cr3 = sregs->cr3;
7440 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7442 kvm_set_cr8(vcpu, sregs->cr8);
7444 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7445 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7446 apic_base_msr.data = sregs->apic_base;
7447 apic_base_msr.host_initiated = true;
7448 kvm_set_apic_base(vcpu, &apic_base_msr);
7450 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7451 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7452 vcpu->arch.cr0 = sregs->cr0;
7454 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7455 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7456 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7457 kvm_update_cpuid(vcpu);
7459 idx = srcu_read_lock(&vcpu->kvm->srcu);
7460 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7461 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7462 mmu_reset_needed = 1;
7464 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7466 if (mmu_reset_needed)
7467 kvm_mmu_reset_context(vcpu);
7469 max_bits = KVM_NR_INTERRUPTS;
7470 pending_vec = find_first_bit(
7471 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7472 if (pending_vec < max_bits) {
7473 kvm_queue_interrupt(vcpu, pending_vec, false);
7474 pr_debug("Set back pending irq %d\n", pending_vec);
7477 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7478 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7479 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7480 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7481 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7482 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7484 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7485 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7487 update_cr8_intercept(vcpu);
7489 /* Older userspace won't unhalt the vcpu on reset. */
7490 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7491 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7493 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7495 kvm_make_request(KVM_REQ_EVENT, vcpu);
7500 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7501 struct kvm_guest_debug *dbg)
7503 unsigned long rflags;
7506 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7508 if (vcpu->arch.exception.pending)
7510 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7511 kvm_queue_exception(vcpu, DB_VECTOR);
7513 kvm_queue_exception(vcpu, BP_VECTOR);
7517 * Read rflags as long as potentially injected trace flags are still
7520 rflags = kvm_get_rflags(vcpu);
7522 vcpu->guest_debug = dbg->control;
7523 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7524 vcpu->guest_debug = 0;
7526 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7527 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7528 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7529 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7531 for (i = 0; i < KVM_NR_DB_REGS; i++)
7532 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7534 kvm_update_dr7(vcpu);
7536 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7537 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7538 get_segment_base(vcpu, VCPU_SREG_CS);
7541 * Trigger an rflags update that will inject or remove the trace
7544 kvm_set_rflags(vcpu, rflags);
7546 kvm_x86_ops->update_bp_intercept(vcpu);
7556 * Translate a guest virtual address to a guest physical address.
7558 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7559 struct kvm_translation *tr)
7561 unsigned long vaddr = tr->linear_address;
7565 idx = srcu_read_lock(&vcpu->kvm->srcu);
7566 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7567 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7568 tr->physical_address = gpa;
7569 tr->valid = gpa != UNMAPPED_GVA;
7576 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7578 struct fxregs_state *fxsave =
7579 &vcpu->arch.guest_fpu.state.fxsave;
7581 memcpy(fpu->fpr, fxsave->st_space, 128);
7582 fpu->fcw = fxsave->cwd;
7583 fpu->fsw = fxsave->swd;
7584 fpu->ftwx = fxsave->twd;
7585 fpu->last_opcode = fxsave->fop;
7586 fpu->last_ip = fxsave->rip;
7587 fpu->last_dp = fxsave->rdp;
7588 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7593 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7595 struct fxregs_state *fxsave =
7596 &vcpu->arch.guest_fpu.state.fxsave;
7598 memcpy(fxsave->st_space, fpu->fpr, 128);
7599 fxsave->cwd = fpu->fcw;
7600 fxsave->swd = fpu->fsw;
7601 fxsave->twd = fpu->ftwx;
7602 fxsave->fop = fpu->last_opcode;
7603 fxsave->rip = fpu->last_ip;
7604 fxsave->rdp = fpu->last_dp;
7605 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7610 static void fx_init(struct kvm_vcpu *vcpu)
7612 fpstate_init(&vcpu->arch.guest_fpu.state);
7613 if (boot_cpu_has(X86_FEATURE_XSAVES))
7614 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7615 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7618 * Ensure guest xcr0 is valid for loading
7620 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7622 vcpu->arch.cr0 |= X86_CR0_ET;
7625 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7627 if (vcpu->guest_fpu_loaded)
7631 * Restore all possible states in the guest,
7632 * and assume host would use all available bits.
7633 * Guest xcr0 would be loaded later.
7635 vcpu->guest_fpu_loaded = 1;
7636 __kernel_fpu_begin();
7637 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7641 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7643 if (!vcpu->guest_fpu_loaded)
7646 vcpu->guest_fpu_loaded = 0;
7647 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7649 ++vcpu->stat.fpu_reload;
7653 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7655 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7657 kvmclock_reset(vcpu);
7659 kvm_x86_ops->vcpu_free(vcpu);
7660 free_cpumask_var(wbinvd_dirty_mask);
7663 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7666 struct kvm_vcpu *vcpu;
7668 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7669 printk_once(KERN_WARNING
7670 "kvm: SMP vm created on host with unstable TSC; "
7671 "guest TSC will not be reliable\n");
7673 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7678 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7682 kvm_vcpu_mtrr_init(vcpu);
7683 r = vcpu_load(vcpu);
7686 kvm_vcpu_reset(vcpu, false);
7687 kvm_mmu_setup(vcpu);
7692 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7694 struct msr_data msr;
7695 struct kvm *kvm = vcpu->kvm;
7697 kvm_hv_vcpu_postcreate(vcpu);
7699 if (vcpu_load(vcpu))
7702 msr.index = MSR_IA32_TSC;
7703 msr.host_initiated = true;
7704 kvm_write_tsc(vcpu, &msr);
7707 if (!kvmclock_periodic_sync)
7710 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7711 KVMCLOCK_SYNC_PERIOD);
7714 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7717 vcpu->arch.apf.msr_val = 0;
7719 r = vcpu_load(vcpu);
7721 kvm_mmu_unload(vcpu);
7724 kvm_x86_ops->vcpu_free(vcpu);
7727 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7729 vcpu->arch.hflags = 0;
7731 vcpu->arch.smi_pending = 0;
7732 atomic_set(&vcpu->arch.nmi_queued, 0);
7733 vcpu->arch.nmi_pending = 0;
7734 vcpu->arch.nmi_injected = false;
7735 kvm_clear_interrupt_queue(vcpu);
7736 kvm_clear_exception_queue(vcpu);
7738 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7739 kvm_update_dr0123(vcpu);
7740 vcpu->arch.dr6 = DR6_INIT;
7741 kvm_update_dr6(vcpu);
7742 vcpu->arch.dr7 = DR7_FIXED_1;
7743 kvm_update_dr7(vcpu);
7747 kvm_make_request(KVM_REQ_EVENT, vcpu);
7748 vcpu->arch.apf.msr_val = 0;
7749 vcpu->arch.st.msr_val = 0;
7751 kvmclock_reset(vcpu);
7753 kvm_clear_async_pf_completion_queue(vcpu);
7754 kvm_async_pf_hash_reset(vcpu);
7755 vcpu->arch.apf.halted = false;
7758 kvm_pmu_reset(vcpu);
7759 vcpu->arch.smbase = 0x30000;
7761 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7762 vcpu->arch.msr_misc_features_enables = 0;
7765 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7766 vcpu->arch.regs_avail = ~0;
7767 vcpu->arch.regs_dirty = ~0;
7769 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7772 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7774 struct kvm_segment cs;
7776 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7777 cs.selector = vector << 8;
7778 cs.base = vector << 12;
7779 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7780 kvm_rip_write(vcpu, 0);
7783 int kvm_arch_hardware_enable(void)
7786 struct kvm_vcpu *vcpu;
7791 bool stable, backwards_tsc = false;
7793 kvm_shared_msr_cpu_online();
7794 ret = kvm_x86_ops->hardware_enable();
7798 local_tsc = rdtsc();
7799 stable = !check_tsc_unstable();
7800 list_for_each_entry(kvm, &vm_list, vm_list) {
7801 kvm_for_each_vcpu(i, vcpu, kvm) {
7802 if (!stable && vcpu->cpu == smp_processor_id())
7803 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7804 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7805 backwards_tsc = true;
7806 if (vcpu->arch.last_host_tsc > max_tsc)
7807 max_tsc = vcpu->arch.last_host_tsc;
7813 * Sometimes, even reliable TSCs go backwards. This happens on
7814 * platforms that reset TSC during suspend or hibernate actions, but
7815 * maintain synchronization. We must compensate. Fortunately, we can
7816 * detect that condition here, which happens early in CPU bringup,
7817 * before any KVM threads can be running. Unfortunately, we can't
7818 * bring the TSCs fully up to date with real time, as we aren't yet far
7819 * enough into CPU bringup that we know how much real time has actually
7820 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
7821 * variables that haven't been updated yet.
7823 * So we simply find the maximum observed TSC above, then record the
7824 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7825 * the adjustment will be applied. Note that we accumulate
7826 * adjustments, in case multiple suspend cycles happen before some VCPU
7827 * gets a chance to run again. In the event that no KVM threads get a
7828 * chance to run, we will miss the entire elapsed period, as we'll have
7829 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7830 * loose cycle time. This isn't too big a deal, since the loss will be
7831 * uniform across all VCPUs (not to mention the scenario is extremely
7832 * unlikely). It is possible that a second hibernate recovery happens
7833 * much faster than a first, causing the observed TSC here to be
7834 * smaller; this would require additional padding adjustment, which is
7835 * why we set last_host_tsc to the local tsc observed here.
7837 * N.B. - this code below runs only on platforms with reliable TSC,
7838 * as that is the only way backwards_tsc is set above. Also note
7839 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7840 * have the same delta_cyc adjustment applied if backwards_tsc
7841 * is detected. Note further, this adjustment is only done once,
7842 * as we reset last_host_tsc on all VCPUs to stop this from being
7843 * called multiple times (one for each physical CPU bringup).
7845 * Platforms with unreliable TSCs don't have to deal with this, they
7846 * will be compensated by the logic in vcpu_load, which sets the TSC to
7847 * catchup mode. This will catchup all VCPUs to real time, but cannot
7848 * guarantee that they stay in perfect synchronization.
7850 if (backwards_tsc) {
7851 u64 delta_cyc = max_tsc - local_tsc;
7852 list_for_each_entry(kvm, &vm_list, vm_list) {
7853 kvm->arch.backwards_tsc_observed = true;
7854 kvm_for_each_vcpu(i, vcpu, kvm) {
7855 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7856 vcpu->arch.last_host_tsc = local_tsc;
7857 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7861 * We have to disable TSC offset matching.. if you were
7862 * booting a VM while issuing an S4 host suspend....
7863 * you may have some problem. Solving this issue is
7864 * left as an exercise to the reader.
7866 kvm->arch.last_tsc_nsec = 0;
7867 kvm->arch.last_tsc_write = 0;
7874 void kvm_arch_hardware_disable(void)
7876 kvm_x86_ops->hardware_disable();
7877 drop_user_return_notifiers();
7880 int kvm_arch_hardware_setup(void)
7884 r = kvm_x86_ops->hardware_setup();
7888 if (kvm_has_tsc_control) {
7890 * Make sure the user can only configure tsc_khz values that
7891 * fit into a signed integer.
7892 * A min value is not calculated needed because it will always
7893 * be 1 on all machines.
7895 u64 max = min(0x7fffffffULL,
7896 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7897 kvm_max_guest_tsc_khz = max;
7899 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7902 kvm_init_msr_list();
7906 void kvm_arch_hardware_unsetup(void)
7908 kvm_x86_ops->hardware_unsetup();
7911 void kvm_arch_check_processor_compat(void *rtn)
7913 kvm_x86_ops->check_processor_compatibility(rtn);
7916 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7918 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7920 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7922 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7924 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7927 struct static_key kvm_no_apic_vcpu __read_mostly;
7928 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7930 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7936 BUG_ON(vcpu->kvm == NULL);
7939 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7940 vcpu->arch.pv.pv_unhalted = false;
7941 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7942 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7943 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7945 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7947 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7952 vcpu->arch.pio_data = page_address(page);
7954 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7956 r = kvm_mmu_create(vcpu);
7958 goto fail_free_pio_data;
7960 if (irqchip_in_kernel(kvm)) {
7961 r = kvm_create_lapic(vcpu);
7963 goto fail_mmu_destroy;
7965 static_key_slow_inc(&kvm_no_apic_vcpu);
7967 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7969 if (!vcpu->arch.mce_banks) {
7971 goto fail_free_lapic;
7973 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7975 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7977 goto fail_free_mce_banks;
7982 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7983 vcpu->arch.pv_time_enabled = false;
7985 vcpu->arch.guest_supported_xcr0 = 0;
7986 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7988 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7990 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7992 kvm_async_pf_hash_reset(vcpu);
7995 vcpu->arch.pending_external_vector = -1;
7997 kvm_hv_vcpu_init(vcpu);
8001 fail_free_mce_banks:
8002 kfree(vcpu->arch.mce_banks);
8004 kvm_free_lapic(vcpu);
8006 kvm_mmu_destroy(vcpu);
8008 free_page((unsigned long)vcpu->arch.pio_data);
8013 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8017 kvm_hv_vcpu_uninit(vcpu);
8018 kvm_pmu_destroy(vcpu);
8019 kfree(vcpu->arch.mce_banks);
8020 kvm_free_lapic(vcpu);
8021 idx = srcu_read_lock(&vcpu->kvm->srcu);
8022 kvm_mmu_destroy(vcpu);
8023 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8024 free_page((unsigned long)vcpu->arch.pio_data);
8025 if (!lapic_in_kernel(vcpu))
8026 static_key_slow_dec(&kvm_no_apic_vcpu);
8029 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8031 kvm_x86_ops->sched_in(vcpu, cpu);
8034 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
8039 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
8040 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
8041 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
8042 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
8043 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
8045 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8046 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
8047 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8048 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8049 &kvm->arch.irq_sources_bitmap);
8051 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
8052 mutex_init(&kvm->arch.apic_map_lock);
8053 mutex_init(&kvm->arch.hyperv.hv_lock);
8054 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8056 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
8057 pvclock_update_vm_gtod_copy(kvm);
8059 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
8060 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
8062 kvm_page_track_init(kvm);
8063 kvm_mmu_init_vm(kvm);
8065 if (kvm_x86_ops->vm_init)
8066 return kvm_x86_ops->vm_init(kvm);
8071 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8074 r = vcpu_load(vcpu);
8076 kvm_mmu_unload(vcpu);
8080 static void kvm_free_vcpus(struct kvm *kvm)
8083 struct kvm_vcpu *vcpu;
8086 * Unpin any mmu pages first.
8088 kvm_for_each_vcpu(i, vcpu, kvm) {
8089 kvm_clear_async_pf_completion_queue(vcpu);
8090 kvm_unload_vcpu_mmu(vcpu);
8092 kvm_for_each_vcpu(i, vcpu, kvm)
8093 kvm_arch_vcpu_free(vcpu);
8095 mutex_lock(&kvm->lock);
8096 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8097 kvm->vcpus[i] = NULL;
8099 atomic_set(&kvm->online_vcpus, 0);
8100 mutex_unlock(&kvm->lock);
8103 void kvm_arch_sync_events(struct kvm *kvm)
8105 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
8106 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
8110 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8114 struct kvm_memslots *slots = kvm_memslots(kvm);
8115 struct kvm_memory_slot *slot, old;
8117 /* Called with kvm->slots_lock held. */
8118 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8121 slot = id_to_memslot(slots, id);
8127 * MAP_SHARED to prevent internal slot pages from being moved
8130 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8131 MAP_SHARED | MAP_ANONYMOUS, 0);
8132 if (IS_ERR((void *)hva))
8133 return PTR_ERR((void *)hva);
8142 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8143 struct kvm_userspace_memory_region m;
8145 m.slot = id | (i << 16);
8147 m.guest_phys_addr = gpa;
8148 m.userspace_addr = hva;
8149 m.memory_size = size;
8150 r = __kvm_set_memory_region(kvm, &m);
8156 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8162 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8164 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8168 mutex_lock(&kvm->slots_lock);
8169 r = __x86_set_memory_region(kvm, id, gpa, size);
8170 mutex_unlock(&kvm->slots_lock);
8174 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8176 void kvm_arch_destroy_vm(struct kvm *kvm)
8178 if (current->mm == kvm->mm) {
8180 * Free memory regions allocated on behalf of userspace,
8181 * unless the the memory map has changed due to process exit
8184 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8185 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8186 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8188 if (kvm_x86_ops->vm_destroy)
8189 kvm_x86_ops->vm_destroy(kvm);
8190 kvm_pic_destroy(kvm);
8191 kvm_ioapic_destroy(kvm);
8192 kvm_free_vcpus(kvm);
8193 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8194 kvm_mmu_uninit_vm(kvm);
8195 kvm_page_track_cleanup(kvm);
8198 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8199 struct kvm_memory_slot *dont)
8203 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8204 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8205 kvfree(free->arch.rmap[i]);
8206 free->arch.rmap[i] = NULL;
8211 if (!dont || free->arch.lpage_info[i - 1] !=
8212 dont->arch.lpage_info[i - 1]) {
8213 kvfree(free->arch.lpage_info[i - 1]);
8214 free->arch.lpage_info[i - 1] = NULL;
8218 kvm_page_track_free_memslot(free, dont);
8221 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8222 unsigned long npages)
8226 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8227 struct kvm_lpage_info *linfo;
8232 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8233 slot->base_gfn, level) + 1;
8235 slot->arch.rmap[i] =
8236 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
8237 if (!slot->arch.rmap[i])
8242 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
8246 slot->arch.lpage_info[i - 1] = linfo;
8248 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8249 linfo[0].disallow_lpage = 1;
8250 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8251 linfo[lpages - 1].disallow_lpage = 1;
8252 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8254 * If the gfn and userspace address are not aligned wrt each
8255 * other, or if explicitly asked to, disable large page
8256 * support for this slot
8258 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8259 !kvm_largepages_enabled()) {
8262 for (j = 0; j < lpages; ++j)
8263 linfo[j].disallow_lpage = 1;
8267 if (kvm_page_track_create_memslot(slot, npages))
8273 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8274 kvfree(slot->arch.rmap[i]);
8275 slot->arch.rmap[i] = NULL;
8279 kvfree(slot->arch.lpage_info[i - 1]);
8280 slot->arch.lpage_info[i - 1] = NULL;
8285 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8288 * memslots->generation has been incremented.
8289 * mmio generation may have reached its maximum value.
8291 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8294 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8295 struct kvm_memory_slot *memslot,
8296 const struct kvm_userspace_memory_region *mem,
8297 enum kvm_mr_change change)
8302 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8303 struct kvm_memory_slot *new)
8305 /* Still write protect RO slot */
8306 if (new->flags & KVM_MEM_READONLY) {
8307 kvm_mmu_slot_remove_write_access(kvm, new);
8312 * Call kvm_x86_ops dirty logging hooks when they are valid.
8314 * kvm_x86_ops->slot_disable_log_dirty is called when:
8316 * - KVM_MR_CREATE with dirty logging is disabled
8317 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8319 * The reason is, in case of PML, we need to set D-bit for any slots
8320 * with dirty logging disabled in order to eliminate unnecessary GPA
8321 * logging in PML buffer (and potential PML buffer full VMEXT). This
8322 * guarantees leaving PML enabled during guest's lifetime won't have
8323 * any additonal overhead from PML when guest is running with dirty
8324 * logging disabled for memory slots.
8326 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8327 * to dirty logging mode.
8329 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8331 * In case of write protect:
8333 * Write protect all pages for dirty logging.
8335 * All the sptes including the large sptes which point to this
8336 * slot are set to readonly. We can not create any new large
8337 * spte on this slot until the end of the logging.
8339 * See the comments in fast_page_fault().
8341 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8342 if (kvm_x86_ops->slot_enable_log_dirty)
8343 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8345 kvm_mmu_slot_remove_write_access(kvm, new);
8347 if (kvm_x86_ops->slot_disable_log_dirty)
8348 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8352 void kvm_arch_commit_memory_region(struct kvm *kvm,
8353 const struct kvm_userspace_memory_region *mem,
8354 const struct kvm_memory_slot *old,
8355 const struct kvm_memory_slot *new,
8356 enum kvm_mr_change change)
8358 int nr_mmu_pages = 0;
8360 if (!kvm->arch.n_requested_mmu_pages)
8361 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8364 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8367 * Dirty logging tracks sptes in 4k granularity, meaning that large
8368 * sptes have to be split. If live migration is successful, the guest
8369 * in the source machine will be destroyed and large sptes will be
8370 * created in the destination. However, if the guest continues to run
8371 * in the source machine (for example if live migration fails), small
8372 * sptes will remain around and cause bad performance.
8374 * Scan sptes if dirty logging has been stopped, dropping those
8375 * which can be collapsed into a single large-page spte. Later
8376 * page faults will create the large-page sptes.
8378 if ((change != KVM_MR_DELETE) &&
8379 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8380 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8381 kvm_mmu_zap_collapsible_sptes(kvm, new);
8384 * Set up write protection and/or dirty logging for the new slot.
8386 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8387 * been zapped so no dirty logging staff is needed for old slot. For
8388 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8389 * new and it's also covered when dealing with the new slot.
8391 * FIXME: const-ify all uses of struct kvm_memory_slot.
8393 if (change != KVM_MR_DELETE)
8394 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8397 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8399 kvm_mmu_invalidate_zap_all_pages(kvm);
8402 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8403 struct kvm_memory_slot *slot)
8405 kvm_page_track_flush_slot(kvm, slot);
8408 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8410 if (!list_empty_careful(&vcpu->async_pf.done))
8413 if (kvm_apic_has_events(vcpu))
8416 if (vcpu->arch.pv.pv_unhalted)
8419 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8420 (vcpu->arch.nmi_pending &&
8421 kvm_x86_ops->nmi_allowed(vcpu)))
8424 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8425 (vcpu->arch.smi_pending && !is_smm(vcpu)))
8428 if (kvm_arch_interrupt_allowed(vcpu) &&
8429 kvm_cpu_has_interrupt(vcpu))
8432 if (kvm_hv_has_stimer_pending(vcpu))
8438 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8440 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8443 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8445 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8448 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8450 return kvm_x86_ops->interrupt_allowed(vcpu);
8453 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8455 if (is_64_bit_mode(vcpu))
8456 return kvm_rip_read(vcpu);
8457 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8458 kvm_rip_read(vcpu));
8460 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8462 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8464 return kvm_get_linear_rip(vcpu) == linear_rip;
8466 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8468 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8470 unsigned long rflags;
8472 rflags = kvm_x86_ops->get_rflags(vcpu);
8473 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8474 rflags &= ~X86_EFLAGS_TF;
8477 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8479 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8481 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8482 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8483 rflags |= X86_EFLAGS_TF;
8484 kvm_x86_ops->set_rflags(vcpu, rflags);
8487 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8489 __kvm_set_rflags(vcpu, rflags);
8490 kvm_make_request(KVM_REQ_EVENT, vcpu);
8492 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8494 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8498 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8502 r = kvm_mmu_reload(vcpu);
8506 if (!vcpu->arch.mmu.direct_map &&
8507 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8510 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8513 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8515 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8518 static inline u32 kvm_async_pf_next_probe(u32 key)
8520 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8523 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8525 u32 key = kvm_async_pf_hash_fn(gfn);
8527 while (vcpu->arch.apf.gfns[key] != ~0)
8528 key = kvm_async_pf_next_probe(key);
8530 vcpu->arch.apf.gfns[key] = gfn;
8533 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8536 u32 key = kvm_async_pf_hash_fn(gfn);
8538 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8539 (vcpu->arch.apf.gfns[key] != gfn &&
8540 vcpu->arch.apf.gfns[key] != ~0); i++)
8541 key = kvm_async_pf_next_probe(key);
8546 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8548 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8551 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8555 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8557 vcpu->arch.apf.gfns[i] = ~0;
8559 j = kvm_async_pf_next_probe(j);
8560 if (vcpu->arch.apf.gfns[j] == ~0)
8562 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8564 * k lies cyclically in ]i,j]
8566 * |....j i.k.| or |.k..j i...|
8568 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8569 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8574 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8577 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8581 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8582 struct kvm_async_pf *work)
8584 struct x86_exception fault;
8586 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8587 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8589 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8590 (vcpu->arch.apf.send_user_only &&
8591 kvm_x86_ops->get_cpl(vcpu) == 0))
8592 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8593 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8594 fault.vector = PF_VECTOR;
8595 fault.error_code_valid = true;
8596 fault.error_code = 0;
8597 fault.nested_page_fault = false;
8598 fault.address = work->arch.token;
8599 fault.async_page_fault = true;
8600 kvm_inject_page_fault(vcpu, &fault);
8604 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8605 struct kvm_async_pf *work)
8607 struct x86_exception fault;
8609 if (work->wakeup_all)
8610 work->arch.token = ~0; /* broadcast wakeup */
8612 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8613 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8615 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8616 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8617 fault.vector = PF_VECTOR;
8618 fault.error_code_valid = true;
8619 fault.error_code = 0;
8620 fault.nested_page_fault = false;
8621 fault.address = work->arch.token;
8622 fault.async_page_fault = true;
8623 kvm_inject_page_fault(vcpu, &fault);
8625 vcpu->arch.apf.halted = false;
8626 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8629 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8631 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8634 return kvm_can_do_async_pf(vcpu);
8637 void kvm_arch_start_assignment(struct kvm *kvm)
8639 atomic_inc(&kvm->arch.assigned_device_count);
8641 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8643 void kvm_arch_end_assignment(struct kvm *kvm)
8645 atomic_dec(&kvm->arch.assigned_device_count);
8647 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8649 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8651 return atomic_read(&kvm->arch.assigned_device_count);
8653 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8655 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8657 atomic_inc(&kvm->arch.noncoherent_dma_count);
8659 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8661 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8663 atomic_dec(&kvm->arch.noncoherent_dma_count);
8665 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8667 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8669 return atomic_read(&kvm->arch.noncoherent_dma_count);
8671 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8673 bool kvm_arch_has_irq_bypass(void)
8675 return kvm_x86_ops->update_pi_irte != NULL;
8678 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8679 struct irq_bypass_producer *prod)
8681 struct kvm_kernel_irqfd *irqfd =
8682 container_of(cons, struct kvm_kernel_irqfd, consumer);
8684 irqfd->producer = prod;
8686 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8687 prod->irq, irqfd->gsi, 1);
8690 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8691 struct irq_bypass_producer *prod)
8694 struct kvm_kernel_irqfd *irqfd =
8695 container_of(cons, struct kvm_kernel_irqfd, consumer);
8697 WARN_ON(irqfd->producer != prod);
8698 irqfd->producer = NULL;
8701 * When producer of consumer is unregistered, we change back to
8702 * remapped mode, so we can re-use the current implementation
8703 * when the irq is masked/disabled or the consumer side (KVM
8704 * int this case doesn't want to receive the interrupts.
8706 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8708 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8709 " fails: %d\n", irqfd->consumer.token, ret);
8712 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8713 uint32_t guest_irq, bool set)
8715 if (!kvm_x86_ops->update_pi_irte)
8718 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8721 bool kvm_vector_hashing_enabled(void)
8723 return vector_hashing;
8725 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8727 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8728 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8729 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8730 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8731 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8732 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8733 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8734 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8735 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8736 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8737 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8738 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8739 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8740 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8741 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8742 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8743 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8744 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8745 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);