1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/sched/isolation.h>
58 #include <linux/mem_encrypt.h>
59 #include <linux/entry-kvm.h>
61 #include <trace/events/kvm.h>
63 #include <asm/debugreg.h>
67 #include <linux/kernel_stat.h>
68 #include <asm/fpu/internal.h> /* Ugh! */
69 #include <asm/pvclock.h>
70 #include <asm/div64.h>
71 #include <asm/irq_remapping.h>
72 #include <asm/mshyperv.h>
73 #include <asm/hypervisor.h>
74 #include <asm/intel_pt.h>
75 #include <asm/emulate_prefix.h>
76 #include <clocksource/hyperv_timer.h>
78 #define CREATE_TRACE_POINTS
81 #define MAX_IO_MSRS 256
82 #define KVM_MAX_MCE_BANKS 32
83 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
84 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
86 #define emul_to_vcpu(ctxt) \
87 ((struct kvm_vcpu *)(ctxt)->vcpu)
90 * - enable syscall per default because its emulated by KVM
91 * - enable LME and LMA per default on 64 bit KVM
95 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
97 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
100 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
102 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
103 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
105 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
106 static void process_nmi(struct kvm_vcpu *vcpu);
107 static void enter_smm(struct kvm_vcpu *vcpu);
108 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
109 static void store_regs(struct kvm_vcpu *vcpu);
110 static int sync_regs(struct kvm_vcpu *vcpu);
112 struct kvm_x86_ops kvm_x86_ops __read_mostly;
113 EXPORT_SYMBOL_GPL(kvm_x86_ops);
115 static bool __read_mostly ignore_msrs = 0;
116 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
118 static bool __read_mostly report_ignored_msrs = true;
119 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
121 unsigned int min_timer_period_us = 200;
122 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
124 static bool __read_mostly kvmclock_periodic_sync = true;
125 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
127 bool __read_mostly kvm_has_tsc_control;
128 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
129 u32 __read_mostly kvm_max_guest_tsc_khz;
130 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
131 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
132 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
133 u64 __read_mostly kvm_max_tsc_scaling_ratio;
134 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
135 u64 __read_mostly kvm_default_tsc_scaling_ratio;
136 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
138 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
139 static u32 __read_mostly tsc_tolerance_ppm = 250;
140 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
143 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
144 * adaptive tuning starting from default advancment of 1000ns. '0' disables
145 * advancement entirely. Any other value is used as-is and disables adaptive
146 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
148 static int __read_mostly lapic_timer_advance_ns = -1;
149 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
151 static bool __read_mostly vector_hashing = true;
152 module_param(vector_hashing, bool, S_IRUGO);
154 bool __read_mostly enable_vmware_backdoor = false;
155 module_param(enable_vmware_backdoor, bool, S_IRUGO);
156 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
158 static bool __read_mostly force_emulation_prefix = false;
159 module_param(force_emulation_prefix, bool, S_IRUGO);
161 int __read_mostly pi_inject_timer = -1;
162 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
164 #define KVM_NR_SHARED_MSRS 16
166 struct kvm_shared_msrs_global {
168 u32 msrs[KVM_NR_SHARED_MSRS];
171 struct kvm_shared_msrs {
172 struct user_return_notifier urn;
174 struct kvm_shared_msr_values {
177 } values[KVM_NR_SHARED_MSRS];
180 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
181 static struct kvm_shared_msrs __percpu *shared_msrs;
183 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
184 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
185 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
186 | XFEATURE_MASK_PKRU)
188 u64 __read_mostly host_efer;
189 EXPORT_SYMBOL_GPL(host_efer);
191 bool __read_mostly allow_smaller_maxphyaddr;
192 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
194 static u64 __read_mostly host_xss;
195 u64 __read_mostly supported_xss;
196 EXPORT_SYMBOL_GPL(supported_xss);
198 struct kvm_stats_debugfs_item debugfs_entries[] = {
199 VCPU_STAT("pf_fixed", pf_fixed),
200 VCPU_STAT("pf_guest", pf_guest),
201 VCPU_STAT("tlb_flush", tlb_flush),
202 VCPU_STAT("invlpg", invlpg),
203 VCPU_STAT("exits", exits),
204 VCPU_STAT("io_exits", io_exits),
205 VCPU_STAT("mmio_exits", mmio_exits),
206 VCPU_STAT("signal_exits", signal_exits),
207 VCPU_STAT("irq_window", irq_window_exits),
208 VCPU_STAT("nmi_window", nmi_window_exits),
209 VCPU_STAT("halt_exits", halt_exits),
210 VCPU_STAT("halt_successful_poll", halt_successful_poll),
211 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
212 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
213 VCPU_STAT("halt_wakeup", halt_wakeup),
214 VCPU_STAT("hypercalls", hypercalls),
215 VCPU_STAT("request_irq", request_irq_exits),
216 VCPU_STAT("irq_exits", irq_exits),
217 VCPU_STAT("host_state_reload", host_state_reload),
218 VCPU_STAT("fpu_reload", fpu_reload),
219 VCPU_STAT("insn_emulation", insn_emulation),
220 VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
221 VCPU_STAT("irq_injections", irq_injections),
222 VCPU_STAT("nmi_injections", nmi_injections),
223 VCPU_STAT("req_event", req_event),
224 VCPU_STAT("l1d_flush", l1d_flush),
225 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
226 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
227 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
228 VM_STAT("mmu_pte_write", mmu_pte_write),
229 VM_STAT("mmu_pte_updated", mmu_pte_updated),
230 VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
231 VM_STAT("mmu_flooded", mmu_flooded),
232 VM_STAT("mmu_recycled", mmu_recycled),
233 VM_STAT("mmu_cache_miss", mmu_cache_miss),
234 VM_STAT("mmu_unsync", mmu_unsync),
235 VM_STAT("remote_tlb_flush", remote_tlb_flush),
236 VM_STAT("largepages", lpages, .mode = 0444),
237 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
238 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
242 u64 __read_mostly host_xcr0;
243 u64 __read_mostly supported_xcr0;
244 EXPORT_SYMBOL_GPL(supported_xcr0);
246 static struct kmem_cache *x86_fpu_cache;
248 static struct kmem_cache *x86_emulator_cache;
251 * When called, it means the previous get/set msr reached an invalid msr.
252 * Return 0 if we want to ignore/silent this failed msr access, or 1 if we want
253 * to fail the caller.
255 static int kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
256 u64 data, bool write)
258 const char *op = write ? "wrmsr" : "rdmsr";
261 if (report_ignored_msrs)
262 vcpu_unimpl(vcpu, "ignored %s: 0x%x data 0x%llx\n",
267 vcpu_debug_ratelimited(vcpu, "unhandled %s: 0x%x data 0x%llx\n",
273 static struct kmem_cache *kvm_alloc_emulator_cache(void)
275 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
276 unsigned int size = sizeof(struct x86_emulate_ctxt);
278 return kmem_cache_create_usercopy("x86_emulator", size,
279 __alignof__(struct x86_emulate_ctxt),
280 SLAB_ACCOUNT, useroffset,
281 size - useroffset, NULL);
284 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
286 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
289 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
290 vcpu->arch.apf.gfns[i] = ~0;
293 static void kvm_on_user_return(struct user_return_notifier *urn)
296 struct kvm_shared_msrs *locals
297 = container_of(urn, struct kvm_shared_msrs, urn);
298 struct kvm_shared_msr_values *values;
302 * Disabling irqs at this point since the following code could be
303 * interrupted and executed through kvm_arch_hardware_disable()
305 local_irq_save(flags);
306 if (locals->registered) {
307 locals->registered = false;
308 user_return_notifier_unregister(urn);
310 local_irq_restore(flags);
311 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
312 values = &locals->values[slot];
313 if (values->host != values->curr) {
314 wrmsrl(shared_msrs_global.msrs[slot], values->host);
315 values->curr = values->host;
320 void kvm_define_shared_msr(unsigned slot, u32 msr)
322 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
323 shared_msrs_global.msrs[slot] = msr;
324 if (slot >= shared_msrs_global.nr)
325 shared_msrs_global.nr = slot + 1;
327 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
329 static void kvm_shared_msr_cpu_online(void)
331 unsigned int cpu = smp_processor_id();
332 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
336 for (i = 0; i < shared_msrs_global.nr; ++i) {
337 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
338 smsr->values[i].host = value;
339 smsr->values[i].curr = value;
343 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
345 unsigned int cpu = smp_processor_id();
346 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
349 value = (value & mask) | (smsr->values[slot].host & ~mask);
350 if (value == smsr->values[slot].curr)
352 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
356 smsr->values[slot].curr = value;
357 if (!smsr->registered) {
358 smsr->urn.on_user_return = kvm_on_user_return;
359 user_return_notifier_register(&smsr->urn);
360 smsr->registered = true;
364 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
366 static void drop_user_return_notifiers(void)
368 unsigned int cpu = smp_processor_id();
369 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
371 if (smsr->registered)
372 kvm_on_user_return(&smsr->urn);
375 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
377 return vcpu->arch.apic_base;
379 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
381 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
383 return kvm_apic_mode(kvm_get_apic_base(vcpu));
385 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
387 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
389 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
390 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
391 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
392 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
394 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
396 if (!msr_info->host_initiated) {
397 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
399 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
403 kvm_lapic_set_base(vcpu, msr_info->data);
404 kvm_recalculate_apic_map(vcpu->kvm);
407 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
409 asmlinkage __visible noinstr void kvm_spurious_fault(void)
411 /* Fault while not rebooting. We want the trace. */
412 BUG_ON(!kvm_rebooting);
414 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
416 #define EXCPT_BENIGN 0
417 #define EXCPT_CONTRIBUTORY 1
420 static int exception_class(int vector)
430 return EXCPT_CONTRIBUTORY;
437 #define EXCPT_FAULT 0
439 #define EXCPT_ABORT 2
440 #define EXCPT_INTERRUPT 3
442 static int exception_type(int vector)
446 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
447 return EXCPT_INTERRUPT;
451 /* #DB is trap, as instruction watchpoints are handled elsewhere */
452 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
455 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
458 /* Reserved exceptions will result in fault */
462 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
464 unsigned nr = vcpu->arch.exception.nr;
465 bool has_payload = vcpu->arch.exception.has_payload;
466 unsigned long payload = vcpu->arch.exception.payload;
474 * "Certain debug exceptions may clear bit 0-3. The
475 * remaining contents of the DR6 register are never
476 * cleared by the processor".
478 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
480 * DR6.RTM is set by all #DB exceptions that don't clear it.
482 vcpu->arch.dr6 |= DR6_RTM;
483 vcpu->arch.dr6 |= payload;
485 * Bit 16 should be set in the payload whenever the #DB
486 * exception should clear DR6.RTM. This makes the payload
487 * compatible with the pending debug exceptions under VMX.
488 * Though not currently documented in the SDM, this also
489 * makes the payload compatible with the exit qualification
490 * for #DB exceptions under VMX.
492 vcpu->arch.dr6 ^= payload & DR6_RTM;
495 * The #DB payload is defined as compatible with the 'pending
496 * debug exceptions' field under VMX, not DR6. While bit 12 is
497 * defined in the 'pending debug exceptions' field (enabled
498 * breakpoint), it is reserved and must be zero in DR6.
500 vcpu->arch.dr6 &= ~BIT(12);
503 vcpu->arch.cr2 = payload;
507 vcpu->arch.exception.has_payload = false;
508 vcpu->arch.exception.payload = 0;
510 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
512 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
513 unsigned nr, bool has_error, u32 error_code,
514 bool has_payload, unsigned long payload, bool reinject)
519 kvm_make_request(KVM_REQ_EVENT, vcpu);
521 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
523 if (has_error && !is_protmode(vcpu))
527 * On vmentry, vcpu->arch.exception.pending is only
528 * true if an event injection was blocked by
529 * nested_run_pending. In that case, however,
530 * vcpu_enter_guest requests an immediate exit,
531 * and the guest shouldn't proceed far enough to
534 WARN_ON_ONCE(vcpu->arch.exception.pending);
535 vcpu->arch.exception.injected = true;
536 if (WARN_ON_ONCE(has_payload)) {
538 * A reinjected event has already
539 * delivered its payload.
545 vcpu->arch.exception.pending = true;
546 vcpu->arch.exception.injected = false;
548 vcpu->arch.exception.has_error_code = has_error;
549 vcpu->arch.exception.nr = nr;
550 vcpu->arch.exception.error_code = error_code;
551 vcpu->arch.exception.has_payload = has_payload;
552 vcpu->arch.exception.payload = payload;
553 if (!is_guest_mode(vcpu))
554 kvm_deliver_exception_payload(vcpu);
558 /* to check exception */
559 prev_nr = vcpu->arch.exception.nr;
560 if (prev_nr == DF_VECTOR) {
561 /* triple fault -> shutdown */
562 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
565 class1 = exception_class(prev_nr);
566 class2 = exception_class(nr);
567 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
568 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
570 * Generate double fault per SDM Table 5-5. Set
571 * exception.pending = true so that the double fault
572 * can trigger a nested vmexit.
574 vcpu->arch.exception.pending = true;
575 vcpu->arch.exception.injected = false;
576 vcpu->arch.exception.has_error_code = true;
577 vcpu->arch.exception.nr = DF_VECTOR;
578 vcpu->arch.exception.error_code = 0;
579 vcpu->arch.exception.has_payload = false;
580 vcpu->arch.exception.payload = 0;
582 /* replace previous exception with a new one in a hope
583 that instruction re-execution will regenerate lost
588 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
590 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
592 EXPORT_SYMBOL_GPL(kvm_queue_exception);
594 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
596 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
598 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
600 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
601 unsigned long payload)
603 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
605 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
607 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
608 u32 error_code, unsigned long payload)
610 kvm_multiple_exception(vcpu, nr, true, error_code,
611 true, payload, false);
614 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
617 kvm_inject_gp(vcpu, 0);
619 return kvm_skip_emulated_instruction(vcpu);
623 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
625 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
627 ++vcpu->stat.pf_guest;
628 vcpu->arch.exception.nested_apf =
629 is_guest_mode(vcpu) && fault->async_page_fault;
630 if (vcpu->arch.exception.nested_apf) {
631 vcpu->arch.apf.nested_apf_token = fault->address;
632 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
634 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
638 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
640 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
641 struct x86_exception *fault)
643 struct kvm_mmu *fault_mmu;
644 WARN_ON_ONCE(fault->vector != PF_VECTOR);
646 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
650 * Invalidate the TLB entry for the faulting address, if it exists,
651 * else the access will fault indefinitely (and to emulate hardware).
653 if ((fault->error_code & PFERR_PRESENT_MASK) &&
654 !(fault->error_code & PFERR_RSVD_MASK))
655 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
656 fault_mmu->root_hpa);
658 fault_mmu->inject_page_fault(vcpu, fault);
659 return fault->nested_page_fault;
661 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
663 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
665 atomic_inc(&vcpu->arch.nmi_queued);
666 kvm_make_request(KVM_REQ_NMI, vcpu);
668 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
670 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
672 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
674 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
676 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
678 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
680 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
683 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
684 * a #GP and return false.
686 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
688 if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
690 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
693 EXPORT_SYMBOL_GPL(kvm_require_cpl);
695 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
697 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
700 kvm_queue_exception(vcpu, UD_VECTOR);
703 EXPORT_SYMBOL_GPL(kvm_require_dr);
706 * This function will be used to read from the physical memory of the currently
707 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
708 * can read from guest physical or from the guest's guest physical memory.
710 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
711 gfn_t ngfn, void *data, int offset, int len,
714 struct x86_exception exception;
718 ngpa = gfn_to_gpa(ngfn);
719 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
720 if (real_gfn == UNMAPPED_GVA)
723 real_gfn = gpa_to_gfn(real_gfn);
725 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
727 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
729 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
730 void *data, int offset, int len, u32 access)
732 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
733 data, offset, len, access);
736 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
738 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
743 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
745 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
747 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
748 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
751 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
753 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
754 offset * sizeof(u64), sizeof(pdpte),
755 PFERR_USER_MASK|PFERR_WRITE_MASK);
760 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
761 if ((pdpte[i] & PT_PRESENT_MASK) &&
762 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
769 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
770 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
776 EXPORT_SYMBOL_GPL(load_pdptrs);
778 bool pdptrs_changed(struct kvm_vcpu *vcpu)
780 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
785 if (!is_pae_paging(vcpu))
788 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
791 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
792 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
793 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
794 PFERR_USER_MASK | PFERR_WRITE_MASK);
798 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
800 EXPORT_SYMBOL_GPL(pdptrs_changed);
802 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
804 unsigned long old_cr0 = kvm_read_cr0(vcpu);
805 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
806 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
811 if (cr0 & 0xffffffff00000000UL)
815 cr0 &= ~CR0_RESERVED_BITS;
817 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
820 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
824 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
825 (cr0 & X86_CR0_PG)) {
830 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
835 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
836 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
837 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
840 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
843 kvm_x86_ops.set_cr0(vcpu, cr0);
845 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
846 kvm_clear_async_pf_completion_queue(vcpu);
847 kvm_async_pf_hash_reset(vcpu);
850 if ((cr0 ^ old_cr0) & update_bits)
851 kvm_mmu_reset_context(vcpu);
853 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
854 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
855 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
856 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
860 EXPORT_SYMBOL_GPL(kvm_set_cr0);
862 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
864 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
866 EXPORT_SYMBOL_GPL(kvm_lmsw);
868 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
870 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
872 if (vcpu->arch.xcr0 != host_xcr0)
873 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
875 if (vcpu->arch.xsaves_enabled &&
876 vcpu->arch.ia32_xss != host_xss)
877 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
880 if (static_cpu_has(X86_FEATURE_PKU) &&
881 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
882 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
883 vcpu->arch.pkru != vcpu->arch.host_pkru)
884 __write_pkru(vcpu->arch.pkru);
886 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
888 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
890 if (static_cpu_has(X86_FEATURE_PKU) &&
891 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
892 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
893 vcpu->arch.pkru = rdpkru();
894 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
895 __write_pkru(vcpu->arch.host_pkru);
898 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
900 if (vcpu->arch.xcr0 != host_xcr0)
901 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
903 if (vcpu->arch.xsaves_enabled &&
904 vcpu->arch.ia32_xss != host_xss)
905 wrmsrl(MSR_IA32_XSS, host_xss);
909 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
911 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
914 u64 old_xcr0 = vcpu->arch.xcr0;
917 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
918 if (index != XCR_XFEATURE_ENABLED_MASK)
920 if (!(xcr0 & XFEATURE_MASK_FP))
922 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
926 * Do not allow the guest to set bits that we do not support
927 * saving. However, xcr0 bit 0 is always set, even if the
928 * emulated CPU does not support XSAVE (see fx_init).
930 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
931 if (xcr0 & ~valid_bits)
934 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
935 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
938 if (xcr0 & XFEATURE_MASK_AVX512) {
939 if (!(xcr0 & XFEATURE_MASK_YMM))
941 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
944 vcpu->arch.xcr0 = xcr0;
946 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
947 kvm_update_cpuid_runtime(vcpu);
951 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
953 if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
954 __kvm_set_xcr(vcpu, index, xcr)) {
955 kvm_inject_gp(vcpu, 0);
960 EXPORT_SYMBOL_GPL(kvm_set_xcr);
962 int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
964 if (cr4 & cr4_reserved_bits)
967 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
972 EXPORT_SYMBOL_GPL(kvm_valid_cr4);
974 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
976 unsigned long old_cr4 = kvm_read_cr4(vcpu);
977 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
980 if (kvm_valid_cr4(vcpu, cr4))
983 if (is_long_mode(vcpu)) {
984 if (!(cr4 & X86_CR4_PAE))
986 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
988 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
989 && ((cr4 ^ old_cr4) & pdptr_bits)
990 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
994 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
995 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
998 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
999 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1003 if (kvm_x86_ops.set_cr4(vcpu, cr4))
1006 if (((cr4 ^ old_cr4) & pdptr_bits) ||
1007 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1008 kvm_mmu_reset_context(vcpu);
1010 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1011 kvm_update_cpuid_runtime(vcpu);
1015 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1017 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1019 bool skip_tlb_flush = false;
1020 #ifdef CONFIG_X86_64
1021 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1024 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1025 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1029 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1030 if (!skip_tlb_flush) {
1031 kvm_mmu_sync_roots(vcpu);
1032 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1037 if (is_long_mode(vcpu) &&
1038 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
1040 else if (is_pae_paging(vcpu) &&
1041 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1044 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1045 vcpu->arch.cr3 = cr3;
1046 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1050 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1052 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1054 if (cr8 & CR8_RESERVED_BITS)
1056 if (lapic_in_kernel(vcpu))
1057 kvm_lapic_set_tpr(vcpu, cr8);
1059 vcpu->arch.cr8 = cr8;
1062 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1064 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1066 if (lapic_in_kernel(vcpu))
1067 return kvm_lapic_get_cr8(vcpu);
1069 return vcpu->arch.cr8;
1071 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1073 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1077 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1078 for (i = 0; i < KVM_NR_DB_REGS; i++)
1079 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1080 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1084 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1088 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1089 dr7 = vcpu->arch.guest_debug_dr7;
1091 dr7 = vcpu->arch.dr7;
1092 kvm_x86_ops.set_dr7(vcpu, dr7);
1093 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1094 if (dr7 & DR7_BP_EN_MASK)
1095 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1097 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1099 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1101 u64 fixed = DR6_FIXED_1;
1103 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1108 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1110 size_t size = ARRAY_SIZE(vcpu->arch.db);
1114 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1115 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1116 vcpu->arch.eff_db[dr] = val;
1121 if (!kvm_dr6_valid(val))
1122 return -1; /* #GP */
1123 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1128 if (!kvm_dr7_valid(val))
1129 return -1; /* #GP */
1130 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1131 kvm_update_dr7(vcpu);
1138 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1140 if (__kvm_set_dr(vcpu, dr, val)) {
1141 kvm_inject_gp(vcpu, 0);
1146 EXPORT_SYMBOL_GPL(kvm_set_dr);
1148 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1150 size_t size = ARRAY_SIZE(vcpu->arch.db);
1154 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1159 *val = vcpu->arch.dr6;
1164 *val = vcpu->arch.dr7;
1169 EXPORT_SYMBOL_GPL(kvm_get_dr);
1171 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1173 u32 ecx = kvm_rcx_read(vcpu);
1177 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1180 kvm_rax_write(vcpu, (u32)data);
1181 kvm_rdx_write(vcpu, data >> 32);
1184 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1187 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1188 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1190 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1191 * extract the supported MSRs from the related const lists.
1192 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1193 * capabilities of the host cpu. This capabilities test skips MSRs that are
1194 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1195 * may depend on host virtualization features rather than host cpu features.
1198 static const u32 msrs_to_save_all[] = {
1199 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1201 #ifdef CONFIG_X86_64
1202 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1204 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1205 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1207 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1208 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1209 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1210 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1211 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1212 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1213 MSR_IA32_UMWAIT_CONTROL,
1215 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1216 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1217 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1218 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1219 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1220 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1221 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1222 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1223 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1224 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1225 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1226 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1227 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1228 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1229 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1230 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1231 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1232 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1233 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1234 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1235 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1236 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1239 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1240 static unsigned num_msrs_to_save;
1242 static const u32 emulated_msrs_all[] = {
1243 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1244 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1245 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1246 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1247 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1248 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1249 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1251 HV_X64_MSR_VP_INDEX,
1252 HV_X64_MSR_VP_RUNTIME,
1253 HV_X64_MSR_SCONTROL,
1254 HV_X64_MSR_STIMER0_CONFIG,
1255 HV_X64_MSR_VP_ASSIST_PAGE,
1256 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1257 HV_X64_MSR_TSC_EMULATION_STATUS,
1258 HV_X64_MSR_SYNDBG_OPTIONS,
1259 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1260 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1261 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1263 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1264 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1266 MSR_IA32_TSC_ADJUST,
1267 MSR_IA32_TSCDEADLINE,
1268 MSR_IA32_ARCH_CAPABILITIES,
1269 MSR_IA32_PERF_CAPABILITIES,
1270 MSR_IA32_MISC_ENABLE,
1271 MSR_IA32_MCG_STATUS,
1273 MSR_IA32_MCG_EXT_CTL,
1277 MSR_MISC_FEATURES_ENABLES,
1278 MSR_AMD64_VIRT_SPEC_CTRL,
1283 * The following list leaves out MSRs whose values are determined
1284 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1285 * We always support the "true" VMX control MSRs, even if the host
1286 * processor does not, so I am putting these registers here rather
1287 * than in msrs_to_save_all.
1290 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1291 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1292 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1293 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1295 MSR_IA32_VMX_CR0_FIXED0,
1296 MSR_IA32_VMX_CR4_FIXED0,
1297 MSR_IA32_VMX_VMCS_ENUM,
1298 MSR_IA32_VMX_PROCBASED_CTLS2,
1299 MSR_IA32_VMX_EPT_VPID_CAP,
1300 MSR_IA32_VMX_VMFUNC,
1303 MSR_KVM_POLL_CONTROL,
1306 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1307 static unsigned num_emulated_msrs;
1310 * List of msr numbers which are used to expose MSR-based features that
1311 * can be used by a hypervisor to validate requested CPU features.
1313 static const u32 msr_based_features_all[] = {
1315 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1316 MSR_IA32_VMX_PINBASED_CTLS,
1317 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1318 MSR_IA32_VMX_PROCBASED_CTLS,
1319 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1320 MSR_IA32_VMX_EXIT_CTLS,
1321 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1322 MSR_IA32_VMX_ENTRY_CTLS,
1324 MSR_IA32_VMX_CR0_FIXED0,
1325 MSR_IA32_VMX_CR0_FIXED1,
1326 MSR_IA32_VMX_CR4_FIXED0,
1327 MSR_IA32_VMX_CR4_FIXED1,
1328 MSR_IA32_VMX_VMCS_ENUM,
1329 MSR_IA32_VMX_PROCBASED_CTLS2,
1330 MSR_IA32_VMX_EPT_VPID_CAP,
1331 MSR_IA32_VMX_VMFUNC,
1335 MSR_IA32_ARCH_CAPABILITIES,
1336 MSR_IA32_PERF_CAPABILITIES,
1339 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1340 static unsigned int num_msr_based_features;
1342 static u64 kvm_get_arch_capabilities(void)
1346 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1347 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1350 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1351 * the nested hypervisor runs with NX huge pages. If it is not,
1352 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1353 * L1 guests, so it need not worry about its own (L2) guests.
1355 data |= ARCH_CAP_PSCHANGE_MC_NO;
1358 * If we're doing cache flushes (either "always" or "cond")
1359 * we will do one whenever the guest does a vmlaunch/vmresume.
1360 * If an outer hypervisor is doing the cache flush for us
1361 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1362 * capability to the guest too, and if EPT is disabled we're not
1363 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1364 * require a nested hypervisor to do a flush of its own.
1366 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1367 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1369 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1370 data |= ARCH_CAP_RDCL_NO;
1371 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1372 data |= ARCH_CAP_SSB_NO;
1373 if (!boot_cpu_has_bug(X86_BUG_MDS))
1374 data |= ARCH_CAP_MDS_NO;
1377 * On TAA affected systems:
1378 * - nothing to do if TSX is disabled on the host.
1379 * - we emulate TSX_CTRL if present on the host.
1380 * This lets the guest use VERW to clear CPU buffers.
1382 if (!boot_cpu_has(X86_FEATURE_RTM))
1383 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1384 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1385 data |= ARCH_CAP_TAA_NO;
1390 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1392 switch (msr->index) {
1393 case MSR_IA32_ARCH_CAPABILITIES:
1394 msr->data = kvm_get_arch_capabilities();
1396 case MSR_IA32_UCODE_REV:
1397 rdmsrl_safe(msr->index, &msr->data);
1400 return kvm_x86_ops.get_msr_feature(msr);
1405 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1407 struct kvm_msr_entry msr;
1411 r = kvm_get_msr_feature(&msr);
1413 if (r == KVM_MSR_RET_INVALID) {
1414 /* Unconditionally clear the output for simplicity */
1416 r = kvm_msr_ignored_check(vcpu, index, 0, false);
1427 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1429 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1432 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1435 if (efer & (EFER_LME | EFER_LMA) &&
1436 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1439 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1445 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1447 if (efer & efer_reserved_bits)
1450 return __kvm_valid_efer(vcpu, efer);
1452 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1454 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1456 u64 old_efer = vcpu->arch.efer;
1457 u64 efer = msr_info->data;
1459 if (efer & efer_reserved_bits)
1462 if (!msr_info->host_initiated) {
1463 if (!__kvm_valid_efer(vcpu, efer))
1466 if (is_paging(vcpu) &&
1467 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1472 efer |= vcpu->arch.efer & EFER_LMA;
1474 kvm_x86_ops.set_efer(vcpu, efer);
1476 /* Update reserved bits */
1477 if ((efer ^ old_efer) & EFER_NX)
1478 kvm_mmu_reset_context(vcpu);
1483 void kvm_enable_efer_bits(u64 mask)
1485 efer_reserved_bits &= ~mask;
1487 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1490 * Write @data into the MSR specified by @index. Select MSR specific fault
1491 * checks are bypassed if @host_initiated is %true.
1492 * Returns 0 on success, non-0 otherwise.
1493 * Assumes vcpu_load() was already called.
1495 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1496 bool host_initiated)
1498 struct msr_data msr;
1503 case MSR_KERNEL_GS_BASE:
1506 if (is_noncanonical_address(data, vcpu))
1509 case MSR_IA32_SYSENTER_EIP:
1510 case MSR_IA32_SYSENTER_ESP:
1512 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1513 * non-canonical address is written on Intel but not on
1514 * AMD (which ignores the top 32-bits, because it does
1515 * not implement 64-bit SYSENTER).
1517 * 64-bit code should hence be able to write a non-canonical
1518 * value on AMD. Making the address canonical ensures that
1519 * vmentry does not fail on Intel after writing a non-canonical
1520 * value, and that something deterministic happens if the guest
1521 * invokes 64-bit SYSENTER.
1523 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1528 msr.host_initiated = host_initiated;
1530 return kvm_x86_ops.set_msr(vcpu, &msr);
1533 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1534 u32 index, u64 data, bool host_initiated)
1536 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1538 if (ret == KVM_MSR_RET_INVALID)
1539 ret = kvm_msr_ignored_check(vcpu, index, data, true);
1545 * Read the MSR specified by @index into @data. Select MSR specific fault
1546 * checks are bypassed if @host_initiated is %true.
1547 * Returns 0 on success, non-0 otherwise.
1548 * Assumes vcpu_load() was already called.
1550 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1551 bool host_initiated)
1553 struct msr_data msr;
1557 msr.host_initiated = host_initiated;
1559 ret = kvm_x86_ops.get_msr(vcpu, &msr);
1565 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1566 u32 index, u64 *data, bool host_initiated)
1568 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1570 if (ret == KVM_MSR_RET_INVALID) {
1571 /* Unconditionally clear *data for simplicity */
1573 ret = kvm_msr_ignored_check(vcpu, index, 0, false);
1579 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1581 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1583 EXPORT_SYMBOL_GPL(kvm_get_msr);
1585 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1587 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1589 EXPORT_SYMBOL_GPL(kvm_set_msr);
1591 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1593 u32 ecx = kvm_rcx_read(vcpu);
1596 if (kvm_get_msr(vcpu, ecx, &data)) {
1597 trace_kvm_msr_read_ex(ecx);
1598 kvm_inject_gp(vcpu, 0);
1602 trace_kvm_msr_read(ecx, data);
1604 kvm_rax_write(vcpu, data & -1u);
1605 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1606 return kvm_skip_emulated_instruction(vcpu);
1608 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1610 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1612 u32 ecx = kvm_rcx_read(vcpu);
1613 u64 data = kvm_read_edx_eax(vcpu);
1615 if (kvm_set_msr(vcpu, ecx, data)) {
1616 trace_kvm_msr_write_ex(ecx, data);
1617 kvm_inject_gp(vcpu, 0);
1621 trace_kvm_msr_write(ecx, data);
1622 return kvm_skip_emulated_instruction(vcpu);
1624 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1626 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1628 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1629 xfer_to_guest_mode_work_pending();
1631 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request);
1634 * The fast path for frequent and performance sensitive wrmsr emulation,
1635 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1636 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1637 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1638 * other cases which must be called after interrupts are enabled on the host.
1640 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1642 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1645 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1646 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1647 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1648 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1651 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1652 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1653 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1654 trace_kvm_apic_write(APIC_ICR, (u32)data);
1661 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1663 if (!kvm_can_use_hv_timer(vcpu))
1666 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1670 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1672 u32 msr = kvm_rcx_read(vcpu);
1674 fastpath_t ret = EXIT_FASTPATH_NONE;
1677 case APIC_BASE_MSR + (APIC_ICR >> 4):
1678 data = kvm_read_edx_eax(vcpu);
1679 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1680 kvm_skip_emulated_instruction(vcpu);
1681 ret = EXIT_FASTPATH_EXIT_HANDLED;
1684 case MSR_IA32_TSCDEADLINE:
1685 data = kvm_read_edx_eax(vcpu);
1686 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1687 kvm_skip_emulated_instruction(vcpu);
1688 ret = EXIT_FASTPATH_REENTER_GUEST;
1695 if (ret != EXIT_FASTPATH_NONE)
1696 trace_kvm_msr_write(msr, data);
1700 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1703 * Adapt set_msr() to msr_io()'s calling convention
1705 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1707 return kvm_get_msr_ignored_check(vcpu, index, data, true);
1710 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1712 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1715 #ifdef CONFIG_X86_64
1716 struct pvclock_clock {
1726 struct pvclock_gtod_data {
1729 struct pvclock_clock clock; /* extract of a clocksource struct */
1730 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1736 static struct pvclock_gtod_data pvclock_gtod_data;
1738 static void update_pvclock_gtod(struct timekeeper *tk)
1740 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1742 write_seqcount_begin(&vdata->seq);
1744 /* copy pvclock gtod data */
1745 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
1746 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1747 vdata->clock.mask = tk->tkr_mono.mask;
1748 vdata->clock.mult = tk->tkr_mono.mult;
1749 vdata->clock.shift = tk->tkr_mono.shift;
1750 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1751 vdata->clock.offset = tk->tkr_mono.base;
1753 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
1754 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1755 vdata->raw_clock.mask = tk->tkr_raw.mask;
1756 vdata->raw_clock.mult = tk->tkr_raw.mult;
1757 vdata->raw_clock.shift = tk->tkr_raw.shift;
1758 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1759 vdata->raw_clock.offset = tk->tkr_raw.base;
1761 vdata->wall_time_sec = tk->xtime_sec;
1763 vdata->offs_boot = tk->offs_boot;
1765 write_seqcount_end(&vdata->seq);
1768 static s64 get_kvmclock_base_ns(void)
1770 /* Count up from boot time, but with the frequency of the raw clock. */
1771 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1774 static s64 get_kvmclock_base_ns(void)
1776 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1777 return ktime_get_boottime_ns();
1781 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1783 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1784 kvm_vcpu_kick(vcpu);
1787 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1791 struct pvclock_wall_clock wc;
1797 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1802 ++version; /* first time write, random junk */
1806 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1810 * The guest calculates current wall clock time by adding
1811 * system time (updated by kvm_guest_time_update below) to the
1812 * wall clock specified here. We do the reverse here.
1814 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1816 wc.nsec = do_div(wall_nsec, 1000000000);
1817 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1818 wc.version = version;
1820 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1823 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1826 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1828 do_shl32_div32(dividend, divisor);
1832 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1833 s8 *pshift, u32 *pmultiplier)
1841 scaled64 = scaled_hz;
1842 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1847 tps32 = (uint32_t)tps64;
1848 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1849 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1857 *pmultiplier = div_frac(scaled64, tps32);
1860 #ifdef CONFIG_X86_64
1861 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1864 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1865 static unsigned long max_tsc_khz;
1867 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1869 u64 v = (u64)khz * (1000000 + ppm);
1874 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1878 /* Guest TSC same frequency as host TSC? */
1880 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1884 /* TSC scaling supported? */
1885 if (!kvm_has_tsc_control) {
1886 if (user_tsc_khz > tsc_khz) {
1887 vcpu->arch.tsc_catchup = 1;
1888 vcpu->arch.tsc_always_catchup = 1;
1891 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1896 /* TSC scaling required - calculate ratio */
1897 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1898 user_tsc_khz, tsc_khz);
1900 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1901 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1906 vcpu->arch.tsc_scaling_ratio = ratio;
1910 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1912 u32 thresh_lo, thresh_hi;
1913 int use_scaling = 0;
1915 /* tsc_khz can be zero if TSC calibration fails */
1916 if (user_tsc_khz == 0) {
1917 /* set tsc_scaling_ratio to a safe value */
1918 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1922 /* Compute a scale to convert nanoseconds in TSC cycles */
1923 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1924 &vcpu->arch.virtual_tsc_shift,
1925 &vcpu->arch.virtual_tsc_mult);
1926 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1929 * Compute the variation in TSC rate which is acceptable
1930 * within the range of tolerance and decide if the
1931 * rate being applied is within that bounds of the hardware
1932 * rate. If so, no scaling or compensation need be done.
1934 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1935 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1936 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1937 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1940 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1943 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1945 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1946 vcpu->arch.virtual_tsc_mult,
1947 vcpu->arch.virtual_tsc_shift);
1948 tsc += vcpu->arch.this_tsc_write;
1952 static inline int gtod_is_based_on_tsc(int mode)
1954 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
1957 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1959 #ifdef CONFIG_X86_64
1961 struct kvm_arch *ka = &vcpu->kvm->arch;
1962 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1964 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1965 atomic_read(&vcpu->kvm->online_vcpus));
1968 * Once the masterclock is enabled, always perform request in
1969 * order to update it.
1971 * In order to enable masterclock, the host clocksource must be TSC
1972 * and the vcpus need to have matched TSCs. When that happens,
1973 * perform request to enable masterclock.
1975 if (ka->use_master_clock ||
1976 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1977 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1979 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1980 atomic_read(&vcpu->kvm->online_vcpus),
1981 ka->use_master_clock, gtod->clock.vclock_mode);
1985 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1987 u64 curr_offset = vcpu->arch.l1_tsc_offset;
1988 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1992 * Multiply tsc by a fixed point number represented by ratio.
1994 * The most significant 64-N bits (mult) of ratio represent the
1995 * integral part of the fixed point number; the remaining N bits
1996 * (frac) represent the fractional part, ie. ratio represents a fixed
1997 * point number (mult + frac * 2^(-N)).
1999 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2001 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2003 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2006 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2009 u64 ratio = vcpu->arch.tsc_scaling_ratio;
2011 if (ratio != kvm_default_tsc_scaling_ratio)
2012 _tsc = __scale_tsc(ratio, tsc);
2016 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2018 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2022 tsc = kvm_scale_tsc(vcpu, rdtsc());
2024 return target_tsc - tsc;
2027 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2029 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2031 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2033 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2035 vcpu->arch.l1_tsc_offset = offset;
2036 vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
2039 static inline bool kvm_check_tsc_unstable(void)
2041 #ifdef CONFIG_X86_64
2043 * TSC is marked unstable when we're running on Hyper-V,
2044 * 'TSC page' clocksource is good.
2046 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2049 return check_tsc_unstable();
2052 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
2054 struct kvm *kvm = vcpu->kvm;
2055 u64 offset, ns, elapsed;
2056 unsigned long flags;
2058 bool already_matched;
2059 u64 data = msr->data;
2060 bool synchronizing = false;
2062 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2063 offset = kvm_compute_tsc_offset(vcpu, data);
2064 ns = get_kvmclock_base_ns();
2065 elapsed = ns - kvm->arch.last_tsc_nsec;
2067 if (vcpu->arch.virtual_tsc_khz) {
2068 if (data == 0 && msr->host_initiated) {
2070 * detection of vcpu initialization -- need to sync
2071 * with other vCPUs. This particularly helps to keep
2072 * kvm_clock stable after CPU hotplug
2074 synchronizing = true;
2076 u64 tsc_exp = kvm->arch.last_tsc_write +
2077 nsec_to_cycles(vcpu, elapsed);
2078 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2080 * Special case: TSC write with a small delta (1 second)
2081 * of virtual cycle time against real time is
2082 * interpreted as an attempt to synchronize the CPU.
2084 synchronizing = data < tsc_exp + tsc_hz &&
2085 data + tsc_hz > tsc_exp;
2090 * For a reliable TSC, we can match TSC offsets, and for an unstable
2091 * TSC, we add elapsed time in this computation. We could let the
2092 * compensation code attempt to catch up if we fall behind, but
2093 * it's better to try to match offsets from the beginning.
2095 if (synchronizing &&
2096 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2097 if (!kvm_check_tsc_unstable()) {
2098 offset = kvm->arch.cur_tsc_offset;
2100 u64 delta = nsec_to_cycles(vcpu, elapsed);
2102 offset = kvm_compute_tsc_offset(vcpu, data);
2105 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2108 * We split periods of matched TSC writes into generations.
2109 * For each generation, we track the original measured
2110 * nanosecond time, offset, and write, so if TSCs are in
2111 * sync, we can match exact offset, and if not, we can match
2112 * exact software computation in compute_guest_tsc()
2114 * These values are tracked in kvm->arch.cur_xxx variables.
2116 kvm->arch.cur_tsc_generation++;
2117 kvm->arch.cur_tsc_nsec = ns;
2118 kvm->arch.cur_tsc_write = data;
2119 kvm->arch.cur_tsc_offset = offset;
2124 * We also track th most recent recorded KHZ, write and time to
2125 * allow the matching interval to be extended at each write.
2127 kvm->arch.last_tsc_nsec = ns;
2128 kvm->arch.last_tsc_write = data;
2129 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2131 vcpu->arch.last_guest_tsc = data;
2133 /* Keep track of which generation this VCPU has synchronized to */
2134 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2135 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2136 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2138 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2139 update_ia32_tsc_adjust_msr(vcpu, offset);
2141 kvm_vcpu_write_tsc_offset(vcpu, offset);
2142 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2144 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2146 kvm->arch.nr_vcpus_matched_tsc = 0;
2147 } else if (!already_matched) {
2148 kvm->arch.nr_vcpus_matched_tsc++;
2151 kvm_track_tsc_matching(vcpu);
2152 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2155 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2157 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2160 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2161 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2164 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2166 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2167 WARN_ON(adjustment < 0);
2168 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2169 adjust_tsc_offset_guest(vcpu, adjustment);
2172 #ifdef CONFIG_X86_64
2174 static u64 read_tsc(void)
2176 u64 ret = (u64)rdtsc_ordered();
2177 u64 last = pvclock_gtod_data.clock.cycle_last;
2179 if (likely(ret >= last))
2183 * GCC likes to generate cmov here, but this branch is extremely
2184 * predictable (it's just a function of time and the likely is
2185 * very likely) and there's a data dependence, so force GCC
2186 * to generate a branch instead. I don't barrier() because
2187 * we don't actually need a barrier, and if this function
2188 * ever gets inlined it will generate worse code.
2194 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2200 switch (clock->vclock_mode) {
2201 case VDSO_CLOCKMODE_HVCLOCK:
2202 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2204 if (tsc_pg_val != U64_MAX) {
2205 /* TSC page valid */
2206 *mode = VDSO_CLOCKMODE_HVCLOCK;
2207 v = (tsc_pg_val - clock->cycle_last) &
2210 /* TSC page invalid */
2211 *mode = VDSO_CLOCKMODE_NONE;
2214 case VDSO_CLOCKMODE_TSC:
2215 *mode = VDSO_CLOCKMODE_TSC;
2216 *tsc_timestamp = read_tsc();
2217 v = (*tsc_timestamp - clock->cycle_last) &
2221 *mode = VDSO_CLOCKMODE_NONE;
2224 if (*mode == VDSO_CLOCKMODE_NONE)
2225 *tsc_timestamp = v = 0;
2227 return v * clock->mult;
2230 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2232 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2238 seq = read_seqcount_begin(>od->seq);
2239 ns = gtod->raw_clock.base_cycles;
2240 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2241 ns >>= gtod->raw_clock.shift;
2242 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2243 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2249 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2251 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2257 seq = read_seqcount_begin(>od->seq);
2258 ts->tv_sec = gtod->wall_time_sec;
2259 ns = gtod->clock.base_cycles;
2260 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2261 ns >>= gtod->clock.shift;
2262 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2264 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2270 /* returns true if host is using TSC based clocksource */
2271 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2273 /* checked again under seqlock below */
2274 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2277 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2281 /* returns true if host is using TSC based clocksource */
2282 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2285 /* checked again under seqlock below */
2286 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2289 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2295 * Assuming a stable TSC across physical CPUS, and a stable TSC
2296 * across virtual CPUs, the following condition is possible.
2297 * Each numbered line represents an event visible to both
2298 * CPUs at the next numbered event.
2300 * "timespecX" represents host monotonic time. "tscX" represents
2303 * VCPU0 on CPU0 | VCPU1 on CPU1
2305 * 1. read timespec0,tsc0
2306 * 2. | timespec1 = timespec0 + N
2308 * 3. transition to guest | transition to guest
2309 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2310 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2311 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2313 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2316 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2318 * - 0 < N - M => M < N
2320 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2321 * always the case (the difference between two distinct xtime instances
2322 * might be smaller then the difference between corresponding TSC reads,
2323 * when updating guest vcpus pvclock areas).
2325 * To avoid that problem, do not allow visibility of distinct
2326 * system_timestamp/tsc_timestamp values simultaneously: use a master
2327 * copy of host monotonic time values. Update that master copy
2330 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2334 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2336 #ifdef CONFIG_X86_64
2337 struct kvm_arch *ka = &kvm->arch;
2339 bool host_tsc_clocksource, vcpus_matched;
2341 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2342 atomic_read(&kvm->online_vcpus));
2345 * If the host uses TSC clock, then passthrough TSC as stable
2348 host_tsc_clocksource = kvm_get_time_and_clockread(
2349 &ka->master_kernel_ns,
2350 &ka->master_cycle_now);
2352 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2353 && !ka->backwards_tsc_observed
2354 && !ka->boot_vcpu_runs_old_kvmclock;
2356 if (ka->use_master_clock)
2357 atomic_set(&kvm_guest_has_master_clock, 1);
2359 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2360 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2365 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2367 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2370 static void kvm_gen_update_masterclock(struct kvm *kvm)
2372 #ifdef CONFIG_X86_64
2374 struct kvm_vcpu *vcpu;
2375 struct kvm_arch *ka = &kvm->arch;
2377 spin_lock(&ka->pvclock_gtod_sync_lock);
2378 kvm_make_mclock_inprogress_request(kvm);
2379 /* no guest entries from this point */
2380 pvclock_update_vm_gtod_copy(kvm);
2382 kvm_for_each_vcpu(i, vcpu, kvm)
2383 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2385 /* guest entries allowed */
2386 kvm_for_each_vcpu(i, vcpu, kvm)
2387 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2389 spin_unlock(&ka->pvclock_gtod_sync_lock);
2393 u64 get_kvmclock_ns(struct kvm *kvm)
2395 struct kvm_arch *ka = &kvm->arch;
2396 struct pvclock_vcpu_time_info hv_clock;
2399 spin_lock(&ka->pvclock_gtod_sync_lock);
2400 if (!ka->use_master_clock) {
2401 spin_unlock(&ka->pvclock_gtod_sync_lock);
2402 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2405 hv_clock.tsc_timestamp = ka->master_cycle_now;
2406 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2407 spin_unlock(&ka->pvclock_gtod_sync_lock);
2409 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2412 if (__this_cpu_read(cpu_tsc_khz)) {
2413 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2414 &hv_clock.tsc_shift,
2415 &hv_clock.tsc_to_system_mul);
2416 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2418 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2425 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2427 struct kvm_vcpu_arch *vcpu = &v->arch;
2428 struct pvclock_vcpu_time_info guest_hv_clock;
2430 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2431 &guest_hv_clock, sizeof(guest_hv_clock))))
2434 /* This VCPU is paused, but it's legal for a guest to read another
2435 * VCPU's kvmclock, so we really have to follow the specification where
2436 * it says that version is odd if data is being modified, and even after
2439 * Version field updates must be kept separate. This is because
2440 * kvm_write_guest_cached might use a "rep movs" instruction, and
2441 * writes within a string instruction are weakly ordered. So there
2442 * are three writes overall.
2444 * As a small optimization, only write the version field in the first
2445 * and third write. The vcpu->pv_time cache is still valid, because the
2446 * version field is the first in the struct.
2448 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2450 if (guest_hv_clock.version & 1)
2451 ++guest_hv_clock.version; /* first time write, random junk */
2453 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2454 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2456 sizeof(vcpu->hv_clock.version));
2460 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2461 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2463 if (vcpu->pvclock_set_guest_stopped_request) {
2464 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2465 vcpu->pvclock_set_guest_stopped_request = false;
2468 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2470 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2472 sizeof(vcpu->hv_clock));
2476 vcpu->hv_clock.version++;
2477 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2479 sizeof(vcpu->hv_clock.version));
2482 static int kvm_guest_time_update(struct kvm_vcpu *v)
2484 unsigned long flags, tgt_tsc_khz;
2485 struct kvm_vcpu_arch *vcpu = &v->arch;
2486 struct kvm_arch *ka = &v->kvm->arch;
2488 u64 tsc_timestamp, host_tsc;
2490 bool use_master_clock;
2496 * If the host uses TSC clock, then passthrough TSC as stable
2499 spin_lock(&ka->pvclock_gtod_sync_lock);
2500 use_master_clock = ka->use_master_clock;
2501 if (use_master_clock) {
2502 host_tsc = ka->master_cycle_now;
2503 kernel_ns = ka->master_kernel_ns;
2505 spin_unlock(&ka->pvclock_gtod_sync_lock);
2507 /* Keep irq disabled to prevent changes to the clock */
2508 local_irq_save(flags);
2509 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2510 if (unlikely(tgt_tsc_khz == 0)) {
2511 local_irq_restore(flags);
2512 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2515 if (!use_master_clock) {
2517 kernel_ns = get_kvmclock_base_ns();
2520 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2523 * We may have to catch up the TSC to match elapsed wall clock
2524 * time for two reasons, even if kvmclock is used.
2525 * 1) CPU could have been running below the maximum TSC rate
2526 * 2) Broken TSC compensation resets the base at each VCPU
2527 * entry to avoid unknown leaps of TSC even when running
2528 * again on the same CPU. This may cause apparent elapsed
2529 * time to disappear, and the guest to stand still or run
2532 if (vcpu->tsc_catchup) {
2533 u64 tsc = compute_guest_tsc(v, kernel_ns);
2534 if (tsc > tsc_timestamp) {
2535 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2536 tsc_timestamp = tsc;
2540 local_irq_restore(flags);
2542 /* With all the info we got, fill in the values */
2544 if (kvm_has_tsc_control)
2545 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2547 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2548 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2549 &vcpu->hv_clock.tsc_shift,
2550 &vcpu->hv_clock.tsc_to_system_mul);
2551 vcpu->hw_tsc_khz = tgt_tsc_khz;
2554 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2555 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2556 vcpu->last_guest_tsc = tsc_timestamp;
2558 /* If the host uses TSC clocksource, then it is stable */
2560 if (use_master_clock)
2561 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2563 vcpu->hv_clock.flags = pvclock_flags;
2565 if (vcpu->pv_time_enabled)
2566 kvm_setup_pvclock_page(v);
2567 if (v == kvm_get_vcpu(v->kvm, 0))
2568 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2573 * kvmclock updates which are isolated to a given vcpu, such as
2574 * vcpu->cpu migration, should not allow system_timestamp from
2575 * the rest of the vcpus to remain static. Otherwise ntp frequency
2576 * correction applies to one vcpu's system_timestamp but not
2579 * So in those cases, request a kvmclock update for all vcpus.
2580 * We need to rate-limit these requests though, as they can
2581 * considerably slow guests that have a large number of vcpus.
2582 * The time for a remote vcpu to update its kvmclock is bound
2583 * by the delay we use to rate-limit the updates.
2586 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2588 static void kvmclock_update_fn(struct work_struct *work)
2591 struct delayed_work *dwork = to_delayed_work(work);
2592 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2593 kvmclock_update_work);
2594 struct kvm *kvm = container_of(ka, struct kvm, arch);
2595 struct kvm_vcpu *vcpu;
2597 kvm_for_each_vcpu(i, vcpu, kvm) {
2598 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2599 kvm_vcpu_kick(vcpu);
2603 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2605 struct kvm *kvm = v->kvm;
2607 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2608 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2609 KVMCLOCK_UPDATE_DELAY);
2612 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2614 static void kvmclock_sync_fn(struct work_struct *work)
2616 struct delayed_work *dwork = to_delayed_work(work);
2617 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2618 kvmclock_sync_work);
2619 struct kvm *kvm = container_of(ka, struct kvm, arch);
2621 if (!kvmclock_periodic_sync)
2624 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2625 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2626 KVMCLOCK_SYNC_PERIOD);
2630 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2632 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2634 /* McStatusWrEn enabled? */
2635 if (guest_cpuid_is_amd_or_hygon(vcpu))
2636 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2641 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2643 u64 mcg_cap = vcpu->arch.mcg_cap;
2644 unsigned bank_num = mcg_cap & 0xff;
2645 u32 msr = msr_info->index;
2646 u64 data = msr_info->data;
2649 case MSR_IA32_MCG_STATUS:
2650 vcpu->arch.mcg_status = data;
2652 case MSR_IA32_MCG_CTL:
2653 if (!(mcg_cap & MCG_CTL_P) &&
2654 (data || !msr_info->host_initiated))
2656 if (data != 0 && data != ~(u64)0)
2658 vcpu->arch.mcg_ctl = data;
2661 if (msr >= MSR_IA32_MC0_CTL &&
2662 msr < MSR_IA32_MCx_CTL(bank_num)) {
2663 u32 offset = array_index_nospec(
2664 msr - MSR_IA32_MC0_CTL,
2665 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2667 /* only 0 or all 1s can be written to IA32_MCi_CTL
2668 * some Linux kernels though clear bit 10 in bank 4 to
2669 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2670 * this to avoid an uncatched #GP in the guest
2672 if ((offset & 0x3) == 0 &&
2673 data != 0 && (data | (1 << 10)) != ~(u64)0)
2677 if (!msr_info->host_initiated &&
2678 (offset & 0x3) == 1 && data != 0) {
2679 if (!can_set_mci_status(vcpu))
2683 vcpu->arch.mce_banks[offset] = data;
2691 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2693 struct kvm *kvm = vcpu->kvm;
2694 int lm = is_long_mode(vcpu);
2695 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2696 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2697 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2698 : kvm->arch.xen_hvm_config.blob_size_32;
2699 u32 page_num = data & ~PAGE_MASK;
2700 u64 page_addr = data & PAGE_MASK;
2705 if (page_num >= blob_size)
2708 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2713 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2722 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2724 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2726 return (vcpu->arch.apf.msr_en_val & mask) == mask;
2729 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2731 gpa_t gpa = data & ~0x3f;
2733 /* Bits 4:5 are reserved, Should be zero */
2737 if (!lapic_in_kernel(vcpu))
2738 return data ? 1 : 0;
2740 vcpu->arch.apf.msr_en_val = data;
2742 if (!kvm_pv_async_pf_enabled(vcpu)) {
2743 kvm_clear_async_pf_completion_queue(vcpu);
2744 kvm_async_pf_hash_reset(vcpu);
2748 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2752 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2753 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2755 kvm_async_pf_wakeup_all(vcpu);
2760 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2762 /* Bits 8-63 are reserved */
2766 if (!lapic_in_kernel(vcpu))
2769 vcpu->arch.apf.msr_int_val = data;
2771 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2776 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2778 vcpu->arch.pv_time_enabled = false;
2779 vcpu->arch.time = 0;
2782 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2784 ++vcpu->stat.tlb_flush;
2785 kvm_x86_ops.tlb_flush_all(vcpu);
2788 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2790 ++vcpu->stat.tlb_flush;
2791 kvm_x86_ops.tlb_flush_guest(vcpu);
2794 static void record_steal_time(struct kvm_vcpu *vcpu)
2796 struct kvm_host_map map;
2797 struct kvm_steal_time *st;
2799 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2802 /* -EAGAIN is returned in atomic context so we can just return. */
2803 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2804 &map, &vcpu->arch.st.cache, false))
2808 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2811 * Doing a TLB flush here, on the guest's behalf, can avoid
2814 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2815 st->preempted & KVM_VCPU_FLUSH_TLB);
2816 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2817 kvm_vcpu_flush_tlb_guest(vcpu);
2819 vcpu->arch.st.preempted = 0;
2821 if (st->version & 1)
2822 st->version += 1; /* first time write, random junk */
2828 st->steal += current->sched_info.run_delay -
2829 vcpu->arch.st.last_steal;
2830 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2836 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2839 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2842 u32 msr = msr_info->index;
2843 u64 data = msr_info->data;
2846 case MSR_AMD64_NB_CFG:
2847 case MSR_IA32_UCODE_WRITE:
2848 case MSR_VM_HSAVE_PA:
2849 case MSR_AMD64_PATCH_LOADER:
2850 case MSR_AMD64_BU_CFG2:
2851 case MSR_AMD64_DC_CFG:
2852 case MSR_F15H_EX_CFG:
2855 case MSR_IA32_UCODE_REV:
2856 if (msr_info->host_initiated)
2857 vcpu->arch.microcode_version = data;
2859 case MSR_IA32_ARCH_CAPABILITIES:
2860 if (!msr_info->host_initiated)
2862 vcpu->arch.arch_capabilities = data;
2864 case MSR_IA32_PERF_CAPABILITIES: {
2865 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
2867 if (!msr_info->host_initiated)
2869 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
2871 if (data & ~msr_ent.data)
2874 vcpu->arch.perf_capabilities = data;
2879 return set_efer(vcpu, msr_info);
2881 data &= ~(u64)0x40; /* ignore flush filter disable */
2882 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2883 data &= ~(u64)0x8; /* ignore TLB cache disable */
2885 /* Handle McStatusWrEn */
2886 if (data == BIT_ULL(18)) {
2887 vcpu->arch.msr_hwcr = data;
2888 } else if (data != 0) {
2889 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2894 case MSR_FAM10H_MMIO_CONF_BASE:
2896 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2901 case MSR_IA32_DEBUGCTLMSR:
2903 /* We support the non-activated case already */
2905 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2906 /* Values other than LBR and BTF are vendor-specific,
2907 thus reserved and should throw a #GP */
2910 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2913 case 0x200 ... 0x2ff:
2914 return kvm_mtrr_set_msr(vcpu, msr, data);
2915 case MSR_IA32_APICBASE:
2916 return kvm_set_apic_base(vcpu, msr_info);
2917 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
2918 return kvm_x2apic_msr_write(vcpu, msr, data);
2919 case MSR_IA32_TSCDEADLINE:
2920 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2922 case MSR_IA32_TSC_ADJUST:
2923 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2924 if (!msr_info->host_initiated) {
2925 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2926 adjust_tsc_offset_guest(vcpu, adj);
2928 vcpu->arch.ia32_tsc_adjust_msr = data;
2931 case MSR_IA32_MISC_ENABLE:
2932 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2933 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2934 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2936 vcpu->arch.ia32_misc_enable_msr = data;
2937 kvm_update_cpuid_runtime(vcpu);
2939 vcpu->arch.ia32_misc_enable_msr = data;
2942 case MSR_IA32_SMBASE:
2943 if (!msr_info->host_initiated)
2945 vcpu->arch.smbase = data;
2947 case MSR_IA32_POWER_CTL:
2948 vcpu->arch.msr_ia32_power_ctl = data;
2951 kvm_write_tsc(vcpu, msr_info);
2954 if (!msr_info->host_initiated &&
2955 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2958 * KVM supports exposing PT to the guest, but does not support
2959 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
2960 * XSAVES/XRSTORS to save/restore PT MSRs.
2962 if (data & ~supported_xss)
2964 vcpu->arch.ia32_xss = data;
2967 if (!msr_info->host_initiated)
2969 vcpu->arch.smi_count = data;
2971 case MSR_KVM_WALL_CLOCK_NEW:
2972 case MSR_KVM_WALL_CLOCK:
2973 vcpu->kvm->arch.wall_clock = data;
2974 kvm_write_wall_clock(vcpu->kvm, data);
2976 case MSR_KVM_SYSTEM_TIME_NEW:
2977 case MSR_KVM_SYSTEM_TIME: {
2978 struct kvm_arch *ka = &vcpu->kvm->arch;
2980 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2981 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2983 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2984 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2986 ka->boot_vcpu_runs_old_kvmclock = tmp;
2989 vcpu->arch.time = data;
2990 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2992 /* we verify if the enable bit is set... */
2993 vcpu->arch.pv_time_enabled = false;
2997 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2998 &vcpu->arch.pv_time, data & ~1ULL,
2999 sizeof(struct pvclock_vcpu_time_info)))
3000 vcpu->arch.pv_time_enabled = true;
3004 case MSR_KVM_ASYNC_PF_EN:
3005 if (kvm_pv_enable_async_pf(vcpu, data))
3008 case MSR_KVM_ASYNC_PF_INT:
3009 if (kvm_pv_enable_async_pf_int(vcpu, data))
3012 case MSR_KVM_ASYNC_PF_ACK:
3014 vcpu->arch.apf.pageready_pending = false;
3015 kvm_check_async_pf_completion(vcpu);
3018 case MSR_KVM_STEAL_TIME:
3020 if (unlikely(!sched_info_on()))
3023 if (data & KVM_STEAL_RESERVED_MASK)
3026 vcpu->arch.st.msr_val = data;
3028 if (!(data & KVM_MSR_ENABLED))
3031 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3034 case MSR_KVM_PV_EOI_EN:
3035 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3039 case MSR_KVM_POLL_CONTROL:
3040 /* only enable bit supported */
3041 if (data & (-1ULL << 1))
3044 vcpu->arch.msr_kvm_poll_control = data;
3047 case MSR_IA32_MCG_CTL:
3048 case MSR_IA32_MCG_STATUS:
3049 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3050 return set_msr_mce(vcpu, msr_info);
3052 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3053 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3054 pr = true; /* fall through */
3055 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3056 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3057 if (kvm_pmu_is_valid_msr(vcpu, msr))
3058 return kvm_pmu_set_msr(vcpu, msr_info);
3060 if (pr || data != 0)
3061 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3062 "0x%x data 0x%llx\n", msr, data);
3064 case MSR_K7_CLK_CTL:
3066 * Ignore all writes to this no longer documented MSR.
3067 * Writes are only relevant for old K7 processors,
3068 * all pre-dating SVM, but a recommended workaround from
3069 * AMD for these chips. It is possible to specify the
3070 * affected processor models on the command line, hence
3071 * the need to ignore the workaround.
3074 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3075 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3076 case HV_X64_MSR_SYNDBG_OPTIONS:
3077 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3078 case HV_X64_MSR_CRASH_CTL:
3079 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3080 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3081 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3082 case HV_X64_MSR_TSC_EMULATION_STATUS:
3083 return kvm_hv_set_msr_common(vcpu, msr, data,
3084 msr_info->host_initiated);
3085 case MSR_IA32_BBL_CR_CTL3:
3086 /* Drop writes to this legacy MSR -- see rdmsr
3087 * counterpart for further detail.
3089 if (report_ignored_msrs)
3090 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3093 case MSR_AMD64_OSVW_ID_LENGTH:
3094 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3096 vcpu->arch.osvw.length = data;
3098 case MSR_AMD64_OSVW_STATUS:
3099 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3101 vcpu->arch.osvw.status = data;
3103 case MSR_PLATFORM_INFO:
3104 if (!msr_info->host_initiated ||
3105 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3106 cpuid_fault_enabled(vcpu)))
3108 vcpu->arch.msr_platform_info = data;
3110 case MSR_MISC_FEATURES_ENABLES:
3111 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3112 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3113 !supports_cpuid_fault(vcpu)))
3115 vcpu->arch.msr_misc_features_enables = data;
3118 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
3119 return xen_hvm_config(vcpu, data);
3120 if (kvm_pmu_is_valid_msr(vcpu, msr))
3121 return kvm_pmu_set_msr(vcpu, msr_info);
3122 return KVM_MSR_RET_INVALID;
3126 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3128 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3131 u64 mcg_cap = vcpu->arch.mcg_cap;
3132 unsigned bank_num = mcg_cap & 0xff;
3135 case MSR_IA32_P5_MC_ADDR:
3136 case MSR_IA32_P5_MC_TYPE:
3139 case MSR_IA32_MCG_CAP:
3140 data = vcpu->arch.mcg_cap;
3142 case MSR_IA32_MCG_CTL:
3143 if (!(mcg_cap & MCG_CTL_P) && !host)
3145 data = vcpu->arch.mcg_ctl;
3147 case MSR_IA32_MCG_STATUS:
3148 data = vcpu->arch.mcg_status;
3151 if (msr >= MSR_IA32_MC0_CTL &&
3152 msr < MSR_IA32_MCx_CTL(bank_num)) {
3153 u32 offset = array_index_nospec(
3154 msr - MSR_IA32_MC0_CTL,
3155 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3157 data = vcpu->arch.mce_banks[offset];
3166 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3168 switch (msr_info->index) {
3169 case MSR_IA32_PLATFORM_ID:
3170 case MSR_IA32_EBL_CR_POWERON:
3171 case MSR_IA32_DEBUGCTLMSR:
3172 case MSR_IA32_LASTBRANCHFROMIP:
3173 case MSR_IA32_LASTBRANCHTOIP:
3174 case MSR_IA32_LASTINTFROMIP:
3175 case MSR_IA32_LASTINTTOIP:
3177 case MSR_K8_TSEG_ADDR:
3178 case MSR_K8_TSEG_MASK:
3179 case MSR_VM_HSAVE_PA:
3180 case MSR_K8_INT_PENDING_MSG:
3181 case MSR_AMD64_NB_CFG:
3182 case MSR_FAM10H_MMIO_CONF_BASE:
3183 case MSR_AMD64_BU_CFG2:
3184 case MSR_IA32_PERF_CTL:
3185 case MSR_AMD64_DC_CFG:
3186 case MSR_F15H_EX_CFG:
3188 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3189 * limit) MSRs. Just return 0, as we do not want to expose the host
3190 * data here. Do not conditionalize this on CPUID, as KVM does not do
3191 * so for existing CPU-specific MSRs.
3193 case MSR_RAPL_POWER_UNIT:
3194 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3195 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3196 case MSR_PKG_ENERGY_STATUS: /* Total package */
3197 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3200 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3201 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3202 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3203 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3204 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3205 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3206 return kvm_pmu_get_msr(vcpu, msr_info);
3209 case MSR_IA32_UCODE_REV:
3210 msr_info->data = vcpu->arch.microcode_version;
3212 case MSR_IA32_ARCH_CAPABILITIES:
3213 if (!msr_info->host_initiated &&
3214 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3216 msr_info->data = vcpu->arch.arch_capabilities;
3218 case MSR_IA32_PERF_CAPABILITIES:
3219 if (!msr_info->host_initiated &&
3220 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3222 msr_info->data = vcpu->arch.perf_capabilities;
3224 case MSR_IA32_POWER_CTL:
3225 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3228 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3231 case 0x200 ... 0x2ff:
3232 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3233 case 0xcd: /* fsb frequency */
3237 * MSR_EBC_FREQUENCY_ID
3238 * Conservative value valid for even the basic CPU models.
3239 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3240 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3241 * and 266MHz for model 3, or 4. Set Core Clock
3242 * Frequency to System Bus Frequency Ratio to 1 (bits
3243 * 31:24) even though these are only valid for CPU
3244 * models > 2, however guests may end up dividing or
3245 * multiplying by zero otherwise.
3247 case MSR_EBC_FREQUENCY_ID:
3248 msr_info->data = 1 << 24;
3250 case MSR_IA32_APICBASE:
3251 msr_info->data = kvm_get_apic_base(vcpu);
3253 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3254 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3255 case MSR_IA32_TSCDEADLINE:
3256 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3258 case MSR_IA32_TSC_ADJUST:
3259 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3261 case MSR_IA32_MISC_ENABLE:
3262 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3264 case MSR_IA32_SMBASE:
3265 if (!msr_info->host_initiated)
3267 msr_info->data = vcpu->arch.smbase;
3270 msr_info->data = vcpu->arch.smi_count;
3272 case MSR_IA32_PERF_STATUS:
3273 /* TSC increment by tick */
3274 msr_info->data = 1000ULL;
3275 /* CPU multiplier */
3276 msr_info->data |= (((uint64_t)4ULL) << 40);
3279 msr_info->data = vcpu->arch.efer;
3281 case MSR_KVM_WALL_CLOCK:
3282 case MSR_KVM_WALL_CLOCK_NEW:
3283 msr_info->data = vcpu->kvm->arch.wall_clock;
3285 case MSR_KVM_SYSTEM_TIME:
3286 case MSR_KVM_SYSTEM_TIME_NEW:
3287 msr_info->data = vcpu->arch.time;
3289 case MSR_KVM_ASYNC_PF_EN:
3290 msr_info->data = vcpu->arch.apf.msr_en_val;
3292 case MSR_KVM_ASYNC_PF_INT:
3293 msr_info->data = vcpu->arch.apf.msr_int_val;
3295 case MSR_KVM_ASYNC_PF_ACK:
3298 case MSR_KVM_STEAL_TIME:
3299 msr_info->data = vcpu->arch.st.msr_val;
3301 case MSR_KVM_PV_EOI_EN:
3302 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3304 case MSR_KVM_POLL_CONTROL:
3305 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3307 case MSR_IA32_P5_MC_ADDR:
3308 case MSR_IA32_P5_MC_TYPE:
3309 case MSR_IA32_MCG_CAP:
3310 case MSR_IA32_MCG_CTL:
3311 case MSR_IA32_MCG_STATUS:
3312 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3313 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3314 msr_info->host_initiated);
3316 if (!msr_info->host_initiated &&
3317 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3319 msr_info->data = vcpu->arch.ia32_xss;
3321 case MSR_K7_CLK_CTL:
3323 * Provide expected ramp-up count for K7. All other
3324 * are set to zero, indicating minimum divisors for
3327 * This prevents guest kernels on AMD host with CPU
3328 * type 6, model 8 and higher from exploding due to
3329 * the rdmsr failing.
3331 msr_info->data = 0x20000000;
3333 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3334 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3335 case HV_X64_MSR_SYNDBG_OPTIONS:
3336 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3337 case HV_X64_MSR_CRASH_CTL:
3338 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3339 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3340 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3341 case HV_X64_MSR_TSC_EMULATION_STATUS:
3342 return kvm_hv_get_msr_common(vcpu,
3343 msr_info->index, &msr_info->data,
3344 msr_info->host_initiated);
3345 case MSR_IA32_BBL_CR_CTL3:
3346 /* This legacy MSR exists but isn't fully documented in current
3347 * silicon. It is however accessed by winxp in very narrow
3348 * scenarios where it sets bit #19, itself documented as
3349 * a "reserved" bit. Best effort attempt to source coherent
3350 * read data here should the balance of the register be
3351 * interpreted by the guest:
3353 * L2 cache control register 3: 64GB range, 256KB size,
3354 * enabled, latency 0x1, configured
3356 msr_info->data = 0xbe702111;
3358 case MSR_AMD64_OSVW_ID_LENGTH:
3359 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3361 msr_info->data = vcpu->arch.osvw.length;
3363 case MSR_AMD64_OSVW_STATUS:
3364 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3366 msr_info->data = vcpu->arch.osvw.status;
3368 case MSR_PLATFORM_INFO:
3369 if (!msr_info->host_initiated &&
3370 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3372 msr_info->data = vcpu->arch.msr_platform_info;
3374 case MSR_MISC_FEATURES_ENABLES:
3375 msr_info->data = vcpu->arch.msr_misc_features_enables;
3378 msr_info->data = vcpu->arch.msr_hwcr;
3381 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3382 return kvm_pmu_get_msr(vcpu, msr_info);
3383 return KVM_MSR_RET_INVALID;
3387 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3390 * Read or write a bunch of msrs. All parameters are kernel addresses.
3392 * @return number of msrs set successfully.
3394 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3395 struct kvm_msr_entry *entries,
3396 int (*do_msr)(struct kvm_vcpu *vcpu,
3397 unsigned index, u64 *data))
3401 for (i = 0; i < msrs->nmsrs; ++i)
3402 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3409 * Read or write a bunch of msrs. Parameters are user addresses.
3411 * @return number of msrs set successfully.
3413 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3414 int (*do_msr)(struct kvm_vcpu *vcpu,
3415 unsigned index, u64 *data),
3418 struct kvm_msrs msrs;
3419 struct kvm_msr_entry *entries;
3424 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3428 if (msrs.nmsrs >= MAX_IO_MSRS)
3431 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3432 entries = memdup_user(user_msrs->entries, size);
3433 if (IS_ERR(entries)) {
3434 r = PTR_ERR(entries);
3438 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3443 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3454 static inline bool kvm_can_mwait_in_guest(void)
3456 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3457 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3458 boot_cpu_has(X86_FEATURE_ARAT);
3461 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3466 case KVM_CAP_IRQCHIP:
3468 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3469 case KVM_CAP_SET_TSS_ADDR:
3470 case KVM_CAP_EXT_CPUID:
3471 case KVM_CAP_EXT_EMUL_CPUID:
3472 case KVM_CAP_CLOCKSOURCE:
3474 case KVM_CAP_NOP_IO_DELAY:
3475 case KVM_CAP_MP_STATE:
3476 case KVM_CAP_SYNC_MMU:
3477 case KVM_CAP_USER_NMI:
3478 case KVM_CAP_REINJECT_CONTROL:
3479 case KVM_CAP_IRQ_INJECT_STATUS:
3480 case KVM_CAP_IOEVENTFD:
3481 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3483 case KVM_CAP_PIT_STATE2:
3484 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3485 case KVM_CAP_XEN_HVM:
3486 case KVM_CAP_VCPU_EVENTS:
3487 case KVM_CAP_HYPERV:
3488 case KVM_CAP_HYPERV_VAPIC:
3489 case KVM_CAP_HYPERV_SPIN:
3490 case KVM_CAP_HYPERV_SYNIC:
3491 case KVM_CAP_HYPERV_SYNIC2:
3492 case KVM_CAP_HYPERV_VP_INDEX:
3493 case KVM_CAP_HYPERV_EVENTFD:
3494 case KVM_CAP_HYPERV_TLBFLUSH:
3495 case KVM_CAP_HYPERV_SEND_IPI:
3496 case KVM_CAP_HYPERV_CPUID:
3497 case KVM_CAP_PCI_SEGMENT:
3498 case KVM_CAP_DEBUGREGS:
3499 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3501 case KVM_CAP_ASYNC_PF:
3502 case KVM_CAP_ASYNC_PF_INT:
3503 case KVM_CAP_GET_TSC_KHZ:
3504 case KVM_CAP_KVMCLOCK_CTRL:
3505 case KVM_CAP_READONLY_MEM:
3506 case KVM_CAP_HYPERV_TIME:
3507 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3508 case KVM_CAP_TSC_DEADLINE_TIMER:
3509 case KVM_CAP_DISABLE_QUIRKS:
3510 case KVM_CAP_SET_BOOT_CPU_ID:
3511 case KVM_CAP_SPLIT_IRQCHIP:
3512 case KVM_CAP_IMMEDIATE_EXIT:
3513 case KVM_CAP_PMU_EVENT_FILTER:
3514 case KVM_CAP_GET_MSR_FEATURES:
3515 case KVM_CAP_MSR_PLATFORM_INFO:
3516 case KVM_CAP_EXCEPTION_PAYLOAD:
3517 case KVM_CAP_SET_GUEST_DEBUG:
3518 case KVM_CAP_LAST_CPU:
3521 case KVM_CAP_SYNC_REGS:
3522 r = KVM_SYNC_X86_VALID_FIELDS;
3524 case KVM_CAP_ADJUST_CLOCK:
3525 r = KVM_CLOCK_TSC_STABLE;
3527 case KVM_CAP_X86_DISABLE_EXITS:
3528 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3529 KVM_X86_DISABLE_EXITS_CSTATE;
3530 if(kvm_can_mwait_in_guest())
3531 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3533 case KVM_CAP_X86_SMM:
3534 /* SMBASE is usually relocated above 1M on modern chipsets,
3535 * and SMM handlers might indeed rely on 4G segment limits,
3536 * so do not report SMM to be available if real mode is
3537 * emulated via vm86 mode. Still, do not go to great lengths
3538 * to avoid userspace's usage of the feature, because it is a
3539 * fringe case that is not enabled except via specific settings
3540 * of the module parameters.
3542 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3545 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3547 case KVM_CAP_NR_VCPUS:
3548 r = KVM_SOFT_MAX_VCPUS;
3550 case KVM_CAP_MAX_VCPUS:
3553 case KVM_CAP_MAX_VCPU_ID:
3554 r = KVM_MAX_VCPU_ID;
3556 case KVM_CAP_PV_MMU: /* obsolete */
3560 r = KVM_MAX_MCE_BANKS;
3563 r = boot_cpu_has(X86_FEATURE_XSAVE);
3565 case KVM_CAP_TSC_CONTROL:
3566 r = kvm_has_tsc_control;
3568 case KVM_CAP_X2APIC_API:
3569 r = KVM_X2APIC_API_VALID_FLAGS;
3571 case KVM_CAP_NESTED_STATE:
3572 r = kvm_x86_ops.nested_ops->get_state ?
3573 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3575 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3576 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3578 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3579 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3581 case KVM_CAP_SMALLER_MAXPHYADDR:
3582 r = (int) allow_smaller_maxphyaddr;
3584 case KVM_CAP_STEAL_TIME:
3585 r = sched_info_on();
3594 long kvm_arch_dev_ioctl(struct file *filp,
3595 unsigned int ioctl, unsigned long arg)
3597 void __user *argp = (void __user *)arg;
3601 case KVM_GET_MSR_INDEX_LIST: {
3602 struct kvm_msr_list __user *user_msr_list = argp;
3603 struct kvm_msr_list msr_list;
3607 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3610 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3611 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3614 if (n < msr_list.nmsrs)
3617 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3618 num_msrs_to_save * sizeof(u32)))
3620 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3622 num_emulated_msrs * sizeof(u32)))
3627 case KVM_GET_SUPPORTED_CPUID:
3628 case KVM_GET_EMULATED_CPUID: {
3629 struct kvm_cpuid2 __user *cpuid_arg = argp;
3630 struct kvm_cpuid2 cpuid;
3633 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3636 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3642 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3647 case KVM_X86_GET_MCE_CAP_SUPPORTED:
3649 if (copy_to_user(argp, &kvm_mce_cap_supported,
3650 sizeof(kvm_mce_cap_supported)))
3654 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3655 struct kvm_msr_list __user *user_msr_list = argp;
3656 struct kvm_msr_list msr_list;
3660 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3663 msr_list.nmsrs = num_msr_based_features;
3664 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3667 if (n < msr_list.nmsrs)
3670 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3671 num_msr_based_features * sizeof(u32)))
3677 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3687 static void wbinvd_ipi(void *garbage)
3692 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3694 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3697 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3699 /* Address WBINVD may be executed by guest */
3700 if (need_emulate_wbinvd(vcpu)) {
3701 if (kvm_x86_ops.has_wbinvd_exit())
3702 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3703 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3704 smp_call_function_single(vcpu->cpu,
3705 wbinvd_ipi, NULL, 1);
3708 kvm_x86_ops.vcpu_load(vcpu, cpu);
3710 /* Save host pkru register if supported */
3711 vcpu->arch.host_pkru = read_pkru();
3713 /* Apply any externally detected TSC adjustments (due to suspend) */
3714 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3715 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3716 vcpu->arch.tsc_offset_adjustment = 0;
3717 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3720 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3721 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3722 rdtsc() - vcpu->arch.last_host_tsc;
3724 mark_tsc_unstable("KVM discovered backwards TSC");
3726 if (kvm_check_tsc_unstable()) {
3727 u64 offset = kvm_compute_tsc_offset(vcpu,
3728 vcpu->arch.last_guest_tsc);
3729 kvm_vcpu_write_tsc_offset(vcpu, offset);
3730 vcpu->arch.tsc_catchup = 1;
3733 if (kvm_lapic_hv_timer_in_use(vcpu))
3734 kvm_lapic_restart_hv_timer(vcpu);
3737 * On a host with synchronized TSC, there is no need to update
3738 * kvmclock on vcpu->cpu migration
3740 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3741 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3742 if (vcpu->cpu != cpu)
3743 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3747 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3750 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3752 struct kvm_host_map map;
3753 struct kvm_steal_time *st;
3755 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3758 if (vcpu->arch.st.preempted)
3761 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3762 &vcpu->arch.st.cache, true))
3766 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3768 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3770 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3773 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3777 if (vcpu->preempted)
3778 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
3781 * Disable page faults because we're in atomic context here.
3782 * kvm_write_guest_offset_cached() would call might_fault()
3783 * that relies on pagefault_disable() to tell if there's a
3784 * bug. NOTE: the write to guest memory may not go through if
3785 * during postcopy live migration or if there's heavy guest
3788 pagefault_disable();
3790 * kvm_memslots() will be called by
3791 * kvm_write_guest_offset_cached() so take the srcu lock.
3793 idx = srcu_read_lock(&vcpu->kvm->srcu);
3794 kvm_steal_time_set_preempted(vcpu);
3795 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3797 kvm_x86_ops.vcpu_put(vcpu);
3798 vcpu->arch.last_host_tsc = rdtsc();
3800 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3801 * on every vmexit, but if not, we might have a stale dr6 from the
3802 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3807 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3808 struct kvm_lapic_state *s)
3810 if (vcpu->arch.apicv_active)
3811 kvm_x86_ops.sync_pir_to_irr(vcpu);
3813 return kvm_apic_get_state(vcpu, s);
3816 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3817 struct kvm_lapic_state *s)
3821 r = kvm_apic_set_state(vcpu, s);
3824 update_cr8_intercept(vcpu);
3829 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3831 return (!lapic_in_kernel(vcpu) ||
3832 kvm_apic_accept_pic_intr(vcpu));
3836 * if userspace requested an interrupt window, check that the
3837 * interrupt window is open.
3839 * No need to exit to userspace if we already have an interrupt queued.
3841 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3843 return kvm_arch_interrupt_allowed(vcpu) &&
3844 !kvm_cpu_has_interrupt(vcpu) &&
3845 !kvm_event_needs_reinjection(vcpu) &&
3846 kvm_cpu_accept_dm_intr(vcpu);
3849 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3850 struct kvm_interrupt *irq)
3852 if (irq->irq >= KVM_NR_INTERRUPTS)
3855 if (!irqchip_in_kernel(vcpu->kvm)) {
3856 kvm_queue_interrupt(vcpu, irq->irq, false);
3857 kvm_make_request(KVM_REQ_EVENT, vcpu);
3862 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3863 * fail for in-kernel 8259.
3865 if (pic_in_kernel(vcpu->kvm))
3868 if (vcpu->arch.pending_external_vector != -1)
3871 vcpu->arch.pending_external_vector = irq->irq;
3872 kvm_make_request(KVM_REQ_EVENT, vcpu);
3876 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3878 kvm_inject_nmi(vcpu);
3883 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3885 kvm_make_request(KVM_REQ_SMI, vcpu);
3890 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3891 struct kvm_tpr_access_ctl *tac)
3895 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3899 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3903 unsigned bank_num = mcg_cap & 0xff, bank;
3906 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
3908 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3911 vcpu->arch.mcg_cap = mcg_cap;
3912 /* Init IA32_MCG_CTL to all 1s */
3913 if (mcg_cap & MCG_CTL_P)
3914 vcpu->arch.mcg_ctl = ~(u64)0;
3915 /* Init IA32_MCi_CTL to all 1s */
3916 for (bank = 0; bank < bank_num; bank++)
3917 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3919 kvm_x86_ops.setup_mce(vcpu);
3924 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3925 struct kvm_x86_mce *mce)
3927 u64 mcg_cap = vcpu->arch.mcg_cap;
3928 unsigned bank_num = mcg_cap & 0xff;
3929 u64 *banks = vcpu->arch.mce_banks;
3931 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3934 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3935 * reporting is disabled
3937 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3938 vcpu->arch.mcg_ctl != ~(u64)0)
3940 banks += 4 * mce->bank;
3942 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3943 * reporting is disabled for the bank
3945 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3947 if (mce->status & MCI_STATUS_UC) {
3948 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3949 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3950 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3953 if (banks[1] & MCI_STATUS_VAL)
3954 mce->status |= MCI_STATUS_OVER;
3955 banks[2] = mce->addr;
3956 banks[3] = mce->misc;
3957 vcpu->arch.mcg_status = mce->mcg_status;
3958 banks[1] = mce->status;
3959 kvm_queue_exception(vcpu, MC_VECTOR);
3960 } else if (!(banks[1] & MCI_STATUS_VAL)
3961 || !(banks[1] & MCI_STATUS_UC)) {
3962 if (banks[1] & MCI_STATUS_VAL)
3963 mce->status |= MCI_STATUS_OVER;
3964 banks[2] = mce->addr;
3965 banks[3] = mce->misc;
3966 banks[1] = mce->status;
3968 banks[1] |= MCI_STATUS_OVER;
3972 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3973 struct kvm_vcpu_events *events)
3978 * In guest mode, payload delivery should be deferred,
3979 * so that the L1 hypervisor can intercept #PF before
3980 * CR2 is modified (or intercept #DB before DR6 is
3981 * modified under nVMX). Unless the per-VM capability,
3982 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3983 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3984 * opportunistically defer the exception payload, deliver it if the
3985 * capability hasn't been requested before processing a
3986 * KVM_GET_VCPU_EVENTS.
3988 if (!vcpu->kvm->arch.exception_payload_enabled &&
3989 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3990 kvm_deliver_exception_payload(vcpu);
3993 * The API doesn't provide the instruction length for software
3994 * exceptions, so don't report them. As long as the guest RIP
3995 * isn't advanced, we should expect to encounter the exception
3998 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3999 events->exception.injected = 0;
4000 events->exception.pending = 0;
4002 events->exception.injected = vcpu->arch.exception.injected;
4003 events->exception.pending = vcpu->arch.exception.pending;
4005 * For ABI compatibility, deliberately conflate
4006 * pending and injected exceptions when
4007 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4009 if (!vcpu->kvm->arch.exception_payload_enabled)
4010 events->exception.injected |=
4011 vcpu->arch.exception.pending;
4013 events->exception.nr = vcpu->arch.exception.nr;
4014 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4015 events->exception.error_code = vcpu->arch.exception.error_code;
4016 events->exception_has_payload = vcpu->arch.exception.has_payload;
4017 events->exception_payload = vcpu->arch.exception.payload;
4019 events->interrupt.injected =
4020 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4021 events->interrupt.nr = vcpu->arch.interrupt.nr;
4022 events->interrupt.soft = 0;
4023 events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
4025 events->nmi.injected = vcpu->arch.nmi_injected;
4026 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4027 events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
4028 events->nmi.pad = 0;
4030 events->sipi_vector = 0; /* never valid when reporting to user space */
4032 events->smi.smm = is_smm(vcpu);
4033 events->smi.pending = vcpu->arch.smi_pending;
4034 events->smi.smm_inside_nmi =
4035 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4036 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4038 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4039 | KVM_VCPUEVENT_VALID_SHADOW
4040 | KVM_VCPUEVENT_VALID_SMM);
4041 if (vcpu->kvm->arch.exception_payload_enabled)
4042 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4044 memset(&events->reserved, 0, sizeof(events->reserved));
4047 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4049 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4050 struct kvm_vcpu_events *events)
4052 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4053 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4054 | KVM_VCPUEVENT_VALID_SHADOW
4055 | KVM_VCPUEVENT_VALID_SMM
4056 | KVM_VCPUEVENT_VALID_PAYLOAD))
4059 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4060 if (!vcpu->kvm->arch.exception_payload_enabled)
4062 if (events->exception.pending)
4063 events->exception.injected = 0;
4065 events->exception_has_payload = 0;
4067 events->exception.pending = 0;
4068 events->exception_has_payload = 0;
4071 if ((events->exception.injected || events->exception.pending) &&
4072 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4075 /* INITs are latched while in SMM */
4076 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4077 (events->smi.smm || events->smi.pending) &&
4078 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4082 vcpu->arch.exception.injected = events->exception.injected;
4083 vcpu->arch.exception.pending = events->exception.pending;
4084 vcpu->arch.exception.nr = events->exception.nr;
4085 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4086 vcpu->arch.exception.error_code = events->exception.error_code;
4087 vcpu->arch.exception.has_payload = events->exception_has_payload;
4088 vcpu->arch.exception.payload = events->exception_payload;
4090 vcpu->arch.interrupt.injected = events->interrupt.injected;
4091 vcpu->arch.interrupt.nr = events->interrupt.nr;
4092 vcpu->arch.interrupt.soft = events->interrupt.soft;
4093 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4094 kvm_x86_ops.set_interrupt_shadow(vcpu,
4095 events->interrupt.shadow);
4097 vcpu->arch.nmi_injected = events->nmi.injected;
4098 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4099 vcpu->arch.nmi_pending = events->nmi.pending;
4100 kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
4102 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4103 lapic_in_kernel(vcpu))
4104 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4106 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4107 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4108 if (events->smi.smm)
4109 vcpu->arch.hflags |= HF_SMM_MASK;
4111 vcpu->arch.hflags &= ~HF_SMM_MASK;
4112 kvm_smm_changed(vcpu);
4115 vcpu->arch.smi_pending = events->smi.pending;
4117 if (events->smi.smm) {
4118 if (events->smi.smm_inside_nmi)
4119 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4121 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4124 if (lapic_in_kernel(vcpu)) {
4125 if (events->smi.latched_init)
4126 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4128 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4132 kvm_make_request(KVM_REQ_EVENT, vcpu);
4137 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4138 struct kvm_debugregs *dbgregs)
4142 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4143 kvm_get_dr(vcpu, 6, &val);
4145 dbgregs->dr7 = vcpu->arch.dr7;
4147 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4150 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4151 struct kvm_debugregs *dbgregs)
4156 if (dbgregs->dr6 & ~0xffffffffull)
4158 if (dbgregs->dr7 & ~0xffffffffull)
4161 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4162 kvm_update_dr0123(vcpu);
4163 vcpu->arch.dr6 = dbgregs->dr6;
4164 vcpu->arch.dr7 = dbgregs->dr7;
4165 kvm_update_dr7(vcpu);
4170 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4172 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4174 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4175 u64 xstate_bv = xsave->header.xfeatures;
4179 * Copy legacy XSAVE area, to avoid complications with CPUID
4180 * leaves 0 and 1 in the loop below.
4182 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4185 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4186 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4189 * Copy each region from the possibly compacted offset to the
4190 * non-compacted offset.
4192 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4194 u64 xfeature_mask = valid & -valid;
4195 int xfeature_nr = fls64(xfeature_mask) - 1;
4196 void *src = get_xsave_addr(xsave, xfeature_nr);
4199 u32 size, offset, ecx, edx;
4200 cpuid_count(XSTATE_CPUID, xfeature_nr,
4201 &size, &offset, &ecx, &edx);
4202 if (xfeature_nr == XFEATURE_PKRU)
4203 memcpy(dest + offset, &vcpu->arch.pkru,
4204 sizeof(vcpu->arch.pkru));
4206 memcpy(dest + offset, src, size);
4210 valid -= xfeature_mask;
4214 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4216 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4217 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4221 * Copy legacy XSAVE area, to avoid complications with CPUID
4222 * leaves 0 and 1 in the loop below.
4224 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4226 /* Set XSTATE_BV and possibly XCOMP_BV. */
4227 xsave->header.xfeatures = xstate_bv;
4228 if (boot_cpu_has(X86_FEATURE_XSAVES))
4229 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4232 * Copy each region from the non-compacted offset to the
4233 * possibly compacted offset.
4235 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4237 u64 xfeature_mask = valid & -valid;
4238 int xfeature_nr = fls64(xfeature_mask) - 1;
4239 void *dest = get_xsave_addr(xsave, xfeature_nr);
4242 u32 size, offset, ecx, edx;
4243 cpuid_count(XSTATE_CPUID, xfeature_nr,
4244 &size, &offset, &ecx, &edx);
4245 if (xfeature_nr == XFEATURE_PKRU)
4246 memcpy(&vcpu->arch.pkru, src + offset,
4247 sizeof(vcpu->arch.pkru));
4249 memcpy(dest, src + offset, size);
4252 valid -= xfeature_mask;
4256 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4257 struct kvm_xsave *guest_xsave)
4259 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4260 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4261 fill_xsave((u8 *) guest_xsave->region, vcpu);
4263 memcpy(guest_xsave->region,
4264 &vcpu->arch.guest_fpu->state.fxsave,
4265 sizeof(struct fxregs_state));
4266 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4267 XFEATURE_MASK_FPSSE;
4271 #define XSAVE_MXCSR_OFFSET 24
4273 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4274 struct kvm_xsave *guest_xsave)
4277 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4278 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4280 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4282 * Here we allow setting states that are not present in
4283 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4284 * with old userspace.
4286 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4288 load_xsave(vcpu, (u8 *)guest_xsave->region);
4290 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4291 mxcsr & ~mxcsr_feature_mask)
4293 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4294 guest_xsave->region, sizeof(struct fxregs_state));
4299 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4300 struct kvm_xcrs *guest_xcrs)
4302 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4303 guest_xcrs->nr_xcrs = 0;
4307 guest_xcrs->nr_xcrs = 1;
4308 guest_xcrs->flags = 0;
4309 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4310 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4313 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4314 struct kvm_xcrs *guest_xcrs)
4318 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4321 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4324 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4325 /* Only support XCR0 currently */
4326 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4327 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4328 guest_xcrs->xcrs[i].value);
4337 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4338 * stopped by the hypervisor. This function will be called from the host only.
4339 * EINVAL is returned when the host attempts to set the flag for a guest that
4340 * does not support pv clocks.
4342 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4344 if (!vcpu->arch.pv_time_enabled)
4346 vcpu->arch.pvclock_set_guest_stopped_request = true;
4347 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4351 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4352 struct kvm_enable_cap *cap)
4355 uint16_t vmcs_version;
4356 void __user *user_ptr;
4362 case KVM_CAP_HYPERV_SYNIC2:
4367 case KVM_CAP_HYPERV_SYNIC:
4368 if (!irqchip_in_kernel(vcpu->kvm))
4370 return kvm_hv_activate_synic(vcpu, cap->cap ==
4371 KVM_CAP_HYPERV_SYNIC2);
4372 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4373 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4375 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4377 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4378 if (copy_to_user(user_ptr, &vmcs_version,
4379 sizeof(vmcs_version)))
4383 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4384 if (!kvm_x86_ops.enable_direct_tlbflush)
4387 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4394 long kvm_arch_vcpu_ioctl(struct file *filp,
4395 unsigned int ioctl, unsigned long arg)
4397 struct kvm_vcpu *vcpu = filp->private_data;
4398 void __user *argp = (void __user *)arg;
4401 struct kvm_lapic_state *lapic;
4402 struct kvm_xsave *xsave;
4403 struct kvm_xcrs *xcrs;
4411 case KVM_GET_LAPIC: {
4413 if (!lapic_in_kernel(vcpu))
4415 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4416 GFP_KERNEL_ACCOUNT);
4421 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4425 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4430 case KVM_SET_LAPIC: {
4432 if (!lapic_in_kernel(vcpu))
4434 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4435 if (IS_ERR(u.lapic)) {
4436 r = PTR_ERR(u.lapic);
4440 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4443 case KVM_INTERRUPT: {
4444 struct kvm_interrupt irq;
4447 if (copy_from_user(&irq, argp, sizeof(irq)))
4449 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4453 r = kvm_vcpu_ioctl_nmi(vcpu);
4457 r = kvm_vcpu_ioctl_smi(vcpu);
4460 case KVM_SET_CPUID: {
4461 struct kvm_cpuid __user *cpuid_arg = argp;
4462 struct kvm_cpuid cpuid;
4465 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4467 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4470 case KVM_SET_CPUID2: {
4471 struct kvm_cpuid2 __user *cpuid_arg = argp;
4472 struct kvm_cpuid2 cpuid;
4475 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4477 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4478 cpuid_arg->entries);
4481 case KVM_GET_CPUID2: {
4482 struct kvm_cpuid2 __user *cpuid_arg = argp;
4483 struct kvm_cpuid2 cpuid;
4486 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4488 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4489 cpuid_arg->entries);
4493 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4498 case KVM_GET_MSRS: {
4499 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4500 r = msr_io(vcpu, argp, do_get_msr, 1);
4501 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4504 case KVM_SET_MSRS: {
4505 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4506 r = msr_io(vcpu, argp, do_set_msr, 0);
4507 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4510 case KVM_TPR_ACCESS_REPORTING: {
4511 struct kvm_tpr_access_ctl tac;
4514 if (copy_from_user(&tac, argp, sizeof(tac)))
4516 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4520 if (copy_to_user(argp, &tac, sizeof(tac)))
4525 case KVM_SET_VAPIC_ADDR: {
4526 struct kvm_vapic_addr va;
4530 if (!lapic_in_kernel(vcpu))
4533 if (copy_from_user(&va, argp, sizeof(va)))
4535 idx = srcu_read_lock(&vcpu->kvm->srcu);
4536 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4537 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4540 case KVM_X86_SETUP_MCE: {
4544 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4546 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4549 case KVM_X86_SET_MCE: {
4550 struct kvm_x86_mce mce;
4553 if (copy_from_user(&mce, argp, sizeof(mce)))
4555 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4558 case KVM_GET_VCPU_EVENTS: {
4559 struct kvm_vcpu_events events;
4561 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4564 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4569 case KVM_SET_VCPU_EVENTS: {
4570 struct kvm_vcpu_events events;
4573 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4576 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4579 case KVM_GET_DEBUGREGS: {
4580 struct kvm_debugregs dbgregs;
4582 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4585 if (copy_to_user(argp, &dbgregs,
4586 sizeof(struct kvm_debugregs)))
4591 case KVM_SET_DEBUGREGS: {
4592 struct kvm_debugregs dbgregs;
4595 if (copy_from_user(&dbgregs, argp,
4596 sizeof(struct kvm_debugregs)))
4599 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4602 case KVM_GET_XSAVE: {
4603 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4608 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4611 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4616 case KVM_SET_XSAVE: {
4617 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4618 if (IS_ERR(u.xsave)) {
4619 r = PTR_ERR(u.xsave);
4623 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4626 case KVM_GET_XCRS: {
4627 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4632 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4635 if (copy_to_user(argp, u.xcrs,
4636 sizeof(struct kvm_xcrs)))
4641 case KVM_SET_XCRS: {
4642 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4643 if (IS_ERR(u.xcrs)) {
4644 r = PTR_ERR(u.xcrs);
4648 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4651 case KVM_SET_TSC_KHZ: {
4655 user_tsc_khz = (u32)arg;
4657 if (kvm_has_tsc_control &&
4658 user_tsc_khz >= kvm_max_guest_tsc_khz)
4661 if (user_tsc_khz == 0)
4662 user_tsc_khz = tsc_khz;
4664 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4669 case KVM_GET_TSC_KHZ: {
4670 r = vcpu->arch.virtual_tsc_khz;
4673 case KVM_KVMCLOCK_CTRL: {
4674 r = kvm_set_guest_paused(vcpu);
4677 case KVM_ENABLE_CAP: {
4678 struct kvm_enable_cap cap;
4681 if (copy_from_user(&cap, argp, sizeof(cap)))
4683 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4686 case KVM_GET_NESTED_STATE: {
4687 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4691 if (!kvm_x86_ops.nested_ops->get_state)
4694 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4696 if (get_user(user_data_size, &user_kvm_nested_state->size))
4699 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4704 if (r > user_data_size) {
4705 if (put_user(r, &user_kvm_nested_state->size))
4715 case KVM_SET_NESTED_STATE: {
4716 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4717 struct kvm_nested_state kvm_state;
4721 if (!kvm_x86_ops.nested_ops->set_state)
4725 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4729 if (kvm_state.size < sizeof(kvm_state))
4732 if (kvm_state.flags &
4733 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4734 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
4735 | KVM_STATE_NESTED_GIF_SET))
4738 /* nested_run_pending implies guest_mode. */
4739 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4740 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4743 idx = srcu_read_lock(&vcpu->kvm->srcu);
4744 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
4745 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4748 case KVM_GET_SUPPORTED_HV_CPUID: {
4749 struct kvm_cpuid2 __user *cpuid_arg = argp;
4750 struct kvm_cpuid2 cpuid;
4753 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4756 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4757 cpuid_arg->entries);
4762 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4777 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4779 return VM_FAULT_SIGBUS;
4782 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4786 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4788 ret = kvm_x86_ops.set_tss_addr(kvm, addr);
4792 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4795 return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
4798 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4799 unsigned long kvm_nr_mmu_pages)
4801 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4804 mutex_lock(&kvm->slots_lock);
4806 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4807 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4809 mutex_unlock(&kvm->slots_lock);
4813 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4815 return kvm->arch.n_max_mmu_pages;
4818 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4820 struct kvm_pic *pic = kvm->arch.vpic;
4824 switch (chip->chip_id) {
4825 case KVM_IRQCHIP_PIC_MASTER:
4826 memcpy(&chip->chip.pic, &pic->pics[0],
4827 sizeof(struct kvm_pic_state));
4829 case KVM_IRQCHIP_PIC_SLAVE:
4830 memcpy(&chip->chip.pic, &pic->pics[1],
4831 sizeof(struct kvm_pic_state));
4833 case KVM_IRQCHIP_IOAPIC:
4834 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4843 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4845 struct kvm_pic *pic = kvm->arch.vpic;
4849 switch (chip->chip_id) {
4850 case KVM_IRQCHIP_PIC_MASTER:
4851 spin_lock(&pic->lock);
4852 memcpy(&pic->pics[0], &chip->chip.pic,
4853 sizeof(struct kvm_pic_state));
4854 spin_unlock(&pic->lock);
4856 case KVM_IRQCHIP_PIC_SLAVE:
4857 spin_lock(&pic->lock);
4858 memcpy(&pic->pics[1], &chip->chip.pic,
4859 sizeof(struct kvm_pic_state));
4860 spin_unlock(&pic->lock);
4862 case KVM_IRQCHIP_IOAPIC:
4863 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4869 kvm_pic_update_irq(pic);
4873 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4875 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4877 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4879 mutex_lock(&kps->lock);
4880 memcpy(ps, &kps->channels, sizeof(*ps));
4881 mutex_unlock(&kps->lock);
4885 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4888 struct kvm_pit *pit = kvm->arch.vpit;
4890 mutex_lock(&pit->pit_state.lock);
4891 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4892 for (i = 0; i < 3; i++)
4893 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4894 mutex_unlock(&pit->pit_state.lock);
4898 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4900 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4901 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4902 sizeof(ps->channels));
4903 ps->flags = kvm->arch.vpit->pit_state.flags;
4904 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4905 memset(&ps->reserved, 0, sizeof(ps->reserved));
4909 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4913 u32 prev_legacy, cur_legacy;
4914 struct kvm_pit *pit = kvm->arch.vpit;
4916 mutex_lock(&pit->pit_state.lock);
4917 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4918 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4919 if (!prev_legacy && cur_legacy)
4921 memcpy(&pit->pit_state.channels, &ps->channels,
4922 sizeof(pit->pit_state.channels));
4923 pit->pit_state.flags = ps->flags;
4924 for (i = 0; i < 3; i++)
4925 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4927 mutex_unlock(&pit->pit_state.lock);
4931 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4932 struct kvm_reinject_control *control)
4934 struct kvm_pit *pit = kvm->arch.vpit;
4936 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4937 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4938 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4940 mutex_lock(&pit->pit_state.lock);
4941 kvm_pit_set_reinject(pit, control->pit_reinject);
4942 mutex_unlock(&pit->pit_state.lock);
4947 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
4950 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4952 if (kvm_x86_ops.flush_log_dirty)
4953 kvm_x86_ops.flush_log_dirty(kvm);
4956 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4959 if (!irqchip_in_kernel(kvm))
4962 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4963 irq_event->irq, irq_event->level,
4968 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4969 struct kvm_enable_cap *cap)
4977 case KVM_CAP_DISABLE_QUIRKS:
4978 kvm->arch.disabled_quirks = cap->args[0];
4981 case KVM_CAP_SPLIT_IRQCHIP: {
4982 mutex_lock(&kvm->lock);
4984 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4985 goto split_irqchip_unlock;
4987 if (irqchip_in_kernel(kvm))
4988 goto split_irqchip_unlock;
4989 if (kvm->created_vcpus)
4990 goto split_irqchip_unlock;
4991 r = kvm_setup_empty_irq_routing(kvm);
4993 goto split_irqchip_unlock;
4994 /* Pairs with irqchip_in_kernel. */
4996 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4997 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4999 split_irqchip_unlock:
5000 mutex_unlock(&kvm->lock);
5003 case KVM_CAP_X2APIC_API:
5005 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5008 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5009 kvm->arch.x2apic_format = true;
5010 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5011 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5015 case KVM_CAP_X86_DISABLE_EXITS:
5017 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5020 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5021 kvm_can_mwait_in_guest())
5022 kvm->arch.mwait_in_guest = true;
5023 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5024 kvm->arch.hlt_in_guest = true;
5025 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5026 kvm->arch.pause_in_guest = true;
5027 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5028 kvm->arch.cstate_in_guest = true;
5031 case KVM_CAP_MSR_PLATFORM_INFO:
5032 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5035 case KVM_CAP_EXCEPTION_PAYLOAD:
5036 kvm->arch.exception_payload_enabled = cap->args[0];
5046 long kvm_arch_vm_ioctl(struct file *filp,
5047 unsigned int ioctl, unsigned long arg)
5049 struct kvm *kvm = filp->private_data;
5050 void __user *argp = (void __user *)arg;
5053 * This union makes it completely explicit to gcc-3.x
5054 * that these two variables' stack usage should be
5055 * combined, not added together.
5058 struct kvm_pit_state ps;
5059 struct kvm_pit_state2 ps2;
5060 struct kvm_pit_config pit_config;
5064 case KVM_SET_TSS_ADDR:
5065 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5067 case KVM_SET_IDENTITY_MAP_ADDR: {
5070 mutex_lock(&kvm->lock);
5072 if (kvm->created_vcpus)
5073 goto set_identity_unlock;
5075 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5076 goto set_identity_unlock;
5077 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5078 set_identity_unlock:
5079 mutex_unlock(&kvm->lock);
5082 case KVM_SET_NR_MMU_PAGES:
5083 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5085 case KVM_GET_NR_MMU_PAGES:
5086 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5088 case KVM_CREATE_IRQCHIP: {
5089 mutex_lock(&kvm->lock);
5092 if (irqchip_in_kernel(kvm))
5093 goto create_irqchip_unlock;
5096 if (kvm->created_vcpus)
5097 goto create_irqchip_unlock;
5099 r = kvm_pic_init(kvm);
5101 goto create_irqchip_unlock;
5103 r = kvm_ioapic_init(kvm);
5105 kvm_pic_destroy(kvm);
5106 goto create_irqchip_unlock;
5109 r = kvm_setup_default_irq_routing(kvm);
5111 kvm_ioapic_destroy(kvm);
5112 kvm_pic_destroy(kvm);
5113 goto create_irqchip_unlock;
5115 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5117 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5118 create_irqchip_unlock:
5119 mutex_unlock(&kvm->lock);
5122 case KVM_CREATE_PIT:
5123 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5125 case KVM_CREATE_PIT2:
5127 if (copy_from_user(&u.pit_config, argp,
5128 sizeof(struct kvm_pit_config)))
5131 mutex_lock(&kvm->lock);
5134 goto create_pit_unlock;
5136 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5140 mutex_unlock(&kvm->lock);
5142 case KVM_GET_IRQCHIP: {
5143 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5144 struct kvm_irqchip *chip;
5146 chip = memdup_user(argp, sizeof(*chip));
5153 if (!irqchip_kernel(kvm))
5154 goto get_irqchip_out;
5155 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5157 goto get_irqchip_out;
5159 if (copy_to_user(argp, chip, sizeof(*chip)))
5160 goto get_irqchip_out;
5166 case KVM_SET_IRQCHIP: {
5167 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5168 struct kvm_irqchip *chip;
5170 chip = memdup_user(argp, sizeof(*chip));
5177 if (!irqchip_kernel(kvm))
5178 goto set_irqchip_out;
5179 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5186 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5189 if (!kvm->arch.vpit)
5191 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5195 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5202 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5204 mutex_lock(&kvm->lock);
5206 if (!kvm->arch.vpit)
5208 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5210 mutex_unlock(&kvm->lock);
5213 case KVM_GET_PIT2: {
5215 if (!kvm->arch.vpit)
5217 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5221 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5226 case KVM_SET_PIT2: {
5228 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5230 mutex_lock(&kvm->lock);
5232 if (!kvm->arch.vpit)
5234 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5236 mutex_unlock(&kvm->lock);
5239 case KVM_REINJECT_CONTROL: {
5240 struct kvm_reinject_control control;
5242 if (copy_from_user(&control, argp, sizeof(control)))
5245 if (!kvm->arch.vpit)
5247 r = kvm_vm_ioctl_reinject(kvm, &control);
5250 case KVM_SET_BOOT_CPU_ID:
5252 mutex_lock(&kvm->lock);
5253 if (kvm->created_vcpus)
5256 kvm->arch.bsp_vcpu_id = arg;
5257 mutex_unlock(&kvm->lock);
5259 case KVM_XEN_HVM_CONFIG: {
5260 struct kvm_xen_hvm_config xhc;
5262 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5267 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5271 case KVM_SET_CLOCK: {
5272 struct kvm_clock_data user_ns;
5276 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5285 * TODO: userspace has to take care of races with VCPU_RUN, so
5286 * kvm_gen_update_masterclock() can be cut down to locked
5287 * pvclock_update_vm_gtod_copy().
5289 kvm_gen_update_masterclock(kvm);
5290 now_ns = get_kvmclock_ns(kvm);
5291 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5292 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5295 case KVM_GET_CLOCK: {
5296 struct kvm_clock_data user_ns;
5299 now_ns = get_kvmclock_ns(kvm);
5300 user_ns.clock = now_ns;
5301 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5302 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5305 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5310 case KVM_MEMORY_ENCRYPT_OP: {
5312 if (kvm_x86_ops.mem_enc_op)
5313 r = kvm_x86_ops.mem_enc_op(kvm, argp);
5316 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5317 struct kvm_enc_region region;
5320 if (copy_from_user(®ion, argp, sizeof(region)))
5324 if (kvm_x86_ops.mem_enc_reg_region)
5325 r = kvm_x86_ops.mem_enc_reg_region(kvm, ®ion);
5328 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5329 struct kvm_enc_region region;
5332 if (copy_from_user(®ion, argp, sizeof(region)))
5336 if (kvm_x86_ops.mem_enc_unreg_region)
5337 r = kvm_x86_ops.mem_enc_unreg_region(kvm, ®ion);
5340 case KVM_HYPERV_EVENTFD: {
5341 struct kvm_hyperv_eventfd hvevfd;
5344 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5346 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5349 case KVM_SET_PMU_EVENT_FILTER:
5350 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5359 static void kvm_init_msr_list(void)
5361 struct x86_pmu_capability x86_pmu;
5365 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5366 "Please update the fixed PMCs in msrs_to_saved_all[]");
5368 perf_get_x86_pmu_capability(&x86_pmu);
5370 num_msrs_to_save = 0;
5371 num_emulated_msrs = 0;
5372 num_msr_based_features = 0;
5374 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5375 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5379 * Even MSRs that are valid in the host may not be exposed
5380 * to the guests in some cases.
5382 switch (msrs_to_save_all[i]) {
5383 case MSR_IA32_BNDCFGS:
5384 if (!kvm_mpx_supported())
5388 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5391 case MSR_IA32_UMWAIT_CONTROL:
5392 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5395 case MSR_IA32_RTIT_CTL:
5396 case MSR_IA32_RTIT_STATUS:
5397 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5400 case MSR_IA32_RTIT_CR3_MATCH:
5401 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5402 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5405 case MSR_IA32_RTIT_OUTPUT_BASE:
5406 case MSR_IA32_RTIT_OUTPUT_MASK:
5407 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5408 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5409 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5412 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5413 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5414 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5415 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5418 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5419 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5420 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5423 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5424 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5425 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5432 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5435 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5436 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5439 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5442 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5443 struct kvm_msr_entry msr;
5445 msr.index = msr_based_features_all[i];
5446 if (kvm_get_msr_feature(&msr))
5449 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5453 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5461 if (!(lapic_in_kernel(vcpu) &&
5462 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5463 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5474 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5481 if (!(lapic_in_kernel(vcpu) &&
5482 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5484 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5486 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5496 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5497 struct kvm_segment *var, int seg)
5499 kvm_x86_ops.set_segment(vcpu, var, seg);
5502 void kvm_get_segment(struct kvm_vcpu *vcpu,
5503 struct kvm_segment *var, int seg)
5505 kvm_x86_ops.get_segment(vcpu, var, seg);
5508 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5509 struct x86_exception *exception)
5513 BUG_ON(!mmu_is_nested(vcpu));
5515 /* NPT walks are always user-walks */
5516 access |= PFERR_USER_MASK;
5517 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5522 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5523 struct x86_exception *exception)
5525 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5526 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5529 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5530 struct x86_exception *exception)
5532 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5533 access |= PFERR_FETCH_MASK;
5534 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5537 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5538 struct x86_exception *exception)
5540 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5541 access |= PFERR_WRITE_MASK;
5542 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5545 /* uses this to access any guest's mapped memory without checking CPL */
5546 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5547 struct x86_exception *exception)
5549 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5552 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5553 struct kvm_vcpu *vcpu, u32 access,
5554 struct x86_exception *exception)
5557 int r = X86EMUL_CONTINUE;
5560 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5562 unsigned offset = addr & (PAGE_SIZE-1);
5563 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5566 if (gpa == UNMAPPED_GVA)
5567 return X86EMUL_PROPAGATE_FAULT;
5568 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5571 r = X86EMUL_IO_NEEDED;
5583 /* used for instruction fetching */
5584 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5585 gva_t addr, void *val, unsigned int bytes,
5586 struct x86_exception *exception)
5588 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5589 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5593 /* Inline kvm_read_guest_virt_helper for speed. */
5594 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5596 if (unlikely(gpa == UNMAPPED_GVA))
5597 return X86EMUL_PROPAGATE_FAULT;
5599 offset = addr & (PAGE_SIZE-1);
5600 if (WARN_ON(offset + bytes > PAGE_SIZE))
5601 bytes = (unsigned)PAGE_SIZE - offset;
5602 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5604 if (unlikely(ret < 0))
5605 return X86EMUL_IO_NEEDED;
5607 return X86EMUL_CONTINUE;
5610 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5611 gva_t addr, void *val, unsigned int bytes,
5612 struct x86_exception *exception)
5614 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5617 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5618 * is returned, but our callers are not ready for that and they blindly
5619 * call kvm_inject_page_fault. Ensure that they at least do not leak
5620 * uninitialized kernel stack memory into cr2 and error code.
5622 memset(exception, 0, sizeof(*exception));
5623 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5626 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5628 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5629 gva_t addr, void *val, unsigned int bytes,
5630 struct x86_exception *exception, bool system)
5632 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5635 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5636 access |= PFERR_USER_MASK;
5638 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5641 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5642 unsigned long addr, void *val, unsigned int bytes)
5644 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5645 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5647 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5650 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5651 struct kvm_vcpu *vcpu, u32 access,
5652 struct x86_exception *exception)
5655 int r = X86EMUL_CONTINUE;
5658 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5661 unsigned offset = addr & (PAGE_SIZE-1);
5662 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5665 if (gpa == UNMAPPED_GVA)
5666 return X86EMUL_PROPAGATE_FAULT;
5667 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5669 r = X86EMUL_IO_NEEDED;
5681 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5682 unsigned int bytes, struct x86_exception *exception,
5685 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5686 u32 access = PFERR_WRITE_MASK;
5688 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5689 access |= PFERR_USER_MASK;
5691 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5695 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5696 unsigned int bytes, struct x86_exception *exception)
5698 /* kvm_write_guest_virt_system can pull in tons of pages. */
5699 vcpu->arch.l1tf_flush_l1d = true;
5701 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5702 PFERR_WRITE_MASK, exception);
5704 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5706 int handle_ud(struct kvm_vcpu *vcpu)
5708 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5709 int emul_type = EMULTYPE_TRAP_UD;
5710 char sig[5]; /* ud2; .ascii "kvm" */
5711 struct x86_exception e;
5713 if (force_emulation_prefix &&
5714 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5715 sig, sizeof(sig), &e) == 0 &&
5716 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5717 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5718 emul_type = EMULTYPE_TRAP_UD_FORCED;
5721 return kvm_emulate_instruction(vcpu, emul_type);
5723 EXPORT_SYMBOL_GPL(handle_ud);
5725 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5726 gpa_t gpa, bool write)
5728 /* For APIC access vmexit */
5729 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5732 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5733 trace_vcpu_match_mmio(gva, gpa, write, true);
5740 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5741 gpa_t *gpa, struct x86_exception *exception,
5744 u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5745 | (write ? PFERR_WRITE_MASK : 0);
5748 * currently PKRU is only applied to ept enabled guest so
5749 * there is no pkey in EPT page table for L1 guest or EPT
5750 * shadow page table for L2 guest.
5752 if (vcpu_match_mmio_gva(vcpu, gva)
5753 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5754 vcpu->arch.mmio_access, 0, access)) {
5755 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5756 (gva & (PAGE_SIZE - 1));
5757 trace_vcpu_match_mmio(gva, *gpa, write, false);
5761 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5763 if (*gpa == UNMAPPED_GVA)
5766 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5769 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5770 const void *val, int bytes)
5774 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5777 kvm_page_track_write(vcpu, gpa, val, bytes);
5781 struct read_write_emulator_ops {
5782 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5784 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5785 void *val, int bytes);
5786 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5787 int bytes, void *val);
5788 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5789 void *val, int bytes);
5793 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5795 if (vcpu->mmio_read_completed) {
5796 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5797 vcpu->mmio_fragments[0].gpa, val);
5798 vcpu->mmio_read_completed = 0;
5805 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5806 void *val, int bytes)
5808 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5811 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5812 void *val, int bytes)
5814 return emulator_write_phys(vcpu, gpa, val, bytes);
5817 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5819 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5820 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5823 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5824 void *val, int bytes)
5826 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5827 return X86EMUL_IO_NEEDED;
5830 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5831 void *val, int bytes)
5833 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5835 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5836 return X86EMUL_CONTINUE;
5839 static const struct read_write_emulator_ops read_emultor = {
5840 .read_write_prepare = read_prepare,
5841 .read_write_emulate = read_emulate,
5842 .read_write_mmio = vcpu_mmio_read,
5843 .read_write_exit_mmio = read_exit_mmio,
5846 static const struct read_write_emulator_ops write_emultor = {
5847 .read_write_emulate = write_emulate,
5848 .read_write_mmio = write_mmio,
5849 .read_write_exit_mmio = write_exit_mmio,
5853 static int emulator_read_write_onepage(unsigned long addr, void *val,
5855 struct x86_exception *exception,
5856 struct kvm_vcpu *vcpu,
5857 const struct read_write_emulator_ops *ops)
5861 bool write = ops->write;
5862 struct kvm_mmio_fragment *frag;
5863 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
5866 * If the exit was due to a NPF we may already have a GPA.
5867 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5868 * Note, this cannot be used on string operations since string
5869 * operation using rep will only have the initial GPA from the NPF
5872 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
5873 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
5874 gpa = ctxt->gpa_val;
5875 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5877 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5879 return X86EMUL_PROPAGATE_FAULT;
5882 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5883 return X86EMUL_CONTINUE;
5886 * Is this MMIO handled locally?
5888 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5889 if (handled == bytes)
5890 return X86EMUL_CONTINUE;
5896 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5897 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5901 return X86EMUL_CONTINUE;
5904 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5906 void *val, unsigned int bytes,
5907 struct x86_exception *exception,
5908 const struct read_write_emulator_ops *ops)
5910 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5914 if (ops->read_write_prepare &&
5915 ops->read_write_prepare(vcpu, val, bytes))
5916 return X86EMUL_CONTINUE;
5918 vcpu->mmio_nr_fragments = 0;
5920 /* Crossing a page boundary? */
5921 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5924 now = -addr & ~PAGE_MASK;
5925 rc = emulator_read_write_onepage(addr, val, now, exception,
5928 if (rc != X86EMUL_CONTINUE)
5931 if (ctxt->mode != X86EMUL_MODE_PROT64)
5937 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5939 if (rc != X86EMUL_CONTINUE)
5942 if (!vcpu->mmio_nr_fragments)
5945 gpa = vcpu->mmio_fragments[0].gpa;
5947 vcpu->mmio_needed = 1;
5948 vcpu->mmio_cur_fragment = 0;
5950 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5951 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5952 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5953 vcpu->run->mmio.phys_addr = gpa;
5955 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5958 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5962 struct x86_exception *exception)
5964 return emulator_read_write(ctxt, addr, val, bytes,
5965 exception, &read_emultor);
5968 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5972 struct x86_exception *exception)
5974 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5975 exception, &write_emultor);
5978 #define CMPXCHG_TYPE(t, ptr, old, new) \
5979 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5981 #ifdef CONFIG_X86_64
5982 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5984 # define CMPXCHG64(ptr, old, new) \
5985 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5988 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5993 struct x86_exception *exception)
5995 struct kvm_host_map map;
5996 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6002 /* guests cmpxchg8b have to be emulated atomically */
6003 if (bytes > 8 || (bytes & (bytes - 1)))
6006 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6008 if (gpa == UNMAPPED_GVA ||
6009 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6013 * Emulate the atomic as a straight write to avoid #AC if SLD is
6014 * enabled in the host and the access splits a cache line.
6016 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6017 page_line_mask = ~(cache_line_size() - 1);
6019 page_line_mask = PAGE_MASK;
6021 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6024 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6027 kaddr = map.hva + offset_in_page(gpa);
6031 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6034 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6037 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6040 exchanged = CMPXCHG64(kaddr, old, new);
6046 kvm_vcpu_unmap(vcpu, &map, true);
6049 return X86EMUL_CMPXCHG_FAILED;
6051 kvm_page_track_write(vcpu, gpa, new, bytes);
6053 return X86EMUL_CONTINUE;
6056 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6058 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6061 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6065 for (i = 0; i < vcpu->arch.pio.count; i++) {
6066 if (vcpu->arch.pio.in)
6067 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6068 vcpu->arch.pio.size, pd);
6070 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6071 vcpu->arch.pio.port, vcpu->arch.pio.size,
6075 pd += vcpu->arch.pio.size;
6080 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6081 unsigned short port, void *val,
6082 unsigned int count, bool in)
6084 vcpu->arch.pio.port = port;
6085 vcpu->arch.pio.in = in;
6086 vcpu->arch.pio.count = count;
6087 vcpu->arch.pio.size = size;
6089 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6090 vcpu->arch.pio.count = 0;
6094 vcpu->run->exit_reason = KVM_EXIT_IO;
6095 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6096 vcpu->run->io.size = size;
6097 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6098 vcpu->run->io.count = count;
6099 vcpu->run->io.port = port;
6104 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6105 unsigned short port, void *val, unsigned int count)
6109 if (vcpu->arch.pio.count)
6112 memset(vcpu->arch.pio_data, 0, size * count);
6114 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6117 memcpy(val, vcpu->arch.pio_data, size * count);
6118 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6119 vcpu->arch.pio.count = 0;
6126 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6127 int size, unsigned short port, void *val,
6130 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6134 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6135 unsigned short port, const void *val,
6138 memcpy(vcpu->arch.pio_data, val, size * count);
6139 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6140 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6143 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6144 int size, unsigned short port,
6145 const void *val, unsigned int count)
6147 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6150 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6152 return kvm_x86_ops.get_segment_base(vcpu, seg);
6155 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6157 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6160 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6162 if (!need_emulate_wbinvd(vcpu))
6163 return X86EMUL_CONTINUE;
6165 if (kvm_x86_ops.has_wbinvd_exit()) {
6166 int cpu = get_cpu();
6168 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6169 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6170 wbinvd_ipi, NULL, 1);
6172 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6175 return X86EMUL_CONTINUE;
6178 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6180 kvm_emulate_wbinvd_noskip(vcpu);
6181 return kvm_skip_emulated_instruction(vcpu);
6183 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6187 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6189 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6192 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6193 unsigned long *dest)
6195 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6198 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6199 unsigned long value)
6202 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6205 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6207 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6210 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6212 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6213 unsigned long value;
6217 value = kvm_read_cr0(vcpu);
6220 value = vcpu->arch.cr2;
6223 value = kvm_read_cr3(vcpu);
6226 value = kvm_read_cr4(vcpu);
6229 value = kvm_get_cr8(vcpu);
6232 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6239 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6241 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6246 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6249 vcpu->arch.cr2 = val;
6252 res = kvm_set_cr3(vcpu, val);
6255 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6258 res = kvm_set_cr8(vcpu, val);
6261 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6268 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6270 return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6273 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6275 kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6278 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6280 kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6283 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6285 kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6288 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6290 kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6293 static unsigned long emulator_get_cached_segment_base(
6294 struct x86_emulate_ctxt *ctxt, int seg)
6296 return get_segment_base(emul_to_vcpu(ctxt), seg);
6299 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6300 struct desc_struct *desc, u32 *base3,
6303 struct kvm_segment var;
6305 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6306 *selector = var.selector;
6309 memset(desc, 0, sizeof(*desc));
6317 set_desc_limit(desc, var.limit);
6318 set_desc_base(desc, (unsigned long)var.base);
6319 #ifdef CONFIG_X86_64
6321 *base3 = var.base >> 32;
6323 desc->type = var.type;
6325 desc->dpl = var.dpl;
6326 desc->p = var.present;
6327 desc->avl = var.avl;
6335 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6336 struct desc_struct *desc, u32 base3,
6339 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6340 struct kvm_segment var;
6342 var.selector = selector;
6343 var.base = get_desc_base(desc);
6344 #ifdef CONFIG_X86_64
6345 var.base |= ((u64)base3) << 32;
6347 var.limit = get_desc_limit(desc);
6349 var.limit = (var.limit << 12) | 0xfff;
6350 var.type = desc->type;
6351 var.dpl = desc->dpl;
6356 var.avl = desc->avl;
6357 var.present = desc->p;
6358 var.unusable = !var.present;
6361 kvm_set_segment(vcpu, &var, seg);
6365 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6366 u32 msr_index, u64 *pdata)
6368 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6371 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6372 u32 msr_index, u64 data)
6374 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6377 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6379 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6381 return vcpu->arch.smbase;
6384 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6386 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6388 vcpu->arch.smbase = smbase;
6391 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6394 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6397 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6398 u32 pmc, u64 *pdata)
6400 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6403 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6405 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6408 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6409 struct x86_instruction_info *info,
6410 enum x86_intercept_stage stage)
6412 return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6416 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6417 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6420 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6423 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6425 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6428 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6430 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6433 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6435 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6438 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6440 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6443 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6445 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6448 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6450 kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6453 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6455 return emul_to_vcpu(ctxt)->arch.hflags;
6458 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6460 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6463 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6464 const char *smstate)
6466 return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6469 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6471 kvm_smm_changed(emul_to_vcpu(ctxt));
6474 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6476 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6479 static const struct x86_emulate_ops emulate_ops = {
6480 .read_gpr = emulator_read_gpr,
6481 .write_gpr = emulator_write_gpr,
6482 .read_std = emulator_read_std,
6483 .write_std = emulator_write_std,
6484 .read_phys = kvm_read_guest_phys_system,
6485 .fetch = kvm_fetch_guest_virt,
6486 .read_emulated = emulator_read_emulated,
6487 .write_emulated = emulator_write_emulated,
6488 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6489 .invlpg = emulator_invlpg,
6490 .pio_in_emulated = emulator_pio_in_emulated,
6491 .pio_out_emulated = emulator_pio_out_emulated,
6492 .get_segment = emulator_get_segment,
6493 .set_segment = emulator_set_segment,
6494 .get_cached_segment_base = emulator_get_cached_segment_base,
6495 .get_gdt = emulator_get_gdt,
6496 .get_idt = emulator_get_idt,
6497 .set_gdt = emulator_set_gdt,
6498 .set_idt = emulator_set_idt,
6499 .get_cr = emulator_get_cr,
6500 .set_cr = emulator_set_cr,
6501 .cpl = emulator_get_cpl,
6502 .get_dr = emulator_get_dr,
6503 .set_dr = emulator_set_dr,
6504 .get_smbase = emulator_get_smbase,
6505 .set_smbase = emulator_set_smbase,
6506 .set_msr = emulator_set_msr,
6507 .get_msr = emulator_get_msr,
6508 .check_pmc = emulator_check_pmc,
6509 .read_pmc = emulator_read_pmc,
6510 .halt = emulator_halt,
6511 .wbinvd = emulator_wbinvd,
6512 .fix_hypercall = emulator_fix_hypercall,
6513 .intercept = emulator_intercept,
6514 .get_cpuid = emulator_get_cpuid,
6515 .guest_has_long_mode = emulator_guest_has_long_mode,
6516 .guest_has_movbe = emulator_guest_has_movbe,
6517 .guest_has_fxsr = emulator_guest_has_fxsr,
6518 .set_nmi_mask = emulator_set_nmi_mask,
6519 .get_hflags = emulator_get_hflags,
6520 .set_hflags = emulator_set_hflags,
6521 .pre_leave_smm = emulator_pre_leave_smm,
6522 .post_leave_smm = emulator_post_leave_smm,
6523 .set_xcr = emulator_set_xcr,
6526 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6528 u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6530 * an sti; sti; sequence only disable interrupts for the first
6531 * instruction. So, if the last instruction, be it emulated or
6532 * not, left the system with the INT_STI flag enabled, it
6533 * means that the last instruction is an sti. We should not
6534 * leave the flag on in this case. The same goes for mov ss
6536 if (int_shadow & mask)
6538 if (unlikely(int_shadow || mask)) {
6539 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6541 kvm_make_request(KVM_REQ_EVENT, vcpu);
6545 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6547 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6548 if (ctxt->exception.vector == PF_VECTOR)
6549 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6551 if (ctxt->exception.error_code_valid)
6552 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6553 ctxt->exception.error_code);
6555 kvm_queue_exception(vcpu, ctxt->exception.vector);
6559 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6561 struct x86_emulate_ctxt *ctxt;
6563 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6565 pr_err("kvm: failed to allocate vcpu's emulator\n");
6570 ctxt->ops = &emulate_ops;
6571 vcpu->arch.emulate_ctxt = ctxt;
6576 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6578 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6581 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6583 ctxt->gpa_available = false;
6584 ctxt->eflags = kvm_get_rflags(vcpu);
6585 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6587 ctxt->eip = kvm_rip_read(vcpu);
6588 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6589 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6590 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6591 cs_db ? X86EMUL_MODE_PROT32 :
6592 X86EMUL_MODE_PROT16;
6593 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6594 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6595 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6597 init_decode_cache(ctxt);
6598 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6601 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6603 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6606 init_emulate_ctxt(vcpu);
6610 ctxt->_eip = ctxt->eip + inc_eip;
6611 ret = emulate_int_real(ctxt, irq);
6613 if (ret != X86EMUL_CONTINUE) {
6614 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6616 ctxt->eip = ctxt->_eip;
6617 kvm_rip_write(vcpu, ctxt->eip);
6618 kvm_set_rflags(vcpu, ctxt->eflags);
6621 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6623 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6625 ++vcpu->stat.insn_emulation_fail;
6626 trace_kvm_emulate_insn_failed(vcpu);
6628 if (emulation_type & EMULTYPE_VMWARE_GP) {
6629 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6633 if (emulation_type & EMULTYPE_SKIP) {
6634 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6635 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6636 vcpu->run->internal.ndata = 0;
6640 kvm_queue_exception(vcpu, UD_VECTOR);
6642 if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
6643 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6644 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6645 vcpu->run->internal.ndata = 0;
6652 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6653 bool write_fault_to_shadow_pgtable,
6656 gpa_t gpa = cr2_or_gpa;
6659 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6662 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6663 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6666 if (!vcpu->arch.mmu->direct_map) {
6668 * Write permission should be allowed since only
6669 * write access need to be emulated.
6671 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6674 * If the mapping is invalid in guest, let cpu retry
6675 * it to generate fault.
6677 if (gpa == UNMAPPED_GVA)
6682 * Do not retry the unhandleable instruction if it faults on the
6683 * readonly host memory, otherwise it will goto a infinite loop:
6684 * retry instruction -> write #PF -> emulation fail -> retry
6685 * instruction -> ...
6687 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6690 * If the instruction failed on the error pfn, it can not be fixed,
6691 * report the error to userspace.
6693 if (is_error_noslot_pfn(pfn))
6696 kvm_release_pfn_clean(pfn);
6698 /* The instructions are well-emulated on direct mmu. */
6699 if (vcpu->arch.mmu->direct_map) {
6700 unsigned int indirect_shadow_pages;
6702 spin_lock(&vcpu->kvm->mmu_lock);
6703 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6704 spin_unlock(&vcpu->kvm->mmu_lock);
6706 if (indirect_shadow_pages)
6707 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6713 * if emulation was due to access to shadowed page table
6714 * and it failed try to unshadow page and re-enter the
6715 * guest to let CPU execute the instruction.
6717 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6720 * If the access faults on its page table, it can not
6721 * be fixed by unprotecting shadow page and it should
6722 * be reported to userspace.
6724 return !write_fault_to_shadow_pgtable;
6727 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6728 gpa_t cr2_or_gpa, int emulation_type)
6730 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6731 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6733 last_retry_eip = vcpu->arch.last_retry_eip;
6734 last_retry_addr = vcpu->arch.last_retry_addr;
6737 * If the emulation is caused by #PF and it is non-page_table
6738 * writing instruction, it means the VM-EXIT is caused by shadow
6739 * page protected, we can zap the shadow page and retry this
6740 * instruction directly.
6742 * Note: if the guest uses a non-page-table modifying instruction
6743 * on the PDE that points to the instruction, then we will unmap
6744 * the instruction and go to an infinite loop. So, we cache the
6745 * last retried eip and the last fault address, if we meet the eip
6746 * and the address again, we can break out of the potential infinite
6749 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6751 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6754 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6755 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6758 if (x86_page_table_writing_insn(ctxt))
6761 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6764 vcpu->arch.last_retry_eip = ctxt->eip;
6765 vcpu->arch.last_retry_addr = cr2_or_gpa;
6767 if (!vcpu->arch.mmu->direct_map)
6768 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6770 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6775 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6776 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6778 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6780 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6781 /* This is a good place to trace that we are exiting SMM. */
6782 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6784 /* Process a latched INIT or SMI, if any. */
6785 kvm_make_request(KVM_REQ_EVENT, vcpu);
6788 kvm_mmu_reset_context(vcpu);
6791 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6800 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6801 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6806 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6808 struct kvm_run *kvm_run = vcpu->run;
6810 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6811 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6812 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6813 kvm_run->debug.arch.exception = DB_VECTOR;
6814 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6817 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6821 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6823 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6826 r = kvm_x86_ops.skip_emulated_instruction(vcpu);
6831 * rflags is the old, "raw" value of the flags. The new value has
6832 * not been saved yet.
6834 * This is correct even for TF set by the guest, because "the
6835 * processor will not generate this exception after the instruction
6836 * that sets the TF flag".
6838 if (unlikely(rflags & X86_EFLAGS_TF))
6839 r = kvm_vcpu_do_singlestep(vcpu);
6842 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6844 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6846 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6847 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6848 struct kvm_run *kvm_run = vcpu->run;
6849 unsigned long eip = kvm_get_linear_rip(vcpu);
6850 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6851 vcpu->arch.guest_debug_dr7,
6855 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6856 kvm_run->debug.arch.pc = eip;
6857 kvm_run->debug.arch.exception = DB_VECTOR;
6858 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6864 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6865 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6866 unsigned long eip = kvm_get_linear_rip(vcpu);
6867 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6872 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
6881 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6883 switch (ctxt->opcode_len) {
6890 case 0xe6: /* OUT */
6894 case 0x6c: /* INS */
6896 case 0x6e: /* OUTS */
6903 case 0x33: /* RDPMC */
6912 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6913 int emulation_type, void *insn, int insn_len)
6916 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6917 bool writeback = true;
6918 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6920 vcpu->arch.l1tf_flush_l1d = true;
6923 * Clear write_fault_to_shadow_pgtable here to ensure it is
6926 vcpu->arch.write_fault_to_shadow_pgtable = false;
6927 kvm_clear_exception_queue(vcpu);
6929 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6930 init_emulate_ctxt(vcpu);
6933 * We will reenter on the same instruction since
6934 * we do not set complete_userspace_io. This does not
6935 * handle watchpoints yet, those would be handled in
6938 if (!(emulation_type & EMULTYPE_SKIP) &&
6939 kvm_vcpu_check_breakpoint(vcpu, &r))
6942 ctxt->interruptibility = 0;
6943 ctxt->have_exception = false;
6944 ctxt->exception.vector = -1;
6945 ctxt->perm_ok = false;
6947 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6949 r = x86_decode_insn(ctxt, insn, insn_len);
6951 trace_kvm_emulate_insn_start(vcpu);
6952 ++vcpu->stat.insn_emulation;
6953 if (r != EMULATION_OK) {
6954 if ((emulation_type & EMULTYPE_TRAP_UD) ||
6955 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6956 kvm_queue_exception(vcpu, UD_VECTOR);
6959 if (reexecute_instruction(vcpu, cr2_or_gpa,
6963 if (ctxt->have_exception) {
6965 * #UD should result in just EMULATION_FAILED, and trap-like
6966 * exception should not be encountered during decode.
6968 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6969 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6970 inject_emulated_exception(vcpu);
6973 return handle_emulation_failure(vcpu, emulation_type);
6977 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6978 !is_vmware_backdoor_opcode(ctxt)) {
6979 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6984 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6985 * for kvm_skip_emulated_instruction(). The caller is responsible for
6986 * updating interruptibility state and injecting single-step #DBs.
6988 if (emulation_type & EMULTYPE_SKIP) {
6989 kvm_rip_write(vcpu, ctxt->_eip);
6990 if (ctxt->eflags & X86_EFLAGS_RF)
6991 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6995 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6998 /* this is needed for vmware backdoor interface to work since it
6999 changes registers values during IO operation */
7000 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
7001 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7002 emulator_invalidate_register_cache(ctxt);
7006 if (emulation_type & EMULTYPE_PF) {
7007 /* Save the faulting GPA (cr2) in the address field */
7008 ctxt->exception.address = cr2_or_gpa;
7010 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7011 if (vcpu->arch.mmu->direct_map) {
7012 ctxt->gpa_available = true;
7013 ctxt->gpa_val = cr2_or_gpa;
7016 /* Sanitize the address out of an abundance of paranoia. */
7017 ctxt->exception.address = 0;
7020 r = x86_emulate_insn(ctxt);
7022 if (r == EMULATION_INTERCEPTED)
7025 if (r == EMULATION_FAILED) {
7026 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7030 return handle_emulation_failure(vcpu, emulation_type);
7033 if (ctxt->have_exception) {
7035 if (inject_emulated_exception(vcpu))
7037 } else if (vcpu->arch.pio.count) {
7038 if (!vcpu->arch.pio.in) {
7039 /* FIXME: return into emulator if single-stepping. */
7040 vcpu->arch.pio.count = 0;
7043 vcpu->arch.complete_userspace_io = complete_emulated_pio;
7046 } else if (vcpu->mmio_needed) {
7047 ++vcpu->stat.mmio_exits;
7049 if (!vcpu->mmio_is_write)
7052 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7053 } else if (r == EMULATION_RESTART)
7059 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7060 toggle_interruptibility(vcpu, ctxt->interruptibility);
7061 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7062 if (!ctxt->have_exception ||
7063 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7064 kvm_rip_write(vcpu, ctxt->eip);
7065 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7066 r = kvm_vcpu_do_singlestep(vcpu);
7067 if (kvm_x86_ops.update_emulated_instruction)
7068 kvm_x86_ops.update_emulated_instruction(vcpu);
7069 __kvm_set_rflags(vcpu, ctxt->eflags);
7073 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7074 * do nothing, and it will be requested again as soon as
7075 * the shadow expires. But we still need to check here,
7076 * because POPF has no interrupt shadow.
7078 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7079 kvm_make_request(KVM_REQ_EVENT, vcpu);
7081 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7086 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7088 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7090 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7092 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7093 void *insn, int insn_len)
7095 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7097 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7099 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7101 vcpu->arch.pio.count = 0;
7105 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7107 vcpu->arch.pio.count = 0;
7109 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7112 return kvm_skip_emulated_instruction(vcpu);
7115 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7116 unsigned short port)
7118 unsigned long val = kvm_rax_read(vcpu);
7119 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7125 * Workaround userspace that relies on old KVM behavior of %rip being
7126 * incremented prior to exiting to userspace to handle "OUT 0x7e".
7129 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7130 vcpu->arch.complete_userspace_io =
7131 complete_fast_pio_out_port_0x7e;
7132 kvm_skip_emulated_instruction(vcpu);
7134 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7135 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7140 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7144 /* We should only ever be called with arch.pio.count equal to 1 */
7145 BUG_ON(vcpu->arch.pio.count != 1);
7147 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7148 vcpu->arch.pio.count = 0;
7152 /* For size less than 4 we merge, else we zero extend */
7153 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7156 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7157 * the copy and tracing
7159 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7160 kvm_rax_write(vcpu, val);
7162 return kvm_skip_emulated_instruction(vcpu);
7165 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7166 unsigned short port)
7171 /* For size less than 4 we merge, else we zero extend */
7172 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7174 ret = emulator_pio_in(vcpu, size, port, &val, 1);
7176 kvm_rax_write(vcpu, val);
7180 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7181 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7186 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7191 ret = kvm_fast_pio_in(vcpu, size, port);
7193 ret = kvm_fast_pio_out(vcpu, size, port);
7194 return ret && kvm_skip_emulated_instruction(vcpu);
7196 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7198 static int kvmclock_cpu_down_prep(unsigned int cpu)
7200 __this_cpu_write(cpu_tsc_khz, 0);
7204 static void tsc_khz_changed(void *data)
7206 struct cpufreq_freqs *freq = data;
7207 unsigned long khz = 0;
7211 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7212 khz = cpufreq_quick_get(raw_smp_processor_id());
7215 __this_cpu_write(cpu_tsc_khz, khz);
7218 #ifdef CONFIG_X86_64
7219 static void kvm_hyperv_tsc_notifier(void)
7222 struct kvm_vcpu *vcpu;
7225 mutex_lock(&kvm_lock);
7226 list_for_each_entry(kvm, &vm_list, vm_list)
7227 kvm_make_mclock_inprogress_request(kvm);
7229 hyperv_stop_tsc_emulation();
7231 /* TSC frequency always matches when on Hyper-V */
7232 for_each_present_cpu(cpu)
7233 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7234 kvm_max_guest_tsc_khz = tsc_khz;
7236 list_for_each_entry(kvm, &vm_list, vm_list) {
7237 struct kvm_arch *ka = &kvm->arch;
7239 spin_lock(&ka->pvclock_gtod_sync_lock);
7241 pvclock_update_vm_gtod_copy(kvm);
7243 kvm_for_each_vcpu(cpu, vcpu, kvm)
7244 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7246 kvm_for_each_vcpu(cpu, vcpu, kvm)
7247 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7249 spin_unlock(&ka->pvclock_gtod_sync_lock);
7251 mutex_unlock(&kvm_lock);
7255 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7258 struct kvm_vcpu *vcpu;
7259 int i, send_ipi = 0;
7262 * We allow guests to temporarily run on slowing clocks,
7263 * provided we notify them after, or to run on accelerating
7264 * clocks, provided we notify them before. Thus time never
7267 * However, we have a problem. We can't atomically update
7268 * the frequency of a given CPU from this function; it is
7269 * merely a notifier, which can be called from any CPU.
7270 * Changing the TSC frequency at arbitrary points in time
7271 * requires a recomputation of local variables related to
7272 * the TSC for each VCPU. We must flag these local variables
7273 * to be updated and be sure the update takes place with the
7274 * new frequency before any guests proceed.
7276 * Unfortunately, the combination of hotplug CPU and frequency
7277 * change creates an intractable locking scenario; the order
7278 * of when these callouts happen is undefined with respect to
7279 * CPU hotplug, and they can race with each other. As such,
7280 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7281 * undefined; you can actually have a CPU frequency change take
7282 * place in between the computation of X and the setting of the
7283 * variable. To protect against this problem, all updates of
7284 * the per_cpu tsc_khz variable are done in an interrupt
7285 * protected IPI, and all callers wishing to update the value
7286 * must wait for a synchronous IPI to complete (which is trivial
7287 * if the caller is on the CPU already). This establishes the
7288 * necessary total order on variable updates.
7290 * Note that because a guest time update may take place
7291 * anytime after the setting of the VCPU's request bit, the
7292 * correct TSC value must be set before the request. However,
7293 * to ensure the update actually makes it to any guest which
7294 * starts running in hardware virtualization between the set
7295 * and the acquisition of the spinlock, we must also ping the
7296 * CPU after setting the request bit.
7300 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7302 mutex_lock(&kvm_lock);
7303 list_for_each_entry(kvm, &vm_list, vm_list) {
7304 kvm_for_each_vcpu(i, vcpu, kvm) {
7305 if (vcpu->cpu != cpu)
7307 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7308 if (vcpu->cpu != raw_smp_processor_id())
7312 mutex_unlock(&kvm_lock);
7314 if (freq->old < freq->new && send_ipi) {
7316 * We upscale the frequency. Must make the guest
7317 * doesn't see old kvmclock values while running with
7318 * the new frequency, otherwise we risk the guest sees
7319 * time go backwards.
7321 * In case we update the frequency for another cpu
7322 * (which might be in guest context) send an interrupt
7323 * to kick the cpu out of guest context. Next time
7324 * guest context is entered kvmclock will be updated,
7325 * so the guest will not see stale values.
7327 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7331 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7334 struct cpufreq_freqs *freq = data;
7337 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7339 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7342 for_each_cpu(cpu, freq->policy->cpus)
7343 __kvmclock_cpufreq_notifier(freq, cpu);
7348 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7349 .notifier_call = kvmclock_cpufreq_notifier
7352 static int kvmclock_cpu_online(unsigned int cpu)
7354 tsc_khz_changed(NULL);
7358 static void kvm_timer_init(void)
7360 max_tsc_khz = tsc_khz;
7362 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7363 #ifdef CONFIG_CPU_FREQ
7364 struct cpufreq_policy *policy;
7368 policy = cpufreq_cpu_get(cpu);
7370 if (policy->cpuinfo.max_freq)
7371 max_tsc_khz = policy->cpuinfo.max_freq;
7372 cpufreq_cpu_put(policy);
7376 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7377 CPUFREQ_TRANSITION_NOTIFIER);
7380 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7381 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7384 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7385 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7387 int kvm_is_in_guest(void)
7389 return __this_cpu_read(current_vcpu) != NULL;
7392 static int kvm_is_user_mode(void)
7396 if (__this_cpu_read(current_vcpu))
7397 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7399 return user_mode != 0;
7402 static unsigned long kvm_get_guest_ip(void)
7404 unsigned long ip = 0;
7406 if (__this_cpu_read(current_vcpu))
7407 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7412 static void kvm_handle_intel_pt_intr(void)
7414 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7416 kvm_make_request(KVM_REQ_PMI, vcpu);
7417 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7418 (unsigned long *)&vcpu->arch.pmu.global_status);
7421 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7422 .is_in_guest = kvm_is_in_guest,
7423 .is_user_mode = kvm_is_user_mode,
7424 .get_guest_ip = kvm_get_guest_ip,
7425 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7428 #ifdef CONFIG_X86_64
7429 static void pvclock_gtod_update_fn(struct work_struct *work)
7433 struct kvm_vcpu *vcpu;
7436 mutex_lock(&kvm_lock);
7437 list_for_each_entry(kvm, &vm_list, vm_list)
7438 kvm_for_each_vcpu(i, vcpu, kvm)
7439 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7440 atomic_set(&kvm_guest_has_master_clock, 0);
7441 mutex_unlock(&kvm_lock);
7444 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7447 * Notification about pvclock gtod data update.
7449 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7452 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7453 struct timekeeper *tk = priv;
7455 update_pvclock_gtod(tk);
7457 /* disable master clock if host does not trust, or does not
7458 * use, TSC based clocksource.
7460 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7461 atomic_read(&kvm_guest_has_master_clock) != 0)
7462 queue_work(system_long_wq, &pvclock_gtod_work);
7467 static struct notifier_block pvclock_gtod_notifier = {
7468 .notifier_call = pvclock_gtod_notify,
7472 int kvm_arch_init(void *opaque)
7474 struct kvm_x86_init_ops *ops = opaque;
7477 if (kvm_x86_ops.hardware_enable) {
7478 printk(KERN_ERR "kvm: already loaded the other module\n");
7483 if (!ops->cpu_has_kvm_support()) {
7484 pr_err_ratelimited("kvm: no hardware support\n");
7488 if (ops->disabled_by_bios()) {
7489 pr_err_ratelimited("kvm: disabled by bios\n");
7495 * KVM explicitly assumes that the guest has an FPU and
7496 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7497 * vCPU's FPU state as a fxregs_state struct.
7499 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7500 printk(KERN_ERR "kvm: inadequate fpu\n");
7506 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7507 __alignof__(struct fpu), SLAB_ACCOUNT,
7509 if (!x86_fpu_cache) {
7510 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7514 x86_emulator_cache = kvm_alloc_emulator_cache();
7515 if (!x86_emulator_cache) {
7516 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7517 goto out_free_x86_fpu_cache;
7520 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7522 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7523 goto out_free_x86_emulator_cache;
7526 r = kvm_mmu_module_init();
7528 goto out_free_percpu;
7530 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7531 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7532 PT_PRESENT_MASK, 0, sme_me_mask);
7535 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7537 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7538 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7539 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7543 if (pi_inject_timer == -1)
7544 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7545 #ifdef CONFIG_X86_64
7546 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7548 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7549 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7555 free_percpu(shared_msrs);
7556 out_free_x86_emulator_cache:
7557 kmem_cache_destroy(x86_emulator_cache);
7558 out_free_x86_fpu_cache:
7559 kmem_cache_destroy(x86_fpu_cache);
7564 void kvm_arch_exit(void)
7566 #ifdef CONFIG_X86_64
7567 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7568 clear_hv_tscchange_cb();
7571 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7573 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7574 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7575 CPUFREQ_TRANSITION_NOTIFIER);
7576 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7577 #ifdef CONFIG_X86_64
7578 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7580 kvm_x86_ops.hardware_enable = NULL;
7581 kvm_mmu_module_exit();
7582 free_percpu(shared_msrs);
7583 kmem_cache_destroy(x86_fpu_cache);
7586 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7588 ++vcpu->stat.halt_exits;
7589 if (lapic_in_kernel(vcpu)) {
7590 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7593 vcpu->run->exit_reason = KVM_EXIT_HLT;
7597 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7599 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7601 int ret = kvm_skip_emulated_instruction(vcpu);
7603 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7604 * KVM_EXIT_DEBUG here.
7606 return kvm_vcpu_halt(vcpu) && ret;
7608 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7610 #ifdef CONFIG_X86_64
7611 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7612 unsigned long clock_type)
7614 struct kvm_clock_pairing clock_pairing;
7615 struct timespec64 ts;
7619 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7620 return -KVM_EOPNOTSUPP;
7622 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7623 return -KVM_EOPNOTSUPP;
7625 clock_pairing.sec = ts.tv_sec;
7626 clock_pairing.nsec = ts.tv_nsec;
7627 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7628 clock_pairing.flags = 0;
7629 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7632 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7633 sizeof(struct kvm_clock_pairing)))
7641 * kvm_pv_kick_cpu_op: Kick a vcpu.
7643 * @apicid - apicid of vcpu to be kicked.
7645 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7647 struct kvm_lapic_irq lapic_irq;
7649 lapic_irq.shorthand = APIC_DEST_NOSHORT;
7650 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7651 lapic_irq.level = 0;
7652 lapic_irq.dest_id = apicid;
7653 lapic_irq.msi_redir_hint = false;
7655 lapic_irq.delivery_mode = APIC_DM_REMRD;
7656 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7659 bool kvm_apicv_activated(struct kvm *kvm)
7661 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7663 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7665 void kvm_apicv_init(struct kvm *kvm, bool enable)
7668 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7669 &kvm->arch.apicv_inhibit_reasons);
7671 set_bit(APICV_INHIBIT_REASON_DISABLE,
7672 &kvm->arch.apicv_inhibit_reasons);
7674 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7676 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7678 struct kvm_vcpu *target = NULL;
7679 struct kvm_apic_map *map;
7682 map = rcu_dereference(kvm->arch.apic_map);
7684 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7685 target = map->phys_map[dest_id]->vcpu;
7689 if (target && READ_ONCE(target->ready))
7690 kvm_vcpu_yield_to(target);
7693 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7695 unsigned long nr, a0, a1, a2, a3, ret;
7698 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7699 return kvm_hv_hypercall(vcpu);
7701 nr = kvm_rax_read(vcpu);
7702 a0 = kvm_rbx_read(vcpu);
7703 a1 = kvm_rcx_read(vcpu);
7704 a2 = kvm_rdx_read(vcpu);
7705 a3 = kvm_rsi_read(vcpu);
7707 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7709 op_64_bit = is_64_bit_mode(vcpu);
7718 if (kvm_x86_ops.get_cpl(vcpu) != 0) {
7724 case KVM_HC_VAPIC_POLL_IRQ:
7727 case KVM_HC_KICK_CPU:
7728 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7729 kvm_sched_yield(vcpu->kvm, a1);
7732 #ifdef CONFIG_X86_64
7733 case KVM_HC_CLOCK_PAIRING:
7734 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7737 case KVM_HC_SEND_IPI:
7738 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7740 case KVM_HC_SCHED_YIELD:
7741 kvm_sched_yield(vcpu->kvm, a0);
7751 kvm_rax_write(vcpu, ret);
7753 ++vcpu->stat.hypercalls;
7754 return kvm_skip_emulated_instruction(vcpu);
7756 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7758 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7760 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7761 char instruction[3];
7762 unsigned long rip = kvm_rip_read(vcpu);
7764 kvm_x86_ops.patch_hypercall(vcpu, instruction);
7766 return emulator_write_emulated(ctxt, rip, instruction, 3,
7770 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7772 return vcpu->run->request_interrupt_window &&
7773 likely(!pic_in_kernel(vcpu->kvm));
7776 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7778 struct kvm_run *kvm_run = vcpu->run;
7780 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7781 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7782 kvm_run->cr8 = kvm_get_cr8(vcpu);
7783 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7784 kvm_run->ready_for_interrupt_injection =
7785 pic_in_kernel(vcpu->kvm) ||
7786 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7789 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7793 if (!kvm_x86_ops.update_cr8_intercept)
7796 if (!lapic_in_kernel(vcpu))
7799 if (vcpu->arch.apicv_active)
7802 if (!vcpu->arch.apic->vapic_addr)
7803 max_irr = kvm_lapic_find_highest_irr(vcpu);
7810 tpr = kvm_lapic_get_cr8(vcpu);
7812 kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
7815 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
7818 bool can_inject = true;
7820 /* try to reinject previous events if any */
7822 if (vcpu->arch.exception.injected) {
7823 kvm_x86_ops.queue_exception(vcpu);
7827 * Do not inject an NMI or interrupt if there is a pending
7828 * exception. Exceptions and interrupts are recognized at
7829 * instruction boundaries, i.e. the start of an instruction.
7830 * Trap-like exceptions, e.g. #DB, have higher priority than
7831 * NMIs and interrupts, i.e. traps are recognized before an
7832 * NMI/interrupt that's pending on the same instruction.
7833 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7834 * priority, but are only generated (pended) during instruction
7835 * execution, i.e. a pending fault-like exception means the
7836 * fault occurred on the *previous* instruction and must be
7837 * serviced prior to recognizing any new events in order to
7838 * fully complete the previous instruction.
7840 else if (!vcpu->arch.exception.pending) {
7841 if (vcpu->arch.nmi_injected) {
7842 kvm_x86_ops.set_nmi(vcpu);
7844 } else if (vcpu->arch.interrupt.injected) {
7845 kvm_x86_ops.set_irq(vcpu);
7850 WARN_ON_ONCE(vcpu->arch.exception.injected &&
7851 vcpu->arch.exception.pending);
7854 * Call check_nested_events() even if we reinjected a previous event
7855 * in order for caller to determine if it should require immediate-exit
7856 * from L2 to L1 due to pending L1 events which require exit
7859 if (is_guest_mode(vcpu)) {
7860 r = kvm_x86_ops.nested_ops->check_events(vcpu);
7865 /* try to inject new event if pending */
7866 if (vcpu->arch.exception.pending) {
7867 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7868 vcpu->arch.exception.has_error_code,
7869 vcpu->arch.exception.error_code);
7871 vcpu->arch.exception.pending = false;
7872 vcpu->arch.exception.injected = true;
7874 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7875 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7878 if (vcpu->arch.exception.nr == DB_VECTOR) {
7879 kvm_deliver_exception_payload(vcpu);
7880 if (vcpu->arch.dr7 & DR7_GD) {
7881 vcpu->arch.dr7 &= ~DR7_GD;
7882 kvm_update_dr7(vcpu);
7886 kvm_x86_ops.queue_exception(vcpu);
7891 * Finally, inject interrupt events. If an event cannot be injected
7892 * due to architectural conditions (e.g. IF=0) a window-open exit
7893 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
7894 * and can architecturally be injected, but we cannot do it right now:
7895 * an interrupt could have arrived just now and we have to inject it
7896 * as a vmexit, or there could already an event in the queue, which is
7897 * indicated by can_inject. In that case we request an immediate exit
7898 * in order to make progress and get back here for another iteration.
7899 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
7901 if (vcpu->arch.smi_pending) {
7902 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY;
7906 vcpu->arch.smi_pending = false;
7907 ++vcpu->arch.smi_count;
7911 kvm_x86_ops.enable_smi_window(vcpu);
7914 if (vcpu->arch.nmi_pending) {
7915 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY;
7919 --vcpu->arch.nmi_pending;
7920 vcpu->arch.nmi_injected = true;
7921 kvm_x86_ops.set_nmi(vcpu);
7923 WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0);
7925 if (vcpu->arch.nmi_pending)
7926 kvm_x86_ops.enable_nmi_window(vcpu);
7929 if (kvm_cpu_has_injectable_intr(vcpu)) {
7930 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY;
7934 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
7935 kvm_x86_ops.set_irq(vcpu);
7936 WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0);
7938 if (kvm_cpu_has_injectable_intr(vcpu))
7939 kvm_x86_ops.enable_irq_window(vcpu);
7942 if (is_guest_mode(vcpu) &&
7943 kvm_x86_ops.nested_ops->hv_timer_pending &&
7944 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
7945 *req_immediate_exit = true;
7947 WARN_ON(vcpu->arch.exception.pending);
7951 *req_immediate_exit = true;
7955 static void process_nmi(struct kvm_vcpu *vcpu)
7960 * x86 is limited to one NMI running, and one NMI pending after it.
7961 * If an NMI is already in progress, limit further NMIs to just one.
7962 * Otherwise, allow two (and we'll inject the first one immediately).
7964 if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7967 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7968 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7969 kvm_make_request(KVM_REQ_EVENT, vcpu);
7972 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7975 flags |= seg->g << 23;
7976 flags |= seg->db << 22;
7977 flags |= seg->l << 21;
7978 flags |= seg->avl << 20;
7979 flags |= seg->present << 15;
7980 flags |= seg->dpl << 13;
7981 flags |= seg->s << 12;
7982 flags |= seg->type << 8;
7986 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7988 struct kvm_segment seg;
7991 kvm_get_segment(vcpu, &seg, n);
7992 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7995 offset = 0x7f84 + n * 12;
7997 offset = 0x7f2c + (n - 3) * 12;
7999 put_smstate(u32, buf, offset + 8, seg.base);
8000 put_smstate(u32, buf, offset + 4, seg.limit);
8001 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
8004 #ifdef CONFIG_X86_64
8005 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8007 struct kvm_segment seg;
8011 kvm_get_segment(vcpu, &seg, n);
8012 offset = 0x7e00 + n * 16;
8014 flags = enter_smm_get_segment_flags(&seg) >> 8;
8015 put_smstate(u16, buf, offset, seg.selector);
8016 put_smstate(u16, buf, offset + 2, flags);
8017 put_smstate(u32, buf, offset + 4, seg.limit);
8018 put_smstate(u64, buf, offset + 8, seg.base);
8022 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8025 struct kvm_segment seg;
8029 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8030 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8031 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8032 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8034 for (i = 0; i < 8; i++)
8035 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8037 kvm_get_dr(vcpu, 6, &val);
8038 put_smstate(u32, buf, 0x7fcc, (u32)val);
8039 kvm_get_dr(vcpu, 7, &val);
8040 put_smstate(u32, buf, 0x7fc8, (u32)val);
8042 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8043 put_smstate(u32, buf, 0x7fc4, seg.selector);
8044 put_smstate(u32, buf, 0x7f64, seg.base);
8045 put_smstate(u32, buf, 0x7f60, seg.limit);
8046 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8048 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8049 put_smstate(u32, buf, 0x7fc0, seg.selector);
8050 put_smstate(u32, buf, 0x7f80, seg.base);
8051 put_smstate(u32, buf, 0x7f7c, seg.limit);
8052 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8054 kvm_x86_ops.get_gdt(vcpu, &dt);
8055 put_smstate(u32, buf, 0x7f74, dt.address);
8056 put_smstate(u32, buf, 0x7f70, dt.size);
8058 kvm_x86_ops.get_idt(vcpu, &dt);
8059 put_smstate(u32, buf, 0x7f58, dt.address);
8060 put_smstate(u32, buf, 0x7f54, dt.size);
8062 for (i = 0; i < 6; i++)
8063 enter_smm_save_seg_32(vcpu, buf, i);
8065 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8068 put_smstate(u32, buf, 0x7efc, 0x00020000);
8069 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8072 #ifdef CONFIG_X86_64
8073 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8076 struct kvm_segment seg;
8080 for (i = 0; i < 16; i++)
8081 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8083 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8084 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8086 kvm_get_dr(vcpu, 6, &val);
8087 put_smstate(u64, buf, 0x7f68, val);
8088 kvm_get_dr(vcpu, 7, &val);
8089 put_smstate(u64, buf, 0x7f60, val);
8091 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8092 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8093 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8095 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8098 put_smstate(u32, buf, 0x7efc, 0x00020064);
8100 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8102 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8103 put_smstate(u16, buf, 0x7e90, seg.selector);
8104 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8105 put_smstate(u32, buf, 0x7e94, seg.limit);
8106 put_smstate(u64, buf, 0x7e98, seg.base);
8108 kvm_x86_ops.get_idt(vcpu, &dt);
8109 put_smstate(u32, buf, 0x7e84, dt.size);
8110 put_smstate(u64, buf, 0x7e88, dt.address);
8112 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8113 put_smstate(u16, buf, 0x7e70, seg.selector);
8114 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8115 put_smstate(u32, buf, 0x7e74, seg.limit);
8116 put_smstate(u64, buf, 0x7e78, seg.base);
8118 kvm_x86_ops.get_gdt(vcpu, &dt);
8119 put_smstate(u32, buf, 0x7e64, dt.size);
8120 put_smstate(u64, buf, 0x7e68, dt.address);
8122 for (i = 0; i < 6; i++)
8123 enter_smm_save_seg_64(vcpu, buf, i);
8127 static void enter_smm(struct kvm_vcpu *vcpu)
8129 struct kvm_segment cs, ds;
8134 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8135 memset(buf, 0, 512);
8136 #ifdef CONFIG_X86_64
8137 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8138 enter_smm_save_state_64(vcpu, buf);
8141 enter_smm_save_state_32(vcpu, buf);
8144 * Give pre_enter_smm() a chance to make ISA-specific changes to the
8145 * vCPU state (e.g. leave guest mode) after we've saved the state into
8146 * the SMM state-save area.
8148 kvm_x86_ops.pre_enter_smm(vcpu, buf);
8150 vcpu->arch.hflags |= HF_SMM_MASK;
8151 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8153 if (kvm_x86_ops.get_nmi_mask(vcpu))
8154 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8156 kvm_x86_ops.set_nmi_mask(vcpu, true);
8158 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8159 kvm_rip_write(vcpu, 0x8000);
8161 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8162 kvm_x86_ops.set_cr0(vcpu, cr0);
8163 vcpu->arch.cr0 = cr0;
8165 kvm_x86_ops.set_cr4(vcpu, 0);
8167 /* Undocumented: IDT limit is set to zero on entry to SMM. */
8168 dt.address = dt.size = 0;
8169 kvm_x86_ops.set_idt(vcpu, &dt);
8171 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8173 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8174 cs.base = vcpu->arch.smbase;
8179 cs.limit = ds.limit = 0xffffffff;
8180 cs.type = ds.type = 0x3;
8181 cs.dpl = ds.dpl = 0;
8186 cs.avl = ds.avl = 0;
8187 cs.present = ds.present = 1;
8188 cs.unusable = ds.unusable = 0;
8189 cs.padding = ds.padding = 0;
8191 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8192 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8193 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8194 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8195 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8196 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8198 #ifdef CONFIG_X86_64
8199 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8200 kvm_x86_ops.set_efer(vcpu, 0);
8203 kvm_update_cpuid_runtime(vcpu);
8204 kvm_mmu_reset_context(vcpu);
8207 static void process_smi(struct kvm_vcpu *vcpu)
8209 vcpu->arch.smi_pending = true;
8210 kvm_make_request(KVM_REQ_EVENT, vcpu);
8213 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8214 unsigned long *vcpu_bitmap)
8218 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8220 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8221 NULL, vcpu_bitmap, cpus);
8223 free_cpumask_var(cpus);
8226 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8228 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8231 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8233 if (!lapic_in_kernel(vcpu))
8236 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8237 kvm_apic_update_apicv(vcpu);
8238 kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8240 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8243 * NOTE: Do not hold any lock prior to calling this.
8245 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8246 * locked, because it calls __x86_set_memory_region() which does
8247 * synchronize_srcu(&kvm->srcu).
8249 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8251 struct kvm_vcpu *except;
8252 unsigned long old, new, expected;
8254 if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8255 !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8258 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8260 expected = new = old;
8262 __clear_bit(bit, &new);
8264 __set_bit(bit, &new);
8267 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8268 } while (old != expected);
8273 trace_kvm_apicv_update_request(activate, bit);
8274 if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8275 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8278 * Sending request to update APICV for all other vcpus,
8279 * while update the calling vcpu immediately instead of
8280 * waiting for another #VMEXIT to handle the request.
8282 except = kvm_get_running_vcpu();
8283 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8286 kvm_vcpu_update_apicv(except);
8288 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8290 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8292 if (!kvm_apic_present(vcpu))
8295 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8297 if (irqchip_split(vcpu->kvm))
8298 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8300 if (vcpu->arch.apicv_active)
8301 kvm_x86_ops.sync_pir_to_irr(vcpu);
8302 if (ioapic_in_kernel(vcpu->kvm))
8303 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8306 if (is_guest_mode(vcpu))
8307 vcpu->arch.load_eoi_exitmap_pending = true;
8309 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8312 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8314 u64 eoi_exit_bitmap[4];
8316 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8319 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8320 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8321 kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8324 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8325 unsigned long start, unsigned long end)
8327 unsigned long apic_address;
8330 * The physical address of apic access page is stored in the VMCS.
8331 * Update it when it becomes invalid.
8333 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8334 if (start <= apic_address && apic_address < end)
8335 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8338 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8340 if (!lapic_in_kernel(vcpu))
8343 if (!kvm_x86_ops.set_apic_access_page_addr)
8346 kvm_x86_ops.set_apic_access_page_addr(vcpu);
8349 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8351 smp_send_reschedule(vcpu->cpu);
8353 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8356 * Returns 1 to let vcpu_run() continue the guest execution loop without
8357 * exiting to the userspace. Otherwise, the value will be returned to the
8360 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8364 dm_request_for_irq_injection(vcpu) &&
8365 kvm_cpu_accept_dm_intr(vcpu);
8366 fastpath_t exit_fastpath;
8368 bool req_immediate_exit = false;
8370 if (kvm_request_pending(vcpu)) {
8371 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8372 if (unlikely(!kvm_x86_ops.nested_ops->get_vmcs12_pages(vcpu))) {
8377 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8378 kvm_mmu_unload(vcpu);
8379 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8380 __kvm_migrate_timers(vcpu);
8381 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8382 kvm_gen_update_masterclock(vcpu->kvm);
8383 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8384 kvm_gen_kvmclock_update(vcpu);
8385 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8386 r = kvm_guest_time_update(vcpu);
8390 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8391 kvm_mmu_sync_roots(vcpu);
8392 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8393 kvm_mmu_load_pgd(vcpu);
8394 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8395 kvm_vcpu_flush_tlb_all(vcpu);
8397 /* Flushing all ASIDs flushes the current ASID... */
8398 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8400 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8401 kvm_vcpu_flush_tlb_current(vcpu);
8402 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8403 kvm_vcpu_flush_tlb_guest(vcpu);
8405 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8406 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8410 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8411 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8412 vcpu->mmio_needed = 0;
8416 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8417 /* Page is swapped out. Do synthetic halt */
8418 vcpu->arch.apf.halted = true;
8422 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8423 record_steal_time(vcpu);
8424 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8426 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8428 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8429 kvm_pmu_handle_event(vcpu);
8430 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8431 kvm_pmu_deliver_pmi(vcpu);
8432 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8433 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8434 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8435 vcpu->arch.ioapic_handled_vectors)) {
8436 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8437 vcpu->run->eoi.vector =
8438 vcpu->arch.pending_ioapic_eoi;
8443 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8444 vcpu_scan_ioapic(vcpu);
8445 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8446 vcpu_load_eoi_exitmap(vcpu);
8447 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8448 kvm_vcpu_reload_apic_access_page(vcpu);
8449 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8450 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8451 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8455 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8456 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8457 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8461 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8462 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8463 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8469 * KVM_REQ_HV_STIMER has to be processed after
8470 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8471 * depend on the guest clock being up-to-date
8473 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8474 kvm_hv_process_stimers(vcpu);
8475 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8476 kvm_vcpu_update_apicv(vcpu);
8477 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8478 kvm_check_async_pf_completion(vcpu);
8481 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8482 ++vcpu->stat.req_event;
8483 kvm_apic_accept_events(vcpu);
8484 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8489 inject_pending_event(vcpu, &req_immediate_exit);
8491 kvm_x86_ops.enable_irq_window(vcpu);
8493 if (kvm_lapic_enabled(vcpu)) {
8494 update_cr8_intercept(vcpu);
8495 kvm_lapic_sync_to_vapic(vcpu);
8499 r = kvm_mmu_reload(vcpu);
8501 goto cancel_injection;
8506 kvm_x86_ops.prepare_guest_switch(vcpu);
8509 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8510 * IPI are then delayed after guest entry, which ensures that they
8511 * result in virtual interrupt delivery.
8513 local_irq_disable();
8514 vcpu->mode = IN_GUEST_MODE;
8516 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8519 * 1) We should set ->mode before checking ->requests. Please see
8520 * the comment in kvm_vcpu_exiting_guest_mode().
8522 * 2) For APICv, we should set ->mode before checking PID.ON. This
8523 * pairs with the memory barrier implicit in pi_test_and_set_on
8524 * (see vmx_deliver_posted_interrupt).
8526 * 3) This also orders the write to mode from any reads to the page
8527 * tables done while the VCPU is running. Please see the comment
8528 * in kvm_flush_remote_tlbs.
8530 smp_mb__after_srcu_read_unlock();
8533 * This handles the case where a posted interrupt was
8534 * notified with kvm_vcpu_kick.
8536 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8537 kvm_x86_ops.sync_pir_to_irr(vcpu);
8539 if (kvm_vcpu_exit_request(vcpu)) {
8540 vcpu->mode = OUTSIDE_GUEST_MODE;
8544 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8546 goto cancel_injection;
8549 if (req_immediate_exit) {
8550 kvm_make_request(KVM_REQ_EVENT, vcpu);
8551 kvm_x86_ops.request_immediate_exit(vcpu);
8554 trace_kvm_entry(vcpu->vcpu_id);
8556 fpregs_assert_state_consistent();
8557 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8558 switch_fpu_return();
8560 if (unlikely(vcpu->arch.switch_db_regs)) {
8562 set_debugreg(vcpu->arch.eff_db[0], 0);
8563 set_debugreg(vcpu->arch.eff_db[1], 1);
8564 set_debugreg(vcpu->arch.eff_db[2], 2);
8565 set_debugreg(vcpu->arch.eff_db[3], 3);
8566 set_debugreg(vcpu->arch.dr6, 6);
8567 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8570 exit_fastpath = kvm_x86_ops.run(vcpu);
8573 * Do this here before restoring debug registers on the host. And
8574 * since we do this before handling the vmexit, a DR access vmexit
8575 * can (a) read the correct value of the debug registers, (b) set
8576 * KVM_DEBUGREG_WONT_EXIT again.
8578 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8579 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8580 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8581 kvm_update_dr0123(vcpu);
8582 kvm_update_dr7(vcpu);
8583 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8587 * If the guest has used debug registers, at least dr7
8588 * will be disabled while returning to the host.
8589 * If we don't have active breakpoints in the host, we don't
8590 * care about the messed up debug address registers. But if
8591 * we have some of them active, restore the old state.
8593 if (hw_breakpoint_active())
8594 hw_breakpoint_restore();
8596 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
8597 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8599 vcpu->mode = OUTSIDE_GUEST_MODE;
8602 kvm_x86_ops.handle_exit_irqoff(vcpu);
8605 * Consume any pending interrupts, including the possible source of
8606 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8607 * An instruction is required after local_irq_enable() to fully unblock
8608 * interrupts on processors that implement an interrupt shadow, the
8609 * stat.exits increment will do nicely.
8611 kvm_before_interrupt(vcpu);
8614 local_irq_disable();
8615 kvm_after_interrupt(vcpu);
8617 if (lapic_in_kernel(vcpu)) {
8618 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8619 if (delta != S64_MIN) {
8620 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8621 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8628 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8631 * Profile KVM exit RIPs:
8633 if (unlikely(prof_on == KVM_PROFILING)) {
8634 unsigned long rip = kvm_rip_read(vcpu);
8635 profile_hit(KVM_PROFILING, (void *)rip);
8638 if (unlikely(vcpu->arch.tsc_always_catchup))
8639 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8641 if (vcpu->arch.apic_attention)
8642 kvm_lapic_sync_from_vapic(vcpu);
8644 r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
8648 if (req_immediate_exit)
8649 kvm_make_request(KVM_REQ_EVENT, vcpu);
8650 kvm_x86_ops.cancel_injection(vcpu);
8651 if (unlikely(vcpu->arch.apic_attention))
8652 kvm_lapic_sync_from_vapic(vcpu);
8657 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8659 if (!kvm_arch_vcpu_runnable(vcpu) &&
8660 (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
8661 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8662 kvm_vcpu_block(vcpu);
8663 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8665 if (kvm_x86_ops.post_block)
8666 kvm_x86_ops.post_block(vcpu);
8668 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8672 kvm_apic_accept_events(vcpu);
8673 switch(vcpu->arch.mp_state) {
8674 case KVM_MP_STATE_HALTED:
8675 vcpu->arch.pv.pv_unhalted = false;
8676 vcpu->arch.mp_state =
8677 KVM_MP_STATE_RUNNABLE;
8679 case KVM_MP_STATE_RUNNABLE:
8680 vcpu->arch.apf.halted = false;
8682 case KVM_MP_STATE_INIT_RECEIVED:
8690 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8692 if (is_guest_mode(vcpu))
8693 kvm_x86_ops.nested_ops->check_events(vcpu);
8695 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8696 !vcpu->arch.apf.halted);
8699 static int vcpu_run(struct kvm_vcpu *vcpu)
8702 struct kvm *kvm = vcpu->kvm;
8704 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8705 vcpu->arch.l1tf_flush_l1d = true;
8708 if (kvm_vcpu_running(vcpu)) {
8709 r = vcpu_enter_guest(vcpu);
8711 r = vcpu_block(kvm, vcpu);
8717 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8718 if (kvm_cpu_has_pending_timer(vcpu))
8719 kvm_inject_pending_timer_irqs(vcpu);
8721 if (dm_request_for_irq_injection(vcpu) &&
8722 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8724 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8725 ++vcpu->stat.request_irq_exits;
8729 if (__xfer_to_guest_mode_work_pending()) {
8730 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8731 r = xfer_to_guest_mode_handle_work(vcpu);
8734 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8738 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8743 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8747 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8748 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8749 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8753 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8755 BUG_ON(!vcpu->arch.pio.count);
8757 return complete_emulated_io(vcpu);
8761 * Implements the following, as a state machine:
8765 * for each mmio piece in the fragment
8773 * for each mmio piece in the fragment
8778 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8780 struct kvm_run *run = vcpu->run;
8781 struct kvm_mmio_fragment *frag;
8784 BUG_ON(!vcpu->mmio_needed);
8786 /* Complete previous fragment */
8787 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8788 len = min(8u, frag->len);
8789 if (!vcpu->mmio_is_write)
8790 memcpy(frag->data, run->mmio.data, len);
8792 if (frag->len <= 8) {
8793 /* Switch to the next fragment. */
8795 vcpu->mmio_cur_fragment++;
8797 /* Go forward to the next mmio piece. */
8803 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8804 vcpu->mmio_needed = 0;
8806 /* FIXME: return into emulator if single-stepping. */
8807 if (vcpu->mmio_is_write)
8809 vcpu->mmio_read_completed = 1;
8810 return complete_emulated_io(vcpu);
8813 run->exit_reason = KVM_EXIT_MMIO;
8814 run->mmio.phys_addr = frag->gpa;
8815 if (vcpu->mmio_is_write)
8816 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8817 run->mmio.len = min(8u, frag->len);
8818 run->mmio.is_write = vcpu->mmio_is_write;
8819 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8823 static void kvm_save_current_fpu(struct fpu *fpu)
8826 * If the target FPU state is not resident in the CPU registers, just
8827 * memcpy() from current, else save CPU state directly to the target.
8829 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8830 memcpy(&fpu->state, ¤t->thread.fpu.state,
8831 fpu_kernel_xstate_size);
8833 copy_fpregs_to_fpstate(fpu);
8836 /* Swap (qemu) user FPU context for the guest FPU context. */
8837 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8841 kvm_save_current_fpu(vcpu->arch.user_fpu);
8843 /* PKRU is separately restored in kvm_x86_ops.run. */
8844 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8845 ~XFEATURE_MASK_PKRU);
8847 fpregs_mark_activate();
8853 /* When vcpu_run ends, restore user space FPU context. */
8854 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8858 kvm_save_current_fpu(vcpu->arch.guest_fpu);
8860 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8862 fpregs_mark_activate();
8865 ++vcpu->stat.fpu_reload;
8869 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
8871 struct kvm_run *kvm_run = vcpu->run;
8875 kvm_sigset_activate(vcpu);
8876 kvm_load_guest_fpu(vcpu);
8878 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8879 if (kvm_run->immediate_exit) {
8883 kvm_vcpu_block(vcpu);
8884 kvm_apic_accept_events(vcpu);
8885 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8887 if (signal_pending(current)) {
8889 kvm_run->exit_reason = KVM_EXIT_INTR;
8890 ++vcpu->stat.signal_exits;
8895 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8900 if (kvm_run->kvm_dirty_regs) {
8901 r = sync_regs(vcpu);
8906 /* re-sync apic's tpr */
8907 if (!lapic_in_kernel(vcpu)) {
8908 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8914 if (unlikely(vcpu->arch.complete_userspace_io)) {
8915 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8916 vcpu->arch.complete_userspace_io = NULL;
8921 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8923 if (kvm_run->immediate_exit)
8929 kvm_put_guest_fpu(vcpu);
8930 if (kvm_run->kvm_valid_regs)
8932 post_kvm_run_save(vcpu);
8933 kvm_sigset_deactivate(vcpu);
8939 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8941 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8943 * We are here if userspace calls get_regs() in the middle of
8944 * instruction emulation. Registers state needs to be copied
8945 * back from emulation context to vcpu. Userspace shouldn't do
8946 * that usually, but some bad designed PV devices (vmware
8947 * backdoor interface) need this to work
8949 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
8950 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8952 regs->rax = kvm_rax_read(vcpu);
8953 regs->rbx = kvm_rbx_read(vcpu);
8954 regs->rcx = kvm_rcx_read(vcpu);
8955 regs->rdx = kvm_rdx_read(vcpu);
8956 regs->rsi = kvm_rsi_read(vcpu);
8957 regs->rdi = kvm_rdi_read(vcpu);
8958 regs->rsp = kvm_rsp_read(vcpu);
8959 regs->rbp = kvm_rbp_read(vcpu);
8960 #ifdef CONFIG_X86_64
8961 regs->r8 = kvm_r8_read(vcpu);
8962 regs->r9 = kvm_r9_read(vcpu);
8963 regs->r10 = kvm_r10_read(vcpu);
8964 regs->r11 = kvm_r11_read(vcpu);
8965 regs->r12 = kvm_r12_read(vcpu);
8966 regs->r13 = kvm_r13_read(vcpu);
8967 regs->r14 = kvm_r14_read(vcpu);
8968 regs->r15 = kvm_r15_read(vcpu);
8971 regs->rip = kvm_rip_read(vcpu);
8972 regs->rflags = kvm_get_rflags(vcpu);
8975 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8978 __get_regs(vcpu, regs);
8983 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8985 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8986 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8988 kvm_rax_write(vcpu, regs->rax);
8989 kvm_rbx_write(vcpu, regs->rbx);
8990 kvm_rcx_write(vcpu, regs->rcx);
8991 kvm_rdx_write(vcpu, regs->rdx);
8992 kvm_rsi_write(vcpu, regs->rsi);
8993 kvm_rdi_write(vcpu, regs->rdi);
8994 kvm_rsp_write(vcpu, regs->rsp);
8995 kvm_rbp_write(vcpu, regs->rbp);
8996 #ifdef CONFIG_X86_64
8997 kvm_r8_write(vcpu, regs->r8);
8998 kvm_r9_write(vcpu, regs->r9);
8999 kvm_r10_write(vcpu, regs->r10);
9000 kvm_r11_write(vcpu, regs->r11);
9001 kvm_r12_write(vcpu, regs->r12);
9002 kvm_r13_write(vcpu, regs->r13);
9003 kvm_r14_write(vcpu, regs->r14);
9004 kvm_r15_write(vcpu, regs->r15);
9007 kvm_rip_write(vcpu, regs->rip);
9008 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9010 vcpu->arch.exception.pending = false;
9012 kvm_make_request(KVM_REQ_EVENT, vcpu);
9015 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9018 __set_regs(vcpu, regs);
9023 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9025 struct kvm_segment cs;
9027 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9031 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9033 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9037 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9038 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9039 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9040 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9041 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9042 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9044 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9045 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9047 kvm_x86_ops.get_idt(vcpu, &dt);
9048 sregs->idt.limit = dt.size;
9049 sregs->idt.base = dt.address;
9050 kvm_x86_ops.get_gdt(vcpu, &dt);
9051 sregs->gdt.limit = dt.size;
9052 sregs->gdt.base = dt.address;
9054 sregs->cr0 = kvm_read_cr0(vcpu);
9055 sregs->cr2 = vcpu->arch.cr2;
9056 sregs->cr3 = kvm_read_cr3(vcpu);
9057 sregs->cr4 = kvm_read_cr4(vcpu);
9058 sregs->cr8 = kvm_get_cr8(vcpu);
9059 sregs->efer = vcpu->arch.efer;
9060 sregs->apic_base = kvm_get_apic_base(vcpu);
9062 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9064 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9065 set_bit(vcpu->arch.interrupt.nr,
9066 (unsigned long *)sregs->interrupt_bitmap);
9069 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9070 struct kvm_sregs *sregs)
9073 __get_sregs(vcpu, sregs);
9078 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9079 struct kvm_mp_state *mp_state)
9082 if (kvm_mpx_supported())
9083 kvm_load_guest_fpu(vcpu);
9085 kvm_apic_accept_events(vcpu);
9086 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
9087 vcpu->arch.pv.pv_unhalted)
9088 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9090 mp_state->mp_state = vcpu->arch.mp_state;
9092 if (kvm_mpx_supported())
9093 kvm_put_guest_fpu(vcpu);
9098 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9099 struct kvm_mp_state *mp_state)
9105 if (!lapic_in_kernel(vcpu) &&
9106 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9110 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9111 * INIT state; latched init should be reported using
9112 * KVM_SET_VCPU_EVENTS, so reject it here.
9114 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9115 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9116 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9119 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9120 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9121 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9123 vcpu->arch.mp_state = mp_state->mp_state;
9124 kvm_make_request(KVM_REQ_EVENT, vcpu);
9132 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9133 int reason, bool has_error_code, u32 error_code)
9135 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9138 init_emulate_ctxt(vcpu);
9140 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9141 has_error_code, error_code);
9143 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9144 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9145 vcpu->run->internal.ndata = 0;
9149 kvm_rip_write(vcpu, ctxt->eip);
9150 kvm_set_rflags(vcpu, ctxt->eflags);
9153 EXPORT_SYMBOL_GPL(kvm_task_switch);
9155 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9157 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9159 * When EFER.LME and CR0.PG are set, the processor is in
9160 * 64-bit mode (though maybe in a 32-bit code segment).
9161 * CR4.PAE and EFER.LMA must be set.
9163 if (!(sregs->cr4 & X86_CR4_PAE)
9164 || !(sregs->efer & EFER_LMA))
9168 * Not in 64-bit mode: EFER.LMA is clear and the code
9169 * segment cannot be 64-bit.
9171 if (sregs->efer & EFER_LMA || sregs->cs.l)
9175 return kvm_valid_cr4(vcpu, sregs->cr4);
9178 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9180 struct msr_data apic_base_msr;
9181 int mmu_reset_needed = 0;
9182 int cpuid_update_needed = 0;
9183 int pending_vec, max_bits, idx;
9187 if (kvm_valid_sregs(vcpu, sregs))
9190 apic_base_msr.data = sregs->apic_base;
9191 apic_base_msr.host_initiated = true;
9192 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9195 dt.size = sregs->idt.limit;
9196 dt.address = sregs->idt.base;
9197 kvm_x86_ops.set_idt(vcpu, &dt);
9198 dt.size = sregs->gdt.limit;
9199 dt.address = sregs->gdt.base;
9200 kvm_x86_ops.set_gdt(vcpu, &dt);
9202 vcpu->arch.cr2 = sregs->cr2;
9203 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9204 vcpu->arch.cr3 = sregs->cr3;
9205 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9207 kvm_set_cr8(vcpu, sregs->cr8);
9209 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9210 kvm_x86_ops.set_efer(vcpu, sregs->efer);
9212 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9213 kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9214 vcpu->arch.cr0 = sregs->cr0;
9216 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9217 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9218 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9219 kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9220 if (cpuid_update_needed)
9221 kvm_update_cpuid_runtime(vcpu);
9223 idx = srcu_read_lock(&vcpu->kvm->srcu);
9224 if (is_pae_paging(vcpu)) {
9225 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9226 mmu_reset_needed = 1;
9228 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9230 if (mmu_reset_needed)
9231 kvm_mmu_reset_context(vcpu);
9233 max_bits = KVM_NR_INTERRUPTS;
9234 pending_vec = find_first_bit(
9235 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9236 if (pending_vec < max_bits) {
9237 kvm_queue_interrupt(vcpu, pending_vec, false);
9238 pr_debug("Set back pending irq %d\n", pending_vec);
9241 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9242 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9243 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9244 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9245 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9246 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9248 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9249 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9251 update_cr8_intercept(vcpu);
9253 /* Older userspace won't unhalt the vcpu on reset. */
9254 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9255 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9257 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9259 kvm_make_request(KVM_REQ_EVENT, vcpu);
9266 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9267 struct kvm_sregs *sregs)
9272 ret = __set_sregs(vcpu, sregs);
9277 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9278 struct kvm_guest_debug *dbg)
9280 unsigned long rflags;
9285 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9287 if (vcpu->arch.exception.pending)
9289 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9290 kvm_queue_exception(vcpu, DB_VECTOR);
9292 kvm_queue_exception(vcpu, BP_VECTOR);
9296 * Read rflags as long as potentially injected trace flags are still
9299 rflags = kvm_get_rflags(vcpu);
9301 vcpu->guest_debug = dbg->control;
9302 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9303 vcpu->guest_debug = 0;
9305 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9306 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9307 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9308 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9310 for (i = 0; i < KVM_NR_DB_REGS; i++)
9311 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9313 kvm_update_dr7(vcpu);
9315 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9316 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9317 get_segment_base(vcpu, VCPU_SREG_CS);
9320 * Trigger an rflags update that will inject or remove the trace
9323 kvm_set_rflags(vcpu, rflags);
9325 kvm_x86_ops.update_exception_bitmap(vcpu);
9335 * Translate a guest virtual address to a guest physical address.
9337 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9338 struct kvm_translation *tr)
9340 unsigned long vaddr = tr->linear_address;
9346 idx = srcu_read_lock(&vcpu->kvm->srcu);
9347 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9348 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9349 tr->physical_address = gpa;
9350 tr->valid = gpa != UNMAPPED_GVA;
9358 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9360 struct fxregs_state *fxsave;
9364 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9365 memcpy(fpu->fpr, fxsave->st_space, 128);
9366 fpu->fcw = fxsave->cwd;
9367 fpu->fsw = fxsave->swd;
9368 fpu->ftwx = fxsave->twd;
9369 fpu->last_opcode = fxsave->fop;
9370 fpu->last_ip = fxsave->rip;
9371 fpu->last_dp = fxsave->rdp;
9372 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9378 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9380 struct fxregs_state *fxsave;
9384 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9386 memcpy(fxsave->st_space, fpu->fpr, 128);
9387 fxsave->cwd = fpu->fcw;
9388 fxsave->swd = fpu->fsw;
9389 fxsave->twd = fpu->ftwx;
9390 fxsave->fop = fpu->last_opcode;
9391 fxsave->rip = fpu->last_ip;
9392 fxsave->rdp = fpu->last_dp;
9393 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9399 static void store_regs(struct kvm_vcpu *vcpu)
9401 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9403 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9404 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9406 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9407 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9409 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9410 kvm_vcpu_ioctl_x86_get_vcpu_events(
9411 vcpu, &vcpu->run->s.regs.events);
9414 static int sync_regs(struct kvm_vcpu *vcpu)
9416 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9419 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9420 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9421 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9423 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9424 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9426 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9428 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9429 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9430 vcpu, &vcpu->run->s.regs.events))
9432 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9438 static void fx_init(struct kvm_vcpu *vcpu)
9440 fpstate_init(&vcpu->arch.guest_fpu->state);
9441 if (boot_cpu_has(X86_FEATURE_XSAVES))
9442 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9443 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9446 * Ensure guest xcr0 is valid for loading
9448 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9450 vcpu->arch.cr0 |= X86_CR0_ET;
9453 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9455 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9456 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9457 "guest TSC will not be reliable\n");
9462 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9467 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9468 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9470 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9472 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9474 r = kvm_mmu_create(vcpu);
9478 if (irqchip_in_kernel(vcpu->kvm)) {
9479 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9481 goto fail_mmu_destroy;
9482 if (kvm_apicv_activated(vcpu->kvm))
9483 vcpu->arch.apicv_active = true;
9485 static_key_slow_inc(&kvm_no_apic_vcpu);
9489 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9491 goto fail_free_lapic;
9492 vcpu->arch.pio_data = page_address(page);
9494 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9495 GFP_KERNEL_ACCOUNT);
9496 if (!vcpu->arch.mce_banks)
9497 goto fail_free_pio_data;
9498 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9500 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9501 GFP_KERNEL_ACCOUNT))
9502 goto fail_free_mce_banks;
9504 if (!alloc_emulate_ctxt(vcpu))
9505 goto free_wbinvd_dirty_mask;
9507 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9508 GFP_KERNEL_ACCOUNT);
9509 if (!vcpu->arch.user_fpu) {
9510 pr_err("kvm: failed to allocate userspace's fpu\n");
9511 goto free_emulate_ctxt;
9514 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9515 GFP_KERNEL_ACCOUNT);
9516 if (!vcpu->arch.guest_fpu) {
9517 pr_err("kvm: failed to allocate vcpu's fpu\n");
9522 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9524 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9526 kvm_async_pf_hash_reset(vcpu);
9529 vcpu->arch.pending_external_vector = -1;
9530 vcpu->arch.preempted_in_kernel = false;
9532 kvm_hv_vcpu_init(vcpu);
9534 r = kvm_x86_ops.vcpu_create(vcpu);
9536 goto free_guest_fpu;
9538 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9539 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9540 kvm_vcpu_mtrr_init(vcpu);
9542 kvm_vcpu_reset(vcpu, false);
9543 kvm_init_mmu(vcpu, false);
9548 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9550 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9552 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9553 free_wbinvd_dirty_mask:
9554 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9555 fail_free_mce_banks:
9556 kfree(vcpu->arch.mce_banks);
9558 free_page((unsigned long)vcpu->arch.pio_data);
9560 kvm_free_lapic(vcpu);
9562 kvm_mmu_destroy(vcpu);
9566 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9568 struct msr_data msr;
9569 struct kvm *kvm = vcpu->kvm;
9571 kvm_hv_vcpu_postcreate(vcpu);
9573 if (mutex_lock_killable(&vcpu->mutex))
9577 msr.index = MSR_IA32_TSC;
9578 msr.host_initiated = true;
9579 kvm_write_tsc(vcpu, &msr);
9582 /* poll control enabled by default */
9583 vcpu->arch.msr_kvm_poll_control = 1;
9585 mutex_unlock(&vcpu->mutex);
9587 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9588 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9589 KVMCLOCK_SYNC_PERIOD);
9592 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9594 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9597 kvm_release_pfn(cache->pfn, cache->dirty, cache);
9599 kvmclock_reset(vcpu);
9601 kvm_x86_ops.vcpu_free(vcpu);
9603 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9604 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9605 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9606 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9608 kvm_hv_vcpu_uninit(vcpu);
9609 kvm_pmu_destroy(vcpu);
9610 kfree(vcpu->arch.mce_banks);
9611 kvm_free_lapic(vcpu);
9612 idx = srcu_read_lock(&vcpu->kvm->srcu);
9613 kvm_mmu_destroy(vcpu);
9614 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9615 free_page((unsigned long)vcpu->arch.pio_data);
9616 if (!lapic_in_kernel(vcpu))
9617 static_key_slow_dec(&kvm_no_apic_vcpu);
9620 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9622 kvm_lapic_reset(vcpu, init_event);
9624 vcpu->arch.hflags = 0;
9626 vcpu->arch.smi_pending = 0;
9627 vcpu->arch.smi_count = 0;
9628 atomic_set(&vcpu->arch.nmi_queued, 0);
9629 vcpu->arch.nmi_pending = 0;
9630 vcpu->arch.nmi_injected = false;
9631 kvm_clear_interrupt_queue(vcpu);
9632 kvm_clear_exception_queue(vcpu);
9634 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9635 kvm_update_dr0123(vcpu);
9636 vcpu->arch.dr6 = DR6_INIT;
9637 vcpu->arch.dr7 = DR7_FIXED_1;
9638 kvm_update_dr7(vcpu);
9642 kvm_make_request(KVM_REQ_EVENT, vcpu);
9643 vcpu->arch.apf.msr_en_val = 0;
9644 vcpu->arch.apf.msr_int_val = 0;
9645 vcpu->arch.st.msr_val = 0;
9647 kvmclock_reset(vcpu);
9649 kvm_clear_async_pf_completion_queue(vcpu);
9650 kvm_async_pf_hash_reset(vcpu);
9651 vcpu->arch.apf.halted = false;
9653 if (kvm_mpx_supported()) {
9654 void *mpx_state_buffer;
9657 * To avoid have the INIT path from kvm_apic_has_events() that be
9658 * called with loaded FPU and does not let userspace fix the state.
9661 kvm_put_guest_fpu(vcpu);
9662 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9664 if (mpx_state_buffer)
9665 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9666 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9668 if (mpx_state_buffer)
9669 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9671 kvm_load_guest_fpu(vcpu);
9675 kvm_pmu_reset(vcpu);
9676 vcpu->arch.smbase = 0x30000;
9678 vcpu->arch.msr_misc_features_enables = 0;
9680 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9683 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9684 vcpu->arch.regs_avail = ~0;
9685 vcpu->arch.regs_dirty = ~0;
9687 vcpu->arch.ia32_xss = 0;
9689 kvm_x86_ops.vcpu_reset(vcpu, init_event);
9692 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9694 struct kvm_segment cs;
9696 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9697 cs.selector = vector << 8;
9698 cs.base = vector << 12;
9699 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9700 kvm_rip_write(vcpu, 0);
9703 int kvm_arch_hardware_enable(void)
9706 struct kvm_vcpu *vcpu;
9711 bool stable, backwards_tsc = false;
9713 kvm_shared_msr_cpu_online();
9714 ret = kvm_x86_ops.hardware_enable();
9718 local_tsc = rdtsc();
9719 stable = !kvm_check_tsc_unstable();
9720 list_for_each_entry(kvm, &vm_list, vm_list) {
9721 kvm_for_each_vcpu(i, vcpu, kvm) {
9722 if (!stable && vcpu->cpu == smp_processor_id())
9723 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9724 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9725 backwards_tsc = true;
9726 if (vcpu->arch.last_host_tsc > max_tsc)
9727 max_tsc = vcpu->arch.last_host_tsc;
9733 * Sometimes, even reliable TSCs go backwards. This happens on
9734 * platforms that reset TSC during suspend or hibernate actions, but
9735 * maintain synchronization. We must compensate. Fortunately, we can
9736 * detect that condition here, which happens early in CPU bringup,
9737 * before any KVM threads can be running. Unfortunately, we can't
9738 * bring the TSCs fully up to date with real time, as we aren't yet far
9739 * enough into CPU bringup that we know how much real time has actually
9740 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9741 * variables that haven't been updated yet.
9743 * So we simply find the maximum observed TSC above, then record the
9744 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9745 * the adjustment will be applied. Note that we accumulate
9746 * adjustments, in case multiple suspend cycles happen before some VCPU
9747 * gets a chance to run again. In the event that no KVM threads get a
9748 * chance to run, we will miss the entire elapsed period, as we'll have
9749 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9750 * loose cycle time. This isn't too big a deal, since the loss will be
9751 * uniform across all VCPUs (not to mention the scenario is extremely
9752 * unlikely). It is possible that a second hibernate recovery happens
9753 * much faster than a first, causing the observed TSC here to be
9754 * smaller; this would require additional padding adjustment, which is
9755 * why we set last_host_tsc to the local tsc observed here.
9757 * N.B. - this code below runs only on platforms with reliable TSC,
9758 * as that is the only way backwards_tsc is set above. Also note
9759 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9760 * have the same delta_cyc adjustment applied if backwards_tsc
9761 * is detected. Note further, this adjustment is only done once,
9762 * as we reset last_host_tsc on all VCPUs to stop this from being
9763 * called multiple times (one for each physical CPU bringup).
9765 * Platforms with unreliable TSCs don't have to deal with this, they
9766 * will be compensated by the logic in vcpu_load, which sets the TSC to
9767 * catchup mode. This will catchup all VCPUs to real time, but cannot
9768 * guarantee that they stay in perfect synchronization.
9770 if (backwards_tsc) {
9771 u64 delta_cyc = max_tsc - local_tsc;
9772 list_for_each_entry(kvm, &vm_list, vm_list) {
9773 kvm->arch.backwards_tsc_observed = true;
9774 kvm_for_each_vcpu(i, vcpu, kvm) {
9775 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9776 vcpu->arch.last_host_tsc = local_tsc;
9777 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9781 * We have to disable TSC offset matching.. if you were
9782 * booting a VM while issuing an S4 host suspend....
9783 * you may have some problem. Solving this issue is
9784 * left as an exercise to the reader.
9786 kvm->arch.last_tsc_nsec = 0;
9787 kvm->arch.last_tsc_write = 0;
9794 void kvm_arch_hardware_disable(void)
9796 kvm_x86_ops.hardware_disable();
9797 drop_user_return_notifiers();
9800 int kvm_arch_hardware_setup(void *opaque)
9802 struct kvm_x86_init_ops *ops = opaque;
9805 rdmsrl_safe(MSR_EFER, &host_efer);
9807 if (boot_cpu_has(X86_FEATURE_XSAVES))
9808 rdmsrl(MSR_IA32_XSS, host_xss);
9810 r = ops->hardware_setup();
9814 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9816 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9819 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9820 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9821 #undef __kvm_cpu_cap_has
9823 if (kvm_has_tsc_control) {
9825 * Make sure the user can only configure tsc_khz values that
9826 * fit into a signed integer.
9827 * A min value is not calculated because it will always
9828 * be 1 on all machines.
9830 u64 max = min(0x7fffffffULL,
9831 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9832 kvm_max_guest_tsc_khz = max;
9834 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9837 kvm_init_msr_list();
9841 void kvm_arch_hardware_unsetup(void)
9843 kvm_x86_ops.hardware_unsetup();
9846 int kvm_arch_check_processor_compat(void *opaque)
9848 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9849 struct kvm_x86_init_ops *ops = opaque;
9851 WARN_ON(!irqs_disabled());
9853 if (__cr4_reserved_bits(cpu_has, c) !=
9854 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9857 return ops->check_processor_compatibility();
9860 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9862 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9864 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9866 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9868 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9871 struct static_key kvm_no_apic_vcpu __read_mostly;
9872 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9874 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9876 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9878 vcpu->arch.l1tf_flush_l1d = true;
9879 if (pmu->version && unlikely(pmu->event_count)) {
9880 pmu->need_cleanup = true;
9881 kvm_make_request(KVM_REQ_PMU, vcpu);
9883 kvm_x86_ops.sched_in(vcpu, cpu);
9886 void kvm_arch_free_vm(struct kvm *kvm)
9888 kfree(kvm->arch.hyperv.hv_pa_pg);
9893 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9898 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9899 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9900 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9901 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9902 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9903 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9905 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9906 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9907 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9908 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9909 &kvm->arch.irq_sources_bitmap);
9911 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9912 mutex_init(&kvm->arch.apic_map_lock);
9913 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9915 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9916 pvclock_update_vm_gtod_copy(kvm);
9918 kvm->arch.guest_can_read_msr_platform_info = true;
9920 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9921 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9923 kvm_hv_init_vm(kvm);
9924 kvm_page_track_init(kvm);
9925 kvm_mmu_init_vm(kvm);
9927 return kvm_x86_ops.vm_init(kvm);
9930 int kvm_arch_post_init_vm(struct kvm *kvm)
9932 return kvm_mmu_post_init_vm(kvm);
9935 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9938 kvm_mmu_unload(vcpu);
9942 static void kvm_free_vcpus(struct kvm *kvm)
9945 struct kvm_vcpu *vcpu;
9948 * Unpin any mmu pages first.
9950 kvm_for_each_vcpu(i, vcpu, kvm) {
9951 kvm_clear_async_pf_completion_queue(vcpu);
9952 kvm_unload_vcpu_mmu(vcpu);
9954 kvm_for_each_vcpu(i, vcpu, kvm)
9955 kvm_vcpu_destroy(vcpu);
9957 mutex_lock(&kvm->lock);
9958 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9959 kvm->vcpus[i] = NULL;
9961 atomic_set(&kvm->online_vcpus, 0);
9962 mutex_unlock(&kvm->lock);
9965 void kvm_arch_sync_events(struct kvm *kvm)
9967 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9968 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9972 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9975 unsigned long hva, old_npages;
9976 struct kvm_memslots *slots = kvm_memslots(kvm);
9977 struct kvm_memory_slot *slot;
9979 /* Called with kvm->slots_lock held. */
9980 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9983 slot = id_to_memslot(slots, id);
9985 if (slot && slot->npages)
9989 * MAP_SHARED to prevent internal slot pages from being moved
9992 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9993 MAP_SHARED | MAP_ANONYMOUS, 0);
9994 if (IS_ERR((void *)hva))
9995 return PTR_ERR((void *)hva);
9997 if (!slot || !slot->npages)
10000 old_npages = slot->npages;
10004 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
10005 struct kvm_userspace_memory_region m;
10007 m.slot = id | (i << 16);
10009 m.guest_phys_addr = gpa;
10010 m.userspace_addr = hva;
10011 m.memory_size = size;
10012 r = __kvm_set_memory_region(kvm, &m);
10018 vm_munmap(hva, old_npages * PAGE_SIZE);
10022 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10024 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10026 kvm_mmu_pre_destroy_vm(kvm);
10029 void kvm_arch_destroy_vm(struct kvm *kvm)
10031 if (current->mm == kvm->mm) {
10033 * Free memory regions allocated on behalf of userspace,
10034 * unless the the memory map has changed due to process exit
10037 mutex_lock(&kvm->slots_lock);
10038 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10040 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10042 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10043 mutex_unlock(&kvm->slots_lock);
10045 if (kvm_x86_ops.vm_destroy)
10046 kvm_x86_ops.vm_destroy(kvm);
10047 kvm_pic_destroy(kvm);
10048 kvm_ioapic_destroy(kvm);
10049 kvm_free_vcpus(kvm);
10050 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10051 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10052 kvm_mmu_uninit_vm(kvm);
10053 kvm_page_track_cleanup(kvm);
10054 kvm_hv_destroy_vm(kvm);
10057 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10061 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10062 kvfree(slot->arch.rmap[i]);
10063 slot->arch.rmap[i] = NULL;
10068 kvfree(slot->arch.lpage_info[i - 1]);
10069 slot->arch.lpage_info[i - 1] = NULL;
10072 kvm_page_track_free_memslot(slot);
10075 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10076 unsigned long npages)
10081 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
10082 * old arrays will be freed by __kvm_set_memory_region() if installing
10083 * the new memslot is successful.
10085 memset(&slot->arch, 0, sizeof(slot->arch));
10087 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10088 struct kvm_lpage_info *linfo;
10089 unsigned long ugfn;
10093 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10094 slot->base_gfn, level) + 1;
10096 slot->arch.rmap[i] =
10097 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10098 GFP_KERNEL_ACCOUNT);
10099 if (!slot->arch.rmap[i])
10104 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10108 slot->arch.lpage_info[i - 1] = linfo;
10110 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10111 linfo[0].disallow_lpage = 1;
10112 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10113 linfo[lpages - 1].disallow_lpage = 1;
10114 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10116 * If the gfn and userspace address are not aligned wrt each
10117 * other, disable large page support for this slot.
10119 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10122 for (j = 0; j < lpages; ++j)
10123 linfo[j].disallow_lpage = 1;
10127 if (kvm_page_track_create_memslot(slot, npages))
10133 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10134 kvfree(slot->arch.rmap[i]);
10135 slot->arch.rmap[i] = NULL;
10139 kvfree(slot->arch.lpage_info[i - 1]);
10140 slot->arch.lpage_info[i - 1] = NULL;
10145 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10147 struct kvm_vcpu *vcpu;
10151 * memslots->generation has been incremented.
10152 * mmio generation may have reached its maximum value.
10154 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10156 /* Force re-initialization of steal_time cache */
10157 kvm_for_each_vcpu(i, vcpu, kvm)
10158 kvm_vcpu_kick(vcpu);
10161 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10162 struct kvm_memory_slot *memslot,
10163 const struct kvm_userspace_memory_region *mem,
10164 enum kvm_mr_change change)
10166 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10167 return kvm_alloc_memslot_metadata(memslot,
10168 mem->memory_size >> PAGE_SHIFT);
10172 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10173 struct kvm_memory_slot *old,
10174 struct kvm_memory_slot *new,
10175 enum kvm_mr_change change)
10178 * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10179 * See comments below.
10181 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10185 * Dirty logging tracks sptes in 4k granularity, meaning that large
10186 * sptes have to be split. If live migration is successful, the guest
10187 * in the source machine will be destroyed and large sptes will be
10188 * created in the destination. However, if the guest continues to run
10189 * in the source machine (for example if live migration fails), small
10190 * sptes will remain around and cause bad performance.
10192 * Scan sptes if dirty logging has been stopped, dropping those
10193 * which can be collapsed into a single large-page spte. Later
10194 * page faults will create the large-page sptes.
10196 * There is no need to do this in any of the following cases:
10197 * CREATE: No dirty mappings will already exist.
10198 * MOVE/DELETE: The old mappings will already have been cleaned up by
10199 * kvm_arch_flush_shadow_memslot()
10201 if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10202 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10203 kvm_mmu_zap_collapsible_sptes(kvm, new);
10206 * Enable or disable dirty logging for the slot.
10208 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10209 * slot have been zapped so no dirty logging updates are needed for
10211 * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10212 * any mappings that might be created in it will consume the
10213 * properties of the new slot and do not need to be updated here.
10215 * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10216 * called to enable/disable dirty logging.
10218 * When disabling dirty logging with PML enabled, the D-bit is set
10219 * for sptes in the slot in order to prevent unnecessary GPA
10220 * logging in the PML buffer (and potential PML buffer full VMEXIT).
10221 * This guarantees leaving PML enabled for the guest's lifetime
10222 * won't have any additional overhead from PML when the guest is
10223 * running with dirty logging disabled.
10225 * When enabling dirty logging, large sptes are write-protected
10226 * so they can be split on first write. New large sptes cannot
10227 * be created for this slot until the end of the logging.
10228 * See the comments in fast_page_fault().
10229 * For small sptes, nothing is done if the dirty log is in the
10230 * initial-all-set state. Otherwise, depending on whether pml
10231 * is enabled the D-bit or the W-bit will be cleared.
10233 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10234 if (kvm_x86_ops.slot_enable_log_dirty) {
10235 kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10238 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10239 PG_LEVEL_2M : PG_LEVEL_4K;
10242 * If we're with initial-all-set, we don't need
10243 * to write protect any small page because
10244 * they're reported as dirty already. However
10245 * we still need to write-protect huge pages
10246 * so that the page split can happen lazily on
10247 * the first write to the huge page.
10249 kvm_mmu_slot_remove_write_access(kvm, new, level);
10252 if (kvm_x86_ops.slot_disable_log_dirty)
10253 kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10257 void kvm_arch_commit_memory_region(struct kvm *kvm,
10258 const struct kvm_userspace_memory_region *mem,
10259 struct kvm_memory_slot *old,
10260 const struct kvm_memory_slot *new,
10261 enum kvm_mr_change change)
10263 if (!kvm->arch.n_requested_mmu_pages)
10264 kvm_mmu_change_mmu_pages(kvm,
10265 kvm_mmu_calculate_default_mmu_pages(kvm));
10268 * FIXME: const-ify all uses of struct kvm_memory_slot.
10270 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10272 /* Free the arrays associated with the old memslot. */
10273 if (change == KVM_MR_MOVE)
10274 kvm_arch_free_memslot(kvm, old);
10277 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10279 kvm_mmu_zap_all(kvm);
10282 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10283 struct kvm_memory_slot *slot)
10285 kvm_page_track_flush_slot(kvm, slot);
10288 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10290 return (is_guest_mode(vcpu) &&
10291 kvm_x86_ops.guest_apic_has_interrupt &&
10292 kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10295 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10297 if (!list_empty_careful(&vcpu->async_pf.done))
10300 if (kvm_apic_has_events(vcpu))
10303 if (vcpu->arch.pv.pv_unhalted)
10306 if (vcpu->arch.exception.pending)
10309 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10310 (vcpu->arch.nmi_pending &&
10311 kvm_x86_ops.nmi_allowed(vcpu, false)))
10314 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10315 (vcpu->arch.smi_pending &&
10316 kvm_x86_ops.smi_allowed(vcpu, false)))
10319 if (kvm_arch_interrupt_allowed(vcpu) &&
10320 (kvm_cpu_has_interrupt(vcpu) ||
10321 kvm_guest_apic_has_interrupt(vcpu)))
10324 if (kvm_hv_has_stimer_pending(vcpu))
10327 if (is_guest_mode(vcpu) &&
10328 kvm_x86_ops.nested_ops->hv_timer_pending &&
10329 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10335 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10337 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10340 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10342 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10345 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10346 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10347 kvm_test_request(KVM_REQ_EVENT, vcpu))
10350 if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10356 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10358 return vcpu->arch.preempted_in_kernel;
10361 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10363 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10366 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10368 return kvm_x86_ops.interrupt_allowed(vcpu, false);
10371 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10373 if (is_64_bit_mode(vcpu))
10374 return kvm_rip_read(vcpu);
10375 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10376 kvm_rip_read(vcpu));
10378 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10380 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10382 return kvm_get_linear_rip(vcpu) == linear_rip;
10384 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10386 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10388 unsigned long rflags;
10390 rflags = kvm_x86_ops.get_rflags(vcpu);
10391 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10392 rflags &= ~X86_EFLAGS_TF;
10395 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10397 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10399 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10400 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10401 rflags |= X86_EFLAGS_TF;
10402 kvm_x86_ops.set_rflags(vcpu, rflags);
10405 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10407 __kvm_set_rflags(vcpu, rflags);
10408 kvm_make_request(KVM_REQ_EVENT, vcpu);
10410 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10412 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10416 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10420 r = kvm_mmu_reload(vcpu);
10424 if (!vcpu->arch.mmu->direct_map &&
10425 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10428 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10431 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10433 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10435 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10438 static inline u32 kvm_async_pf_next_probe(u32 key)
10440 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10443 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10445 u32 key = kvm_async_pf_hash_fn(gfn);
10447 while (vcpu->arch.apf.gfns[key] != ~0)
10448 key = kvm_async_pf_next_probe(key);
10450 vcpu->arch.apf.gfns[key] = gfn;
10453 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10456 u32 key = kvm_async_pf_hash_fn(gfn);
10458 for (i = 0; i < ASYNC_PF_PER_VCPU &&
10459 (vcpu->arch.apf.gfns[key] != gfn &&
10460 vcpu->arch.apf.gfns[key] != ~0); i++)
10461 key = kvm_async_pf_next_probe(key);
10466 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10468 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10471 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10475 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10477 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
10481 vcpu->arch.apf.gfns[i] = ~0;
10483 j = kvm_async_pf_next_probe(j);
10484 if (vcpu->arch.apf.gfns[j] == ~0)
10486 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10488 * k lies cyclically in ]i,j]
10490 * |....j i.k.| or |.k..j i...|
10492 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10493 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10498 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
10500 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
10502 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
10506 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
10508 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10510 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10511 &token, offset, sizeof(token));
10514 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
10516 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10519 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10520 &val, offset, sizeof(val)))
10526 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10528 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10531 if (!kvm_pv_async_pf_enabled(vcpu) ||
10532 (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0))
10538 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10540 if (unlikely(!lapic_in_kernel(vcpu) ||
10541 kvm_event_needs_reinjection(vcpu) ||
10542 vcpu->arch.exception.pending))
10545 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10549 * If interrupts are off we cannot even use an artificial
10552 return kvm_arch_interrupt_allowed(vcpu);
10555 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10556 struct kvm_async_pf *work)
10558 struct x86_exception fault;
10560 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10561 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10563 if (kvm_can_deliver_async_pf(vcpu) &&
10564 !apf_put_user_notpresent(vcpu)) {
10565 fault.vector = PF_VECTOR;
10566 fault.error_code_valid = true;
10567 fault.error_code = 0;
10568 fault.nested_page_fault = false;
10569 fault.address = work->arch.token;
10570 fault.async_page_fault = true;
10571 kvm_inject_page_fault(vcpu, &fault);
10575 * It is not possible to deliver a paravirtualized asynchronous
10576 * page fault, but putting the guest in an artificial halt state
10577 * can be beneficial nevertheless: if an interrupt arrives, we
10578 * can deliver it timely and perhaps the guest will schedule
10579 * another process. When the instruction that triggered a page
10580 * fault is retried, hopefully the page will be ready in the host.
10582 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10587 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10588 struct kvm_async_pf *work)
10590 struct kvm_lapic_irq irq = {
10591 .delivery_mode = APIC_DM_FIXED,
10592 .vector = vcpu->arch.apf.vec
10595 if (work->wakeup_all)
10596 work->arch.token = ~0; /* broadcast wakeup */
10598 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10599 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10601 if ((work->wakeup_all || work->notpresent_injected) &&
10602 kvm_pv_async_pf_enabled(vcpu) &&
10603 !apf_put_user_ready(vcpu, work->arch.token)) {
10604 vcpu->arch.apf.pageready_pending = true;
10605 kvm_apic_set_irq(vcpu, &irq, NULL);
10608 vcpu->arch.apf.halted = false;
10609 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10612 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
10614 kvm_make_request(KVM_REQ_APF_READY, vcpu);
10615 if (!vcpu->arch.apf.pageready_pending)
10616 kvm_vcpu_kick(vcpu);
10619 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
10621 if (!kvm_pv_async_pf_enabled(vcpu))
10624 return apf_pageready_slot_free(vcpu);
10627 void kvm_arch_start_assignment(struct kvm *kvm)
10629 atomic_inc(&kvm->arch.assigned_device_count);
10631 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10633 void kvm_arch_end_assignment(struct kvm *kvm)
10635 atomic_dec(&kvm->arch.assigned_device_count);
10637 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10639 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10641 return atomic_read(&kvm->arch.assigned_device_count);
10643 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10645 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10647 atomic_inc(&kvm->arch.noncoherent_dma_count);
10649 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10651 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10653 atomic_dec(&kvm->arch.noncoherent_dma_count);
10655 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10657 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10659 return atomic_read(&kvm->arch.noncoherent_dma_count);
10661 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10663 bool kvm_arch_has_irq_bypass(void)
10668 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10669 struct irq_bypass_producer *prod)
10671 struct kvm_kernel_irqfd *irqfd =
10672 container_of(cons, struct kvm_kernel_irqfd, consumer);
10675 irqfd->producer = prod;
10676 kvm_arch_start_assignment(irqfd->kvm);
10677 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm,
10678 prod->irq, irqfd->gsi, 1);
10681 kvm_arch_end_assignment(irqfd->kvm);
10686 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10687 struct irq_bypass_producer *prod)
10690 struct kvm_kernel_irqfd *irqfd =
10691 container_of(cons, struct kvm_kernel_irqfd, consumer);
10693 WARN_ON(irqfd->producer != prod);
10694 irqfd->producer = NULL;
10697 * When producer of consumer is unregistered, we change back to
10698 * remapped mode, so we can re-use the current implementation
10699 * when the irq is masked/disabled or the consumer side (KVM
10700 * int this case doesn't want to receive the interrupts.
10702 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10704 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10705 " fails: %d\n", irqfd->consumer.token, ret);
10707 kvm_arch_end_assignment(irqfd->kvm);
10710 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10711 uint32_t guest_irq, bool set)
10713 return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
10716 bool kvm_vector_hashing_enabled(void)
10718 return vector_hashing;
10721 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10723 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10725 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10728 int kvm_spec_ctrl_test_value(u64 value)
10731 * test that setting IA32_SPEC_CTRL to given value
10732 * is allowed by the host processor
10736 unsigned long flags;
10739 local_irq_save(flags);
10741 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
10743 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
10746 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
10748 local_irq_restore(flags);
10752 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
10754 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
10756 struct x86_exception fault;
10757 u32 access = error_code &
10758 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
10760 if (!(error_code & PFERR_PRESENT_MASK) ||
10761 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
10763 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
10764 * tables probably do not match the TLB. Just proceed
10765 * with the error code that the processor gave.
10767 fault.vector = PF_VECTOR;
10768 fault.error_code_valid = true;
10769 fault.error_code = error_code;
10770 fault.nested_page_fault = false;
10771 fault.address = gva;
10773 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
10775 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
10777 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10778 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10779 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10780 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10781 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10782 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10783 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10784 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10785 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10786 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10787 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10788 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10789 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10790 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10791 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10792 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10793 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10794 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10795 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10796 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10797 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
10798 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);