2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
30 #include <linux/clocksource.h>
31 #include <linux/interrupt.h>
32 #include <linux/kvm.h>
34 #include <linux/vmalloc.h>
35 #include <linux/module.h>
36 #include <linux/mman.h>
37 #include <linux/highmem.h>
38 #include <linux/iommu.h>
39 #include <linux/intel-iommu.h>
40 #include <linux/cpufreq.h>
41 #include <linux/user-return-notifier.h>
42 #include <linux/srcu.h>
43 #include <linux/slab.h>
44 #include <linux/perf_event.h>
45 #include <linux/uaccess.h>
46 #include <trace/events/kvm.h>
48 #define CREATE_TRACE_POINTS
51 #include <asm/debugreg.h>
58 #include <asm/pvclock.h>
59 #include <asm/div64.h>
61 #define MAX_IO_MSRS 256
62 #define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66 #define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
73 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
75 #define KVM_MAX_MCE_BANKS 32
76 #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
83 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
85 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
88 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
91 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
92 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
95 struct kvm_x86_ops *kvm_x86_ops;
96 EXPORT_SYMBOL_GPL(kvm_x86_ops);
99 module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
101 #define KVM_NR_SHARED_MSRS 16
103 struct kvm_shared_msrs_global {
105 u32 msrs[KVM_NR_SHARED_MSRS];
108 struct kvm_shared_msrs {
109 struct user_return_notifier urn;
111 struct kvm_shared_msr_values {
114 } values[KVM_NR_SHARED_MSRS];
117 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
120 struct kvm_stats_debugfs_item debugfs_entries[] = {
121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
133 { "hypercalls", VCPU_STAT(hypercalls) },
134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
141 { "irq_injections", VCPU_STAT(irq_injections) },
142 { "nmi_injections", VCPU_STAT(nmi_injections) },
143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
150 { "mmu_unsync", VM_STAT(mmu_unsync) },
151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
152 { "largepages", VM_STAT(lpages) },
156 u64 __read_mostly host_xcr0;
158 static inline u32 bit(int bitno)
160 return 1 << (bitno & 31);
163 static void kvm_on_user_return(struct user_return_notifier *urn)
166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
168 struct kvm_shared_msr_values *values;
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
181 static void shared_msr_update(unsigned slot, u32 msr)
183 struct kvm_shared_msrs *smsr;
186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
198 void kvm_define_shared_msr(unsigned slot, u32 msr)
200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
206 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
208 static void kvm_shared_msr_cpu_online(void)
212 for (i = 0; i < shared_msrs_global.nr; ++i)
213 shared_msr_update(i, shared_msrs_global.msrs[i]);
216 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
230 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
232 static void drop_user_return_notifiers(void *ignore)
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
240 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
242 if (irqchip_in_kernel(vcpu->kvm))
243 return vcpu->arch.apic_base;
245 return vcpu->arch.apic_base;
247 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
249 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
255 vcpu->arch.apic_base = data;
257 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259 #define EXCPT_BENIGN 0
260 #define EXCPT_CONTRIBUTORY 1
263 static int exception_class(int vector)
273 return EXCPT_CONTRIBUTORY;
280 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
281 unsigned nr, bool has_error, u32 error_code,
287 if (!vcpu->arch.exception.pending) {
289 vcpu->arch.exception.pending = true;
290 vcpu->arch.exception.has_error_code = has_error;
291 vcpu->arch.exception.nr = nr;
292 vcpu->arch.exception.error_code = error_code;
293 vcpu->arch.exception.reinject = reinject;
297 /* to check exception */
298 prev_nr = vcpu->arch.exception.nr;
299 if (prev_nr == DF_VECTOR) {
300 /* triple fault -> shutdown */
301 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
304 class1 = exception_class(prev_nr);
305 class2 = exception_class(nr);
306 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
307 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
308 /* generate double fault per SDM Table 5-5 */
309 vcpu->arch.exception.pending = true;
310 vcpu->arch.exception.has_error_code = true;
311 vcpu->arch.exception.nr = DF_VECTOR;
312 vcpu->arch.exception.error_code = 0;
314 /* replace previous exception with a new one in a hope
315 that instruction re-execution will regenerate lost
320 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
322 kvm_multiple_exception(vcpu, nr, false, 0, false);
324 EXPORT_SYMBOL_GPL(kvm_queue_exception);
326 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
328 kvm_multiple_exception(vcpu, nr, false, 0, true);
330 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
332 void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
334 unsigned error_code = vcpu->arch.fault.error_code;
336 ++vcpu->stat.pf_guest;
337 vcpu->arch.cr2 = vcpu->arch.fault.address;
338 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
341 void kvm_propagate_fault(struct kvm_vcpu *vcpu)
345 error = vcpu->arch.fault.error_code;
346 nested = error & PFERR_NESTED_MASK;
347 error = error & ~PFERR_NESTED_MASK;
349 vcpu->arch.fault.error_code = error;
351 if (mmu_is_nested(vcpu) && !nested)
352 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
354 vcpu->arch.mmu.inject_page_fault(vcpu);
357 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
359 vcpu->arch.nmi_pending = 1;
361 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
363 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
365 kvm_multiple_exception(vcpu, nr, true, error_code, false);
367 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
369 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
371 kvm_multiple_exception(vcpu, nr, true, error_code, true);
373 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
376 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
377 * a #GP and return false.
379 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
381 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
383 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
386 EXPORT_SYMBOL_GPL(kvm_require_cpl);
389 * This function will be used to read from the physical memory of the currently
390 * running guest. The difference to kvm_read_guest_page is that this function
391 * can read from guest physical or from the guest's guest physical memory.
393 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
394 gfn_t ngfn, void *data, int offset, int len,
400 ngpa = gfn_to_gpa(ngfn);
401 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
402 if (real_gfn == UNMAPPED_GVA)
405 real_gfn = gpa_to_gfn(real_gfn);
407 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
409 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
411 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
412 void *data, int offset, int len, u32 access)
414 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
415 data, offset, len, access);
419 * Load the pae pdptrs. Return true is they are all valid.
421 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
423 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
424 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
427 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
429 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
430 offset * sizeof(u64), sizeof(pdpte),
431 PFERR_USER_MASK|PFERR_WRITE_MASK);
436 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
437 if (is_present_gpte(pdpte[i]) &&
438 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
445 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
446 __set_bit(VCPU_EXREG_PDPTR,
447 (unsigned long *)&vcpu->arch.regs_avail);
448 __set_bit(VCPU_EXREG_PDPTR,
449 (unsigned long *)&vcpu->arch.regs_dirty);
454 EXPORT_SYMBOL_GPL(load_pdptrs);
456 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
458 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
464 if (is_long_mode(vcpu) || !is_pae(vcpu))
467 if (!test_bit(VCPU_EXREG_PDPTR,
468 (unsigned long *)&vcpu->arch.regs_avail))
471 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
472 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
473 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
474 PFERR_USER_MASK | PFERR_WRITE_MASK);
477 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
483 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
485 unsigned long old_cr0 = kvm_read_cr0(vcpu);
486 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
487 X86_CR0_CD | X86_CR0_NW;
492 if (cr0 & 0xffffffff00000000UL)
496 cr0 &= ~CR0_RESERVED_BITS;
498 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
501 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
504 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
506 if ((vcpu->arch.efer & EFER_LME)) {
511 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
516 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
521 kvm_x86_ops->set_cr0(vcpu, cr0);
523 if ((cr0 ^ old_cr0) & update_bits)
524 kvm_mmu_reset_context(vcpu);
527 EXPORT_SYMBOL_GPL(kvm_set_cr0);
529 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
531 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
533 EXPORT_SYMBOL_GPL(kvm_lmsw);
535 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
539 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
540 if (index != XCR_XFEATURE_ENABLED_MASK)
543 if (kvm_x86_ops->get_cpl(vcpu) != 0)
545 if (!(xcr0 & XSTATE_FP))
547 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
549 if (xcr0 & ~host_xcr0)
551 vcpu->arch.xcr0 = xcr0;
552 vcpu->guest_xcr0_loaded = 0;
556 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
558 if (__kvm_set_xcr(vcpu, index, xcr)) {
559 kvm_inject_gp(vcpu, 0);
564 EXPORT_SYMBOL_GPL(kvm_set_xcr);
566 static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
568 struct kvm_cpuid_entry2 *best;
570 best = kvm_find_cpuid_entry(vcpu, 1, 0);
571 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
574 static void update_cpuid(struct kvm_vcpu *vcpu)
576 struct kvm_cpuid_entry2 *best;
578 best = kvm_find_cpuid_entry(vcpu, 1, 0);
582 /* Update OSXSAVE bit */
583 if (cpu_has_xsave && best->function == 0x1) {
584 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
585 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
586 best->ecx |= bit(X86_FEATURE_OSXSAVE);
590 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
592 unsigned long old_cr4 = kvm_read_cr4(vcpu);
593 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
595 if (cr4 & CR4_RESERVED_BITS)
598 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
601 if (is_long_mode(vcpu)) {
602 if (!(cr4 & X86_CR4_PAE))
604 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605 && ((cr4 ^ old_cr4) & pdptr_bits)
606 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
609 if (cr4 & X86_CR4_VMXE)
612 kvm_x86_ops->set_cr4(vcpu, cr4);
614 if ((cr4 ^ old_cr4) & pdptr_bits)
615 kvm_mmu_reset_context(vcpu);
617 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
622 EXPORT_SYMBOL_GPL(kvm_set_cr4);
624 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
626 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
627 kvm_mmu_sync_roots(vcpu);
628 kvm_mmu_flush_tlb(vcpu);
632 if (is_long_mode(vcpu)) {
633 if (cr3 & CR3_L_MODE_RESERVED_BITS)
637 if (cr3 & CR3_PAE_RESERVED_BITS)
639 if (is_paging(vcpu) &&
640 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
644 * We don't check reserved bits in nonpae mode, because
645 * this isn't enforced, and VMware depends on this.
650 * Does the new cr3 value map to physical memory? (Note, we
651 * catch an invalid cr3 even in real-mode, because it would
652 * cause trouble later on when we turn on paging anyway.)
654 * A real CPU would silently accept an invalid cr3 and would
655 * attempt to use it - with largely undefined (and often hard
656 * to debug) behavior on the guest side.
658 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
660 vcpu->arch.cr3 = cr3;
661 vcpu->arch.mmu.new_cr3(vcpu);
664 EXPORT_SYMBOL_GPL(kvm_set_cr3);
666 int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
668 if (cr8 & CR8_RESERVED_BITS)
670 if (irqchip_in_kernel(vcpu->kvm))
671 kvm_lapic_set_tpr(vcpu, cr8);
673 vcpu->arch.cr8 = cr8;
677 void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
679 if (__kvm_set_cr8(vcpu, cr8))
680 kvm_inject_gp(vcpu, 0);
682 EXPORT_SYMBOL_GPL(kvm_set_cr8);
684 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
686 if (irqchip_in_kernel(vcpu->kvm))
687 return kvm_lapic_get_cr8(vcpu);
689 return vcpu->arch.cr8;
691 EXPORT_SYMBOL_GPL(kvm_get_cr8);
693 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
697 vcpu->arch.db[dr] = val;
698 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
699 vcpu->arch.eff_db[dr] = val;
702 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
706 if (val & 0xffffffff00000000ULL)
708 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
711 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
715 if (val & 0xffffffff00000000ULL)
717 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
718 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
719 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
720 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
728 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
732 res = __kvm_set_dr(vcpu, dr, val);
734 kvm_queue_exception(vcpu, UD_VECTOR);
736 kvm_inject_gp(vcpu, 0);
740 EXPORT_SYMBOL_GPL(kvm_set_dr);
742 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
746 *val = vcpu->arch.db[dr];
749 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
753 *val = vcpu->arch.dr6;
756 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
760 *val = vcpu->arch.dr7;
767 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
769 if (_kvm_get_dr(vcpu, dr, val)) {
770 kvm_queue_exception(vcpu, UD_VECTOR);
775 EXPORT_SYMBOL_GPL(kvm_get_dr);
778 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
779 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
781 * This list is modified at module load time to reflect the
782 * capabilities of the host cpu. This capabilities test skips MSRs that are
783 * kvm-specific. Those are put in the beginning of the list.
786 #define KVM_SAVE_MSRS_BEGIN 7
787 static u32 msrs_to_save[] = {
788 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
789 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
790 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
791 HV_X64_MSR_APIC_ASSIST_PAGE,
792 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
795 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
797 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
800 static unsigned num_msrs_to_save;
802 static u32 emulated_msrs[] = {
803 MSR_IA32_MISC_ENABLE,
808 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
810 u64 old_efer = vcpu->arch.efer;
812 if (efer & efer_reserved_bits)
816 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
819 if (efer & EFER_FFXSR) {
820 struct kvm_cpuid_entry2 *feat;
822 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
823 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
827 if (efer & EFER_SVME) {
828 struct kvm_cpuid_entry2 *feat;
830 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
831 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
836 efer |= vcpu->arch.efer & EFER_LMA;
838 kvm_x86_ops->set_efer(vcpu, efer);
840 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
841 kvm_mmu_reset_context(vcpu);
843 /* Update reserved bits */
844 if ((efer ^ old_efer) & EFER_NX)
845 kvm_mmu_reset_context(vcpu);
850 void kvm_enable_efer_bits(u64 mask)
852 efer_reserved_bits &= ~mask;
854 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
858 * Writes msr value into into the appropriate "register".
859 * Returns 0 on success, non-0 otherwise.
860 * Assumes vcpu_load() was already called.
862 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
864 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
868 * Adapt set_msr() to msr_io()'s calling convention
870 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
872 return kvm_set_msr(vcpu, index, *data);
875 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
879 struct pvclock_wall_clock wc;
880 struct timespec boot;
885 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
890 ++version; /* first time write, random junk */
894 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
897 * The guest calculates current wall clock time by adding
898 * system time (updated by kvm_write_guest_time below) to the
899 * wall clock specified here. guest system time equals host
900 * system time for us, thus we must fill in host boot time here.
904 wc.sec = boot.tv_sec;
905 wc.nsec = boot.tv_nsec;
906 wc.version = version;
908 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
911 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
914 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
916 uint32_t quotient, remainder;
918 /* Don't try to replace with do_div(), this one calculates
919 * "(dividend << 32) / divisor" */
921 : "=a" (quotient), "=d" (remainder)
922 : "0" (0), "1" (dividend), "r" (divisor) );
926 static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
928 uint64_t nsecs = 1000000000LL;
933 tps64 = tsc_khz * 1000LL;
934 while (tps64 > nsecs*2) {
939 tps32 = (uint32_t)tps64;
940 while (tps32 <= (uint32_t)nsecs) {
945 hv_clock->tsc_shift = shift;
946 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
948 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
949 __func__, tsc_khz, hv_clock->tsc_shift,
950 hv_clock->tsc_to_system_mul);
953 static inline u64 get_kernel_ns(void)
957 WARN_ON(preemptible());
959 monotonic_to_bootbased(&ts);
960 return timespec_to_ns(&ts);
963 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
965 static inline int kvm_tsc_changes_freq(void)
968 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
969 cpufreq_quick_get(cpu) != 0;
974 static inline u64 nsec_to_cycles(u64 nsec)
978 WARN_ON(preemptible());
979 if (kvm_tsc_changes_freq())
980 printk_once(KERN_WARNING
981 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
982 ret = nsec * __get_cpu_var(cpu_tsc_khz);
983 do_div(ret, USEC_PER_SEC);
987 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
989 struct kvm *kvm = vcpu->kvm;
990 u64 offset, ns, elapsed;
994 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
995 offset = data - native_read_tsc();
996 ns = get_kernel_ns();
997 elapsed = ns - kvm->arch.last_tsc_nsec;
998 sdiff = data - kvm->arch.last_tsc_write;
1003 * Special case: close write to TSC within 5 seconds of
1004 * another CPU is interpreted as an attempt to synchronize
1005 * The 5 seconds is to accomodate host load / swapping as
1006 * well as any reset of TSC during the boot process.
1008 * In that case, for a reliable TSC, we can match TSC offsets,
1009 * or make a best guest using elapsed value.
1011 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1012 elapsed < 5ULL * NSEC_PER_SEC) {
1013 if (!check_tsc_unstable()) {
1014 offset = kvm->arch.last_tsc_offset;
1015 pr_debug("kvm: matched tsc offset for %llu\n", data);
1017 u64 delta = nsec_to_cycles(elapsed);
1019 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1021 ns = kvm->arch.last_tsc_nsec;
1023 kvm->arch.last_tsc_nsec = ns;
1024 kvm->arch.last_tsc_write = data;
1025 kvm->arch.last_tsc_offset = offset;
1026 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1027 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1029 /* Reset of TSC must disable overshoot protection below */
1030 vcpu->arch.hv_clock.tsc_timestamp = 0;
1032 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1034 static int kvm_write_guest_time(struct kvm_vcpu *v)
1036 unsigned long flags;
1037 struct kvm_vcpu_arch *vcpu = &v->arch;
1039 unsigned long this_tsc_khz;
1040 s64 kernel_ns, max_kernel_ns;
1043 if ((!vcpu->time_page))
1046 /* Keep irq disabled to prevent changes to the clock */
1047 local_irq_save(flags);
1048 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
1049 kernel_ns = get_kernel_ns();
1050 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1051 local_irq_restore(flags);
1053 if (unlikely(this_tsc_khz == 0)) {
1054 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1059 * Time as measured by the TSC may go backwards when resetting the base
1060 * tsc_timestamp. The reason for this is that the TSC resolution is
1061 * higher than the resolution of the other clock scales. Thus, many
1062 * possible measurments of the TSC correspond to one measurement of any
1063 * other clock, and so a spread of values is possible. This is not a
1064 * problem for the computation of the nanosecond clock; with TSC rates
1065 * around 1GHZ, there can only be a few cycles which correspond to one
1066 * nanosecond value, and any path through this code will inevitably
1067 * take longer than that. However, with the kernel_ns value itself,
1068 * the precision may be much lower, down to HZ granularity. If the
1069 * first sampling of TSC against kernel_ns ends in the low part of the
1070 * range, and the second in the high end of the range, we can get:
1072 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1074 * As the sampling errors potentially range in the thousands of cycles,
1075 * it is possible such a time value has already been observed by the
1076 * guest. To protect against this, we must compute the system time as
1077 * observed by the guest and ensure the new system time is greater.
1080 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1081 max_kernel_ns = vcpu->last_guest_tsc -
1082 vcpu->hv_clock.tsc_timestamp;
1083 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1084 vcpu->hv_clock.tsc_to_system_mul,
1085 vcpu->hv_clock.tsc_shift);
1086 max_kernel_ns += vcpu->last_kernel_ns;
1089 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1090 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
1091 vcpu->hw_tsc_khz = this_tsc_khz;
1094 if (max_kernel_ns > kernel_ns)
1095 kernel_ns = max_kernel_ns;
1097 /* With all the info we got, fill in the values */
1098 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1099 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1100 vcpu->last_kernel_ns = kernel_ns;
1101 vcpu->hv_clock.flags = 0;
1104 * The interface expects us to write an even number signaling that the
1105 * update is finished. Since the guest won't see the intermediate
1106 * state, we just increase by 2 at the end.
1108 vcpu->hv_clock.version += 2;
1110 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1112 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1113 sizeof(vcpu->hv_clock));
1115 kunmap_atomic(shared_kaddr, KM_USER0);
1117 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1121 static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1123 struct kvm_vcpu_arch *vcpu = &v->arch;
1125 if (!vcpu->time_page)
1127 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1131 static bool msr_mtrr_valid(unsigned msr)
1134 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1135 case MSR_MTRRfix64K_00000:
1136 case MSR_MTRRfix16K_80000:
1137 case MSR_MTRRfix16K_A0000:
1138 case MSR_MTRRfix4K_C0000:
1139 case MSR_MTRRfix4K_C8000:
1140 case MSR_MTRRfix4K_D0000:
1141 case MSR_MTRRfix4K_D8000:
1142 case MSR_MTRRfix4K_E0000:
1143 case MSR_MTRRfix4K_E8000:
1144 case MSR_MTRRfix4K_F0000:
1145 case MSR_MTRRfix4K_F8000:
1146 case MSR_MTRRdefType:
1147 case MSR_IA32_CR_PAT:
1155 static bool valid_pat_type(unsigned t)
1157 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1160 static bool valid_mtrr_type(unsigned t)
1162 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1165 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1169 if (!msr_mtrr_valid(msr))
1172 if (msr == MSR_IA32_CR_PAT) {
1173 for (i = 0; i < 8; i++)
1174 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1177 } else if (msr == MSR_MTRRdefType) {
1180 return valid_mtrr_type(data & 0xff);
1181 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1182 for (i = 0; i < 8 ; i++)
1183 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1188 /* variable MTRRs */
1189 return valid_mtrr_type(data & 0xff);
1192 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1194 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1196 if (!mtrr_valid(vcpu, msr, data))
1199 if (msr == MSR_MTRRdefType) {
1200 vcpu->arch.mtrr_state.def_type = data;
1201 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1202 } else if (msr == MSR_MTRRfix64K_00000)
1204 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1205 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1206 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1207 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1208 else if (msr == MSR_IA32_CR_PAT)
1209 vcpu->arch.pat = data;
1210 else { /* Variable MTRRs */
1211 int idx, is_mtrr_mask;
1214 idx = (msr - 0x200) / 2;
1215 is_mtrr_mask = msr - 0x200 - 2 * idx;
1218 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1221 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1225 kvm_mmu_reset_context(vcpu);
1229 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1231 u64 mcg_cap = vcpu->arch.mcg_cap;
1232 unsigned bank_num = mcg_cap & 0xff;
1235 case MSR_IA32_MCG_STATUS:
1236 vcpu->arch.mcg_status = data;
1238 case MSR_IA32_MCG_CTL:
1239 if (!(mcg_cap & MCG_CTL_P))
1241 if (data != 0 && data != ~(u64)0)
1243 vcpu->arch.mcg_ctl = data;
1246 if (msr >= MSR_IA32_MC0_CTL &&
1247 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1248 u32 offset = msr - MSR_IA32_MC0_CTL;
1249 /* only 0 or all 1s can be written to IA32_MCi_CTL
1250 * some Linux kernels though clear bit 10 in bank 4 to
1251 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1252 * this to avoid an uncatched #GP in the guest
1254 if ((offset & 0x3) == 0 &&
1255 data != 0 && (data | (1 << 10)) != ~(u64)0)
1257 vcpu->arch.mce_banks[offset] = data;
1265 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1267 struct kvm *kvm = vcpu->kvm;
1268 int lm = is_long_mode(vcpu);
1269 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1270 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1271 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1272 : kvm->arch.xen_hvm_config.blob_size_32;
1273 u32 page_num = data & ~PAGE_MASK;
1274 u64 page_addr = data & PAGE_MASK;
1279 if (page_num >= blob_size)
1282 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1286 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1288 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1297 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1299 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1302 static bool kvm_hv_msr_partition_wide(u32 msr)
1306 case HV_X64_MSR_GUEST_OS_ID:
1307 case HV_X64_MSR_HYPERCALL:
1315 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1317 struct kvm *kvm = vcpu->kvm;
1320 case HV_X64_MSR_GUEST_OS_ID:
1321 kvm->arch.hv_guest_os_id = data;
1322 /* setting guest os id to zero disables hypercall page */
1323 if (!kvm->arch.hv_guest_os_id)
1324 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1326 case HV_X64_MSR_HYPERCALL: {
1331 /* if guest os id is not set hypercall should remain disabled */
1332 if (!kvm->arch.hv_guest_os_id)
1334 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1335 kvm->arch.hv_hypercall = data;
1338 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1339 addr = gfn_to_hva(kvm, gfn);
1340 if (kvm_is_error_hva(addr))
1342 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1343 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1344 if (copy_to_user((void __user *)addr, instructions, 4))
1346 kvm->arch.hv_hypercall = data;
1350 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1351 "data 0x%llx\n", msr, data);
1357 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1360 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1363 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1364 vcpu->arch.hv_vapic = data;
1367 addr = gfn_to_hva(vcpu->kvm, data >>
1368 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1369 if (kvm_is_error_hva(addr))
1371 if (clear_user((void __user *)addr, PAGE_SIZE))
1373 vcpu->arch.hv_vapic = data;
1376 case HV_X64_MSR_EOI:
1377 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1378 case HV_X64_MSR_ICR:
1379 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1380 case HV_X64_MSR_TPR:
1381 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1383 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1384 "data 0x%llx\n", msr, data);
1391 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1395 return set_efer(vcpu, data);
1397 data &= ~(u64)0x40; /* ignore flush filter disable */
1398 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1400 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1405 case MSR_FAM10H_MMIO_CONF_BASE:
1407 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1412 case MSR_AMD64_NB_CFG:
1414 case MSR_IA32_DEBUGCTLMSR:
1416 /* We support the non-activated case already */
1418 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1419 /* Values other than LBR and BTF are vendor-specific,
1420 thus reserved and should throw a #GP */
1423 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1426 case MSR_IA32_UCODE_REV:
1427 case MSR_IA32_UCODE_WRITE:
1428 case MSR_VM_HSAVE_PA:
1429 case MSR_AMD64_PATCH_LOADER:
1431 case 0x200 ... 0x2ff:
1432 return set_msr_mtrr(vcpu, msr, data);
1433 case MSR_IA32_APICBASE:
1434 kvm_set_apic_base(vcpu, data);
1436 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1437 return kvm_x2apic_msr_write(vcpu, msr, data);
1438 case MSR_IA32_MISC_ENABLE:
1439 vcpu->arch.ia32_misc_enable_msr = data;
1441 case MSR_KVM_WALL_CLOCK_NEW:
1442 case MSR_KVM_WALL_CLOCK:
1443 vcpu->kvm->arch.wall_clock = data;
1444 kvm_write_wall_clock(vcpu->kvm, data);
1446 case MSR_KVM_SYSTEM_TIME_NEW:
1447 case MSR_KVM_SYSTEM_TIME: {
1448 if (vcpu->arch.time_page) {
1449 kvm_release_page_dirty(vcpu->arch.time_page);
1450 vcpu->arch.time_page = NULL;
1453 vcpu->arch.time = data;
1455 /* we verify if the enable bit is set... */
1459 /* ...but clean it before doing the actual write */
1460 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1462 vcpu->arch.time_page =
1463 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1465 if (is_error_page(vcpu->arch.time_page)) {
1466 kvm_release_page_clean(vcpu->arch.time_page);
1467 vcpu->arch.time_page = NULL;
1470 kvm_request_guest_time_update(vcpu);
1473 case MSR_IA32_MCG_CTL:
1474 case MSR_IA32_MCG_STATUS:
1475 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1476 return set_msr_mce(vcpu, msr, data);
1478 /* Performance counters are not protected by a CPUID bit,
1479 * so we should check all of them in the generic path for the sake of
1480 * cross vendor migration.
1481 * Writing a zero into the event select MSRs disables them,
1482 * which we perfectly emulate ;-). Any other value should be at least
1483 * reported, some guests depend on them.
1485 case MSR_P6_EVNTSEL0:
1486 case MSR_P6_EVNTSEL1:
1487 case MSR_K7_EVNTSEL0:
1488 case MSR_K7_EVNTSEL1:
1489 case MSR_K7_EVNTSEL2:
1490 case MSR_K7_EVNTSEL3:
1492 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1493 "0x%x data 0x%llx\n", msr, data);
1495 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1496 * so we ignore writes to make it happy.
1498 case MSR_P6_PERFCTR0:
1499 case MSR_P6_PERFCTR1:
1500 case MSR_K7_PERFCTR0:
1501 case MSR_K7_PERFCTR1:
1502 case MSR_K7_PERFCTR2:
1503 case MSR_K7_PERFCTR3:
1504 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1505 "0x%x data 0x%llx\n", msr, data);
1507 case MSR_K7_CLK_CTL:
1509 * Ignore all writes to this no longer documented MSR.
1510 * Writes are only relevant for old K7 processors,
1511 * all pre-dating SVM, but a recommended workaround from
1512 * AMD for these chips. It is possible to speicify the
1513 * affected processor models on the command line, hence
1514 * the need to ignore the workaround.
1517 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1518 if (kvm_hv_msr_partition_wide(msr)) {
1520 mutex_lock(&vcpu->kvm->lock);
1521 r = set_msr_hyperv_pw(vcpu, msr, data);
1522 mutex_unlock(&vcpu->kvm->lock);
1525 return set_msr_hyperv(vcpu, msr, data);
1528 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1529 return xen_hvm_config(vcpu, data);
1531 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1535 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1542 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1546 * Reads an msr value (of 'msr_index') into 'pdata'.
1547 * Returns 0 on success, non-0 otherwise.
1548 * Assumes vcpu_load() was already called.
1550 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1552 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1555 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1557 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1559 if (!msr_mtrr_valid(msr))
1562 if (msr == MSR_MTRRdefType)
1563 *pdata = vcpu->arch.mtrr_state.def_type +
1564 (vcpu->arch.mtrr_state.enabled << 10);
1565 else if (msr == MSR_MTRRfix64K_00000)
1567 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1568 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1569 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1570 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1571 else if (msr == MSR_IA32_CR_PAT)
1572 *pdata = vcpu->arch.pat;
1573 else { /* Variable MTRRs */
1574 int idx, is_mtrr_mask;
1577 idx = (msr - 0x200) / 2;
1578 is_mtrr_mask = msr - 0x200 - 2 * idx;
1581 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1584 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1591 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1594 u64 mcg_cap = vcpu->arch.mcg_cap;
1595 unsigned bank_num = mcg_cap & 0xff;
1598 case MSR_IA32_P5_MC_ADDR:
1599 case MSR_IA32_P5_MC_TYPE:
1602 case MSR_IA32_MCG_CAP:
1603 data = vcpu->arch.mcg_cap;
1605 case MSR_IA32_MCG_CTL:
1606 if (!(mcg_cap & MCG_CTL_P))
1608 data = vcpu->arch.mcg_ctl;
1610 case MSR_IA32_MCG_STATUS:
1611 data = vcpu->arch.mcg_status;
1614 if (msr >= MSR_IA32_MC0_CTL &&
1615 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1616 u32 offset = msr - MSR_IA32_MC0_CTL;
1617 data = vcpu->arch.mce_banks[offset];
1626 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1629 struct kvm *kvm = vcpu->kvm;
1632 case HV_X64_MSR_GUEST_OS_ID:
1633 data = kvm->arch.hv_guest_os_id;
1635 case HV_X64_MSR_HYPERCALL:
1636 data = kvm->arch.hv_hypercall;
1639 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1647 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1652 case HV_X64_MSR_VP_INDEX: {
1655 kvm_for_each_vcpu(r, v, vcpu->kvm)
1660 case HV_X64_MSR_EOI:
1661 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1662 case HV_X64_MSR_ICR:
1663 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1664 case HV_X64_MSR_TPR:
1665 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1667 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1674 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1679 case MSR_IA32_PLATFORM_ID:
1680 case MSR_IA32_UCODE_REV:
1681 case MSR_IA32_EBL_CR_POWERON:
1682 case MSR_IA32_DEBUGCTLMSR:
1683 case MSR_IA32_LASTBRANCHFROMIP:
1684 case MSR_IA32_LASTBRANCHTOIP:
1685 case MSR_IA32_LASTINTFROMIP:
1686 case MSR_IA32_LASTINTTOIP:
1689 case MSR_VM_HSAVE_PA:
1690 case MSR_P6_PERFCTR0:
1691 case MSR_P6_PERFCTR1:
1692 case MSR_P6_EVNTSEL0:
1693 case MSR_P6_EVNTSEL1:
1694 case MSR_K7_EVNTSEL0:
1695 case MSR_K7_PERFCTR0:
1696 case MSR_K8_INT_PENDING_MSG:
1697 case MSR_AMD64_NB_CFG:
1698 case MSR_FAM10H_MMIO_CONF_BASE:
1702 data = 0x500 | KVM_NR_VAR_MTRR;
1704 case 0x200 ... 0x2ff:
1705 return get_msr_mtrr(vcpu, msr, pdata);
1706 case 0xcd: /* fsb frequency */
1710 * MSR_EBC_FREQUENCY_ID
1711 * Conservative value valid for even the basic CPU models.
1712 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1713 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1714 * and 266MHz for model 3, or 4. Set Core Clock
1715 * Frequency to System Bus Frequency Ratio to 1 (bits
1716 * 31:24) even though these are only valid for CPU
1717 * models > 2, however guests may end up dividing or
1718 * multiplying by zero otherwise.
1720 case MSR_EBC_FREQUENCY_ID:
1723 case MSR_IA32_APICBASE:
1724 data = kvm_get_apic_base(vcpu);
1726 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1727 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1729 case MSR_IA32_MISC_ENABLE:
1730 data = vcpu->arch.ia32_misc_enable_msr;
1732 case MSR_IA32_PERF_STATUS:
1733 /* TSC increment by tick */
1735 /* CPU multiplier */
1736 data |= (((uint64_t)4ULL) << 40);
1739 data = vcpu->arch.efer;
1741 case MSR_KVM_WALL_CLOCK:
1742 case MSR_KVM_WALL_CLOCK_NEW:
1743 data = vcpu->kvm->arch.wall_clock;
1745 case MSR_KVM_SYSTEM_TIME:
1746 case MSR_KVM_SYSTEM_TIME_NEW:
1747 data = vcpu->arch.time;
1749 case MSR_IA32_P5_MC_ADDR:
1750 case MSR_IA32_P5_MC_TYPE:
1751 case MSR_IA32_MCG_CAP:
1752 case MSR_IA32_MCG_CTL:
1753 case MSR_IA32_MCG_STATUS:
1754 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1755 return get_msr_mce(vcpu, msr, pdata);
1756 case MSR_K7_CLK_CTL:
1758 * Provide expected ramp-up count for K7. All other
1759 * are set to zero, indicating minimum divisors for
1762 * This prevents guest kernels on AMD host with CPU
1763 * type 6, model 8 and higher from exploding due to
1764 * the rdmsr failing.
1768 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1769 if (kvm_hv_msr_partition_wide(msr)) {
1771 mutex_lock(&vcpu->kvm->lock);
1772 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1773 mutex_unlock(&vcpu->kvm->lock);
1776 return get_msr_hyperv(vcpu, msr, pdata);
1780 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1783 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1791 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1794 * Read or write a bunch of msrs. All parameters are kernel addresses.
1796 * @return number of msrs set successfully.
1798 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1799 struct kvm_msr_entry *entries,
1800 int (*do_msr)(struct kvm_vcpu *vcpu,
1801 unsigned index, u64 *data))
1805 idx = srcu_read_lock(&vcpu->kvm->srcu);
1806 for (i = 0; i < msrs->nmsrs; ++i)
1807 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1809 srcu_read_unlock(&vcpu->kvm->srcu, idx);
1815 * Read or write a bunch of msrs. Parameters are user addresses.
1817 * @return number of msrs set successfully.
1819 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1820 int (*do_msr)(struct kvm_vcpu *vcpu,
1821 unsigned index, u64 *data),
1824 struct kvm_msrs msrs;
1825 struct kvm_msr_entry *entries;
1830 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1834 if (msrs.nmsrs >= MAX_IO_MSRS)
1838 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1839 entries = kmalloc(size, GFP_KERNEL);
1844 if (copy_from_user(entries, user_msrs->entries, size))
1847 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1852 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1863 int kvm_dev_ioctl_check_extension(long ext)
1868 case KVM_CAP_IRQCHIP:
1870 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
1871 case KVM_CAP_SET_TSS_ADDR:
1872 case KVM_CAP_EXT_CPUID:
1873 case KVM_CAP_CLOCKSOURCE:
1875 case KVM_CAP_NOP_IO_DELAY:
1876 case KVM_CAP_MP_STATE:
1877 case KVM_CAP_SYNC_MMU:
1878 case KVM_CAP_REINJECT_CONTROL:
1879 case KVM_CAP_IRQ_INJECT_STATUS:
1880 case KVM_CAP_ASSIGN_DEV_IRQ:
1882 case KVM_CAP_IOEVENTFD:
1884 case KVM_CAP_PIT_STATE2:
1885 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
1886 case KVM_CAP_XEN_HVM:
1887 case KVM_CAP_ADJUST_CLOCK:
1888 case KVM_CAP_VCPU_EVENTS:
1889 case KVM_CAP_HYPERV:
1890 case KVM_CAP_HYPERV_VAPIC:
1891 case KVM_CAP_HYPERV_SPIN:
1892 case KVM_CAP_PCI_SEGMENT:
1893 case KVM_CAP_DEBUGREGS:
1894 case KVM_CAP_X86_ROBUST_SINGLESTEP:
1898 case KVM_CAP_COALESCED_MMIO:
1899 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1902 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1904 case KVM_CAP_NR_VCPUS:
1907 case KVM_CAP_NR_MEMSLOTS:
1908 r = KVM_MEMORY_SLOTS;
1910 case KVM_CAP_PV_MMU: /* obsolete */
1917 r = KVM_MAX_MCE_BANKS;
1930 long kvm_arch_dev_ioctl(struct file *filp,
1931 unsigned int ioctl, unsigned long arg)
1933 void __user *argp = (void __user *)arg;
1937 case KVM_GET_MSR_INDEX_LIST: {
1938 struct kvm_msr_list __user *user_msr_list = argp;
1939 struct kvm_msr_list msr_list;
1943 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1946 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1947 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1950 if (n < msr_list.nmsrs)
1953 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1954 num_msrs_to_save * sizeof(u32)))
1956 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
1958 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1963 case KVM_GET_SUPPORTED_CPUID: {
1964 struct kvm_cpuid2 __user *cpuid_arg = argp;
1965 struct kvm_cpuid2 cpuid;
1968 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1970 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1971 cpuid_arg->entries);
1976 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1981 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1984 mce_cap = KVM_MCE_CAP_SUPPORTED;
1986 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1998 static void wbinvd_ipi(void *garbage)
2003 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2005 return vcpu->kvm->arch.iommu_domain &&
2006 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2009 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2011 /* Address WBINVD may be executed by guest */
2012 if (need_emulate_wbinvd(vcpu)) {
2013 if (kvm_x86_ops->has_wbinvd_exit())
2014 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2015 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2016 smp_call_function_single(vcpu->cpu,
2017 wbinvd_ipi, NULL, 1);
2020 kvm_x86_ops->vcpu_load(vcpu, cpu);
2021 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2022 /* Make sure TSC doesn't go backwards */
2023 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2024 native_read_tsc() - vcpu->arch.last_host_tsc;
2026 mark_tsc_unstable("KVM discovered backwards TSC");
2027 if (check_tsc_unstable())
2028 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2029 kvm_migrate_timers(vcpu);
2034 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2036 kvm_x86_ops->vcpu_put(vcpu);
2037 kvm_put_guest_fpu(vcpu);
2038 vcpu->arch.last_host_tsc = native_read_tsc();
2041 static int is_efer_nx(void)
2043 unsigned long long efer = 0;
2045 rdmsrl_safe(MSR_EFER, &efer);
2046 return efer & EFER_NX;
2049 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2052 struct kvm_cpuid_entry2 *e, *entry;
2055 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2056 e = &vcpu->arch.cpuid_entries[i];
2057 if (e->function == 0x80000001) {
2062 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
2063 entry->edx &= ~(1 << 20);
2064 printk(KERN_INFO "kvm: guest NX capability removed\n");
2068 /* when an old userspace process fills a new kernel module */
2069 static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2070 struct kvm_cpuid *cpuid,
2071 struct kvm_cpuid_entry __user *entries)
2074 struct kvm_cpuid_entry *cpuid_entries;
2077 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2080 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2084 if (copy_from_user(cpuid_entries, entries,
2085 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2087 for (i = 0; i < cpuid->nent; i++) {
2088 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2089 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2090 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2091 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2092 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2093 vcpu->arch.cpuid_entries[i].index = 0;
2094 vcpu->arch.cpuid_entries[i].flags = 0;
2095 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2096 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2097 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2099 vcpu->arch.cpuid_nent = cpuid->nent;
2100 cpuid_fix_nx_cap(vcpu);
2102 kvm_apic_set_version(vcpu);
2103 kvm_x86_ops->cpuid_update(vcpu);
2107 vfree(cpuid_entries);
2112 static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
2113 struct kvm_cpuid2 *cpuid,
2114 struct kvm_cpuid_entry2 __user *entries)
2119 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2122 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
2123 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
2125 vcpu->arch.cpuid_nent = cpuid->nent;
2126 kvm_apic_set_version(vcpu);
2127 kvm_x86_ops->cpuid_update(vcpu);
2135 static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
2136 struct kvm_cpuid2 *cpuid,
2137 struct kvm_cpuid_entry2 __user *entries)
2142 if (cpuid->nent < vcpu->arch.cpuid_nent)
2145 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
2146 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
2151 cpuid->nent = vcpu->arch.cpuid_nent;
2155 static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2158 entry->function = function;
2159 entry->index = index;
2160 cpuid_count(entry->function, entry->index,
2161 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
2165 #define F(x) bit(X86_FEATURE_##x)
2167 static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2168 u32 index, int *nent, int maxnent)
2170 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
2171 #ifdef CONFIG_X86_64
2172 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2174 unsigned f_lm = F(LM);
2176 unsigned f_gbpages = 0;
2179 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
2182 const u32 kvm_supported_word0_x86_features =
2183 F(FPU) | F(VME) | F(DE) | F(PSE) |
2184 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2185 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2186 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2187 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2188 0 /* Reserved, DS, ACPI */ | F(MMX) |
2189 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2190 0 /* HTT, TM, Reserved, PBE */;
2191 /* cpuid 0x80000001.edx */
2192 const u32 kvm_supported_word1_x86_features =
2193 F(FPU) | F(VME) | F(DE) | F(PSE) |
2194 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2195 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2196 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2197 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2198 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
2199 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
2200 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2202 const u32 kvm_supported_word4_x86_features =
2203 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
2204 0 /* DS-CPL, VMX, SMX, EST */ |
2205 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2206 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2207 0 /* Reserved, DCA */ | F(XMM4_1) |
2208 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
2209 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
2210 /* cpuid 0x80000001.ecx */
2211 const u32 kvm_supported_word6_x86_features =
2212 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
2213 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2214 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2215 0 /* SKINIT */ | 0 /* WDT */;
2217 /* all calls to cpuid_count() should be made on the same cpu */
2219 do_cpuid_1_ent(entry, function, index);
2224 entry->eax = min(entry->eax, (u32)0xd);
2227 entry->edx &= kvm_supported_word0_x86_features;
2228 entry->ecx &= kvm_supported_word4_x86_features;
2229 /* we support x2apic emulation even if host does not support
2230 * it since we emulate x2apic in software */
2231 entry->ecx |= F(X2APIC);
2233 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2234 * may return different values. This forces us to get_cpu() before
2235 * issuing the first command, and also to emulate this annoying behavior
2236 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2238 int t, times = entry->eax & 0xff;
2240 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2241 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2242 for (t = 1; t < times && *nent < maxnent; ++t) {
2243 do_cpuid_1_ent(&entry[t], function, 0);
2244 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2249 /* function 4 and 0xb have additional index. */
2253 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2254 /* read more entries until cache_type is zero */
2255 for (i = 1; *nent < maxnent; ++i) {
2256 cache_type = entry[i - 1].eax & 0x1f;
2259 do_cpuid_1_ent(&entry[i], function, i);
2261 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2269 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2270 /* read more entries until level_type is zero */
2271 for (i = 1; *nent < maxnent; ++i) {
2272 level_type = entry[i - 1].ecx & 0xff00;
2275 do_cpuid_1_ent(&entry[i], function, i);
2277 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2285 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2286 for (i = 1; *nent < maxnent; ++i) {
2287 if (entry[i - 1].eax == 0 && i != 2)
2289 do_cpuid_1_ent(&entry[i], function, i);
2291 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2296 case KVM_CPUID_SIGNATURE: {
2297 char signature[12] = "KVMKVMKVM\0\0";
2298 u32 *sigptr = (u32 *)signature;
2300 entry->ebx = sigptr[0];
2301 entry->ecx = sigptr[1];
2302 entry->edx = sigptr[2];
2305 case KVM_CPUID_FEATURES:
2306 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2307 (1 << KVM_FEATURE_NOP_IO_DELAY) |
2308 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2309 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
2315 entry->eax = min(entry->eax, 0x8000001a);
2318 entry->edx &= kvm_supported_word1_x86_features;
2319 entry->ecx &= kvm_supported_word6_x86_features;
2323 kvm_x86_ops->set_supported_cpuid(function, entry);
2330 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
2331 struct kvm_cpuid_entry2 __user *entries)
2333 struct kvm_cpuid_entry2 *cpuid_entries;
2334 int limit, nent = 0, r = -E2BIG;
2337 if (cpuid->nent < 1)
2339 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2340 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
2342 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2346 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2347 limit = cpuid_entries[0].eax;
2348 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2349 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2350 &nent, cpuid->nent);
2352 if (nent >= cpuid->nent)
2355 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2356 limit = cpuid_entries[nent - 1].eax;
2357 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2358 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2359 &nent, cpuid->nent);
2364 if (nent >= cpuid->nent)
2367 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2371 if (nent >= cpuid->nent)
2374 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2378 if (nent >= cpuid->nent)
2382 if (copy_to_user(entries, cpuid_entries,
2383 nent * sizeof(struct kvm_cpuid_entry2)))
2389 vfree(cpuid_entries);
2394 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2395 struct kvm_lapic_state *s)
2397 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2402 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2403 struct kvm_lapic_state *s)
2405 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2406 kvm_apic_post_state_restore(vcpu);
2407 update_cr8_intercept(vcpu);
2412 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2413 struct kvm_interrupt *irq)
2415 if (irq->irq < 0 || irq->irq >= 256)
2417 if (irqchip_in_kernel(vcpu->kvm))
2420 kvm_queue_interrupt(vcpu, irq->irq, false);
2425 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2427 kvm_inject_nmi(vcpu);
2432 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2433 struct kvm_tpr_access_ctl *tac)
2437 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2441 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2445 unsigned bank_num = mcg_cap & 0xff, bank;
2448 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2450 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2453 vcpu->arch.mcg_cap = mcg_cap;
2454 /* Init IA32_MCG_CTL to all 1s */
2455 if (mcg_cap & MCG_CTL_P)
2456 vcpu->arch.mcg_ctl = ~(u64)0;
2457 /* Init IA32_MCi_CTL to all 1s */
2458 for (bank = 0; bank < bank_num; bank++)
2459 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2464 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2465 struct kvm_x86_mce *mce)
2467 u64 mcg_cap = vcpu->arch.mcg_cap;
2468 unsigned bank_num = mcg_cap & 0xff;
2469 u64 *banks = vcpu->arch.mce_banks;
2471 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2474 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2475 * reporting is disabled
2477 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2478 vcpu->arch.mcg_ctl != ~(u64)0)
2480 banks += 4 * mce->bank;
2482 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2483 * reporting is disabled for the bank
2485 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2487 if (mce->status & MCI_STATUS_UC) {
2488 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2489 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2490 printk(KERN_DEBUG "kvm: set_mce: "
2491 "injects mce exception while "
2492 "previous one is in progress!\n");
2493 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2496 if (banks[1] & MCI_STATUS_VAL)
2497 mce->status |= MCI_STATUS_OVER;
2498 banks[2] = mce->addr;
2499 banks[3] = mce->misc;
2500 vcpu->arch.mcg_status = mce->mcg_status;
2501 banks[1] = mce->status;
2502 kvm_queue_exception(vcpu, MC_VECTOR);
2503 } else if (!(banks[1] & MCI_STATUS_VAL)
2504 || !(banks[1] & MCI_STATUS_UC)) {
2505 if (banks[1] & MCI_STATUS_VAL)
2506 mce->status |= MCI_STATUS_OVER;
2507 banks[2] = mce->addr;
2508 banks[3] = mce->misc;
2509 banks[1] = mce->status;
2511 banks[1] |= MCI_STATUS_OVER;
2515 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2516 struct kvm_vcpu_events *events)
2518 events->exception.injected =
2519 vcpu->arch.exception.pending &&
2520 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2521 events->exception.nr = vcpu->arch.exception.nr;
2522 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2523 events->exception.error_code = vcpu->arch.exception.error_code;
2525 events->interrupt.injected =
2526 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2527 events->interrupt.nr = vcpu->arch.interrupt.nr;
2528 events->interrupt.soft = 0;
2529 events->interrupt.shadow =
2530 kvm_x86_ops->get_interrupt_shadow(vcpu,
2531 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2533 events->nmi.injected = vcpu->arch.nmi_injected;
2534 events->nmi.pending = vcpu->arch.nmi_pending;
2535 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2537 events->sipi_vector = vcpu->arch.sipi_vector;
2539 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2540 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2541 | KVM_VCPUEVENT_VALID_SHADOW);
2544 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2545 struct kvm_vcpu_events *events)
2547 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2548 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2549 | KVM_VCPUEVENT_VALID_SHADOW))
2552 vcpu->arch.exception.pending = events->exception.injected;
2553 vcpu->arch.exception.nr = events->exception.nr;
2554 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2555 vcpu->arch.exception.error_code = events->exception.error_code;
2557 vcpu->arch.interrupt.pending = events->interrupt.injected;
2558 vcpu->arch.interrupt.nr = events->interrupt.nr;
2559 vcpu->arch.interrupt.soft = events->interrupt.soft;
2560 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2561 kvm_pic_clear_isr_ack(vcpu->kvm);
2562 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2563 kvm_x86_ops->set_interrupt_shadow(vcpu,
2564 events->interrupt.shadow);
2566 vcpu->arch.nmi_injected = events->nmi.injected;
2567 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2568 vcpu->arch.nmi_pending = events->nmi.pending;
2569 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2571 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2572 vcpu->arch.sipi_vector = events->sipi_vector;
2577 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2578 struct kvm_debugregs *dbgregs)
2580 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2581 dbgregs->dr6 = vcpu->arch.dr6;
2582 dbgregs->dr7 = vcpu->arch.dr7;
2586 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2587 struct kvm_debugregs *dbgregs)
2592 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2593 vcpu->arch.dr6 = dbgregs->dr6;
2594 vcpu->arch.dr7 = dbgregs->dr7;
2599 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2600 struct kvm_xsave *guest_xsave)
2603 memcpy(guest_xsave->region,
2604 &vcpu->arch.guest_fpu.state->xsave,
2607 memcpy(guest_xsave->region,
2608 &vcpu->arch.guest_fpu.state->fxsave,
2609 sizeof(struct i387_fxsave_struct));
2610 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2615 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2616 struct kvm_xsave *guest_xsave)
2619 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2622 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2623 guest_xsave->region, xstate_size);
2625 if (xstate_bv & ~XSTATE_FPSSE)
2627 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2628 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2633 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2634 struct kvm_xcrs *guest_xcrs)
2636 if (!cpu_has_xsave) {
2637 guest_xcrs->nr_xcrs = 0;
2641 guest_xcrs->nr_xcrs = 1;
2642 guest_xcrs->flags = 0;
2643 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2644 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2647 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2648 struct kvm_xcrs *guest_xcrs)
2655 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2658 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2659 /* Only support XCR0 currently */
2660 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2661 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2662 guest_xcrs->xcrs[0].value);
2670 long kvm_arch_vcpu_ioctl(struct file *filp,
2671 unsigned int ioctl, unsigned long arg)
2673 struct kvm_vcpu *vcpu = filp->private_data;
2674 void __user *argp = (void __user *)arg;
2677 struct kvm_lapic_state *lapic;
2678 struct kvm_xsave *xsave;
2679 struct kvm_xcrs *xcrs;
2685 case KVM_GET_LAPIC: {
2687 if (!vcpu->arch.apic)
2689 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2694 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2698 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2703 case KVM_SET_LAPIC: {
2705 if (!vcpu->arch.apic)
2707 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2712 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
2714 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2720 case KVM_INTERRUPT: {
2721 struct kvm_interrupt irq;
2724 if (copy_from_user(&irq, argp, sizeof irq))
2726 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2733 r = kvm_vcpu_ioctl_nmi(vcpu);
2739 case KVM_SET_CPUID: {
2740 struct kvm_cpuid __user *cpuid_arg = argp;
2741 struct kvm_cpuid cpuid;
2744 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2746 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2751 case KVM_SET_CPUID2: {
2752 struct kvm_cpuid2 __user *cpuid_arg = argp;
2753 struct kvm_cpuid2 cpuid;
2756 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2758 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2759 cpuid_arg->entries);
2764 case KVM_GET_CPUID2: {
2765 struct kvm_cpuid2 __user *cpuid_arg = argp;
2766 struct kvm_cpuid2 cpuid;
2769 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2771 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2772 cpuid_arg->entries);
2776 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2782 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2785 r = msr_io(vcpu, argp, do_set_msr, 0);
2787 case KVM_TPR_ACCESS_REPORTING: {
2788 struct kvm_tpr_access_ctl tac;
2791 if (copy_from_user(&tac, argp, sizeof tac))
2793 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2797 if (copy_to_user(argp, &tac, sizeof tac))
2802 case KVM_SET_VAPIC_ADDR: {
2803 struct kvm_vapic_addr va;
2806 if (!irqchip_in_kernel(vcpu->kvm))
2809 if (copy_from_user(&va, argp, sizeof va))
2812 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2815 case KVM_X86_SETUP_MCE: {
2819 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2821 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2824 case KVM_X86_SET_MCE: {
2825 struct kvm_x86_mce mce;
2828 if (copy_from_user(&mce, argp, sizeof mce))
2830 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2833 case KVM_GET_VCPU_EVENTS: {
2834 struct kvm_vcpu_events events;
2836 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2839 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2844 case KVM_SET_VCPU_EVENTS: {
2845 struct kvm_vcpu_events events;
2848 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2851 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2854 case KVM_GET_DEBUGREGS: {
2855 struct kvm_debugregs dbgregs;
2857 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2860 if (copy_to_user(argp, &dbgregs,
2861 sizeof(struct kvm_debugregs)))
2866 case KVM_SET_DEBUGREGS: {
2867 struct kvm_debugregs dbgregs;
2870 if (copy_from_user(&dbgregs, argp,
2871 sizeof(struct kvm_debugregs)))
2874 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2877 case KVM_GET_XSAVE: {
2878 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2883 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2886 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2891 case KVM_SET_XSAVE: {
2892 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2898 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2901 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2904 case KVM_GET_XCRS: {
2905 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2910 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2913 if (copy_to_user(argp, u.xcrs,
2914 sizeof(struct kvm_xcrs)))
2919 case KVM_SET_XCRS: {
2920 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2926 if (copy_from_user(u.xcrs, argp,
2927 sizeof(struct kvm_xcrs)))
2930 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2941 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2945 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2947 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2951 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2954 kvm->arch.ept_identity_map_addr = ident_addr;
2958 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2959 u32 kvm_nr_mmu_pages)
2961 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2964 mutex_lock(&kvm->slots_lock);
2965 spin_lock(&kvm->mmu_lock);
2967 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2968 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2970 spin_unlock(&kvm->mmu_lock);
2971 mutex_unlock(&kvm->slots_lock);
2975 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2977 return kvm->arch.n_max_mmu_pages;
2980 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2985 switch (chip->chip_id) {
2986 case KVM_IRQCHIP_PIC_MASTER:
2987 memcpy(&chip->chip.pic,
2988 &pic_irqchip(kvm)->pics[0],
2989 sizeof(struct kvm_pic_state));
2991 case KVM_IRQCHIP_PIC_SLAVE:
2992 memcpy(&chip->chip.pic,
2993 &pic_irqchip(kvm)->pics[1],
2994 sizeof(struct kvm_pic_state));
2996 case KVM_IRQCHIP_IOAPIC:
2997 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3006 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3011 switch (chip->chip_id) {
3012 case KVM_IRQCHIP_PIC_MASTER:
3013 raw_spin_lock(&pic_irqchip(kvm)->lock);
3014 memcpy(&pic_irqchip(kvm)->pics[0],
3016 sizeof(struct kvm_pic_state));
3017 raw_spin_unlock(&pic_irqchip(kvm)->lock);
3019 case KVM_IRQCHIP_PIC_SLAVE:
3020 raw_spin_lock(&pic_irqchip(kvm)->lock);
3021 memcpy(&pic_irqchip(kvm)->pics[1],
3023 sizeof(struct kvm_pic_state));
3024 raw_spin_unlock(&pic_irqchip(kvm)->lock);
3026 case KVM_IRQCHIP_IOAPIC:
3027 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3033 kvm_pic_update_irq(pic_irqchip(kvm));
3037 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3041 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3042 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3043 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3047 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3051 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3052 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3053 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3054 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3058 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3062 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3063 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3064 sizeof(ps->channels));
3065 ps->flags = kvm->arch.vpit->pit_state.flags;
3066 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3070 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3072 int r = 0, start = 0;
3073 u32 prev_legacy, cur_legacy;
3074 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3075 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3076 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3077 if (!prev_legacy && cur_legacy)
3079 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3080 sizeof(kvm->arch.vpit->pit_state.channels));
3081 kvm->arch.vpit->pit_state.flags = ps->flags;
3082 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3083 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3087 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3088 struct kvm_reinject_control *control)
3090 if (!kvm->arch.vpit)
3092 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3093 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3094 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3099 * Get (and clear) the dirty memory log for a memory slot.
3101 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3102 struct kvm_dirty_log *log)
3105 struct kvm_memory_slot *memslot;
3107 unsigned long is_dirty = 0;
3109 mutex_lock(&kvm->slots_lock);
3112 if (log->slot >= KVM_MEMORY_SLOTS)
3115 memslot = &kvm->memslots->memslots[log->slot];
3117 if (!memslot->dirty_bitmap)
3120 n = kvm_dirty_bitmap_bytes(memslot);
3122 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3123 is_dirty = memslot->dirty_bitmap[i];
3125 /* If nothing is dirty, don't bother messing with page tables. */
3127 struct kvm_memslots *slots, *old_slots;
3128 unsigned long *dirty_bitmap;
3130 spin_lock(&kvm->mmu_lock);
3131 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3132 spin_unlock(&kvm->mmu_lock);
3135 dirty_bitmap = vmalloc(n);
3138 memset(dirty_bitmap, 0, n);
3141 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3143 vfree(dirty_bitmap);
3146 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3147 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3149 old_slots = kvm->memslots;
3150 rcu_assign_pointer(kvm->memslots, slots);
3151 synchronize_srcu_expedited(&kvm->srcu);
3152 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3156 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3157 vfree(dirty_bitmap);
3160 vfree(dirty_bitmap);
3163 if (clear_user(log->dirty_bitmap, n))
3169 mutex_unlock(&kvm->slots_lock);
3173 long kvm_arch_vm_ioctl(struct file *filp,
3174 unsigned int ioctl, unsigned long arg)
3176 struct kvm *kvm = filp->private_data;
3177 void __user *argp = (void __user *)arg;
3180 * This union makes it completely explicit to gcc-3.x
3181 * that these two variables' stack usage should be
3182 * combined, not added together.
3185 struct kvm_pit_state ps;
3186 struct kvm_pit_state2 ps2;
3187 struct kvm_pit_config pit_config;
3191 case KVM_SET_TSS_ADDR:
3192 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3196 case KVM_SET_IDENTITY_MAP_ADDR: {
3200 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3202 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3207 case KVM_SET_NR_MMU_PAGES:
3208 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3212 case KVM_GET_NR_MMU_PAGES:
3213 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3215 case KVM_CREATE_IRQCHIP: {
3216 struct kvm_pic *vpic;
3218 mutex_lock(&kvm->lock);
3221 goto create_irqchip_unlock;
3223 vpic = kvm_create_pic(kvm);
3225 r = kvm_ioapic_init(kvm);
3227 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3230 goto create_irqchip_unlock;
3233 goto create_irqchip_unlock;
3235 kvm->arch.vpic = vpic;
3237 r = kvm_setup_default_irq_routing(kvm);
3239 mutex_lock(&kvm->irq_lock);
3240 kvm_ioapic_destroy(kvm);
3241 kvm_destroy_pic(kvm);
3242 mutex_unlock(&kvm->irq_lock);
3244 create_irqchip_unlock:
3245 mutex_unlock(&kvm->lock);
3248 case KVM_CREATE_PIT:
3249 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3251 case KVM_CREATE_PIT2:
3253 if (copy_from_user(&u.pit_config, argp,
3254 sizeof(struct kvm_pit_config)))
3257 mutex_lock(&kvm->slots_lock);
3260 goto create_pit_unlock;
3262 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3266 mutex_unlock(&kvm->slots_lock);
3268 case KVM_IRQ_LINE_STATUS:
3269 case KVM_IRQ_LINE: {
3270 struct kvm_irq_level irq_event;
3273 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3276 if (irqchip_in_kernel(kvm)) {
3278 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3279 irq_event.irq, irq_event.level);
3280 if (ioctl == KVM_IRQ_LINE_STATUS) {
3282 irq_event.status = status;
3283 if (copy_to_user(argp, &irq_event,
3291 case KVM_GET_IRQCHIP: {
3292 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3293 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
3299 if (copy_from_user(chip, argp, sizeof *chip))
3300 goto get_irqchip_out;
3302 if (!irqchip_in_kernel(kvm))
3303 goto get_irqchip_out;
3304 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3306 goto get_irqchip_out;
3308 if (copy_to_user(argp, chip, sizeof *chip))
3309 goto get_irqchip_out;
3317 case KVM_SET_IRQCHIP: {
3318 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3319 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
3325 if (copy_from_user(chip, argp, sizeof *chip))
3326 goto set_irqchip_out;
3328 if (!irqchip_in_kernel(kvm))
3329 goto set_irqchip_out;
3330 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3332 goto set_irqchip_out;
3342 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3345 if (!kvm->arch.vpit)
3347 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3351 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3358 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3361 if (!kvm->arch.vpit)
3363 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3369 case KVM_GET_PIT2: {
3371 if (!kvm->arch.vpit)
3373 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3377 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3382 case KVM_SET_PIT2: {
3384 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3387 if (!kvm->arch.vpit)
3389 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3395 case KVM_REINJECT_CONTROL: {
3396 struct kvm_reinject_control control;
3398 if (copy_from_user(&control, argp, sizeof(control)))
3400 r = kvm_vm_ioctl_reinject(kvm, &control);
3406 case KVM_XEN_HVM_CONFIG: {
3408 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3409 sizeof(struct kvm_xen_hvm_config)))
3412 if (kvm->arch.xen_hvm_config.flags)
3417 case KVM_SET_CLOCK: {
3418 struct kvm_clock_data user_ns;
3423 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3431 now_ns = get_kernel_ns();
3432 delta = user_ns.clock - now_ns;
3433 kvm->arch.kvmclock_offset = delta;
3436 case KVM_GET_CLOCK: {
3437 struct kvm_clock_data user_ns;
3440 now_ns = get_kernel_ns();
3441 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3445 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3458 static void kvm_init_msr_list(void)
3463 /* skip the first msrs in the list. KVM-specific */
3464 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3465 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3468 msrs_to_save[j] = msrs_to_save[i];
3471 num_msrs_to_save = j;
3474 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3477 if (vcpu->arch.apic &&
3478 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3481 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
3484 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3486 if (vcpu->arch.apic &&
3487 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3490 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
3493 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3494 struct kvm_segment *var, int seg)
3496 kvm_x86_ops->set_segment(vcpu, var, seg);
3499 void kvm_get_segment(struct kvm_vcpu *vcpu,
3500 struct kvm_segment *var, int seg)
3502 kvm_x86_ops->get_segment(vcpu, var, seg);
3505 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3510 static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3515 BUG_ON(!mmu_is_nested(vcpu));
3517 /* NPT walks are always user-walks */
3518 access |= PFERR_USER_MASK;
3519 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3520 if (t_gpa == UNMAPPED_GVA)
3521 vcpu->arch.fault.error_code |= PFERR_NESTED_MASK;
3526 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3528 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3529 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
3532 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3534 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3535 access |= PFERR_FETCH_MASK;
3536 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
3539 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3541 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3542 access |= PFERR_WRITE_MASK;
3543 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
3546 /* uses this to access any guest's mapped memory without checking CPL */
3547 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3549 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
3552 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3553 struct kvm_vcpu *vcpu, u32 access,
3557 int r = X86EMUL_CONTINUE;
3560 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3562 unsigned offset = addr & (PAGE_SIZE-1);
3563 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3566 if (gpa == UNMAPPED_GVA) {
3567 r = X86EMUL_PROPAGATE_FAULT;
3570 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3572 r = X86EMUL_IO_NEEDED;
3584 /* used for instruction fetching */
3585 static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3586 struct kvm_vcpu *vcpu, u32 *error)
3588 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3589 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3590 access | PFERR_FETCH_MASK, error);
3593 static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3594 struct kvm_vcpu *vcpu, u32 *error)
3596 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3597 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3601 static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3602 struct kvm_vcpu *vcpu, u32 *error)
3604 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3607 static int kvm_write_guest_virt_system(gva_t addr, void *val,
3609 struct kvm_vcpu *vcpu,
3613 int r = X86EMUL_CONTINUE;
3616 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3619 unsigned offset = addr & (PAGE_SIZE-1);
3620 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3623 if (gpa == UNMAPPED_GVA) {
3624 r = X86EMUL_PROPAGATE_FAULT;
3627 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3629 r = X86EMUL_IO_NEEDED;
3641 static int emulator_read_emulated(unsigned long addr,
3644 unsigned int *error_code,
3645 struct kvm_vcpu *vcpu)
3649 if (vcpu->mmio_read_completed) {
3650 memcpy(val, vcpu->mmio_data, bytes);
3651 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3652 vcpu->mmio_phys_addr, *(u64 *)val);
3653 vcpu->mmio_read_completed = 0;
3654 return X86EMUL_CONTINUE;
3657 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
3659 if (gpa == UNMAPPED_GVA)
3660 return X86EMUL_PROPAGATE_FAULT;
3662 /* For APIC access vmexit */
3663 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3666 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
3667 == X86EMUL_CONTINUE)
3668 return X86EMUL_CONTINUE;
3672 * Is this MMIO handled locally?
3674 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3675 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
3676 return X86EMUL_CONTINUE;
3679 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3681 vcpu->mmio_needed = 1;
3682 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3683 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3684 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3685 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
3687 return X86EMUL_IO_NEEDED;
3690 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3691 const void *val, int bytes)
3695 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3698 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
3702 static int emulator_write_emulated_onepage(unsigned long addr,
3705 unsigned int *error_code,
3706 struct kvm_vcpu *vcpu)
3710 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
3712 if (gpa == UNMAPPED_GVA)
3713 return X86EMUL_PROPAGATE_FAULT;
3715 /* For APIC access vmexit */
3716 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3719 if (emulator_write_phys(vcpu, gpa, val, bytes))
3720 return X86EMUL_CONTINUE;
3723 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3725 * Is this MMIO handled locally?
3727 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
3728 return X86EMUL_CONTINUE;
3730 vcpu->mmio_needed = 1;
3731 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3732 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3733 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3734 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3735 memcpy(vcpu->run->mmio.data, val, bytes);
3737 return X86EMUL_CONTINUE;
3740 int emulator_write_emulated(unsigned long addr,
3743 unsigned int *error_code,
3744 struct kvm_vcpu *vcpu)
3746 /* Crossing a page boundary? */
3747 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3750 now = -addr & ~PAGE_MASK;
3751 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3753 if (rc != X86EMUL_CONTINUE)
3759 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3763 #define CMPXCHG_TYPE(t, ptr, old, new) \
3764 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3766 #ifdef CONFIG_X86_64
3767 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3769 # define CMPXCHG64(ptr, old, new) \
3770 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3773 static int emulator_cmpxchg_emulated(unsigned long addr,
3777 unsigned int *error_code,
3778 struct kvm_vcpu *vcpu)
3785 /* guests cmpxchg8b have to be emulated atomically */
3786 if (bytes > 8 || (bytes & (bytes - 1)))
3789 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3791 if (gpa == UNMAPPED_GVA ||
3792 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3795 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3798 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3799 if (is_error_page(page)) {
3800 kvm_release_page_clean(page);
3804 kaddr = kmap_atomic(page, KM_USER0);
3805 kaddr += offset_in_page(gpa);
3808 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3811 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3814 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3817 exchanged = CMPXCHG64(kaddr, old, new);
3822 kunmap_atomic(kaddr, KM_USER0);
3823 kvm_release_page_dirty(page);
3826 return X86EMUL_CMPXCHG_FAILED;
3828 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3830 return X86EMUL_CONTINUE;
3833 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3835 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
3838 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3840 /* TODO: String I/O for in kernel device */
3843 if (vcpu->arch.pio.in)
3844 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3845 vcpu->arch.pio.size, pd);
3847 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3848 vcpu->arch.pio.port, vcpu->arch.pio.size,
3854 static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3855 unsigned int count, struct kvm_vcpu *vcpu)
3857 if (vcpu->arch.pio.count)
3860 trace_kvm_pio(0, port, size, 1);
3862 vcpu->arch.pio.port = port;
3863 vcpu->arch.pio.in = 1;
3864 vcpu->arch.pio.count = count;
3865 vcpu->arch.pio.size = size;
3867 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3869 memcpy(val, vcpu->arch.pio_data, size * count);
3870 vcpu->arch.pio.count = 0;
3874 vcpu->run->exit_reason = KVM_EXIT_IO;
3875 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3876 vcpu->run->io.size = size;
3877 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3878 vcpu->run->io.count = count;
3879 vcpu->run->io.port = port;
3884 static int emulator_pio_out_emulated(int size, unsigned short port,
3885 const void *val, unsigned int count,
3886 struct kvm_vcpu *vcpu)
3888 trace_kvm_pio(1, port, size, 1);
3890 vcpu->arch.pio.port = port;
3891 vcpu->arch.pio.in = 0;
3892 vcpu->arch.pio.count = count;
3893 vcpu->arch.pio.size = size;
3895 memcpy(vcpu->arch.pio_data, val, size * count);
3897 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3898 vcpu->arch.pio.count = 0;
3902 vcpu->run->exit_reason = KVM_EXIT_IO;
3903 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3904 vcpu->run->io.size = size;
3905 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3906 vcpu->run->io.count = count;
3907 vcpu->run->io.port = port;
3912 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3914 return kvm_x86_ops->get_segment_base(vcpu, seg);
3917 int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3919 kvm_mmu_invlpg(vcpu, address);
3920 return X86EMUL_CONTINUE;
3923 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3925 if (!need_emulate_wbinvd(vcpu))
3926 return X86EMUL_CONTINUE;
3928 if (kvm_x86_ops->has_wbinvd_exit()) {
3929 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3930 wbinvd_ipi, NULL, 1);
3931 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3934 return X86EMUL_CONTINUE;
3936 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3938 int emulate_clts(struct kvm_vcpu *vcpu)
3940 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3941 kvm_x86_ops->fpu_activate(vcpu);
3942 return X86EMUL_CONTINUE;
3945 int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
3947 return _kvm_get_dr(vcpu, dr, dest);
3950 int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
3953 return __kvm_set_dr(vcpu, dr, value);
3956 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3958 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3961 static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
3963 unsigned long value;
3967 value = kvm_read_cr0(vcpu);
3970 value = vcpu->arch.cr2;
3973 value = vcpu->arch.cr3;
3976 value = kvm_read_cr4(vcpu);
3979 value = kvm_get_cr8(vcpu);
3982 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3989 static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
3995 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
3998 vcpu->arch.cr2 = val;
4001 res = kvm_set_cr3(vcpu, val);
4004 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4007 res = __kvm_set_cr8(vcpu, val & 0xfUL);
4010 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4017 static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4019 return kvm_x86_ops->get_cpl(vcpu);
4022 static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4024 kvm_x86_ops->get_gdt(vcpu, dt);
4027 static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4029 kvm_x86_ops->get_idt(vcpu, dt);
4032 static unsigned long emulator_get_cached_segment_base(int seg,
4033 struct kvm_vcpu *vcpu)
4035 return get_segment_base(vcpu, seg);
4038 static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4039 struct kvm_vcpu *vcpu)
4041 struct kvm_segment var;
4043 kvm_get_segment(vcpu, &var, seg);
4050 set_desc_limit(desc, var.limit);
4051 set_desc_base(desc, (unsigned long)var.base);
4052 desc->type = var.type;
4054 desc->dpl = var.dpl;
4055 desc->p = var.present;
4056 desc->avl = var.avl;
4064 static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4065 struct kvm_vcpu *vcpu)
4067 struct kvm_segment var;
4069 /* needed to preserve selector */
4070 kvm_get_segment(vcpu, &var, seg);
4072 var.base = get_desc_base(desc);
4073 var.limit = get_desc_limit(desc);
4075 var.limit = (var.limit << 12) | 0xfff;
4076 var.type = desc->type;
4077 var.present = desc->p;
4078 var.dpl = desc->dpl;
4083 var.avl = desc->avl;
4084 var.present = desc->p;
4085 var.unusable = !var.present;
4088 kvm_set_segment(vcpu, &var, seg);
4092 static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4094 struct kvm_segment kvm_seg;
4096 kvm_get_segment(vcpu, &kvm_seg, seg);
4097 return kvm_seg.selector;
4100 static void emulator_set_segment_selector(u16 sel, int seg,
4101 struct kvm_vcpu *vcpu)
4103 struct kvm_segment kvm_seg;
4105 kvm_get_segment(vcpu, &kvm_seg, seg);
4106 kvm_seg.selector = sel;
4107 kvm_set_segment(vcpu, &kvm_seg, seg);
4110 static struct x86_emulate_ops emulate_ops = {
4111 .read_std = kvm_read_guest_virt_system,
4112 .write_std = kvm_write_guest_virt_system,
4113 .fetch = kvm_fetch_guest_virt,
4114 .read_emulated = emulator_read_emulated,
4115 .write_emulated = emulator_write_emulated,
4116 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4117 .pio_in_emulated = emulator_pio_in_emulated,
4118 .pio_out_emulated = emulator_pio_out_emulated,
4119 .get_cached_descriptor = emulator_get_cached_descriptor,
4120 .set_cached_descriptor = emulator_set_cached_descriptor,
4121 .get_segment_selector = emulator_get_segment_selector,
4122 .set_segment_selector = emulator_set_segment_selector,
4123 .get_cached_segment_base = emulator_get_cached_segment_base,
4124 .get_gdt = emulator_get_gdt,
4125 .get_idt = emulator_get_idt,
4126 .get_cr = emulator_get_cr,
4127 .set_cr = emulator_set_cr,
4128 .cpl = emulator_get_cpl,
4129 .get_dr = emulator_get_dr,
4130 .set_dr = emulator_set_dr,
4131 .set_msr = kvm_set_msr,
4132 .get_msr = kvm_get_msr,
4135 static void cache_all_regs(struct kvm_vcpu *vcpu)
4137 kvm_register_read(vcpu, VCPU_REGS_RAX);
4138 kvm_register_read(vcpu, VCPU_REGS_RSP);
4139 kvm_register_read(vcpu, VCPU_REGS_RIP);
4140 vcpu->arch.regs_dirty = ~0;
4143 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4145 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4147 * an sti; sti; sequence only disable interrupts for the first
4148 * instruction. So, if the last instruction, be it emulated or
4149 * not, left the system with the INT_STI flag enabled, it
4150 * means that the last instruction is an sti. We should not
4151 * leave the flag on in this case. The same goes for mov ss
4153 if (!(int_shadow & mask))
4154 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4157 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4159 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4160 if (ctxt->exception == PF_VECTOR)
4161 kvm_propagate_fault(vcpu);
4162 else if (ctxt->error_code_valid)
4163 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4165 kvm_queue_exception(vcpu, ctxt->exception);
4168 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4170 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4173 cache_all_regs(vcpu);
4175 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4177 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4178 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4179 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4180 vcpu->arch.emulate_ctxt.mode =
4181 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4182 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4183 ? X86EMUL_MODE_VM86 : cs_l
4184 ? X86EMUL_MODE_PROT64 : cs_db
4185 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4186 memset(c, 0, sizeof(struct decode_cache));
4187 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4190 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4192 ++vcpu->stat.insn_emulation_fail;
4193 trace_kvm_emulate_insn_failed(vcpu);
4194 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4195 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4196 vcpu->run->internal.ndata = 0;
4197 kvm_queue_exception(vcpu, UD_VECTOR);
4198 return EMULATE_FAIL;
4201 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4209 * if emulation was due to access to shadowed page table
4210 * and it failed try to unshadow page and re-entetr the
4211 * guest to let CPU execute the instruction.
4213 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4216 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4218 if (gpa == UNMAPPED_GVA)
4219 return true; /* let cpu generate fault */
4221 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4227 int emulate_instruction(struct kvm_vcpu *vcpu,
4233 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4235 kvm_clear_exception_queue(vcpu);
4236 vcpu->arch.mmio_fault_cr2 = cr2;
4238 * TODO: fix emulate.c to use guest_read/write_register
4239 * instead of direct ->regs accesses, can save hundred cycles
4240 * on Intel for instructions that don't read/change RSP, for
4243 cache_all_regs(vcpu);
4245 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4246 init_emulate_ctxt(vcpu);
4247 vcpu->arch.emulate_ctxt.interruptibility = 0;
4248 vcpu->arch.emulate_ctxt.exception = -1;
4249 vcpu->arch.emulate_ctxt.perm_ok = false;
4251 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
4252 if (r == X86EMUL_PROPAGATE_FAULT)
4255 trace_kvm_emulate_insn_start(vcpu);
4257 /* Only allow emulation of specific instructions on #UD
4258 * (namely VMMCALL, sysenter, sysexit, syscall)*/
4259 if (emulation_type & EMULTYPE_TRAP_UD) {
4261 return EMULATE_FAIL;
4263 case 0x01: /* VMMCALL */
4264 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4265 return EMULATE_FAIL;
4267 case 0x34: /* sysenter */
4268 case 0x35: /* sysexit */
4269 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4270 return EMULATE_FAIL;
4272 case 0x05: /* syscall */
4273 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4274 return EMULATE_FAIL;
4277 return EMULATE_FAIL;
4280 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4281 return EMULATE_FAIL;
4284 ++vcpu->stat.insn_emulation;
4286 if (reexecute_instruction(vcpu, cr2))
4287 return EMULATE_DONE;
4288 if (emulation_type & EMULTYPE_SKIP)
4289 return EMULATE_FAIL;
4290 return handle_emulation_failure(vcpu);
4294 if (emulation_type & EMULTYPE_SKIP) {
4295 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4296 return EMULATE_DONE;
4299 /* this is needed for vmware backdor interface to work since it
4300 changes registers values during IO operation */
4301 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4304 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
4306 if (r == EMULATION_FAILED) {
4307 if (reexecute_instruction(vcpu, cr2))
4308 return EMULATE_DONE;
4310 return handle_emulation_failure(vcpu);
4314 if (vcpu->arch.emulate_ctxt.exception >= 0) {
4315 inject_emulated_exception(vcpu);
4317 } else if (vcpu->arch.pio.count) {
4318 if (!vcpu->arch.pio.in)
4319 vcpu->arch.pio.count = 0;
4320 r = EMULATE_DO_MMIO;
4321 } else if (vcpu->mmio_needed) {
4322 if (vcpu->mmio_is_write)
4323 vcpu->mmio_needed = 0;
4324 r = EMULATE_DO_MMIO;
4325 } else if (r == EMULATION_RESTART)
4330 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4331 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4332 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4333 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4337 EXPORT_SYMBOL_GPL(emulate_instruction);
4339 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4341 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4342 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4343 /* do not return to emulator after return from userspace */
4344 vcpu->arch.pio.count = 0;
4347 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4349 static void tsc_bad(void *info)
4351 __get_cpu_var(cpu_tsc_khz) = 0;
4354 static void tsc_khz_changed(void *data)
4356 struct cpufreq_freqs *freq = data;
4357 unsigned long khz = 0;
4361 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4362 khz = cpufreq_quick_get(raw_smp_processor_id());
4365 __get_cpu_var(cpu_tsc_khz) = khz;
4368 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4371 struct cpufreq_freqs *freq = data;
4373 struct kvm_vcpu *vcpu;
4374 int i, send_ipi = 0;
4377 * We allow guests to temporarily run on slowing clocks,
4378 * provided we notify them after, or to run on accelerating
4379 * clocks, provided we notify them before. Thus time never
4382 * However, we have a problem. We can't atomically update
4383 * the frequency of a given CPU from this function; it is
4384 * merely a notifier, which can be called from any CPU.
4385 * Changing the TSC frequency at arbitrary points in time
4386 * requires a recomputation of local variables related to
4387 * the TSC for each VCPU. We must flag these local variables
4388 * to be updated and be sure the update takes place with the
4389 * new frequency before any guests proceed.
4391 * Unfortunately, the combination of hotplug CPU and frequency
4392 * change creates an intractable locking scenario; the order
4393 * of when these callouts happen is undefined with respect to
4394 * CPU hotplug, and they can race with each other. As such,
4395 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4396 * undefined; you can actually have a CPU frequency change take
4397 * place in between the computation of X and the setting of the
4398 * variable. To protect against this problem, all updates of
4399 * the per_cpu tsc_khz variable are done in an interrupt
4400 * protected IPI, and all callers wishing to update the value
4401 * must wait for a synchronous IPI to complete (which is trivial
4402 * if the caller is on the CPU already). This establishes the
4403 * necessary total order on variable updates.
4405 * Note that because a guest time update may take place
4406 * anytime after the setting of the VCPU's request bit, the
4407 * correct TSC value must be set before the request. However,
4408 * to ensure the update actually makes it to any guest which
4409 * starts running in hardware virtualization between the set
4410 * and the acquisition of the spinlock, we must also ping the
4411 * CPU after setting the request bit.
4415 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4417 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4420 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4422 spin_lock(&kvm_lock);
4423 list_for_each_entry(kvm, &vm_list, vm_list) {
4424 kvm_for_each_vcpu(i, vcpu, kvm) {
4425 if (vcpu->cpu != freq->cpu)
4427 if (!kvm_request_guest_time_update(vcpu))
4429 if (vcpu->cpu != smp_processor_id())
4433 spin_unlock(&kvm_lock);
4435 if (freq->old < freq->new && send_ipi) {
4437 * We upscale the frequency. Must make the guest
4438 * doesn't see old kvmclock values while running with
4439 * the new frequency, otherwise we risk the guest sees
4440 * time go backwards.
4442 * In case we update the frequency for another cpu
4443 * (which might be in guest context) send an interrupt
4444 * to kick the cpu out of guest context. Next time
4445 * guest context is entered kvmclock will be updated,
4446 * so the guest will not see stale values.
4448 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4453 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4454 .notifier_call = kvmclock_cpufreq_notifier
4457 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4458 unsigned long action, void *hcpu)
4460 unsigned int cpu = (unsigned long)hcpu;
4464 case CPU_DOWN_FAILED:
4465 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4467 case CPU_DOWN_PREPARE:
4468 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4474 static struct notifier_block kvmclock_cpu_notifier_block = {
4475 .notifier_call = kvmclock_cpu_notifier,
4476 .priority = -INT_MAX
4479 static void kvm_timer_init(void)
4483 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4484 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4485 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4486 CPUFREQ_TRANSITION_NOTIFIER);
4488 for_each_online_cpu(cpu)
4489 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4492 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4494 static int kvm_is_in_guest(void)
4496 return percpu_read(current_vcpu) != NULL;
4499 static int kvm_is_user_mode(void)
4503 if (percpu_read(current_vcpu))
4504 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
4506 return user_mode != 0;
4509 static unsigned long kvm_get_guest_ip(void)
4511 unsigned long ip = 0;
4513 if (percpu_read(current_vcpu))
4514 ip = kvm_rip_read(percpu_read(current_vcpu));
4519 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4520 .is_in_guest = kvm_is_in_guest,
4521 .is_user_mode = kvm_is_user_mode,
4522 .get_guest_ip = kvm_get_guest_ip,
4525 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4527 percpu_write(current_vcpu, vcpu);
4529 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4531 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4533 percpu_write(current_vcpu, NULL);
4535 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4537 int kvm_arch_init(void *opaque)
4540 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4543 printk(KERN_ERR "kvm: already loaded the other module\n");
4548 if (!ops->cpu_has_kvm_support()) {
4549 printk(KERN_ERR "kvm: no hardware support\n");
4553 if (ops->disabled_by_bios()) {
4554 printk(KERN_ERR "kvm: disabled by bios\n");
4559 r = kvm_mmu_module_init();
4563 kvm_init_msr_list();
4566 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
4567 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4568 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4569 PT_DIRTY_MASK, PT64_NX_MASK, 0);
4573 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4576 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4584 void kvm_arch_exit(void)
4586 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4588 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4589 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4590 CPUFREQ_TRANSITION_NOTIFIER);
4591 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4593 kvm_mmu_module_exit();
4596 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4598 ++vcpu->stat.halt_exits;
4599 if (irqchip_in_kernel(vcpu->kvm)) {
4600 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4603 vcpu->run->exit_reason = KVM_EXIT_HLT;
4607 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4609 static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4612 if (is_long_mode(vcpu))
4615 return a0 | ((gpa_t)a1 << 32);
4618 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4620 u64 param, ingpa, outgpa, ret;
4621 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4622 bool fast, longmode;
4626 * hypercall generates UD from non zero cpl and real mode
4629 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4630 kvm_queue_exception(vcpu, UD_VECTOR);
4634 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4635 longmode = is_long_mode(vcpu) && cs_l == 1;
4638 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4639 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4640 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4641 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4642 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4643 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4645 #ifdef CONFIG_X86_64
4647 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4648 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4649 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4653 code = param & 0xffff;
4654 fast = (param >> 16) & 0x1;
4655 rep_cnt = (param >> 32) & 0xfff;
4656 rep_idx = (param >> 48) & 0xfff;
4658 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4661 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4662 kvm_vcpu_on_spin(vcpu);
4665 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4669 ret = res | (((u64)rep_done & 0xfff) << 32);
4671 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4673 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4674 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4680 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4682 unsigned long nr, a0, a1, a2, a3, ret;
4685 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4686 return kvm_hv_hypercall(vcpu);
4688 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4689 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4690 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4691 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4692 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
4694 trace_kvm_hypercall(nr, a0, a1, a2, a3);
4696 if (!is_long_mode(vcpu)) {
4704 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4710 case KVM_HC_VAPIC_POLL_IRQ:
4714 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4721 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4722 ++vcpu->stat.hypercalls;
4725 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4727 int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4729 char instruction[3];
4730 unsigned long rip = kvm_rip_read(vcpu);
4733 * Blow out the MMU to ensure that no other VCPU has an active mapping
4734 * to ensure that the updated hypercall appears atomically across all
4737 kvm_mmu_zap_all(vcpu->kvm);
4739 kvm_x86_ops->patch_hypercall(vcpu, instruction);
4741 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
4744 void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4746 struct desc_ptr dt = { limit, base };
4748 kvm_x86_ops->set_gdt(vcpu, &dt);
4751 void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4753 struct desc_ptr dt = { limit, base };
4755 kvm_x86_ops->set_idt(vcpu, &dt);
4758 static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4760 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4761 int j, nent = vcpu->arch.cpuid_nent;
4763 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4764 /* when no next entry is found, the current entry[i] is reselected */
4765 for (j = i + 1; ; j = (j + 1) % nent) {
4766 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
4767 if (ej->function == e->function) {
4768 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4772 return 0; /* silence gcc, even though control never reaches here */
4775 /* find an entry with matching function, matching index (if needed), and that
4776 * should be read next (if it's stateful) */
4777 static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4778 u32 function, u32 index)
4780 if (e->function != function)
4782 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4784 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
4785 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
4790 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4791 u32 function, u32 index)
4794 struct kvm_cpuid_entry2 *best = NULL;
4796 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
4797 struct kvm_cpuid_entry2 *e;
4799 e = &vcpu->arch.cpuid_entries[i];
4800 if (is_matching_cpuid_entry(e, function, index)) {
4801 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4802 move_to_next_stateful_cpuid_entry(vcpu, i);
4807 * Both basic or both extended?
4809 if (((e->function ^ function) & 0x80000000) == 0)
4810 if (!best || e->function > best->function)
4815 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
4817 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4819 struct kvm_cpuid_entry2 *best;
4821 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4822 if (!best || best->eax < 0x80000008)
4824 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4826 return best->eax & 0xff;
4831 void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4833 u32 function, index;
4834 struct kvm_cpuid_entry2 *best;
4836 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4837 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4838 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4839 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4840 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4841 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4842 best = kvm_find_cpuid_entry(vcpu, function, index);
4844 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4845 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4846 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4847 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
4849 kvm_x86_ops->skip_emulated_instruction(vcpu);
4850 trace_kvm_cpuid(function,
4851 kvm_register_read(vcpu, VCPU_REGS_RAX),
4852 kvm_register_read(vcpu, VCPU_REGS_RBX),
4853 kvm_register_read(vcpu, VCPU_REGS_RCX),
4854 kvm_register_read(vcpu, VCPU_REGS_RDX));
4856 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
4859 * Check if userspace requested an interrupt window, and that the
4860 * interrupt window is open.
4862 * No need to exit to userspace if we already have an interrupt queued.
4864 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
4866 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
4867 vcpu->run->request_interrupt_window &&
4868 kvm_arch_interrupt_allowed(vcpu));
4871 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
4873 struct kvm_run *kvm_run = vcpu->run;
4875 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
4876 kvm_run->cr8 = kvm_get_cr8(vcpu);
4877 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4878 if (irqchip_in_kernel(vcpu->kvm))
4879 kvm_run->ready_for_interrupt_injection = 1;
4881 kvm_run->ready_for_interrupt_injection =
4882 kvm_arch_interrupt_allowed(vcpu) &&
4883 !kvm_cpu_has_interrupt(vcpu) &&
4884 !kvm_event_needs_reinjection(vcpu);
4887 static void vapic_enter(struct kvm_vcpu *vcpu)
4889 struct kvm_lapic *apic = vcpu->arch.apic;
4892 if (!apic || !apic->vapic_addr)
4895 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4897 vcpu->arch.apic->vapic_page = page;
4900 static void vapic_exit(struct kvm_vcpu *vcpu)
4902 struct kvm_lapic *apic = vcpu->arch.apic;
4905 if (!apic || !apic->vapic_addr)
4908 idx = srcu_read_lock(&vcpu->kvm->srcu);
4909 kvm_release_page_dirty(apic->vapic_page);
4910 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4911 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4914 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4918 if (!kvm_x86_ops->update_cr8_intercept)
4921 if (!vcpu->arch.apic)
4924 if (!vcpu->arch.apic->vapic_addr)
4925 max_irr = kvm_lapic_find_highest_irr(vcpu);
4932 tpr = kvm_lapic_get_cr8(vcpu);
4934 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4937 static void inject_pending_event(struct kvm_vcpu *vcpu)
4939 /* try to reinject previous events if any */
4940 if (vcpu->arch.exception.pending) {
4941 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4942 vcpu->arch.exception.has_error_code,
4943 vcpu->arch.exception.error_code);
4944 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4945 vcpu->arch.exception.has_error_code,
4946 vcpu->arch.exception.error_code,
4947 vcpu->arch.exception.reinject);
4951 if (vcpu->arch.nmi_injected) {
4952 kvm_x86_ops->set_nmi(vcpu);
4956 if (vcpu->arch.interrupt.pending) {
4957 kvm_x86_ops->set_irq(vcpu);
4961 /* try to inject new event if pending */
4962 if (vcpu->arch.nmi_pending) {
4963 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4964 vcpu->arch.nmi_pending = false;
4965 vcpu->arch.nmi_injected = true;
4966 kvm_x86_ops->set_nmi(vcpu);
4968 } else if (kvm_cpu_has_interrupt(vcpu)) {
4969 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
4970 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4972 kvm_x86_ops->set_irq(vcpu);
4977 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4979 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4980 !vcpu->guest_xcr0_loaded) {
4981 /* kvm_set_xcr() also depends on this */
4982 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4983 vcpu->guest_xcr0_loaded = 1;
4987 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4989 if (vcpu->guest_xcr0_loaded) {
4990 if (vcpu->arch.xcr0 != host_xcr0)
4991 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4992 vcpu->guest_xcr0_loaded = 0;
4996 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
4999 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5000 vcpu->run->request_interrupt_window;
5002 if (vcpu->requests) {
5003 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5004 kvm_mmu_unload(vcpu);
5005 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5006 __kvm_migrate_timers(vcpu);
5007 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) {
5008 r = kvm_write_guest_time(vcpu);
5012 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5013 kvm_mmu_sync_roots(vcpu);
5014 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5015 kvm_x86_ops->tlb_flush(vcpu);
5016 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5017 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5021 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5022 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5026 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5027 vcpu->fpu_active = 0;
5028 kvm_x86_ops->fpu_deactivate(vcpu);
5032 r = kvm_mmu_reload(vcpu);
5038 kvm_x86_ops->prepare_guest_switch(vcpu);
5039 if (vcpu->fpu_active)
5040 kvm_load_guest_fpu(vcpu);
5041 kvm_load_guest_xcr0(vcpu);
5043 atomic_set(&vcpu->guest_mode, 1);
5046 local_irq_disable();
5048 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5049 || need_resched() || signal_pending(current)) {
5050 atomic_set(&vcpu->guest_mode, 0);
5058 inject_pending_event(vcpu);
5060 /* enable NMI/IRQ window open exits if needed */
5061 if (vcpu->arch.nmi_pending)
5062 kvm_x86_ops->enable_nmi_window(vcpu);
5063 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5064 kvm_x86_ops->enable_irq_window(vcpu);
5066 if (kvm_lapic_enabled(vcpu)) {
5067 update_cr8_intercept(vcpu);
5068 kvm_lapic_sync_to_vapic(vcpu);
5071 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5075 if (unlikely(vcpu->arch.switch_db_regs)) {
5077 set_debugreg(vcpu->arch.eff_db[0], 0);
5078 set_debugreg(vcpu->arch.eff_db[1], 1);
5079 set_debugreg(vcpu->arch.eff_db[2], 2);
5080 set_debugreg(vcpu->arch.eff_db[3], 3);
5083 trace_kvm_entry(vcpu->vcpu_id);
5084 kvm_x86_ops->run(vcpu);
5087 * If the guest has used debug registers, at least dr7
5088 * will be disabled while returning to the host.
5089 * If we don't have active breakpoints in the host, we don't
5090 * care about the messed up debug address registers. But if
5091 * we have some of them active, restore the old state.
5093 if (hw_breakpoint_active())
5094 hw_breakpoint_restore();
5096 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5098 atomic_set(&vcpu->guest_mode, 0);
5105 * We must have an instruction between local_irq_enable() and
5106 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5107 * the interrupt shadow. The stat.exits increment will do nicely.
5108 * But we need to prevent reordering, hence this barrier():
5116 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5119 * Profile KVM exit RIPs:
5121 if (unlikely(prof_on == KVM_PROFILING)) {
5122 unsigned long rip = kvm_rip_read(vcpu);
5123 profile_hit(KVM_PROFILING, (void *)rip);
5127 kvm_lapic_sync_from_vapic(vcpu);
5129 r = kvm_x86_ops->handle_exit(vcpu);
5135 static int __vcpu_run(struct kvm_vcpu *vcpu)
5138 struct kvm *kvm = vcpu->kvm;
5140 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5141 pr_debug("vcpu %d received sipi with vector # %x\n",
5142 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5143 kvm_lapic_reset(vcpu);
5144 r = kvm_arch_vcpu_reset(vcpu);
5147 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5150 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5155 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
5156 r = vcpu_enter_guest(vcpu);
5158 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5159 kvm_vcpu_block(vcpu);
5160 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5161 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5163 switch(vcpu->arch.mp_state) {
5164 case KVM_MP_STATE_HALTED:
5165 vcpu->arch.mp_state =
5166 KVM_MP_STATE_RUNNABLE;
5167 case KVM_MP_STATE_RUNNABLE:
5169 case KVM_MP_STATE_SIPI_RECEIVED:
5180 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5181 if (kvm_cpu_has_pending_timer(vcpu))
5182 kvm_inject_pending_timer_irqs(vcpu);
5184 if (dm_request_for_irq_injection(vcpu)) {
5186 vcpu->run->exit_reason = KVM_EXIT_INTR;
5187 ++vcpu->stat.request_irq_exits;
5189 if (signal_pending(current)) {
5191 vcpu->run->exit_reason = KVM_EXIT_INTR;
5192 ++vcpu->stat.signal_exits;
5194 if (need_resched()) {
5195 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5197 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5201 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5208 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5213 if (vcpu->sigset_active)
5214 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5216 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5217 kvm_vcpu_block(vcpu);
5218 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5223 /* re-sync apic's tpr */
5224 if (!irqchip_in_kernel(vcpu->kvm))
5225 kvm_set_cr8(vcpu, kvm_run->cr8);
5227 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
5228 if (vcpu->mmio_needed) {
5229 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5230 vcpu->mmio_read_completed = 1;
5231 vcpu->mmio_needed = 0;
5233 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5234 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
5235 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5236 if (r != EMULATE_DONE) {
5241 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5242 kvm_register_write(vcpu, VCPU_REGS_RAX,
5243 kvm_run->hypercall.ret);
5245 r = __vcpu_run(vcpu);
5248 post_kvm_run_save(vcpu);
5249 if (vcpu->sigset_active)
5250 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5255 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5257 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5258 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5259 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5260 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5261 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5262 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5263 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5264 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5265 #ifdef CONFIG_X86_64
5266 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5267 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5268 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5269 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5270 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5271 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5272 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5273 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5276 regs->rip = kvm_rip_read(vcpu);
5277 regs->rflags = kvm_get_rflags(vcpu);
5282 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5284 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5285 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5286 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5287 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5288 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5289 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5290 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5291 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5292 #ifdef CONFIG_X86_64
5293 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5294 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5295 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5296 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5297 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5298 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5299 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5300 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5303 kvm_rip_write(vcpu, regs->rip);
5304 kvm_set_rflags(vcpu, regs->rflags);
5306 vcpu->arch.exception.pending = false;
5311 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5313 struct kvm_segment cs;
5315 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5319 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5321 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5322 struct kvm_sregs *sregs)
5326 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5327 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5328 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5329 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5330 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5331 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5333 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5334 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5336 kvm_x86_ops->get_idt(vcpu, &dt);
5337 sregs->idt.limit = dt.size;
5338 sregs->idt.base = dt.address;
5339 kvm_x86_ops->get_gdt(vcpu, &dt);
5340 sregs->gdt.limit = dt.size;
5341 sregs->gdt.base = dt.address;
5343 sregs->cr0 = kvm_read_cr0(vcpu);
5344 sregs->cr2 = vcpu->arch.cr2;
5345 sregs->cr3 = vcpu->arch.cr3;
5346 sregs->cr4 = kvm_read_cr4(vcpu);
5347 sregs->cr8 = kvm_get_cr8(vcpu);
5348 sregs->efer = vcpu->arch.efer;
5349 sregs->apic_base = kvm_get_apic_base(vcpu);
5351 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5353 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5354 set_bit(vcpu->arch.interrupt.nr,
5355 (unsigned long *)sregs->interrupt_bitmap);
5360 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5361 struct kvm_mp_state *mp_state)
5363 mp_state->mp_state = vcpu->arch.mp_state;
5367 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5368 struct kvm_mp_state *mp_state)
5370 vcpu->arch.mp_state = mp_state->mp_state;
5374 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5375 bool has_error_code, u32 error_code)
5377 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
5380 init_emulate_ctxt(vcpu);
5382 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
5383 tss_selector, reason, has_error_code,
5387 return EMULATE_FAIL;
5389 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
5390 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
5391 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5392 return EMULATE_DONE;
5394 EXPORT_SYMBOL_GPL(kvm_task_switch);
5396 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5397 struct kvm_sregs *sregs)
5399 int mmu_reset_needed = 0;
5400 int pending_vec, max_bits;
5403 dt.size = sregs->idt.limit;
5404 dt.address = sregs->idt.base;
5405 kvm_x86_ops->set_idt(vcpu, &dt);
5406 dt.size = sregs->gdt.limit;
5407 dt.address = sregs->gdt.base;
5408 kvm_x86_ops->set_gdt(vcpu, &dt);
5410 vcpu->arch.cr2 = sregs->cr2;
5411 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
5412 vcpu->arch.cr3 = sregs->cr3;
5414 kvm_set_cr8(vcpu, sregs->cr8);
5416 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5417 kvm_x86_ops->set_efer(vcpu, sregs->efer);
5418 kvm_set_apic_base(vcpu, sregs->apic_base);
5420 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5421 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5422 vcpu->arch.cr0 = sregs->cr0;
5424 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5425 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5426 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5427 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
5428 mmu_reset_needed = 1;
5431 if (mmu_reset_needed)
5432 kvm_mmu_reset_context(vcpu);
5434 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5435 pending_vec = find_first_bit(
5436 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5437 if (pending_vec < max_bits) {
5438 kvm_queue_interrupt(vcpu, pending_vec, false);
5439 pr_debug("Set back pending irq %d\n", pending_vec);
5440 if (irqchip_in_kernel(vcpu->kvm))
5441 kvm_pic_clear_isr_ack(vcpu->kvm);
5444 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5445 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5446 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5447 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5448 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5449 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5451 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5452 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5454 update_cr8_intercept(vcpu);
5456 /* Older userspace won't unhalt the vcpu on reset. */
5457 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5458 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5460 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5465 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5466 struct kvm_guest_debug *dbg)
5468 unsigned long rflags;
5471 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5473 if (vcpu->arch.exception.pending)
5475 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5476 kvm_queue_exception(vcpu, DB_VECTOR);
5478 kvm_queue_exception(vcpu, BP_VECTOR);
5482 * Read rflags as long as potentially injected trace flags are still
5485 rflags = kvm_get_rflags(vcpu);
5487 vcpu->guest_debug = dbg->control;
5488 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5489 vcpu->guest_debug = 0;
5491 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5492 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5493 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5494 vcpu->arch.switch_db_regs =
5495 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5497 for (i = 0; i < KVM_NR_DB_REGS; i++)
5498 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5499 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5502 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5503 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5504 get_segment_base(vcpu, VCPU_SREG_CS);
5507 * Trigger an rflags update that will inject or remove the trace
5510 kvm_set_rflags(vcpu, rflags);
5512 kvm_x86_ops->set_guest_debug(vcpu, dbg);
5522 * Translate a guest virtual address to a guest physical address.
5524 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5525 struct kvm_translation *tr)
5527 unsigned long vaddr = tr->linear_address;
5531 idx = srcu_read_lock(&vcpu->kvm->srcu);
5532 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5533 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5534 tr->physical_address = gpa;
5535 tr->valid = gpa != UNMAPPED_GVA;
5542 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5544 struct i387_fxsave_struct *fxsave =
5545 &vcpu->arch.guest_fpu.state->fxsave;
5547 memcpy(fpu->fpr, fxsave->st_space, 128);
5548 fpu->fcw = fxsave->cwd;
5549 fpu->fsw = fxsave->swd;
5550 fpu->ftwx = fxsave->twd;
5551 fpu->last_opcode = fxsave->fop;
5552 fpu->last_ip = fxsave->rip;
5553 fpu->last_dp = fxsave->rdp;
5554 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5559 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5561 struct i387_fxsave_struct *fxsave =
5562 &vcpu->arch.guest_fpu.state->fxsave;
5564 memcpy(fxsave->st_space, fpu->fpr, 128);
5565 fxsave->cwd = fpu->fcw;
5566 fxsave->swd = fpu->fsw;
5567 fxsave->twd = fpu->ftwx;
5568 fxsave->fop = fpu->last_opcode;
5569 fxsave->rip = fpu->last_ip;
5570 fxsave->rdp = fpu->last_dp;
5571 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5576 int fx_init(struct kvm_vcpu *vcpu)
5580 err = fpu_alloc(&vcpu->arch.guest_fpu);
5584 fpu_finit(&vcpu->arch.guest_fpu);
5587 * Ensure guest xcr0 is valid for loading
5589 vcpu->arch.xcr0 = XSTATE_FP;
5591 vcpu->arch.cr0 |= X86_CR0_ET;
5595 EXPORT_SYMBOL_GPL(fx_init);
5597 static void fx_free(struct kvm_vcpu *vcpu)
5599 fpu_free(&vcpu->arch.guest_fpu);
5602 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5604 if (vcpu->guest_fpu_loaded)
5608 * Restore all possible states in the guest,
5609 * and assume host would use all available bits.
5610 * Guest xcr0 would be loaded later.
5612 kvm_put_guest_xcr0(vcpu);
5613 vcpu->guest_fpu_loaded = 1;
5614 unlazy_fpu(current);
5615 fpu_restore_checking(&vcpu->arch.guest_fpu);
5619 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5621 kvm_put_guest_xcr0(vcpu);
5623 if (!vcpu->guest_fpu_loaded)
5626 vcpu->guest_fpu_loaded = 0;
5627 fpu_save_init(&vcpu->arch.guest_fpu);
5628 ++vcpu->stat.fpu_reload;
5629 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5633 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5635 if (vcpu->arch.time_page) {
5636 kvm_release_page_dirty(vcpu->arch.time_page);
5637 vcpu->arch.time_page = NULL;
5640 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5642 kvm_x86_ops->vcpu_free(vcpu);
5645 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5648 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5649 printk_once(KERN_WARNING
5650 "kvm: SMP vm created on host with unstable TSC; "
5651 "guest TSC will not be reliable\n");
5652 return kvm_x86_ops->vcpu_create(kvm, id);
5655 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5659 vcpu->arch.mtrr_state.have_fixed = 1;
5661 r = kvm_arch_vcpu_reset(vcpu);
5663 r = kvm_mmu_setup(vcpu);
5670 kvm_x86_ops->vcpu_free(vcpu);
5674 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
5677 kvm_mmu_unload(vcpu);
5681 kvm_x86_ops->vcpu_free(vcpu);
5684 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5686 vcpu->arch.nmi_pending = false;
5687 vcpu->arch.nmi_injected = false;
5689 vcpu->arch.switch_db_regs = 0;
5690 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5691 vcpu->arch.dr6 = DR6_FIXED_1;
5692 vcpu->arch.dr7 = DR7_FIXED_1;
5694 return kvm_x86_ops->vcpu_reset(vcpu);
5697 int kvm_arch_hardware_enable(void *garbage)
5700 struct kvm_vcpu *vcpu;
5703 kvm_shared_msr_cpu_online();
5704 list_for_each_entry(kvm, &vm_list, vm_list)
5705 kvm_for_each_vcpu(i, vcpu, kvm)
5706 if (vcpu->cpu == smp_processor_id())
5707 kvm_request_guest_time_update(vcpu);
5708 return kvm_x86_ops->hardware_enable(garbage);
5711 void kvm_arch_hardware_disable(void *garbage)
5713 kvm_x86_ops->hardware_disable(garbage);
5714 drop_user_return_notifiers(garbage);
5717 int kvm_arch_hardware_setup(void)
5719 return kvm_x86_ops->hardware_setup();
5722 void kvm_arch_hardware_unsetup(void)
5724 kvm_x86_ops->hardware_unsetup();
5727 void kvm_arch_check_processor_compat(void *rtn)
5729 kvm_x86_ops->check_processor_compatibility(rtn);
5732 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5738 BUG_ON(vcpu->kvm == NULL);
5741 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
5742 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
5743 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
5744 vcpu->arch.mmu.translate_gpa = translate_gpa;
5745 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5746 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
5747 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5749 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
5751 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5756 vcpu->arch.pio_data = page_address(page);
5758 r = kvm_mmu_create(vcpu);
5760 goto fail_free_pio_data;
5762 if (irqchip_in_kernel(kvm)) {
5763 r = kvm_create_lapic(vcpu);
5765 goto fail_mmu_destroy;
5768 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5770 if (!vcpu->arch.mce_banks) {
5772 goto fail_free_lapic;
5774 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5776 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5777 goto fail_free_mce_banks;
5780 fail_free_mce_banks:
5781 kfree(vcpu->arch.mce_banks);
5783 kvm_free_lapic(vcpu);
5785 kvm_mmu_destroy(vcpu);
5787 free_page((unsigned long)vcpu->arch.pio_data);
5792 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5796 kfree(vcpu->arch.mce_banks);
5797 kvm_free_lapic(vcpu);
5798 idx = srcu_read_lock(&vcpu->kvm->srcu);
5799 kvm_mmu_destroy(vcpu);
5800 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5801 free_page((unsigned long)vcpu->arch.pio_data);
5804 struct kvm *kvm_arch_create_vm(void)
5806 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5809 return ERR_PTR(-ENOMEM);
5811 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
5812 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
5814 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5815 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5817 spin_lock_init(&kvm->arch.tsc_write_lock);
5822 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5825 kvm_mmu_unload(vcpu);
5829 static void kvm_free_vcpus(struct kvm *kvm)
5832 struct kvm_vcpu *vcpu;
5835 * Unpin any mmu pages first.
5837 kvm_for_each_vcpu(i, vcpu, kvm)
5838 kvm_unload_vcpu_mmu(vcpu);
5839 kvm_for_each_vcpu(i, vcpu, kvm)
5840 kvm_arch_vcpu_free(vcpu);
5842 mutex_lock(&kvm->lock);
5843 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5844 kvm->vcpus[i] = NULL;
5846 atomic_set(&kvm->online_vcpus, 0);
5847 mutex_unlock(&kvm->lock);
5850 void kvm_arch_sync_events(struct kvm *kvm)
5852 kvm_free_all_assigned_devices(kvm);
5856 void kvm_arch_destroy_vm(struct kvm *kvm)
5858 kvm_iommu_unmap_guest(kvm);
5859 kfree(kvm->arch.vpic);
5860 kfree(kvm->arch.vioapic);
5861 kvm_free_vcpus(kvm);
5862 kvm_free_physmem(kvm);
5863 if (kvm->arch.apic_access_page)
5864 put_page(kvm->arch.apic_access_page);
5865 if (kvm->arch.ept_identity_pagetable)
5866 put_page(kvm->arch.ept_identity_pagetable);
5867 cleanup_srcu_struct(&kvm->srcu);
5871 int kvm_arch_prepare_memory_region(struct kvm *kvm,
5872 struct kvm_memory_slot *memslot,
5873 struct kvm_memory_slot old,
5874 struct kvm_userspace_memory_region *mem,
5877 int npages = memslot->npages;
5878 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5880 /* Prevent internal slot pages from being moved by fork()/COW. */
5881 if (memslot->id >= KVM_MEMORY_SLOTS)
5882 map_flags = MAP_SHARED | MAP_ANONYMOUS;
5884 /*To keep backward compatibility with older userspace,
5885 *x86 needs to hanlde !user_alloc case.
5888 if (npages && !old.rmap) {
5889 unsigned long userspace_addr;
5891 down_write(¤t->mm->mmap_sem);
5892 userspace_addr = do_mmap(NULL, 0,
5894 PROT_READ | PROT_WRITE,
5897 up_write(¤t->mm->mmap_sem);
5899 if (IS_ERR((void *)userspace_addr))
5900 return PTR_ERR((void *)userspace_addr);
5902 memslot->userspace_addr = userspace_addr;
5910 void kvm_arch_commit_memory_region(struct kvm *kvm,
5911 struct kvm_userspace_memory_region *mem,
5912 struct kvm_memory_slot old,
5916 int npages = mem->memory_size >> PAGE_SHIFT;
5918 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5921 down_write(¤t->mm->mmap_sem);
5922 ret = do_munmap(current->mm, old.userspace_addr,
5923 old.npages * PAGE_SIZE);
5924 up_write(¤t->mm->mmap_sem);
5927 "kvm_vm_ioctl_set_memory_region: "
5928 "failed to munmap memory\n");
5931 spin_lock(&kvm->mmu_lock);
5932 if (!kvm->arch.n_requested_mmu_pages) {
5933 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5934 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5937 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
5938 spin_unlock(&kvm->mmu_lock);
5941 void kvm_arch_flush_shadow(struct kvm *kvm)
5943 kvm_mmu_zap_all(kvm);
5944 kvm_reload_remote_mmus(kvm);
5947 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5949 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
5950 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5951 || vcpu->arch.nmi_pending ||
5952 (kvm_arch_interrupt_allowed(vcpu) &&
5953 kvm_cpu_has_interrupt(vcpu));
5956 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5959 int cpu = vcpu->cpu;
5961 if (waitqueue_active(&vcpu->wq)) {
5962 wake_up_interruptible(&vcpu->wq);
5963 ++vcpu->stat.halt_wakeup;
5967 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5968 if (atomic_xchg(&vcpu->guest_mode, 0))
5969 smp_send_reschedule(cpu);
5973 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5975 return kvm_x86_ops->interrupt_allowed(vcpu);
5978 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5980 unsigned long current_rip = kvm_rip_read(vcpu) +
5981 get_segment_base(vcpu, VCPU_SREG_CS);
5983 return current_rip == linear_rip;
5985 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5987 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5989 unsigned long rflags;
5991 rflags = kvm_x86_ops->get_rflags(vcpu);
5992 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5993 rflags &= ~X86_EFLAGS_TF;
5996 EXPORT_SYMBOL_GPL(kvm_get_rflags);
5998 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6000 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6001 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6002 rflags |= X86_EFLAGS_TF;
6003 kvm_x86_ops->set_rflags(vcpu, rflags);
6005 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6007 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6008 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6009 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6010 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6011 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
6012 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
6013 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
6014 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
6015 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
6016 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
6017 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
6018 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);