1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/kvm_host.h>
26 #include "kvm_cache_regs.h"
27 #include "kvm_emulate.h"
36 #include <linux/clocksource.h>
37 #include <linux/interrupt.h>
38 #include <linux/kvm.h>
40 #include <linux/vmalloc.h>
41 #include <linux/export.h>
42 #include <linux/moduleparam.h>
43 #include <linux/mman.h>
44 #include <linux/highmem.h>
45 #include <linux/iommu.h>
46 #include <linux/cpufreq.h>
47 #include <linux/user-return-notifier.h>
48 #include <linux/srcu.h>
49 #include <linux/slab.h>
50 #include <linux/perf_event.h>
51 #include <linux/uaccess.h>
52 #include <linux/hash.h>
53 #include <linux/pci.h>
54 #include <linux/timekeeper_internal.h>
55 #include <linux/pvclock_gtod.h>
56 #include <linux/kvm_irqfd.h>
57 #include <linux/irqbypass.h>
58 #include <linux/sched/stat.h>
59 #include <linux/sched/isolation.h>
60 #include <linux/mem_encrypt.h>
61 #include <linux/entry-kvm.h>
62 #include <linux/suspend.h>
64 #include <trace/events/kvm.h>
66 #include <asm/debugreg.h>
71 #include <linux/kernel_stat.h>
72 #include <asm/fpu/api.h>
73 #include <asm/fpu/xcr.h>
74 #include <asm/fpu/xstate.h>
75 #include <asm/pvclock.h>
76 #include <asm/div64.h>
77 #include <asm/irq_remapping.h>
78 #include <asm/mshyperv.h>
79 #include <asm/hypervisor.h>
80 #include <asm/tlbflush.h>
81 #include <asm/intel_pt.h>
82 #include <asm/emulate_prefix.h>
84 #include <clocksource/hyperv_timer.h>
86 #define CREATE_TRACE_POINTS
89 #define MAX_IO_MSRS 256
90 #define KVM_MAX_MCE_BANKS 32
92 struct kvm_caps kvm_caps __read_mostly = {
93 .supported_mce_cap = MCG_CTL_P | MCG_SER_P,
95 EXPORT_SYMBOL_GPL(kvm_caps);
97 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
99 #define emul_to_vcpu(ctxt) \
100 ((struct kvm_vcpu *)(ctxt)->vcpu)
103 * - enable syscall per default because its emulated by KVM
104 * - enable LME and LMA per default on 64 bit KVM
108 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
110 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
113 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
115 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
117 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
119 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
120 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
122 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
123 static void process_nmi(struct kvm_vcpu *vcpu);
124 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
125 static void store_regs(struct kvm_vcpu *vcpu);
126 static int sync_regs(struct kvm_vcpu *vcpu);
127 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
129 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
130 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
132 static DEFINE_MUTEX(vendor_module_lock);
133 struct kvm_x86_ops kvm_x86_ops __read_mostly;
135 #define KVM_X86_OP(func) \
136 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
137 *(((struct kvm_x86_ops *)0)->func));
138 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
139 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
140 #include <asm/kvm-x86-ops.h>
141 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
142 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
144 static bool __read_mostly ignore_msrs = 0;
145 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
147 bool __read_mostly report_ignored_msrs = true;
148 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
149 EXPORT_SYMBOL_GPL(report_ignored_msrs);
151 unsigned int min_timer_period_us = 200;
152 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
154 static bool __read_mostly kvmclock_periodic_sync = true;
155 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
157 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
158 static u32 __read_mostly tsc_tolerance_ppm = 250;
159 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
162 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
163 * adaptive tuning starting from default advancement of 1000ns. '0' disables
164 * advancement entirely. Any other value is used as-is and disables adaptive
165 * tuning, i.e. allows privileged userspace to set an exact advancement time.
167 static int __read_mostly lapic_timer_advance_ns = -1;
168 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
170 static bool __read_mostly vector_hashing = true;
171 module_param(vector_hashing, bool, S_IRUGO);
173 bool __read_mostly enable_vmware_backdoor = false;
174 module_param(enable_vmware_backdoor, bool, S_IRUGO);
175 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
178 * Flags to manipulate forced emulation behavior (any non-zero value will
179 * enable forced emulation).
181 #define KVM_FEP_CLEAR_RFLAGS_RF BIT(1)
182 static int __read_mostly force_emulation_prefix;
183 module_param(force_emulation_prefix, int, 0644);
185 int __read_mostly pi_inject_timer = -1;
186 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
188 /* Enable/disable PMU virtualization */
189 bool __read_mostly enable_pmu = true;
190 EXPORT_SYMBOL_GPL(enable_pmu);
191 module_param(enable_pmu, bool, 0444);
193 bool __read_mostly eager_page_split = true;
194 module_param(eager_page_split, bool, 0644);
196 /* Enable/disable SMT_RSB bug mitigation */
197 bool __read_mostly mitigate_smt_rsb;
198 module_param(mitigate_smt_rsb, bool, 0444);
201 * Restoring the host value for MSRs that are only consumed when running in
202 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
203 * returns to userspace, i.e. the kernel can run with the guest's value.
205 #define KVM_MAX_NR_USER_RETURN_MSRS 16
207 struct kvm_user_return_msrs {
208 struct user_return_notifier urn;
210 struct kvm_user_return_msr_values {
213 } values[KVM_MAX_NR_USER_RETURN_MSRS];
216 u32 __read_mostly kvm_nr_uret_msrs;
217 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
218 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
219 static struct kvm_user_return_msrs __percpu *user_return_msrs;
221 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
222 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
223 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
224 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
226 u64 __read_mostly host_efer;
227 EXPORT_SYMBOL_GPL(host_efer);
229 bool __read_mostly allow_smaller_maxphyaddr = 0;
230 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
232 bool __read_mostly enable_apicv = true;
233 EXPORT_SYMBOL_GPL(enable_apicv);
235 u64 __read_mostly host_xss;
236 EXPORT_SYMBOL_GPL(host_xss);
238 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
239 KVM_GENERIC_VM_STATS(),
240 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
241 STATS_DESC_COUNTER(VM, mmu_pte_write),
242 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
243 STATS_DESC_COUNTER(VM, mmu_flooded),
244 STATS_DESC_COUNTER(VM, mmu_recycled),
245 STATS_DESC_COUNTER(VM, mmu_cache_miss),
246 STATS_DESC_ICOUNTER(VM, mmu_unsync),
247 STATS_DESC_ICOUNTER(VM, pages_4k),
248 STATS_DESC_ICOUNTER(VM, pages_2m),
249 STATS_DESC_ICOUNTER(VM, pages_1g),
250 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
251 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
252 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
255 const struct kvm_stats_header kvm_vm_stats_header = {
256 .name_size = KVM_STATS_NAME_SIZE,
257 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
258 .id_offset = sizeof(struct kvm_stats_header),
259 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
260 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
261 sizeof(kvm_vm_stats_desc),
264 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
265 KVM_GENERIC_VCPU_STATS(),
266 STATS_DESC_COUNTER(VCPU, pf_taken),
267 STATS_DESC_COUNTER(VCPU, pf_fixed),
268 STATS_DESC_COUNTER(VCPU, pf_emulate),
269 STATS_DESC_COUNTER(VCPU, pf_spurious),
270 STATS_DESC_COUNTER(VCPU, pf_fast),
271 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created),
272 STATS_DESC_COUNTER(VCPU, pf_guest),
273 STATS_DESC_COUNTER(VCPU, tlb_flush),
274 STATS_DESC_COUNTER(VCPU, invlpg),
275 STATS_DESC_COUNTER(VCPU, exits),
276 STATS_DESC_COUNTER(VCPU, io_exits),
277 STATS_DESC_COUNTER(VCPU, mmio_exits),
278 STATS_DESC_COUNTER(VCPU, signal_exits),
279 STATS_DESC_COUNTER(VCPU, irq_window_exits),
280 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
281 STATS_DESC_COUNTER(VCPU, l1d_flush),
282 STATS_DESC_COUNTER(VCPU, halt_exits),
283 STATS_DESC_COUNTER(VCPU, request_irq_exits),
284 STATS_DESC_COUNTER(VCPU, irq_exits),
285 STATS_DESC_COUNTER(VCPU, host_state_reload),
286 STATS_DESC_COUNTER(VCPU, fpu_reload),
287 STATS_DESC_COUNTER(VCPU, insn_emulation),
288 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
289 STATS_DESC_COUNTER(VCPU, hypercalls),
290 STATS_DESC_COUNTER(VCPU, irq_injections),
291 STATS_DESC_COUNTER(VCPU, nmi_injections),
292 STATS_DESC_COUNTER(VCPU, req_event),
293 STATS_DESC_COUNTER(VCPU, nested_run),
294 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
295 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
296 STATS_DESC_COUNTER(VCPU, preemption_reported),
297 STATS_DESC_COUNTER(VCPU, preemption_other),
298 STATS_DESC_IBOOLEAN(VCPU, guest_mode),
299 STATS_DESC_COUNTER(VCPU, notify_window_exits),
302 const struct kvm_stats_header kvm_vcpu_stats_header = {
303 .name_size = KVM_STATS_NAME_SIZE,
304 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
305 .id_offset = sizeof(struct kvm_stats_header),
306 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
307 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
308 sizeof(kvm_vcpu_stats_desc),
311 u64 __read_mostly host_xcr0;
313 static struct kmem_cache *x86_emulator_cache;
316 * When called, it means the previous get/set msr reached an invalid msr.
317 * Return true if we want to ignore/silent this failed msr access.
319 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
321 const char *op = write ? "wrmsr" : "rdmsr";
324 if (report_ignored_msrs)
325 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
330 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
336 static struct kmem_cache *kvm_alloc_emulator_cache(void)
338 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
339 unsigned int size = sizeof(struct x86_emulate_ctxt);
341 return kmem_cache_create_usercopy("x86_emulator", size,
342 __alignof__(struct x86_emulate_ctxt),
343 SLAB_ACCOUNT, useroffset,
344 size - useroffset, NULL);
347 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
349 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
352 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
353 vcpu->arch.apf.gfns[i] = ~0;
356 static void kvm_on_user_return(struct user_return_notifier *urn)
359 struct kvm_user_return_msrs *msrs
360 = container_of(urn, struct kvm_user_return_msrs, urn);
361 struct kvm_user_return_msr_values *values;
365 * Disabling irqs at this point since the following code could be
366 * interrupted and executed through kvm_arch_hardware_disable()
368 local_irq_save(flags);
369 if (msrs->registered) {
370 msrs->registered = false;
371 user_return_notifier_unregister(urn);
373 local_irq_restore(flags);
374 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
375 values = &msrs->values[slot];
376 if (values->host != values->curr) {
377 wrmsrl(kvm_uret_msrs_list[slot], values->host);
378 values->curr = values->host;
383 static int kvm_probe_user_return_msr(u32 msr)
389 ret = rdmsrl_safe(msr, &val);
392 ret = wrmsrl_safe(msr, val);
398 int kvm_add_user_return_msr(u32 msr)
400 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
402 if (kvm_probe_user_return_msr(msr))
405 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
406 return kvm_nr_uret_msrs++;
408 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
410 int kvm_find_user_return_msr(u32 msr)
414 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
415 if (kvm_uret_msrs_list[i] == msr)
420 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
422 static void kvm_user_return_msr_cpu_online(void)
424 unsigned int cpu = smp_processor_id();
425 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
429 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
430 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
431 msrs->values[i].host = value;
432 msrs->values[i].curr = value;
436 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
438 unsigned int cpu = smp_processor_id();
439 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
442 value = (value & mask) | (msrs->values[slot].host & ~mask);
443 if (value == msrs->values[slot].curr)
445 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
449 msrs->values[slot].curr = value;
450 if (!msrs->registered) {
451 msrs->urn.on_user_return = kvm_on_user_return;
452 user_return_notifier_register(&msrs->urn);
453 msrs->registered = true;
457 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
459 static void drop_user_return_notifiers(void)
461 unsigned int cpu = smp_processor_id();
462 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
464 if (msrs->registered)
465 kvm_on_user_return(&msrs->urn);
468 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
470 return vcpu->arch.apic_base;
473 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
475 return kvm_apic_mode(kvm_get_apic_base(vcpu));
477 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
479 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
481 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
482 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
483 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
484 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
486 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
488 if (!msr_info->host_initiated) {
489 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
491 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
495 kvm_lapic_set_base(vcpu, msr_info->data);
496 kvm_recalculate_apic_map(vcpu->kvm);
501 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
503 * Hardware virtualization extension instructions may fault if a reboot turns
504 * off virtualization while processes are running. Usually after catching the
505 * fault we just panic; during reboot instead the instruction is ignored.
507 noinstr void kvm_spurious_fault(void)
509 /* Fault while not rebooting. We want the trace. */
510 BUG_ON(!kvm_rebooting);
512 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
514 #define EXCPT_BENIGN 0
515 #define EXCPT_CONTRIBUTORY 1
518 static int exception_class(int vector)
528 return EXCPT_CONTRIBUTORY;
535 #define EXCPT_FAULT 0
537 #define EXCPT_ABORT 2
538 #define EXCPT_INTERRUPT 3
541 static int exception_type(int vector)
545 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
546 return EXCPT_INTERRUPT;
551 * #DBs can be trap-like or fault-like, the caller must check other CPU
552 * state, e.g. DR6, to determine whether a #DB is a trap or fault.
554 if (mask & (1 << DB_VECTOR))
557 if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR)))
560 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
563 /* Reserved exceptions will result in fault */
567 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
568 struct kvm_queued_exception *ex)
570 if (!ex->has_payload)
573 switch (ex->vector) {
576 * "Certain debug exceptions may clear bit 0-3. The
577 * remaining contents of the DR6 register are never
578 * cleared by the processor".
580 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
582 * In order to reflect the #DB exception payload in guest
583 * dr6, three components need to be considered: active low
584 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
586 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
587 * In the target guest dr6:
588 * FIXED_1 bits should always be set.
589 * Active low bits should be cleared if 1-setting in payload.
590 * Active high bits should be set if 1-setting in payload.
592 * Note, the payload is compatible with the pending debug
593 * exceptions/exit qualification under VMX, that active_low bits
594 * are active high in payload.
595 * So they need to be flipped for DR6.
597 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
598 vcpu->arch.dr6 |= ex->payload;
599 vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW;
602 * The #DB payload is defined as compatible with the 'pending
603 * debug exceptions' field under VMX, not DR6. While bit 12 is
604 * defined in the 'pending debug exceptions' field (enabled
605 * breakpoint), it is reserved and must be zero in DR6.
607 vcpu->arch.dr6 &= ~BIT(12);
610 vcpu->arch.cr2 = ex->payload;
614 ex->has_payload = false;
617 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
619 static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector,
620 bool has_error_code, u32 error_code,
621 bool has_payload, unsigned long payload)
623 struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit;
626 ex->injected = false;
628 ex->has_error_code = has_error_code;
629 ex->error_code = error_code;
630 ex->has_payload = has_payload;
631 ex->payload = payload;
634 /* Forcibly leave the nested mode in cases like a vCPU reset */
635 static void kvm_leave_nested(struct kvm_vcpu *vcpu)
637 kvm_x86_ops.nested_ops->leave_nested(vcpu);
640 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
641 unsigned nr, bool has_error, u32 error_code,
642 bool has_payload, unsigned long payload, bool reinject)
647 kvm_make_request(KVM_REQ_EVENT, vcpu);
650 * If the exception is destined for L2 and isn't being reinjected,
651 * morph it to a VM-Exit if L1 wants to intercept the exception. A
652 * previously injected exception is not checked because it was checked
653 * when it was original queued, and re-checking is incorrect if _L1_
654 * injected the exception, in which case it's exempt from interception.
656 if (!reinject && is_guest_mode(vcpu) &&
657 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) {
658 kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code,
659 has_payload, payload);
663 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
667 * On VM-Entry, an exception can be pending if and only
668 * if event injection was blocked by nested_run_pending.
669 * In that case, however, vcpu_enter_guest() requests an
670 * immediate exit, and the guest shouldn't proceed far
671 * enough to need reinjection.
673 WARN_ON_ONCE(kvm_is_exception_pending(vcpu));
674 vcpu->arch.exception.injected = true;
675 if (WARN_ON_ONCE(has_payload)) {
677 * A reinjected event has already
678 * delivered its payload.
684 vcpu->arch.exception.pending = true;
685 vcpu->arch.exception.injected = false;
687 vcpu->arch.exception.has_error_code = has_error;
688 vcpu->arch.exception.vector = nr;
689 vcpu->arch.exception.error_code = error_code;
690 vcpu->arch.exception.has_payload = has_payload;
691 vcpu->arch.exception.payload = payload;
692 if (!is_guest_mode(vcpu))
693 kvm_deliver_exception_payload(vcpu,
694 &vcpu->arch.exception);
698 /* to check exception */
699 prev_nr = vcpu->arch.exception.vector;
700 if (prev_nr == DF_VECTOR) {
701 /* triple fault -> shutdown */
702 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
705 class1 = exception_class(prev_nr);
706 class2 = exception_class(nr);
707 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) ||
708 (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
710 * Synthesize #DF. Clear the previously injected or pending
711 * exception so as not to incorrectly trigger shutdown.
713 vcpu->arch.exception.injected = false;
714 vcpu->arch.exception.pending = false;
716 kvm_queue_exception_e(vcpu, DF_VECTOR, 0);
718 /* replace previous exception with a new one in a hope
719 that instruction re-execution will regenerate lost
725 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
727 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
729 EXPORT_SYMBOL_GPL(kvm_queue_exception);
731 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
733 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
735 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
737 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
738 unsigned long payload)
740 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
742 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
744 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
745 u32 error_code, unsigned long payload)
747 kvm_multiple_exception(vcpu, nr, true, error_code,
748 true, payload, false);
751 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
754 kvm_inject_gp(vcpu, 0);
756 return kvm_skip_emulated_instruction(vcpu);
760 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
762 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
765 kvm_inject_gp(vcpu, 0);
769 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
770 EMULTYPE_COMPLETE_USER_EXIT);
773 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
775 ++vcpu->stat.pf_guest;
778 * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of
779 * whether or not L1 wants to intercept "regular" #PF.
781 if (is_guest_mode(vcpu) && fault->async_page_fault)
782 kvm_queue_exception_vmexit(vcpu, PF_VECTOR,
783 true, fault->error_code,
784 true, fault->address);
786 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
790 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
791 struct x86_exception *fault)
793 struct kvm_mmu *fault_mmu;
794 WARN_ON_ONCE(fault->vector != PF_VECTOR);
796 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
800 * Invalidate the TLB entry for the faulting address, if it exists,
801 * else the access will fault indefinitely (and to emulate hardware).
803 if ((fault->error_code & PFERR_PRESENT_MASK) &&
804 !(fault->error_code & PFERR_RSVD_MASK))
805 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
806 fault_mmu->root.hpa);
808 fault_mmu->inject_page_fault(vcpu, fault);
810 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
812 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
814 atomic_inc(&vcpu->arch.nmi_queued);
815 kvm_make_request(KVM_REQ_NMI, vcpu);
818 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
820 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
822 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
824 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
826 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
828 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
831 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
832 * a #GP and return false.
834 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
836 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
838 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
842 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
844 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
847 kvm_queue_exception(vcpu, UD_VECTOR);
850 EXPORT_SYMBOL_GPL(kvm_require_dr);
852 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
854 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
858 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
860 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
862 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
863 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
867 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
870 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
873 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
874 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
875 if (real_gpa == INVALID_GPA)
878 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
879 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
880 cr3 & GENMASK(11, 5), sizeof(pdpte));
884 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
885 if ((pdpte[i] & PT_PRESENT_MASK) &&
886 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
892 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
893 * Shadow page roots need to be reconstructed instead.
895 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
896 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
898 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
899 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
900 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
901 vcpu->arch.pdptrs_from_userspace = false;
905 EXPORT_SYMBOL_GPL(load_pdptrs);
907 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
909 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
910 kvm_clear_async_pf_completion_queue(vcpu);
911 kvm_async_pf_hash_reset(vcpu);
914 * Clearing CR0.PG is defined to flush the TLB from the guest's
917 if (!(cr0 & X86_CR0_PG))
918 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
921 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
922 kvm_mmu_reset_context(vcpu);
924 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
925 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
926 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
927 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
929 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
931 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
933 unsigned long old_cr0 = kvm_read_cr0(vcpu);
938 if (cr0 & 0xffffffff00000000UL)
942 cr0 &= ~CR0_RESERVED_BITS;
944 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
947 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
951 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
952 (cr0 & X86_CR0_PG)) {
957 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
962 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
963 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
964 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
967 if (!(cr0 & X86_CR0_PG) &&
968 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)))
971 static_call(kvm_x86_set_cr0)(vcpu, cr0);
973 kvm_post_set_cr0(vcpu, old_cr0, cr0);
977 EXPORT_SYMBOL_GPL(kvm_set_cr0);
979 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
981 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
983 EXPORT_SYMBOL_GPL(kvm_lmsw);
985 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
987 if (vcpu->arch.guest_state_protected)
990 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
992 if (vcpu->arch.xcr0 != host_xcr0)
993 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
995 if (vcpu->arch.xsaves_enabled &&
996 vcpu->arch.ia32_xss != host_xss)
997 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
1000 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
1001 if (static_cpu_has(X86_FEATURE_PKU) &&
1002 vcpu->arch.pkru != vcpu->arch.host_pkru &&
1003 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1004 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)))
1005 write_pkru(vcpu->arch.pkru);
1006 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
1008 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
1010 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
1012 if (vcpu->arch.guest_state_protected)
1015 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
1016 if (static_cpu_has(X86_FEATURE_PKU) &&
1017 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1018 kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) {
1019 vcpu->arch.pkru = rdpkru();
1020 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
1021 write_pkru(vcpu->arch.host_pkru);
1023 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
1025 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
1027 if (vcpu->arch.xcr0 != host_xcr0)
1028 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
1030 if (vcpu->arch.xsaves_enabled &&
1031 vcpu->arch.ia32_xss != host_xss)
1032 wrmsrl(MSR_IA32_XSS, host_xss);
1036 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
1038 #ifdef CONFIG_X86_64
1039 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1041 return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC;
1045 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1048 u64 old_xcr0 = vcpu->arch.xcr0;
1051 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1052 if (index != XCR_XFEATURE_ENABLED_MASK)
1054 if (!(xcr0 & XFEATURE_MASK_FP))
1056 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1060 * Do not allow the guest to set bits that we do not support
1061 * saving. However, xcr0 bit 0 is always set, even if the
1062 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1064 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
1065 if (xcr0 & ~valid_bits)
1068 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1069 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1072 if (xcr0 & XFEATURE_MASK_AVX512) {
1073 if (!(xcr0 & XFEATURE_MASK_YMM))
1075 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1079 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1080 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1083 vcpu->arch.xcr0 = xcr0;
1085 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1086 kvm_update_cpuid_runtime(vcpu);
1090 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1092 /* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
1093 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1094 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1095 kvm_inject_gp(vcpu, 0);
1099 return kvm_skip_emulated_instruction(vcpu);
1101 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1103 bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1105 if (cr4 & cr4_reserved_bits)
1108 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1113 EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4);
1115 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1117 return __kvm_is_valid_cr4(vcpu, cr4) &&
1118 static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1121 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1123 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1124 kvm_mmu_reset_context(vcpu);
1127 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1128 * according to the SDM; however, stale prev_roots could be reused
1129 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1130 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1131 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1135 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1136 kvm_mmu_unload(vcpu);
1139 * The TLB has to be flushed for all PCIDs if any of the following
1140 * (architecturally required) changes happen:
1141 * - CR4.PCIDE is changed from 1 to 0
1142 * - CR4.PGE is toggled
1144 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1146 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1147 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1148 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1151 * The TLB has to be flushed for the current PCID if any of the
1152 * following (architecturally required) changes happen:
1153 * - CR4.SMEP is changed from 0 to 1
1154 * - CR4.PAE is toggled
1156 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1157 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1158 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1161 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1163 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1165 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1167 if (!kvm_is_valid_cr4(vcpu, cr4))
1170 if (is_long_mode(vcpu)) {
1171 if (!(cr4 & X86_CR4_PAE))
1173 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1175 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1176 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1177 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1180 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1181 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1184 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1185 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1189 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1191 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1195 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1197 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1199 struct kvm_mmu *mmu = vcpu->arch.mmu;
1200 unsigned long roots_to_free = 0;
1204 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1205 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1206 * also via the emulator. KVM's TDP page tables are not in the scope of
1207 * the invalidation, but the guest's TLB entries need to be flushed as
1208 * the CPU may have cached entries in its TLB for the target PCID.
1210 if (unlikely(tdp_enabled)) {
1211 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1216 * If neither the current CR3 nor any of the prev_roots use the given
1217 * PCID, then nothing needs to be done here because a resync will
1218 * happen anyway before switching to any other CR3.
1220 if (kvm_get_active_pcid(vcpu) == pcid) {
1221 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1222 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1226 * If PCID is disabled, there is no need to free prev_roots even if the
1227 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1230 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
1233 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1234 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1235 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1237 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1240 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1242 bool skip_tlb_flush = false;
1243 unsigned long pcid = 0;
1244 #ifdef CONFIG_X86_64
1245 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1248 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1249 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1250 pcid = cr3 & X86_CR3_PCID_MASK;
1254 /* PDPTRs are always reloaded for PAE paging. */
1255 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1256 goto handle_tlb_flush;
1259 * Do not condition the GPA check on long mode, this helper is used to
1260 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1261 * the current vCPU mode is accurate.
1263 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1266 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1269 if (cr3 != kvm_read_cr3(vcpu))
1270 kvm_mmu_new_pgd(vcpu, cr3);
1272 vcpu->arch.cr3 = cr3;
1273 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1274 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1278 * A load of CR3 that flushes the TLB flushes only the current PCID,
1279 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1280 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1281 * and it's impossible to use a non-zero PCID when PCID is disabled,
1282 * i.e. only PCID=0 can be relevant.
1284 if (!skip_tlb_flush)
1285 kvm_invalidate_pcid(vcpu, pcid);
1289 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1291 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1293 if (cr8 & CR8_RESERVED_BITS)
1295 if (lapic_in_kernel(vcpu))
1296 kvm_lapic_set_tpr(vcpu, cr8);
1298 vcpu->arch.cr8 = cr8;
1301 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1303 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1305 if (lapic_in_kernel(vcpu))
1306 return kvm_lapic_get_cr8(vcpu);
1308 return vcpu->arch.cr8;
1310 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1312 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1316 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1317 for (i = 0; i < KVM_NR_DB_REGS; i++)
1318 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1322 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1326 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1327 dr7 = vcpu->arch.guest_debug_dr7;
1329 dr7 = vcpu->arch.dr7;
1330 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1331 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1332 if (dr7 & DR7_BP_EN_MASK)
1333 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1335 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1337 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1339 u64 fixed = DR6_FIXED_1;
1341 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1344 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1345 fixed |= DR6_BUS_LOCK;
1349 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1351 size_t size = ARRAY_SIZE(vcpu->arch.db);
1355 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1356 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1357 vcpu->arch.eff_db[dr] = val;
1361 if (!kvm_dr6_valid(val))
1363 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1367 if (!kvm_dr7_valid(val))
1369 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1370 kvm_update_dr7(vcpu);
1376 EXPORT_SYMBOL_GPL(kvm_set_dr);
1378 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1380 size_t size = ARRAY_SIZE(vcpu->arch.db);
1384 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1388 *val = vcpu->arch.dr6;
1392 *val = vcpu->arch.dr7;
1396 EXPORT_SYMBOL_GPL(kvm_get_dr);
1398 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1400 u32 ecx = kvm_rcx_read(vcpu);
1403 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1404 kvm_inject_gp(vcpu, 0);
1408 kvm_rax_write(vcpu, (u32)data);
1409 kvm_rdx_write(vcpu, data >> 32);
1410 return kvm_skip_emulated_instruction(vcpu);
1412 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1415 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1416 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1418 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1419 * extract the supported MSRs from the related const lists.
1420 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1421 * capabilities of the host cpu. This capabilities test skips MSRs that are
1422 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1423 * may depend on host virtualization features rather than host cpu features.
1426 static const u32 msrs_to_save_base[] = {
1427 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1429 #ifdef CONFIG_X86_64
1430 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1432 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1433 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1435 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1436 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1437 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1438 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1439 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1440 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1441 MSR_IA32_UMWAIT_CONTROL,
1443 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1446 static const u32 msrs_to_save_pmu[] = {
1447 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1448 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1449 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1450 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1451 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
1453 /* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */
1454 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1455 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1456 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1457 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1458 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1459 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1460 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1461 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1463 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1464 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1466 /* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */
1467 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1468 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1469 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1470 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1473 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) +
1474 ARRAY_SIZE(msrs_to_save_pmu)];
1475 static unsigned num_msrs_to_save;
1477 static const u32 emulated_msrs_all[] = {
1478 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1479 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1480 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1481 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1482 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1483 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1484 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1486 HV_X64_MSR_VP_INDEX,
1487 HV_X64_MSR_VP_RUNTIME,
1488 HV_X64_MSR_SCONTROL,
1489 HV_X64_MSR_STIMER0_CONFIG,
1490 HV_X64_MSR_VP_ASSIST_PAGE,
1491 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1492 HV_X64_MSR_TSC_EMULATION_STATUS, HV_X64_MSR_TSC_INVARIANT_CONTROL,
1493 HV_X64_MSR_SYNDBG_OPTIONS,
1494 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1495 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1496 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1498 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1499 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1501 MSR_IA32_TSC_ADJUST,
1502 MSR_IA32_TSC_DEADLINE,
1503 MSR_IA32_ARCH_CAPABILITIES,
1504 MSR_IA32_PERF_CAPABILITIES,
1505 MSR_IA32_MISC_ENABLE,
1506 MSR_IA32_MCG_STATUS,
1508 MSR_IA32_MCG_EXT_CTL,
1512 MSR_MISC_FEATURES_ENABLES,
1513 MSR_AMD64_VIRT_SPEC_CTRL,
1514 MSR_AMD64_TSC_RATIO,
1519 * The following list leaves out MSRs whose values are determined
1520 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1521 * We always support the "true" VMX control MSRs, even if the host
1522 * processor does not, so I am putting these registers here rather
1523 * than in msrs_to_save_all.
1526 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1527 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1528 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1529 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1531 MSR_IA32_VMX_CR0_FIXED0,
1532 MSR_IA32_VMX_CR4_FIXED0,
1533 MSR_IA32_VMX_VMCS_ENUM,
1534 MSR_IA32_VMX_PROCBASED_CTLS2,
1535 MSR_IA32_VMX_EPT_VPID_CAP,
1536 MSR_IA32_VMX_VMFUNC,
1539 MSR_KVM_POLL_CONTROL,
1542 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1543 static unsigned num_emulated_msrs;
1546 * List of msr numbers which are used to expose MSR-based features that
1547 * can be used by a hypervisor to validate requested CPU features.
1549 static const u32 msr_based_features_all[] = {
1551 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1552 MSR_IA32_VMX_PINBASED_CTLS,
1553 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1554 MSR_IA32_VMX_PROCBASED_CTLS,
1555 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1556 MSR_IA32_VMX_EXIT_CTLS,
1557 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1558 MSR_IA32_VMX_ENTRY_CTLS,
1560 MSR_IA32_VMX_CR0_FIXED0,
1561 MSR_IA32_VMX_CR0_FIXED1,
1562 MSR_IA32_VMX_CR4_FIXED0,
1563 MSR_IA32_VMX_CR4_FIXED1,
1564 MSR_IA32_VMX_VMCS_ENUM,
1565 MSR_IA32_VMX_PROCBASED_CTLS2,
1566 MSR_IA32_VMX_EPT_VPID_CAP,
1567 MSR_IA32_VMX_VMFUNC,
1571 MSR_IA32_ARCH_CAPABILITIES,
1572 MSR_IA32_PERF_CAPABILITIES,
1575 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1576 static unsigned int num_msr_based_features;
1579 * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM
1580 * does not yet virtualize. These include:
1581 * 10 - MISC_PACKAGE_CTRLS
1582 * 11 - ENERGY_FILTERING_CTL
1584 * 18 - FB_CLEAR_CTRL
1585 * 21 - XAPIC_DISABLE_STATUS
1586 * 23 - OVERCLOCKING_STATUS
1589 #define KVM_SUPPORTED_ARCH_CAP \
1590 (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \
1591 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \
1592 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \
1593 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \
1594 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO)
1596 static u64 kvm_get_arch_capabilities(void)
1600 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
1601 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1602 data &= KVM_SUPPORTED_ARCH_CAP;
1606 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1607 * the nested hypervisor runs with NX huge pages. If it is not,
1608 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1609 * L1 guests, so it need not worry about its own (L2) guests.
1611 data |= ARCH_CAP_PSCHANGE_MC_NO;
1614 * If we're doing cache flushes (either "always" or "cond")
1615 * we will do one whenever the guest does a vmlaunch/vmresume.
1616 * If an outer hypervisor is doing the cache flush for us
1617 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1618 * capability to the guest too, and if EPT is disabled we're not
1619 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1620 * require a nested hypervisor to do a flush of its own.
1622 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1623 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1625 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1626 data |= ARCH_CAP_RDCL_NO;
1627 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1628 data |= ARCH_CAP_SSB_NO;
1629 if (!boot_cpu_has_bug(X86_BUG_MDS))
1630 data |= ARCH_CAP_MDS_NO;
1632 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1634 * If RTM=0 because the kernel has disabled TSX, the host might
1635 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1636 * and therefore knows that there cannot be TAA) but keep
1637 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1638 * and we want to allow migrating those guests to tsx=off hosts.
1640 data &= ~ARCH_CAP_TAA_NO;
1641 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1642 data |= ARCH_CAP_TAA_NO;
1645 * Nothing to do here; we emulate TSX_CTRL if present on the
1646 * host so the guest can choose between disabling TSX or
1647 * using VERW to clear CPU buffers.
1654 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1656 switch (msr->index) {
1657 case MSR_IA32_ARCH_CAPABILITIES:
1658 msr->data = kvm_get_arch_capabilities();
1660 case MSR_IA32_PERF_CAPABILITIES:
1661 msr->data = kvm_caps.supported_perf_cap;
1663 case MSR_IA32_UCODE_REV:
1664 rdmsrl_safe(msr->index, &msr->data);
1667 return static_call(kvm_x86_get_msr_feature)(msr);
1672 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1674 struct kvm_msr_entry msr;
1678 r = kvm_get_msr_feature(&msr);
1680 if (r == KVM_MSR_RET_INVALID) {
1681 /* Unconditionally clear the output for simplicity */
1683 if (kvm_msr_ignored_check(index, 0, false))
1695 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1697 if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS))
1700 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1703 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1706 if (efer & (EFER_LME | EFER_LMA) &&
1707 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1710 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1716 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1718 if (efer & efer_reserved_bits)
1721 return __kvm_valid_efer(vcpu, efer);
1723 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1725 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1727 u64 old_efer = vcpu->arch.efer;
1728 u64 efer = msr_info->data;
1731 if (efer & efer_reserved_bits)
1734 if (!msr_info->host_initiated) {
1735 if (!__kvm_valid_efer(vcpu, efer))
1738 if (is_paging(vcpu) &&
1739 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1744 efer |= vcpu->arch.efer & EFER_LMA;
1746 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1752 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1753 kvm_mmu_reset_context(vcpu);
1758 void kvm_enable_efer_bits(u64 mask)
1760 efer_reserved_bits &= ~mask;
1762 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1764 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1766 struct kvm_x86_msr_filter *msr_filter;
1767 struct msr_bitmap_range *ranges;
1768 struct kvm *kvm = vcpu->kvm;
1773 /* x2APIC MSRs do not support filtering. */
1774 if (index >= 0x800 && index <= 0x8ff)
1777 idx = srcu_read_lock(&kvm->srcu);
1779 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1785 allowed = msr_filter->default_allow;
1786 ranges = msr_filter->ranges;
1788 for (i = 0; i < msr_filter->count; i++) {
1789 u32 start = ranges[i].base;
1790 u32 end = start + ranges[i].nmsrs;
1791 u32 flags = ranges[i].flags;
1792 unsigned long *bitmap = ranges[i].bitmap;
1794 if ((index >= start) && (index < end) && (flags & type)) {
1795 allowed = !!test_bit(index - start, bitmap);
1801 srcu_read_unlock(&kvm->srcu, idx);
1805 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1808 * Write @data into the MSR specified by @index. Select MSR specific fault
1809 * checks are bypassed if @host_initiated is %true.
1810 * Returns 0 on success, non-0 otherwise.
1811 * Assumes vcpu_load() was already called.
1813 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1814 bool host_initiated)
1816 struct msr_data msr;
1821 case MSR_KERNEL_GS_BASE:
1824 if (is_noncanonical_address(data, vcpu))
1827 case MSR_IA32_SYSENTER_EIP:
1828 case MSR_IA32_SYSENTER_ESP:
1830 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1831 * non-canonical address is written on Intel but not on
1832 * AMD (which ignores the top 32-bits, because it does
1833 * not implement 64-bit SYSENTER).
1835 * 64-bit code should hence be able to write a non-canonical
1836 * value on AMD. Making the address canonical ensures that
1837 * vmentry does not fail on Intel after writing a non-canonical
1838 * value, and that something deterministic happens if the guest
1839 * invokes 64-bit SYSENTER.
1841 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1844 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1847 if (!host_initiated &&
1848 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1849 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1853 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1854 * incomplete and conflicting architectural behavior. Current
1855 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1856 * reserved and always read as zeros. Enforce Intel's reserved
1857 * bits check if and only if the guest CPU is Intel, and clear
1858 * the bits in all other cases. This ensures cross-vendor
1859 * migration will provide consistent behavior for the guest.
1861 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1870 msr.host_initiated = host_initiated;
1872 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1875 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1876 u32 index, u64 data, bool host_initiated)
1878 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1880 if (ret == KVM_MSR_RET_INVALID)
1881 if (kvm_msr_ignored_check(index, data, true))
1888 * Read the MSR specified by @index into @data. Select MSR specific fault
1889 * checks are bypassed if @host_initiated is %true.
1890 * Returns 0 on success, non-0 otherwise.
1891 * Assumes vcpu_load() was already called.
1893 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1894 bool host_initiated)
1896 struct msr_data msr;
1901 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1904 if (!host_initiated &&
1905 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1906 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1912 msr.host_initiated = host_initiated;
1914 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1920 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1921 u32 index, u64 *data, bool host_initiated)
1923 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1925 if (ret == KVM_MSR_RET_INVALID) {
1926 /* Unconditionally clear *data for simplicity */
1928 if (kvm_msr_ignored_check(index, 0, false))
1935 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1937 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1938 return KVM_MSR_RET_FILTERED;
1939 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1942 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1944 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1945 return KVM_MSR_RET_FILTERED;
1946 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1949 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1951 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1953 EXPORT_SYMBOL_GPL(kvm_get_msr);
1955 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1957 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1959 EXPORT_SYMBOL_GPL(kvm_set_msr);
1961 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1963 if (!vcpu->run->msr.error) {
1964 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1965 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1969 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
1971 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
1974 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1976 complete_userspace_rdmsr(vcpu);
1977 return complete_emulated_msr_access(vcpu);
1980 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
1982 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
1985 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
1987 complete_userspace_rdmsr(vcpu);
1988 return complete_fast_msr_access(vcpu);
1991 static u64 kvm_msr_reason(int r)
1994 case KVM_MSR_RET_INVALID:
1995 return KVM_MSR_EXIT_REASON_UNKNOWN;
1996 case KVM_MSR_RET_FILTERED:
1997 return KVM_MSR_EXIT_REASON_FILTER;
1999 return KVM_MSR_EXIT_REASON_INVAL;
2003 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
2004 u32 exit_reason, u64 data,
2005 int (*completion)(struct kvm_vcpu *vcpu),
2008 u64 msr_reason = kvm_msr_reason(r);
2010 /* Check if the user wanted to know about this MSR fault */
2011 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
2014 vcpu->run->exit_reason = exit_reason;
2015 vcpu->run->msr.error = 0;
2016 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
2017 vcpu->run->msr.reason = msr_reason;
2018 vcpu->run->msr.index = index;
2019 vcpu->run->msr.data = data;
2020 vcpu->arch.complete_userspace_io = completion;
2025 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
2027 u32 ecx = kvm_rcx_read(vcpu);
2031 r = kvm_get_msr_with_filter(vcpu, ecx, &data);
2034 trace_kvm_msr_read(ecx, data);
2036 kvm_rax_write(vcpu, data & -1u);
2037 kvm_rdx_write(vcpu, (data >> 32) & -1u);
2039 /* MSR read failed? See if we should ask user space */
2040 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
2041 complete_fast_rdmsr, r))
2043 trace_kvm_msr_read_ex(ecx);
2046 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2048 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
2050 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
2052 u32 ecx = kvm_rcx_read(vcpu);
2053 u64 data = kvm_read_edx_eax(vcpu);
2056 r = kvm_set_msr_with_filter(vcpu, ecx, data);
2059 trace_kvm_msr_write(ecx, data);
2061 /* MSR write failed? See if we should ask user space */
2062 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
2063 complete_fast_msr_access, r))
2065 /* Signal all other negative errors to userspace */
2068 trace_kvm_msr_write_ex(ecx, data);
2071 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2073 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2075 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2077 return kvm_skip_emulated_instruction(vcpu);
2080 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2082 /* Treat an INVD instruction as a NOP and just skip it. */
2083 return kvm_emulate_as_nop(vcpu);
2085 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2087 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2089 kvm_queue_exception(vcpu, UD_VECTOR);
2092 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2095 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn)
2097 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) &&
2098 !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT))
2099 return kvm_handle_invalid_op(vcpu);
2101 pr_warn_once("%s instruction emulated as NOP!\n", insn);
2102 return kvm_emulate_as_nop(vcpu);
2104 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2106 return kvm_emulate_monitor_mwait(vcpu, "MWAIT");
2108 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2110 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2112 return kvm_emulate_monitor_mwait(vcpu, "MONITOR");
2114 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2116 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2118 xfer_to_guest_mode_prepare();
2119 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2120 xfer_to_guest_mode_work_pending();
2124 * The fast path for frequent and performance sensitive wrmsr emulation,
2125 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2126 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2127 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2128 * other cases which must be called after interrupts are enabled on the host.
2130 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2132 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2135 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2136 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2137 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2138 ((u32)(data >> 32) != X2APIC_BROADCAST))
2139 return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2144 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2146 if (!kvm_can_use_hv_timer(vcpu))
2149 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2153 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2155 u32 msr = kvm_rcx_read(vcpu);
2157 fastpath_t ret = EXIT_FASTPATH_NONE;
2160 case APIC_BASE_MSR + (APIC_ICR >> 4):
2161 data = kvm_read_edx_eax(vcpu);
2162 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2163 kvm_skip_emulated_instruction(vcpu);
2164 ret = EXIT_FASTPATH_EXIT_HANDLED;
2167 case MSR_IA32_TSC_DEADLINE:
2168 data = kvm_read_edx_eax(vcpu);
2169 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2170 kvm_skip_emulated_instruction(vcpu);
2171 ret = EXIT_FASTPATH_REENTER_GUEST;
2178 if (ret != EXIT_FASTPATH_NONE)
2179 trace_kvm_msr_write(msr, data);
2183 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2186 * Adapt set_msr() to msr_io()'s calling convention
2188 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2190 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2193 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2195 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2198 #ifdef CONFIG_X86_64
2199 struct pvclock_clock {
2209 struct pvclock_gtod_data {
2212 struct pvclock_clock clock; /* extract of a clocksource struct */
2213 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2219 static struct pvclock_gtod_data pvclock_gtod_data;
2221 static void update_pvclock_gtod(struct timekeeper *tk)
2223 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2225 write_seqcount_begin(&vdata->seq);
2227 /* copy pvclock gtod data */
2228 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2229 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2230 vdata->clock.mask = tk->tkr_mono.mask;
2231 vdata->clock.mult = tk->tkr_mono.mult;
2232 vdata->clock.shift = tk->tkr_mono.shift;
2233 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2234 vdata->clock.offset = tk->tkr_mono.base;
2236 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2237 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2238 vdata->raw_clock.mask = tk->tkr_raw.mask;
2239 vdata->raw_clock.mult = tk->tkr_raw.mult;
2240 vdata->raw_clock.shift = tk->tkr_raw.shift;
2241 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2242 vdata->raw_clock.offset = tk->tkr_raw.base;
2244 vdata->wall_time_sec = tk->xtime_sec;
2246 vdata->offs_boot = tk->offs_boot;
2248 write_seqcount_end(&vdata->seq);
2251 static s64 get_kvmclock_base_ns(void)
2253 /* Count up from boot time, but with the frequency of the raw clock. */
2254 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2257 static s64 get_kvmclock_base_ns(void)
2259 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2260 return ktime_get_boottime_ns();
2264 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2268 struct pvclock_wall_clock wc;
2275 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2280 ++version; /* first time write, random junk */
2284 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2288 * The guest calculates current wall clock time by adding
2289 * system time (updated by kvm_guest_time_update below) to the
2290 * wall clock specified here. We do the reverse here.
2292 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
2294 wc.nsec = do_div(wall_nsec, 1000000000);
2295 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2296 wc.version = version;
2298 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2301 wc_sec_hi = wall_nsec >> 32;
2302 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2303 &wc_sec_hi, sizeof(wc_sec_hi));
2307 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2310 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2311 bool old_msr, bool host_initiated)
2313 struct kvm_arch *ka = &vcpu->kvm->arch;
2315 if (vcpu->vcpu_id == 0 && !host_initiated) {
2316 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2317 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2319 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2322 vcpu->arch.time = system_time;
2323 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2325 /* we verify if the enable bit is set... */
2326 if (system_time & 1)
2327 kvm_gpc_activate(&vcpu->arch.pv_time, system_time & ~1ULL,
2328 sizeof(struct pvclock_vcpu_time_info));
2330 kvm_gpc_deactivate(&vcpu->arch.pv_time);
2335 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2337 do_shl32_div32(dividend, divisor);
2341 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2342 s8 *pshift, u32 *pmultiplier)
2350 scaled64 = scaled_hz;
2351 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2356 tps32 = (uint32_t)tps64;
2357 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2358 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2366 *pmultiplier = div_frac(scaled64, tps32);
2369 #ifdef CONFIG_X86_64
2370 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2373 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2374 static unsigned long max_tsc_khz;
2376 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2378 u64 v = (u64)khz * (1000000 + ppm);
2383 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2385 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2389 /* Guest TSC same frequency as host TSC? */
2391 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2395 /* TSC scaling supported? */
2396 if (!kvm_caps.has_tsc_control) {
2397 if (user_tsc_khz > tsc_khz) {
2398 vcpu->arch.tsc_catchup = 1;
2399 vcpu->arch.tsc_always_catchup = 1;
2402 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2407 /* TSC scaling required - calculate ratio */
2408 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,
2409 user_tsc_khz, tsc_khz);
2411 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) {
2412 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2417 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2421 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2423 u32 thresh_lo, thresh_hi;
2424 int use_scaling = 0;
2426 /* tsc_khz can be zero if TSC calibration fails */
2427 if (user_tsc_khz == 0) {
2428 /* set tsc_scaling_ratio to a safe value */
2429 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2433 /* Compute a scale to convert nanoseconds in TSC cycles */
2434 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2435 &vcpu->arch.virtual_tsc_shift,
2436 &vcpu->arch.virtual_tsc_mult);
2437 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2440 * Compute the variation in TSC rate which is acceptable
2441 * within the range of tolerance and decide if the
2442 * rate being applied is within that bounds of the hardware
2443 * rate. If so, no scaling or compensation need be done.
2445 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2446 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2447 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2448 pr_debug("requested TSC rate %u falls outside tolerance [%u,%u]\n",
2449 user_tsc_khz, thresh_lo, thresh_hi);
2452 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2455 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2457 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2458 vcpu->arch.virtual_tsc_mult,
2459 vcpu->arch.virtual_tsc_shift);
2460 tsc += vcpu->arch.this_tsc_write;
2464 #ifdef CONFIG_X86_64
2465 static inline int gtod_is_based_on_tsc(int mode)
2467 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2471 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2473 #ifdef CONFIG_X86_64
2475 struct kvm_arch *ka = &vcpu->kvm->arch;
2476 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2478 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2479 atomic_read(&vcpu->kvm->online_vcpus));
2482 * Once the masterclock is enabled, always perform request in
2483 * order to update it.
2485 * In order to enable masterclock, the host clocksource must be TSC
2486 * and the vcpus need to have matched TSCs. When that happens,
2487 * perform request to enable masterclock.
2489 if (ka->use_master_clock ||
2490 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2491 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2493 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2494 atomic_read(&vcpu->kvm->online_vcpus),
2495 ka->use_master_clock, gtod->clock.vclock_mode);
2500 * Multiply tsc by a fixed point number represented by ratio.
2502 * The most significant 64-N bits (mult) of ratio represent the
2503 * integral part of the fixed point number; the remaining N bits
2504 * (frac) represent the fractional part, ie. ratio represents a fixed
2505 * point number (mult + frac * 2^(-N)).
2507 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
2509 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2511 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
2514 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2518 if (ratio != kvm_caps.default_tsc_scaling_ratio)
2519 _tsc = __scale_tsc(ratio, tsc);
2524 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2528 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2530 return target_tsc - tsc;
2533 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2535 return vcpu->arch.l1_tsc_offset +
2536 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2538 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2540 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2544 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio)
2545 nested_offset = l1_offset;
2547 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2548 kvm_caps.tsc_scaling_ratio_frac_bits);
2550 nested_offset += l2_offset;
2551 return nested_offset;
2553 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2555 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2557 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
2558 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2559 kvm_caps.tsc_scaling_ratio_frac_bits);
2561 return l1_multiplier;
2563 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2565 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2567 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2568 vcpu->arch.l1_tsc_offset,
2571 vcpu->arch.l1_tsc_offset = l1_offset;
2574 * If we are here because L1 chose not to trap WRMSR to TSC then
2575 * according to the spec this should set L1's TSC (as opposed to
2576 * setting L1's offset for L2).
2578 if (is_guest_mode(vcpu))
2579 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2581 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2582 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2584 vcpu->arch.tsc_offset = l1_offset;
2586 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset);
2589 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2591 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2593 /* Userspace is changing the multiplier while L2 is active */
2594 if (is_guest_mode(vcpu))
2595 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2597 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2599 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2601 if (kvm_caps.has_tsc_control)
2602 static_call(kvm_x86_write_tsc_multiplier)(
2603 vcpu, vcpu->arch.tsc_scaling_ratio);
2606 static inline bool kvm_check_tsc_unstable(void)
2608 #ifdef CONFIG_X86_64
2610 * TSC is marked unstable when we're running on Hyper-V,
2611 * 'TSC page' clocksource is good.
2613 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2616 return check_tsc_unstable();
2620 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2621 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2624 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2625 u64 ns, bool matched)
2627 struct kvm *kvm = vcpu->kvm;
2629 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2632 * We also track th most recent recorded KHZ, write and time to
2633 * allow the matching interval to be extended at each write.
2635 kvm->arch.last_tsc_nsec = ns;
2636 kvm->arch.last_tsc_write = tsc;
2637 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2638 kvm->arch.last_tsc_offset = offset;
2640 vcpu->arch.last_guest_tsc = tsc;
2642 kvm_vcpu_write_tsc_offset(vcpu, offset);
2646 * We split periods of matched TSC writes into generations.
2647 * For each generation, we track the original measured
2648 * nanosecond time, offset, and write, so if TSCs are in
2649 * sync, we can match exact offset, and if not, we can match
2650 * exact software computation in compute_guest_tsc()
2652 * These values are tracked in kvm->arch.cur_xxx variables.
2654 kvm->arch.cur_tsc_generation++;
2655 kvm->arch.cur_tsc_nsec = ns;
2656 kvm->arch.cur_tsc_write = tsc;
2657 kvm->arch.cur_tsc_offset = offset;
2658 kvm->arch.nr_vcpus_matched_tsc = 0;
2659 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2660 kvm->arch.nr_vcpus_matched_tsc++;
2663 /* Keep track of which generation this VCPU has synchronized to */
2664 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2665 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2666 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2668 kvm_track_tsc_matching(vcpu);
2671 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2673 struct kvm *kvm = vcpu->kvm;
2674 u64 offset, ns, elapsed;
2675 unsigned long flags;
2676 bool matched = false;
2677 bool synchronizing = false;
2679 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2680 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2681 ns = get_kvmclock_base_ns();
2682 elapsed = ns - kvm->arch.last_tsc_nsec;
2684 if (vcpu->arch.virtual_tsc_khz) {
2687 * detection of vcpu initialization -- need to sync
2688 * with other vCPUs. This particularly helps to keep
2689 * kvm_clock stable after CPU hotplug
2691 synchronizing = true;
2693 u64 tsc_exp = kvm->arch.last_tsc_write +
2694 nsec_to_cycles(vcpu, elapsed);
2695 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2697 * Special case: TSC write with a small delta (1 second)
2698 * of virtual cycle time against real time is
2699 * interpreted as an attempt to synchronize the CPU.
2701 synchronizing = data < tsc_exp + tsc_hz &&
2702 data + tsc_hz > tsc_exp;
2707 * For a reliable TSC, we can match TSC offsets, and for an unstable
2708 * TSC, we add elapsed time in this computation. We could let the
2709 * compensation code attempt to catch up if we fall behind, but
2710 * it's better to try to match offsets from the beginning.
2712 if (synchronizing &&
2713 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2714 if (!kvm_check_tsc_unstable()) {
2715 offset = kvm->arch.cur_tsc_offset;
2717 u64 delta = nsec_to_cycles(vcpu, elapsed);
2719 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2724 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2725 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2728 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2731 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2732 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2735 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2737 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
2738 WARN_ON(adjustment < 0);
2739 adjustment = kvm_scale_tsc((u64) adjustment,
2740 vcpu->arch.l1_tsc_scaling_ratio);
2741 adjust_tsc_offset_guest(vcpu, adjustment);
2744 #ifdef CONFIG_X86_64
2746 static u64 read_tsc(void)
2748 u64 ret = (u64)rdtsc_ordered();
2749 u64 last = pvclock_gtod_data.clock.cycle_last;
2751 if (likely(ret >= last))
2755 * GCC likes to generate cmov here, but this branch is extremely
2756 * predictable (it's just a function of time and the likely is
2757 * very likely) and there's a data dependence, so force GCC
2758 * to generate a branch instead. I don't barrier() because
2759 * we don't actually need a barrier, and if this function
2760 * ever gets inlined it will generate worse code.
2766 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2772 switch (clock->vclock_mode) {
2773 case VDSO_CLOCKMODE_HVCLOCK:
2774 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2776 if (tsc_pg_val != U64_MAX) {
2777 /* TSC page valid */
2778 *mode = VDSO_CLOCKMODE_HVCLOCK;
2779 v = (tsc_pg_val - clock->cycle_last) &
2782 /* TSC page invalid */
2783 *mode = VDSO_CLOCKMODE_NONE;
2786 case VDSO_CLOCKMODE_TSC:
2787 *mode = VDSO_CLOCKMODE_TSC;
2788 *tsc_timestamp = read_tsc();
2789 v = (*tsc_timestamp - clock->cycle_last) &
2793 *mode = VDSO_CLOCKMODE_NONE;
2796 if (*mode == VDSO_CLOCKMODE_NONE)
2797 *tsc_timestamp = v = 0;
2799 return v * clock->mult;
2802 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2804 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2810 seq = read_seqcount_begin(>od->seq);
2811 ns = gtod->raw_clock.base_cycles;
2812 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2813 ns >>= gtod->raw_clock.shift;
2814 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2815 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2821 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2823 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2829 seq = read_seqcount_begin(>od->seq);
2830 ts->tv_sec = gtod->wall_time_sec;
2831 ns = gtod->clock.base_cycles;
2832 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2833 ns >>= gtod->clock.shift;
2834 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2836 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2842 /* returns true if host is using TSC based clocksource */
2843 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2845 /* checked again under seqlock below */
2846 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2849 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2853 /* returns true if host is using TSC based clocksource */
2854 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2857 /* checked again under seqlock below */
2858 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2861 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2867 * Assuming a stable TSC across physical CPUS, and a stable TSC
2868 * across virtual CPUs, the following condition is possible.
2869 * Each numbered line represents an event visible to both
2870 * CPUs at the next numbered event.
2872 * "timespecX" represents host monotonic time. "tscX" represents
2875 * VCPU0 on CPU0 | VCPU1 on CPU1
2877 * 1. read timespec0,tsc0
2878 * 2. | timespec1 = timespec0 + N
2880 * 3. transition to guest | transition to guest
2881 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2882 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2883 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2885 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2888 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2890 * - 0 < N - M => M < N
2892 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2893 * always the case (the difference between two distinct xtime instances
2894 * might be smaller then the difference between corresponding TSC reads,
2895 * when updating guest vcpus pvclock areas).
2897 * To avoid that problem, do not allow visibility of distinct
2898 * system_timestamp/tsc_timestamp values simultaneously: use a master
2899 * copy of host monotonic time values. Update that master copy
2902 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2906 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2908 #ifdef CONFIG_X86_64
2909 struct kvm_arch *ka = &kvm->arch;
2911 bool host_tsc_clocksource, vcpus_matched;
2913 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2914 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2915 atomic_read(&kvm->online_vcpus));
2918 * If the host uses TSC clock, then passthrough TSC as stable
2921 host_tsc_clocksource = kvm_get_time_and_clockread(
2922 &ka->master_kernel_ns,
2923 &ka->master_cycle_now);
2925 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2926 && !ka->backwards_tsc_observed
2927 && !ka->boot_vcpu_runs_old_kvmclock;
2929 if (ka->use_master_clock)
2930 atomic_set(&kvm_guest_has_master_clock, 1);
2932 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2933 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2938 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2940 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2943 static void __kvm_start_pvclock_update(struct kvm *kvm)
2945 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
2946 write_seqcount_begin(&kvm->arch.pvclock_sc);
2949 static void kvm_start_pvclock_update(struct kvm *kvm)
2951 kvm_make_mclock_inprogress_request(kvm);
2953 /* no guest entries from this point */
2954 __kvm_start_pvclock_update(kvm);
2957 static void kvm_end_pvclock_update(struct kvm *kvm)
2959 struct kvm_arch *ka = &kvm->arch;
2960 struct kvm_vcpu *vcpu;
2963 write_seqcount_end(&ka->pvclock_sc);
2964 raw_spin_unlock_irq(&ka->tsc_write_lock);
2965 kvm_for_each_vcpu(i, vcpu, kvm)
2966 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2968 /* guest entries allowed */
2969 kvm_for_each_vcpu(i, vcpu, kvm)
2970 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2973 static void kvm_update_masterclock(struct kvm *kvm)
2975 kvm_hv_request_tsc_page_update(kvm);
2976 kvm_start_pvclock_update(kvm);
2977 pvclock_update_vm_gtod_copy(kvm);
2978 kvm_end_pvclock_update(kvm);
2982 * Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's
2983 * per-CPU value (which may be zero if a CPU is going offline). Note, tsc_khz
2984 * can change during boot even if the TSC is constant, as it's possible for KVM
2985 * to be loaded before TSC calibration completes. Ideally, KVM would get a
2986 * notification when calibration completes, but practically speaking calibration
2987 * will complete before userspace is alive enough to create VMs.
2989 static unsigned long get_cpu_tsc_khz(void)
2991 if (static_cpu_has(X86_FEATURE_CONSTANT_TSC))
2994 return __this_cpu_read(cpu_tsc_khz);
2997 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
2998 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3000 struct kvm_arch *ka = &kvm->arch;
3001 struct pvclock_vcpu_time_info hv_clock;
3003 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
3007 if (ka->use_master_clock &&
3008 (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) {
3009 #ifdef CONFIG_X86_64
3010 struct timespec64 ts;
3012 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
3013 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
3014 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
3017 data->host_tsc = rdtsc();
3019 data->flags |= KVM_CLOCK_TSC_STABLE;
3020 hv_clock.tsc_timestamp = ka->master_cycle_now;
3021 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
3022 kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL,
3023 &hv_clock.tsc_shift,
3024 &hv_clock.tsc_to_system_mul);
3025 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
3027 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
3033 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3035 struct kvm_arch *ka = &kvm->arch;
3039 seq = read_seqcount_begin(&ka->pvclock_sc);
3040 __get_kvmclock(kvm, data);
3041 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3044 u64 get_kvmclock_ns(struct kvm *kvm)
3046 struct kvm_clock_data data;
3048 get_kvmclock(kvm, &data);
3052 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v,
3053 struct gfn_to_pfn_cache *gpc,
3054 unsigned int offset)
3056 struct kvm_vcpu_arch *vcpu = &v->arch;
3057 struct pvclock_vcpu_time_info *guest_hv_clock;
3058 unsigned long flags;
3060 read_lock_irqsave(&gpc->lock, flags);
3061 while (!kvm_gpc_check(gpc, offset + sizeof(*guest_hv_clock))) {
3062 read_unlock_irqrestore(&gpc->lock, flags);
3064 if (kvm_gpc_refresh(gpc, offset + sizeof(*guest_hv_clock)))
3067 read_lock_irqsave(&gpc->lock, flags);
3070 guest_hv_clock = (void *)(gpc->khva + offset);
3073 * This VCPU is paused, but it's legal for a guest to read another
3074 * VCPU's kvmclock, so we really have to follow the specification where
3075 * it says that version is odd if data is being modified, and even after
3079 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1;
3082 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3083 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
3085 if (vcpu->pvclock_set_guest_stopped_request) {
3086 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3087 vcpu->pvclock_set_guest_stopped_request = false;
3090 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock));
3093 guest_hv_clock->version = ++vcpu->hv_clock.version;
3095 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT);
3096 read_unlock_irqrestore(&gpc->lock, flags);
3098 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3101 static int kvm_guest_time_update(struct kvm_vcpu *v)
3103 unsigned long flags, tgt_tsc_khz;
3105 struct kvm_vcpu_arch *vcpu = &v->arch;
3106 struct kvm_arch *ka = &v->kvm->arch;
3108 u64 tsc_timestamp, host_tsc;
3110 bool use_master_clock;
3116 * If the host uses TSC clock, then passthrough TSC as stable
3120 seq = read_seqcount_begin(&ka->pvclock_sc);
3121 use_master_clock = ka->use_master_clock;
3122 if (use_master_clock) {
3123 host_tsc = ka->master_cycle_now;
3124 kernel_ns = ka->master_kernel_ns;
3126 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3128 /* Keep irq disabled to prevent changes to the clock */
3129 local_irq_save(flags);
3130 tgt_tsc_khz = get_cpu_tsc_khz();
3131 if (unlikely(tgt_tsc_khz == 0)) {
3132 local_irq_restore(flags);
3133 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3136 if (!use_master_clock) {
3138 kernel_ns = get_kvmclock_base_ns();
3141 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3144 * We may have to catch up the TSC to match elapsed wall clock
3145 * time for two reasons, even if kvmclock is used.
3146 * 1) CPU could have been running below the maximum TSC rate
3147 * 2) Broken TSC compensation resets the base at each VCPU
3148 * entry to avoid unknown leaps of TSC even when running
3149 * again on the same CPU. This may cause apparent elapsed
3150 * time to disappear, and the guest to stand still or run
3153 if (vcpu->tsc_catchup) {
3154 u64 tsc = compute_guest_tsc(v, kernel_ns);
3155 if (tsc > tsc_timestamp) {
3156 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3157 tsc_timestamp = tsc;
3161 local_irq_restore(flags);
3163 /* With all the info we got, fill in the values */
3165 if (kvm_caps.has_tsc_control)
3166 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3167 v->arch.l1_tsc_scaling_ratio);
3169 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3170 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3171 &vcpu->hv_clock.tsc_shift,
3172 &vcpu->hv_clock.tsc_to_system_mul);
3173 vcpu->hw_tsc_khz = tgt_tsc_khz;
3174 kvm_xen_update_tsc_info(v);
3177 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3178 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3179 vcpu->last_guest_tsc = tsc_timestamp;
3181 /* If the host uses TSC clocksource, then it is stable */
3183 if (use_master_clock)
3184 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3186 vcpu->hv_clock.flags = pvclock_flags;
3188 if (vcpu->pv_time.active)
3189 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0);
3190 if (vcpu->xen.vcpu_info_cache.active)
3191 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache,
3192 offsetof(struct compat_vcpu_info, time));
3193 if (vcpu->xen.vcpu_time_info_cache.active)
3194 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0);
3195 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3200 * kvmclock updates which are isolated to a given vcpu, such as
3201 * vcpu->cpu migration, should not allow system_timestamp from
3202 * the rest of the vcpus to remain static. Otherwise ntp frequency
3203 * correction applies to one vcpu's system_timestamp but not
3206 * So in those cases, request a kvmclock update for all vcpus.
3207 * We need to rate-limit these requests though, as they can
3208 * considerably slow guests that have a large number of vcpus.
3209 * The time for a remote vcpu to update its kvmclock is bound
3210 * by the delay we use to rate-limit the updates.
3213 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3215 static void kvmclock_update_fn(struct work_struct *work)
3218 struct delayed_work *dwork = to_delayed_work(work);
3219 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3220 kvmclock_update_work);
3221 struct kvm *kvm = container_of(ka, struct kvm, arch);
3222 struct kvm_vcpu *vcpu;
3224 kvm_for_each_vcpu(i, vcpu, kvm) {
3225 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3226 kvm_vcpu_kick(vcpu);
3230 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3232 struct kvm *kvm = v->kvm;
3234 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3235 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3236 KVMCLOCK_UPDATE_DELAY);
3239 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3241 static void kvmclock_sync_fn(struct work_struct *work)
3243 struct delayed_work *dwork = to_delayed_work(work);
3244 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3245 kvmclock_sync_work);
3246 struct kvm *kvm = container_of(ka, struct kvm, arch);
3248 if (!kvmclock_periodic_sync)
3251 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3252 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3253 KVMCLOCK_SYNC_PERIOD);
3256 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */
3257 static bool is_mci_control_msr(u32 msr)
3259 return (msr & 3) == 0;
3261 static bool is_mci_status_msr(u32 msr)
3263 return (msr & 3) == 1;
3267 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3269 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3271 /* McStatusWrEn enabled? */
3272 if (guest_cpuid_is_amd_or_hygon(vcpu))
3273 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3278 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3280 u64 mcg_cap = vcpu->arch.mcg_cap;
3281 unsigned bank_num = mcg_cap & 0xff;
3282 u32 msr = msr_info->index;
3283 u64 data = msr_info->data;
3284 u32 offset, last_msr;
3287 case MSR_IA32_MCG_STATUS:
3288 vcpu->arch.mcg_status = data;
3290 case MSR_IA32_MCG_CTL:
3291 if (!(mcg_cap & MCG_CTL_P) &&
3292 (data || !msr_info->host_initiated))
3294 if (data != 0 && data != ~(u64)0)
3296 vcpu->arch.mcg_ctl = data;
3298 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3299 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3303 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
3305 /* An attempt to write a 1 to a reserved bit raises #GP */
3306 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
3308 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3309 last_msr + 1 - MSR_IA32_MC0_CTL2);
3310 vcpu->arch.mci_ctl2_banks[offset] = data;
3312 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3313 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3318 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other
3319 * values are architecturally undefined. But, some Linux
3320 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
3321 * issue on AMD K8s, allow bit 10 to be clear when setting all
3322 * other bits in order to avoid an uncaught #GP in the guest.
3324 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable,
3325 * single-bit ECC data errors.
3327 if (is_mci_control_msr(msr) &&
3328 data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
3332 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR.
3333 * AMD-based CPUs allow non-zero values, but if and only if
3334 * HWCR[McStatusWrEn] is set.
3336 if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
3337 data != 0 && !can_set_mci_status(vcpu))
3340 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3341 last_msr + 1 - MSR_IA32_MC0_CTL);
3342 vcpu->arch.mce_banks[offset] = data;
3350 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3352 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3354 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3357 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3359 gpa_t gpa = data & ~0x3f;
3361 /* Bits 4:5 are reserved, Should be zero */
3365 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3366 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3369 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3370 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3373 if (!lapic_in_kernel(vcpu))
3374 return data ? 1 : 0;
3376 vcpu->arch.apf.msr_en_val = data;
3378 if (!kvm_pv_async_pf_enabled(vcpu)) {
3379 kvm_clear_async_pf_completion_queue(vcpu);
3380 kvm_async_pf_hash_reset(vcpu);
3384 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3388 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3389 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3391 kvm_async_pf_wakeup_all(vcpu);
3396 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3398 /* Bits 8-63 are reserved */
3402 if (!lapic_in_kernel(vcpu))
3405 vcpu->arch.apf.msr_int_val = data;
3407 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3412 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3414 kvm_gpc_deactivate(&vcpu->arch.pv_time);
3415 vcpu->arch.time = 0;
3418 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3420 ++vcpu->stat.tlb_flush;
3421 static_call(kvm_x86_flush_tlb_all)(vcpu);
3423 /* Flushing all ASIDs flushes the current ASID... */
3424 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3427 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3429 ++vcpu->stat.tlb_flush;
3433 * A TLB flush on behalf of the guest is equivalent to
3434 * INVPCID(all), toggling CR4.PGE, etc., which requires
3435 * a forced sync of the shadow page tables. Ensure all the
3436 * roots are synced and the guest TLB in hardware is clean.
3438 kvm_mmu_sync_roots(vcpu);
3439 kvm_mmu_sync_prev_roots(vcpu);
3442 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3445 * Flushing all "guest" TLB is always a superset of Hyper-V's fine
3448 kvm_hv_vcpu_purge_flush_tlb(vcpu);
3452 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3454 ++vcpu->stat.tlb_flush;
3455 static_call(kvm_x86_flush_tlb_current)(vcpu);
3459 * Service "local" TLB flush requests, which are specific to the current MMU
3460 * context. In addition to the generic event handling in vcpu_enter_guest(),
3461 * TLB flushes that are targeted at an MMU context also need to be serviced
3462 * prior before nested VM-Enter/VM-Exit.
3464 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3466 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3467 kvm_vcpu_flush_tlb_current(vcpu);
3469 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3470 kvm_vcpu_flush_tlb_guest(vcpu);
3472 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3474 static void record_steal_time(struct kvm_vcpu *vcpu)
3476 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3477 struct kvm_steal_time __user *st;
3478 struct kvm_memslots *slots;
3479 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3483 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3484 kvm_xen_runstate_set_running(vcpu);
3488 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3491 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3494 slots = kvm_memslots(vcpu->kvm);
3496 if (unlikely(slots->generation != ghc->generation ||
3498 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3499 /* We rely on the fact that it fits in a single page. */
3500 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3502 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) ||
3503 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3507 st = (struct kvm_steal_time __user *)ghc->hva;
3509 * Doing a TLB flush here, on the guest's behalf, can avoid
3512 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3513 u8 st_preempted = 0;
3516 if (!user_access_begin(st, sizeof(*st)))
3519 asm volatile("1: xchgb %0, %2\n"
3522 _ASM_EXTABLE_UA(1b, 2b)
3523 : "+q" (st_preempted),
3525 "+m" (st->preempted));
3531 vcpu->arch.st.preempted = 0;
3533 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3534 st_preempted & KVM_VCPU_FLUSH_TLB);
3535 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3536 kvm_vcpu_flush_tlb_guest(vcpu);
3538 if (!user_access_begin(st, sizeof(*st)))
3541 if (!user_access_begin(st, sizeof(*st)))
3544 unsafe_put_user(0, &st->preempted, out);
3545 vcpu->arch.st.preempted = 0;
3548 unsafe_get_user(version, &st->version, out);
3550 version += 1; /* first time write, random junk */
3553 unsafe_put_user(version, &st->version, out);
3557 unsafe_get_user(steal, &st->steal, out);
3558 steal += current->sched_info.run_delay -
3559 vcpu->arch.st.last_steal;
3560 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3561 unsafe_put_user(steal, &st->steal, out);
3564 unsafe_put_user(version, &st->version, out);
3569 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3572 static bool kvm_is_msr_to_save(u32 msr_index)
3576 for (i = 0; i < num_msrs_to_save; i++) {
3577 if (msrs_to_save[i] == msr_index)
3584 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3586 u32 msr = msr_info->index;
3587 u64 data = msr_info->data;
3589 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3590 return kvm_xen_write_hypercall_page(vcpu, data);
3593 case MSR_AMD64_NB_CFG:
3594 case MSR_IA32_UCODE_WRITE:
3595 case MSR_VM_HSAVE_PA:
3596 case MSR_AMD64_PATCH_LOADER:
3597 case MSR_AMD64_BU_CFG2:
3598 case MSR_AMD64_DC_CFG:
3599 case MSR_F15H_EX_CFG:
3602 case MSR_IA32_UCODE_REV:
3603 if (msr_info->host_initiated)
3604 vcpu->arch.microcode_version = data;
3606 case MSR_IA32_ARCH_CAPABILITIES:
3607 if (!msr_info->host_initiated)
3609 vcpu->arch.arch_capabilities = data;
3611 case MSR_IA32_PERF_CAPABILITIES:
3612 if (!msr_info->host_initiated)
3614 if (data & ~kvm_caps.supported_perf_cap)
3617 vcpu->arch.perf_capabilities = data;
3618 kvm_pmu_refresh(vcpu);
3620 case MSR_IA32_PRED_CMD:
3621 if (!msr_info->host_initiated && !guest_has_pred_cmd_msr(vcpu))
3624 if (!boot_cpu_has(X86_FEATURE_IBPB) || (data & ~PRED_CMD_IBPB))
3629 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3631 case MSR_IA32_FLUSH_CMD:
3632 if (!msr_info->host_initiated &&
3633 !guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D))
3636 if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH))
3641 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
3644 return set_efer(vcpu, msr_info);
3646 data &= ~(u64)0x40; /* ignore flush filter disable */
3647 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3648 data &= ~(u64)0x8; /* ignore TLB cache disable */
3650 /* Handle McStatusWrEn */
3651 if (data == BIT_ULL(18)) {
3652 vcpu->arch.msr_hwcr = data;
3653 } else if (data != 0) {
3654 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3658 case MSR_FAM10H_MMIO_CONF_BASE:
3660 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3664 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
3665 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
3666 return kvm_mtrr_set_msr(vcpu, msr, data);
3667 case MSR_IA32_APICBASE:
3668 return kvm_set_apic_base(vcpu, msr_info);
3669 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3670 return kvm_x2apic_msr_write(vcpu, msr, data);
3671 case MSR_IA32_TSC_DEADLINE:
3672 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3674 case MSR_IA32_TSC_ADJUST:
3675 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3676 if (!msr_info->host_initiated) {
3677 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3678 adjust_tsc_offset_guest(vcpu, adj);
3679 /* Before back to guest, tsc_timestamp must be adjusted
3680 * as well, otherwise guest's percpu pvclock time could jump.
3682 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3684 vcpu->arch.ia32_tsc_adjust_msr = data;
3687 case MSR_IA32_MISC_ENABLE: {
3688 u64 old_val = vcpu->arch.ia32_misc_enable_msr;
3690 if (!msr_info->host_initiated) {
3692 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK)
3695 /* R bits, i.e. writes are ignored, but don't fault. */
3696 data = data & ~MSR_IA32_MISC_ENABLE_EMON;
3697 data |= old_val & MSR_IA32_MISC_ENABLE_EMON;
3700 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3701 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3702 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3704 vcpu->arch.ia32_misc_enable_msr = data;
3705 kvm_update_cpuid_runtime(vcpu);
3707 vcpu->arch.ia32_misc_enable_msr = data;
3711 case MSR_IA32_SMBASE:
3712 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
3714 vcpu->arch.smbase = data;
3716 case MSR_IA32_POWER_CTL:
3717 vcpu->arch.msr_ia32_power_ctl = data;
3720 if (msr_info->host_initiated) {
3721 kvm_synchronize_tsc(vcpu, data);
3723 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3724 adjust_tsc_offset_guest(vcpu, adj);
3725 vcpu->arch.ia32_tsc_adjust_msr += adj;
3729 if (!msr_info->host_initiated &&
3730 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3733 * KVM supports exposing PT to the guest, but does not support
3734 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3735 * XSAVES/XRSTORS to save/restore PT MSRs.
3737 if (data & ~kvm_caps.supported_xss)
3739 vcpu->arch.ia32_xss = data;
3740 kvm_update_cpuid_runtime(vcpu);
3743 if (!msr_info->host_initiated)
3745 vcpu->arch.smi_count = data;
3747 case MSR_KVM_WALL_CLOCK_NEW:
3748 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3751 vcpu->kvm->arch.wall_clock = data;
3752 kvm_write_wall_clock(vcpu->kvm, data, 0);
3754 case MSR_KVM_WALL_CLOCK:
3755 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3758 vcpu->kvm->arch.wall_clock = data;
3759 kvm_write_wall_clock(vcpu->kvm, data, 0);
3761 case MSR_KVM_SYSTEM_TIME_NEW:
3762 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3765 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3767 case MSR_KVM_SYSTEM_TIME:
3768 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3771 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3773 case MSR_KVM_ASYNC_PF_EN:
3774 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3777 if (kvm_pv_enable_async_pf(vcpu, data))
3780 case MSR_KVM_ASYNC_PF_INT:
3781 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3784 if (kvm_pv_enable_async_pf_int(vcpu, data))
3787 case MSR_KVM_ASYNC_PF_ACK:
3788 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3791 vcpu->arch.apf.pageready_pending = false;
3792 kvm_check_async_pf_completion(vcpu);
3795 case MSR_KVM_STEAL_TIME:
3796 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3799 if (unlikely(!sched_info_on()))
3802 if (data & KVM_STEAL_RESERVED_MASK)
3805 vcpu->arch.st.msr_val = data;
3807 if (!(data & KVM_MSR_ENABLED))
3810 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3813 case MSR_KVM_PV_EOI_EN:
3814 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3817 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
3821 case MSR_KVM_POLL_CONTROL:
3822 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3825 /* only enable bit supported */
3826 if (data & (-1ULL << 1))
3829 vcpu->arch.msr_kvm_poll_control = data;
3832 case MSR_IA32_MCG_CTL:
3833 case MSR_IA32_MCG_STATUS:
3834 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3835 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3836 return set_msr_mce(vcpu, msr_info);
3838 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3839 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3840 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3841 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3842 if (kvm_pmu_is_valid_msr(vcpu, msr))
3843 return kvm_pmu_set_msr(vcpu, msr_info);
3846 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3848 case MSR_K7_CLK_CTL:
3850 * Ignore all writes to this no longer documented MSR.
3851 * Writes are only relevant for old K7 processors,
3852 * all pre-dating SVM, but a recommended workaround from
3853 * AMD for these chips. It is possible to specify the
3854 * affected processor models on the command line, hence
3855 * the need to ignore the workaround.
3858 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3859 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3860 case HV_X64_MSR_SYNDBG_OPTIONS:
3861 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3862 case HV_X64_MSR_CRASH_CTL:
3863 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3864 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3865 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3866 case HV_X64_MSR_TSC_EMULATION_STATUS:
3867 case HV_X64_MSR_TSC_INVARIANT_CONTROL:
3868 return kvm_hv_set_msr_common(vcpu, msr, data,
3869 msr_info->host_initiated);
3870 case MSR_IA32_BBL_CR_CTL3:
3871 /* Drop writes to this legacy MSR -- see rdmsr
3872 * counterpart for further detail.
3874 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3876 case MSR_AMD64_OSVW_ID_LENGTH:
3877 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3879 vcpu->arch.osvw.length = data;
3881 case MSR_AMD64_OSVW_STATUS:
3882 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3884 vcpu->arch.osvw.status = data;
3886 case MSR_PLATFORM_INFO:
3887 if (!msr_info->host_initiated ||
3888 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3889 cpuid_fault_enabled(vcpu)))
3891 vcpu->arch.msr_platform_info = data;
3893 case MSR_MISC_FEATURES_ENABLES:
3894 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3895 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3896 !supports_cpuid_fault(vcpu)))
3898 vcpu->arch.msr_misc_features_enables = data;
3900 #ifdef CONFIG_X86_64
3902 if (!msr_info->host_initiated &&
3903 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3906 if (data & ~kvm_guest_supported_xfd(vcpu))
3909 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
3911 case MSR_IA32_XFD_ERR:
3912 if (!msr_info->host_initiated &&
3913 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3916 if (data & ~kvm_guest_supported_xfd(vcpu))
3919 vcpu->arch.guest_fpu.xfd_err = data;
3923 if (kvm_pmu_is_valid_msr(vcpu, msr))
3924 return kvm_pmu_set_msr(vcpu, msr_info);
3927 * Userspace is allowed to write '0' to MSRs that KVM reports
3928 * as to-be-saved, even if an MSRs isn't fully supported.
3930 if (msr_info->host_initiated && !data &&
3931 kvm_is_msr_to_save(msr))
3934 return KVM_MSR_RET_INVALID;
3938 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3940 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3943 u64 mcg_cap = vcpu->arch.mcg_cap;
3944 unsigned bank_num = mcg_cap & 0xff;
3945 u32 offset, last_msr;
3948 case MSR_IA32_P5_MC_ADDR:
3949 case MSR_IA32_P5_MC_TYPE:
3952 case MSR_IA32_MCG_CAP:
3953 data = vcpu->arch.mcg_cap;
3955 case MSR_IA32_MCG_CTL:
3956 if (!(mcg_cap & MCG_CTL_P) && !host)
3958 data = vcpu->arch.mcg_ctl;
3960 case MSR_IA32_MCG_STATUS:
3961 data = vcpu->arch.mcg_status;
3963 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3964 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3968 if (!(mcg_cap & MCG_CMCI_P) && !host)
3970 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3971 last_msr + 1 - MSR_IA32_MC0_CTL2);
3972 data = vcpu->arch.mci_ctl2_banks[offset];
3974 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3975 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3979 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3980 last_msr + 1 - MSR_IA32_MC0_CTL);
3981 data = vcpu->arch.mce_banks[offset];
3990 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3992 switch (msr_info->index) {
3993 case MSR_IA32_PLATFORM_ID:
3994 case MSR_IA32_EBL_CR_POWERON:
3995 case MSR_IA32_LASTBRANCHFROMIP:
3996 case MSR_IA32_LASTBRANCHTOIP:
3997 case MSR_IA32_LASTINTFROMIP:
3998 case MSR_IA32_LASTINTTOIP:
3999 case MSR_AMD64_SYSCFG:
4000 case MSR_K8_TSEG_ADDR:
4001 case MSR_K8_TSEG_MASK:
4002 case MSR_VM_HSAVE_PA:
4003 case MSR_K8_INT_PENDING_MSG:
4004 case MSR_AMD64_NB_CFG:
4005 case MSR_FAM10H_MMIO_CONF_BASE:
4006 case MSR_AMD64_BU_CFG2:
4007 case MSR_IA32_PERF_CTL:
4008 case MSR_AMD64_DC_CFG:
4009 case MSR_F15H_EX_CFG:
4011 * Intel Sandy Bridge CPUs must support the RAPL (running average power
4012 * limit) MSRs. Just return 0, as we do not want to expose the host
4013 * data here. Do not conditionalize this on CPUID, as KVM does not do
4014 * so for existing CPU-specific MSRs.
4016 case MSR_RAPL_POWER_UNIT:
4017 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
4018 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
4019 case MSR_PKG_ENERGY_STATUS: /* Total package */
4020 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
4023 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
4024 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
4025 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
4026 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
4027 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4028 return kvm_pmu_get_msr(vcpu, msr_info);
4031 case MSR_IA32_UCODE_REV:
4032 msr_info->data = vcpu->arch.microcode_version;
4034 case MSR_IA32_ARCH_CAPABILITIES:
4035 if (!msr_info->host_initiated &&
4036 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4038 msr_info->data = vcpu->arch.arch_capabilities;
4040 case MSR_IA32_PERF_CAPABILITIES:
4041 if (!msr_info->host_initiated &&
4042 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
4044 msr_info->data = vcpu->arch.perf_capabilities;
4046 case MSR_IA32_POWER_CTL:
4047 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
4049 case MSR_IA32_TSC: {
4051 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
4052 * even when not intercepted. AMD manual doesn't explicitly
4053 * state this but appears to behave the same.
4055 * On userspace reads and writes, however, we unconditionally
4056 * return L1's TSC value to ensure backwards-compatible
4057 * behavior for migration.
4061 if (msr_info->host_initiated) {
4062 offset = vcpu->arch.l1_tsc_offset;
4063 ratio = vcpu->arch.l1_tsc_scaling_ratio;
4065 offset = vcpu->arch.tsc_offset;
4066 ratio = vcpu->arch.tsc_scaling_ratio;
4069 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
4073 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
4074 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
4075 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
4076 case 0xcd: /* fsb frequency */
4080 * MSR_EBC_FREQUENCY_ID
4081 * Conservative value valid for even the basic CPU models.
4082 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
4083 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
4084 * and 266MHz for model 3, or 4. Set Core Clock
4085 * Frequency to System Bus Frequency Ratio to 1 (bits
4086 * 31:24) even though these are only valid for CPU
4087 * models > 2, however guests may end up dividing or
4088 * multiplying by zero otherwise.
4090 case MSR_EBC_FREQUENCY_ID:
4091 msr_info->data = 1 << 24;
4093 case MSR_IA32_APICBASE:
4094 msr_info->data = kvm_get_apic_base(vcpu);
4096 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
4097 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
4098 case MSR_IA32_TSC_DEADLINE:
4099 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
4101 case MSR_IA32_TSC_ADJUST:
4102 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
4104 case MSR_IA32_MISC_ENABLE:
4105 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
4107 case MSR_IA32_SMBASE:
4108 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
4110 msr_info->data = vcpu->arch.smbase;
4113 msr_info->data = vcpu->arch.smi_count;
4115 case MSR_IA32_PERF_STATUS:
4116 /* TSC increment by tick */
4117 msr_info->data = 1000ULL;
4118 /* CPU multiplier */
4119 msr_info->data |= (((uint64_t)4ULL) << 40);
4122 msr_info->data = vcpu->arch.efer;
4124 case MSR_KVM_WALL_CLOCK:
4125 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4128 msr_info->data = vcpu->kvm->arch.wall_clock;
4130 case MSR_KVM_WALL_CLOCK_NEW:
4131 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4134 msr_info->data = vcpu->kvm->arch.wall_clock;
4136 case MSR_KVM_SYSTEM_TIME:
4137 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4140 msr_info->data = vcpu->arch.time;
4142 case MSR_KVM_SYSTEM_TIME_NEW:
4143 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4146 msr_info->data = vcpu->arch.time;
4148 case MSR_KVM_ASYNC_PF_EN:
4149 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
4152 msr_info->data = vcpu->arch.apf.msr_en_val;
4154 case MSR_KVM_ASYNC_PF_INT:
4155 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4158 msr_info->data = vcpu->arch.apf.msr_int_val;
4160 case MSR_KVM_ASYNC_PF_ACK:
4161 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4166 case MSR_KVM_STEAL_TIME:
4167 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
4170 msr_info->data = vcpu->arch.st.msr_val;
4172 case MSR_KVM_PV_EOI_EN:
4173 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4176 msr_info->data = vcpu->arch.pv_eoi.msr_val;
4178 case MSR_KVM_POLL_CONTROL:
4179 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4182 msr_info->data = vcpu->arch.msr_kvm_poll_control;
4184 case MSR_IA32_P5_MC_ADDR:
4185 case MSR_IA32_P5_MC_TYPE:
4186 case MSR_IA32_MCG_CAP:
4187 case MSR_IA32_MCG_CTL:
4188 case MSR_IA32_MCG_STATUS:
4189 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4190 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4191 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4192 msr_info->host_initiated);
4194 if (!msr_info->host_initiated &&
4195 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4197 msr_info->data = vcpu->arch.ia32_xss;
4199 case MSR_K7_CLK_CTL:
4201 * Provide expected ramp-up count for K7. All other
4202 * are set to zero, indicating minimum divisors for
4205 * This prevents guest kernels on AMD host with CPU
4206 * type 6, model 8 and higher from exploding due to
4207 * the rdmsr failing.
4209 msr_info->data = 0x20000000;
4211 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4212 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4213 case HV_X64_MSR_SYNDBG_OPTIONS:
4214 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4215 case HV_X64_MSR_CRASH_CTL:
4216 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4217 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4218 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4219 case HV_X64_MSR_TSC_EMULATION_STATUS:
4220 case HV_X64_MSR_TSC_INVARIANT_CONTROL:
4221 return kvm_hv_get_msr_common(vcpu,
4222 msr_info->index, &msr_info->data,
4223 msr_info->host_initiated);
4224 case MSR_IA32_BBL_CR_CTL3:
4225 /* This legacy MSR exists but isn't fully documented in current
4226 * silicon. It is however accessed by winxp in very narrow
4227 * scenarios where it sets bit #19, itself documented as
4228 * a "reserved" bit. Best effort attempt to source coherent
4229 * read data here should the balance of the register be
4230 * interpreted by the guest:
4232 * L2 cache control register 3: 64GB range, 256KB size,
4233 * enabled, latency 0x1, configured
4235 msr_info->data = 0xbe702111;
4237 case MSR_AMD64_OSVW_ID_LENGTH:
4238 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4240 msr_info->data = vcpu->arch.osvw.length;
4242 case MSR_AMD64_OSVW_STATUS:
4243 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4245 msr_info->data = vcpu->arch.osvw.status;
4247 case MSR_PLATFORM_INFO:
4248 if (!msr_info->host_initiated &&
4249 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4251 msr_info->data = vcpu->arch.msr_platform_info;
4253 case MSR_MISC_FEATURES_ENABLES:
4254 msr_info->data = vcpu->arch.msr_misc_features_enables;
4257 msr_info->data = vcpu->arch.msr_hwcr;
4259 #ifdef CONFIG_X86_64
4261 if (!msr_info->host_initiated &&
4262 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4265 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4267 case MSR_IA32_XFD_ERR:
4268 if (!msr_info->host_initiated &&
4269 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4272 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4276 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4277 return kvm_pmu_get_msr(vcpu, msr_info);
4280 * Userspace is allowed to read MSRs that KVM reports as
4281 * to-be-saved, even if an MSR isn't fully supported.
4283 if (msr_info->host_initiated &&
4284 kvm_is_msr_to_save(msr_info->index)) {
4289 return KVM_MSR_RET_INVALID;
4293 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4296 * Read or write a bunch of msrs. All parameters are kernel addresses.
4298 * @return number of msrs set successfully.
4300 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4301 struct kvm_msr_entry *entries,
4302 int (*do_msr)(struct kvm_vcpu *vcpu,
4303 unsigned index, u64 *data))
4307 for (i = 0; i < msrs->nmsrs; ++i)
4308 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4315 * Read or write a bunch of msrs. Parameters are user addresses.
4317 * @return number of msrs set successfully.
4319 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4320 int (*do_msr)(struct kvm_vcpu *vcpu,
4321 unsigned index, u64 *data),
4324 struct kvm_msrs msrs;
4325 struct kvm_msr_entry *entries;
4330 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4334 if (msrs.nmsrs >= MAX_IO_MSRS)
4337 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4338 entries = memdup_user(user_msrs->entries, size);
4339 if (IS_ERR(entries)) {
4340 r = PTR_ERR(entries);
4344 r = __msr_io(vcpu, &msrs, entries, do_msr);
4346 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4354 static inline bool kvm_can_mwait_in_guest(void)
4356 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4357 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4358 boot_cpu_has(X86_FEATURE_ARAT);
4361 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4362 struct kvm_cpuid2 __user *cpuid_arg)
4364 struct kvm_cpuid2 cpuid;
4368 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4371 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4376 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4382 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4387 case KVM_CAP_IRQCHIP:
4389 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4390 case KVM_CAP_SET_TSS_ADDR:
4391 case KVM_CAP_EXT_CPUID:
4392 case KVM_CAP_EXT_EMUL_CPUID:
4393 case KVM_CAP_CLOCKSOURCE:
4395 case KVM_CAP_NOP_IO_DELAY:
4396 case KVM_CAP_MP_STATE:
4397 case KVM_CAP_SYNC_MMU:
4398 case KVM_CAP_USER_NMI:
4399 case KVM_CAP_REINJECT_CONTROL:
4400 case KVM_CAP_IRQ_INJECT_STATUS:
4401 case KVM_CAP_IOEVENTFD:
4402 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4404 case KVM_CAP_PIT_STATE2:
4405 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4406 case KVM_CAP_VCPU_EVENTS:
4407 case KVM_CAP_HYPERV:
4408 case KVM_CAP_HYPERV_VAPIC:
4409 case KVM_CAP_HYPERV_SPIN:
4410 case KVM_CAP_HYPERV_SYNIC:
4411 case KVM_CAP_HYPERV_SYNIC2:
4412 case KVM_CAP_HYPERV_VP_INDEX:
4413 case KVM_CAP_HYPERV_EVENTFD:
4414 case KVM_CAP_HYPERV_TLBFLUSH:
4415 case KVM_CAP_HYPERV_SEND_IPI:
4416 case KVM_CAP_HYPERV_CPUID:
4417 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4418 case KVM_CAP_SYS_HYPERV_CPUID:
4419 case KVM_CAP_PCI_SEGMENT:
4420 case KVM_CAP_DEBUGREGS:
4421 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4423 case KVM_CAP_ASYNC_PF:
4424 case KVM_CAP_ASYNC_PF_INT:
4425 case KVM_CAP_GET_TSC_KHZ:
4426 case KVM_CAP_KVMCLOCK_CTRL:
4427 case KVM_CAP_READONLY_MEM:
4428 case KVM_CAP_HYPERV_TIME:
4429 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4430 case KVM_CAP_TSC_DEADLINE_TIMER:
4431 case KVM_CAP_DISABLE_QUIRKS:
4432 case KVM_CAP_SET_BOOT_CPU_ID:
4433 case KVM_CAP_SPLIT_IRQCHIP:
4434 case KVM_CAP_IMMEDIATE_EXIT:
4435 case KVM_CAP_PMU_EVENT_FILTER:
4436 case KVM_CAP_PMU_EVENT_MASKED_EVENTS:
4437 case KVM_CAP_GET_MSR_FEATURES:
4438 case KVM_CAP_MSR_PLATFORM_INFO:
4439 case KVM_CAP_EXCEPTION_PAYLOAD:
4440 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
4441 case KVM_CAP_SET_GUEST_DEBUG:
4442 case KVM_CAP_LAST_CPU:
4443 case KVM_CAP_X86_USER_SPACE_MSR:
4444 case KVM_CAP_X86_MSR_FILTER:
4445 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4446 #ifdef CONFIG_X86_SGX_KVM
4447 case KVM_CAP_SGX_ATTRIBUTE:
4449 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4450 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4451 case KVM_CAP_SREGS2:
4452 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4453 case KVM_CAP_VCPU_ATTRIBUTES:
4454 case KVM_CAP_SYS_ATTRIBUTES:
4456 case KVM_CAP_ENABLE_CAP:
4457 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
4460 case KVM_CAP_EXIT_HYPERCALL:
4461 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4463 case KVM_CAP_SET_GUEST_DEBUG2:
4464 return KVM_GUESTDBG_VALID_MASK;
4465 #ifdef CONFIG_KVM_XEN
4466 case KVM_CAP_XEN_HVM:
4467 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4468 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4469 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4470 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL |
4471 KVM_XEN_HVM_CONFIG_EVTCHN_SEND;
4472 if (sched_info_on())
4473 r |= KVM_XEN_HVM_CONFIG_RUNSTATE |
4474 KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG;
4477 case KVM_CAP_SYNC_REGS:
4478 r = KVM_SYNC_X86_VALID_FIELDS;
4480 case KVM_CAP_ADJUST_CLOCK:
4481 r = KVM_CLOCK_VALID_FLAGS;
4483 case KVM_CAP_X86_DISABLE_EXITS:
4484 r = KVM_X86_DISABLE_EXITS_PAUSE;
4486 if (!mitigate_smt_rsb) {
4487 r |= KVM_X86_DISABLE_EXITS_HLT |
4488 KVM_X86_DISABLE_EXITS_CSTATE;
4490 if (kvm_can_mwait_in_guest())
4491 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4494 case KVM_CAP_X86_SMM:
4495 if (!IS_ENABLED(CONFIG_KVM_SMM))
4498 /* SMBASE is usually relocated above 1M on modern chipsets,
4499 * and SMM handlers might indeed rely on 4G segment limits,
4500 * so do not report SMM to be available if real mode is
4501 * emulated via vm86 mode. Still, do not go to great lengths
4502 * to avoid userspace's usage of the feature, because it is a
4503 * fringe case that is not enabled except via specific settings
4504 * of the module parameters.
4506 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4508 case KVM_CAP_NR_VCPUS:
4509 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4511 case KVM_CAP_MAX_VCPUS:
4514 case KVM_CAP_MAX_VCPU_ID:
4515 r = KVM_MAX_VCPU_IDS;
4517 case KVM_CAP_PV_MMU: /* obsolete */
4521 r = KVM_MAX_MCE_BANKS;
4524 r = boot_cpu_has(X86_FEATURE_XSAVE);
4526 case KVM_CAP_TSC_CONTROL:
4527 case KVM_CAP_VM_TSC_CONTROL:
4528 r = kvm_caps.has_tsc_control;
4530 case KVM_CAP_X2APIC_API:
4531 r = KVM_X2APIC_API_VALID_FLAGS;
4533 case KVM_CAP_NESTED_STATE:
4534 r = kvm_x86_ops.nested_ops->get_state ?
4535 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4537 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4538 r = kvm_x86_ops.enable_l2_tlb_flush != NULL;
4540 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4541 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4543 case KVM_CAP_SMALLER_MAXPHYADDR:
4544 r = (int) allow_smaller_maxphyaddr;
4546 case KVM_CAP_STEAL_TIME:
4547 r = sched_info_on();
4549 case KVM_CAP_X86_BUS_LOCK_EXIT:
4550 if (kvm_caps.has_bus_lock_exit)
4551 r = KVM_BUS_LOCK_DETECTION_OFF |
4552 KVM_BUS_LOCK_DETECTION_EXIT;
4556 case KVM_CAP_XSAVE2: {
4557 u64 guest_perm = xstate_get_guest_group_perm();
4559 r = xstate_required_size(kvm_caps.supported_xcr0 & guest_perm, false);
4560 if (r < sizeof(struct kvm_xsave))
4561 r = sizeof(struct kvm_xsave);
4564 case KVM_CAP_PMU_CAPABILITY:
4565 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4567 case KVM_CAP_DISABLE_QUIRKS2:
4568 r = KVM_X86_VALID_QUIRKS;
4570 case KVM_CAP_X86_NOTIFY_VMEXIT:
4571 r = kvm_caps.has_notify_vmexit;
4579 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4581 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4583 if ((u64)(unsigned long)uaddr != attr->addr)
4584 return ERR_PTR_USR(-EFAULT);
4588 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4590 u64 __user *uaddr = kvm_get_attr_addr(attr);
4596 return PTR_ERR(uaddr);
4598 switch (attr->attr) {
4599 case KVM_X86_XCOMP_GUEST_SUPP:
4600 if (put_user(kvm_caps.supported_xcr0, uaddr))
4609 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4614 switch (attr->attr) {
4615 case KVM_X86_XCOMP_GUEST_SUPP:
4622 long kvm_arch_dev_ioctl(struct file *filp,
4623 unsigned int ioctl, unsigned long arg)
4625 void __user *argp = (void __user *)arg;
4629 case KVM_GET_MSR_INDEX_LIST: {
4630 struct kvm_msr_list __user *user_msr_list = argp;
4631 struct kvm_msr_list msr_list;
4635 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4638 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4639 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4642 if (n < msr_list.nmsrs)
4645 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4646 num_msrs_to_save * sizeof(u32)))
4648 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4650 num_emulated_msrs * sizeof(u32)))
4655 case KVM_GET_SUPPORTED_CPUID:
4656 case KVM_GET_EMULATED_CPUID: {
4657 struct kvm_cpuid2 __user *cpuid_arg = argp;
4658 struct kvm_cpuid2 cpuid;
4661 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4664 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4670 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4675 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4677 if (copy_to_user(argp, &kvm_caps.supported_mce_cap,
4678 sizeof(kvm_caps.supported_mce_cap)))
4682 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4683 struct kvm_msr_list __user *user_msr_list = argp;
4684 struct kvm_msr_list msr_list;
4688 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4691 msr_list.nmsrs = num_msr_based_features;
4692 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4695 if (n < msr_list.nmsrs)
4698 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4699 num_msr_based_features * sizeof(u32)))
4705 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4707 case KVM_GET_SUPPORTED_HV_CPUID:
4708 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4710 case KVM_GET_DEVICE_ATTR: {
4711 struct kvm_device_attr attr;
4713 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4715 r = kvm_x86_dev_get_attr(&attr);
4718 case KVM_HAS_DEVICE_ATTR: {
4719 struct kvm_device_attr attr;
4721 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4723 r = kvm_x86_dev_has_attr(&attr);
4734 static void wbinvd_ipi(void *garbage)
4739 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4741 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4744 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4746 /* Address WBINVD may be executed by guest */
4747 if (need_emulate_wbinvd(vcpu)) {
4748 if (static_call(kvm_x86_has_wbinvd_exit)())
4749 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4750 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4751 smp_call_function_single(vcpu->cpu,
4752 wbinvd_ipi, NULL, 1);
4755 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4757 /* Save host pkru register if supported */
4758 vcpu->arch.host_pkru = read_pkru();
4760 /* Apply any externally detected TSC adjustments (due to suspend) */
4761 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4762 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4763 vcpu->arch.tsc_offset_adjustment = 0;
4764 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4767 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4768 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4769 rdtsc() - vcpu->arch.last_host_tsc;
4771 mark_tsc_unstable("KVM discovered backwards TSC");
4773 if (kvm_check_tsc_unstable()) {
4774 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4775 vcpu->arch.last_guest_tsc);
4776 kvm_vcpu_write_tsc_offset(vcpu, offset);
4777 vcpu->arch.tsc_catchup = 1;
4780 if (kvm_lapic_hv_timer_in_use(vcpu))
4781 kvm_lapic_restart_hv_timer(vcpu);
4784 * On a host with synchronized TSC, there is no need to update
4785 * kvmclock on vcpu->cpu migration
4787 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4788 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4789 if (vcpu->cpu != cpu)
4790 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4794 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4797 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4799 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
4800 struct kvm_steal_time __user *st;
4801 struct kvm_memslots *slots;
4802 static const u8 preempted = KVM_VCPU_PREEMPTED;
4803 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
4806 * The vCPU can be marked preempted if and only if the VM-Exit was on
4807 * an instruction boundary and will not trigger guest emulation of any
4808 * kind (see vcpu_run). Vendor specific code controls (conservatively)
4809 * when this is true, for example allowing the vCPU to be marked
4810 * preempted if and only if the VM-Exit was due to a host interrupt.
4812 if (!vcpu->arch.at_instruction_boundary) {
4813 vcpu->stat.preemption_other++;
4817 vcpu->stat.preemption_reported++;
4818 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4821 if (vcpu->arch.st.preempted)
4824 /* This happens on process exit */
4825 if (unlikely(current->mm != vcpu->kvm->mm))
4828 slots = kvm_memslots(vcpu->kvm);
4830 if (unlikely(slots->generation != ghc->generation ||
4832 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
4835 st = (struct kvm_steal_time __user *)ghc->hva;
4836 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
4838 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
4839 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4841 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
4844 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4848 if (vcpu->preempted) {
4849 if (!vcpu->arch.guest_state_protected)
4850 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4853 * Take the srcu lock as memslots will be accessed to check the gfn
4854 * cache generation against the memslots generation.
4856 idx = srcu_read_lock(&vcpu->kvm->srcu);
4857 if (kvm_xen_msr_enabled(vcpu->kvm))
4858 kvm_xen_runstate_set_preempted(vcpu);
4860 kvm_steal_time_set_preempted(vcpu);
4861 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4864 static_call(kvm_x86_vcpu_put)(vcpu);
4865 vcpu->arch.last_host_tsc = rdtsc();
4868 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4869 struct kvm_lapic_state *s)
4871 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
4873 return kvm_apic_get_state(vcpu, s);
4876 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4877 struct kvm_lapic_state *s)
4881 r = kvm_apic_set_state(vcpu, s);
4884 update_cr8_intercept(vcpu);
4889 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4892 * We can accept userspace's request for interrupt injection
4893 * as long as we have a place to store the interrupt number.
4894 * The actual injection will happen when the CPU is able to
4895 * deliver the interrupt.
4897 if (kvm_cpu_has_extint(vcpu))
4900 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4901 return (!lapic_in_kernel(vcpu) ||
4902 kvm_apic_accept_pic_intr(vcpu));
4905 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4908 * Do not cause an interrupt window exit if an exception
4909 * is pending or an event needs reinjection; userspace
4910 * might want to inject the interrupt manually using KVM_SET_REGS
4911 * or KVM_SET_SREGS. For that to work, we must be at an
4912 * instruction boundary and with no events half-injected.
4914 return (kvm_arch_interrupt_allowed(vcpu) &&
4915 kvm_cpu_accept_dm_intr(vcpu) &&
4916 !kvm_event_needs_reinjection(vcpu) &&
4917 !kvm_is_exception_pending(vcpu));
4920 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4921 struct kvm_interrupt *irq)
4923 if (irq->irq >= KVM_NR_INTERRUPTS)
4926 if (!irqchip_in_kernel(vcpu->kvm)) {
4927 kvm_queue_interrupt(vcpu, irq->irq, false);
4928 kvm_make_request(KVM_REQ_EVENT, vcpu);
4933 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4934 * fail for in-kernel 8259.
4936 if (pic_in_kernel(vcpu->kvm))
4939 if (vcpu->arch.pending_external_vector != -1)
4942 vcpu->arch.pending_external_vector = irq->irq;
4943 kvm_make_request(KVM_REQ_EVENT, vcpu);
4947 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4949 kvm_inject_nmi(vcpu);
4954 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4955 struct kvm_tpr_access_ctl *tac)
4959 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4963 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4967 unsigned bank_num = mcg_cap & 0xff, bank;
4970 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4972 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000))
4975 vcpu->arch.mcg_cap = mcg_cap;
4976 /* Init IA32_MCG_CTL to all 1s */
4977 if (mcg_cap & MCG_CTL_P)
4978 vcpu->arch.mcg_ctl = ~(u64)0;
4979 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */
4980 for (bank = 0; bank < bank_num; bank++) {
4981 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4982 if (mcg_cap & MCG_CMCI_P)
4983 vcpu->arch.mci_ctl2_banks[bank] = 0;
4986 kvm_apic_after_set_mcg_cap(vcpu);
4988 static_call(kvm_x86_setup_mce)(vcpu);
4994 * Validate this is an UCNA (uncorrectable no action) error by checking the
4995 * MCG_STATUS and MCi_STATUS registers:
4996 * - none of the bits for Machine Check Exceptions are set
4997 * - both the VAL (valid) and UC (uncorrectable) bits are set
4998 * MCI_STATUS_PCC - Processor Context Corrupted
4999 * MCI_STATUS_S - Signaled as a Machine Check Exception
5000 * MCI_STATUS_AR - Software recoverable Action Required
5002 static bool is_ucna(struct kvm_x86_mce *mce)
5004 return !mce->mcg_status &&
5005 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) &&
5006 (mce->status & MCI_STATUS_VAL) &&
5007 (mce->status & MCI_STATUS_UC);
5010 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks)
5012 u64 mcg_cap = vcpu->arch.mcg_cap;
5014 banks[1] = mce->status;
5015 banks[2] = mce->addr;
5016 banks[3] = mce->misc;
5017 vcpu->arch.mcg_status = mce->mcg_status;
5019 if (!(mcg_cap & MCG_CMCI_P) ||
5020 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))
5023 if (lapic_in_kernel(vcpu))
5024 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI);
5029 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
5030 struct kvm_x86_mce *mce)
5032 u64 mcg_cap = vcpu->arch.mcg_cap;
5033 unsigned bank_num = mcg_cap & 0xff;
5034 u64 *banks = vcpu->arch.mce_banks;
5036 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
5039 banks += array_index_nospec(4 * mce->bank, 4 * bank_num);
5042 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks);
5045 * if IA32_MCG_CTL is not all 1s, the uncorrected error
5046 * reporting is disabled
5048 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
5049 vcpu->arch.mcg_ctl != ~(u64)0)
5052 * if IA32_MCi_CTL is not all 1s, the uncorrected error
5053 * reporting is disabled for the bank
5055 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
5057 if (mce->status & MCI_STATUS_UC) {
5058 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
5059 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
5060 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5063 if (banks[1] & MCI_STATUS_VAL)
5064 mce->status |= MCI_STATUS_OVER;
5065 banks[2] = mce->addr;
5066 banks[3] = mce->misc;
5067 vcpu->arch.mcg_status = mce->mcg_status;
5068 banks[1] = mce->status;
5069 kvm_queue_exception(vcpu, MC_VECTOR);
5070 } else if (!(banks[1] & MCI_STATUS_VAL)
5071 || !(banks[1] & MCI_STATUS_UC)) {
5072 if (banks[1] & MCI_STATUS_VAL)
5073 mce->status |= MCI_STATUS_OVER;
5074 banks[2] = mce->addr;
5075 banks[3] = mce->misc;
5076 banks[1] = mce->status;
5078 banks[1] |= MCI_STATUS_OVER;
5082 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
5083 struct kvm_vcpu_events *events)
5085 struct kvm_queued_exception *ex;
5089 #ifdef CONFIG_KVM_SMM
5090 if (kvm_check_request(KVM_REQ_SMI, vcpu))
5095 * KVM's ABI only allows for one exception to be migrated. Luckily,
5096 * the only time there can be two queued exceptions is if there's a
5097 * non-exiting _injected_ exception, and a pending exiting exception.
5098 * In that case, ignore the VM-Exiting exception as it's an extension
5099 * of the injected exception.
5101 if (vcpu->arch.exception_vmexit.pending &&
5102 !vcpu->arch.exception.pending &&
5103 !vcpu->arch.exception.injected)
5104 ex = &vcpu->arch.exception_vmexit;
5106 ex = &vcpu->arch.exception;
5109 * In guest mode, payload delivery should be deferred if the exception
5110 * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1
5111 * intercepts #PF, ditto for DR6 and #DBs. If the per-VM capability,
5112 * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not
5113 * propagate the payload and so it cannot be safely deferred. Deliver
5114 * the payload if the capability hasn't been requested.
5116 if (!vcpu->kvm->arch.exception_payload_enabled &&
5117 ex->pending && ex->has_payload)
5118 kvm_deliver_exception_payload(vcpu, ex);
5120 memset(events, 0, sizeof(*events));
5123 * The API doesn't provide the instruction length for software
5124 * exceptions, so don't report them. As long as the guest RIP
5125 * isn't advanced, we should expect to encounter the exception
5128 if (!kvm_exception_is_soft(ex->vector)) {
5129 events->exception.injected = ex->injected;
5130 events->exception.pending = ex->pending;
5132 * For ABI compatibility, deliberately conflate
5133 * pending and injected exceptions when
5134 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
5136 if (!vcpu->kvm->arch.exception_payload_enabled)
5137 events->exception.injected |= ex->pending;
5139 events->exception.nr = ex->vector;
5140 events->exception.has_error_code = ex->has_error_code;
5141 events->exception.error_code = ex->error_code;
5142 events->exception_has_payload = ex->has_payload;
5143 events->exception_payload = ex->payload;
5145 events->interrupt.injected =
5146 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
5147 events->interrupt.nr = vcpu->arch.interrupt.nr;
5148 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
5150 events->nmi.injected = vcpu->arch.nmi_injected;
5151 events->nmi.pending = vcpu->arch.nmi_pending != 0;
5152 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
5154 /* events->sipi_vector is never valid when reporting to user space */
5156 #ifdef CONFIG_KVM_SMM
5157 events->smi.smm = is_smm(vcpu);
5158 events->smi.pending = vcpu->arch.smi_pending;
5159 events->smi.smm_inside_nmi =
5160 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
5162 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
5164 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
5165 | KVM_VCPUEVENT_VALID_SHADOW
5166 | KVM_VCPUEVENT_VALID_SMM);
5167 if (vcpu->kvm->arch.exception_payload_enabled)
5168 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5169 if (vcpu->kvm->arch.triple_fault_event) {
5170 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5171 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5175 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
5176 struct kvm_vcpu_events *events)
5178 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
5179 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
5180 | KVM_VCPUEVENT_VALID_SHADOW
5181 | KVM_VCPUEVENT_VALID_SMM
5182 | KVM_VCPUEVENT_VALID_PAYLOAD
5183 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT))
5186 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5187 if (!vcpu->kvm->arch.exception_payload_enabled)
5189 if (events->exception.pending)
5190 events->exception.injected = 0;
5192 events->exception_has_payload = 0;
5194 events->exception.pending = 0;
5195 events->exception_has_payload = 0;
5198 if ((events->exception.injected || events->exception.pending) &&
5199 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
5202 /* INITs are latched while in SMM */
5203 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
5204 (events->smi.smm || events->smi.pending) &&
5205 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
5211 * Flag that userspace is stuffing an exception, the next KVM_RUN will
5212 * morph the exception to a VM-Exit if appropriate. Do this only for
5213 * pending exceptions, already-injected exceptions are not subject to
5214 * intercpetion. Note, userspace that conflates pending and injected
5215 * is hosed, and will incorrectly convert an injected exception into a
5216 * pending exception, which in turn may cause a spurious VM-Exit.
5218 vcpu->arch.exception_from_userspace = events->exception.pending;
5220 vcpu->arch.exception_vmexit.pending = false;
5222 vcpu->arch.exception.injected = events->exception.injected;
5223 vcpu->arch.exception.pending = events->exception.pending;
5224 vcpu->arch.exception.vector = events->exception.nr;
5225 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
5226 vcpu->arch.exception.error_code = events->exception.error_code;
5227 vcpu->arch.exception.has_payload = events->exception_has_payload;
5228 vcpu->arch.exception.payload = events->exception_payload;
5230 vcpu->arch.interrupt.injected = events->interrupt.injected;
5231 vcpu->arch.interrupt.nr = events->interrupt.nr;
5232 vcpu->arch.interrupt.soft = events->interrupt.soft;
5233 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
5234 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
5235 events->interrupt.shadow);
5237 vcpu->arch.nmi_injected = events->nmi.injected;
5238 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
5239 vcpu->arch.nmi_pending = events->nmi.pending;
5240 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
5242 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
5243 lapic_in_kernel(vcpu))
5244 vcpu->arch.apic->sipi_vector = events->sipi_vector;
5246 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
5247 #ifdef CONFIG_KVM_SMM
5248 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
5249 kvm_leave_nested(vcpu);
5250 kvm_smm_changed(vcpu, events->smi.smm);
5253 vcpu->arch.smi_pending = events->smi.pending;
5255 if (events->smi.smm) {
5256 if (events->smi.smm_inside_nmi)
5257 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
5259 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
5263 if (events->smi.smm || events->smi.pending ||
5264 events->smi.smm_inside_nmi)
5268 if (lapic_in_kernel(vcpu)) {
5269 if (events->smi.latched_init)
5270 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5272 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5276 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5277 if (!vcpu->kvm->arch.triple_fault_event)
5279 if (events->triple_fault.pending)
5280 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5282 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5285 kvm_make_request(KVM_REQ_EVENT, vcpu);
5290 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
5291 struct kvm_debugregs *dbgregs)
5295 memset(dbgregs, 0, sizeof(*dbgregs));
5296 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
5297 kvm_get_dr(vcpu, 6, &val);
5299 dbgregs->dr7 = vcpu->arch.dr7;
5302 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5303 struct kvm_debugregs *dbgregs)
5308 if (!kvm_dr6_valid(dbgregs->dr6))
5310 if (!kvm_dr7_valid(dbgregs->dr7))
5313 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5314 kvm_update_dr0123(vcpu);
5315 vcpu->arch.dr6 = dbgregs->dr6;
5316 vcpu->arch.dr7 = dbgregs->dr7;
5317 kvm_update_dr7(vcpu);
5322 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5323 struct kvm_xsave *guest_xsave)
5325 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5328 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5329 guest_xsave->region,
5330 sizeof(guest_xsave->region),
5334 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5335 u8 *state, unsigned int size)
5337 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5340 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5341 state, size, vcpu->arch.pkru);
5344 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5345 struct kvm_xsave *guest_xsave)
5347 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5350 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5351 guest_xsave->region,
5352 kvm_caps.supported_xcr0,
5356 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5357 struct kvm_xcrs *guest_xcrs)
5359 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5360 guest_xcrs->nr_xcrs = 0;
5364 guest_xcrs->nr_xcrs = 1;
5365 guest_xcrs->flags = 0;
5366 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5367 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5370 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5371 struct kvm_xcrs *guest_xcrs)
5375 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5378 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5381 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5382 /* Only support XCR0 currently */
5383 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5384 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5385 guest_xcrs->xcrs[i].value);
5394 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5395 * stopped by the hypervisor. This function will be called from the host only.
5396 * EINVAL is returned when the host attempts to set the flag for a guest that
5397 * does not support pv clocks.
5399 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5401 if (!vcpu->arch.pv_time.active)
5403 vcpu->arch.pvclock_set_guest_stopped_request = true;
5404 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5408 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5409 struct kvm_device_attr *attr)
5413 switch (attr->attr) {
5414 case KVM_VCPU_TSC_OFFSET:
5424 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5425 struct kvm_device_attr *attr)
5427 u64 __user *uaddr = kvm_get_attr_addr(attr);
5431 return PTR_ERR(uaddr);
5433 switch (attr->attr) {
5434 case KVM_VCPU_TSC_OFFSET:
5436 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5447 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5448 struct kvm_device_attr *attr)
5450 u64 __user *uaddr = kvm_get_attr_addr(attr);
5451 struct kvm *kvm = vcpu->kvm;
5455 return PTR_ERR(uaddr);
5457 switch (attr->attr) {
5458 case KVM_VCPU_TSC_OFFSET: {
5459 u64 offset, tsc, ns;
5460 unsigned long flags;
5464 if (get_user(offset, uaddr))
5467 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5469 matched = (vcpu->arch.virtual_tsc_khz &&
5470 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5471 kvm->arch.last_tsc_offset == offset);
5473 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5474 ns = get_kvmclock_base_ns();
5476 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5477 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5489 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5493 struct kvm_device_attr attr;
5496 if (copy_from_user(&attr, argp, sizeof(attr)))
5499 if (attr.group != KVM_VCPU_TSC_CTRL)
5503 case KVM_HAS_DEVICE_ATTR:
5504 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5506 case KVM_GET_DEVICE_ATTR:
5507 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5509 case KVM_SET_DEVICE_ATTR:
5510 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5517 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5518 struct kvm_enable_cap *cap)
5521 uint16_t vmcs_version;
5522 void __user *user_ptr;
5528 case KVM_CAP_HYPERV_SYNIC2:
5533 case KVM_CAP_HYPERV_SYNIC:
5534 if (!irqchip_in_kernel(vcpu->kvm))
5536 return kvm_hv_activate_synic(vcpu, cap->cap ==
5537 KVM_CAP_HYPERV_SYNIC2);
5538 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5539 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5541 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5543 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5544 if (copy_to_user(user_ptr, &vmcs_version,
5545 sizeof(vmcs_version)))
5549 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5550 if (!kvm_x86_ops.enable_l2_tlb_flush)
5553 return static_call(kvm_x86_enable_l2_tlb_flush)(vcpu);
5555 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5556 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5558 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5559 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5560 if (vcpu->arch.pv_cpuid.enforce)
5561 kvm_update_pv_runtime(vcpu);
5569 long kvm_arch_vcpu_ioctl(struct file *filp,
5570 unsigned int ioctl, unsigned long arg)
5572 struct kvm_vcpu *vcpu = filp->private_data;
5573 void __user *argp = (void __user *)arg;
5576 struct kvm_sregs2 *sregs2;
5577 struct kvm_lapic_state *lapic;
5578 struct kvm_xsave *xsave;
5579 struct kvm_xcrs *xcrs;
5587 case KVM_GET_LAPIC: {
5589 if (!lapic_in_kernel(vcpu))
5591 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5592 GFP_KERNEL_ACCOUNT);
5597 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5601 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5606 case KVM_SET_LAPIC: {
5608 if (!lapic_in_kernel(vcpu))
5610 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5611 if (IS_ERR(u.lapic)) {
5612 r = PTR_ERR(u.lapic);
5616 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5619 case KVM_INTERRUPT: {
5620 struct kvm_interrupt irq;
5623 if (copy_from_user(&irq, argp, sizeof(irq)))
5625 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5629 r = kvm_vcpu_ioctl_nmi(vcpu);
5633 r = kvm_inject_smi(vcpu);
5636 case KVM_SET_CPUID: {
5637 struct kvm_cpuid __user *cpuid_arg = argp;
5638 struct kvm_cpuid cpuid;
5641 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5643 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5646 case KVM_SET_CPUID2: {
5647 struct kvm_cpuid2 __user *cpuid_arg = argp;
5648 struct kvm_cpuid2 cpuid;
5651 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5653 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5654 cpuid_arg->entries);
5657 case KVM_GET_CPUID2: {
5658 struct kvm_cpuid2 __user *cpuid_arg = argp;
5659 struct kvm_cpuid2 cpuid;
5662 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5664 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5665 cpuid_arg->entries);
5669 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5674 case KVM_GET_MSRS: {
5675 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5676 r = msr_io(vcpu, argp, do_get_msr, 1);
5677 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5680 case KVM_SET_MSRS: {
5681 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5682 r = msr_io(vcpu, argp, do_set_msr, 0);
5683 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5686 case KVM_TPR_ACCESS_REPORTING: {
5687 struct kvm_tpr_access_ctl tac;
5690 if (copy_from_user(&tac, argp, sizeof(tac)))
5692 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5696 if (copy_to_user(argp, &tac, sizeof(tac)))
5701 case KVM_SET_VAPIC_ADDR: {
5702 struct kvm_vapic_addr va;
5706 if (!lapic_in_kernel(vcpu))
5709 if (copy_from_user(&va, argp, sizeof(va)))
5711 idx = srcu_read_lock(&vcpu->kvm->srcu);
5712 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5713 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5716 case KVM_X86_SETUP_MCE: {
5720 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5722 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5725 case KVM_X86_SET_MCE: {
5726 struct kvm_x86_mce mce;
5729 if (copy_from_user(&mce, argp, sizeof(mce)))
5731 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5734 case KVM_GET_VCPU_EVENTS: {
5735 struct kvm_vcpu_events events;
5737 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5740 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5745 case KVM_SET_VCPU_EVENTS: {
5746 struct kvm_vcpu_events events;
5749 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5752 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5755 case KVM_GET_DEBUGREGS: {
5756 struct kvm_debugregs dbgregs;
5758 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5761 if (copy_to_user(argp, &dbgregs,
5762 sizeof(struct kvm_debugregs)))
5767 case KVM_SET_DEBUGREGS: {
5768 struct kvm_debugregs dbgregs;
5771 if (copy_from_user(&dbgregs, argp,
5772 sizeof(struct kvm_debugregs)))
5775 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
5778 case KVM_GET_XSAVE: {
5780 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
5783 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
5788 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
5791 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
5796 case KVM_SET_XSAVE: {
5797 int size = vcpu->arch.guest_fpu.uabi_size;
5799 u.xsave = memdup_user(argp, size);
5800 if (IS_ERR(u.xsave)) {
5801 r = PTR_ERR(u.xsave);
5805 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
5809 case KVM_GET_XSAVE2: {
5810 int size = vcpu->arch.guest_fpu.uabi_size;
5812 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
5817 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
5820 if (copy_to_user(argp, u.xsave, size))
5827 case KVM_GET_XCRS: {
5828 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
5833 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
5836 if (copy_to_user(argp, u.xcrs,
5837 sizeof(struct kvm_xcrs)))
5842 case KVM_SET_XCRS: {
5843 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
5844 if (IS_ERR(u.xcrs)) {
5845 r = PTR_ERR(u.xcrs);
5849 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
5852 case KVM_SET_TSC_KHZ: {
5856 user_tsc_khz = (u32)arg;
5858 if (kvm_caps.has_tsc_control &&
5859 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
5862 if (user_tsc_khz == 0)
5863 user_tsc_khz = tsc_khz;
5865 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
5870 case KVM_GET_TSC_KHZ: {
5871 r = vcpu->arch.virtual_tsc_khz;
5874 case KVM_KVMCLOCK_CTRL: {
5875 r = kvm_set_guest_paused(vcpu);
5878 case KVM_ENABLE_CAP: {
5879 struct kvm_enable_cap cap;
5882 if (copy_from_user(&cap, argp, sizeof(cap)))
5884 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
5887 case KVM_GET_NESTED_STATE: {
5888 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5892 if (!kvm_x86_ops.nested_ops->get_state)
5895 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
5897 if (get_user(user_data_size, &user_kvm_nested_state->size))
5900 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
5905 if (r > user_data_size) {
5906 if (put_user(r, &user_kvm_nested_state->size))
5916 case KVM_SET_NESTED_STATE: {
5917 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5918 struct kvm_nested_state kvm_state;
5922 if (!kvm_x86_ops.nested_ops->set_state)
5926 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5930 if (kvm_state.size < sizeof(kvm_state))
5933 if (kvm_state.flags &
5934 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5935 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5936 | KVM_STATE_NESTED_GIF_SET))
5939 /* nested_run_pending implies guest_mode. */
5940 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5941 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5944 idx = srcu_read_lock(&vcpu->kvm->srcu);
5945 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5946 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5949 case KVM_GET_SUPPORTED_HV_CPUID:
5950 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5952 #ifdef CONFIG_KVM_XEN
5953 case KVM_XEN_VCPU_GET_ATTR: {
5954 struct kvm_xen_vcpu_attr xva;
5957 if (copy_from_user(&xva, argp, sizeof(xva)))
5959 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
5960 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
5964 case KVM_XEN_VCPU_SET_ATTR: {
5965 struct kvm_xen_vcpu_attr xva;
5968 if (copy_from_user(&xva, argp, sizeof(xva)))
5970 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
5974 case KVM_GET_SREGS2: {
5975 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
5979 __get_sregs2(vcpu, u.sregs2);
5981 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
5986 case KVM_SET_SREGS2: {
5987 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
5988 if (IS_ERR(u.sregs2)) {
5989 r = PTR_ERR(u.sregs2);
5993 r = __set_sregs2(vcpu, u.sregs2);
5996 case KVM_HAS_DEVICE_ATTR:
5997 case KVM_GET_DEVICE_ATTR:
5998 case KVM_SET_DEVICE_ATTR:
5999 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
6011 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
6013 return VM_FAULT_SIGBUS;
6016 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
6020 if (addr > (unsigned int)(-3 * PAGE_SIZE))
6022 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
6026 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
6029 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
6032 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
6033 unsigned long kvm_nr_mmu_pages)
6035 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
6038 mutex_lock(&kvm->slots_lock);
6040 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
6041 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
6043 mutex_unlock(&kvm->slots_lock);
6047 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6049 struct kvm_pic *pic = kvm->arch.vpic;
6053 switch (chip->chip_id) {
6054 case KVM_IRQCHIP_PIC_MASTER:
6055 memcpy(&chip->chip.pic, &pic->pics[0],
6056 sizeof(struct kvm_pic_state));
6058 case KVM_IRQCHIP_PIC_SLAVE:
6059 memcpy(&chip->chip.pic, &pic->pics[1],
6060 sizeof(struct kvm_pic_state));
6062 case KVM_IRQCHIP_IOAPIC:
6063 kvm_get_ioapic(kvm, &chip->chip.ioapic);
6072 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6074 struct kvm_pic *pic = kvm->arch.vpic;
6078 switch (chip->chip_id) {
6079 case KVM_IRQCHIP_PIC_MASTER:
6080 spin_lock(&pic->lock);
6081 memcpy(&pic->pics[0], &chip->chip.pic,
6082 sizeof(struct kvm_pic_state));
6083 spin_unlock(&pic->lock);
6085 case KVM_IRQCHIP_PIC_SLAVE:
6086 spin_lock(&pic->lock);
6087 memcpy(&pic->pics[1], &chip->chip.pic,
6088 sizeof(struct kvm_pic_state));
6089 spin_unlock(&pic->lock);
6091 case KVM_IRQCHIP_IOAPIC:
6092 kvm_set_ioapic(kvm, &chip->chip.ioapic);
6098 kvm_pic_update_irq(pic);
6102 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6104 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
6106 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
6108 mutex_lock(&kps->lock);
6109 memcpy(ps, &kps->channels, sizeof(*ps));
6110 mutex_unlock(&kps->lock);
6114 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6117 struct kvm_pit *pit = kvm->arch.vpit;
6119 mutex_lock(&pit->pit_state.lock);
6120 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
6121 for (i = 0; i < 3; i++)
6122 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
6123 mutex_unlock(&pit->pit_state.lock);
6127 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6129 mutex_lock(&kvm->arch.vpit->pit_state.lock);
6130 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
6131 sizeof(ps->channels));
6132 ps->flags = kvm->arch.vpit->pit_state.flags;
6133 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
6134 memset(&ps->reserved, 0, sizeof(ps->reserved));
6138 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6142 u32 prev_legacy, cur_legacy;
6143 struct kvm_pit *pit = kvm->arch.vpit;
6145 mutex_lock(&pit->pit_state.lock);
6146 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
6147 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
6148 if (!prev_legacy && cur_legacy)
6150 memcpy(&pit->pit_state.channels, &ps->channels,
6151 sizeof(pit->pit_state.channels));
6152 pit->pit_state.flags = ps->flags;
6153 for (i = 0; i < 3; i++)
6154 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
6156 mutex_unlock(&pit->pit_state.lock);
6160 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
6161 struct kvm_reinject_control *control)
6163 struct kvm_pit *pit = kvm->arch.vpit;
6165 /* pit->pit_state.lock was overloaded to prevent userspace from getting
6166 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
6167 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
6169 mutex_lock(&pit->pit_state.lock);
6170 kvm_pit_set_reinject(pit, control->pit_reinject);
6171 mutex_unlock(&pit->pit_state.lock);
6176 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
6180 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
6181 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
6182 * on all VM-Exits, thus we only need to kick running vCPUs to force a
6185 struct kvm_vcpu *vcpu;
6188 kvm_for_each_vcpu(i, vcpu, kvm)
6189 kvm_vcpu_kick(vcpu);
6192 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
6195 if (!irqchip_in_kernel(kvm))
6198 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
6199 irq_event->irq, irq_event->level,
6204 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
6205 struct kvm_enable_cap *cap)
6213 case KVM_CAP_DISABLE_QUIRKS2:
6215 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
6218 case KVM_CAP_DISABLE_QUIRKS:
6219 kvm->arch.disabled_quirks = cap->args[0];
6222 case KVM_CAP_SPLIT_IRQCHIP: {
6223 mutex_lock(&kvm->lock);
6225 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
6226 goto split_irqchip_unlock;
6228 if (irqchip_in_kernel(kvm))
6229 goto split_irqchip_unlock;
6230 if (kvm->created_vcpus)
6231 goto split_irqchip_unlock;
6232 r = kvm_setup_empty_irq_routing(kvm);
6234 goto split_irqchip_unlock;
6235 /* Pairs with irqchip_in_kernel. */
6237 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
6238 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
6239 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6241 split_irqchip_unlock:
6242 mutex_unlock(&kvm->lock);
6245 case KVM_CAP_X2APIC_API:
6247 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
6250 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
6251 kvm->arch.x2apic_format = true;
6252 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
6253 kvm->arch.x2apic_broadcast_quirk_disabled = true;
6257 case KVM_CAP_X86_DISABLE_EXITS:
6259 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
6262 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
6263 kvm->arch.pause_in_guest = true;
6265 #define SMT_RSB_MSG "This processor is affected by the Cross-Thread Return Predictions vulnerability. " \
6266 "KVM_CAP_X86_DISABLE_EXITS should only be used with SMT disabled or trusted guests."
6268 if (!mitigate_smt_rsb) {
6269 if (boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible() &&
6270 (cap->args[0] & ~KVM_X86_DISABLE_EXITS_PAUSE))
6271 pr_warn_once(SMT_RSB_MSG);
6273 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
6274 kvm_can_mwait_in_guest())
6275 kvm->arch.mwait_in_guest = true;
6276 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
6277 kvm->arch.hlt_in_guest = true;
6278 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
6279 kvm->arch.cstate_in_guest = true;
6284 case KVM_CAP_MSR_PLATFORM_INFO:
6285 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
6288 case KVM_CAP_EXCEPTION_PAYLOAD:
6289 kvm->arch.exception_payload_enabled = cap->args[0];
6292 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
6293 kvm->arch.triple_fault_event = cap->args[0];
6296 case KVM_CAP_X86_USER_SPACE_MSR:
6298 if (cap->args[0] & ~KVM_MSR_EXIT_REASON_VALID_MASK)
6300 kvm->arch.user_space_msr_mask = cap->args[0];
6303 case KVM_CAP_X86_BUS_LOCK_EXIT:
6305 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
6308 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6309 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6312 if (kvm_caps.has_bus_lock_exit &&
6313 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6314 kvm->arch.bus_lock_detection_enabled = true;
6317 #ifdef CONFIG_X86_SGX_KVM
6318 case KVM_CAP_SGX_ATTRIBUTE: {
6319 unsigned long allowed_attributes = 0;
6321 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6325 /* KVM only supports the PROVISIONKEY privileged attribute. */
6326 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6327 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6328 kvm->arch.sgx_provisioning_allowed = true;
6334 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6336 if (!kvm_x86_ops.vm_copy_enc_context_from)
6339 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6341 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6343 if (!kvm_x86_ops.vm_move_enc_context_from)
6346 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6348 case KVM_CAP_EXIT_HYPERCALL:
6349 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6353 kvm->arch.hypercall_exit_enabled = cap->args[0];
6356 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6358 if (cap->args[0] & ~1)
6360 kvm->arch.exit_on_emulation_error = cap->args[0];
6363 case KVM_CAP_PMU_CAPABILITY:
6365 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6368 mutex_lock(&kvm->lock);
6369 if (!kvm->created_vcpus) {
6370 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6373 mutex_unlock(&kvm->lock);
6375 case KVM_CAP_MAX_VCPU_ID:
6377 if (cap->args[0] > KVM_MAX_VCPU_IDS)
6380 mutex_lock(&kvm->lock);
6381 if (kvm->arch.max_vcpu_ids == cap->args[0]) {
6383 } else if (!kvm->arch.max_vcpu_ids) {
6384 kvm->arch.max_vcpu_ids = cap->args[0];
6387 mutex_unlock(&kvm->lock);
6389 case KVM_CAP_X86_NOTIFY_VMEXIT:
6391 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS)
6393 if (!kvm_caps.has_notify_vmexit)
6395 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED))
6397 mutex_lock(&kvm->lock);
6398 if (!kvm->created_vcpus) {
6399 kvm->arch.notify_window = cap->args[0] >> 32;
6400 kvm->arch.notify_vmexit_flags = (u32)cap->args[0];
6403 mutex_unlock(&kvm->lock);
6405 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
6409 * Since the risk of disabling NX hugepages is a guest crashing
6410 * the system, ensure the userspace process has permission to
6411 * reboot the system.
6413 * Note that unlike the reboot() syscall, the process must have
6414 * this capability in the root namespace because exposing
6415 * /dev/kvm into a container does not limit the scope of the
6416 * iTLB multihit bug to that container. In other words,
6417 * this must use capable(), not ns_capable().
6419 if (!capable(CAP_SYS_BOOT)) {
6427 mutex_lock(&kvm->lock);
6428 if (!kvm->created_vcpus) {
6429 kvm->arch.disable_nx_huge_pages = true;
6432 mutex_unlock(&kvm->lock);
6441 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6443 struct kvm_x86_msr_filter *msr_filter;
6445 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6449 msr_filter->default_allow = default_allow;
6453 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6460 for (i = 0; i < msr_filter->count; i++)
6461 kfree(msr_filter->ranges[i].bitmap);
6466 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6467 struct kvm_msr_filter_range *user_range)
6469 unsigned long *bitmap = NULL;
6472 if (!user_range->nmsrs)
6475 if (user_range->flags & ~KVM_MSR_FILTER_RANGE_VALID_MASK)
6478 if (!user_range->flags)
6481 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6482 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6485 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6487 return PTR_ERR(bitmap);
6489 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6490 .flags = user_range->flags,
6491 .base = user_range->base,
6492 .nmsrs = user_range->nmsrs,
6496 msr_filter->count++;
6500 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm,
6501 struct kvm_msr_filter *filter)
6503 struct kvm_x86_msr_filter *new_filter, *old_filter;
6509 if (filter->flags & ~KVM_MSR_FILTER_VALID_MASK)
6512 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++)
6513 empty &= !filter->ranges[i].nmsrs;
6515 default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY);
6516 if (empty && !default_allow)
6519 new_filter = kvm_alloc_msr_filter(default_allow);
6523 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) {
6524 r = kvm_add_msr_filter(new_filter, &filter->ranges[i]);
6526 kvm_free_msr_filter(new_filter);
6531 mutex_lock(&kvm->lock);
6532 old_filter = rcu_replace_pointer(kvm->arch.msr_filter, new_filter,
6533 mutex_is_locked(&kvm->lock));
6534 mutex_unlock(&kvm->lock);
6535 synchronize_srcu(&kvm->srcu);
6537 kvm_free_msr_filter(old_filter);
6539 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6544 #ifdef CONFIG_KVM_COMPAT
6545 /* for KVM_X86_SET_MSR_FILTER */
6546 struct kvm_msr_filter_range_compat {
6553 struct kvm_msr_filter_compat {
6555 struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES];
6558 #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat)
6560 long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl,
6563 void __user *argp = (void __user *)arg;
6564 struct kvm *kvm = filp->private_data;
6568 case KVM_X86_SET_MSR_FILTER_COMPAT: {
6569 struct kvm_msr_filter __user *user_msr_filter = argp;
6570 struct kvm_msr_filter_compat filter_compat;
6571 struct kvm_msr_filter filter;
6574 if (copy_from_user(&filter_compat, user_msr_filter,
6575 sizeof(filter_compat)))
6578 filter.flags = filter_compat.flags;
6579 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6580 struct kvm_msr_filter_range_compat *cr;
6582 cr = &filter_compat.ranges[i];
6583 filter.ranges[i] = (struct kvm_msr_filter_range) {
6587 .bitmap = (__u8 *)(ulong)cr->bitmap,
6591 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
6600 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6601 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6603 struct kvm_vcpu *vcpu;
6607 mutex_lock(&kvm->lock);
6608 kvm_for_each_vcpu(i, vcpu, kvm) {
6609 if (!vcpu->arch.pv_time.active)
6612 ret = kvm_set_guest_paused(vcpu);
6614 kvm_err("Failed to pause guest VCPU%d: %d\n",
6615 vcpu->vcpu_id, ret);
6619 mutex_unlock(&kvm->lock);
6621 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6624 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6627 case PM_HIBERNATION_PREPARE:
6628 case PM_SUSPEND_PREPARE:
6629 return kvm_arch_suspend_notifier(kvm);
6634 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6636 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6638 struct kvm_clock_data data = { 0 };
6640 get_kvmclock(kvm, &data);
6641 if (copy_to_user(argp, &data, sizeof(data)))
6647 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6649 struct kvm_arch *ka = &kvm->arch;
6650 struct kvm_clock_data data;
6653 if (copy_from_user(&data, argp, sizeof(data)))
6657 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6658 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6660 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6663 kvm_hv_request_tsc_page_update(kvm);
6664 kvm_start_pvclock_update(kvm);
6665 pvclock_update_vm_gtod_copy(kvm);
6668 * This pairs with kvm_guest_time_update(): when masterclock is
6669 * in use, we use master_kernel_ns + kvmclock_offset to set
6670 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6671 * is slightly ahead) here we risk going negative on unsigned
6672 * 'system_time' when 'data.clock' is very small.
6674 if (data.flags & KVM_CLOCK_REALTIME) {
6675 u64 now_real_ns = ktime_get_real_ns();
6678 * Avoid stepping the kvmclock backwards.
6680 if (now_real_ns > data.realtime)
6681 data.clock += now_real_ns - data.realtime;
6684 if (ka->use_master_clock)
6685 now_raw_ns = ka->master_kernel_ns;
6687 now_raw_ns = get_kvmclock_base_ns();
6688 ka->kvmclock_offset = data.clock - now_raw_ns;
6689 kvm_end_pvclock_update(kvm);
6693 int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
6695 struct kvm *kvm = filp->private_data;
6696 void __user *argp = (void __user *)arg;
6699 * This union makes it completely explicit to gcc-3.x
6700 * that these two variables' stack usage should be
6701 * combined, not added together.
6704 struct kvm_pit_state ps;
6705 struct kvm_pit_state2 ps2;
6706 struct kvm_pit_config pit_config;
6710 case KVM_SET_TSS_ADDR:
6711 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6713 case KVM_SET_IDENTITY_MAP_ADDR: {
6716 mutex_lock(&kvm->lock);
6718 if (kvm->created_vcpus)
6719 goto set_identity_unlock;
6721 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6722 goto set_identity_unlock;
6723 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6724 set_identity_unlock:
6725 mutex_unlock(&kvm->lock);
6728 case KVM_SET_NR_MMU_PAGES:
6729 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6731 case KVM_CREATE_IRQCHIP: {
6732 mutex_lock(&kvm->lock);
6735 if (irqchip_in_kernel(kvm))
6736 goto create_irqchip_unlock;
6739 if (kvm->created_vcpus)
6740 goto create_irqchip_unlock;
6742 r = kvm_pic_init(kvm);
6744 goto create_irqchip_unlock;
6746 r = kvm_ioapic_init(kvm);
6748 kvm_pic_destroy(kvm);
6749 goto create_irqchip_unlock;
6752 r = kvm_setup_default_irq_routing(kvm);
6754 kvm_ioapic_destroy(kvm);
6755 kvm_pic_destroy(kvm);
6756 goto create_irqchip_unlock;
6758 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6760 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
6761 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6762 create_irqchip_unlock:
6763 mutex_unlock(&kvm->lock);
6766 case KVM_CREATE_PIT:
6767 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
6769 case KVM_CREATE_PIT2:
6771 if (copy_from_user(&u.pit_config, argp,
6772 sizeof(struct kvm_pit_config)))
6775 mutex_lock(&kvm->lock);
6778 goto create_pit_unlock;
6780 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
6784 mutex_unlock(&kvm->lock);
6786 case KVM_GET_IRQCHIP: {
6787 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6788 struct kvm_irqchip *chip;
6790 chip = memdup_user(argp, sizeof(*chip));
6797 if (!irqchip_kernel(kvm))
6798 goto get_irqchip_out;
6799 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
6801 goto get_irqchip_out;
6803 if (copy_to_user(argp, chip, sizeof(*chip)))
6804 goto get_irqchip_out;
6810 case KVM_SET_IRQCHIP: {
6811 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6812 struct kvm_irqchip *chip;
6814 chip = memdup_user(argp, sizeof(*chip));
6821 if (!irqchip_kernel(kvm))
6822 goto set_irqchip_out;
6823 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
6830 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
6833 if (!kvm->arch.vpit)
6835 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
6839 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
6846 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
6848 mutex_lock(&kvm->lock);
6850 if (!kvm->arch.vpit)
6852 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
6854 mutex_unlock(&kvm->lock);
6857 case KVM_GET_PIT2: {
6859 if (!kvm->arch.vpit)
6861 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
6865 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
6870 case KVM_SET_PIT2: {
6872 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
6874 mutex_lock(&kvm->lock);
6876 if (!kvm->arch.vpit)
6878 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
6880 mutex_unlock(&kvm->lock);
6883 case KVM_REINJECT_CONTROL: {
6884 struct kvm_reinject_control control;
6886 if (copy_from_user(&control, argp, sizeof(control)))
6889 if (!kvm->arch.vpit)
6891 r = kvm_vm_ioctl_reinject(kvm, &control);
6894 case KVM_SET_BOOT_CPU_ID:
6896 mutex_lock(&kvm->lock);
6897 if (kvm->created_vcpus)
6900 kvm->arch.bsp_vcpu_id = arg;
6901 mutex_unlock(&kvm->lock);
6903 #ifdef CONFIG_KVM_XEN
6904 case KVM_XEN_HVM_CONFIG: {
6905 struct kvm_xen_hvm_config xhc;
6907 if (copy_from_user(&xhc, argp, sizeof(xhc)))
6909 r = kvm_xen_hvm_config(kvm, &xhc);
6912 case KVM_XEN_HVM_GET_ATTR: {
6913 struct kvm_xen_hvm_attr xha;
6916 if (copy_from_user(&xha, argp, sizeof(xha)))
6918 r = kvm_xen_hvm_get_attr(kvm, &xha);
6919 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
6923 case KVM_XEN_HVM_SET_ATTR: {
6924 struct kvm_xen_hvm_attr xha;
6927 if (copy_from_user(&xha, argp, sizeof(xha)))
6929 r = kvm_xen_hvm_set_attr(kvm, &xha);
6932 case KVM_XEN_HVM_EVTCHN_SEND: {
6933 struct kvm_irq_routing_xen_evtchn uxe;
6936 if (copy_from_user(&uxe, argp, sizeof(uxe)))
6938 r = kvm_xen_hvm_evtchn_send(kvm, &uxe);
6943 r = kvm_vm_ioctl_set_clock(kvm, argp);
6946 r = kvm_vm_ioctl_get_clock(kvm, argp);
6948 case KVM_SET_TSC_KHZ: {
6952 user_tsc_khz = (u32)arg;
6954 if (kvm_caps.has_tsc_control &&
6955 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
6958 if (user_tsc_khz == 0)
6959 user_tsc_khz = tsc_khz;
6961 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz);
6966 case KVM_GET_TSC_KHZ: {
6967 r = READ_ONCE(kvm->arch.default_tsc_khz);
6970 case KVM_MEMORY_ENCRYPT_OP: {
6972 if (!kvm_x86_ops.mem_enc_ioctl)
6975 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
6978 case KVM_MEMORY_ENCRYPT_REG_REGION: {
6979 struct kvm_enc_region region;
6982 if (copy_from_user(®ion, argp, sizeof(region)))
6986 if (!kvm_x86_ops.mem_enc_register_region)
6989 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
6992 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
6993 struct kvm_enc_region region;
6996 if (copy_from_user(®ion, argp, sizeof(region)))
7000 if (!kvm_x86_ops.mem_enc_unregister_region)
7003 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
7006 case KVM_HYPERV_EVENTFD: {
7007 struct kvm_hyperv_eventfd hvevfd;
7010 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
7012 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
7015 case KVM_SET_PMU_EVENT_FILTER:
7016 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
7018 case KVM_X86_SET_MSR_FILTER: {
7019 struct kvm_msr_filter __user *user_msr_filter = argp;
7020 struct kvm_msr_filter filter;
7022 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
7025 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
7035 static void kvm_probe_msr_to_save(u32 msr_index)
7039 if (rdmsr_safe(msr_index, &dummy[0], &dummy[1]))
7043 * Even MSRs that are valid in the host may not be exposed to guests in
7046 switch (msr_index) {
7047 case MSR_IA32_BNDCFGS:
7048 if (!kvm_mpx_supported())
7052 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
7053 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
7056 case MSR_IA32_UMWAIT_CONTROL:
7057 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
7060 case MSR_IA32_RTIT_CTL:
7061 case MSR_IA32_RTIT_STATUS:
7062 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
7065 case MSR_IA32_RTIT_CR3_MATCH:
7066 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7067 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
7070 case MSR_IA32_RTIT_OUTPUT_BASE:
7071 case MSR_IA32_RTIT_OUTPUT_MASK:
7072 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7073 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
7074 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
7077 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
7078 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7079 (msr_index - MSR_IA32_RTIT_ADDR0_A >=
7080 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2))
7083 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX:
7084 if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >=
7085 kvm_pmu_cap.num_counters_gp)
7088 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX:
7089 if (msr_index - MSR_ARCH_PERFMON_EVENTSEL0 >=
7090 kvm_pmu_cap.num_counters_gp)
7093 case MSR_ARCH_PERFMON_FIXED_CTR0 ... MSR_ARCH_PERFMON_FIXED_CTR_MAX:
7094 if (msr_index - MSR_ARCH_PERFMON_FIXED_CTR0 >=
7095 kvm_pmu_cap.num_counters_fixed)
7099 case MSR_IA32_XFD_ERR:
7100 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
7107 msrs_to_save[num_msrs_to_save++] = msr_index;
7110 static void kvm_init_msr_list(void)
7114 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
7115 "Please update the fixed PMCs in msrs_to_save_pmu[]");
7117 num_msrs_to_save = 0;
7118 num_emulated_msrs = 0;
7119 num_msr_based_features = 0;
7121 for (i = 0; i < ARRAY_SIZE(msrs_to_save_base); i++)
7122 kvm_probe_msr_to_save(msrs_to_save_base[i]);
7125 for (i = 0; i < ARRAY_SIZE(msrs_to_save_pmu); i++)
7126 kvm_probe_msr_to_save(msrs_to_save_pmu[i]);
7129 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
7130 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
7133 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
7136 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
7137 struct kvm_msr_entry msr;
7139 msr.index = msr_based_features_all[i];
7140 if (kvm_get_msr_feature(&msr))
7143 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
7147 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
7155 if (!(lapic_in_kernel(vcpu) &&
7156 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
7157 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
7168 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
7175 if (!(lapic_in_kernel(vcpu) &&
7176 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
7178 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
7180 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
7190 void kvm_set_segment(struct kvm_vcpu *vcpu,
7191 struct kvm_segment *var, int seg)
7193 static_call(kvm_x86_set_segment)(vcpu, var, seg);
7196 void kvm_get_segment(struct kvm_vcpu *vcpu,
7197 struct kvm_segment *var, int seg)
7199 static_call(kvm_x86_get_segment)(vcpu, var, seg);
7202 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
7203 struct x86_exception *exception)
7205 struct kvm_mmu *mmu = vcpu->arch.mmu;
7208 BUG_ON(!mmu_is_nested(vcpu));
7210 /* NPT walks are always user-walks */
7211 access |= PFERR_USER_MASK;
7212 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
7217 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
7218 struct x86_exception *exception)
7220 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7222 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7223 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7225 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
7227 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
7228 struct x86_exception *exception)
7230 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7232 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7233 access |= PFERR_WRITE_MASK;
7234 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7236 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
7238 /* uses this to access any guest's mapped memory without checking CPL */
7239 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
7240 struct x86_exception *exception)
7242 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7244 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
7247 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7248 struct kvm_vcpu *vcpu, u64 access,
7249 struct x86_exception *exception)
7251 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7253 int r = X86EMUL_CONTINUE;
7256 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7257 unsigned offset = addr & (PAGE_SIZE-1);
7258 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
7261 if (gpa == INVALID_GPA)
7262 return X86EMUL_PROPAGATE_FAULT;
7263 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
7266 r = X86EMUL_IO_NEEDED;
7278 /* used for instruction fetching */
7279 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
7280 gva_t addr, void *val, unsigned int bytes,
7281 struct x86_exception *exception)
7283 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7284 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7285 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7289 /* Inline kvm_read_guest_virt_helper for speed. */
7290 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
7292 if (unlikely(gpa == INVALID_GPA))
7293 return X86EMUL_PROPAGATE_FAULT;
7295 offset = addr & (PAGE_SIZE-1);
7296 if (WARN_ON(offset + bytes > PAGE_SIZE))
7297 bytes = (unsigned)PAGE_SIZE - offset;
7298 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
7300 if (unlikely(ret < 0))
7301 return X86EMUL_IO_NEEDED;
7303 return X86EMUL_CONTINUE;
7306 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
7307 gva_t addr, void *val, unsigned int bytes,
7308 struct x86_exception *exception)
7310 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7313 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
7314 * is returned, but our callers are not ready for that and they blindly
7315 * call kvm_inject_page_fault. Ensure that they at least do not leak
7316 * uninitialized kernel stack memory into cr2 and error code.
7318 memset(exception, 0, sizeof(*exception));
7319 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
7322 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
7324 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
7325 gva_t addr, void *val, unsigned int bytes,
7326 struct x86_exception *exception, bool system)
7328 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7332 access |= PFERR_IMPLICIT_ACCESS;
7333 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7334 access |= PFERR_USER_MASK;
7336 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
7339 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7340 struct kvm_vcpu *vcpu, u64 access,
7341 struct x86_exception *exception)
7343 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7345 int r = X86EMUL_CONTINUE;
7348 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7349 unsigned offset = addr & (PAGE_SIZE-1);
7350 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
7353 if (gpa == INVALID_GPA)
7354 return X86EMUL_PROPAGATE_FAULT;
7355 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
7357 r = X86EMUL_IO_NEEDED;
7369 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
7370 unsigned int bytes, struct x86_exception *exception,
7373 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7374 u64 access = PFERR_WRITE_MASK;
7377 access |= PFERR_IMPLICIT_ACCESS;
7378 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7379 access |= PFERR_USER_MASK;
7381 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7385 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
7386 unsigned int bytes, struct x86_exception *exception)
7388 /* kvm_write_guest_virt_system can pull in tons of pages. */
7389 vcpu->arch.l1tf_flush_l1d = true;
7391 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7392 PFERR_WRITE_MASK, exception);
7394 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
7396 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
7397 void *insn, int insn_len)
7399 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type,
7403 int handle_ud(struct kvm_vcpu *vcpu)
7405 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
7406 int fep_flags = READ_ONCE(force_emulation_prefix);
7407 int emul_type = EMULTYPE_TRAP_UD;
7408 char sig[5]; /* ud2; .ascii "kvm" */
7409 struct x86_exception e;
7411 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0)))
7415 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
7416 sig, sizeof(sig), &e) == 0 &&
7417 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
7418 if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF)
7419 kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF);
7420 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
7421 emul_type = EMULTYPE_TRAP_UD_FORCED;
7424 return kvm_emulate_instruction(vcpu, emul_type);
7426 EXPORT_SYMBOL_GPL(handle_ud);
7428 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7429 gpa_t gpa, bool write)
7431 /* For APIC access vmexit */
7432 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7435 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
7436 trace_vcpu_match_mmio(gva, gpa, write, true);
7443 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7444 gpa_t *gpa, struct x86_exception *exception,
7447 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7448 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7449 | (write ? PFERR_WRITE_MASK : 0);
7452 * currently PKRU is only applied to ept enabled guest so
7453 * there is no pkey in EPT page table for L1 guest or EPT
7454 * shadow page table for L2 guest.
7456 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7457 !permission_fault(vcpu, vcpu->arch.walk_mmu,
7458 vcpu->arch.mmio_access, 0, access))) {
7459 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7460 (gva & (PAGE_SIZE - 1));
7461 trace_vcpu_match_mmio(gva, *gpa, write, false);
7465 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7467 if (*gpa == INVALID_GPA)
7470 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7473 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7474 const void *val, int bytes)
7478 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7481 kvm_page_track_write(vcpu, gpa, val, bytes);
7485 struct read_write_emulator_ops {
7486 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7488 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7489 void *val, int bytes);
7490 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7491 int bytes, void *val);
7492 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7493 void *val, int bytes);
7497 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7499 if (vcpu->mmio_read_completed) {
7500 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7501 vcpu->mmio_fragments[0].gpa, val);
7502 vcpu->mmio_read_completed = 0;
7509 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7510 void *val, int bytes)
7512 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7515 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7516 void *val, int bytes)
7518 return emulator_write_phys(vcpu, gpa, val, bytes);
7521 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7523 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7524 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7527 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7528 void *val, int bytes)
7530 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7531 return X86EMUL_IO_NEEDED;
7534 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7535 void *val, int bytes)
7537 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7539 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7540 return X86EMUL_CONTINUE;
7543 static const struct read_write_emulator_ops read_emultor = {
7544 .read_write_prepare = read_prepare,
7545 .read_write_emulate = read_emulate,
7546 .read_write_mmio = vcpu_mmio_read,
7547 .read_write_exit_mmio = read_exit_mmio,
7550 static const struct read_write_emulator_ops write_emultor = {
7551 .read_write_emulate = write_emulate,
7552 .read_write_mmio = write_mmio,
7553 .read_write_exit_mmio = write_exit_mmio,
7557 static int emulator_read_write_onepage(unsigned long addr, void *val,
7559 struct x86_exception *exception,
7560 struct kvm_vcpu *vcpu,
7561 const struct read_write_emulator_ops *ops)
7565 bool write = ops->write;
7566 struct kvm_mmio_fragment *frag;
7567 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7570 * If the exit was due to a NPF we may already have a GPA.
7571 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7572 * Note, this cannot be used on string operations since string
7573 * operation using rep will only have the initial GPA from the NPF
7576 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7577 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7578 gpa = ctxt->gpa_val;
7579 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7581 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7583 return X86EMUL_PROPAGATE_FAULT;
7586 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7587 return X86EMUL_CONTINUE;
7590 * Is this MMIO handled locally?
7592 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7593 if (handled == bytes)
7594 return X86EMUL_CONTINUE;
7600 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7601 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7605 return X86EMUL_CONTINUE;
7608 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7610 void *val, unsigned int bytes,
7611 struct x86_exception *exception,
7612 const struct read_write_emulator_ops *ops)
7614 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7618 if (ops->read_write_prepare &&
7619 ops->read_write_prepare(vcpu, val, bytes))
7620 return X86EMUL_CONTINUE;
7622 vcpu->mmio_nr_fragments = 0;
7624 /* Crossing a page boundary? */
7625 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7628 now = -addr & ~PAGE_MASK;
7629 rc = emulator_read_write_onepage(addr, val, now, exception,
7632 if (rc != X86EMUL_CONTINUE)
7635 if (ctxt->mode != X86EMUL_MODE_PROT64)
7641 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7643 if (rc != X86EMUL_CONTINUE)
7646 if (!vcpu->mmio_nr_fragments)
7649 gpa = vcpu->mmio_fragments[0].gpa;
7651 vcpu->mmio_needed = 1;
7652 vcpu->mmio_cur_fragment = 0;
7654 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7655 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7656 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7657 vcpu->run->mmio.phys_addr = gpa;
7659 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7662 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7666 struct x86_exception *exception)
7668 return emulator_read_write(ctxt, addr, val, bytes,
7669 exception, &read_emultor);
7672 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7676 struct x86_exception *exception)
7678 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7679 exception, &write_emultor);
7682 #define emulator_try_cmpxchg_user(t, ptr, old, new) \
7683 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t))
7685 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7690 struct x86_exception *exception)
7692 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7698 /* guests cmpxchg8b have to be emulated atomically */
7699 if (bytes > 8 || (bytes & (bytes - 1)))
7702 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7704 if (gpa == INVALID_GPA ||
7705 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7709 * Emulate the atomic as a straight write to avoid #AC if SLD is
7710 * enabled in the host and the access splits a cache line.
7712 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7713 page_line_mask = ~(cache_line_size() - 1);
7715 page_line_mask = PAGE_MASK;
7717 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7720 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa));
7721 if (kvm_is_error_hva(hva))
7724 hva += offset_in_page(gpa);
7728 r = emulator_try_cmpxchg_user(u8, hva, old, new);
7731 r = emulator_try_cmpxchg_user(u16, hva, old, new);
7734 r = emulator_try_cmpxchg_user(u32, hva, old, new);
7737 r = emulator_try_cmpxchg_user(u64, hva, old, new);
7744 return X86EMUL_UNHANDLEABLE;
7746 return X86EMUL_CMPXCHG_FAILED;
7748 kvm_page_track_write(vcpu, gpa, new, bytes);
7750 return X86EMUL_CONTINUE;
7753 pr_warn_once("emulating exchange as write\n");
7755 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
7758 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
7759 unsigned short port, void *data,
7760 unsigned int count, bool in)
7765 WARN_ON_ONCE(vcpu->arch.pio.count);
7766 for (i = 0; i < count; i++) {
7768 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data);
7770 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data);
7777 * Userspace must have unregistered the device while PIO
7778 * was running. Drop writes / read as 0.
7781 memset(data, 0, size * (count - i));
7790 vcpu->arch.pio.port = port;
7791 vcpu->arch.pio.in = in;
7792 vcpu->arch.pio.count = count;
7793 vcpu->arch.pio.size = size;
7796 memset(vcpu->arch.pio_data, 0, size * count);
7798 memcpy(vcpu->arch.pio_data, data, size * count);
7800 vcpu->run->exit_reason = KVM_EXIT_IO;
7801 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
7802 vcpu->run->io.size = size;
7803 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
7804 vcpu->run->io.count = count;
7805 vcpu->run->io.port = port;
7809 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7810 unsigned short port, void *val, unsigned int count)
7812 int r = emulator_pio_in_out(vcpu, size, port, val, count, true);
7814 trace_kvm_pio(KVM_PIO_IN, port, size, count, val);
7819 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
7821 int size = vcpu->arch.pio.size;
7822 unsigned int count = vcpu->arch.pio.count;
7823 memcpy(val, vcpu->arch.pio_data, size * count);
7824 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
7825 vcpu->arch.pio.count = 0;
7828 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
7829 int size, unsigned short port, void *val,
7832 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7833 if (vcpu->arch.pio.count) {
7835 * Complete a previous iteration that required userspace I/O.
7836 * Note, @count isn't guaranteed to match pio.count as userspace
7837 * can modify ECX before rerunning the vCPU. Ignore any such
7838 * shenanigans as KVM doesn't support modifying the rep count,
7839 * and the emulator ensures @count doesn't overflow the buffer.
7841 complete_emulator_pio_in(vcpu, val);
7845 return emulator_pio_in(vcpu, size, port, val, count);
7848 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
7849 unsigned short port, const void *val,
7852 trace_kvm_pio(KVM_PIO_OUT, port, size, count, val);
7853 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
7856 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
7857 int size, unsigned short port,
7858 const void *val, unsigned int count)
7860 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
7863 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
7865 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
7868 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
7870 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
7873 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
7875 if (!need_emulate_wbinvd(vcpu))
7876 return X86EMUL_CONTINUE;
7878 if (static_call(kvm_x86_has_wbinvd_exit)()) {
7879 int cpu = get_cpu();
7881 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
7882 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
7883 wbinvd_ipi, NULL, 1);
7885 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
7888 return X86EMUL_CONTINUE;
7891 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
7893 kvm_emulate_wbinvd_noskip(vcpu);
7894 return kvm_skip_emulated_instruction(vcpu);
7896 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
7900 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
7902 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
7905 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
7906 unsigned long *dest)
7908 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
7911 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
7912 unsigned long value)
7915 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
7918 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
7920 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
7923 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
7925 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7926 unsigned long value;
7930 value = kvm_read_cr0(vcpu);
7933 value = vcpu->arch.cr2;
7936 value = kvm_read_cr3(vcpu);
7939 value = kvm_read_cr4(vcpu);
7942 value = kvm_get_cr8(vcpu);
7945 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7952 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
7954 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7959 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
7962 vcpu->arch.cr2 = val;
7965 res = kvm_set_cr3(vcpu, val);
7968 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
7971 res = kvm_set_cr8(vcpu, val);
7974 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7981 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
7983 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
7986 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7988 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
7991 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7993 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
7996 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7998 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
8001 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8003 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
8006 static unsigned long emulator_get_cached_segment_base(
8007 struct x86_emulate_ctxt *ctxt, int seg)
8009 return get_segment_base(emul_to_vcpu(ctxt), seg);
8012 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
8013 struct desc_struct *desc, u32 *base3,
8016 struct kvm_segment var;
8018 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
8019 *selector = var.selector;
8022 memset(desc, 0, sizeof(*desc));
8030 set_desc_limit(desc, var.limit);
8031 set_desc_base(desc, (unsigned long)var.base);
8032 #ifdef CONFIG_X86_64
8034 *base3 = var.base >> 32;
8036 desc->type = var.type;
8038 desc->dpl = var.dpl;
8039 desc->p = var.present;
8040 desc->avl = var.avl;
8048 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
8049 struct desc_struct *desc, u32 base3,
8052 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8053 struct kvm_segment var;
8055 var.selector = selector;
8056 var.base = get_desc_base(desc);
8057 #ifdef CONFIG_X86_64
8058 var.base |= ((u64)base3) << 32;
8060 var.limit = get_desc_limit(desc);
8062 var.limit = (var.limit << 12) | 0xfff;
8063 var.type = desc->type;
8064 var.dpl = desc->dpl;
8069 var.avl = desc->avl;
8070 var.present = desc->p;
8071 var.unusable = !var.present;
8074 kvm_set_segment(vcpu, &var, seg);
8078 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8079 u32 msr_index, u64 *pdata)
8081 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8084 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
8086 return X86EMUL_UNHANDLEABLE;
8089 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
8090 complete_emulated_rdmsr, r))
8091 return X86EMUL_IO_NEEDED;
8093 trace_kvm_msr_read_ex(msr_index);
8094 return X86EMUL_PROPAGATE_FAULT;
8097 trace_kvm_msr_read(msr_index, *pdata);
8098 return X86EMUL_CONTINUE;
8101 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8102 u32 msr_index, u64 data)
8104 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8107 r = kvm_set_msr_with_filter(vcpu, msr_index, data);
8109 return X86EMUL_UNHANDLEABLE;
8112 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
8113 complete_emulated_msr_access, r))
8114 return X86EMUL_IO_NEEDED;
8116 trace_kvm_msr_write_ex(msr_index, data);
8117 return X86EMUL_PROPAGATE_FAULT;
8120 trace_kvm_msr_write(msr_index, data);
8121 return X86EMUL_CONTINUE;
8124 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
8125 u32 msr_index, u64 *pdata)
8127 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
8130 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
8133 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
8138 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
8139 u32 pmc, u64 *pdata)
8141 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
8144 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
8146 emul_to_vcpu(ctxt)->arch.halt_request = 1;
8149 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8150 struct x86_instruction_info *info,
8151 enum x86_intercept_stage stage)
8153 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
8157 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
8158 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
8161 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
8164 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
8166 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
8169 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
8171 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
8174 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
8176 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
8179 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
8181 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
8184 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
8186 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
8189 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
8191 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
8194 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
8196 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
8199 static bool emulator_is_smm(struct x86_emulate_ctxt *ctxt)
8201 return is_smm(emul_to_vcpu(ctxt));
8204 static bool emulator_is_guest_mode(struct x86_emulate_ctxt *ctxt)
8206 return is_guest_mode(emul_to_vcpu(ctxt));
8209 #ifndef CONFIG_KVM_SMM
8210 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt)
8213 return X86EMUL_UNHANDLEABLE;
8217 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
8219 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
8222 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
8224 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
8227 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt)
8229 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm;
8231 if (!kvm->vm_bugged)
8235 static const struct x86_emulate_ops emulate_ops = {
8236 .vm_bugged = emulator_vm_bugged,
8237 .read_gpr = emulator_read_gpr,
8238 .write_gpr = emulator_write_gpr,
8239 .read_std = emulator_read_std,
8240 .write_std = emulator_write_std,
8241 .fetch = kvm_fetch_guest_virt,
8242 .read_emulated = emulator_read_emulated,
8243 .write_emulated = emulator_write_emulated,
8244 .cmpxchg_emulated = emulator_cmpxchg_emulated,
8245 .invlpg = emulator_invlpg,
8246 .pio_in_emulated = emulator_pio_in_emulated,
8247 .pio_out_emulated = emulator_pio_out_emulated,
8248 .get_segment = emulator_get_segment,
8249 .set_segment = emulator_set_segment,
8250 .get_cached_segment_base = emulator_get_cached_segment_base,
8251 .get_gdt = emulator_get_gdt,
8252 .get_idt = emulator_get_idt,
8253 .set_gdt = emulator_set_gdt,
8254 .set_idt = emulator_set_idt,
8255 .get_cr = emulator_get_cr,
8256 .set_cr = emulator_set_cr,
8257 .cpl = emulator_get_cpl,
8258 .get_dr = emulator_get_dr,
8259 .set_dr = emulator_set_dr,
8260 .set_msr_with_filter = emulator_set_msr_with_filter,
8261 .get_msr_with_filter = emulator_get_msr_with_filter,
8262 .get_msr = emulator_get_msr,
8263 .check_pmc = emulator_check_pmc,
8264 .read_pmc = emulator_read_pmc,
8265 .halt = emulator_halt,
8266 .wbinvd = emulator_wbinvd,
8267 .fix_hypercall = emulator_fix_hypercall,
8268 .intercept = emulator_intercept,
8269 .get_cpuid = emulator_get_cpuid,
8270 .guest_has_long_mode = emulator_guest_has_long_mode,
8271 .guest_has_movbe = emulator_guest_has_movbe,
8272 .guest_has_fxsr = emulator_guest_has_fxsr,
8273 .guest_has_rdpid = emulator_guest_has_rdpid,
8274 .set_nmi_mask = emulator_set_nmi_mask,
8275 .is_smm = emulator_is_smm,
8276 .is_guest_mode = emulator_is_guest_mode,
8277 .leave_smm = emulator_leave_smm,
8278 .triple_fault = emulator_triple_fault,
8279 .set_xcr = emulator_set_xcr,
8282 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
8284 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8286 * an sti; sti; sequence only disable interrupts for the first
8287 * instruction. So, if the last instruction, be it emulated or
8288 * not, left the system with the INT_STI flag enabled, it
8289 * means that the last instruction is an sti. We should not
8290 * leave the flag on in this case. The same goes for mov ss
8292 if (int_shadow & mask)
8294 if (unlikely(int_shadow || mask)) {
8295 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
8297 kvm_make_request(KVM_REQ_EVENT, vcpu);
8301 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
8303 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8305 if (ctxt->exception.vector == PF_VECTOR)
8306 kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
8307 else if (ctxt->exception.error_code_valid)
8308 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
8309 ctxt->exception.error_code);
8311 kvm_queue_exception(vcpu, ctxt->exception.vector);
8314 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
8316 struct x86_emulate_ctxt *ctxt;
8318 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
8320 pr_err("failed to allocate vcpu's emulator\n");
8325 ctxt->ops = &emulate_ops;
8326 vcpu->arch.emulate_ctxt = ctxt;
8331 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
8333 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8336 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
8338 ctxt->gpa_available = false;
8339 ctxt->eflags = kvm_get_rflags(vcpu);
8340 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
8342 ctxt->eip = kvm_rip_read(vcpu);
8343 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
8344 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
8345 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
8346 cs_db ? X86EMUL_MODE_PROT32 :
8347 X86EMUL_MODE_PROT16;
8348 ctxt->interruptibility = 0;
8349 ctxt->have_exception = false;
8350 ctxt->exception.vector = -1;
8351 ctxt->perm_ok = false;
8353 init_decode_cache(ctxt);
8354 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8357 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
8359 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8362 init_emulate_ctxt(vcpu);
8366 ctxt->_eip = ctxt->eip + inc_eip;
8367 ret = emulate_int_real(ctxt, irq);
8369 if (ret != X86EMUL_CONTINUE) {
8370 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8372 ctxt->eip = ctxt->_eip;
8373 kvm_rip_write(vcpu, ctxt->eip);
8374 kvm_set_rflags(vcpu, ctxt->eflags);
8377 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
8379 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8380 u8 ndata, u8 *insn_bytes, u8 insn_size)
8382 struct kvm_run *run = vcpu->run;
8387 * Zero the whole array used to retrieve the exit info, as casting to
8388 * u32 for select entries will leave some chunks uninitialized.
8390 memset(&info, 0, sizeof(info));
8392 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
8393 &info[2], (u32 *)&info[3],
8396 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8397 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
8400 * There's currently space for 13 entries, but 5 are used for the exit
8401 * reason and info. Restrict to 4 to reduce the maintenance burden
8402 * when expanding kvm_run.emulation_failure in the future.
8404 if (WARN_ON_ONCE(ndata > 4))
8407 /* Always include the flags as a 'data' entry. */
8409 run->emulation_failure.flags = 0;
8412 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
8413 sizeof(run->emulation_failure.insn_bytes) != 16));
8415 run->emulation_failure.flags |=
8416 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
8417 run->emulation_failure.insn_size = insn_size;
8418 memset(run->emulation_failure.insn_bytes, 0x90,
8419 sizeof(run->emulation_failure.insn_bytes));
8420 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
8423 memcpy(&run->internal.data[info_start], info, sizeof(info));
8424 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
8425 ndata * sizeof(data[0]));
8427 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8430 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8432 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8434 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8435 ctxt->fetch.end - ctxt->fetch.data);
8438 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8441 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8443 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8445 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8447 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8449 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8451 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8453 struct kvm *kvm = vcpu->kvm;
8455 ++vcpu->stat.insn_emulation_fail;
8456 trace_kvm_emulate_insn_failed(vcpu);
8458 if (emulation_type & EMULTYPE_VMWARE_GP) {
8459 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8463 if (kvm->arch.exit_on_emulation_error ||
8464 (emulation_type & EMULTYPE_SKIP)) {
8465 prepare_emulation_ctxt_failure_exit(vcpu);
8469 kvm_queue_exception(vcpu, UD_VECTOR);
8471 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8472 prepare_emulation_ctxt_failure_exit(vcpu);
8479 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8482 gpa_t gpa = cr2_or_gpa;
8485 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8488 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8489 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8492 if (!vcpu->arch.mmu->root_role.direct) {
8494 * Write permission should be allowed since only
8495 * write access need to be emulated.
8497 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8500 * If the mapping is invalid in guest, let cpu retry
8501 * it to generate fault.
8503 if (gpa == INVALID_GPA)
8508 * Do not retry the unhandleable instruction if it faults on the
8509 * readonly host memory, otherwise it will goto a infinite loop:
8510 * retry instruction -> write #PF -> emulation fail -> retry
8511 * instruction -> ...
8513 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8516 * If the instruction failed on the error pfn, it can not be fixed,
8517 * report the error to userspace.
8519 if (is_error_noslot_pfn(pfn))
8522 kvm_release_pfn_clean(pfn);
8524 /* The instructions are well-emulated on direct mmu. */
8525 if (vcpu->arch.mmu->root_role.direct) {
8526 unsigned int indirect_shadow_pages;
8528 write_lock(&vcpu->kvm->mmu_lock);
8529 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8530 write_unlock(&vcpu->kvm->mmu_lock);
8532 if (indirect_shadow_pages)
8533 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8539 * if emulation was due to access to shadowed page table
8540 * and it failed try to unshadow page and re-enter the
8541 * guest to let CPU execute the instruction.
8543 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8546 * If the access faults on its page table, it can not
8547 * be fixed by unprotecting shadow page and it should
8548 * be reported to userspace.
8550 return !(emulation_type & EMULTYPE_WRITE_PF_TO_SP);
8553 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8554 gpa_t cr2_or_gpa, int emulation_type)
8556 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8557 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8559 last_retry_eip = vcpu->arch.last_retry_eip;
8560 last_retry_addr = vcpu->arch.last_retry_addr;
8563 * If the emulation is caused by #PF and it is non-page_table
8564 * writing instruction, it means the VM-EXIT is caused by shadow
8565 * page protected, we can zap the shadow page and retry this
8566 * instruction directly.
8568 * Note: if the guest uses a non-page-table modifying instruction
8569 * on the PDE that points to the instruction, then we will unmap
8570 * the instruction and go to an infinite loop. So, we cache the
8571 * last retried eip and the last fault address, if we meet the eip
8572 * and the address again, we can break out of the potential infinite
8575 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8577 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8580 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8581 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8584 if (x86_page_table_writing_insn(ctxt))
8587 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8590 vcpu->arch.last_retry_eip = ctxt->eip;
8591 vcpu->arch.last_retry_addr = cr2_or_gpa;
8593 if (!vcpu->arch.mmu->root_role.direct)
8594 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8596 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8601 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8602 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8604 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8613 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8614 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8619 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8621 struct kvm_run *kvm_run = vcpu->run;
8623 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8624 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8625 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8626 kvm_run->debug.arch.exception = DB_VECTOR;
8627 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8630 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8634 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8636 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8639 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8643 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8646 * rflags is the old, "raw" value of the flags. The new value has
8647 * not been saved yet.
8649 * This is correct even for TF set by the guest, because "the
8650 * processor will not generate this exception after the instruction
8651 * that sets the TF flag".
8653 if (unlikely(rflags & X86_EFLAGS_TF))
8654 r = kvm_vcpu_do_singlestep(vcpu);
8657 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8659 static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu)
8663 if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF)
8667 * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active,
8668 * but AMD CPUs do not. MOV/POP SS blocking is rare, check that first
8669 * to avoid the relatively expensive CPUID lookup.
8671 shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8672 return (shadow & KVM_X86_SHADOW_INT_MOV_SS) &&
8673 guest_cpuid_is_intel(vcpu);
8676 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu,
8677 int emulation_type, int *r)
8679 WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE);
8682 * Do not check for code breakpoints if hardware has already done the
8683 * checks, as inferred from the emulation type. On NO_DECODE and SKIP,
8684 * the instruction has passed all exception checks, and all intercepted
8685 * exceptions that trigger emulation have lower priority than code
8686 * breakpoints, i.e. the fact that the intercepted exception occurred
8687 * means any code breakpoints have already been serviced.
8689 * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as
8690 * hardware has checked the RIP of the magic prefix, but not the RIP of
8691 * the instruction being emulated. The intent of forced emulation is
8692 * to behave as if KVM intercepted the instruction without an exception
8693 * and without a prefix.
8695 if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
8696 EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF))
8699 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8700 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8701 struct kvm_run *kvm_run = vcpu->run;
8702 unsigned long eip = kvm_get_linear_rip(vcpu);
8703 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8704 vcpu->arch.guest_debug_dr7,
8708 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8709 kvm_run->debug.arch.pc = eip;
8710 kvm_run->debug.arch.exception = DB_VECTOR;
8711 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8717 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8718 !kvm_is_code_breakpoint_inhibited(vcpu)) {
8719 unsigned long eip = kvm_get_linear_rip(vcpu);
8720 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8725 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
8734 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
8736 switch (ctxt->opcode_len) {
8743 case 0xe6: /* OUT */
8747 case 0x6c: /* INS */
8749 case 0x6e: /* OUTS */
8756 case 0x33: /* RDPMC */
8766 * Decode an instruction for emulation. The caller is responsible for handling
8767 * code breakpoints. Note, manually detecting code breakpoints is unnecessary
8768 * (and wrong) when emulating on an intercepted fault-like exception[*], as
8769 * code breakpoints have higher priority and thus have already been done by
8772 * [*] Except #MC, which is higher priority, but KVM should never emulate in
8773 * response to a machine check.
8775 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
8776 void *insn, int insn_len)
8778 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8781 init_emulate_ctxt(vcpu);
8783 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
8785 trace_kvm_emulate_insn_start(vcpu);
8786 ++vcpu->stat.insn_emulation;
8790 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
8792 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8793 int emulation_type, void *insn, int insn_len)
8796 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8797 bool writeback = true;
8799 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len)))
8802 vcpu->arch.l1tf_flush_l1d = true;
8804 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8805 kvm_clear_exception_queue(vcpu);
8808 * Return immediately if RIP hits a code breakpoint, such #DBs
8809 * are fault-like and are higher priority than any faults on
8810 * the code fetch itself.
8812 if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r))
8815 r = x86_decode_emulated_instruction(vcpu, emulation_type,
8817 if (r != EMULATION_OK) {
8818 if ((emulation_type & EMULTYPE_TRAP_UD) ||
8819 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
8820 kvm_queue_exception(vcpu, UD_VECTOR);
8823 if (reexecute_instruction(vcpu, cr2_or_gpa,
8827 if (ctxt->have_exception &&
8828 !(emulation_type & EMULTYPE_SKIP)) {
8830 * #UD should result in just EMULATION_FAILED, and trap-like
8831 * exception should not be encountered during decode.
8833 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
8834 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8835 inject_emulated_exception(vcpu);
8838 return handle_emulation_failure(vcpu, emulation_type);
8842 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
8843 !is_vmware_backdoor_opcode(ctxt)) {
8844 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8849 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
8850 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
8851 * The caller is responsible for updating interruptibility state and
8852 * injecting single-step #DBs.
8854 if (emulation_type & EMULTYPE_SKIP) {
8855 if (ctxt->mode != X86EMUL_MODE_PROT64)
8856 ctxt->eip = (u32)ctxt->_eip;
8858 ctxt->eip = ctxt->_eip;
8860 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
8865 kvm_rip_write(vcpu, ctxt->eip);
8866 if (ctxt->eflags & X86_EFLAGS_RF)
8867 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
8871 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
8874 /* this is needed for vmware backdoor interface to work since it
8875 changes registers values during IO operation */
8876 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
8877 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8878 emulator_invalidate_register_cache(ctxt);
8882 if (emulation_type & EMULTYPE_PF) {
8883 /* Save the faulting GPA (cr2) in the address field */
8884 ctxt->exception.address = cr2_or_gpa;
8886 /* With shadow page tables, cr2 contains a GVA or nGPA. */
8887 if (vcpu->arch.mmu->root_role.direct) {
8888 ctxt->gpa_available = true;
8889 ctxt->gpa_val = cr2_or_gpa;
8892 /* Sanitize the address out of an abundance of paranoia. */
8893 ctxt->exception.address = 0;
8896 r = x86_emulate_insn(ctxt);
8898 if (r == EMULATION_INTERCEPTED)
8901 if (r == EMULATION_FAILED) {
8902 if (reexecute_instruction(vcpu, cr2_or_gpa, emulation_type))
8905 return handle_emulation_failure(vcpu, emulation_type);
8908 if (ctxt->have_exception) {
8910 inject_emulated_exception(vcpu);
8911 } else if (vcpu->arch.pio.count) {
8912 if (!vcpu->arch.pio.in) {
8913 /* FIXME: return into emulator if single-stepping. */
8914 vcpu->arch.pio.count = 0;
8917 vcpu->arch.complete_userspace_io = complete_emulated_pio;
8920 } else if (vcpu->mmio_needed) {
8921 ++vcpu->stat.mmio_exits;
8923 if (!vcpu->mmio_is_write)
8926 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8927 } else if (vcpu->arch.complete_userspace_io) {
8930 } else if (r == EMULATION_RESTART)
8937 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8938 toggle_interruptibility(vcpu, ctxt->interruptibility);
8939 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8942 * Note, EXCPT_DB is assumed to be fault-like as the emulator
8943 * only supports code breakpoints and general detect #DB, both
8944 * of which are fault-like.
8946 if (!ctxt->have_exception ||
8947 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
8948 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8949 if (ctxt->is_branch)
8950 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
8951 kvm_rip_write(vcpu, ctxt->eip);
8952 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
8953 r = kvm_vcpu_do_singlestep(vcpu);
8954 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
8955 __kvm_set_rflags(vcpu, ctxt->eflags);
8959 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
8960 * do nothing, and it will be requested again as soon as
8961 * the shadow expires. But we still need to check here,
8962 * because POPF has no interrupt shadow.
8964 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
8965 kvm_make_request(KVM_REQ_EVENT, vcpu);
8967 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
8972 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
8974 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
8976 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
8978 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
8979 void *insn, int insn_len)
8981 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
8983 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
8985 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
8987 vcpu->arch.pio.count = 0;
8991 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
8993 vcpu->arch.pio.count = 0;
8995 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
8998 return kvm_skip_emulated_instruction(vcpu);
9001 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
9002 unsigned short port)
9004 unsigned long val = kvm_rax_read(vcpu);
9005 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
9011 * Workaround userspace that relies on old KVM behavior of %rip being
9012 * incremented prior to exiting to userspace to handle "OUT 0x7e".
9015 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
9016 vcpu->arch.complete_userspace_io =
9017 complete_fast_pio_out_port_0x7e;
9018 kvm_skip_emulated_instruction(vcpu);
9020 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9021 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
9026 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
9030 /* We should only ever be called with arch.pio.count equal to 1 */
9031 BUG_ON(vcpu->arch.pio.count != 1);
9033 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
9034 vcpu->arch.pio.count = 0;
9038 /* For size less than 4 we merge, else we zero extend */
9039 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
9041 complete_emulator_pio_in(vcpu, &val);
9042 kvm_rax_write(vcpu, val);
9044 return kvm_skip_emulated_instruction(vcpu);
9047 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
9048 unsigned short port)
9053 /* For size less than 4 we merge, else we zero extend */
9054 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
9056 ret = emulator_pio_in(vcpu, size, port, &val, 1);
9058 kvm_rax_write(vcpu, val);
9062 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9063 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
9068 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
9073 ret = kvm_fast_pio_in(vcpu, size, port);
9075 ret = kvm_fast_pio_out(vcpu, size, port);
9076 return ret && kvm_skip_emulated_instruction(vcpu);
9078 EXPORT_SYMBOL_GPL(kvm_fast_pio);
9080 static int kvmclock_cpu_down_prep(unsigned int cpu)
9082 __this_cpu_write(cpu_tsc_khz, 0);
9086 static void tsc_khz_changed(void *data)
9088 struct cpufreq_freqs *freq = data;
9089 unsigned long khz = 0;
9091 WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_CONSTANT_TSC));
9096 khz = cpufreq_quick_get(raw_smp_processor_id());
9099 __this_cpu_write(cpu_tsc_khz, khz);
9102 #ifdef CONFIG_X86_64
9103 static void kvm_hyperv_tsc_notifier(void)
9108 mutex_lock(&kvm_lock);
9109 list_for_each_entry(kvm, &vm_list, vm_list)
9110 kvm_make_mclock_inprogress_request(kvm);
9112 /* no guest entries from this point */
9113 hyperv_stop_tsc_emulation();
9115 /* TSC frequency always matches when on Hyper-V */
9116 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9117 for_each_present_cpu(cpu)
9118 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
9120 kvm_caps.max_guest_tsc_khz = tsc_khz;
9122 list_for_each_entry(kvm, &vm_list, vm_list) {
9123 __kvm_start_pvclock_update(kvm);
9124 pvclock_update_vm_gtod_copy(kvm);
9125 kvm_end_pvclock_update(kvm);
9128 mutex_unlock(&kvm_lock);
9132 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
9135 struct kvm_vcpu *vcpu;
9140 * We allow guests to temporarily run on slowing clocks,
9141 * provided we notify them after, or to run on accelerating
9142 * clocks, provided we notify them before. Thus time never
9145 * However, we have a problem. We can't atomically update
9146 * the frequency of a given CPU from this function; it is
9147 * merely a notifier, which can be called from any CPU.
9148 * Changing the TSC frequency at arbitrary points in time
9149 * requires a recomputation of local variables related to
9150 * the TSC for each VCPU. We must flag these local variables
9151 * to be updated and be sure the update takes place with the
9152 * new frequency before any guests proceed.
9154 * Unfortunately, the combination of hotplug CPU and frequency
9155 * change creates an intractable locking scenario; the order
9156 * of when these callouts happen is undefined with respect to
9157 * CPU hotplug, and they can race with each other. As such,
9158 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
9159 * undefined; you can actually have a CPU frequency change take
9160 * place in between the computation of X and the setting of the
9161 * variable. To protect against this problem, all updates of
9162 * the per_cpu tsc_khz variable are done in an interrupt
9163 * protected IPI, and all callers wishing to update the value
9164 * must wait for a synchronous IPI to complete (which is trivial
9165 * if the caller is on the CPU already). This establishes the
9166 * necessary total order on variable updates.
9168 * Note that because a guest time update may take place
9169 * anytime after the setting of the VCPU's request bit, the
9170 * correct TSC value must be set before the request. However,
9171 * to ensure the update actually makes it to any guest which
9172 * starts running in hardware virtualization between the set
9173 * and the acquisition of the spinlock, we must also ping the
9174 * CPU after setting the request bit.
9178 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9180 mutex_lock(&kvm_lock);
9181 list_for_each_entry(kvm, &vm_list, vm_list) {
9182 kvm_for_each_vcpu(i, vcpu, kvm) {
9183 if (vcpu->cpu != cpu)
9185 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9186 if (vcpu->cpu != raw_smp_processor_id())
9190 mutex_unlock(&kvm_lock);
9192 if (freq->old < freq->new && send_ipi) {
9194 * We upscale the frequency. Must make the guest
9195 * doesn't see old kvmclock values while running with
9196 * the new frequency, otherwise we risk the guest sees
9197 * time go backwards.
9199 * In case we update the frequency for another cpu
9200 * (which might be in guest context) send an interrupt
9201 * to kick the cpu out of guest context. Next time
9202 * guest context is entered kvmclock will be updated,
9203 * so the guest will not see stale values.
9205 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9209 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
9212 struct cpufreq_freqs *freq = data;
9215 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
9217 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
9220 for_each_cpu(cpu, freq->policy->cpus)
9221 __kvmclock_cpufreq_notifier(freq, cpu);
9226 static struct notifier_block kvmclock_cpufreq_notifier_block = {
9227 .notifier_call = kvmclock_cpufreq_notifier
9230 static int kvmclock_cpu_online(unsigned int cpu)
9232 tsc_khz_changed(NULL);
9236 static void kvm_timer_init(void)
9238 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9239 max_tsc_khz = tsc_khz;
9241 if (IS_ENABLED(CONFIG_CPU_FREQ)) {
9242 struct cpufreq_policy *policy;
9246 policy = cpufreq_cpu_get(cpu);
9248 if (policy->cpuinfo.max_freq)
9249 max_tsc_khz = policy->cpuinfo.max_freq;
9250 cpufreq_cpu_put(policy);
9254 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
9255 CPUFREQ_TRANSITION_NOTIFIER);
9257 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
9258 kvmclock_cpu_online, kvmclock_cpu_down_prep);
9262 #ifdef CONFIG_X86_64
9263 static void pvclock_gtod_update_fn(struct work_struct *work)
9266 struct kvm_vcpu *vcpu;
9269 mutex_lock(&kvm_lock);
9270 list_for_each_entry(kvm, &vm_list, vm_list)
9271 kvm_for_each_vcpu(i, vcpu, kvm)
9272 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9273 atomic_set(&kvm_guest_has_master_clock, 0);
9274 mutex_unlock(&kvm_lock);
9277 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
9280 * Indirection to move queue_work() out of the tk_core.seq write held
9281 * region to prevent possible deadlocks against time accessors which
9282 * are invoked with work related locks held.
9284 static void pvclock_irq_work_fn(struct irq_work *w)
9286 queue_work(system_long_wq, &pvclock_gtod_work);
9289 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
9292 * Notification about pvclock gtod data update.
9294 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
9297 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
9298 struct timekeeper *tk = priv;
9300 update_pvclock_gtod(tk);
9303 * Disable master clock if host does not trust, or does not use,
9304 * TSC based clocksource. Delegate queue_work() to irq_work as
9305 * this is invoked with tk_core.seq write held.
9307 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
9308 atomic_read(&kvm_guest_has_master_clock) != 0)
9309 irq_work_queue(&pvclock_irq_work);
9313 static struct notifier_block pvclock_gtod_notifier = {
9314 .notifier_call = pvclock_gtod_notify,
9318 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops)
9320 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9322 #define __KVM_X86_OP(func) \
9323 static_call_update(kvm_x86_##func, kvm_x86_ops.func);
9324 #define KVM_X86_OP(func) \
9325 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func)
9326 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP
9327 #define KVM_X86_OP_OPTIONAL_RET0(func) \
9328 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \
9329 (void *)__static_call_return0);
9330 #include <asm/kvm-x86-ops.h>
9333 kvm_pmu_ops_update(ops->pmu_ops);
9336 static int kvm_x86_check_processor_compatibility(void)
9338 int cpu = smp_processor_id();
9339 struct cpuinfo_x86 *c = &cpu_data(cpu);
9342 * Compatibility checks are done when loading KVM and when enabling
9343 * hardware, e.g. during CPU hotplug, to ensure all online CPUs are
9344 * compatible, i.e. KVM should never perform a compatibility check on
9347 WARN_ON(!cpu_online(cpu));
9349 if (__cr4_reserved_bits(cpu_has, c) !=
9350 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9353 return static_call(kvm_x86_check_processor_compatibility)();
9356 static void kvm_x86_check_cpu_compat(void *ret)
9358 *(int *)ret = kvm_x86_check_processor_compatibility();
9361 static int __kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9366 if (kvm_x86_ops.hardware_enable) {
9367 pr_err("already loaded vendor module '%s'\n", kvm_x86_ops.name);
9372 * KVM explicitly assumes that the guest has an FPU and
9373 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
9374 * vCPU's FPU state as a fxregs_state struct.
9376 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
9377 pr_err("inadequate fpu\n");
9381 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9382 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
9387 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes
9388 * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something
9389 * other than WB. Note, EPT doesn't utilize the PAT, but don't bother
9390 * with an exception. PAT[0] is set to WB on RESET and also by the
9391 * kernel, i.e. failure indicates a kernel bug or broken firmware.
9393 if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) ||
9394 (host_pat & GENMASK(2, 0)) != 6) {
9395 pr_err("host PAT[0] is not WB\n");
9399 x86_emulator_cache = kvm_alloc_emulator_cache();
9400 if (!x86_emulator_cache) {
9401 pr_err("failed to allocate cache for x86 emulator\n");
9405 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
9406 if (!user_return_msrs) {
9407 pr_err("failed to allocate percpu kvm_user_return_msrs\n");
9409 goto out_free_x86_emulator_cache;
9411 kvm_nr_uret_msrs = 0;
9413 r = kvm_mmu_vendor_module_init();
9415 goto out_free_percpu;
9417 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
9418 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
9419 kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
9422 rdmsrl_safe(MSR_EFER, &host_efer);
9424 if (boot_cpu_has(X86_FEATURE_XSAVES))
9425 rdmsrl(MSR_IA32_XSS, host_xss);
9427 kvm_init_pmu_capability(ops->pmu_ops);
9429 r = ops->hardware_setup();
9433 kvm_ops_update(ops);
9435 for_each_online_cpu(cpu) {
9436 smp_call_function_single(cpu, kvm_x86_check_cpu_compat, &r, 1);
9438 goto out_unwind_ops;
9442 * Point of no return! DO NOT add error paths below this point unless
9443 * absolutely necessary, as most operations from this point forward
9444 * require unwinding.
9448 if (pi_inject_timer == -1)
9449 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
9450 #ifdef CONFIG_X86_64
9451 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
9453 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9454 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
9457 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
9459 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9460 kvm_caps.supported_xss = 0;
9462 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9463 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9464 #undef __kvm_cpu_cap_has
9466 if (kvm_caps.has_tsc_control) {
9468 * Make sure the user can only configure tsc_khz values that
9469 * fit into a signed integer.
9470 * A min value is not calculated because it will always
9471 * be 1 on all machines.
9473 u64 max = min(0x7fffffffULL,
9474 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz));
9475 kvm_caps.max_guest_tsc_khz = max;
9477 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits;
9478 kvm_init_msr_list();
9482 kvm_x86_ops.hardware_enable = NULL;
9483 static_call(kvm_x86_hardware_unsetup)();
9485 kvm_mmu_vendor_module_exit();
9487 free_percpu(user_return_msrs);
9488 out_free_x86_emulator_cache:
9489 kmem_cache_destroy(x86_emulator_cache);
9493 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9497 mutex_lock(&vendor_module_lock);
9498 r = __kvm_x86_vendor_init(ops);
9499 mutex_unlock(&vendor_module_lock);
9503 EXPORT_SYMBOL_GPL(kvm_x86_vendor_init);
9505 void kvm_x86_vendor_exit(void)
9507 kvm_unregister_perf_callbacks();
9509 #ifdef CONFIG_X86_64
9510 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9511 clear_hv_tscchange_cb();
9515 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9516 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
9517 CPUFREQ_TRANSITION_NOTIFIER);
9518 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
9520 #ifdef CONFIG_X86_64
9521 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
9522 irq_work_sync(&pvclock_irq_work);
9523 cancel_work_sync(&pvclock_gtod_work);
9525 static_call(kvm_x86_hardware_unsetup)();
9526 kvm_mmu_vendor_module_exit();
9527 free_percpu(user_return_msrs);
9528 kmem_cache_destroy(x86_emulator_cache);
9529 #ifdef CONFIG_KVM_XEN
9530 static_key_deferred_flush(&kvm_xen_enabled);
9531 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
9533 mutex_lock(&vendor_module_lock);
9534 kvm_x86_ops.hardware_enable = NULL;
9535 mutex_unlock(&vendor_module_lock);
9537 EXPORT_SYMBOL_GPL(kvm_x86_vendor_exit);
9539 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
9542 * The vCPU has halted, e.g. executed HLT. Update the run state if the
9543 * local APIC is in-kernel, the run loop will detect the non-runnable
9544 * state and halt the vCPU. Exit to userspace if the local APIC is
9545 * managed by userspace, in which case userspace is responsible for
9546 * handling wake events.
9548 ++vcpu->stat.halt_exits;
9549 if (lapic_in_kernel(vcpu)) {
9550 vcpu->arch.mp_state = state;
9553 vcpu->run->exit_reason = reason;
9558 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9560 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9562 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9564 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9566 int ret = kvm_skip_emulated_instruction(vcpu);
9568 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9569 * KVM_EXIT_DEBUG here.
9571 return kvm_emulate_halt_noskip(vcpu) && ret;
9573 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9575 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9577 int ret = kvm_skip_emulated_instruction(vcpu);
9579 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9580 KVM_EXIT_AP_RESET_HOLD) && ret;
9582 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9584 #ifdef CONFIG_X86_64
9585 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9586 unsigned long clock_type)
9588 struct kvm_clock_pairing clock_pairing;
9589 struct timespec64 ts;
9593 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9594 return -KVM_EOPNOTSUPP;
9597 * When tsc is in permanent catchup mode guests won't be able to use
9598 * pvclock_read_retry loop to get consistent view of pvclock
9600 if (vcpu->arch.tsc_always_catchup)
9601 return -KVM_EOPNOTSUPP;
9603 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9604 return -KVM_EOPNOTSUPP;
9606 clock_pairing.sec = ts.tv_sec;
9607 clock_pairing.nsec = ts.tv_nsec;
9608 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9609 clock_pairing.flags = 0;
9610 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9613 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9614 sizeof(struct kvm_clock_pairing)))
9622 * kvm_pv_kick_cpu_op: Kick a vcpu.
9624 * @apicid - apicid of vcpu to be kicked.
9626 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9629 * All other fields are unused for APIC_DM_REMRD, but may be consumed by
9630 * common code, e.g. for tracing. Defer initialization to the compiler.
9632 struct kvm_lapic_irq lapic_irq = {
9633 .delivery_mode = APIC_DM_REMRD,
9634 .dest_mode = APIC_DEST_PHYSICAL,
9635 .shorthand = APIC_DEST_NOSHORT,
9639 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9642 bool kvm_apicv_activated(struct kvm *kvm)
9644 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9646 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9648 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu)
9650 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons);
9651 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu);
9653 return (vm_reasons | vcpu_reasons) == 0;
9655 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated);
9657 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9658 enum kvm_apicv_inhibit reason, bool set)
9661 __set_bit(reason, inhibits);
9663 __clear_bit(reason, inhibits);
9665 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9668 static void kvm_apicv_init(struct kvm *kvm)
9670 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9672 init_rwsem(&kvm->arch.apicv_update_lock);
9674 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9677 set_or_clear_apicv_inhibit(inhibits,
9678 APICV_INHIBIT_REASON_DISABLE, true);
9681 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9683 struct kvm_vcpu *target = NULL;
9684 struct kvm_apic_map *map;
9686 vcpu->stat.directed_yield_attempted++;
9688 if (single_task_running())
9692 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9694 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9695 target = map->phys_map[dest_id]->vcpu;
9699 if (!target || !READ_ONCE(target->ready))
9702 /* Ignore requests to yield to self */
9706 if (kvm_vcpu_yield_to(target) <= 0)
9709 vcpu->stat.directed_yield_successful++;
9715 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
9717 u64 ret = vcpu->run->hypercall.ret;
9719 if (!is_64_bit_mode(vcpu))
9721 kvm_rax_write(vcpu, ret);
9722 ++vcpu->stat.hypercalls;
9723 return kvm_skip_emulated_instruction(vcpu);
9726 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
9728 unsigned long nr, a0, a1, a2, a3, ret;
9731 if (kvm_xen_hypercall_enabled(vcpu->kvm))
9732 return kvm_xen_hypercall(vcpu);
9734 if (kvm_hv_hypercall_enabled(vcpu))
9735 return kvm_hv_hypercall(vcpu);
9737 nr = kvm_rax_read(vcpu);
9738 a0 = kvm_rbx_read(vcpu);
9739 a1 = kvm_rcx_read(vcpu);
9740 a2 = kvm_rdx_read(vcpu);
9741 a3 = kvm_rsi_read(vcpu);
9743 trace_kvm_hypercall(nr, a0, a1, a2, a3);
9745 op_64_bit = is_64_bit_hypercall(vcpu);
9754 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
9762 case KVM_HC_VAPIC_POLL_IRQ:
9765 case KVM_HC_KICK_CPU:
9766 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
9769 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
9770 kvm_sched_yield(vcpu, a1);
9773 #ifdef CONFIG_X86_64
9774 case KVM_HC_CLOCK_PAIRING:
9775 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
9778 case KVM_HC_SEND_IPI:
9779 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
9782 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
9784 case KVM_HC_SCHED_YIELD:
9785 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
9788 kvm_sched_yield(vcpu, a0);
9791 case KVM_HC_MAP_GPA_RANGE: {
9792 u64 gpa = a0, npages = a1, attrs = a2;
9795 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
9798 if (!PAGE_ALIGNED(gpa) || !npages ||
9799 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
9804 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
9805 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
9806 vcpu->run->hypercall.args[0] = gpa;
9807 vcpu->run->hypercall.args[1] = npages;
9808 vcpu->run->hypercall.args[2] = attrs;
9809 vcpu->run->hypercall.longmode = op_64_bit;
9810 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
9820 kvm_rax_write(vcpu, ret);
9822 ++vcpu->stat.hypercalls;
9823 return kvm_skip_emulated_instruction(vcpu);
9825 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
9827 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
9829 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
9830 char instruction[3];
9831 unsigned long rip = kvm_rip_read(vcpu);
9834 * If the quirk is disabled, synthesize a #UD and let the guest pick up
9837 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) {
9838 ctxt->exception.error_code_valid = false;
9839 ctxt->exception.vector = UD_VECTOR;
9840 ctxt->have_exception = true;
9841 return X86EMUL_PROPAGATE_FAULT;
9844 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
9846 return emulator_write_emulated(ctxt, rip, instruction, 3,
9850 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
9852 return vcpu->run->request_interrupt_window &&
9853 likely(!pic_in_kernel(vcpu->kvm));
9856 /* Called within kvm->srcu read side. */
9857 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
9859 struct kvm_run *kvm_run = vcpu->run;
9861 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
9862 kvm_run->cr8 = kvm_get_cr8(vcpu);
9863 kvm_run->apic_base = kvm_get_apic_base(vcpu);
9865 kvm_run->ready_for_interrupt_injection =
9866 pic_in_kernel(vcpu->kvm) ||
9867 kvm_vcpu_ready_for_interrupt_injection(vcpu);
9870 kvm_run->flags |= KVM_RUN_X86_SMM;
9873 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
9877 if (!kvm_x86_ops.update_cr8_intercept)
9880 if (!lapic_in_kernel(vcpu))
9883 if (vcpu->arch.apic->apicv_active)
9886 if (!vcpu->arch.apic->vapic_addr)
9887 max_irr = kvm_lapic_find_highest_irr(vcpu);
9894 tpr = kvm_lapic_get_cr8(vcpu);
9896 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
9900 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
9902 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9903 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9907 return kvm_x86_ops.nested_ops->check_events(vcpu);
9910 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
9912 trace_kvm_inj_exception(vcpu->arch.exception.vector,
9913 vcpu->arch.exception.has_error_code,
9914 vcpu->arch.exception.error_code,
9915 vcpu->arch.exception.injected);
9917 if (vcpu->arch.exception.error_code && !is_protmode(vcpu))
9918 vcpu->arch.exception.error_code = false;
9919 static_call(kvm_x86_inject_exception)(vcpu);
9923 * Check for any event (interrupt or exception) that is ready to be injected,
9924 * and if there is at least one event, inject the event with the highest
9925 * priority. This handles both "pending" events, i.e. events that have never
9926 * been injected into the guest, and "injected" events, i.e. events that were
9927 * injected as part of a previous VM-Enter, but weren't successfully delivered
9928 * and need to be re-injected.
9930 * Note, this is not guaranteed to be invoked on a guest instruction boundary,
9931 * i.e. doesn't guarantee that there's an event window in the guest. KVM must
9932 * be able to inject exceptions in the "middle" of an instruction, and so must
9933 * also be able to re-inject NMIs and IRQs in the middle of an instruction.
9934 * I.e. for exceptions and re-injected events, NOT invoking this on instruction
9935 * boundaries is necessary and correct.
9937 * For simplicity, KVM uses a single path to inject all events (except events
9938 * that are injected directly from L1 to L2) and doesn't explicitly track
9939 * instruction boundaries for asynchronous events. However, because VM-Exits
9940 * that can occur during instruction execution typically result in KVM skipping
9941 * the instruction or injecting an exception, e.g. instruction and exception
9942 * intercepts, and because pending exceptions have higher priority than pending
9943 * interrupts, KVM still honors instruction boundaries in most scenarios.
9945 * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip
9946 * the instruction or inject an exception, then KVM can incorrecty inject a new
9947 * asynchrounous event if the event became pending after the CPU fetched the
9948 * instruction (in the guest). E.g. if a page fault (#PF, #NPF, EPT violation)
9949 * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be
9950 * injected on the restarted instruction instead of being deferred until the
9951 * instruction completes.
9953 * In practice, this virtualization hole is unlikely to be observed by the
9954 * guest, and even less likely to cause functional problems. To detect the
9955 * hole, the guest would have to trigger an event on a side effect of an early
9956 * phase of instruction execution, e.g. on the instruction fetch from memory.
9957 * And for it to be a functional problem, the guest would need to depend on the
9958 * ordering between that side effect, the instruction completing, _and_ the
9959 * delivery of the asynchronous event.
9961 static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu,
9962 bool *req_immediate_exit)
9968 * Process nested events first, as nested VM-Exit supercedes event
9969 * re-injection. If there's an event queued for re-injection, it will
9970 * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit.
9972 if (is_guest_mode(vcpu))
9973 r = kvm_check_nested_events(vcpu);
9978 * Re-inject exceptions and events *especially* if immediate entry+exit
9979 * to/from L2 is needed, as any event that has already been injected
9980 * into L2 needs to complete its lifecycle before injecting a new event.
9982 * Don't re-inject an NMI or interrupt if there is a pending exception.
9983 * This collision arises if an exception occurred while vectoring the
9984 * injected event, KVM intercepted said exception, and KVM ultimately
9985 * determined the fault belongs to the guest and queues the exception
9986 * for injection back into the guest.
9988 * "Injected" interrupts can also collide with pending exceptions if
9989 * userspace ignores the "ready for injection" flag and blindly queues
9990 * an interrupt. In that case, prioritizing the exception is correct,
9991 * as the exception "occurred" before the exit to userspace. Trap-like
9992 * exceptions, e.g. most #DBs, have higher priority than interrupts.
9993 * And while fault-like exceptions, e.g. #GP and #PF, are the lowest
9994 * priority, they're only generated (pended) during instruction
9995 * execution, and interrupts are recognized at instruction boundaries.
9996 * Thus a pending fault-like exception means the fault occurred on the
9997 * *previous* instruction and must be serviced prior to recognizing any
9998 * new events in order to fully complete the previous instruction.
10000 if (vcpu->arch.exception.injected)
10001 kvm_inject_exception(vcpu);
10002 else if (kvm_is_exception_pending(vcpu))
10004 else if (vcpu->arch.nmi_injected)
10005 static_call(kvm_x86_inject_nmi)(vcpu);
10006 else if (vcpu->arch.interrupt.injected)
10007 static_call(kvm_x86_inject_irq)(vcpu, true);
10010 * Exceptions that morph to VM-Exits are handled above, and pending
10011 * exceptions on top of injected exceptions that do not VM-Exit should
10012 * either morph to #DF or, sadly, override the injected exception.
10014 WARN_ON_ONCE(vcpu->arch.exception.injected &&
10015 vcpu->arch.exception.pending);
10018 * Bail if immediate entry+exit to/from the guest is needed to complete
10019 * nested VM-Enter or event re-injection so that a different pending
10020 * event can be serviced (or if KVM needs to exit to userspace).
10022 * Otherwise, continue processing events even if VM-Exit occurred. The
10023 * VM-Exit will have cleared exceptions that were meant for L2, but
10024 * there may now be events that can be injected into L1.
10030 * A pending exception VM-Exit should either result in nested VM-Exit
10031 * or force an immediate re-entry and exit to/from L2, and exception
10032 * VM-Exits cannot be injected (flag should _never_ be set).
10034 WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected ||
10035 vcpu->arch.exception_vmexit.pending);
10038 * New events, other than exceptions, cannot be injected if KVM needs
10039 * to re-inject a previous event. See above comments on re-injecting
10040 * for why pending exceptions get priority.
10042 can_inject = !kvm_event_needs_reinjection(vcpu);
10044 if (vcpu->arch.exception.pending) {
10046 * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS
10047 * value pushed on the stack. Trap-like exception and all #DBs
10048 * leave RF as-is (KVM follows Intel's behavior in this regard;
10049 * AMD states that code breakpoint #DBs excplitly clear RF=0).
10051 * Note, most versions of Intel's SDM and AMD's APM incorrectly
10052 * describe the behavior of General Detect #DBs, which are
10053 * fault-like. They do _not_ set RF, a la code breakpoints.
10055 if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT)
10056 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
10059 if (vcpu->arch.exception.vector == DB_VECTOR) {
10060 kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception);
10061 if (vcpu->arch.dr7 & DR7_GD) {
10062 vcpu->arch.dr7 &= ~DR7_GD;
10063 kvm_update_dr7(vcpu);
10067 kvm_inject_exception(vcpu);
10069 vcpu->arch.exception.pending = false;
10070 vcpu->arch.exception.injected = true;
10072 can_inject = false;
10075 /* Don't inject interrupts if the user asked to avoid doing so */
10076 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
10080 * Finally, inject interrupt events. If an event cannot be injected
10081 * due to architectural conditions (e.g. IF=0) a window-open exit
10082 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
10083 * and can architecturally be injected, but we cannot do it right now:
10084 * an interrupt could have arrived just now and we have to inject it
10085 * as a vmexit, or there could already an event in the queue, which is
10086 * indicated by can_inject. In that case we request an immediate exit
10087 * in order to make progress and get back here for another iteration.
10088 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
10090 #ifdef CONFIG_KVM_SMM
10091 if (vcpu->arch.smi_pending) {
10092 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
10096 vcpu->arch.smi_pending = false;
10097 ++vcpu->arch.smi_count;
10099 can_inject = false;
10101 static_call(kvm_x86_enable_smi_window)(vcpu);
10105 if (vcpu->arch.nmi_pending) {
10106 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
10110 --vcpu->arch.nmi_pending;
10111 vcpu->arch.nmi_injected = true;
10112 static_call(kvm_x86_inject_nmi)(vcpu);
10113 can_inject = false;
10114 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
10116 if (vcpu->arch.nmi_pending)
10117 static_call(kvm_x86_enable_nmi_window)(vcpu);
10120 if (kvm_cpu_has_injectable_intr(vcpu)) {
10121 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
10125 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
10126 static_call(kvm_x86_inject_irq)(vcpu, false);
10127 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
10129 if (kvm_cpu_has_injectable_intr(vcpu))
10130 static_call(kvm_x86_enable_irq_window)(vcpu);
10133 if (is_guest_mode(vcpu) &&
10134 kvm_x86_ops.nested_ops->has_events &&
10135 kvm_x86_ops.nested_ops->has_events(vcpu))
10136 *req_immediate_exit = true;
10139 * KVM must never queue a new exception while injecting an event; KVM
10140 * is done emulating and should only propagate the to-be-injected event
10141 * to the VMCS/VMCB. Queueing a new exception can put the vCPU into an
10142 * infinite loop as KVM will bail from VM-Enter to inject the pending
10143 * exception and start the cycle all over.
10145 * Exempt triple faults as they have special handling and won't put the
10146 * vCPU into an infinite loop. Triple fault can be queued when running
10147 * VMX without unrestricted guest, as that requires KVM to emulate Real
10148 * Mode events (see kvm_inject_realmode_interrupt()).
10150 WARN_ON_ONCE(vcpu->arch.exception.pending ||
10151 vcpu->arch.exception_vmexit.pending);
10156 *req_immediate_exit = true;
10162 static void process_nmi(struct kvm_vcpu *vcpu)
10164 unsigned limit = 2;
10167 * x86 is limited to one NMI running, and one NMI pending after it.
10168 * If an NMI is already in progress, limit further NMIs to just one.
10169 * Otherwise, allow two (and we'll inject the first one immediately).
10171 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
10174 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
10175 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
10176 kvm_make_request(KVM_REQ_EVENT, vcpu);
10179 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
10180 unsigned long *vcpu_bitmap)
10182 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
10185 void kvm_make_scan_ioapic_request(struct kvm *kvm)
10187 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
10190 void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10192 struct kvm_lapic *apic = vcpu->arch.apic;
10195 if (!lapic_in_kernel(vcpu))
10198 down_read(&vcpu->kvm->arch.apicv_update_lock);
10201 /* Do not activate APICV when APIC is disabled */
10202 activate = kvm_vcpu_apicv_activated(vcpu) &&
10203 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED);
10205 if (apic->apicv_active == activate)
10208 apic->apicv_active = activate;
10209 kvm_apic_update_apicv(vcpu);
10210 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
10213 * When APICv gets disabled, we may still have injected interrupts
10214 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
10215 * still active when the interrupt got accepted. Make sure
10216 * kvm_check_and_inject_events() is called to check for that.
10218 if (!apic->apicv_active)
10219 kvm_make_request(KVM_REQ_EVENT, vcpu);
10223 up_read(&vcpu->kvm->arch.apicv_update_lock);
10225 EXPORT_SYMBOL_GPL(__kvm_vcpu_update_apicv);
10227 static void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10229 if (!lapic_in_kernel(vcpu))
10233 * Due to sharing page tables across vCPUs, the xAPIC memslot must be
10234 * deleted if any vCPU has xAPIC virtualization and x2APIC enabled, but
10235 * and hardware doesn't support x2APIC virtualization. E.g. some AMD
10236 * CPUs support AVIC but not x2APIC. KVM still allows enabling AVIC in
10237 * this case so that KVM can the AVIC doorbell to inject interrupts to
10238 * running vCPUs, but KVM must not create SPTEs for the APIC base as
10239 * the vCPU would incorrectly be able to access the vAPIC page via MMIO
10240 * despite being in x2APIC mode. For simplicity, inhibiting the APIC
10241 * access page is sticky.
10243 if (apic_x2apic_mode(vcpu->arch.apic) &&
10244 kvm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization)
10245 kvm_inhibit_apic_access_page(vcpu);
10247 __kvm_vcpu_update_apicv(vcpu);
10250 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10251 enum kvm_apicv_inhibit reason, bool set)
10253 unsigned long old, new;
10255 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
10257 if (!(kvm_x86_ops.required_apicv_inhibits & BIT(reason)))
10260 old = new = kvm->arch.apicv_inhibit_reasons;
10262 set_or_clear_apicv_inhibit(&new, reason, set);
10264 if (!!old != !!new) {
10266 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
10267 * false positives in the sanity check WARN in svm_vcpu_run().
10268 * This task will wait for all vCPUs to ack the kick IRQ before
10269 * updating apicv_inhibit_reasons, and all other vCPUs will
10270 * block on acquiring apicv_update_lock so that vCPUs can't
10271 * redo svm_vcpu_run() without seeing the new inhibit state.
10273 * Note, holding apicv_update_lock and taking it in the read
10274 * side (handling the request) also prevents other vCPUs from
10275 * servicing the request with a stale apicv_inhibit_reasons.
10277 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
10278 kvm->arch.apicv_inhibit_reasons = new;
10280 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
10281 int idx = srcu_read_lock(&kvm->srcu);
10283 kvm_zap_gfn_range(kvm, gfn, gfn+1);
10284 srcu_read_unlock(&kvm->srcu, idx);
10287 kvm->arch.apicv_inhibit_reasons = new;
10291 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10292 enum kvm_apicv_inhibit reason, bool set)
10297 down_write(&kvm->arch.apicv_update_lock);
10298 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
10299 up_write(&kvm->arch.apicv_update_lock);
10301 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
10303 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
10305 if (!kvm_apic_present(vcpu))
10308 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
10310 if (irqchip_split(vcpu->kvm))
10311 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
10313 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10314 if (ioapic_in_kernel(vcpu->kvm))
10315 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
10318 if (is_guest_mode(vcpu))
10319 vcpu->arch.load_eoi_exitmap_pending = true;
10321 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
10324 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
10326 u64 eoi_exit_bitmap[4];
10328 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
10331 if (to_hv_vcpu(vcpu)) {
10332 bitmap_or((ulong *)eoi_exit_bitmap,
10333 vcpu->arch.ioapic_handled_vectors,
10334 to_hv_synic(vcpu)->vec_bitmap, 256);
10335 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
10339 static_call_cond(kvm_x86_load_eoi_exitmap)(
10340 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
10343 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
10344 unsigned long start, unsigned long end)
10346 unsigned long apic_address;
10349 * The physical address of apic access page is stored in the VMCS.
10350 * Update it when it becomes invalid.
10352 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
10353 if (start <= apic_address && apic_address < end)
10354 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
10357 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
10359 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm);
10362 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
10364 if (!lapic_in_kernel(vcpu))
10367 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
10370 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
10372 smp_send_reschedule(vcpu->cpu);
10374 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
10377 * Called within kvm->srcu read side.
10378 * Returns 1 to let vcpu_run() continue the guest execution loop without
10379 * exiting to the userspace. Otherwise, the value will be returned to the
10382 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
10386 dm_request_for_irq_injection(vcpu) &&
10387 kvm_cpu_accept_dm_intr(vcpu);
10388 fastpath_t exit_fastpath;
10390 bool req_immediate_exit = false;
10392 if (kvm_request_pending(vcpu)) {
10393 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
10398 if (kvm_dirty_ring_check_request(vcpu)) {
10403 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
10404 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
10409 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
10410 kvm_mmu_free_obsolete_roots(vcpu);
10411 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
10412 __kvm_migrate_timers(vcpu);
10413 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
10414 kvm_update_masterclock(vcpu->kvm);
10415 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
10416 kvm_gen_kvmclock_update(vcpu);
10417 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
10418 r = kvm_guest_time_update(vcpu);
10422 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
10423 kvm_mmu_sync_roots(vcpu);
10424 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
10425 kvm_mmu_load_pgd(vcpu);
10428 * Note, the order matters here, as flushing "all" TLB entries
10429 * also flushes the "current" TLB entries, i.e. servicing the
10430 * flush "all" will clear any request to flush "current".
10432 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
10433 kvm_vcpu_flush_tlb_all(vcpu);
10435 kvm_service_local_tlb_flush_requests(vcpu);
10438 * Fall back to a "full" guest flush if Hyper-V's precise
10439 * flushing fails. Note, Hyper-V's flushing is per-vCPU, but
10440 * the flushes are considered "remote" and not "local" because
10441 * the requests can be initiated from other vCPUs.
10443 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu) &&
10444 kvm_hv_vcpu_flush_tlb(vcpu))
10445 kvm_vcpu_flush_tlb_guest(vcpu);
10447 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
10448 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
10452 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10453 if (is_guest_mode(vcpu))
10454 kvm_x86_ops.nested_ops->triple_fault(vcpu);
10456 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10457 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
10458 vcpu->mmio_needed = 0;
10463 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
10464 /* Page is swapped out. Do synthetic halt */
10465 vcpu->arch.apf.halted = true;
10469 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
10470 record_steal_time(vcpu);
10471 #ifdef CONFIG_KVM_SMM
10472 if (kvm_check_request(KVM_REQ_SMI, vcpu))
10475 if (kvm_check_request(KVM_REQ_NMI, vcpu))
10477 if (kvm_check_request(KVM_REQ_PMU, vcpu))
10478 kvm_pmu_handle_event(vcpu);
10479 if (kvm_check_request(KVM_REQ_PMI, vcpu))
10480 kvm_pmu_deliver_pmi(vcpu);
10481 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10482 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10483 if (test_bit(vcpu->arch.pending_ioapic_eoi,
10484 vcpu->arch.ioapic_handled_vectors)) {
10485 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10486 vcpu->run->eoi.vector =
10487 vcpu->arch.pending_ioapic_eoi;
10492 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10493 vcpu_scan_ioapic(vcpu);
10494 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10495 vcpu_load_eoi_exitmap(vcpu);
10496 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10497 kvm_vcpu_reload_apic_access_page(vcpu);
10498 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10499 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10500 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10501 vcpu->run->system_event.ndata = 0;
10505 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10506 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10507 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10508 vcpu->run->system_event.ndata = 0;
10512 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10513 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10515 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10516 vcpu->run->hyperv = hv_vcpu->exit;
10522 * KVM_REQ_HV_STIMER has to be processed after
10523 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10524 * depend on the guest clock being up-to-date
10526 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10527 kvm_hv_process_stimers(vcpu);
10528 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10529 kvm_vcpu_update_apicv(vcpu);
10530 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10531 kvm_check_async_pf_completion(vcpu);
10532 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10533 static_call(kvm_x86_msr_filter_changed)(vcpu);
10535 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10536 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10539 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10540 kvm_xen_has_interrupt(vcpu)) {
10541 ++vcpu->stat.req_event;
10542 r = kvm_apic_accept_events(vcpu);
10547 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10552 r = kvm_check_and_inject_events(vcpu, &req_immediate_exit);
10558 static_call(kvm_x86_enable_irq_window)(vcpu);
10560 if (kvm_lapic_enabled(vcpu)) {
10561 update_cr8_intercept(vcpu);
10562 kvm_lapic_sync_to_vapic(vcpu);
10566 r = kvm_mmu_reload(vcpu);
10568 goto cancel_injection;
10573 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10576 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10577 * IPI are then delayed after guest entry, which ensures that they
10578 * result in virtual interrupt delivery.
10580 local_irq_disable();
10582 /* Store vcpu->apicv_active before vcpu->mode. */
10583 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10585 kvm_vcpu_srcu_read_unlock(vcpu);
10588 * 1) We should set ->mode before checking ->requests. Please see
10589 * the comment in kvm_vcpu_exiting_guest_mode().
10591 * 2) For APICv, we should set ->mode before checking PID.ON. This
10592 * pairs with the memory barrier implicit in pi_test_and_set_on
10593 * (see vmx_deliver_posted_interrupt).
10595 * 3) This also orders the write to mode from any reads to the page
10596 * tables done while the VCPU is running. Please see the comment
10597 * in kvm_flush_remote_tlbs.
10599 smp_mb__after_srcu_read_unlock();
10602 * Process pending posted interrupts to handle the case where the
10603 * notification IRQ arrived in the host, or was never sent (because the
10604 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10605 * status, KVM doesn't update assigned devices when APICv is inhibited,
10606 * i.e. they can post interrupts even if APICv is temporarily disabled.
10608 if (kvm_lapic_enabled(vcpu))
10609 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10611 if (kvm_vcpu_exit_request(vcpu)) {
10612 vcpu->mode = OUTSIDE_GUEST_MODE;
10614 local_irq_enable();
10616 kvm_vcpu_srcu_read_lock(vcpu);
10618 goto cancel_injection;
10621 if (req_immediate_exit) {
10622 kvm_make_request(KVM_REQ_EVENT, vcpu);
10623 static_call(kvm_x86_request_immediate_exit)(vcpu);
10626 fpregs_assert_state_consistent();
10627 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10628 switch_fpu_return();
10630 if (vcpu->arch.guest_fpu.xfd_err)
10631 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10633 if (unlikely(vcpu->arch.switch_db_regs)) {
10634 set_debugreg(0, 7);
10635 set_debugreg(vcpu->arch.eff_db[0], 0);
10636 set_debugreg(vcpu->arch.eff_db[1], 1);
10637 set_debugreg(vcpu->arch.eff_db[2], 2);
10638 set_debugreg(vcpu->arch.eff_db[3], 3);
10639 } else if (unlikely(hw_breakpoint_active())) {
10640 set_debugreg(0, 7);
10643 guest_timing_enter_irqoff();
10647 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10648 * update must kick and wait for all vCPUs before toggling the
10649 * per-VM state, and responsing vCPUs must wait for the update
10650 * to complete before servicing KVM_REQ_APICV_UPDATE.
10652 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) &&
10653 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED));
10655 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10656 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10659 if (kvm_lapic_enabled(vcpu))
10660 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10662 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10663 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10669 * Do this here before restoring debug registers on the host. And
10670 * since we do this before handling the vmexit, a DR access vmexit
10671 * can (a) read the correct value of the debug registers, (b) set
10672 * KVM_DEBUGREG_WONT_EXIT again.
10674 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
10675 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
10676 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
10677 kvm_update_dr0123(vcpu);
10678 kvm_update_dr7(vcpu);
10682 * If the guest has used debug registers, at least dr7
10683 * will be disabled while returning to the host.
10684 * If we don't have active breakpoints in the host, we don't
10685 * care about the messed up debug address registers. But if
10686 * we have some of them active, restore the old state.
10688 if (hw_breakpoint_active())
10689 hw_breakpoint_restore();
10691 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
10692 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
10694 vcpu->mode = OUTSIDE_GUEST_MODE;
10698 * Sync xfd before calling handle_exit_irqoff() which may
10699 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
10700 * in #NM irqoff handler).
10702 if (vcpu->arch.xfd_no_write_intercept)
10703 fpu_sync_guest_vmexit_xfd_state();
10705 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
10707 if (vcpu->arch.guest_fpu.xfd_err)
10708 wrmsrl(MSR_IA32_XFD_ERR, 0);
10711 * Consume any pending interrupts, including the possible source of
10712 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
10713 * An instruction is required after local_irq_enable() to fully unblock
10714 * interrupts on processors that implement an interrupt shadow, the
10715 * stat.exits increment will do nicely.
10717 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
10718 local_irq_enable();
10719 ++vcpu->stat.exits;
10720 local_irq_disable();
10721 kvm_after_interrupt(vcpu);
10724 * Wait until after servicing IRQs to account guest time so that any
10725 * ticks that occurred while running the guest are properly accounted
10726 * to the guest. Waiting until IRQs are enabled degrades the accuracy
10727 * of accounting via context tracking, but the loss of accuracy is
10728 * acceptable for all known use cases.
10730 guest_timing_exit_irqoff();
10732 local_irq_enable();
10735 kvm_vcpu_srcu_read_lock(vcpu);
10738 * Profile KVM exit RIPs:
10740 if (unlikely(prof_on == KVM_PROFILING)) {
10741 unsigned long rip = kvm_rip_read(vcpu);
10742 profile_hit(KVM_PROFILING, (void *)rip);
10745 if (unlikely(vcpu->arch.tsc_always_catchup))
10746 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10748 if (vcpu->arch.apic_attention)
10749 kvm_lapic_sync_from_vapic(vcpu);
10751 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
10755 if (req_immediate_exit)
10756 kvm_make_request(KVM_REQ_EVENT, vcpu);
10757 static_call(kvm_x86_cancel_injection)(vcpu);
10758 if (unlikely(vcpu->arch.apic_attention))
10759 kvm_lapic_sync_from_vapic(vcpu);
10764 /* Called within kvm->srcu read side. */
10765 static inline int vcpu_block(struct kvm_vcpu *vcpu)
10769 if (!kvm_arch_vcpu_runnable(vcpu)) {
10771 * Switch to the software timer before halt-polling/blocking as
10772 * the guest's timer may be a break event for the vCPU, and the
10773 * hypervisor timer runs only when the CPU is in guest mode.
10774 * Switch before halt-polling so that KVM recognizes an expired
10775 * timer before blocking.
10777 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
10779 kvm_lapic_switch_to_sw_timer(vcpu);
10781 kvm_vcpu_srcu_read_unlock(vcpu);
10782 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10783 kvm_vcpu_halt(vcpu);
10785 kvm_vcpu_block(vcpu);
10786 kvm_vcpu_srcu_read_lock(vcpu);
10789 kvm_lapic_switch_to_hv_timer(vcpu);
10792 * If the vCPU is not runnable, a signal or another host event
10793 * of some kind is pending; service it without changing the
10794 * vCPU's activity state.
10796 if (!kvm_arch_vcpu_runnable(vcpu))
10801 * Evaluate nested events before exiting the halted state. This allows
10802 * the halt state to be recorded properly in the VMCS12's activity
10803 * state field (AMD does not have a similar field and a VM-Exit always
10804 * causes a spurious wakeup from HLT).
10806 if (is_guest_mode(vcpu)) {
10807 if (kvm_check_nested_events(vcpu) < 0)
10811 if (kvm_apic_accept_events(vcpu) < 0)
10813 switch(vcpu->arch.mp_state) {
10814 case KVM_MP_STATE_HALTED:
10815 case KVM_MP_STATE_AP_RESET_HOLD:
10816 vcpu->arch.pv.pv_unhalted = false;
10817 vcpu->arch.mp_state =
10818 KVM_MP_STATE_RUNNABLE;
10820 case KVM_MP_STATE_RUNNABLE:
10821 vcpu->arch.apf.halted = false;
10823 case KVM_MP_STATE_INIT_RECEIVED:
10832 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
10834 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
10835 !vcpu->arch.apf.halted);
10838 /* Called within kvm->srcu read side. */
10839 static int vcpu_run(struct kvm_vcpu *vcpu)
10843 vcpu->arch.l1tf_flush_l1d = true;
10847 * If another guest vCPU requests a PV TLB flush in the middle
10848 * of instruction emulation, the rest of the emulation could
10849 * use a stale page translation. Assume that any code after
10850 * this point can start executing an instruction.
10852 vcpu->arch.at_instruction_boundary = false;
10853 if (kvm_vcpu_running(vcpu)) {
10854 r = vcpu_enter_guest(vcpu);
10856 r = vcpu_block(vcpu);
10862 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
10863 if (kvm_xen_has_pending_events(vcpu))
10864 kvm_xen_inject_pending_events(vcpu);
10866 if (kvm_cpu_has_pending_timer(vcpu))
10867 kvm_inject_pending_timer_irqs(vcpu);
10869 if (dm_request_for_irq_injection(vcpu) &&
10870 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
10872 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
10873 ++vcpu->stat.request_irq_exits;
10877 if (__xfer_to_guest_mode_work_pending()) {
10878 kvm_vcpu_srcu_read_unlock(vcpu);
10879 r = xfer_to_guest_mode_handle_work(vcpu);
10880 kvm_vcpu_srcu_read_lock(vcpu);
10889 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
10891 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
10894 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
10896 BUG_ON(!vcpu->arch.pio.count);
10898 return complete_emulated_io(vcpu);
10902 * Implements the following, as a state machine:
10905 * for each fragment
10906 * for each mmio piece in the fragment
10913 * for each fragment
10914 * for each mmio piece in the fragment
10919 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
10921 struct kvm_run *run = vcpu->run;
10922 struct kvm_mmio_fragment *frag;
10925 BUG_ON(!vcpu->mmio_needed);
10927 /* Complete previous fragment */
10928 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
10929 len = min(8u, frag->len);
10930 if (!vcpu->mmio_is_write)
10931 memcpy(frag->data, run->mmio.data, len);
10933 if (frag->len <= 8) {
10934 /* Switch to the next fragment. */
10936 vcpu->mmio_cur_fragment++;
10938 /* Go forward to the next mmio piece. */
10944 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
10945 vcpu->mmio_needed = 0;
10947 /* FIXME: return into emulator if single-stepping. */
10948 if (vcpu->mmio_is_write)
10950 vcpu->mmio_read_completed = 1;
10951 return complete_emulated_io(vcpu);
10954 run->exit_reason = KVM_EXIT_MMIO;
10955 run->mmio.phys_addr = frag->gpa;
10956 if (vcpu->mmio_is_write)
10957 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
10958 run->mmio.len = min(8u, frag->len);
10959 run->mmio.is_write = vcpu->mmio_is_write;
10960 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
10964 /* Swap (qemu) user FPU context for the guest FPU context. */
10965 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
10967 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
10968 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
10972 /* When vcpu_run ends, restore user space FPU context. */
10973 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
10975 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
10976 ++vcpu->stat.fpu_reload;
10980 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
10982 struct kvm_queued_exception *ex = &vcpu->arch.exception;
10983 struct kvm_run *kvm_run = vcpu->run;
10987 kvm_sigset_activate(vcpu);
10988 kvm_run->flags = 0;
10989 kvm_load_guest_fpu(vcpu);
10991 kvm_vcpu_srcu_read_lock(vcpu);
10992 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
10993 if (kvm_run->immediate_exit) {
10998 * It should be impossible for the hypervisor timer to be in
10999 * use before KVM has ever run the vCPU.
11001 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu));
11003 kvm_vcpu_srcu_read_unlock(vcpu);
11004 kvm_vcpu_block(vcpu);
11005 kvm_vcpu_srcu_read_lock(vcpu);
11007 if (kvm_apic_accept_events(vcpu) < 0) {
11012 if (signal_pending(current)) {
11014 kvm_run->exit_reason = KVM_EXIT_INTR;
11015 ++vcpu->stat.signal_exits;
11020 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
11021 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
11026 if (kvm_run->kvm_dirty_regs) {
11027 r = sync_regs(vcpu);
11032 /* re-sync apic's tpr */
11033 if (!lapic_in_kernel(vcpu)) {
11034 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
11041 * If userspace set a pending exception and L2 is active, convert it to
11042 * a pending VM-Exit if L1 wants to intercept the exception.
11044 if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) &&
11045 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector,
11047 kvm_queue_exception_vmexit(vcpu, ex->vector,
11048 ex->has_error_code, ex->error_code,
11049 ex->has_payload, ex->payload);
11050 ex->injected = false;
11051 ex->pending = false;
11053 vcpu->arch.exception_from_userspace = false;
11055 if (unlikely(vcpu->arch.complete_userspace_io)) {
11056 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
11057 vcpu->arch.complete_userspace_io = NULL;
11062 WARN_ON_ONCE(vcpu->arch.pio.count);
11063 WARN_ON_ONCE(vcpu->mmio_needed);
11066 if (kvm_run->immediate_exit) {
11071 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
11075 r = vcpu_run(vcpu);
11078 kvm_put_guest_fpu(vcpu);
11079 if (kvm_run->kvm_valid_regs)
11081 post_kvm_run_save(vcpu);
11082 kvm_vcpu_srcu_read_unlock(vcpu);
11084 kvm_sigset_deactivate(vcpu);
11089 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11091 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
11093 * We are here if userspace calls get_regs() in the middle of
11094 * instruction emulation. Registers state needs to be copied
11095 * back from emulation context to vcpu. Userspace shouldn't do
11096 * that usually, but some bad designed PV devices (vmware
11097 * backdoor interface) need this to work
11099 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
11100 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11102 regs->rax = kvm_rax_read(vcpu);
11103 regs->rbx = kvm_rbx_read(vcpu);
11104 regs->rcx = kvm_rcx_read(vcpu);
11105 regs->rdx = kvm_rdx_read(vcpu);
11106 regs->rsi = kvm_rsi_read(vcpu);
11107 regs->rdi = kvm_rdi_read(vcpu);
11108 regs->rsp = kvm_rsp_read(vcpu);
11109 regs->rbp = kvm_rbp_read(vcpu);
11110 #ifdef CONFIG_X86_64
11111 regs->r8 = kvm_r8_read(vcpu);
11112 regs->r9 = kvm_r9_read(vcpu);
11113 regs->r10 = kvm_r10_read(vcpu);
11114 regs->r11 = kvm_r11_read(vcpu);
11115 regs->r12 = kvm_r12_read(vcpu);
11116 regs->r13 = kvm_r13_read(vcpu);
11117 regs->r14 = kvm_r14_read(vcpu);
11118 regs->r15 = kvm_r15_read(vcpu);
11121 regs->rip = kvm_rip_read(vcpu);
11122 regs->rflags = kvm_get_rflags(vcpu);
11125 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11128 __get_regs(vcpu, regs);
11133 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11135 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
11136 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11138 kvm_rax_write(vcpu, regs->rax);
11139 kvm_rbx_write(vcpu, regs->rbx);
11140 kvm_rcx_write(vcpu, regs->rcx);
11141 kvm_rdx_write(vcpu, regs->rdx);
11142 kvm_rsi_write(vcpu, regs->rsi);
11143 kvm_rdi_write(vcpu, regs->rdi);
11144 kvm_rsp_write(vcpu, regs->rsp);
11145 kvm_rbp_write(vcpu, regs->rbp);
11146 #ifdef CONFIG_X86_64
11147 kvm_r8_write(vcpu, regs->r8);
11148 kvm_r9_write(vcpu, regs->r9);
11149 kvm_r10_write(vcpu, regs->r10);
11150 kvm_r11_write(vcpu, regs->r11);
11151 kvm_r12_write(vcpu, regs->r12);
11152 kvm_r13_write(vcpu, regs->r13);
11153 kvm_r14_write(vcpu, regs->r14);
11154 kvm_r15_write(vcpu, regs->r15);
11157 kvm_rip_write(vcpu, regs->rip);
11158 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
11160 vcpu->arch.exception.pending = false;
11161 vcpu->arch.exception_vmexit.pending = false;
11163 kvm_make_request(KVM_REQ_EVENT, vcpu);
11166 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11169 __set_regs(vcpu, regs);
11174 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11176 struct desc_ptr dt;
11178 if (vcpu->arch.guest_state_protected)
11179 goto skip_protected_regs;
11181 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11182 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11183 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11184 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11185 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11186 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11188 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11189 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11191 static_call(kvm_x86_get_idt)(vcpu, &dt);
11192 sregs->idt.limit = dt.size;
11193 sregs->idt.base = dt.address;
11194 static_call(kvm_x86_get_gdt)(vcpu, &dt);
11195 sregs->gdt.limit = dt.size;
11196 sregs->gdt.base = dt.address;
11198 sregs->cr2 = vcpu->arch.cr2;
11199 sregs->cr3 = kvm_read_cr3(vcpu);
11201 skip_protected_regs:
11202 sregs->cr0 = kvm_read_cr0(vcpu);
11203 sregs->cr4 = kvm_read_cr4(vcpu);
11204 sregs->cr8 = kvm_get_cr8(vcpu);
11205 sregs->efer = vcpu->arch.efer;
11206 sregs->apic_base = kvm_get_apic_base(vcpu);
11209 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11211 __get_sregs_common(vcpu, sregs);
11213 if (vcpu->arch.guest_state_protected)
11216 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
11217 set_bit(vcpu->arch.interrupt.nr,
11218 (unsigned long *)sregs->interrupt_bitmap);
11221 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11225 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
11227 if (vcpu->arch.guest_state_protected)
11230 if (is_pae_paging(vcpu)) {
11231 for (i = 0 ; i < 4 ; i++)
11232 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
11233 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
11237 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
11238 struct kvm_sregs *sregs)
11241 __get_sregs(vcpu, sregs);
11246 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
11247 struct kvm_mp_state *mp_state)
11252 if (kvm_mpx_supported())
11253 kvm_load_guest_fpu(vcpu);
11255 r = kvm_apic_accept_events(vcpu);
11260 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
11261 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
11262 vcpu->arch.pv.pv_unhalted)
11263 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
11265 mp_state->mp_state = vcpu->arch.mp_state;
11268 if (kvm_mpx_supported())
11269 kvm_put_guest_fpu(vcpu);
11274 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
11275 struct kvm_mp_state *mp_state)
11281 switch (mp_state->mp_state) {
11282 case KVM_MP_STATE_UNINITIALIZED:
11283 case KVM_MP_STATE_HALTED:
11284 case KVM_MP_STATE_AP_RESET_HOLD:
11285 case KVM_MP_STATE_INIT_RECEIVED:
11286 case KVM_MP_STATE_SIPI_RECEIVED:
11287 if (!lapic_in_kernel(vcpu))
11291 case KVM_MP_STATE_RUNNABLE:
11299 * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow
11300 * forcing the guest into INIT/SIPI if those events are supposed to be
11301 * blocked. KVM prioritizes SMI over INIT, so reject INIT/SIPI state
11302 * if an SMI is pending as well.
11304 if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) &&
11305 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
11306 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
11309 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
11310 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
11311 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
11313 vcpu->arch.mp_state = mp_state->mp_state;
11314 kvm_make_request(KVM_REQ_EVENT, vcpu);
11322 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
11323 int reason, bool has_error_code, u32 error_code)
11325 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
11328 init_emulate_ctxt(vcpu);
11330 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
11331 has_error_code, error_code);
11333 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11334 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11335 vcpu->run->internal.ndata = 0;
11339 kvm_rip_write(vcpu, ctxt->eip);
11340 kvm_set_rflags(vcpu, ctxt->eflags);
11343 EXPORT_SYMBOL_GPL(kvm_task_switch);
11345 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11347 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
11349 * When EFER.LME and CR0.PG are set, the processor is in
11350 * 64-bit mode (though maybe in a 32-bit code segment).
11351 * CR4.PAE and EFER.LMA must be set.
11353 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
11355 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
11359 * Not in 64-bit mode: EFER.LMA is clear and the code
11360 * segment cannot be 64-bit.
11362 if (sregs->efer & EFER_LMA || sregs->cs.l)
11366 return kvm_is_valid_cr4(vcpu, sregs->cr4);
11369 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
11370 int *mmu_reset_needed, bool update_pdptrs)
11372 struct msr_data apic_base_msr;
11374 struct desc_ptr dt;
11376 if (!kvm_is_valid_sregs(vcpu, sregs))
11379 apic_base_msr.data = sregs->apic_base;
11380 apic_base_msr.host_initiated = true;
11381 if (kvm_set_apic_base(vcpu, &apic_base_msr))
11384 if (vcpu->arch.guest_state_protected)
11387 dt.size = sregs->idt.limit;
11388 dt.address = sregs->idt.base;
11389 static_call(kvm_x86_set_idt)(vcpu, &dt);
11390 dt.size = sregs->gdt.limit;
11391 dt.address = sregs->gdt.base;
11392 static_call(kvm_x86_set_gdt)(vcpu, &dt);
11394 vcpu->arch.cr2 = sregs->cr2;
11395 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
11396 vcpu->arch.cr3 = sregs->cr3;
11397 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11398 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
11400 kvm_set_cr8(vcpu, sregs->cr8);
11402 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
11403 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
11405 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
11406 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
11407 vcpu->arch.cr0 = sregs->cr0;
11409 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
11410 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
11412 if (update_pdptrs) {
11413 idx = srcu_read_lock(&vcpu->kvm->srcu);
11414 if (is_pae_paging(vcpu)) {
11415 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
11416 *mmu_reset_needed = 1;
11418 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11421 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11422 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11423 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11424 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11425 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11426 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11428 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11429 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11431 update_cr8_intercept(vcpu);
11433 /* Older userspace won't unhalt the vcpu on reset. */
11434 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
11435 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
11436 !is_protmode(vcpu))
11437 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11442 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11444 int pending_vec, max_bits;
11445 int mmu_reset_needed = 0;
11446 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
11451 if (mmu_reset_needed)
11452 kvm_mmu_reset_context(vcpu);
11454 max_bits = KVM_NR_INTERRUPTS;
11455 pending_vec = find_first_bit(
11456 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
11458 if (pending_vec < max_bits) {
11459 kvm_queue_interrupt(vcpu, pending_vec, false);
11460 pr_debug("Set back pending irq %d\n", pending_vec);
11461 kvm_make_request(KVM_REQ_EVENT, vcpu);
11466 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11468 int mmu_reset_needed = 0;
11469 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
11470 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
11471 !(sregs2->efer & EFER_LMA);
11474 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
11477 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
11480 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
11481 &mmu_reset_needed, !valid_pdptrs);
11485 if (valid_pdptrs) {
11486 for (i = 0; i < 4 ; i++)
11487 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
11489 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
11490 mmu_reset_needed = 1;
11491 vcpu->arch.pdptrs_from_userspace = true;
11493 if (mmu_reset_needed)
11494 kvm_mmu_reset_context(vcpu);
11498 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
11499 struct kvm_sregs *sregs)
11504 ret = __set_sregs(vcpu, sregs);
11509 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
11512 struct kvm_vcpu *vcpu;
11518 down_write(&kvm->arch.apicv_update_lock);
11520 kvm_for_each_vcpu(i, vcpu, kvm) {
11521 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
11526 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11527 up_write(&kvm->arch.apicv_update_lock);
11530 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11531 struct kvm_guest_debug *dbg)
11533 unsigned long rflags;
11536 if (vcpu->arch.guest_state_protected)
11541 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11543 if (kvm_is_exception_pending(vcpu))
11545 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11546 kvm_queue_exception(vcpu, DB_VECTOR);
11548 kvm_queue_exception(vcpu, BP_VECTOR);
11552 * Read rflags as long as potentially injected trace flags are still
11555 rflags = kvm_get_rflags(vcpu);
11557 vcpu->guest_debug = dbg->control;
11558 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11559 vcpu->guest_debug = 0;
11561 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11562 for (i = 0; i < KVM_NR_DB_REGS; ++i)
11563 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11564 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11566 for (i = 0; i < KVM_NR_DB_REGS; i++)
11567 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11569 kvm_update_dr7(vcpu);
11571 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11572 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11575 * Trigger an rflags update that will inject or remove the trace
11578 kvm_set_rflags(vcpu, rflags);
11580 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11582 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11592 * Translate a guest virtual address to a guest physical address.
11594 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11595 struct kvm_translation *tr)
11597 unsigned long vaddr = tr->linear_address;
11603 idx = srcu_read_lock(&vcpu->kvm->srcu);
11604 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11605 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11606 tr->physical_address = gpa;
11607 tr->valid = gpa != INVALID_GPA;
11615 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11617 struct fxregs_state *fxsave;
11619 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11624 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11625 memcpy(fpu->fpr, fxsave->st_space, 128);
11626 fpu->fcw = fxsave->cwd;
11627 fpu->fsw = fxsave->swd;
11628 fpu->ftwx = fxsave->twd;
11629 fpu->last_opcode = fxsave->fop;
11630 fpu->last_ip = fxsave->rip;
11631 fpu->last_dp = fxsave->rdp;
11632 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11638 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11640 struct fxregs_state *fxsave;
11642 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11647 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11649 memcpy(fxsave->st_space, fpu->fpr, 128);
11650 fxsave->cwd = fpu->fcw;
11651 fxsave->swd = fpu->fsw;
11652 fxsave->twd = fpu->ftwx;
11653 fxsave->fop = fpu->last_opcode;
11654 fxsave->rip = fpu->last_ip;
11655 fxsave->rdp = fpu->last_dp;
11656 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11662 static void store_regs(struct kvm_vcpu *vcpu)
11664 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
11666 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
11667 __get_regs(vcpu, &vcpu->run->s.regs.regs);
11669 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
11670 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
11672 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
11673 kvm_vcpu_ioctl_x86_get_vcpu_events(
11674 vcpu, &vcpu->run->s.regs.events);
11677 static int sync_regs(struct kvm_vcpu *vcpu)
11679 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
11680 __set_regs(vcpu, &vcpu->run->s.regs.regs);
11681 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
11683 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
11684 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
11686 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
11688 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
11689 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
11690 vcpu, &vcpu->run->s.regs.events))
11692 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
11698 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
11700 if (kvm_check_tsc_unstable() && kvm->created_vcpus)
11701 pr_warn_once("SMP vm created on host with unstable TSC; "
11702 "guest TSC will not be reliable\n");
11704 if (!kvm->arch.max_vcpu_ids)
11705 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS;
11707 if (id >= kvm->arch.max_vcpu_ids)
11710 return static_call(kvm_x86_vcpu_precreate)(kvm);
11713 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
11718 vcpu->arch.last_vmentry_cpu = -1;
11719 vcpu->arch.regs_avail = ~0;
11720 vcpu->arch.regs_dirty = ~0;
11722 kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm, vcpu, KVM_HOST_USES_PFN);
11724 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
11725 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11727 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
11729 r = kvm_mmu_create(vcpu);
11733 if (irqchip_in_kernel(vcpu->kvm)) {
11734 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
11736 goto fail_mmu_destroy;
11739 * Defer evaluating inhibits until the vCPU is first run, as
11740 * this vCPU will not get notified of any changes until this
11741 * vCPU is visible to other vCPUs (marked online and added to
11742 * the set of vCPUs). Opportunistically mark APICv active as
11743 * VMX in particularly is highly unlikely to have inhibits.
11744 * Ignore the current per-VM APICv state so that vCPU creation
11745 * is guaranteed to run with a deterministic value, the request
11746 * will ensure the vCPU gets the correct state before VM-Entry.
11748 if (enable_apicv) {
11749 vcpu->arch.apic->apicv_active = true;
11750 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
11753 static_branch_inc(&kvm_has_noapic_vcpu);
11757 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
11759 goto fail_free_lapic;
11760 vcpu->arch.pio_data = page_address(page);
11762 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64),
11763 GFP_KERNEL_ACCOUNT);
11764 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64),
11765 GFP_KERNEL_ACCOUNT);
11766 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks)
11767 goto fail_free_mce_banks;
11768 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
11770 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
11771 GFP_KERNEL_ACCOUNT))
11772 goto fail_free_mce_banks;
11774 if (!alloc_emulate_ctxt(vcpu))
11775 goto free_wbinvd_dirty_mask;
11777 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
11778 pr_err("failed to allocate vcpu's fpu\n");
11779 goto free_emulate_ctxt;
11782 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
11783 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
11785 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
11787 kvm_async_pf_hash_reset(vcpu);
11789 vcpu->arch.perf_capabilities = kvm_caps.supported_perf_cap;
11790 kvm_pmu_init(vcpu);
11792 vcpu->arch.pending_external_vector = -1;
11793 vcpu->arch.preempted_in_kernel = false;
11795 #if IS_ENABLED(CONFIG_HYPERV)
11796 vcpu->arch.hv_root_tdp = INVALID_PAGE;
11799 r = static_call(kvm_x86_vcpu_create)(vcpu);
11801 goto free_guest_fpu;
11803 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
11804 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
11805 kvm_xen_init_vcpu(vcpu);
11806 kvm_vcpu_mtrr_init(vcpu);
11808 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz);
11809 kvm_vcpu_reset(vcpu, false);
11810 kvm_init_mmu(vcpu);
11815 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11817 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11818 free_wbinvd_dirty_mask:
11819 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11820 fail_free_mce_banks:
11821 kfree(vcpu->arch.mce_banks);
11822 kfree(vcpu->arch.mci_ctl2_banks);
11823 free_page((unsigned long)vcpu->arch.pio_data);
11825 kvm_free_lapic(vcpu);
11827 kvm_mmu_destroy(vcpu);
11831 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
11833 struct kvm *kvm = vcpu->kvm;
11835 if (mutex_lock_killable(&vcpu->mutex))
11838 kvm_synchronize_tsc(vcpu, 0);
11841 /* poll control enabled by default */
11842 vcpu->arch.msr_kvm_poll_control = 1;
11844 mutex_unlock(&vcpu->mutex);
11846 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
11847 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
11848 KVMCLOCK_SYNC_PERIOD);
11851 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
11855 kvmclock_reset(vcpu);
11857 static_call(kvm_x86_vcpu_free)(vcpu);
11859 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11860 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11861 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11863 kvm_xen_destroy_vcpu(vcpu);
11864 kvm_hv_vcpu_uninit(vcpu);
11865 kvm_pmu_destroy(vcpu);
11866 kfree(vcpu->arch.mce_banks);
11867 kfree(vcpu->arch.mci_ctl2_banks);
11868 kvm_free_lapic(vcpu);
11869 idx = srcu_read_lock(&vcpu->kvm->srcu);
11870 kvm_mmu_destroy(vcpu);
11871 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11872 free_page((unsigned long)vcpu->arch.pio_data);
11873 kvfree(vcpu->arch.cpuid_entries);
11874 if (!lapic_in_kernel(vcpu))
11875 static_branch_dec(&kvm_has_noapic_vcpu);
11878 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
11880 struct kvm_cpuid_entry2 *cpuid_0x1;
11881 unsigned long old_cr0 = kvm_read_cr0(vcpu);
11882 unsigned long new_cr0;
11885 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
11886 * to handle side effects. RESET emulation hits those flows and relies
11887 * on emulated/virtualized registers, including those that are loaded
11888 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
11889 * to detect improper or missing initialization.
11891 WARN_ON_ONCE(!init_event &&
11892 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
11895 * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's
11896 * possible to INIT the vCPU while L2 is active. Force the vCPU back
11897 * into L1 as EFER.SVME is cleared on INIT (along with all other EFER
11898 * bits), i.e. virtualization is disabled.
11900 if (is_guest_mode(vcpu))
11901 kvm_leave_nested(vcpu);
11903 kvm_lapic_reset(vcpu, init_event);
11905 WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu));
11906 vcpu->arch.hflags = 0;
11908 vcpu->arch.smi_pending = 0;
11909 vcpu->arch.smi_count = 0;
11910 atomic_set(&vcpu->arch.nmi_queued, 0);
11911 vcpu->arch.nmi_pending = 0;
11912 vcpu->arch.nmi_injected = false;
11913 kvm_clear_interrupt_queue(vcpu);
11914 kvm_clear_exception_queue(vcpu);
11916 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
11917 kvm_update_dr0123(vcpu);
11918 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
11919 vcpu->arch.dr7 = DR7_FIXED_1;
11920 kvm_update_dr7(vcpu);
11922 vcpu->arch.cr2 = 0;
11924 kvm_make_request(KVM_REQ_EVENT, vcpu);
11925 vcpu->arch.apf.msr_en_val = 0;
11926 vcpu->arch.apf.msr_int_val = 0;
11927 vcpu->arch.st.msr_val = 0;
11929 kvmclock_reset(vcpu);
11931 kvm_clear_async_pf_completion_queue(vcpu);
11932 kvm_async_pf_hash_reset(vcpu);
11933 vcpu->arch.apf.halted = false;
11935 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
11936 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
11939 * All paths that lead to INIT are required to load the guest's
11940 * FPU state (because most paths are buried in KVM_RUN).
11943 kvm_put_guest_fpu(vcpu);
11945 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
11946 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
11949 kvm_load_guest_fpu(vcpu);
11953 kvm_pmu_reset(vcpu);
11954 vcpu->arch.smbase = 0x30000;
11956 vcpu->arch.msr_misc_features_enables = 0;
11957 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
11958 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
11960 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
11961 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
11964 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
11965 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
11966 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
11969 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
11970 * if no CPUID match is found. Note, it's impossible to get a match at
11971 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
11972 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
11973 * on RESET. But, go through the motions in case that's ever remedied.
11975 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1);
11976 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
11978 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
11980 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
11981 kvm_rip_write(vcpu, 0xfff0);
11983 vcpu->arch.cr3 = 0;
11984 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11987 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
11988 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
11989 * (or qualify) that with a footnote stating that CD/NW are preserved.
11991 new_cr0 = X86_CR0_ET;
11993 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
11995 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
11997 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
11998 static_call(kvm_x86_set_cr4)(vcpu, 0);
11999 static_call(kvm_x86_set_efer)(vcpu, 0);
12000 static_call(kvm_x86_update_exception_bitmap)(vcpu);
12003 * On the standard CR0/CR4/EFER modification paths, there are several
12004 * complex conditions determining whether the MMU has to be reset and/or
12005 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
12006 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
12007 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
12008 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
12010 if (old_cr0 & X86_CR0_PG) {
12011 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12012 kvm_mmu_reset_context(vcpu);
12016 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
12017 * APM states the TLBs are untouched by INIT, but it also states that
12018 * the TLBs are flushed on "External initialization of the processor."
12019 * Flush the guest TLB regardless of vendor, there is no meaningful
12020 * benefit in relying on the guest to flush the TLB immediately after
12021 * INIT. A spurious TLB flush is benign and likely negligible from a
12022 * performance perspective.
12025 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12027 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
12029 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
12031 struct kvm_segment cs;
12033 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
12034 cs.selector = vector << 8;
12035 cs.base = vector << 12;
12036 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
12037 kvm_rip_write(vcpu, 0);
12039 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
12041 int kvm_arch_hardware_enable(void)
12044 struct kvm_vcpu *vcpu;
12049 bool stable, backwards_tsc = false;
12051 kvm_user_return_msr_cpu_online();
12053 ret = kvm_x86_check_processor_compatibility();
12057 ret = static_call(kvm_x86_hardware_enable)();
12061 local_tsc = rdtsc();
12062 stable = !kvm_check_tsc_unstable();
12063 list_for_each_entry(kvm, &vm_list, vm_list) {
12064 kvm_for_each_vcpu(i, vcpu, kvm) {
12065 if (!stable && vcpu->cpu == smp_processor_id())
12066 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
12067 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
12068 backwards_tsc = true;
12069 if (vcpu->arch.last_host_tsc > max_tsc)
12070 max_tsc = vcpu->arch.last_host_tsc;
12076 * Sometimes, even reliable TSCs go backwards. This happens on
12077 * platforms that reset TSC during suspend or hibernate actions, but
12078 * maintain synchronization. We must compensate. Fortunately, we can
12079 * detect that condition here, which happens early in CPU bringup,
12080 * before any KVM threads can be running. Unfortunately, we can't
12081 * bring the TSCs fully up to date with real time, as we aren't yet far
12082 * enough into CPU bringup that we know how much real time has actually
12083 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
12084 * variables that haven't been updated yet.
12086 * So we simply find the maximum observed TSC above, then record the
12087 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
12088 * the adjustment will be applied. Note that we accumulate
12089 * adjustments, in case multiple suspend cycles happen before some VCPU
12090 * gets a chance to run again. In the event that no KVM threads get a
12091 * chance to run, we will miss the entire elapsed period, as we'll have
12092 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
12093 * loose cycle time. This isn't too big a deal, since the loss will be
12094 * uniform across all VCPUs (not to mention the scenario is extremely
12095 * unlikely). It is possible that a second hibernate recovery happens
12096 * much faster than a first, causing the observed TSC here to be
12097 * smaller; this would require additional padding adjustment, which is
12098 * why we set last_host_tsc to the local tsc observed here.
12100 * N.B. - this code below runs only on platforms with reliable TSC,
12101 * as that is the only way backwards_tsc is set above. Also note
12102 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
12103 * have the same delta_cyc adjustment applied if backwards_tsc
12104 * is detected. Note further, this adjustment is only done once,
12105 * as we reset last_host_tsc on all VCPUs to stop this from being
12106 * called multiple times (one for each physical CPU bringup).
12108 * Platforms with unreliable TSCs don't have to deal with this, they
12109 * will be compensated by the logic in vcpu_load, which sets the TSC to
12110 * catchup mode. This will catchup all VCPUs to real time, but cannot
12111 * guarantee that they stay in perfect synchronization.
12113 if (backwards_tsc) {
12114 u64 delta_cyc = max_tsc - local_tsc;
12115 list_for_each_entry(kvm, &vm_list, vm_list) {
12116 kvm->arch.backwards_tsc_observed = true;
12117 kvm_for_each_vcpu(i, vcpu, kvm) {
12118 vcpu->arch.tsc_offset_adjustment += delta_cyc;
12119 vcpu->arch.last_host_tsc = local_tsc;
12120 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
12124 * We have to disable TSC offset matching.. if you were
12125 * booting a VM while issuing an S4 host suspend....
12126 * you may have some problem. Solving this issue is
12127 * left as an exercise to the reader.
12129 kvm->arch.last_tsc_nsec = 0;
12130 kvm->arch.last_tsc_write = 0;
12137 void kvm_arch_hardware_disable(void)
12139 static_call(kvm_x86_hardware_disable)();
12140 drop_user_return_notifiers();
12143 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
12145 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
12148 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
12150 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
12153 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
12154 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
12156 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
12158 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
12160 vcpu->arch.l1tf_flush_l1d = true;
12161 if (pmu->version && unlikely(pmu->event_count)) {
12162 pmu->need_cleanup = true;
12163 kvm_make_request(KVM_REQ_PMU, vcpu);
12165 static_call(kvm_x86_sched_in)(vcpu, cpu);
12168 void kvm_arch_free_vm(struct kvm *kvm)
12170 kfree(to_kvm_hv(kvm)->hv_pa_pg);
12171 __kvm_arch_free_vm(kvm);
12175 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
12178 unsigned long flags;
12183 ret = kvm_page_track_init(kvm);
12187 ret = kvm_mmu_init_vm(kvm);
12189 goto out_page_track;
12191 ret = static_call(kvm_x86_vm_init)(kvm);
12193 goto out_uninit_mmu;
12195 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
12196 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
12197 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
12199 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
12200 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
12201 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
12202 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
12203 &kvm->arch.irq_sources_bitmap);
12205 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
12206 mutex_init(&kvm->arch.apic_map_lock);
12207 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
12208 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
12210 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
12211 pvclock_update_vm_gtod_copy(kvm);
12212 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
12214 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz;
12215 kvm->arch.guest_can_read_msr_platform_info = true;
12216 kvm->arch.enable_pmu = enable_pmu;
12218 #if IS_ENABLED(CONFIG_HYPERV)
12219 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
12220 kvm->arch.hv_root_tdp = INVALID_PAGE;
12223 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
12224 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
12226 kvm_apicv_init(kvm);
12227 kvm_hv_init_vm(kvm);
12228 kvm_xen_init_vm(kvm);
12233 kvm_mmu_uninit_vm(kvm);
12235 kvm_page_track_cleanup(kvm);
12240 int kvm_arch_post_init_vm(struct kvm *kvm)
12242 return kvm_mmu_post_init_vm(kvm);
12245 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
12248 kvm_mmu_unload(vcpu);
12252 static void kvm_unload_vcpu_mmus(struct kvm *kvm)
12255 struct kvm_vcpu *vcpu;
12257 kvm_for_each_vcpu(i, vcpu, kvm) {
12258 kvm_clear_async_pf_completion_queue(vcpu);
12259 kvm_unload_vcpu_mmu(vcpu);
12263 void kvm_arch_sync_events(struct kvm *kvm)
12265 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
12266 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
12271 * __x86_set_memory_region: Setup KVM internal memory slot
12273 * @kvm: the kvm pointer to the VM.
12274 * @id: the slot ID to setup.
12275 * @gpa: the GPA to install the slot (unused when @size == 0).
12276 * @size: the size of the slot. Set to zero to uninstall a slot.
12278 * This function helps to setup a KVM internal memory slot. Specify
12279 * @size > 0 to install a new slot, while @size == 0 to uninstall a
12280 * slot. The return code can be one of the following:
12282 * HVA: on success (uninstall will return a bogus HVA)
12285 * The caller should always use IS_ERR() to check the return value
12286 * before use. Note, the KVM internal memory slots are guaranteed to
12287 * remain valid and unchanged until the VM is destroyed, i.e., the
12288 * GPA->HVA translation will not change. However, the HVA is a user
12289 * address, i.e. its accessibility is not guaranteed, and must be
12290 * accessed via __copy_{to,from}_user().
12292 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
12296 unsigned long hva, old_npages;
12297 struct kvm_memslots *slots = kvm_memslots(kvm);
12298 struct kvm_memory_slot *slot;
12300 /* Called with kvm->slots_lock held. */
12301 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
12302 return ERR_PTR_USR(-EINVAL);
12304 slot = id_to_memslot(slots, id);
12306 if (slot && slot->npages)
12307 return ERR_PTR_USR(-EEXIST);
12310 * MAP_SHARED to prevent internal slot pages from being moved
12313 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
12314 MAP_SHARED | MAP_ANONYMOUS, 0);
12315 if (IS_ERR_VALUE(hva))
12316 return (void __user *)hva;
12318 if (!slot || !slot->npages)
12321 old_npages = slot->npages;
12322 hva = slot->userspace_addr;
12325 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
12326 struct kvm_userspace_memory_region m;
12328 m.slot = id | (i << 16);
12330 m.guest_phys_addr = gpa;
12331 m.userspace_addr = hva;
12332 m.memory_size = size;
12333 r = __kvm_set_memory_region(kvm, &m);
12335 return ERR_PTR_USR(r);
12339 vm_munmap(hva, old_npages * PAGE_SIZE);
12341 return (void __user *)hva;
12343 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
12345 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
12347 kvm_mmu_pre_destroy_vm(kvm);
12350 void kvm_arch_destroy_vm(struct kvm *kvm)
12352 if (current->mm == kvm->mm) {
12354 * Free memory regions allocated on behalf of userspace,
12355 * unless the memory map has changed due to process exit
12358 mutex_lock(&kvm->slots_lock);
12359 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
12361 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
12363 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
12364 mutex_unlock(&kvm->slots_lock);
12366 kvm_unload_vcpu_mmus(kvm);
12367 static_call_cond(kvm_x86_vm_destroy)(kvm);
12368 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
12369 kvm_pic_destroy(kvm);
12370 kvm_ioapic_destroy(kvm);
12371 kvm_destroy_vcpus(kvm);
12372 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
12373 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
12374 kvm_mmu_uninit_vm(kvm);
12375 kvm_page_track_cleanup(kvm);
12376 kvm_xen_destroy_vm(kvm);
12377 kvm_hv_destroy_vm(kvm);
12380 static void memslot_rmap_free(struct kvm_memory_slot *slot)
12384 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12385 kvfree(slot->arch.rmap[i]);
12386 slot->arch.rmap[i] = NULL;
12390 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
12394 memslot_rmap_free(slot);
12396 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12397 kvfree(slot->arch.lpage_info[i - 1]);
12398 slot->arch.lpage_info[i - 1] = NULL;
12401 kvm_page_track_free_memslot(slot);
12404 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
12406 const int sz = sizeof(*slot->arch.rmap[0]);
12409 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12411 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12413 if (slot->arch.rmap[i])
12416 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
12417 if (!slot->arch.rmap[i]) {
12418 memslot_rmap_free(slot);
12426 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
12427 struct kvm_memory_slot *slot)
12429 unsigned long npages = slot->npages;
12433 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
12434 * old arrays will be freed by __kvm_set_memory_region() if installing
12435 * the new memslot is successful.
12437 memset(&slot->arch, 0, sizeof(slot->arch));
12439 if (kvm_memslots_have_rmaps(kvm)) {
12440 r = memslot_rmap_alloc(slot, npages);
12445 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12446 struct kvm_lpage_info *linfo;
12447 unsigned long ugfn;
12451 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12453 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
12457 slot->arch.lpage_info[i - 1] = linfo;
12459 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
12460 linfo[0].disallow_lpage = 1;
12461 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
12462 linfo[lpages - 1].disallow_lpage = 1;
12463 ugfn = slot->userspace_addr >> PAGE_SHIFT;
12465 * If the gfn and userspace address are not aligned wrt each
12466 * other, disable large page support for this slot.
12468 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
12471 for (j = 0; j < lpages; ++j)
12472 linfo[j].disallow_lpage = 1;
12476 if (kvm_page_track_create_memslot(kvm, slot, npages))
12482 memslot_rmap_free(slot);
12484 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12485 kvfree(slot->arch.lpage_info[i - 1]);
12486 slot->arch.lpage_info[i - 1] = NULL;
12491 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
12493 struct kvm_vcpu *vcpu;
12497 * memslots->generation has been incremented.
12498 * mmio generation may have reached its maximum value.
12500 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
12502 /* Force re-initialization of steal_time cache */
12503 kvm_for_each_vcpu(i, vcpu, kvm)
12504 kvm_vcpu_kick(vcpu);
12507 int kvm_arch_prepare_memory_region(struct kvm *kvm,
12508 const struct kvm_memory_slot *old,
12509 struct kvm_memory_slot *new,
12510 enum kvm_mr_change change)
12512 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
12513 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
12516 return kvm_alloc_memslot_metadata(kvm, new);
12519 if (change == KVM_MR_FLAGS_ONLY)
12520 memcpy(&new->arch, &old->arch, sizeof(old->arch));
12521 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12528 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12532 if (!kvm_x86_ops.cpu_dirty_log_size)
12535 nr_slots = atomic_read(&kvm->nr_memslots_dirty_logging);
12536 if ((enable && nr_slots == 1) || !nr_slots)
12537 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12540 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12541 struct kvm_memory_slot *old,
12542 const struct kvm_memory_slot *new,
12543 enum kvm_mr_change change)
12545 u32 old_flags = old ? old->flags : 0;
12546 u32 new_flags = new ? new->flags : 0;
12547 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12550 * Update CPU dirty logging if dirty logging is being toggled. This
12551 * applies to all operations.
12553 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12554 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12557 * Nothing more to do for RO slots (which can't be dirtied and can't be
12558 * made writable) or CREATE/MOVE/DELETE of a slot.
12560 * For a memslot with dirty logging disabled:
12561 * CREATE: No dirty mappings will already exist.
12562 * MOVE/DELETE: The old mappings will already have been cleaned up by
12563 * kvm_arch_flush_shadow_memslot()
12565 * For a memslot with dirty logging enabled:
12566 * CREATE: No shadow pages exist, thus nothing to write-protect
12567 * and no dirty bits to clear.
12568 * MOVE/DELETE: The old mappings will already have been cleaned up by
12569 * kvm_arch_flush_shadow_memslot().
12571 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12575 * READONLY and non-flags changes were filtered out above, and the only
12576 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12577 * logging isn't being toggled on or off.
12579 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12582 if (!log_dirty_pages) {
12584 * Dirty logging tracks sptes in 4k granularity, meaning that
12585 * large sptes have to be split. If live migration succeeds,
12586 * the guest in the source machine will be destroyed and large
12587 * sptes will be created in the destination. However, if the
12588 * guest continues to run in the source machine (for example if
12589 * live migration fails), small sptes will remain around and
12590 * cause bad performance.
12592 * Scan sptes if dirty logging has been stopped, dropping those
12593 * which can be collapsed into a single large-page spte. Later
12594 * page faults will create the large-page sptes.
12596 kvm_mmu_zap_collapsible_sptes(kvm, new);
12599 * Initially-all-set does not require write protecting any page,
12600 * because they're all assumed to be dirty.
12602 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12605 if (READ_ONCE(eager_page_split))
12606 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12608 if (kvm_x86_ops.cpu_dirty_log_size) {
12609 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12610 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12612 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12616 * Unconditionally flush the TLBs after enabling dirty logging.
12617 * A flush is almost always going to be necessary (see below),
12618 * and unconditionally flushing allows the helpers to omit
12619 * the subtly complex checks when removing write access.
12621 * Do the flush outside of mmu_lock to reduce the amount of
12622 * time mmu_lock is held. Flushing after dropping mmu_lock is
12623 * safe as KVM only needs to guarantee the slot is fully
12624 * write-protected before returning to userspace, i.e. before
12625 * userspace can consume the dirty status.
12627 * Flushing outside of mmu_lock requires KVM to be careful when
12628 * making decisions based on writable status of an SPTE, e.g. a
12629 * !writable SPTE doesn't guarantee a CPU can't perform writes.
12631 * Specifically, KVM also write-protects guest page tables to
12632 * monitor changes when using shadow paging, and must guarantee
12633 * no CPUs can write to those page before mmu_lock is dropped.
12634 * Because CPUs may have stale TLB entries at this point, a
12635 * !writable SPTE doesn't guarantee CPUs can't perform writes.
12637 * KVM also allows making SPTES writable outside of mmu_lock,
12638 * e.g. to allow dirty logging without taking mmu_lock.
12640 * To handle these scenarios, KVM uses a separate software-only
12641 * bit (MMU-writable) to track if a SPTE is !writable due to
12642 * a guest page table being write-protected (KVM clears the
12643 * MMU-writable flag when write-protecting for shadow paging).
12645 * The use of MMU-writable is also the primary motivation for
12646 * the unconditional flush. Because KVM must guarantee that a
12647 * CPU doesn't contain stale, writable TLB entries for a
12648 * !MMU-writable SPTE, KVM must flush if it encounters any
12649 * MMU-writable SPTE regardless of whether the actual hardware
12650 * writable bit was set. I.e. KVM is almost guaranteed to need
12651 * to flush, while unconditionally flushing allows the "remove
12652 * write access" helpers to ignore MMU-writable entirely.
12654 * See is_writable_pte() for more details (the case involving
12655 * access-tracked SPTEs is particularly relevant).
12657 kvm_arch_flush_remote_tlbs_memslot(kvm, new);
12661 void kvm_arch_commit_memory_region(struct kvm *kvm,
12662 struct kvm_memory_slot *old,
12663 const struct kvm_memory_slot *new,
12664 enum kvm_mr_change change)
12666 if (!kvm->arch.n_requested_mmu_pages &&
12667 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
12668 unsigned long nr_mmu_pages;
12670 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
12671 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
12672 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
12675 kvm_mmu_slot_apply_flags(kvm, old, new, change);
12677 /* Free the arrays associated with the old memslot. */
12678 if (change == KVM_MR_MOVE)
12679 kvm_arch_free_memslot(kvm, old);
12682 void kvm_arch_flush_shadow_all(struct kvm *kvm)
12684 kvm_mmu_zap_all(kvm);
12687 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
12688 struct kvm_memory_slot *slot)
12690 kvm_page_track_flush_slot(kvm, slot);
12693 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
12695 return (is_guest_mode(vcpu) &&
12696 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
12699 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
12701 if (!list_empty_careful(&vcpu->async_pf.done))
12704 if (kvm_apic_has_pending_init_or_sipi(vcpu) &&
12705 kvm_apic_init_sipi_allowed(vcpu))
12708 if (vcpu->arch.pv.pv_unhalted)
12711 if (kvm_is_exception_pending(vcpu))
12714 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12715 (vcpu->arch.nmi_pending &&
12716 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
12719 #ifdef CONFIG_KVM_SMM
12720 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
12721 (vcpu->arch.smi_pending &&
12722 static_call(kvm_x86_smi_allowed)(vcpu, false)))
12726 if (kvm_arch_interrupt_allowed(vcpu) &&
12727 (kvm_cpu_has_interrupt(vcpu) ||
12728 kvm_guest_apic_has_interrupt(vcpu)))
12731 if (kvm_hv_has_stimer_pending(vcpu))
12734 if (is_guest_mode(vcpu) &&
12735 kvm_x86_ops.nested_ops->has_events &&
12736 kvm_x86_ops.nested_ops->has_events(vcpu))
12739 if (kvm_xen_has_pending_events(vcpu))
12745 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
12747 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
12750 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
12752 if (kvm_vcpu_apicv_active(vcpu) &&
12753 static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
12759 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
12761 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
12764 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12765 #ifdef CONFIG_KVM_SMM
12766 kvm_test_request(KVM_REQ_SMI, vcpu) ||
12768 kvm_test_request(KVM_REQ_EVENT, vcpu))
12771 return kvm_arch_dy_has_pending_interrupt(vcpu);
12774 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
12776 if (vcpu->arch.guest_state_protected)
12779 return vcpu->arch.preempted_in_kernel;
12782 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
12784 return kvm_rip_read(vcpu);
12787 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
12789 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
12792 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
12794 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
12797 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
12799 /* Can't read the RIP when guest state is protected, just return 0 */
12800 if (vcpu->arch.guest_state_protected)
12803 if (is_64_bit_mode(vcpu))
12804 return kvm_rip_read(vcpu);
12805 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
12806 kvm_rip_read(vcpu));
12808 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
12810 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
12812 return kvm_get_linear_rip(vcpu) == linear_rip;
12814 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
12816 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
12818 unsigned long rflags;
12820 rflags = static_call(kvm_x86_get_rflags)(vcpu);
12821 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
12822 rflags &= ~X86_EFLAGS_TF;
12825 EXPORT_SYMBOL_GPL(kvm_get_rflags);
12827 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12829 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
12830 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
12831 rflags |= X86_EFLAGS_TF;
12832 static_call(kvm_x86_set_rflags)(vcpu, rflags);
12835 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12837 __kvm_set_rflags(vcpu, rflags);
12838 kvm_make_request(KVM_REQ_EVENT, vcpu);
12840 EXPORT_SYMBOL_GPL(kvm_set_rflags);
12842 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
12844 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
12846 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
12849 static inline u32 kvm_async_pf_next_probe(u32 key)
12851 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
12854 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12856 u32 key = kvm_async_pf_hash_fn(gfn);
12858 while (vcpu->arch.apf.gfns[key] != ~0)
12859 key = kvm_async_pf_next_probe(key);
12861 vcpu->arch.apf.gfns[key] = gfn;
12864 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
12867 u32 key = kvm_async_pf_hash_fn(gfn);
12869 for (i = 0; i < ASYNC_PF_PER_VCPU &&
12870 (vcpu->arch.apf.gfns[key] != gfn &&
12871 vcpu->arch.apf.gfns[key] != ~0); i++)
12872 key = kvm_async_pf_next_probe(key);
12877 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12879 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
12882 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12886 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
12888 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
12892 vcpu->arch.apf.gfns[i] = ~0;
12894 j = kvm_async_pf_next_probe(j);
12895 if (vcpu->arch.apf.gfns[j] == ~0)
12897 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
12899 * k lies cyclically in ]i,j]
12901 * |....j i.k.| or |.k..j i...|
12903 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
12904 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
12909 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
12911 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
12913 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
12917 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
12919 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12921 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12922 &token, offset, sizeof(token));
12925 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
12927 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12930 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12931 &val, offset, sizeof(val)))
12937 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
12940 if (!kvm_pv_async_pf_enabled(vcpu))
12943 if (vcpu->arch.apf.send_user_only &&
12944 static_call(kvm_x86_get_cpl)(vcpu) == 0)
12947 if (is_guest_mode(vcpu)) {
12949 * L1 needs to opt into the special #PF vmexits that are
12950 * used to deliver async page faults.
12952 return vcpu->arch.apf.delivery_as_pf_vmexit;
12955 * Play it safe in case the guest temporarily disables paging.
12956 * The real mode IDT in particular is unlikely to have a #PF
12959 return is_paging(vcpu);
12963 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
12965 if (unlikely(!lapic_in_kernel(vcpu) ||
12966 kvm_event_needs_reinjection(vcpu) ||
12967 kvm_is_exception_pending(vcpu)))
12970 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
12974 * If interrupts are off we cannot even use an artificial
12977 return kvm_arch_interrupt_allowed(vcpu);
12980 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
12981 struct kvm_async_pf *work)
12983 struct x86_exception fault;
12985 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
12986 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
12988 if (kvm_can_deliver_async_pf(vcpu) &&
12989 !apf_put_user_notpresent(vcpu)) {
12990 fault.vector = PF_VECTOR;
12991 fault.error_code_valid = true;
12992 fault.error_code = 0;
12993 fault.nested_page_fault = false;
12994 fault.address = work->arch.token;
12995 fault.async_page_fault = true;
12996 kvm_inject_page_fault(vcpu, &fault);
13000 * It is not possible to deliver a paravirtualized asynchronous
13001 * page fault, but putting the guest in an artificial halt state
13002 * can be beneficial nevertheless: if an interrupt arrives, we
13003 * can deliver it timely and perhaps the guest will schedule
13004 * another process. When the instruction that triggered a page
13005 * fault is retried, hopefully the page will be ready in the host.
13007 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
13012 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
13013 struct kvm_async_pf *work)
13015 struct kvm_lapic_irq irq = {
13016 .delivery_mode = APIC_DM_FIXED,
13017 .vector = vcpu->arch.apf.vec
13020 if (work->wakeup_all)
13021 work->arch.token = ~0; /* broadcast wakeup */
13023 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
13024 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
13026 if ((work->wakeup_all || work->notpresent_injected) &&
13027 kvm_pv_async_pf_enabled(vcpu) &&
13028 !apf_put_user_ready(vcpu, work->arch.token)) {
13029 vcpu->arch.apf.pageready_pending = true;
13030 kvm_apic_set_irq(vcpu, &irq, NULL);
13033 vcpu->arch.apf.halted = false;
13034 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13037 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
13039 kvm_make_request(KVM_REQ_APF_READY, vcpu);
13040 if (!vcpu->arch.apf.pageready_pending)
13041 kvm_vcpu_kick(vcpu);
13044 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
13046 if (!kvm_pv_async_pf_enabled(vcpu))
13049 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
13052 void kvm_arch_start_assignment(struct kvm *kvm)
13054 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
13055 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
13057 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
13059 void kvm_arch_end_assignment(struct kvm *kvm)
13061 atomic_dec(&kvm->arch.assigned_device_count);
13063 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
13065 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm)
13067 return arch_atomic_read(&kvm->arch.assigned_device_count);
13069 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
13071 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
13073 atomic_inc(&kvm->arch.noncoherent_dma_count);
13075 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
13077 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
13079 atomic_dec(&kvm->arch.noncoherent_dma_count);
13081 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
13083 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
13085 return atomic_read(&kvm->arch.noncoherent_dma_count);
13087 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
13089 bool kvm_arch_has_irq_bypass(void)
13094 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
13095 struct irq_bypass_producer *prod)
13097 struct kvm_kernel_irqfd *irqfd =
13098 container_of(cons, struct kvm_kernel_irqfd, consumer);
13101 irqfd->producer = prod;
13102 kvm_arch_start_assignment(irqfd->kvm);
13103 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
13104 prod->irq, irqfd->gsi, 1);
13107 kvm_arch_end_assignment(irqfd->kvm);
13112 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
13113 struct irq_bypass_producer *prod)
13116 struct kvm_kernel_irqfd *irqfd =
13117 container_of(cons, struct kvm_kernel_irqfd, consumer);
13119 WARN_ON(irqfd->producer != prod);
13120 irqfd->producer = NULL;
13123 * When producer of consumer is unregistered, we change back to
13124 * remapped mode, so we can re-use the current implementation
13125 * when the irq is masked/disabled or the consumer side (KVM
13126 * int this case doesn't want to receive the interrupts.
13128 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
13130 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
13131 " fails: %d\n", irqfd->consumer.token, ret);
13133 kvm_arch_end_assignment(irqfd->kvm);
13136 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
13137 uint32_t guest_irq, bool set)
13139 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
13142 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
13143 struct kvm_kernel_irq_routing_entry *new)
13145 if (new->type != KVM_IRQ_ROUTING_MSI)
13148 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
13151 bool kvm_vector_hashing_enabled(void)
13153 return vector_hashing;
13156 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
13158 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
13160 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
13163 int kvm_spec_ctrl_test_value(u64 value)
13166 * test that setting IA32_SPEC_CTRL to given value
13167 * is allowed by the host processor
13171 unsigned long flags;
13174 local_irq_save(flags);
13176 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
13178 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
13181 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
13183 local_irq_restore(flags);
13187 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
13189 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
13191 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
13192 struct x86_exception fault;
13193 u64 access = error_code &
13194 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
13196 if (!(error_code & PFERR_PRESENT_MASK) ||
13197 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) {
13199 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
13200 * tables probably do not match the TLB. Just proceed
13201 * with the error code that the processor gave.
13203 fault.vector = PF_VECTOR;
13204 fault.error_code_valid = true;
13205 fault.error_code = error_code;
13206 fault.nested_page_fault = false;
13207 fault.address = gva;
13208 fault.async_page_fault = false;
13210 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
13212 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
13215 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
13216 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
13217 * indicates whether exit to userspace is needed.
13219 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
13220 struct x86_exception *e)
13222 if (r == X86EMUL_PROPAGATE_FAULT) {
13223 if (KVM_BUG_ON(!e, vcpu->kvm))
13226 kvm_inject_emulated_page_fault(vcpu, e);
13231 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
13232 * while handling a VMX instruction KVM could've handled the request
13233 * correctly by exiting to userspace and performing I/O but there
13234 * doesn't seem to be a real use-case behind such requests, just return
13235 * KVM_EXIT_INTERNAL_ERROR for now.
13237 kvm_prepare_emulation_failure_exit(vcpu);
13241 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
13243 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
13246 struct x86_exception e;
13253 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
13254 if (r != X86EMUL_CONTINUE)
13255 return kvm_handle_memory_failure(vcpu, r, &e);
13257 if (operand.pcid >> 12 != 0) {
13258 kvm_inject_gp(vcpu, 0);
13262 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
13265 case INVPCID_TYPE_INDIV_ADDR:
13266 if ((!pcid_enabled && (operand.pcid != 0)) ||
13267 is_noncanonical_address(operand.gla, vcpu)) {
13268 kvm_inject_gp(vcpu, 0);
13271 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
13272 return kvm_skip_emulated_instruction(vcpu);
13274 case INVPCID_TYPE_SINGLE_CTXT:
13275 if (!pcid_enabled && (operand.pcid != 0)) {
13276 kvm_inject_gp(vcpu, 0);
13280 kvm_invalidate_pcid(vcpu, operand.pcid);
13281 return kvm_skip_emulated_instruction(vcpu);
13283 case INVPCID_TYPE_ALL_NON_GLOBAL:
13285 * Currently, KVM doesn't mark global entries in the shadow
13286 * page tables, so a non-global flush just degenerates to a
13287 * global flush. If needed, we could optimize this later by
13288 * keeping track of global entries in shadow page tables.
13292 case INVPCID_TYPE_ALL_INCL_GLOBAL:
13293 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
13294 return kvm_skip_emulated_instruction(vcpu);
13297 kvm_inject_gp(vcpu, 0);
13301 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
13303 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
13305 struct kvm_run *run = vcpu->run;
13306 struct kvm_mmio_fragment *frag;
13309 BUG_ON(!vcpu->mmio_needed);
13311 /* Complete previous fragment */
13312 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
13313 len = min(8u, frag->len);
13314 if (!vcpu->mmio_is_write)
13315 memcpy(frag->data, run->mmio.data, len);
13317 if (frag->len <= 8) {
13318 /* Switch to the next fragment. */
13320 vcpu->mmio_cur_fragment++;
13322 /* Go forward to the next mmio piece. */
13328 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
13329 vcpu->mmio_needed = 0;
13331 // VMG change, at this point, we're always done
13332 // RIP has already been advanced
13336 // More MMIO is needed
13337 run->mmio.phys_addr = frag->gpa;
13338 run->mmio.len = min(8u, frag->len);
13339 run->mmio.is_write = vcpu->mmio_is_write;
13340 if (run->mmio.is_write)
13341 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
13342 run->exit_reason = KVM_EXIT_MMIO;
13344 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13349 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13353 struct kvm_mmio_fragment *frag;
13358 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13359 if (handled == bytes)
13366 /*TODO: Check if need to increment number of frags */
13367 frag = vcpu->mmio_fragments;
13368 vcpu->mmio_nr_fragments = 1;
13373 vcpu->mmio_needed = 1;
13374 vcpu->mmio_cur_fragment = 0;
13376 vcpu->run->mmio.phys_addr = gpa;
13377 vcpu->run->mmio.len = min(8u, frag->len);
13378 vcpu->run->mmio.is_write = 1;
13379 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
13380 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13382 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13386 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
13388 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13392 struct kvm_mmio_fragment *frag;
13397 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13398 if (handled == bytes)
13405 /*TODO: Check if need to increment number of frags */
13406 frag = vcpu->mmio_fragments;
13407 vcpu->mmio_nr_fragments = 1;
13412 vcpu->mmio_needed = 1;
13413 vcpu->mmio_cur_fragment = 0;
13415 vcpu->run->mmio.phys_addr = gpa;
13416 vcpu->run->mmio.len = min(8u, frag->len);
13417 vcpu->run->mmio.is_write = 0;
13418 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13420 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13424 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
13426 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size)
13428 vcpu->arch.sev_pio_count -= count;
13429 vcpu->arch.sev_pio_data += count * size;
13432 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13433 unsigned int port);
13435 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
13437 int size = vcpu->arch.pio.size;
13438 int port = vcpu->arch.pio.port;
13440 vcpu->arch.pio.count = 0;
13441 if (vcpu->arch.sev_pio_count)
13442 return kvm_sev_es_outs(vcpu, size, port);
13446 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13450 unsigned int count =
13451 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13452 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
13454 /* memcpy done already by emulator_pio_out. */
13455 advance_sev_es_emulated_pio(vcpu, count, size);
13459 /* Emulation done by the kernel. */
13460 if (!vcpu->arch.sev_pio_count)
13464 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
13468 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13469 unsigned int port);
13471 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
13473 unsigned count = vcpu->arch.pio.count;
13474 int size = vcpu->arch.pio.size;
13475 int port = vcpu->arch.pio.port;
13477 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
13478 advance_sev_es_emulated_pio(vcpu, count, size);
13479 if (vcpu->arch.sev_pio_count)
13480 return kvm_sev_es_ins(vcpu, size, port);
13484 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13488 unsigned int count =
13489 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13490 if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count))
13493 /* Emulation done by the kernel. */
13494 advance_sev_es_emulated_pio(vcpu, count, size);
13495 if (!vcpu->arch.sev_pio_count)
13499 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
13503 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
13504 unsigned int port, void *data, unsigned int count,
13507 vcpu->arch.sev_pio_data = data;
13508 vcpu->arch.sev_pio_count = count;
13509 return in ? kvm_sev_es_ins(vcpu, size, port)
13510 : kvm_sev_es_outs(vcpu, size, port);
13512 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
13514 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
13515 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
13516 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
13517 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
13518 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
13519 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
13520 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
13521 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter);
13522 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
13523 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
13524 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
13525 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
13526 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
13527 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
13528 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
13529 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
13530 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
13531 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
13532 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
13533 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
13534 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
13535 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
13536 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath);
13537 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell);
13538 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
13539 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
13540 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
13541 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
13542 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
13544 static int __init kvm_x86_init(void)
13546 kvm_mmu_x86_module_init();
13547 mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible();
13550 module_init(kvm_x86_init);
13552 static void __exit kvm_x86_exit(void)
13555 * If module_init() is implemented, module_exit() must also be
13556 * implemented to allow module unload.
13559 module_exit(kvm_x86_exit);