2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
59 #include <trace/events/kvm.h>
61 #include <asm/debugreg.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70 #include <asm/mshyperv.h>
71 #include <asm/hypervisor.h>
73 #define CREATE_TRACE_POINTS
76 #define MAX_IO_MSRS 256
77 #define KVM_MAX_MCE_BANKS 32
78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
81 #define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
95 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
101 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
102 static void process_nmi(struct kvm_vcpu *vcpu);
103 static void enter_smm(struct kvm_vcpu *vcpu);
104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
105 static void store_regs(struct kvm_vcpu *vcpu);
106 static int sync_regs(struct kvm_vcpu *vcpu);
108 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
109 EXPORT_SYMBOL_GPL(kvm_x86_ops);
111 static bool __read_mostly ignore_msrs = 0;
112 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
114 static bool __read_mostly report_ignored_msrs = true;
115 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117 unsigned int min_timer_period_us = 200;
118 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120 static bool __read_mostly kvmclock_periodic_sync = true;
121 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123 bool __read_mostly kvm_has_tsc_control;
124 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
125 u32 __read_mostly kvm_max_guest_tsc_khz;
126 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
127 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129 u64 __read_mostly kvm_max_tsc_scaling_ratio;
130 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
131 u64 __read_mostly kvm_default_tsc_scaling_ratio;
132 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
134 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
135 static u32 __read_mostly tsc_tolerance_ppm = 250;
136 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
138 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
139 unsigned int __read_mostly lapic_timer_advance_ns = 0;
140 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
142 static bool __read_mostly vector_hashing = true;
143 module_param(vector_hashing, bool, S_IRUGO);
145 bool __read_mostly enable_vmware_backdoor = false;
146 module_param(enable_vmware_backdoor, bool, S_IRUGO);
147 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149 static bool __read_mostly force_emulation_prefix = false;
150 module_param(force_emulation_prefix, bool, S_IRUGO);
152 #define KVM_NR_SHARED_MSRS 16
154 struct kvm_shared_msrs_global {
156 u32 msrs[KVM_NR_SHARED_MSRS];
159 struct kvm_shared_msrs {
160 struct user_return_notifier urn;
162 struct kvm_shared_msr_values {
165 } values[KVM_NR_SHARED_MSRS];
168 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
169 static struct kvm_shared_msrs __percpu *shared_msrs;
171 struct kvm_stats_debugfs_item debugfs_entries[] = {
172 { "pf_fixed", VCPU_STAT(pf_fixed) },
173 { "pf_guest", VCPU_STAT(pf_guest) },
174 { "tlb_flush", VCPU_STAT(tlb_flush) },
175 { "invlpg", VCPU_STAT(invlpg) },
176 { "exits", VCPU_STAT(exits) },
177 { "io_exits", VCPU_STAT(io_exits) },
178 { "mmio_exits", VCPU_STAT(mmio_exits) },
179 { "signal_exits", VCPU_STAT(signal_exits) },
180 { "irq_window", VCPU_STAT(irq_window_exits) },
181 { "nmi_window", VCPU_STAT(nmi_window_exits) },
182 { "halt_exits", VCPU_STAT(halt_exits) },
183 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
184 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
185 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
186 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
187 { "hypercalls", VCPU_STAT(hypercalls) },
188 { "request_irq", VCPU_STAT(request_irq_exits) },
189 { "irq_exits", VCPU_STAT(irq_exits) },
190 { "host_state_reload", VCPU_STAT(host_state_reload) },
191 { "fpu_reload", VCPU_STAT(fpu_reload) },
192 { "insn_emulation", VCPU_STAT(insn_emulation) },
193 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
194 { "irq_injections", VCPU_STAT(irq_injections) },
195 { "nmi_injections", VCPU_STAT(nmi_injections) },
196 { "req_event", VCPU_STAT(req_event) },
197 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
198 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
199 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
200 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
201 { "mmu_flooded", VM_STAT(mmu_flooded) },
202 { "mmu_recycled", VM_STAT(mmu_recycled) },
203 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
204 { "mmu_unsync", VM_STAT(mmu_unsync) },
205 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
206 { "largepages", VM_STAT(lpages) },
207 { "max_mmu_page_hash_collisions",
208 VM_STAT(max_mmu_page_hash_collisions) },
212 u64 __read_mostly host_xcr0;
214 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
216 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
219 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
220 vcpu->arch.apf.gfns[i] = ~0;
223 static void kvm_on_user_return(struct user_return_notifier *urn)
226 struct kvm_shared_msrs *locals
227 = container_of(urn, struct kvm_shared_msrs, urn);
228 struct kvm_shared_msr_values *values;
232 * Disabling irqs at this point since the following code could be
233 * interrupted and executed through kvm_arch_hardware_disable()
235 local_irq_save(flags);
236 if (locals->registered) {
237 locals->registered = false;
238 user_return_notifier_unregister(urn);
240 local_irq_restore(flags);
241 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
242 values = &locals->values[slot];
243 if (values->host != values->curr) {
244 wrmsrl(shared_msrs_global.msrs[slot], values->host);
245 values->curr = values->host;
250 static void shared_msr_update(unsigned slot, u32 msr)
253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
256 /* only read, and nobody should modify it at this time,
257 * so don't need lock */
258 if (slot >= shared_msrs_global.nr) {
259 printk(KERN_ERR "kvm: invalid MSR slot!");
262 rdmsrl_safe(msr, &value);
263 smsr->values[slot].host = value;
264 smsr->values[slot].curr = value;
267 void kvm_define_shared_msr(unsigned slot, u32 msr)
269 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
270 shared_msrs_global.msrs[slot] = msr;
271 if (slot >= shared_msrs_global.nr)
272 shared_msrs_global.nr = slot + 1;
274 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
276 static void kvm_shared_msr_cpu_online(void)
280 for (i = 0; i < shared_msrs_global.nr; ++i)
281 shared_msr_update(i, shared_msrs_global.msrs[i]);
284 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
286 unsigned int cpu = smp_processor_id();
287 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
290 if (((value ^ smsr->values[slot].curr) & mask) == 0)
292 smsr->values[slot].curr = value;
293 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
297 if (!smsr->registered) {
298 smsr->urn.on_user_return = kvm_on_user_return;
299 user_return_notifier_register(&smsr->urn);
300 smsr->registered = true;
304 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
306 static void drop_user_return_notifiers(void)
308 unsigned int cpu = smp_processor_id();
309 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
311 if (smsr->registered)
312 kvm_on_user_return(&smsr->urn);
315 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
317 return vcpu->arch.apic_base;
319 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
321 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
323 u64 old_state = vcpu->arch.apic_base &
324 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
325 u64 new_state = msr_info->data &
326 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
327 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
328 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
330 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
332 if (!msr_info->host_initiated &&
333 ((new_state == MSR_IA32_APICBASE_ENABLE &&
334 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
335 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
339 kvm_lapic_set_base(vcpu, msr_info->data);
342 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
344 asmlinkage __visible void kvm_spurious_fault(void)
346 /* Fault while not rebooting. We want the trace. */
349 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
351 #define EXCPT_BENIGN 0
352 #define EXCPT_CONTRIBUTORY 1
355 static int exception_class(int vector)
365 return EXCPT_CONTRIBUTORY;
372 #define EXCPT_FAULT 0
374 #define EXCPT_ABORT 2
375 #define EXCPT_INTERRUPT 3
377 static int exception_type(int vector)
381 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
382 return EXCPT_INTERRUPT;
386 /* #DB is trap, as instruction watchpoints are handled elsewhere */
387 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
390 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
393 /* Reserved exceptions will result in fault */
397 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
398 unsigned nr, bool has_error, u32 error_code,
404 kvm_make_request(KVM_REQ_EVENT, vcpu);
406 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
408 if (has_error && !is_protmode(vcpu))
412 * On vmentry, vcpu->arch.exception.pending is only
413 * true if an event injection was blocked by
414 * nested_run_pending. In that case, however,
415 * vcpu_enter_guest requests an immediate exit,
416 * and the guest shouldn't proceed far enough to
419 WARN_ON_ONCE(vcpu->arch.exception.pending);
420 vcpu->arch.exception.injected = true;
422 vcpu->arch.exception.pending = true;
423 vcpu->arch.exception.injected = false;
425 vcpu->arch.exception.has_error_code = has_error;
426 vcpu->arch.exception.nr = nr;
427 vcpu->arch.exception.error_code = error_code;
431 /* to check exception */
432 prev_nr = vcpu->arch.exception.nr;
433 if (prev_nr == DF_VECTOR) {
434 /* triple fault -> shutdown */
435 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
438 class1 = exception_class(prev_nr);
439 class2 = exception_class(nr);
440 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
441 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
443 * Generate double fault per SDM Table 5-5. Set
444 * exception.pending = true so that the double fault
445 * can trigger a nested vmexit.
447 vcpu->arch.exception.pending = true;
448 vcpu->arch.exception.injected = false;
449 vcpu->arch.exception.has_error_code = true;
450 vcpu->arch.exception.nr = DF_VECTOR;
451 vcpu->arch.exception.error_code = 0;
453 /* replace previous exception with a new one in a hope
454 that instruction re-execution will regenerate lost
459 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
461 kvm_multiple_exception(vcpu, nr, false, 0, false);
463 EXPORT_SYMBOL_GPL(kvm_queue_exception);
465 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
467 kvm_multiple_exception(vcpu, nr, false, 0, true);
469 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
471 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
474 kvm_inject_gp(vcpu, 0);
476 return kvm_skip_emulated_instruction(vcpu);
480 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
482 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
484 ++vcpu->stat.pf_guest;
485 vcpu->arch.exception.nested_apf =
486 is_guest_mode(vcpu) && fault->async_page_fault;
487 if (vcpu->arch.exception.nested_apf)
488 vcpu->arch.apf.nested_apf_token = fault->address;
490 vcpu->arch.cr2 = fault->address;
491 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
493 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
495 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
497 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
498 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
500 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
502 return fault->nested_page_fault;
505 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
507 atomic_inc(&vcpu->arch.nmi_queued);
508 kvm_make_request(KVM_REQ_NMI, vcpu);
510 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
512 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
514 kvm_multiple_exception(vcpu, nr, true, error_code, false);
516 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
518 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
520 kvm_multiple_exception(vcpu, nr, true, error_code, true);
522 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
525 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
526 * a #GP and return false.
528 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
530 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
532 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
535 EXPORT_SYMBOL_GPL(kvm_require_cpl);
537 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
539 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
542 kvm_queue_exception(vcpu, UD_VECTOR);
545 EXPORT_SYMBOL_GPL(kvm_require_dr);
548 * This function will be used to read from the physical memory of the currently
549 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
550 * can read from guest physical or from the guest's guest physical memory.
552 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
553 gfn_t ngfn, void *data, int offset, int len,
556 struct x86_exception exception;
560 ngpa = gfn_to_gpa(ngfn);
561 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
562 if (real_gfn == UNMAPPED_GVA)
565 real_gfn = gpa_to_gfn(real_gfn);
567 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
569 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
571 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
572 void *data, int offset, int len, u32 access)
574 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
575 data, offset, len, access);
579 * Load the pae pdptrs. Return true is they are all valid.
581 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
583 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
584 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
587 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
589 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
590 offset * sizeof(u64), sizeof(pdpte),
591 PFERR_USER_MASK|PFERR_WRITE_MASK);
596 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
597 if ((pdpte[i] & PT_PRESENT_MASK) &&
599 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
606 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
607 __set_bit(VCPU_EXREG_PDPTR,
608 (unsigned long *)&vcpu->arch.regs_avail);
609 __set_bit(VCPU_EXREG_PDPTR,
610 (unsigned long *)&vcpu->arch.regs_dirty);
615 EXPORT_SYMBOL_GPL(load_pdptrs);
617 bool pdptrs_changed(struct kvm_vcpu *vcpu)
619 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
625 if (is_long_mode(vcpu) || !is_pae(vcpu))
628 if (!test_bit(VCPU_EXREG_PDPTR,
629 (unsigned long *)&vcpu->arch.regs_avail))
632 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
633 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
634 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
635 PFERR_USER_MASK | PFERR_WRITE_MASK);
638 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
643 EXPORT_SYMBOL_GPL(pdptrs_changed);
645 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
647 unsigned long old_cr0 = kvm_read_cr0(vcpu);
648 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
653 if (cr0 & 0xffffffff00000000UL)
657 cr0 &= ~CR0_RESERVED_BITS;
659 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
662 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
665 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
667 if ((vcpu->arch.efer & EFER_LME)) {
672 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
677 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
682 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
685 kvm_x86_ops->set_cr0(vcpu, cr0);
687 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
688 kvm_clear_async_pf_completion_queue(vcpu);
689 kvm_async_pf_hash_reset(vcpu);
692 if ((cr0 ^ old_cr0) & update_bits)
693 kvm_mmu_reset_context(vcpu);
695 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
696 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
697 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
698 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
702 EXPORT_SYMBOL_GPL(kvm_set_cr0);
704 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
706 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
708 EXPORT_SYMBOL_GPL(kvm_lmsw);
710 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
712 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
713 !vcpu->guest_xcr0_loaded) {
714 /* kvm_set_xcr() also depends on this */
715 if (vcpu->arch.xcr0 != host_xcr0)
716 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
717 vcpu->guest_xcr0_loaded = 1;
721 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
723 if (vcpu->guest_xcr0_loaded) {
724 if (vcpu->arch.xcr0 != host_xcr0)
725 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
726 vcpu->guest_xcr0_loaded = 0;
730 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
733 u64 old_xcr0 = vcpu->arch.xcr0;
736 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
737 if (index != XCR_XFEATURE_ENABLED_MASK)
739 if (!(xcr0 & XFEATURE_MASK_FP))
741 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
745 * Do not allow the guest to set bits that we do not support
746 * saving. However, xcr0 bit 0 is always set, even if the
747 * emulated CPU does not support XSAVE (see fx_init).
749 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
750 if (xcr0 & ~valid_bits)
753 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
754 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
757 if (xcr0 & XFEATURE_MASK_AVX512) {
758 if (!(xcr0 & XFEATURE_MASK_YMM))
760 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
763 vcpu->arch.xcr0 = xcr0;
765 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
766 kvm_update_cpuid(vcpu);
770 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
772 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
773 __kvm_set_xcr(vcpu, index, xcr)) {
774 kvm_inject_gp(vcpu, 0);
779 EXPORT_SYMBOL_GPL(kvm_set_xcr);
781 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
783 unsigned long old_cr4 = kvm_read_cr4(vcpu);
784 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
785 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
787 if (cr4 & CR4_RESERVED_BITS)
790 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
793 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
796 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
799 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
802 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
805 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
808 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
811 if (is_long_mode(vcpu)) {
812 if (!(cr4 & X86_CR4_PAE))
814 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
815 && ((cr4 ^ old_cr4) & pdptr_bits)
816 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
820 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
821 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
824 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
825 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
829 if (kvm_x86_ops->set_cr4(vcpu, cr4))
832 if (((cr4 ^ old_cr4) & pdptr_bits) ||
833 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
834 kvm_mmu_reset_context(vcpu);
836 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
837 kvm_update_cpuid(vcpu);
841 EXPORT_SYMBOL_GPL(kvm_set_cr4);
843 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
846 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
849 cr3 &= ~CR3_PCID_INVD;
852 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
853 kvm_mmu_sync_roots(vcpu);
854 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
858 if (is_long_mode(vcpu) &&
859 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
861 else if (is_pae(vcpu) && is_paging(vcpu) &&
862 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
865 vcpu->arch.cr3 = cr3;
866 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
867 kvm_mmu_new_cr3(vcpu);
870 EXPORT_SYMBOL_GPL(kvm_set_cr3);
872 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
874 if (cr8 & CR8_RESERVED_BITS)
876 if (lapic_in_kernel(vcpu))
877 kvm_lapic_set_tpr(vcpu, cr8);
879 vcpu->arch.cr8 = cr8;
882 EXPORT_SYMBOL_GPL(kvm_set_cr8);
884 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
886 if (lapic_in_kernel(vcpu))
887 return kvm_lapic_get_cr8(vcpu);
889 return vcpu->arch.cr8;
891 EXPORT_SYMBOL_GPL(kvm_get_cr8);
893 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
897 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
898 for (i = 0; i < KVM_NR_DB_REGS; i++)
899 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
900 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
904 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
906 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
907 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
910 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
914 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
915 dr7 = vcpu->arch.guest_debug_dr7;
917 dr7 = vcpu->arch.dr7;
918 kvm_x86_ops->set_dr7(vcpu, dr7);
919 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
920 if (dr7 & DR7_BP_EN_MASK)
921 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
924 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
926 u64 fixed = DR6_FIXED_1;
928 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
933 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
937 vcpu->arch.db[dr] = val;
938 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
939 vcpu->arch.eff_db[dr] = val;
944 if (val & 0xffffffff00000000ULL)
946 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
947 kvm_update_dr6(vcpu);
952 if (val & 0xffffffff00000000ULL)
954 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
955 kvm_update_dr7(vcpu);
962 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
964 if (__kvm_set_dr(vcpu, dr, val)) {
965 kvm_inject_gp(vcpu, 0);
970 EXPORT_SYMBOL_GPL(kvm_set_dr);
972 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
976 *val = vcpu->arch.db[dr];
981 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
982 *val = vcpu->arch.dr6;
984 *val = kvm_x86_ops->get_dr6(vcpu);
989 *val = vcpu->arch.dr7;
994 EXPORT_SYMBOL_GPL(kvm_get_dr);
996 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
998 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1002 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1005 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1006 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1009 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1012 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1013 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1015 * This list is modified at module load time to reflect the
1016 * capabilities of the host cpu. This capabilities test skips MSRs that are
1017 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1018 * may depend on host virtualization features rather than host cpu features.
1021 static u32 msrs_to_save[] = {
1022 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1024 #ifdef CONFIG_X86_64
1025 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1027 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1028 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1029 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
1032 static unsigned num_msrs_to_save;
1034 static u32 emulated_msrs[] = {
1035 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1036 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1037 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1038 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1039 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1040 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1041 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1043 HV_X64_MSR_VP_INDEX,
1044 HV_X64_MSR_VP_RUNTIME,
1045 HV_X64_MSR_SCONTROL,
1046 HV_X64_MSR_STIMER0_CONFIG,
1047 HV_X64_MSR_VP_ASSIST_PAGE,
1048 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1049 HV_X64_MSR_TSC_EMULATION_STATUS,
1051 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1054 MSR_IA32_TSC_ADJUST,
1055 MSR_IA32_TSCDEADLINE,
1056 MSR_IA32_MISC_ENABLE,
1057 MSR_IA32_MCG_STATUS,
1059 MSR_IA32_MCG_EXT_CTL,
1063 MSR_MISC_FEATURES_ENABLES,
1064 MSR_AMD64_VIRT_SPEC_CTRL,
1067 static unsigned num_emulated_msrs;
1070 * List of msr numbers which are used to expose MSR-based features that
1071 * can be used by a hypervisor to validate requested CPU features.
1073 static u32 msr_based_features[] = {
1075 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1076 MSR_IA32_VMX_PINBASED_CTLS,
1077 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1078 MSR_IA32_VMX_PROCBASED_CTLS,
1079 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1080 MSR_IA32_VMX_EXIT_CTLS,
1081 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1082 MSR_IA32_VMX_ENTRY_CTLS,
1084 MSR_IA32_VMX_CR0_FIXED0,
1085 MSR_IA32_VMX_CR0_FIXED1,
1086 MSR_IA32_VMX_CR4_FIXED0,
1087 MSR_IA32_VMX_CR4_FIXED1,
1088 MSR_IA32_VMX_VMCS_ENUM,
1089 MSR_IA32_VMX_PROCBASED_CTLS2,
1090 MSR_IA32_VMX_EPT_VPID_CAP,
1091 MSR_IA32_VMX_VMFUNC,
1097 static unsigned int num_msr_based_features;
1099 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1101 switch (msr->index) {
1102 case MSR_IA32_UCODE_REV:
1103 rdmsrl(msr->index, msr->data);
1106 if (kvm_x86_ops->get_msr_feature(msr))
1112 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1114 struct kvm_msr_entry msr;
1118 r = kvm_get_msr_feature(&msr);
1127 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1129 if (efer & efer_reserved_bits)
1132 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1135 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1140 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1142 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1144 u64 old_efer = vcpu->arch.efer;
1146 if (!kvm_valid_efer(vcpu, efer))
1150 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1154 efer |= vcpu->arch.efer & EFER_LMA;
1156 kvm_x86_ops->set_efer(vcpu, efer);
1158 /* Update reserved bits */
1159 if ((efer ^ old_efer) & EFER_NX)
1160 kvm_mmu_reset_context(vcpu);
1165 void kvm_enable_efer_bits(u64 mask)
1167 efer_reserved_bits &= ~mask;
1169 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1172 * Writes msr value into into the appropriate "register".
1173 * Returns 0 on success, non-0 otherwise.
1174 * Assumes vcpu_load() was already called.
1176 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1178 switch (msr->index) {
1181 case MSR_KERNEL_GS_BASE:
1184 if (is_noncanonical_address(msr->data, vcpu))
1187 case MSR_IA32_SYSENTER_EIP:
1188 case MSR_IA32_SYSENTER_ESP:
1190 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1191 * non-canonical address is written on Intel but not on
1192 * AMD (which ignores the top 32-bits, because it does
1193 * not implement 64-bit SYSENTER).
1195 * 64-bit code should hence be able to write a non-canonical
1196 * value on AMD. Making the address canonical ensures that
1197 * vmentry does not fail on Intel after writing a non-canonical
1198 * value, and that something deterministic happens if the guest
1199 * invokes 64-bit SYSENTER.
1201 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1203 return kvm_x86_ops->set_msr(vcpu, msr);
1205 EXPORT_SYMBOL_GPL(kvm_set_msr);
1208 * Adapt set_msr() to msr_io()'s calling convention
1210 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1212 struct msr_data msr;
1216 msr.host_initiated = true;
1217 r = kvm_get_msr(vcpu, &msr);
1225 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1227 struct msr_data msr;
1231 msr.host_initiated = true;
1232 return kvm_set_msr(vcpu, &msr);
1235 #ifdef CONFIG_X86_64
1236 struct pvclock_gtod_data {
1239 struct { /* extract of a clocksource struct */
1252 static struct pvclock_gtod_data pvclock_gtod_data;
1254 static void update_pvclock_gtod(struct timekeeper *tk)
1256 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1259 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1261 write_seqcount_begin(&vdata->seq);
1263 /* copy pvclock gtod data */
1264 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1265 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1266 vdata->clock.mask = tk->tkr_mono.mask;
1267 vdata->clock.mult = tk->tkr_mono.mult;
1268 vdata->clock.shift = tk->tkr_mono.shift;
1270 vdata->boot_ns = boot_ns;
1271 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1273 vdata->wall_time_sec = tk->xtime_sec;
1275 write_seqcount_end(&vdata->seq);
1279 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1282 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1283 * vcpu_enter_guest. This function is only called from
1284 * the physical CPU that is running vcpu.
1286 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1289 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1293 struct pvclock_wall_clock wc;
1294 struct timespec64 boot;
1299 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1304 ++version; /* first time write, random junk */
1308 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1312 * The guest calculates current wall clock time by adding
1313 * system time (updated by kvm_guest_time_update below) to the
1314 * wall clock specified here. guest system time equals host
1315 * system time for us, thus we must fill in host boot time here.
1317 getboottime64(&boot);
1319 if (kvm->arch.kvmclock_offset) {
1320 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1321 boot = timespec64_sub(boot, ts);
1323 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1324 wc.nsec = boot.tv_nsec;
1325 wc.version = version;
1327 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1330 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1333 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1335 do_shl32_div32(dividend, divisor);
1339 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1340 s8 *pshift, u32 *pmultiplier)
1348 scaled64 = scaled_hz;
1349 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1354 tps32 = (uint32_t)tps64;
1355 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1356 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1364 *pmultiplier = div_frac(scaled64, tps32);
1366 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1367 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1370 #ifdef CONFIG_X86_64
1371 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1374 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1375 static unsigned long max_tsc_khz;
1377 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1379 u64 v = (u64)khz * (1000000 + ppm);
1384 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1388 /* Guest TSC same frequency as host TSC? */
1390 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1394 /* TSC scaling supported? */
1395 if (!kvm_has_tsc_control) {
1396 if (user_tsc_khz > tsc_khz) {
1397 vcpu->arch.tsc_catchup = 1;
1398 vcpu->arch.tsc_always_catchup = 1;
1401 WARN(1, "user requested TSC rate below hardware speed\n");
1406 /* TSC scaling required - calculate ratio */
1407 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1408 user_tsc_khz, tsc_khz);
1410 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1411 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1416 vcpu->arch.tsc_scaling_ratio = ratio;
1420 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1422 u32 thresh_lo, thresh_hi;
1423 int use_scaling = 0;
1425 /* tsc_khz can be zero if TSC calibration fails */
1426 if (user_tsc_khz == 0) {
1427 /* set tsc_scaling_ratio to a safe value */
1428 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1432 /* Compute a scale to convert nanoseconds in TSC cycles */
1433 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1434 &vcpu->arch.virtual_tsc_shift,
1435 &vcpu->arch.virtual_tsc_mult);
1436 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1439 * Compute the variation in TSC rate which is acceptable
1440 * within the range of tolerance and decide if the
1441 * rate being applied is within that bounds of the hardware
1442 * rate. If so, no scaling or compensation need be done.
1444 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1445 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1446 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1447 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1450 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1453 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1455 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1456 vcpu->arch.virtual_tsc_mult,
1457 vcpu->arch.virtual_tsc_shift);
1458 tsc += vcpu->arch.this_tsc_write;
1462 static inline int gtod_is_based_on_tsc(int mode)
1464 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1467 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1469 #ifdef CONFIG_X86_64
1471 struct kvm_arch *ka = &vcpu->kvm->arch;
1472 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1474 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1475 atomic_read(&vcpu->kvm->online_vcpus));
1478 * Once the masterclock is enabled, always perform request in
1479 * order to update it.
1481 * In order to enable masterclock, the host clocksource must be TSC
1482 * and the vcpus need to have matched TSCs. When that happens,
1483 * perform request to enable masterclock.
1485 if (ka->use_master_clock ||
1486 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1487 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1489 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1490 atomic_read(&vcpu->kvm->online_vcpus),
1491 ka->use_master_clock, gtod->clock.vclock_mode);
1495 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1497 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1498 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1502 * Multiply tsc by a fixed point number represented by ratio.
1504 * The most significant 64-N bits (mult) of ratio represent the
1505 * integral part of the fixed point number; the remaining N bits
1506 * (frac) represent the fractional part, ie. ratio represents a fixed
1507 * point number (mult + frac * 2^(-N)).
1509 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1511 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1513 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1516 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1519 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1521 if (ratio != kvm_default_tsc_scaling_ratio)
1522 _tsc = __scale_tsc(ratio, tsc);
1526 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1528 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1532 tsc = kvm_scale_tsc(vcpu, rdtsc());
1534 return target_tsc - tsc;
1537 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1539 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1541 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1543 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1545 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1547 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1548 vcpu->arch.tsc_offset = offset;
1551 static inline bool kvm_check_tsc_unstable(void)
1553 #ifdef CONFIG_X86_64
1555 * TSC is marked unstable when we're running on Hyper-V,
1556 * 'TSC page' clocksource is good.
1558 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1561 return check_tsc_unstable();
1564 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1566 struct kvm *kvm = vcpu->kvm;
1567 u64 offset, ns, elapsed;
1568 unsigned long flags;
1570 bool already_matched;
1571 u64 data = msr->data;
1572 bool synchronizing = false;
1574 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1575 offset = kvm_compute_tsc_offset(vcpu, data);
1576 ns = ktime_get_boot_ns();
1577 elapsed = ns - kvm->arch.last_tsc_nsec;
1579 if (vcpu->arch.virtual_tsc_khz) {
1580 if (data == 0 && msr->host_initiated) {
1582 * detection of vcpu initialization -- need to sync
1583 * with other vCPUs. This particularly helps to keep
1584 * kvm_clock stable after CPU hotplug
1586 synchronizing = true;
1588 u64 tsc_exp = kvm->arch.last_tsc_write +
1589 nsec_to_cycles(vcpu, elapsed);
1590 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1592 * Special case: TSC write with a small delta (1 second)
1593 * of virtual cycle time against real time is
1594 * interpreted as an attempt to synchronize the CPU.
1596 synchronizing = data < tsc_exp + tsc_hz &&
1597 data + tsc_hz > tsc_exp;
1602 * For a reliable TSC, we can match TSC offsets, and for an unstable
1603 * TSC, we add elapsed time in this computation. We could let the
1604 * compensation code attempt to catch up if we fall behind, but
1605 * it's better to try to match offsets from the beginning.
1607 if (synchronizing &&
1608 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1609 if (!kvm_check_tsc_unstable()) {
1610 offset = kvm->arch.cur_tsc_offset;
1611 pr_debug("kvm: matched tsc offset for %llu\n", data);
1613 u64 delta = nsec_to_cycles(vcpu, elapsed);
1615 offset = kvm_compute_tsc_offset(vcpu, data);
1616 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1619 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1622 * We split periods of matched TSC writes into generations.
1623 * For each generation, we track the original measured
1624 * nanosecond time, offset, and write, so if TSCs are in
1625 * sync, we can match exact offset, and if not, we can match
1626 * exact software computation in compute_guest_tsc()
1628 * These values are tracked in kvm->arch.cur_xxx variables.
1630 kvm->arch.cur_tsc_generation++;
1631 kvm->arch.cur_tsc_nsec = ns;
1632 kvm->arch.cur_tsc_write = data;
1633 kvm->arch.cur_tsc_offset = offset;
1635 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1636 kvm->arch.cur_tsc_generation, data);
1640 * We also track th most recent recorded KHZ, write and time to
1641 * allow the matching interval to be extended at each write.
1643 kvm->arch.last_tsc_nsec = ns;
1644 kvm->arch.last_tsc_write = data;
1645 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1647 vcpu->arch.last_guest_tsc = data;
1649 /* Keep track of which generation this VCPU has synchronized to */
1650 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1651 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1652 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1654 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1655 update_ia32_tsc_adjust_msr(vcpu, offset);
1657 kvm_vcpu_write_tsc_offset(vcpu, offset);
1658 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1660 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1662 kvm->arch.nr_vcpus_matched_tsc = 0;
1663 } else if (!already_matched) {
1664 kvm->arch.nr_vcpus_matched_tsc++;
1667 kvm_track_tsc_matching(vcpu);
1668 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1671 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1673 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1676 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1679 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1681 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1682 WARN_ON(adjustment < 0);
1683 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1684 adjust_tsc_offset_guest(vcpu, adjustment);
1687 #ifdef CONFIG_X86_64
1689 static u64 read_tsc(void)
1691 u64 ret = (u64)rdtsc_ordered();
1692 u64 last = pvclock_gtod_data.clock.cycle_last;
1694 if (likely(ret >= last))
1698 * GCC likes to generate cmov here, but this branch is extremely
1699 * predictable (it's just a function of time and the likely is
1700 * very likely) and there's a data dependence, so force GCC
1701 * to generate a branch instead. I don't barrier() because
1702 * we don't actually need a barrier, and if this function
1703 * ever gets inlined it will generate worse code.
1709 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1712 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1715 switch (gtod->clock.vclock_mode) {
1716 case VCLOCK_HVCLOCK:
1717 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1719 if (tsc_pg_val != U64_MAX) {
1720 /* TSC page valid */
1721 *mode = VCLOCK_HVCLOCK;
1722 v = (tsc_pg_val - gtod->clock.cycle_last) &
1725 /* TSC page invalid */
1726 *mode = VCLOCK_NONE;
1731 *tsc_timestamp = read_tsc();
1732 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1736 *mode = VCLOCK_NONE;
1739 if (*mode == VCLOCK_NONE)
1740 *tsc_timestamp = v = 0;
1742 return v * gtod->clock.mult;
1745 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1747 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1753 seq = read_seqcount_begin(>od->seq);
1754 ns = gtod->nsec_base;
1755 ns += vgettsc(tsc_timestamp, &mode);
1756 ns >>= gtod->clock.shift;
1757 ns += gtod->boot_ns;
1758 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1764 static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
1766 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1772 seq = read_seqcount_begin(>od->seq);
1773 ts->tv_sec = gtod->wall_time_sec;
1774 ns = gtod->nsec_base;
1775 ns += vgettsc(tsc_timestamp, &mode);
1776 ns >>= gtod->clock.shift;
1777 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1779 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1785 /* returns true if host is using TSC based clocksource */
1786 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
1788 /* checked again under seqlock below */
1789 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1792 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1796 /* returns true if host is using TSC based clocksource */
1797 static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1800 /* checked again under seqlock below */
1801 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1804 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
1810 * Assuming a stable TSC across physical CPUS, and a stable TSC
1811 * across virtual CPUs, the following condition is possible.
1812 * Each numbered line represents an event visible to both
1813 * CPUs at the next numbered event.
1815 * "timespecX" represents host monotonic time. "tscX" represents
1818 * VCPU0 on CPU0 | VCPU1 on CPU1
1820 * 1. read timespec0,tsc0
1821 * 2. | timespec1 = timespec0 + N
1823 * 3. transition to guest | transition to guest
1824 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1825 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1826 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1828 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1831 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1833 * - 0 < N - M => M < N
1835 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1836 * always the case (the difference between two distinct xtime instances
1837 * might be smaller then the difference between corresponding TSC reads,
1838 * when updating guest vcpus pvclock areas).
1840 * To avoid that problem, do not allow visibility of distinct
1841 * system_timestamp/tsc_timestamp values simultaneously: use a master
1842 * copy of host monotonic time values. Update that master copy
1845 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1849 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1851 #ifdef CONFIG_X86_64
1852 struct kvm_arch *ka = &kvm->arch;
1854 bool host_tsc_clocksource, vcpus_matched;
1856 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1857 atomic_read(&kvm->online_vcpus));
1860 * If the host uses TSC clock, then passthrough TSC as stable
1863 host_tsc_clocksource = kvm_get_time_and_clockread(
1864 &ka->master_kernel_ns,
1865 &ka->master_cycle_now);
1867 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1868 && !ka->backwards_tsc_observed
1869 && !ka->boot_vcpu_runs_old_kvmclock;
1871 if (ka->use_master_clock)
1872 atomic_set(&kvm_guest_has_master_clock, 1);
1874 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1875 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1880 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1882 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1885 static void kvm_gen_update_masterclock(struct kvm *kvm)
1887 #ifdef CONFIG_X86_64
1889 struct kvm_vcpu *vcpu;
1890 struct kvm_arch *ka = &kvm->arch;
1892 spin_lock(&ka->pvclock_gtod_sync_lock);
1893 kvm_make_mclock_inprogress_request(kvm);
1894 /* no guest entries from this point */
1895 pvclock_update_vm_gtod_copy(kvm);
1897 kvm_for_each_vcpu(i, vcpu, kvm)
1898 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1900 /* guest entries allowed */
1901 kvm_for_each_vcpu(i, vcpu, kvm)
1902 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
1904 spin_unlock(&ka->pvclock_gtod_sync_lock);
1908 u64 get_kvmclock_ns(struct kvm *kvm)
1910 struct kvm_arch *ka = &kvm->arch;
1911 struct pvclock_vcpu_time_info hv_clock;
1914 spin_lock(&ka->pvclock_gtod_sync_lock);
1915 if (!ka->use_master_clock) {
1916 spin_unlock(&ka->pvclock_gtod_sync_lock);
1917 return ktime_get_boot_ns() + ka->kvmclock_offset;
1920 hv_clock.tsc_timestamp = ka->master_cycle_now;
1921 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1922 spin_unlock(&ka->pvclock_gtod_sync_lock);
1924 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1927 if (__this_cpu_read(cpu_tsc_khz)) {
1928 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1929 &hv_clock.tsc_shift,
1930 &hv_clock.tsc_to_system_mul);
1931 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1933 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
1940 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1942 struct kvm_vcpu_arch *vcpu = &v->arch;
1943 struct pvclock_vcpu_time_info guest_hv_clock;
1945 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1946 &guest_hv_clock, sizeof(guest_hv_clock))))
1949 /* This VCPU is paused, but it's legal for a guest to read another
1950 * VCPU's kvmclock, so we really have to follow the specification where
1951 * it says that version is odd if data is being modified, and even after
1954 * Version field updates must be kept separate. This is because
1955 * kvm_write_guest_cached might use a "rep movs" instruction, and
1956 * writes within a string instruction are weakly ordered. So there
1957 * are three writes overall.
1959 * As a small optimization, only write the version field in the first
1960 * and third write. The vcpu->pv_time cache is still valid, because the
1961 * version field is the first in the struct.
1963 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1965 if (guest_hv_clock.version & 1)
1966 ++guest_hv_clock.version; /* first time write, random junk */
1968 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1969 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1971 sizeof(vcpu->hv_clock.version));
1975 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1976 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1978 if (vcpu->pvclock_set_guest_stopped_request) {
1979 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1980 vcpu->pvclock_set_guest_stopped_request = false;
1983 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1985 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1987 sizeof(vcpu->hv_clock));
1991 vcpu->hv_clock.version++;
1992 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1994 sizeof(vcpu->hv_clock.version));
1997 static int kvm_guest_time_update(struct kvm_vcpu *v)
1999 unsigned long flags, tgt_tsc_khz;
2000 struct kvm_vcpu_arch *vcpu = &v->arch;
2001 struct kvm_arch *ka = &v->kvm->arch;
2003 u64 tsc_timestamp, host_tsc;
2005 bool use_master_clock;
2011 * If the host uses TSC clock, then passthrough TSC as stable
2014 spin_lock(&ka->pvclock_gtod_sync_lock);
2015 use_master_clock = ka->use_master_clock;
2016 if (use_master_clock) {
2017 host_tsc = ka->master_cycle_now;
2018 kernel_ns = ka->master_kernel_ns;
2020 spin_unlock(&ka->pvclock_gtod_sync_lock);
2022 /* Keep irq disabled to prevent changes to the clock */
2023 local_irq_save(flags);
2024 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2025 if (unlikely(tgt_tsc_khz == 0)) {
2026 local_irq_restore(flags);
2027 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2030 if (!use_master_clock) {
2032 kernel_ns = ktime_get_boot_ns();
2035 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2038 * We may have to catch up the TSC to match elapsed wall clock
2039 * time for two reasons, even if kvmclock is used.
2040 * 1) CPU could have been running below the maximum TSC rate
2041 * 2) Broken TSC compensation resets the base at each VCPU
2042 * entry to avoid unknown leaps of TSC even when running
2043 * again on the same CPU. This may cause apparent elapsed
2044 * time to disappear, and the guest to stand still or run
2047 if (vcpu->tsc_catchup) {
2048 u64 tsc = compute_guest_tsc(v, kernel_ns);
2049 if (tsc > tsc_timestamp) {
2050 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2051 tsc_timestamp = tsc;
2055 local_irq_restore(flags);
2057 /* With all the info we got, fill in the values */
2059 if (kvm_has_tsc_control)
2060 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2062 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2063 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2064 &vcpu->hv_clock.tsc_shift,
2065 &vcpu->hv_clock.tsc_to_system_mul);
2066 vcpu->hw_tsc_khz = tgt_tsc_khz;
2069 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2070 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2071 vcpu->last_guest_tsc = tsc_timestamp;
2073 /* If the host uses TSC clocksource, then it is stable */
2075 if (use_master_clock)
2076 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2078 vcpu->hv_clock.flags = pvclock_flags;
2080 if (vcpu->pv_time_enabled)
2081 kvm_setup_pvclock_page(v);
2082 if (v == kvm_get_vcpu(v->kvm, 0))
2083 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2088 * kvmclock updates which are isolated to a given vcpu, such as
2089 * vcpu->cpu migration, should not allow system_timestamp from
2090 * the rest of the vcpus to remain static. Otherwise ntp frequency
2091 * correction applies to one vcpu's system_timestamp but not
2094 * So in those cases, request a kvmclock update for all vcpus.
2095 * We need to rate-limit these requests though, as they can
2096 * considerably slow guests that have a large number of vcpus.
2097 * The time for a remote vcpu to update its kvmclock is bound
2098 * by the delay we use to rate-limit the updates.
2101 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2103 static void kvmclock_update_fn(struct work_struct *work)
2106 struct delayed_work *dwork = to_delayed_work(work);
2107 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2108 kvmclock_update_work);
2109 struct kvm *kvm = container_of(ka, struct kvm, arch);
2110 struct kvm_vcpu *vcpu;
2112 kvm_for_each_vcpu(i, vcpu, kvm) {
2113 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2114 kvm_vcpu_kick(vcpu);
2118 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2120 struct kvm *kvm = v->kvm;
2122 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2123 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2124 KVMCLOCK_UPDATE_DELAY);
2127 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2129 static void kvmclock_sync_fn(struct work_struct *work)
2131 struct delayed_work *dwork = to_delayed_work(work);
2132 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2133 kvmclock_sync_work);
2134 struct kvm *kvm = container_of(ka, struct kvm, arch);
2136 if (!kvmclock_periodic_sync)
2139 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2140 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2141 KVMCLOCK_SYNC_PERIOD);
2144 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2146 u64 mcg_cap = vcpu->arch.mcg_cap;
2147 unsigned bank_num = mcg_cap & 0xff;
2148 u32 msr = msr_info->index;
2149 u64 data = msr_info->data;
2152 case MSR_IA32_MCG_STATUS:
2153 vcpu->arch.mcg_status = data;
2155 case MSR_IA32_MCG_CTL:
2156 if (!(mcg_cap & MCG_CTL_P))
2158 if (data != 0 && data != ~(u64)0)
2160 vcpu->arch.mcg_ctl = data;
2163 if (msr >= MSR_IA32_MC0_CTL &&
2164 msr < MSR_IA32_MCx_CTL(bank_num)) {
2165 u32 offset = msr - MSR_IA32_MC0_CTL;
2166 /* only 0 or all 1s can be written to IA32_MCi_CTL
2167 * some Linux kernels though clear bit 10 in bank 4 to
2168 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2169 * this to avoid an uncatched #GP in the guest
2171 if ((offset & 0x3) == 0 &&
2172 data != 0 && (data | (1 << 10)) != ~(u64)0)
2174 if (!msr_info->host_initiated &&
2175 (offset & 0x3) == 1 && data != 0)
2177 vcpu->arch.mce_banks[offset] = data;
2185 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2187 struct kvm *kvm = vcpu->kvm;
2188 int lm = is_long_mode(vcpu);
2189 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2190 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2191 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2192 : kvm->arch.xen_hvm_config.blob_size_32;
2193 u32 page_num = data & ~PAGE_MASK;
2194 u64 page_addr = data & PAGE_MASK;
2199 if (page_num >= blob_size)
2202 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2207 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2216 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2218 gpa_t gpa = data & ~0x3f;
2220 /* Bits 3:5 are reserved, Should be zero */
2224 vcpu->arch.apf.msr_val = data;
2226 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2227 kvm_clear_async_pf_completion_queue(vcpu);
2228 kvm_async_pf_hash_reset(vcpu);
2232 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2236 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2237 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2238 kvm_async_pf_wakeup_all(vcpu);
2242 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2244 vcpu->arch.pv_time_enabled = false;
2247 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2249 ++vcpu->stat.tlb_flush;
2250 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2253 static void record_steal_time(struct kvm_vcpu *vcpu)
2255 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2258 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2259 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2263 * Doing a TLB flush here, on the guest's behalf, can avoid
2266 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2267 kvm_vcpu_flush_tlb(vcpu, false);
2269 if (vcpu->arch.st.steal.version & 1)
2270 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2272 vcpu->arch.st.steal.version += 1;
2274 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2275 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2279 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2280 vcpu->arch.st.last_steal;
2281 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2283 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2284 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2288 vcpu->arch.st.steal.version += 1;
2290 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2291 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2294 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2297 u32 msr = msr_info->index;
2298 u64 data = msr_info->data;
2301 case MSR_AMD64_NB_CFG:
2302 case MSR_IA32_UCODE_WRITE:
2303 case MSR_VM_HSAVE_PA:
2304 case MSR_AMD64_PATCH_LOADER:
2305 case MSR_AMD64_BU_CFG2:
2306 case MSR_AMD64_DC_CFG:
2309 case MSR_IA32_UCODE_REV:
2310 if (msr_info->host_initiated)
2311 vcpu->arch.microcode_version = data;
2314 return set_efer(vcpu, data);
2316 data &= ~(u64)0x40; /* ignore flush filter disable */
2317 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2318 data &= ~(u64)0x8; /* ignore TLB cache disable */
2319 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2321 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2326 case MSR_FAM10H_MMIO_CONF_BASE:
2328 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2333 case MSR_IA32_DEBUGCTLMSR:
2335 /* We support the non-activated case already */
2337 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2338 /* Values other than LBR and BTF are vendor-specific,
2339 thus reserved and should throw a #GP */
2342 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2345 case 0x200 ... 0x2ff:
2346 return kvm_mtrr_set_msr(vcpu, msr, data);
2347 case MSR_IA32_APICBASE:
2348 return kvm_set_apic_base(vcpu, msr_info);
2349 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2350 return kvm_x2apic_msr_write(vcpu, msr, data);
2351 case MSR_IA32_TSCDEADLINE:
2352 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2354 case MSR_IA32_TSC_ADJUST:
2355 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2356 if (!msr_info->host_initiated) {
2357 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2358 adjust_tsc_offset_guest(vcpu, adj);
2360 vcpu->arch.ia32_tsc_adjust_msr = data;
2363 case MSR_IA32_MISC_ENABLE:
2364 vcpu->arch.ia32_misc_enable_msr = data;
2366 case MSR_IA32_SMBASE:
2367 if (!msr_info->host_initiated)
2369 vcpu->arch.smbase = data;
2372 kvm_write_tsc(vcpu, msr_info);
2375 if (!msr_info->host_initiated)
2377 vcpu->arch.smi_count = data;
2379 case MSR_KVM_WALL_CLOCK_NEW:
2380 case MSR_KVM_WALL_CLOCK:
2381 vcpu->kvm->arch.wall_clock = data;
2382 kvm_write_wall_clock(vcpu->kvm, data);
2384 case MSR_KVM_SYSTEM_TIME_NEW:
2385 case MSR_KVM_SYSTEM_TIME: {
2386 struct kvm_arch *ka = &vcpu->kvm->arch;
2388 kvmclock_reset(vcpu);
2390 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2391 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2393 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2394 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2396 ka->boot_vcpu_runs_old_kvmclock = tmp;
2399 vcpu->arch.time = data;
2400 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2402 /* we verify if the enable bit is set... */
2406 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2407 &vcpu->arch.pv_time, data & ~1ULL,
2408 sizeof(struct pvclock_vcpu_time_info)))
2409 vcpu->arch.pv_time_enabled = false;
2411 vcpu->arch.pv_time_enabled = true;
2415 case MSR_KVM_ASYNC_PF_EN:
2416 if (kvm_pv_enable_async_pf(vcpu, data))
2419 case MSR_KVM_STEAL_TIME:
2421 if (unlikely(!sched_info_on()))
2424 if (data & KVM_STEAL_RESERVED_MASK)
2427 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2428 data & KVM_STEAL_VALID_BITS,
2429 sizeof(struct kvm_steal_time)))
2432 vcpu->arch.st.msr_val = data;
2434 if (!(data & KVM_MSR_ENABLED))
2437 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2440 case MSR_KVM_PV_EOI_EN:
2441 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2445 case MSR_IA32_MCG_CTL:
2446 case MSR_IA32_MCG_STATUS:
2447 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2448 return set_msr_mce(vcpu, msr_info);
2450 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2451 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2452 pr = true; /* fall through */
2453 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2454 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2455 if (kvm_pmu_is_valid_msr(vcpu, msr))
2456 return kvm_pmu_set_msr(vcpu, msr_info);
2458 if (pr || data != 0)
2459 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2460 "0x%x data 0x%llx\n", msr, data);
2462 case MSR_K7_CLK_CTL:
2464 * Ignore all writes to this no longer documented MSR.
2465 * Writes are only relevant for old K7 processors,
2466 * all pre-dating SVM, but a recommended workaround from
2467 * AMD for these chips. It is possible to specify the
2468 * affected processor models on the command line, hence
2469 * the need to ignore the workaround.
2472 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2473 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2474 case HV_X64_MSR_CRASH_CTL:
2475 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2476 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2477 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2478 case HV_X64_MSR_TSC_EMULATION_STATUS:
2479 return kvm_hv_set_msr_common(vcpu, msr, data,
2480 msr_info->host_initiated);
2481 case MSR_IA32_BBL_CR_CTL3:
2482 /* Drop writes to this legacy MSR -- see rdmsr
2483 * counterpart for further detail.
2485 if (report_ignored_msrs)
2486 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2489 case MSR_AMD64_OSVW_ID_LENGTH:
2490 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2492 vcpu->arch.osvw.length = data;
2494 case MSR_AMD64_OSVW_STATUS:
2495 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2497 vcpu->arch.osvw.status = data;
2499 case MSR_PLATFORM_INFO:
2500 if (!msr_info->host_initiated ||
2501 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2502 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2503 cpuid_fault_enabled(vcpu)))
2505 vcpu->arch.msr_platform_info = data;
2507 case MSR_MISC_FEATURES_ENABLES:
2508 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2509 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2510 !supports_cpuid_fault(vcpu)))
2512 vcpu->arch.msr_misc_features_enables = data;
2515 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2516 return xen_hvm_config(vcpu, data);
2517 if (kvm_pmu_is_valid_msr(vcpu, msr))
2518 return kvm_pmu_set_msr(vcpu, msr_info);
2520 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2524 if (report_ignored_msrs)
2526 "ignored wrmsr: 0x%x data 0x%llx\n",
2533 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2537 * Reads an msr value (of 'msr_index') into 'pdata'.
2538 * Returns 0 on success, non-0 otherwise.
2539 * Assumes vcpu_load() was already called.
2541 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2543 return kvm_x86_ops->get_msr(vcpu, msr);
2545 EXPORT_SYMBOL_GPL(kvm_get_msr);
2547 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2550 u64 mcg_cap = vcpu->arch.mcg_cap;
2551 unsigned bank_num = mcg_cap & 0xff;
2554 case MSR_IA32_P5_MC_ADDR:
2555 case MSR_IA32_P5_MC_TYPE:
2558 case MSR_IA32_MCG_CAP:
2559 data = vcpu->arch.mcg_cap;
2561 case MSR_IA32_MCG_CTL:
2562 if (!(mcg_cap & MCG_CTL_P))
2564 data = vcpu->arch.mcg_ctl;
2566 case MSR_IA32_MCG_STATUS:
2567 data = vcpu->arch.mcg_status;
2570 if (msr >= MSR_IA32_MC0_CTL &&
2571 msr < MSR_IA32_MCx_CTL(bank_num)) {
2572 u32 offset = msr - MSR_IA32_MC0_CTL;
2573 data = vcpu->arch.mce_banks[offset];
2582 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2584 switch (msr_info->index) {
2585 case MSR_IA32_PLATFORM_ID:
2586 case MSR_IA32_EBL_CR_POWERON:
2587 case MSR_IA32_DEBUGCTLMSR:
2588 case MSR_IA32_LASTBRANCHFROMIP:
2589 case MSR_IA32_LASTBRANCHTOIP:
2590 case MSR_IA32_LASTINTFROMIP:
2591 case MSR_IA32_LASTINTTOIP:
2593 case MSR_K8_TSEG_ADDR:
2594 case MSR_K8_TSEG_MASK:
2596 case MSR_VM_HSAVE_PA:
2597 case MSR_K8_INT_PENDING_MSG:
2598 case MSR_AMD64_NB_CFG:
2599 case MSR_FAM10H_MMIO_CONF_BASE:
2600 case MSR_AMD64_BU_CFG2:
2601 case MSR_IA32_PERF_CTL:
2602 case MSR_AMD64_DC_CFG:
2605 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2606 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2607 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2608 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2609 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2610 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2611 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2614 case MSR_IA32_UCODE_REV:
2615 msr_info->data = vcpu->arch.microcode_version;
2618 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2621 case 0x200 ... 0x2ff:
2622 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2623 case 0xcd: /* fsb frequency */
2627 * MSR_EBC_FREQUENCY_ID
2628 * Conservative value valid for even the basic CPU models.
2629 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2630 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2631 * and 266MHz for model 3, or 4. Set Core Clock
2632 * Frequency to System Bus Frequency Ratio to 1 (bits
2633 * 31:24) even though these are only valid for CPU
2634 * models > 2, however guests may end up dividing or
2635 * multiplying by zero otherwise.
2637 case MSR_EBC_FREQUENCY_ID:
2638 msr_info->data = 1 << 24;
2640 case MSR_IA32_APICBASE:
2641 msr_info->data = kvm_get_apic_base(vcpu);
2643 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2644 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2646 case MSR_IA32_TSCDEADLINE:
2647 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2649 case MSR_IA32_TSC_ADJUST:
2650 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2652 case MSR_IA32_MISC_ENABLE:
2653 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2655 case MSR_IA32_SMBASE:
2656 if (!msr_info->host_initiated)
2658 msr_info->data = vcpu->arch.smbase;
2661 msr_info->data = vcpu->arch.smi_count;
2663 case MSR_IA32_PERF_STATUS:
2664 /* TSC increment by tick */
2665 msr_info->data = 1000ULL;
2666 /* CPU multiplier */
2667 msr_info->data |= (((uint64_t)4ULL) << 40);
2670 msr_info->data = vcpu->arch.efer;
2672 case MSR_KVM_WALL_CLOCK:
2673 case MSR_KVM_WALL_CLOCK_NEW:
2674 msr_info->data = vcpu->kvm->arch.wall_clock;
2676 case MSR_KVM_SYSTEM_TIME:
2677 case MSR_KVM_SYSTEM_TIME_NEW:
2678 msr_info->data = vcpu->arch.time;
2680 case MSR_KVM_ASYNC_PF_EN:
2681 msr_info->data = vcpu->arch.apf.msr_val;
2683 case MSR_KVM_STEAL_TIME:
2684 msr_info->data = vcpu->arch.st.msr_val;
2686 case MSR_KVM_PV_EOI_EN:
2687 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2689 case MSR_IA32_P5_MC_ADDR:
2690 case MSR_IA32_P5_MC_TYPE:
2691 case MSR_IA32_MCG_CAP:
2692 case MSR_IA32_MCG_CTL:
2693 case MSR_IA32_MCG_STATUS:
2694 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2695 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2696 case MSR_K7_CLK_CTL:
2698 * Provide expected ramp-up count for K7. All other
2699 * are set to zero, indicating minimum divisors for
2702 * This prevents guest kernels on AMD host with CPU
2703 * type 6, model 8 and higher from exploding due to
2704 * the rdmsr failing.
2706 msr_info->data = 0x20000000;
2708 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2709 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2710 case HV_X64_MSR_CRASH_CTL:
2711 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2712 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2713 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2714 case HV_X64_MSR_TSC_EMULATION_STATUS:
2715 return kvm_hv_get_msr_common(vcpu,
2716 msr_info->index, &msr_info->data);
2718 case MSR_IA32_BBL_CR_CTL3:
2719 /* This legacy MSR exists but isn't fully documented in current
2720 * silicon. It is however accessed by winxp in very narrow
2721 * scenarios where it sets bit #19, itself documented as
2722 * a "reserved" bit. Best effort attempt to source coherent
2723 * read data here should the balance of the register be
2724 * interpreted by the guest:
2726 * L2 cache control register 3: 64GB range, 256KB size,
2727 * enabled, latency 0x1, configured
2729 msr_info->data = 0xbe702111;
2731 case MSR_AMD64_OSVW_ID_LENGTH:
2732 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2734 msr_info->data = vcpu->arch.osvw.length;
2736 case MSR_AMD64_OSVW_STATUS:
2737 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2739 msr_info->data = vcpu->arch.osvw.status;
2741 case MSR_PLATFORM_INFO:
2742 msr_info->data = vcpu->arch.msr_platform_info;
2744 case MSR_MISC_FEATURES_ENABLES:
2745 msr_info->data = vcpu->arch.msr_misc_features_enables;
2748 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2749 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2751 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2755 if (report_ignored_msrs)
2756 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2764 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2767 * Read or write a bunch of msrs. All parameters are kernel addresses.
2769 * @return number of msrs set successfully.
2771 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2772 struct kvm_msr_entry *entries,
2773 int (*do_msr)(struct kvm_vcpu *vcpu,
2774 unsigned index, u64 *data))
2778 for (i = 0; i < msrs->nmsrs; ++i)
2779 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2786 * Read or write a bunch of msrs. Parameters are user addresses.
2788 * @return number of msrs set successfully.
2790 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2791 int (*do_msr)(struct kvm_vcpu *vcpu,
2792 unsigned index, u64 *data),
2795 struct kvm_msrs msrs;
2796 struct kvm_msr_entry *entries;
2801 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2805 if (msrs.nmsrs >= MAX_IO_MSRS)
2808 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2809 entries = memdup_user(user_msrs->entries, size);
2810 if (IS_ERR(entries)) {
2811 r = PTR_ERR(entries);
2815 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2820 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2831 static inline bool kvm_can_mwait_in_guest(void)
2833 return boot_cpu_has(X86_FEATURE_MWAIT) &&
2834 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2835 boot_cpu_has(X86_FEATURE_ARAT);
2838 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2843 case KVM_CAP_IRQCHIP:
2845 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2846 case KVM_CAP_SET_TSS_ADDR:
2847 case KVM_CAP_EXT_CPUID:
2848 case KVM_CAP_EXT_EMUL_CPUID:
2849 case KVM_CAP_CLOCKSOURCE:
2851 case KVM_CAP_NOP_IO_DELAY:
2852 case KVM_CAP_MP_STATE:
2853 case KVM_CAP_SYNC_MMU:
2854 case KVM_CAP_USER_NMI:
2855 case KVM_CAP_REINJECT_CONTROL:
2856 case KVM_CAP_IRQ_INJECT_STATUS:
2857 case KVM_CAP_IOEVENTFD:
2858 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2860 case KVM_CAP_PIT_STATE2:
2861 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2862 case KVM_CAP_XEN_HVM:
2863 case KVM_CAP_VCPU_EVENTS:
2864 case KVM_CAP_HYPERV:
2865 case KVM_CAP_HYPERV_VAPIC:
2866 case KVM_CAP_HYPERV_SPIN:
2867 case KVM_CAP_HYPERV_SYNIC:
2868 case KVM_CAP_HYPERV_SYNIC2:
2869 case KVM_CAP_HYPERV_VP_INDEX:
2870 case KVM_CAP_HYPERV_EVENTFD:
2871 case KVM_CAP_PCI_SEGMENT:
2872 case KVM_CAP_DEBUGREGS:
2873 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2875 case KVM_CAP_ASYNC_PF:
2876 case KVM_CAP_GET_TSC_KHZ:
2877 case KVM_CAP_KVMCLOCK_CTRL:
2878 case KVM_CAP_READONLY_MEM:
2879 case KVM_CAP_HYPERV_TIME:
2880 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2881 case KVM_CAP_TSC_DEADLINE_TIMER:
2882 case KVM_CAP_ENABLE_CAP_VM:
2883 case KVM_CAP_DISABLE_QUIRKS:
2884 case KVM_CAP_SET_BOOT_CPU_ID:
2885 case KVM_CAP_SPLIT_IRQCHIP:
2886 case KVM_CAP_IMMEDIATE_EXIT:
2887 case KVM_CAP_GET_MSR_FEATURES:
2890 case KVM_CAP_SYNC_REGS:
2891 r = KVM_SYNC_X86_VALID_FIELDS;
2893 case KVM_CAP_ADJUST_CLOCK:
2894 r = KVM_CLOCK_TSC_STABLE;
2896 case KVM_CAP_X86_DISABLE_EXITS:
2897 r |= KVM_X86_DISABLE_EXITS_HTL | KVM_X86_DISABLE_EXITS_PAUSE;
2898 if(kvm_can_mwait_in_guest())
2899 r |= KVM_X86_DISABLE_EXITS_MWAIT;
2901 case KVM_CAP_X86_SMM:
2902 /* SMBASE is usually relocated above 1M on modern chipsets,
2903 * and SMM handlers might indeed rely on 4G segment limits,
2904 * so do not report SMM to be available if real mode is
2905 * emulated via vm86 mode. Still, do not go to great lengths
2906 * to avoid userspace's usage of the feature, because it is a
2907 * fringe case that is not enabled except via specific settings
2908 * of the module parameters.
2910 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
2913 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2915 case KVM_CAP_NR_VCPUS:
2916 r = KVM_SOFT_MAX_VCPUS;
2918 case KVM_CAP_MAX_VCPUS:
2921 case KVM_CAP_NR_MEMSLOTS:
2922 r = KVM_USER_MEM_SLOTS;
2924 case KVM_CAP_PV_MMU: /* obsolete */
2928 r = KVM_MAX_MCE_BANKS;
2931 r = boot_cpu_has(X86_FEATURE_XSAVE);
2933 case KVM_CAP_TSC_CONTROL:
2934 r = kvm_has_tsc_control;
2936 case KVM_CAP_X2APIC_API:
2937 r = KVM_X2APIC_API_VALID_FLAGS;
2946 long kvm_arch_dev_ioctl(struct file *filp,
2947 unsigned int ioctl, unsigned long arg)
2949 void __user *argp = (void __user *)arg;
2953 case KVM_GET_MSR_INDEX_LIST: {
2954 struct kvm_msr_list __user *user_msr_list = argp;
2955 struct kvm_msr_list msr_list;
2959 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2962 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2963 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2966 if (n < msr_list.nmsrs)
2969 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2970 num_msrs_to_save * sizeof(u32)))
2972 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2974 num_emulated_msrs * sizeof(u32)))
2979 case KVM_GET_SUPPORTED_CPUID:
2980 case KVM_GET_EMULATED_CPUID: {
2981 struct kvm_cpuid2 __user *cpuid_arg = argp;
2982 struct kvm_cpuid2 cpuid;
2985 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2988 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2994 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2999 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3001 if (copy_to_user(argp, &kvm_mce_cap_supported,
3002 sizeof(kvm_mce_cap_supported)))
3006 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3007 struct kvm_msr_list __user *user_msr_list = argp;
3008 struct kvm_msr_list msr_list;
3012 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3015 msr_list.nmsrs = num_msr_based_features;
3016 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3019 if (n < msr_list.nmsrs)
3022 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3023 num_msr_based_features * sizeof(u32)))
3029 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3039 static void wbinvd_ipi(void *garbage)
3044 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3046 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3049 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3051 /* Address WBINVD may be executed by guest */
3052 if (need_emulate_wbinvd(vcpu)) {
3053 if (kvm_x86_ops->has_wbinvd_exit())
3054 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3055 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3056 smp_call_function_single(vcpu->cpu,
3057 wbinvd_ipi, NULL, 1);
3060 kvm_x86_ops->vcpu_load(vcpu, cpu);
3062 /* Apply any externally detected TSC adjustments (due to suspend) */
3063 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3064 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3065 vcpu->arch.tsc_offset_adjustment = 0;
3066 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3069 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3070 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3071 rdtsc() - vcpu->arch.last_host_tsc;
3073 mark_tsc_unstable("KVM discovered backwards TSC");
3075 if (kvm_check_tsc_unstable()) {
3076 u64 offset = kvm_compute_tsc_offset(vcpu,
3077 vcpu->arch.last_guest_tsc);
3078 kvm_vcpu_write_tsc_offset(vcpu, offset);
3079 vcpu->arch.tsc_catchup = 1;
3082 if (kvm_lapic_hv_timer_in_use(vcpu))
3083 kvm_lapic_restart_hv_timer(vcpu);
3086 * On a host with synchronized TSC, there is no need to update
3087 * kvmclock on vcpu->cpu migration
3089 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3090 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3091 if (vcpu->cpu != cpu)
3092 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3096 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3099 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3101 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3104 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3106 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3107 &vcpu->arch.st.steal.preempted,
3108 offsetof(struct kvm_steal_time, preempted),
3109 sizeof(vcpu->arch.st.steal.preempted));
3112 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3116 if (vcpu->preempted)
3117 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3120 * Disable page faults because we're in atomic context here.
3121 * kvm_write_guest_offset_cached() would call might_fault()
3122 * that relies on pagefault_disable() to tell if there's a
3123 * bug. NOTE: the write to guest memory may not go through if
3124 * during postcopy live migration or if there's heavy guest
3127 pagefault_disable();
3129 * kvm_memslots() will be called by
3130 * kvm_write_guest_offset_cached() so take the srcu lock.
3132 idx = srcu_read_lock(&vcpu->kvm->srcu);
3133 kvm_steal_time_set_preempted(vcpu);
3134 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3136 kvm_x86_ops->vcpu_put(vcpu);
3137 vcpu->arch.last_host_tsc = rdtsc();
3139 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3140 * on every vmexit, but if not, we might have a stale dr6 from the
3141 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3146 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3147 struct kvm_lapic_state *s)
3149 if (vcpu->arch.apicv_active)
3150 kvm_x86_ops->sync_pir_to_irr(vcpu);
3152 return kvm_apic_get_state(vcpu, s);
3155 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3156 struct kvm_lapic_state *s)
3160 r = kvm_apic_set_state(vcpu, s);
3163 update_cr8_intercept(vcpu);
3168 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3170 return (!lapic_in_kernel(vcpu) ||
3171 kvm_apic_accept_pic_intr(vcpu));
3175 * if userspace requested an interrupt window, check that the
3176 * interrupt window is open.
3178 * No need to exit to userspace if we already have an interrupt queued.
3180 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3182 return kvm_arch_interrupt_allowed(vcpu) &&
3183 !kvm_cpu_has_interrupt(vcpu) &&
3184 !kvm_event_needs_reinjection(vcpu) &&
3185 kvm_cpu_accept_dm_intr(vcpu);
3188 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3189 struct kvm_interrupt *irq)
3191 if (irq->irq >= KVM_NR_INTERRUPTS)
3194 if (!irqchip_in_kernel(vcpu->kvm)) {
3195 kvm_queue_interrupt(vcpu, irq->irq, false);
3196 kvm_make_request(KVM_REQ_EVENT, vcpu);
3201 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3202 * fail for in-kernel 8259.
3204 if (pic_in_kernel(vcpu->kvm))
3207 if (vcpu->arch.pending_external_vector != -1)
3210 vcpu->arch.pending_external_vector = irq->irq;
3211 kvm_make_request(KVM_REQ_EVENT, vcpu);
3215 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3217 kvm_inject_nmi(vcpu);
3222 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3224 kvm_make_request(KVM_REQ_SMI, vcpu);
3229 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3230 struct kvm_tpr_access_ctl *tac)
3234 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3238 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3242 unsigned bank_num = mcg_cap & 0xff, bank;
3245 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3247 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3250 vcpu->arch.mcg_cap = mcg_cap;
3251 /* Init IA32_MCG_CTL to all 1s */
3252 if (mcg_cap & MCG_CTL_P)
3253 vcpu->arch.mcg_ctl = ~(u64)0;
3254 /* Init IA32_MCi_CTL to all 1s */
3255 for (bank = 0; bank < bank_num; bank++)
3256 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3258 if (kvm_x86_ops->setup_mce)
3259 kvm_x86_ops->setup_mce(vcpu);
3264 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3265 struct kvm_x86_mce *mce)
3267 u64 mcg_cap = vcpu->arch.mcg_cap;
3268 unsigned bank_num = mcg_cap & 0xff;
3269 u64 *banks = vcpu->arch.mce_banks;
3271 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3274 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3275 * reporting is disabled
3277 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3278 vcpu->arch.mcg_ctl != ~(u64)0)
3280 banks += 4 * mce->bank;
3282 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3283 * reporting is disabled for the bank
3285 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3287 if (mce->status & MCI_STATUS_UC) {
3288 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3289 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3290 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3293 if (banks[1] & MCI_STATUS_VAL)
3294 mce->status |= MCI_STATUS_OVER;
3295 banks[2] = mce->addr;
3296 banks[3] = mce->misc;
3297 vcpu->arch.mcg_status = mce->mcg_status;
3298 banks[1] = mce->status;
3299 kvm_queue_exception(vcpu, MC_VECTOR);
3300 } else if (!(banks[1] & MCI_STATUS_VAL)
3301 || !(banks[1] & MCI_STATUS_UC)) {
3302 if (banks[1] & MCI_STATUS_VAL)
3303 mce->status |= MCI_STATUS_OVER;
3304 banks[2] = mce->addr;
3305 banks[3] = mce->misc;
3306 banks[1] = mce->status;
3308 banks[1] |= MCI_STATUS_OVER;
3312 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3313 struct kvm_vcpu_events *events)
3317 * FIXME: pass injected and pending separately. This is only
3318 * needed for nested virtualization, whose state cannot be
3319 * migrated yet. For now we can combine them.
3321 events->exception.injected =
3322 (vcpu->arch.exception.pending ||
3323 vcpu->arch.exception.injected) &&
3324 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3325 events->exception.nr = vcpu->arch.exception.nr;
3326 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3327 events->exception.pad = 0;
3328 events->exception.error_code = vcpu->arch.exception.error_code;
3330 events->interrupt.injected =
3331 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3332 events->interrupt.nr = vcpu->arch.interrupt.nr;
3333 events->interrupt.soft = 0;
3334 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3336 events->nmi.injected = vcpu->arch.nmi_injected;
3337 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3338 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3339 events->nmi.pad = 0;
3341 events->sipi_vector = 0; /* never valid when reporting to user space */
3343 events->smi.smm = is_smm(vcpu);
3344 events->smi.pending = vcpu->arch.smi_pending;
3345 events->smi.smm_inside_nmi =
3346 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3347 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3349 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3350 | KVM_VCPUEVENT_VALID_SHADOW
3351 | KVM_VCPUEVENT_VALID_SMM);
3352 memset(&events->reserved, 0, sizeof(events->reserved));
3355 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3357 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3358 struct kvm_vcpu_events *events)
3360 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3361 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3362 | KVM_VCPUEVENT_VALID_SHADOW
3363 | KVM_VCPUEVENT_VALID_SMM))
3366 if (events->exception.injected &&
3367 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3368 is_guest_mode(vcpu)))
3371 /* INITs are latched while in SMM */
3372 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3373 (events->smi.smm || events->smi.pending) &&
3374 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3378 vcpu->arch.exception.injected = false;
3379 vcpu->arch.exception.pending = events->exception.injected;
3380 vcpu->arch.exception.nr = events->exception.nr;
3381 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3382 vcpu->arch.exception.error_code = events->exception.error_code;
3384 vcpu->arch.interrupt.injected = events->interrupt.injected;
3385 vcpu->arch.interrupt.nr = events->interrupt.nr;
3386 vcpu->arch.interrupt.soft = events->interrupt.soft;
3387 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3388 kvm_x86_ops->set_interrupt_shadow(vcpu,
3389 events->interrupt.shadow);
3391 vcpu->arch.nmi_injected = events->nmi.injected;
3392 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3393 vcpu->arch.nmi_pending = events->nmi.pending;
3394 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3396 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3397 lapic_in_kernel(vcpu))
3398 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3400 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3401 u32 hflags = vcpu->arch.hflags;
3402 if (events->smi.smm)
3403 hflags |= HF_SMM_MASK;
3405 hflags &= ~HF_SMM_MASK;
3406 kvm_set_hflags(vcpu, hflags);
3408 vcpu->arch.smi_pending = events->smi.pending;
3410 if (events->smi.smm) {
3411 if (events->smi.smm_inside_nmi)
3412 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3414 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3415 if (lapic_in_kernel(vcpu)) {
3416 if (events->smi.latched_init)
3417 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3419 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3424 kvm_make_request(KVM_REQ_EVENT, vcpu);
3429 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3430 struct kvm_debugregs *dbgregs)
3434 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3435 kvm_get_dr(vcpu, 6, &val);
3437 dbgregs->dr7 = vcpu->arch.dr7;
3439 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3442 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3443 struct kvm_debugregs *dbgregs)
3448 if (dbgregs->dr6 & ~0xffffffffull)
3450 if (dbgregs->dr7 & ~0xffffffffull)
3453 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3454 kvm_update_dr0123(vcpu);
3455 vcpu->arch.dr6 = dbgregs->dr6;
3456 kvm_update_dr6(vcpu);
3457 vcpu->arch.dr7 = dbgregs->dr7;
3458 kvm_update_dr7(vcpu);
3463 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3465 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3467 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3468 u64 xstate_bv = xsave->header.xfeatures;
3472 * Copy legacy XSAVE area, to avoid complications with CPUID
3473 * leaves 0 and 1 in the loop below.
3475 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3478 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3479 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3482 * Copy each region from the possibly compacted offset to the
3483 * non-compacted offset.
3485 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3487 u64 feature = valid & -valid;
3488 int index = fls64(feature) - 1;
3489 void *src = get_xsave_addr(xsave, feature);
3492 u32 size, offset, ecx, edx;
3493 cpuid_count(XSTATE_CPUID, index,
3494 &size, &offset, &ecx, &edx);
3495 if (feature == XFEATURE_MASK_PKRU)
3496 memcpy(dest + offset, &vcpu->arch.pkru,
3497 sizeof(vcpu->arch.pkru));
3499 memcpy(dest + offset, src, size);
3507 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3509 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3510 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3514 * Copy legacy XSAVE area, to avoid complications with CPUID
3515 * leaves 0 and 1 in the loop below.
3517 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3519 /* Set XSTATE_BV and possibly XCOMP_BV. */
3520 xsave->header.xfeatures = xstate_bv;
3521 if (boot_cpu_has(X86_FEATURE_XSAVES))
3522 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3525 * Copy each region from the non-compacted offset to the
3526 * possibly compacted offset.
3528 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3530 u64 feature = valid & -valid;
3531 int index = fls64(feature) - 1;
3532 void *dest = get_xsave_addr(xsave, feature);
3535 u32 size, offset, ecx, edx;
3536 cpuid_count(XSTATE_CPUID, index,
3537 &size, &offset, &ecx, &edx);
3538 if (feature == XFEATURE_MASK_PKRU)
3539 memcpy(&vcpu->arch.pkru, src + offset,
3540 sizeof(vcpu->arch.pkru));
3542 memcpy(dest, src + offset, size);
3549 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3550 struct kvm_xsave *guest_xsave)
3552 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3553 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3554 fill_xsave((u8 *) guest_xsave->region, vcpu);
3556 memcpy(guest_xsave->region,
3557 &vcpu->arch.guest_fpu.state.fxsave,
3558 sizeof(struct fxregs_state));
3559 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3560 XFEATURE_MASK_FPSSE;
3564 #define XSAVE_MXCSR_OFFSET 24
3566 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3567 struct kvm_xsave *guest_xsave)
3570 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3571 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3573 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3575 * Here we allow setting states that are not present in
3576 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3577 * with old userspace.
3579 if (xstate_bv & ~kvm_supported_xcr0() ||
3580 mxcsr & ~mxcsr_feature_mask)
3582 load_xsave(vcpu, (u8 *)guest_xsave->region);
3584 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3585 mxcsr & ~mxcsr_feature_mask)
3587 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3588 guest_xsave->region, sizeof(struct fxregs_state));
3593 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3594 struct kvm_xcrs *guest_xcrs)
3596 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3597 guest_xcrs->nr_xcrs = 0;
3601 guest_xcrs->nr_xcrs = 1;
3602 guest_xcrs->flags = 0;
3603 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3604 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3607 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3608 struct kvm_xcrs *guest_xcrs)
3612 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3615 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3618 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3619 /* Only support XCR0 currently */
3620 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3621 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3622 guest_xcrs->xcrs[i].value);
3631 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3632 * stopped by the hypervisor. This function will be called from the host only.
3633 * EINVAL is returned when the host attempts to set the flag for a guest that
3634 * does not support pv clocks.
3636 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3638 if (!vcpu->arch.pv_time_enabled)
3640 vcpu->arch.pvclock_set_guest_stopped_request = true;
3641 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3645 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3646 struct kvm_enable_cap *cap)
3652 case KVM_CAP_HYPERV_SYNIC2:
3655 case KVM_CAP_HYPERV_SYNIC:
3656 if (!irqchip_in_kernel(vcpu->kvm))
3658 return kvm_hv_activate_synic(vcpu, cap->cap ==
3659 KVM_CAP_HYPERV_SYNIC2);
3665 long kvm_arch_vcpu_ioctl(struct file *filp,
3666 unsigned int ioctl, unsigned long arg)
3668 struct kvm_vcpu *vcpu = filp->private_data;
3669 void __user *argp = (void __user *)arg;
3672 struct kvm_lapic_state *lapic;
3673 struct kvm_xsave *xsave;
3674 struct kvm_xcrs *xcrs;
3682 case KVM_GET_LAPIC: {
3684 if (!lapic_in_kernel(vcpu))
3686 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3691 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3695 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3700 case KVM_SET_LAPIC: {
3702 if (!lapic_in_kernel(vcpu))
3704 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3705 if (IS_ERR(u.lapic)) {
3706 r = PTR_ERR(u.lapic);
3710 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3713 case KVM_INTERRUPT: {
3714 struct kvm_interrupt irq;
3717 if (copy_from_user(&irq, argp, sizeof irq))
3719 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3723 r = kvm_vcpu_ioctl_nmi(vcpu);
3727 r = kvm_vcpu_ioctl_smi(vcpu);
3730 case KVM_SET_CPUID: {
3731 struct kvm_cpuid __user *cpuid_arg = argp;
3732 struct kvm_cpuid cpuid;
3735 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3737 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3740 case KVM_SET_CPUID2: {
3741 struct kvm_cpuid2 __user *cpuid_arg = argp;
3742 struct kvm_cpuid2 cpuid;
3745 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3747 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3748 cpuid_arg->entries);
3751 case KVM_GET_CPUID2: {
3752 struct kvm_cpuid2 __user *cpuid_arg = argp;
3753 struct kvm_cpuid2 cpuid;
3756 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3758 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3759 cpuid_arg->entries);
3763 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3768 case KVM_GET_MSRS: {
3769 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3770 r = msr_io(vcpu, argp, do_get_msr, 1);
3771 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3774 case KVM_SET_MSRS: {
3775 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3776 r = msr_io(vcpu, argp, do_set_msr, 0);
3777 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3780 case KVM_TPR_ACCESS_REPORTING: {
3781 struct kvm_tpr_access_ctl tac;
3784 if (copy_from_user(&tac, argp, sizeof tac))
3786 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3790 if (copy_to_user(argp, &tac, sizeof tac))
3795 case KVM_SET_VAPIC_ADDR: {
3796 struct kvm_vapic_addr va;
3800 if (!lapic_in_kernel(vcpu))
3803 if (copy_from_user(&va, argp, sizeof va))
3805 idx = srcu_read_lock(&vcpu->kvm->srcu);
3806 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3807 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3810 case KVM_X86_SETUP_MCE: {
3814 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3816 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3819 case KVM_X86_SET_MCE: {
3820 struct kvm_x86_mce mce;
3823 if (copy_from_user(&mce, argp, sizeof mce))
3825 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3828 case KVM_GET_VCPU_EVENTS: {
3829 struct kvm_vcpu_events events;
3831 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3834 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3839 case KVM_SET_VCPU_EVENTS: {
3840 struct kvm_vcpu_events events;
3843 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3846 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3849 case KVM_GET_DEBUGREGS: {
3850 struct kvm_debugregs dbgregs;
3852 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3855 if (copy_to_user(argp, &dbgregs,
3856 sizeof(struct kvm_debugregs)))
3861 case KVM_SET_DEBUGREGS: {
3862 struct kvm_debugregs dbgregs;
3865 if (copy_from_user(&dbgregs, argp,
3866 sizeof(struct kvm_debugregs)))
3869 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3872 case KVM_GET_XSAVE: {
3873 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3878 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3881 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3886 case KVM_SET_XSAVE: {
3887 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3888 if (IS_ERR(u.xsave)) {
3889 r = PTR_ERR(u.xsave);
3893 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3896 case KVM_GET_XCRS: {
3897 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3902 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3905 if (copy_to_user(argp, u.xcrs,
3906 sizeof(struct kvm_xcrs)))
3911 case KVM_SET_XCRS: {
3912 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3913 if (IS_ERR(u.xcrs)) {
3914 r = PTR_ERR(u.xcrs);
3918 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3921 case KVM_SET_TSC_KHZ: {
3925 user_tsc_khz = (u32)arg;
3927 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3930 if (user_tsc_khz == 0)
3931 user_tsc_khz = tsc_khz;
3933 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3938 case KVM_GET_TSC_KHZ: {
3939 r = vcpu->arch.virtual_tsc_khz;
3942 case KVM_KVMCLOCK_CTRL: {
3943 r = kvm_set_guest_paused(vcpu);
3946 case KVM_ENABLE_CAP: {
3947 struct kvm_enable_cap cap;
3950 if (copy_from_user(&cap, argp, sizeof(cap)))
3952 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3965 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3967 return VM_FAULT_SIGBUS;
3970 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3974 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3976 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3980 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3983 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
3986 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3987 u32 kvm_nr_mmu_pages)
3989 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3992 mutex_lock(&kvm->slots_lock);
3994 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3995 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3997 mutex_unlock(&kvm->slots_lock);
4001 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4003 return kvm->arch.n_max_mmu_pages;
4006 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4008 struct kvm_pic *pic = kvm->arch.vpic;
4012 switch (chip->chip_id) {
4013 case KVM_IRQCHIP_PIC_MASTER:
4014 memcpy(&chip->chip.pic, &pic->pics[0],
4015 sizeof(struct kvm_pic_state));
4017 case KVM_IRQCHIP_PIC_SLAVE:
4018 memcpy(&chip->chip.pic, &pic->pics[1],
4019 sizeof(struct kvm_pic_state));
4021 case KVM_IRQCHIP_IOAPIC:
4022 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4031 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4033 struct kvm_pic *pic = kvm->arch.vpic;
4037 switch (chip->chip_id) {
4038 case KVM_IRQCHIP_PIC_MASTER:
4039 spin_lock(&pic->lock);
4040 memcpy(&pic->pics[0], &chip->chip.pic,
4041 sizeof(struct kvm_pic_state));
4042 spin_unlock(&pic->lock);
4044 case KVM_IRQCHIP_PIC_SLAVE:
4045 spin_lock(&pic->lock);
4046 memcpy(&pic->pics[1], &chip->chip.pic,
4047 sizeof(struct kvm_pic_state));
4048 spin_unlock(&pic->lock);
4050 case KVM_IRQCHIP_IOAPIC:
4051 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4057 kvm_pic_update_irq(pic);
4061 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4063 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4065 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4067 mutex_lock(&kps->lock);
4068 memcpy(ps, &kps->channels, sizeof(*ps));
4069 mutex_unlock(&kps->lock);
4073 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4076 struct kvm_pit *pit = kvm->arch.vpit;
4078 mutex_lock(&pit->pit_state.lock);
4079 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4080 for (i = 0; i < 3; i++)
4081 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4082 mutex_unlock(&pit->pit_state.lock);
4086 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4088 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4089 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4090 sizeof(ps->channels));
4091 ps->flags = kvm->arch.vpit->pit_state.flags;
4092 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4093 memset(&ps->reserved, 0, sizeof(ps->reserved));
4097 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4101 u32 prev_legacy, cur_legacy;
4102 struct kvm_pit *pit = kvm->arch.vpit;
4104 mutex_lock(&pit->pit_state.lock);
4105 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4106 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4107 if (!prev_legacy && cur_legacy)
4109 memcpy(&pit->pit_state.channels, &ps->channels,
4110 sizeof(pit->pit_state.channels));
4111 pit->pit_state.flags = ps->flags;
4112 for (i = 0; i < 3; i++)
4113 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4115 mutex_unlock(&pit->pit_state.lock);
4119 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4120 struct kvm_reinject_control *control)
4122 struct kvm_pit *pit = kvm->arch.vpit;
4127 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4128 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4129 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4131 mutex_lock(&pit->pit_state.lock);
4132 kvm_pit_set_reinject(pit, control->pit_reinject);
4133 mutex_unlock(&pit->pit_state.lock);
4139 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4140 * @kvm: kvm instance
4141 * @log: slot id and address to which we copy the log
4143 * Steps 1-4 below provide general overview of dirty page logging. See
4144 * kvm_get_dirty_log_protect() function description for additional details.
4146 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4147 * always flush the TLB (step 4) even if previous step failed and the dirty
4148 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4149 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4150 * writes will be marked dirty for next log read.
4152 * 1. Take a snapshot of the bit and clear it if needed.
4153 * 2. Write protect the corresponding page.
4154 * 3. Copy the snapshot to the userspace.
4155 * 4. Flush TLB's if needed.
4157 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4159 bool is_dirty = false;
4162 mutex_lock(&kvm->slots_lock);
4165 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4167 if (kvm_x86_ops->flush_log_dirty)
4168 kvm_x86_ops->flush_log_dirty(kvm);
4170 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
4173 * All the TLBs can be flushed out of mmu lock, see the comments in
4174 * kvm_mmu_slot_remove_write_access().
4176 lockdep_assert_held(&kvm->slots_lock);
4178 kvm_flush_remote_tlbs(kvm);
4180 mutex_unlock(&kvm->slots_lock);
4184 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4187 if (!irqchip_in_kernel(kvm))
4190 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4191 irq_event->irq, irq_event->level,
4196 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4197 struct kvm_enable_cap *cap)
4205 case KVM_CAP_DISABLE_QUIRKS:
4206 kvm->arch.disabled_quirks = cap->args[0];
4209 case KVM_CAP_SPLIT_IRQCHIP: {
4210 mutex_lock(&kvm->lock);
4212 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4213 goto split_irqchip_unlock;
4215 if (irqchip_in_kernel(kvm))
4216 goto split_irqchip_unlock;
4217 if (kvm->created_vcpus)
4218 goto split_irqchip_unlock;
4219 r = kvm_setup_empty_irq_routing(kvm);
4221 goto split_irqchip_unlock;
4222 /* Pairs with irqchip_in_kernel. */
4224 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4225 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4227 split_irqchip_unlock:
4228 mutex_unlock(&kvm->lock);
4231 case KVM_CAP_X2APIC_API:
4233 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4236 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4237 kvm->arch.x2apic_format = true;
4238 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4239 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4243 case KVM_CAP_X86_DISABLE_EXITS:
4245 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4248 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4249 kvm_can_mwait_in_guest())
4250 kvm->arch.mwait_in_guest = true;
4251 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HTL)
4252 kvm->arch.hlt_in_guest = true;
4253 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4254 kvm->arch.pause_in_guest = true;
4264 long kvm_arch_vm_ioctl(struct file *filp,
4265 unsigned int ioctl, unsigned long arg)
4267 struct kvm *kvm = filp->private_data;
4268 void __user *argp = (void __user *)arg;
4271 * This union makes it completely explicit to gcc-3.x
4272 * that these two variables' stack usage should be
4273 * combined, not added together.
4276 struct kvm_pit_state ps;
4277 struct kvm_pit_state2 ps2;
4278 struct kvm_pit_config pit_config;
4282 case KVM_SET_TSS_ADDR:
4283 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4285 case KVM_SET_IDENTITY_MAP_ADDR: {
4288 mutex_lock(&kvm->lock);
4290 if (kvm->created_vcpus)
4291 goto set_identity_unlock;
4293 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4294 goto set_identity_unlock;
4295 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4296 set_identity_unlock:
4297 mutex_unlock(&kvm->lock);
4300 case KVM_SET_NR_MMU_PAGES:
4301 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4303 case KVM_GET_NR_MMU_PAGES:
4304 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4306 case KVM_CREATE_IRQCHIP: {
4307 mutex_lock(&kvm->lock);
4310 if (irqchip_in_kernel(kvm))
4311 goto create_irqchip_unlock;
4314 if (kvm->created_vcpus)
4315 goto create_irqchip_unlock;
4317 r = kvm_pic_init(kvm);
4319 goto create_irqchip_unlock;
4321 r = kvm_ioapic_init(kvm);
4323 kvm_pic_destroy(kvm);
4324 goto create_irqchip_unlock;
4327 r = kvm_setup_default_irq_routing(kvm);
4329 kvm_ioapic_destroy(kvm);
4330 kvm_pic_destroy(kvm);
4331 goto create_irqchip_unlock;
4333 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4335 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4336 create_irqchip_unlock:
4337 mutex_unlock(&kvm->lock);
4340 case KVM_CREATE_PIT:
4341 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4343 case KVM_CREATE_PIT2:
4345 if (copy_from_user(&u.pit_config, argp,
4346 sizeof(struct kvm_pit_config)))
4349 mutex_lock(&kvm->lock);
4352 goto create_pit_unlock;
4354 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4358 mutex_unlock(&kvm->lock);
4360 case KVM_GET_IRQCHIP: {
4361 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4362 struct kvm_irqchip *chip;
4364 chip = memdup_user(argp, sizeof(*chip));
4371 if (!irqchip_kernel(kvm))
4372 goto get_irqchip_out;
4373 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4375 goto get_irqchip_out;
4377 if (copy_to_user(argp, chip, sizeof *chip))
4378 goto get_irqchip_out;
4384 case KVM_SET_IRQCHIP: {
4385 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4386 struct kvm_irqchip *chip;
4388 chip = memdup_user(argp, sizeof(*chip));
4395 if (!irqchip_kernel(kvm))
4396 goto set_irqchip_out;
4397 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4399 goto set_irqchip_out;
4407 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4410 if (!kvm->arch.vpit)
4412 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4416 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4423 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4426 if (!kvm->arch.vpit)
4428 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4431 case KVM_GET_PIT2: {
4433 if (!kvm->arch.vpit)
4435 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4439 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4444 case KVM_SET_PIT2: {
4446 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4449 if (!kvm->arch.vpit)
4451 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4454 case KVM_REINJECT_CONTROL: {
4455 struct kvm_reinject_control control;
4457 if (copy_from_user(&control, argp, sizeof(control)))
4459 r = kvm_vm_ioctl_reinject(kvm, &control);
4462 case KVM_SET_BOOT_CPU_ID:
4464 mutex_lock(&kvm->lock);
4465 if (kvm->created_vcpus)
4468 kvm->arch.bsp_vcpu_id = arg;
4469 mutex_unlock(&kvm->lock);
4471 case KVM_XEN_HVM_CONFIG: {
4472 struct kvm_xen_hvm_config xhc;
4474 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4479 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4483 case KVM_SET_CLOCK: {
4484 struct kvm_clock_data user_ns;
4488 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4497 * TODO: userspace has to take care of races with VCPU_RUN, so
4498 * kvm_gen_update_masterclock() can be cut down to locked
4499 * pvclock_update_vm_gtod_copy().
4501 kvm_gen_update_masterclock(kvm);
4502 now_ns = get_kvmclock_ns(kvm);
4503 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4504 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4507 case KVM_GET_CLOCK: {
4508 struct kvm_clock_data user_ns;
4511 now_ns = get_kvmclock_ns(kvm);
4512 user_ns.clock = now_ns;
4513 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4514 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4517 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4522 case KVM_ENABLE_CAP: {
4523 struct kvm_enable_cap cap;
4526 if (copy_from_user(&cap, argp, sizeof(cap)))
4528 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4531 case KVM_MEMORY_ENCRYPT_OP: {
4533 if (kvm_x86_ops->mem_enc_op)
4534 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4537 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4538 struct kvm_enc_region region;
4541 if (copy_from_user(®ion, argp, sizeof(region)))
4545 if (kvm_x86_ops->mem_enc_reg_region)
4546 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion);
4549 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4550 struct kvm_enc_region region;
4553 if (copy_from_user(®ion, argp, sizeof(region)))
4557 if (kvm_x86_ops->mem_enc_unreg_region)
4558 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion);
4561 case KVM_HYPERV_EVENTFD: {
4562 struct kvm_hyperv_eventfd hvevfd;
4565 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4567 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4577 static void kvm_init_msr_list(void)
4582 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4583 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4587 * Even MSRs that are valid in the host may not be exposed
4588 * to the guests in some cases.
4590 switch (msrs_to_save[i]) {
4591 case MSR_IA32_BNDCFGS:
4592 if (!kvm_x86_ops->mpx_supported())
4596 if (!kvm_x86_ops->rdtscp_supported())
4604 msrs_to_save[j] = msrs_to_save[i];
4607 num_msrs_to_save = j;
4609 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4610 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4614 emulated_msrs[j] = emulated_msrs[i];
4617 num_emulated_msrs = j;
4619 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4620 struct kvm_msr_entry msr;
4622 msr.index = msr_based_features[i];
4623 if (kvm_get_msr_feature(&msr))
4627 msr_based_features[j] = msr_based_features[i];
4630 num_msr_based_features = j;
4633 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4641 if (!(lapic_in_kernel(vcpu) &&
4642 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4643 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4654 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4661 if (!(lapic_in_kernel(vcpu) &&
4662 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4664 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4666 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
4676 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4677 struct kvm_segment *var, int seg)
4679 kvm_x86_ops->set_segment(vcpu, var, seg);
4682 void kvm_get_segment(struct kvm_vcpu *vcpu,
4683 struct kvm_segment *var, int seg)
4685 kvm_x86_ops->get_segment(vcpu, var, seg);
4688 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4689 struct x86_exception *exception)
4693 BUG_ON(!mmu_is_nested(vcpu));
4695 /* NPT walks are always user-walks */
4696 access |= PFERR_USER_MASK;
4697 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4702 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4703 struct x86_exception *exception)
4705 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4706 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4709 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4710 struct x86_exception *exception)
4712 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4713 access |= PFERR_FETCH_MASK;
4714 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4717 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4718 struct x86_exception *exception)
4720 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4721 access |= PFERR_WRITE_MASK;
4722 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4725 /* uses this to access any guest's mapped memory without checking CPL */
4726 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4727 struct x86_exception *exception)
4729 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4732 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4733 struct kvm_vcpu *vcpu, u32 access,
4734 struct x86_exception *exception)
4737 int r = X86EMUL_CONTINUE;
4740 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4742 unsigned offset = addr & (PAGE_SIZE-1);
4743 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4746 if (gpa == UNMAPPED_GVA)
4747 return X86EMUL_PROPAGATE_FAULT;
4748 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4751 r = X86EMUL_IO_NEEDED;
4763 /* used for instruction fetching */
4764 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4765 gva_t addr, void *val, unsigned int bytes,
4766 struct x86_exception *exception)
4768 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4769 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4773 /* Inline kvm_read_guest_virt_helper for speed. */
4774 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4776 if (unlikely(gpa == UNMAPPED_GVA))
4777 return X86EMUL_PROPAGATE_FAULT;
4779 offset = addr & (PAGE_SIZE-1);
4780 if (WARN_ON(offset + bytes > PAGE_SIZE))
4781 bytes = (unsigned)PAGE_SIZE - offset;
4782 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4784 if (unlikely(ret < 0))
4785 return X86EMUL_IO_NEEDED;
4787 return X86EMUL_CONTINUE;
4790 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4791 gva_t addr, void *val, unsigned int bytes,
4792 struct x86_exception *exception)
4794 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4795 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4797 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4800 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4802 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4803 gva_t addr, void *val, unsigned int bytes,
4804 struct x86_exception *exception)
4806 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4807 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4810 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4811 unsigned long addr, void *val, unsigned int bytes)
4813 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4814 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4816 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4819 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4820 gva_t addr, void *val,
4822 struct x86_exception *exception)
4824 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4826 int r = X86EMUL_CONTINUE;
4829 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4832 unsigned offset = addr & (PAGE_SIZE-1);
4833 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4836 if (gpa == UNMAPPED_GVA)
4837 return X86EMUL_PROPAGATE_FAULT;
4838 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4840 r = X86EMUL_IO_NEEDED;
4851 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4853 int handle_ud(struct kvm_vcpu *vcpu)
4855 int emul_type = EMULTYPE_TRAP_UD;
4856 enum emulation_result er;
4857 char sig[5]; /* ud2; .ascii "kvm" */
4858 struct x86_exception e;
4860 if (force_emulation_prefix &&
4861 kvm_read_guest_virt(&vcpu->arch.emulate_ctxt,
4862 kvm_get_linear_rip(vcpu), sig, sizeof(sig), &e) == 0 &&
4863 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
4864 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
4868 er = emulate_instruction(vcpu, emul_type);
4869 if (er == EMULATE_USER_EXIT)
4871 if (er != EMULATE_DONE)
4872 kvm_queue_exception(vcpu, UD_VECTOR);
4875 EXPORT_SYMBOL_GPL(handle_ud);
4877 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4878 gpa_t gpa, bool write)
4880 /* For APIC access vmexit */
4881 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4884 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4885 trace_vcpu_match_mmio(gva, gpa, write, true);
4892 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4893 gpa_t *gpa, struct x86_exception *exception,
4896 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4897 | (write ? PFERR_WRITE_MASK : 0);
4900 * currently PKRU is only applied to ept enabled guest so
4901 * there is no pkey in EPT page table for L1 guest or EPT
4902 * shadow page table for L2 guest.
4904 if (vcpu_match_mmio_gva(vcpu, gva)
4905 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4906 vcpu->arch.access, 0, access)) {
4907 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4908 (gva & (PAGE_SIZE - 1));
4909 trace_vcpu_match_mmio(gva, *gpa, write, false);
4913 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4915 if (*gpa == UNMAPPED_GVA)
4918 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4921 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4922 const void *val, int bytes)
4926 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4929 kvm_page_track_write(vcpu, gpa, val, bytes);
4933 struct read_write_emulator_ops {
4934 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4936 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4937 void *val, int bytes);
4938 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4939 int bytes, void *val);
4940 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4941 void *val, int bytes);
4945 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4947 if (vcpu->mmio_read_completed) {
4948 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4949 vcpu->mmio_fragments[0].gpa, val);
4950 vcpu->mmio_read_completed = 0;
4957 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4958 void *val, int bytes)
4960 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4963 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4964 void *val, int bytes)
4966 return emulator_write_phys(vcpu, gpa, val, bytes);
4969 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4971 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
4972 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4975 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4976 void *val, int bytes)
4978 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
4979 return X86EMUL_IO_NEEDED;
4982 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4983 void *val, int bytes)
4985 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4987 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4988 return X86EMUL_CONTINUE;
4991 static const struct read_write_emulator_ops read_emultor = {
4992 .read_write_prepare = read_prepare,
4993 .read_write_emulate = read_emulate,
4994 .read_write_mmio = vcpu_mmio_read,
4995 .read_write_exit_mmio = read_exit_mmio,
4998 static const struct read_write_emulator_ops write_emultor = {
4999 .read_write_emulate = write_emulate,
5000 .read_write_mmio = write_mmio,
5001 .read_write_exit_mmio = write_exit_mmio,
5005 static int emulator_read_write_onepage(unsigned long addr, void *val,
5007 struct x86_exception *exception,
5008 struct kvm_vcpu *vcpu,
5009 const struct read_write_emulator_ops *ops)
5013 bool write = ops->write;
5014 struct kvm_mmio_fragment *frag;
5015 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5018 * If the exit was due to a NPF we may already have a GPA.
5019 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5020 * Note, this cannot be used on string operations since string
5021 * operation using rep will only have the initial GPA from the NPF
5024 if (vcpu->arch.gpa_available &&
5025 emulator_can_use_gpa(ctxt) &&
5026 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5027 gpa = vcpu->arch.gpa_val;
5028 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5030 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5032 return X86EMUL_PROPAGATE_FAULT;
5035 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5036 return X86EMUL_CONTINUE;
5039 * Is this MMIO handled locally?
5041 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5042 if (handled == bytes)
5043 return X86EMUL_CONTINUE;
5049 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5050 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5054 return X86EMUL_CONTINUE;
5057 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5059 void *val, unsigned int bytes,
5060 struct x86_exception *exception,
5061 const struct read_write_emulator_ops *ops)
5063 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5067 if (ops->read_write_prepare &&
5068 ops->read_write_prepare(vcpu, val, bytes))
5069 return X86EMUL_CONTINUE;
5071 vcpu->mmio_nr_fragments = 0;
5073 /* Crossing a page boundary? */
5074 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5077 now = -addr & ~PAGE_MASK;
5078 rc = emulator_read_write_onepage(addr, val, now, exception,
5081 if (rc != X86EMUL_CONTINUE)
5084 if (ctxt->mode != X86EMUL_MODE_PROT64)
5090 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5092 if (rc != X86EMUL_CONTINUE)
5095 if (!vcpu->mmio_nr_fragments)
5098 gpa = vcpu->mmio_fragments[0].gpa;
5100 vcpu->mmio_needed = 1;
5101 vcpu->mmio_cur_fragment = 0;
5103 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5104 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5105 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5106 vcpu->run->mmio.phys_addr = gpa;
5108 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5111 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5115 struct x86_exception *exception)
5117 return emulator_read_write(ctxt, addr, val, bytes,
5118 exception, &read_emultor);
5121 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5125 struct x86_exception *exception)
5127 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5128 exception, &write_emultor);
5131 #define CMPXCHG_TYPE(t, ptr, old, new) \
5132 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5134 #ifdef CONFIG_X86_64
5135 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5137 # define CMPXCHG64(ptr, old, new) \
5138 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5141 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5146 struct x86_exception *exception)
5148 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5154 /* guests cmpxchg8b have to be emulated atomically */
5155 if (bytes > 8 || (bytes & (bytes - 1)))
5158 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5160 if (gpa == UNMAPPED_GVA ||
5161 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5164 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5167 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
5168 if (is_error_page(page))
5171 kaddr = kmap_atomic(page);
5172 kaddr += offset_in_page(gpa);
5175 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5178 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5181 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5184 exchanged = CMPXCHG64(kaddr, old, new);
5189 kunmap_atomic(kaddr);
5190 kvm_release_page_dirty(page);
5193 return X86EMUL_CMPXCHG_FAILED;
5195 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5196 kvm_page_track_write(vcpu, gpa, new, bytes);
5198 return X86EMUL_CONTINUE;
5201 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5203 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5206 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5210 for (i = 0; i < vcpu->arch.pio.count; i++) {
5211 if (vcpu->arch.pio.in)
5212 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5213 vcpu->arch.pio.size, pd);
5215 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5216 vcpu->arch.pio.port, vcpu->arch.pio.size,
5220 pd += vcpu->arch.pio.size;
5225 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5226 unsigned short port, void *val,
5227 unsigned int count, bool in)
5229 vcpu->arch.pio.port = port;
5230 vcpu->arch.pio.in = in;
5231 vcpu->arch.pio.count = count;
5232 vcpu->arch.pio.size = size;
5234 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5235 vcpu->arch.pio.count = 0;
5239 vcpu->run->exit_reason = KVM_EXIT_IO;
5240 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5241 vcpu->run->io.size = size;
5242 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5243 vcpu->run->io.count = count;
5244 vcpu->run->io.port = port;
5249 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5250 int size, unsigned short port, void *val,
5253 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5256 if (vcpu->arch.pio.count)
5259 memset(vcpu->arch.pio_data, 0, size * count);
5261 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5264 memcpy(val, vcpu->arch.pio_data, size * count);
5265 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5266 vcpu->arch.pio.count = 0;
5273 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5274 int size, unsigned short port,
5275 const void *val, unsigned int count)
5277 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5279 memcpy(vcpu->arch.pio_data, val, size * count);
5280 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5281 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5284 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5286 return kvm_x86_ops->get_segment_base(vcpu, seg);
5289 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5291 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5294 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5296 if (!need_emulate_wbinvd(vcpu))
5297 return X86EMUL_CONTINUE;
5299 if (kvm_x86_ops->has_wbinvd_exit()) {
5300 int cpu = get_cpu();
5302 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5303 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5304 wbinvd_ipi, NULL, 1);
5306 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5309 return X86EMUL_CONTINUE;
5312 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5314 kvm_emulate_wbinvd_noskip(vcpu);
5315 return kvm_skip_emulated_instruction(vcpu);
5317 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5321 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5323 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5326 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5327 unsigned long *dest)
5329 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5332 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5333 unsigned long value)
5336 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5339 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5341 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5344 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5346 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5347 unsigned long value;
5351 value = kvm_read_cr0(vcpu);
5354 value = vcpu->arch.cr2;
5357 value = kvm_read_cr3(vcpu);
5360 value = kvm_read_cr4(vcpu);
5363 value = kvm_get_cr8(vcpu);
5366 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5373 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5375 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5380 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5383 vcpu->arch.cr2 = val;
5386 res = kvm_set_cr3(vcpu, val);
5389 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5392 res = kvm_set_cr8(vcpu, val);
5395 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5402 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5404 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5407 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5409 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5412 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5414 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5417 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5419 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5422 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5424 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5427 static unsigned long emulator_get_cached_segment_base(
5428 struct x86_emulate_ctxt *ctxt, int seg)
5430 return get_segment_base(emul_to_vcpu(ctxt), seg);
5433 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5434 struct desc_struct *desc, u32 *base3,
5437 struct kvm_segment var;
5439 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5440 *selector = var.selector;
5443 memset(desc, 0, sizeof(*desc));
5451 set_desc_limit(desc, var.limit);
5452 set_desc_base(desc, (unsigned long)var.base);
5453 #ifdef CONFIG_X86_64
5455 *base3 = var.base >> 32;
5457 desc->type = var.type;
5459 desc->dpl = var.dpl;
5460 desc->p = var.present;
5461 desc->avl = var.avl;
5469 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5470 struct desc_struct *desc, u32 base3,
5473 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5474 struct kvm_segment var;
5476 var.selector = selector;
5477 var.base = get_desc_base(desc);
5478 #ifdef CONFIG_X86_64
5479 var.base |= ((u64)base3) << 32;
5481 var.limit = get_desc_limit(desc);
5483 var.limit = (var.limit << 12) | 0xfff;
5484 var.type = desc->type;
5485 var.dpl = desc->dpl;
5490 var.avl = desc->avl;
5491 var.present = desc->p;
5492 var.unusable = !var.present;
5495 kvm_set_segment(vcpu, &var, seg);
5499 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5500 u32 msr_index, u64 *pdata)
5502 struct msr_data msr;
5505 msr.index = msr_index;
5506 msr.host_initiated = false;
5507 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5515 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5516 u32 msr_index, u64 data)
5518 struct msr_data msr;
5521 msr.index = msr_index;
5522 msr.host_initiated = false;
5523 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5526 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5528 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5530 return vcpu->arch.smbase;
5533 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5535 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5537 vcpu->arch.smbase = smbase;
5540 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5543 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5546 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5547 u32 pmc, u64 *pdata)
5549 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5552 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5554 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5557 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5558 struct x86_instruction_info *info,
5559 enum x86_intercept_stage stage)
5561 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5564 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5565 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5567 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5570 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5572 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5575 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5577 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5580 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5582 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5585 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5587 return emul_to_vcpu(ctxt)->arch.hflags;
5590 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5592 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5595 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5597 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5600 static const struct x86_emulate_ops emulate_ops = {
5601 .read_gpr = emulator_read_gpr,
5602 .write_gpr = emulator_write_gpr,
5603 .read_std = kvm_read_guest_virt_system,
5604 .write_std = kvm_write_guest_virt_system,
5605 .read_phys = kvm_read_guest_phys_system,
5606 .fetch = kvm_fetch_guest_virt,
5607 .read_emulated = emulator_read_emulated,
5608 .write_emulated = emulator_write_emulated,
5609 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5610 .invlpg = emulator_invlpg,
5611 .pio_in_emulated = emulator_pio_in_emulated,
5612 .pio_out_emulated = emulator_pio_out_emulated,
5613 .get_segment = emulator_get_segment,
5614 .set_segment = emulator_set_segment,
5615 .get_cached_segment_base = emulator_get_cached_segment_base,
5616 .get_gdt = emulator_get_gdt,
5617 .get_idt = emulator_get_idt,
5618 .set_gdt = emulator_set_gdt,
5619 .set_idt = emulator_set_idt,
5620 .get_cr = emulator_get_cr,
5621 .set_cr = emulator_set_cr,
5622 .cpl = emulator_get_cpl,
5623 .get_dr = emulator_get_dr,
5624 .set_dr = emulator_set_dr,
5625 .get_smbase = emulator_get_smbase,
5626 .set_smbase = emulator_set_smbase,
5627 .set_msr = emulator_set_msr,
5628 .get_msr = emulator_get_msr,
5629 .check_pmc = emulator_check_pmc,
5630 .read_pmc = emulator_read_pmc,
5631 .halt = emulator_halt,
5632 .wbinvd = emulator_wbinvd,
5633 .fix_hypercall = emulator_fix_hypercall,
5634 .intercept = emulator_intercept,
5635 .get_cpuid = emulator_get_cpuid,
5636 .set_nmi_mask = emulator_set_nmi_mask,
5637 .get_hflags = emulator_get_hflags,
5638 .set_hflags = emulator_set_hflags,
5639 .pre_leave_smm = emulator_pre_leave_smm,
5642 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5644 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5646 * an sti; sti; sequence only disable interrupts for the first
5647 * instruction. So, if the last instruction, be it emulated or
5648 * not, left the system with the INT_STI flag enabled, it
5649 * means that the last instruction is an sti. We should not
5650 * leave the flag on in this case. The same goes for mov ss
5652 if (int_shadow & mask)
5654 if (unlikely(int_shadow || mask)) {
5655 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5657 kvm_make_request(KVM_REQ_EVENT, vcpu);
5661 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5663 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5664 if (ctxt->exception.vector == PF_VECTOR)
5665 return kvm_propagate_fault(vcpu, &ctxt->exception);
5667 if (ctxt->exception.error_code_valid)
5668 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5669 ctxt->exception.error_code);
5671 kvm_queue_exception(vcpu, ctxt->exception.vector);
5675 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5677 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5680 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5682 ctxt->eflags = kvm_get_rflags(vcpu);
5683 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5685 ctxt->eip = kvm_rip_read(vcpu);
5686 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5687 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5688 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5689 cs_db ? X86EMUL_MODE_PROT32 :
5690 X86EMUL_MODE_PROT16;
5691 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5692 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5693 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5695 init_decode_cache(ctxt);
5696 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5699 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5701 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5704 init_emulate_ctxt(vcpu);
5708 ctxt->_eip = ctxt->eip + inc_eip;
5709 ret = emulate_int_real(ctxt, irq);
5711 if (ret != X86EMUL_CONTINUE)
5712 return EMULATE_FAIL;
5714 ctxt->eip = ctxt->_eip;
5715 kvm_rip_write(vcpu, ctxt->eip);
5716 kvm_set_rflags(vcpu, ctxt->eflags);
5718 return EMULATE_DONE;
5720 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5722 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
5724 int r = EMULATE_DONE;
5726 ++vcpu->stat.insn_emulation_fail;
5727 trace_kvm_emulate_insn_failed(vcpu);
5729 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5730 return EMULATE_FAIL;
5732 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5733 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5734 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5735 vcpu->run->internal.ndata = 0;
5736 r = EMULATE_USER_EXIT;
5739 kvm_queue_exception(vcpu, UD_VECTOR);
5744 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5745 bool write_fault_to_shadow_pgtable,
5751 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5754 if (!vcpu->arch.mmu.direct_map) {
5756 * Write permission should be allowed since only
5757 * write access need to be emulated.
5759 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5762 * If the mapping is invalid in guest, let cpu retry
5763 * it to generate fault.
5765 if (gpa == UNMAPPED_GVA)
5770 * Do not retry the unhandleable instruction if it faults on the
5771 * readonly host memory, otherwise it will goto a infinite loop:
5772 * retry instruction -> write #PF -> emulation fail -> retry
5773 * instruction -> ...
5775 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5778 * If the instruction failed on the error pfn, it can not be fixed,
5779 * report the error to userspace.
5781 if (is_error_noslot_pfn(pfn))
5784 kvm_release_pfn_clean(pfn);
5786 /* The instructions are well-emulated on direct mmu. */
5787 if (vcpu->arch.mmu.direct_map) {
5788 unsigned int indirect_shadow_pages;
5790 spin_lock(&vcpu->kvm->mmu_lock);
5791 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5792 spin_unlock(&vcpu->kvm->mmu_lock);
5794 if (indirect_shadow_pages)
5795 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5801 * if emulation was due to access to shadowed page table
5802 * and it failed try to unshadow page and re-enter the
5803 * guest to let CPU execute the instruction.
5805 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5808 * If the access faults on its page table, it can not
5809 * be fixed by unprotecting shadow page and it should
5810 * be reported to userspace.
5812 return !write_fault_to_shadow_pgtable;
5815 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5816 unsigned long cr2, int emulation_type)
5818 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5819 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5821 last_retry_eip = vcpu->arch.last_retry_eip;
5822 last_retry_addr = vcpu->arch.last_retry_addr;
5825 * If the emulation is caused by #PF and it is non-page_table
5826 * writing instruction, it means the VM-EXIT is caused by shadow
5827 * page protected, we can zap the shadow page and retry this
5828 * instruction directly.
5830 * Note: if the guest uses a non-page-table modifying instruction
5831 * on the PDE that points to the instruction, then we will unmap
5832 * the instruction and go to an infinite loop. So, we cache the
5833 * last retried eip and the last fault address, if we meet the eip
5834 * and the address again, we can break out of the potential infinite
5837 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5839 if (!(emulation_type & EMULTYPE_RETRY))
5842 if (x86_page_table_writing_insn(ctxt))
5845 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5848 vcpu->arch.last_retry_eip = ctxt->eip;
5849 vcpu->arch.last_retry_addr = cr2;
5851 if (!vcpu->arch.mmu.direct_map)
5852 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5854 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5859 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5860 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5862 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5864 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5865 /* This is a good place to trace that we are exiting SMM. */
5866 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5868 /* Process a latched INIT or SMI, if any. */
5869 kvm_make_request(KVM_REQ_EVENT, vcpu);
5872 kvm_mmu_reset_context(vcpu);
5875 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5877 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5879 vcpu->arch.hflags = emul_flags;
5881 if (changed & HF_SMM_MASK)
5882 kvm_smm_changed(vcpu);
5885 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5894 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5895 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5900 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
5902 struct kvm_run *kvm_run = vcpu->run;
5904 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5905 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5906 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5907 kvm_run->debug.arch.exception = DB_VECTOR;
5908 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5909 *r = EMULATE_USER_EXIT;
5912 * "Certain debug exceptions may clear bit 0-3. The
5913 * remaining contents of the DR6 register are never
5914 * cleared by the processor".
5916 vcpu->arch.dr6 &= ~15;
5917 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5918 kvm_queue_exception(vcpu, DB_VECTOR);
5922 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5924 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5925 int r = EMULATE_DONE;
5927 kvm_x86_ops->skip_emulated_instruction(vcpu);
5930 * rflags is the old, "raw" value of the flags. The new value has
5931 * not been saved yet.
5933 * This is correct even for TF set by the guest, because "the
5934 * processor will not generate this exception after the instruction
5935 * that sets the TF flag".
5937 if (unlikely(rflags & X86_EFLAGS_TF))
5938 kvm_vcpu_do_singlestep(vcpu, &r);
5939 return r == EMULATE_DONE;
5941 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5943 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5945 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5946 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5947 struct kvm_run *kvm_run = vcpu->run;
5948 unsigned long eip = kvm_get_linear_rip(vcpu);
5949 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5950 vcpu->arch.guest_debug_dr7,
5954 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5955 kvm_run->debug.arch.pc = eip;
5956 kvm_run->debug.arch.exception = DB_VECTOR;
5957 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5958 *r = EMULATE_USER_EXIT;
5963 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5964 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5965 unsigned long eip = kvm_get_linear_rip(vcpu);
5966 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5971 vcpu->arch.dr6 &= ~15;
5972 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5973 kvm_queue_exception(vcpu, DB_VECTOR);
5982 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
5984 switch (ctxt->opcode_len) {
5991 case 0xe6: /* OUT */
5995 case 0x6c: /* INS */
5997 case 0x6e: /* OUTS */
6004 case 0x33: /* RDPMC */
6013 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6020 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6021 bool writeback = true;
6022 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6025 * Clear write_fault_to_shadow_pgtable here to ensure it is
6028 vcpu->arch.write_fault_to_shadow_pgtable = false;
6029 kvm_clear_exception_queue(vcpu);
6031 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6032 init_emulate_ctxt(vcpu);
6035 * We will reenter on the same instruction since
6036 * we do not set complete_userspace_io. This does not
6037 * handle watchpoints yet, those would be handled in
6040 if (!(emulation_type & EMULTYPE_SKIP) &&
6041 kvm_vcpu_check_breakpoint(vcpu, &r))
6044 ctxt->interruptibility = 0;
6045 ctxt->have_exception = false;
6046 ctxt->exception.vector = -1;
6047 ctxt->perm_ok = false;
6049 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6051 r = x86_decode_insn(ctxt, insn, insn_len);
6053 trace_kvm_emulate_insn_start(vcpu);
6054 ++vcpu->stat.insn_emulation;
6055 if (r != EMULATION_OK) {
6056 if (emulation_type & EMULTYPE_TRAP_UD)
6057 return EMULATE_FAIL;
6058 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6060 return EMULATE_DONE;
6061 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6062 return EMULATE_DONE;
6063 if (emulation_type & EMULTYPE_SKIP)
6064 return EMULATE_FAIL;
6065 return handle_emulation_failure(vcpu, emulation_type);
6069 if ((emulation_type & EMULTYPE_VMWARE) &&
6070 !is_vmware_backdoor_opcode(ctxt))
6071 return EMULATE_FAIL;
6073 if (emulation_type & EMULTYPE_SKIP) {
6074 kvm_rip_write(vcpu, ctxt->_eip);
6075 if (ctxt->eflags & X86_EFLAGS_RF)
6076 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6077 return EMULATE_DONE;
6080 if (retry_instruction(ctxt, cr2, emulation_type))
6081 return EMULATE_DONE;
6083 /* this is needed for vmware backdoor interface to work since it
6084 changes registers values during IO operation */
6085 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6086 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6087 emulator_invalidate_register_cache(ctxt);
6091 /* Save the faulting GPA (cr2) in the address field */
6092 ctxt->exception.address = cr2;
6094 r = x86_emulate_insn(ctxt);
6096 if (r == EMULATION_INTERCEPTED)
6097 return EMULATE_DONE;
6099 if (r == EMULATION_FAILED) {
6100 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6102 return EMULATE_DONE;
6104 return handle_emulation_failure(vcpu, emulation_type);
6107 if (ctxt->have_exception) {
6109 if (inject_emulated_exception(vcpu))
6111 } else if (vcpu->arch.pio.count) {
6112 if (!vcpu->arch.pio.in) {
6113 /* FIXME: return into emulator if single-stepping. */
6114 vcpu->arch.pio.count = 0;
6117 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6119 r = EMULATE_USER_EXIT;
6120 } else if (vcpu->mmio_needed) {
6121 if (!vcpu->mmio_is_write)
6123 r = EMULATE_USER_EXIT;
6124 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6125 } else if (r == EMULATION_RESTART)
6131 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6132 toggle_interruptibility(vcpu, ctxt->interruptibility);
6133 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6134 kvm_rip_write(vcpu, ctxt->eip);
6135 if (r == EMULATE_DONE &&
6136 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6137 kvm_vcpu_do_singlestep(vcpu, &r);
6138 if (!ctxt->have_exception ||
6139 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6140 __kvm_set_rflags(vcpu, ctxt->eflags);
6143 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6144 * do nothing, and it will be requested again as soon as
6145 * the shadow expires. But we still need to check here,
6146 * because POPF has no interrupt shadow.
6148 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6149 kvm_make_request(KVM_REQ_EVENT, vcpu);
6151 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6155 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
6157 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6158 unsigned short port)
6160 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
6161 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6162 size, port, &val, 1);
6163 /* do not return to emulator after return from userspace */
6164 vcpu->arch.pio.count = 0;
6168 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6172 /* We should only ever be called with arch.pio.count equal to 1 */
6173 BUG_ON(vcpu->arch.pio.count != 1);
6175 /* For size less than 4 we merge, else we zero extend */
6176 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6180 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6181 * the copy and tracing
6183 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6184 vcpu->arch.pio.port, &val, 1);
6185 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6190 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6191 unsigned short port)
6196 /* For size less than 4 we merge, else we zero extend */
6197 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6199 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6202 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6206 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6211 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6213 int ret = kvm_skip_emulated_instruction(vcpu);
6216 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6217 * KVM_EXIT_DEBUG here.
6220 return kvm_fast_pio_in(vcpu, size, port) && ret;
6222 return kvm_fast_pio_out(vcpu, size, port) && ret;
6224 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6226 static int kvmclock_cpu_down_prep(unsigned int cpu)
6228 __this_cpu_write(cpu_tsc_khz, 0);
6232 static void tsc_khz_changed(void *data)
6234 struct cpufreq_freqs *freq = data;
6235 unsigned long khz = 0;
6239 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6240 khz = cpufreq_quick_get(raw_smp_processor_id());
6243 __this_cpu_write(cpu_tsc_khz, khz);
6246 #ifdef CONFIG_X86_64
6247 static void kvm_hyperv_tsc_notifier(void)
6250 struct kvm_vcpu *vcpu;
6253 spin_lock(&kvm_lock);
6254 list_for_each_entry(kvm, &vm_list, vm_list)
6255 kvm_make_mclock_inprogress_request(kvm);
6257 hyperv_stop_tsc_emulation();
6259 /* TSC frequency always matches when on Hyper-V */
6260 for_each_present_cpu(cpu)
6261 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6262 kvm_max_guest_tsc_khz = tsc_khz;
6264 list_for_each_entry(kvm, &vm_list, vm_list) {
6265 struct kvm_arch *ka = &kvm->arch;
6267 spin_lock(&ka->pvclock_gtod_sync_lock);
6269 pvclock_update_vm_gtod_copy(kvm);
6271 kvm_for_each_vcpu(cpu, vcpu, kvm)
6272 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6274 kvm_for_each_vcpu(cpu, vcpu, kvm)
6275 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6277 spin_unlock(&ka->pvclock_gtod_sync_lock);
6279 spin_unlock(&kvm_lock);
6283 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6286 struct cpufreq_freqs *freq = data;
6288 struct kvm_vcpu *vcpu;
6289 int i, send_ipi = 0;
6292 * We allow guests to temporarily run on slowing clocks,
6293 * provided we notify them after, or to run on accelerating
6294 * clocks, provided we notify them before. Thus time never
6297 * However, we have a problem. We can't atomically update
6298 * the frequency of a given CPU from this function; it is
6299 * merely a notifier, which can be called from any CPU.
6300 * Changing the TSC frequency at arbitrary points in time
6301 * requires a recomputation of local variables related to
6302 * the TSC for each VCPU. We must flag these local variables
6303 * to be updated and be sure the update takes place with the
6304 * new frequency before any guests proceed.
6306 * Unfortunately, the combination of hotplug CPU and frequency
6307 * change creates an intractable locking scenario; the order
6308 * of when these callouts happen is undefined with respect to
6309 * CPU hotplug, and they can race with each other. As such,
6310 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6311 * undefined; you can actually have a CPU frequency change take
6312 * place in between the computation of X and the setting of the
6313 * variable. To protect against this problem, all updates of
6314 * the per_cpu tsc_khz variable are done in an interrupt
6315 * protected IPI, and all callers wishing to update the value
6316 * must wait for a synchronous IPI to complete (which is trivial
6317 * if the caller is on the CPU already). This establishes the
6318 * necessary total order on variable updates.
6320 * Note that because a guest time update may take place
6321 * anytime after the setting of the VCPU's request bit, the
6322 * correct TSC value must be set before the request. However,
6323 * to ensure the update actually makes it to any guest which
6324 * starts running in hardware virtualization between the set
6325 * and the acquisition of the spinlock, we must also ping the
6326 * CPU after setting the request bit.
6330 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6332 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6335 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6337 spin_lock(&kvm_lock);
6338 list_for_each_entry(kvm, &vm_list, vm_list) {
6339 kvm_for_each_vcpu(i, vcpu, kvm) {
6340 if (vcpu->cpu != freq->cpu)
6342 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6343 if (vcpu->cpu != smp_processor_id())
6347 spin_unlock(&kvm_lock);
6349 if (freq->old < freq->new && send_ipi) {
6351 * We upscale the frequency. Must make the guest
6352 * doesn't see old kvmclock values while running with
6353 * the new frequency, otherwise we risk the guest sees
6354 * time go backwards.
6356 * In case we update the frequency for another cpu
6357 * (which might be in guest context) send an interrupt
6358 * to kick the cpu out of guest context. Next time
6359 * guest context is entered kvmclock will be updated,
6360 * so the guest will not see stale values.
6362 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6367 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6368 .notifier_call = kvmclock_cpufreq_notifier
6371 static int kvmclock_cpu_online(unsigned int cpu)
6373 tsc_khz_changed(NULL);
6377 static void kvm_timer_init(void)
6379 max_tsc_khz = tsc_khz;
6381 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6382 #ifdef CONFIG_CPU_FREQ
6383 struct cpufreq_policy policy;
6386 memset(&policy, 0, sizeof(policy));
6388 cpufreq_get_policy(&policy, cpu);
6389 if (policy.cpuinfo.max_freq)
6390 max_tsc_khz = policy.cpuinfo.max_freq;
6393 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6394 CPUFREQ_TRANSITION_NOTIFIER);
6396 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6398 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6399 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6402 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6403 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
6405 int kvm_is_in_guest(void)
6407 return __this_cpu_read(current_vcpu) != NULL;
6410 static int kvm_is_user_mode(void)
6414 if (__this_cpu_read(current_vcpu))
6415 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6417 return user_mode != 0;
6420 static unsigned long kvm_get_guest_ip(void)
6422 unsigned long ip = 0;
6424 if (__this_cpu_read(current_vcpu))
6425 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6430 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6431 .is_in_guest = kvm_is_in_guest,
6432 .is_user_mode = kvm_is_user_mode,
6433 .get_guest_ip = kvm_get_guest_ip,
6436 static void kvm_set_mmio_spte_mask(void)
6439 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6442 * Set the reserved bits and the present bit of an paging-structure
6443 * entry to generate page fault with PFER.RSV = 1.
6445 /* Mask the reserved physical address bits. */
6446 mask = rsvd_bits(maxphyaddr, 51);
6448 /* Set the present bit. */
6451 #ifdef CONFIG_X86_64
6453 * If reserved bit is not supported, clear the present bit to disable
6456 if (maxphyaddr == 52)
6460 kvm_mmu_set_mmio_spte_mask(mask, mask);
6463 #ifdef CONFIG_X86_64
6464 static void pvclock_gtod_update_fn(struct work_struct *work)
6468 struct kvm_vcpu *vcpu;
6471 spin_lock(&kvm_lock);
6472 list_for_each_entry(kvm, &vm_list, vm_list)
6473 kvm_for_each_vcpu(i, vcpu, kvm)
6474 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6475 atomic_set(&kvm_guest_has_master_clock, 0);
6476 spin_unlock(&kvm_lock);
6479 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6482 * Notification about pvclock gtod data update.
6484 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6487 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6488 struct timekeeper *tk = priv;
6490 update_pvclock_gtod(tk);
6492 /* disable master clock if host does not trust, or does not
6493 * use, TSC based clocksource.
6495 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
6496 atomic_read(&kvm_guest_has_master_clock) != 0)
6497 queue_work(system_long_wq, &pvclock_gtod_work);
6502 static struct notifier_block pvclock_gtod_notifier = {
6503 .notifier_call = pvclock_gtod_notify,
6507 int kvm_arch_init(void *opaque)
6510 struct kvm_x86_ops *ops = opaque;
6513 printk(KERN_ERR "kvm: already loaded the other module\n");
6518 if (!ops->cpu_has_kvm_support()) {
6519 printk(KERN_ERR "kvm: no hardware support\n");
6523 if (ops->disabled_by_bios()) {
6524 printk(KERN_ERR "kvm: disabled by bios\n");
6530 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6532 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6536 r = kvm_mmu_module_init();
6538 goto out_free_percpu;
6540 kvm_set_mmio_spte_mask();
6544 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6545 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6546 PT_PRESENT_MASK, 0, sme_me_mask);
6549 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6551 if (boot_cpu_has(X86_FEATURE_XSAVE))
6552 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6555 #ifdef CONFIG_X86_64
6556 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6558 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
6559 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
6565 free_percpu(shared_msrs);
6570 void kvm_arch_exit(void)
6572 #ifdef CONFIG_X86_64
6573 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
6574 clear_hv_tscchange_cb();
6577 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6579 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6580 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6581 CPUFREQ_TRANSITION_NOTIFIER);
6582 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6583 #ifdef CONFIG_X86_64
6584 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6587 kvm_mmu_module_exit();
6588 free_percpu(shared_msrs);
6591 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6593 ++vcpu->stat.halt_exits;
6594 if (lapic_in_kernel(vcpu)) {
6595 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6598 vcpu->run->exit_reason = KVM_EXIT_HLT;
6602 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6604 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6606 int ret = kvm_skip_emulated_instruction(vcpu);
6608 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6609 * KVM_EXIT_DEBUG here.
6611 return kvm_vcpu_halt(vcpu) && ret;
6613 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6615 #ifdef CONFIG_X86_64
6616 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6617 unsigned long clock_type)
6619 struct kvm_clock_pairing clock_pairing;
6624 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6625 return -KVM_EOPNOTSUPP;
6627 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6628 return -KVM_EOPNOTSUPP;
6630 clock_pairing.sec = ts.tv_sec;
6631 clock_pairing.nsec = ts.tv_nsec;
6632 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6633 clock_pairing.flags = 0;
6636 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6637 sizeof(struct kvm_clock_pairing)))
6645 * kvm_pv_kick_cpu_op: Kick a vcpu.
6647 * @apicid - apicid of vcpu to be kicked.
6649 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6651 struct kvm_lapic_irq lapic_irq;
6653 lapic_irq.shorthand = 0;
6654 lapic_irq.dest_mode = 0;
6655 lapic_irq.level = 0;
6656 lapic_irq.dest_id = apicid;
6657 lapic_irq.msi_redir_hint = false;
6659 lapic_irq.delivery_mode = APIC_DM_REMRD;
6660 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6663 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6665 vcpu->arch.apicv_active = false;
6666 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6669 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6671 unsigned long nr, a0, a1, a2, a3, ret;
6674 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6675 return kvm_hv_hypercall(vcpu);
6677 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6678 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6679 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6680 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6681 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6683 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6685 op_64_bit = is_64_bit_mode(vcpu);
6694 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6700 case KVM_HC_VAPIC_POLL_IRQ:
6703 case KVM_HC_KICK_CPU:
6704 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6707 #ifdef CONFIG_X86_64
6708 case KVM_HC_CLOCK_PAIRING:
6709 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6719 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6721 ++vcpu->stat.hypercalls;
6722 return kvm_skip_emulated_instruction(vcpu);
6724 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6726 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6728 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6729 char instruction[3];
6730 unsigned long rip = kvm_rip_read(vcpu);
6732 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6734 return emulator_write_emulated(ctxt, rip, instruction, 3,
6738 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6740 return vcpu->run->request_interrupt_window &&
6741 likely(!pic_in_kernel(vcpu->kvm));
6744 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6746 struct kvm_run *kvm_run = vcpu->run;
6748 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6749 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6750 kvm_run->cr8 = kvm_get_cr8(vcpu);
6751 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6752 kvm_run->ready_for_interrupt_injection =
6753 pic_in_kernel(vcpu->kvm) ||
6754 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6757 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6761 if (!kvm_x86_ops->update_cr8_intercept)
6764 if (!lapic_in_kernel(vcpu))
6767 if (vcpu->arch.apicv_active)
6770 if (!vcpu->arch.apic->vapic_addr)
6771 max_irr = kvm_lapic_find_highest_irr(vcpu);
6778 tpr = kvm_lapic_get_cr8(vcpu);
6780 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6783 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6787 /* try to reinject previous events if any */
6789 if (vcpu->arch.exception.injected)
6790 kvm_x86_ops->queue_exception(vcpu);
6792 * Do not inject an NMI or interrupt if there is a pending
6793 * exception. Exceptions and interrupts are recognized at
6794 * instruction boundaries, i.e. the start of an instruction.
6795 * Trap-like exceptions, e.g. #DB, have higher priority than
6796 * NMIs and interrupts, i.e. traps are recognized before an
6797 * NMI/interrupt that's pending on the same instruction.
6798 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6799 * priority, but are only generated (pended) during instruction
6800 * execution, i.e. a pending fault-like exception means the
6801 * fault occurred on the *previous* instruction and must be
6802 * serviced prior to recognizing any new events in order to
6803 * fully complete the previous instruction.
6805 else if (!vcpu->arch.exception.pending) {
6806 if (vcpu->arch.nmi_injected)
6807 kvm_x86_ops->set_nmi(vcpu);
6808 else if (vcpu->arch.interrupt.injected)
6809 kvm_x86_ops->set_irq(vcpu);
6813 * Call check_nested_events() even if we reinjected a previous event
6814 * in order for caller to determine if it should require immediate-exit
6815 * from L2 to L1 due to pending L1 events which require exit
6818 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6819 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6824 /* try to inject new event if pending */
6825 if (vcpu->arch.exception.pending) {
6826 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6827 vcpu->arch.exception.has_error_code,
6828 vcpu->arch.exception.error_code);
6830 WARN_ON_ONCE(vcpu->arch.exception.injected);
6831 vcpu->arch.exception.pending = false;
6832 vcpu->arch.exception.injected = true;
6834 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6835 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6838 if (vcpu->arch.exception.nr == DB_VECTOR &&
6839 (vcpu->arch.dr7 & DR7_GD)) {
6840 vcpu->arch.dr7 &= ~DR7_GD;
6841 kvm_update_dr7(vcpu);
6844 kvm_x86_ops->queue_exception(vcpu);
6847 /* Don't consider new event if we re-injected an event */
6848 if (kvm_event_needs_reinjection(vcpu))
6851 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
6852 kvm_x86_ops->smi_allowed(vcpu)) {
6853 vcpu->arch.smi_pending = false;
6854 ++vcpu->arch.smi_count;
6856 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6857 --vcpu->arch.nmi_pending;
6858 vcpu->arch.nmi_injected = true;
6859 kvm_x86_ops->set_nmi(vcpu);
6860 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6862 * Because interrupts can be injected asynchronously, we are
6863 * calling check_nested_events again here to avoid a race condition.
6864 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6865 * proposal and current concerns. Perhaps we should be setting
6866 * KVM_REQ_EVENT only on certain events and not unconditionally?
6868 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6869 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6873 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6874 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6876 kvm_x86_ops->set_irq(vcpu);
6883 static void process_nmi(struct kvm_vcpu *vcpu)
6888 * x86 is limited to one NMI running, and one NMI pending after it.
6889 * If an NMI is already in progress, limit further NMIs to just one.
6890 * Otherwise, allow two (and we'll inject the first one immediately).
6892 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6895 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6896 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6897 kvm_make_request(KVM_REQ_EVENT, vcpu);
6900 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6903 flags |= seg->g << 23;
6904 flags |= seg->db << 22;
6905 flags |= seg->l << 21;
6906 flags |= seg->avl << 20;
6907 flags |= seg->present << 15;
6908 flags |= seg->dpl << 13;
6909 flags |= seg->s << 12;
6910 flags |= seg->type << 8;
6914 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6916 struct kvm_segment seg;
6919 kvm_get_segment(vcpu, &seg, n);
6920 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6923 offset = 0x7f84 + n * 12;
6925 offset = 0x7f2c + (n - 3) * 12;
6927 put_smstate(u32, buf, offset + 8, seg.base);
6928 put_smstate(u32, buf, offset + 4, seg.limit);
6929 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6932 #ifdef CONFIG_X86_64
6933 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6935 struct kvm_segment seg;
6939 kvm_get_segment(vcpu, &seg, n);
6940 offset = 0x7e00 + n * 16;
6942 flags = enter_smm_get_segment_flags(&seg) >> 8;
6943 put_smstate(u16, buf, offset, seg.selector);
6944 put_smstate(u16, buf, offset + 2, flags);
6945 put_smstate(u32, buf, offset + 4, seg.limit);
6946 put_smstate(u64, buf, offset + 8, seg.base);
6950 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6953 struct kvm_segment seg;
6957 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6958 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6959 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6960 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6962 for (i = 0; i < 8; i++)
6963 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6965 kvm_get_dr(vcpu, 6, &val);
6966 put_smstate(u32, buf, 0x7fcc, (u32)val);
6967 kvm_get_dr(vcpu, 7, &val);
6968 put_smstate(u32, buf, 0x7fc8, (u32)val);
6970 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6971 put_smstate(u32, buf, 0x7fc4, seg.selector);
6972 put_smstate(u32, buf, 0x7f64, seg.base);
6973 put_smstate(u32, buf, 0x7f60, seg.limit);
6974 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6976 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6977 put_smstate(u32, buf, 0x7fc0, seg.selector);
6978 put_smstate(u32, buf, 0x7f80, seg.base);
6979 put_smstate(u32, buf, 0x7f7c, seg.limit);
6980 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6982 kvm_x86_ops->get_gdt(vcpu, &dt);
6983 put_smstate(u32, buf, 0x7f74, dt.address);
6984 put_smstate(u32, buf, 0x7f70, dt.size);
6986 kvm_x86_ops->get_idt(vcpu, &dt);
6987 put_smstate(u32, buf, 0x7f58, dt.address);
6988 put_smstate(u32, buf, 0x7f54, dt.size);
6990 for (i = 0; i < 6; i++)
6991 enter_smm_save_seg_32(vcpu, buf, i);
6993 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6996 put_smstate(u32, buf, 0x7efc, 0x00020000);
6997 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7000 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7002 #ifdef CONFIG_X86_64
7004 struct kvm_segment seg;
7008 for (i = 0; i < 16; i++)
7009 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7011 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7012 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7014 kvm_get_dr(vcpu, 6, &val);
7015 put_smstate(u64, buf, 0x7f68, val);
7016 kvm_get_dr(vcpu, 7, &val);
7017 put_smstate(u64, buf, 0x7f60, val);
7019 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7020 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7021 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7023 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7026 put_smstate(u32, buf, 0x7efc, 0x00020064);
7028 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7030 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7031 put_smstate(u16, buf, 0x7e90, seg.selector);
7032 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7033 put_smstate(u32, buf, 0x7e94, seg.limit);
7034 put_smstate(u64, buf, 0x7e98, seg.base);
7036 kvm_x86_ops->get_idt(vcpu, &dt);
7037 put_smstate(u32, buf, 0x7e84, dt.size);
7038 put_smstate(u64, buf, 0x7e88, dt.address);
7040 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7041 put_smstate(u16, buf, 0x7e70, seg.selector);
7042 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7043 put_smstate(u32, buf, 0x7e74, seg.limit);
7044 put_smstate(u64, buf, 0x7e78, seg.base);
7046 kvm_x86_ops->get_gdt(vcpu, &dt);
7047 put_smstate(u32, buf, 0x7e64, dt.size);
7048 put_smstate(u64, buf, 0x7e68, dt.address);
7050 for (i = 0; i < 6; i++)
7051 enter_smm_save_seg_64(vcpu, buf, i);
7057 static void enter_smm(struct kvm_vcpu *vcpu)
7059 struct kvm_segment cs, ds;
7064 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7065 memset(buf, 0, 512);
7066 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7067 enter_smm_save_state_64(vcpu, buf);
7069 enter_smm_save_state_32(vcpu, buf);
7072 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7073 * vCPU state (e.g. leave guest mode) after we've saved the state into
7074 * the SMM state-save area.
7076 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7078 vcpu->arch.hflags |= HF_SMM_MASK;
7079 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7081 if (kvm_x86_ops->get_nmi_mask(vcpu))
7082 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7084 kvm_x86_ops->set_nmi_mask(vcpu, true);
7086 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7087 kvm_rip_write(vcpu, 0x8000);
7089 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7090 kvm_x86_ops->set_cr0(vcpu, cr0);
7091 vcpu->arch.cr0 = cr0;
7093 kvm_x86_ops->set_cr4(vcpu, 0);
7095 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7096 dt.address = dt.size = 0;
7097 kvm_x86_ops->set_idt(vcpu, &dt);
7099 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7101 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7102 cs.base = vcpu->arch.smbase;
7107 cs.limit = ds.limit = 0xffffffff;
7108 cs.type = ds.type = 0x3;
7109 cs.dpl = ds.dpl = 0;
7114 cs.avl = ds.avl = 0;
7115 cs.present = ds.present = 1;
7116 cs.unusable = ds.unusable = 0;
7117 cs.padding = ds.padding = 0;
7119 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7120 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7121 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7122 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7123 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7124 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7126 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7127 kvm_x86_ops->set_efer(vcpu, 0);
7129 kvm_update_cpuid(vcpu);
7130 kvm_mmu_reset_context(vcpu);
7133 static void process_smi(struct kvm_vcpu *vcpu)
7135 vcpu->arch.smi_pending = true;
7136 kvm_make_request(KVM_REQ_EVENT, vcpu);
7139 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7141 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7144 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7146 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7149 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7151 if (irqchip_split(vcpu->kvm))
7152 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7154 if (vcpu->arch.apicv_active)
7155 kvm_x86_ops->sync_pir_to_irr(vcpu);
7156 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7159 if (is_guest_mode(vcpu))
7160 vcpu->arch.load_eoi_exitmap_pending = true;
7162 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7165 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7167 u64 eoi_exit_bitmap[4];
7169 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7172 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7173 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7174 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7177 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7178 unsigned long start, unsigned long end)
7180 unsigned long apic_address;
7183 * The physical address of apic access page is stored in the VMCS.
7184 * Update it when it becomes invalid.
7186 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7187 if (start <= apic_address && apic_address < end)
7188 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7191 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7193 struct page *page = NULL;
7195 if (!lapic_in_kernel(vcpu))
7198 if (!kvm_x86_ops->set_apic_access_page_addr)
7201 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7202 if (is_error_page(page))
7204 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7207 * Do not pin apic access page in memory, the MMU notifier
7208 * will call us again if it is migrated or swapped out.
7212 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7215 * Returns 1 to let vcpu_run() continue the guest execution loop without
7216 * exiting to the userspace. Otherwise, the value will be returned to the
7219 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7223 dm_request_for_irq_injection(vcpu) &&
7224 kvm_cpu_accept_dm_intr(vcpu);
7226 bool req_immediate_exit = false;
7228 if (kvm_request_pending(vcpu)) {
7229 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7230 kvm_mmu_unload(vcpu);
7231 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7232 __kvm_migrate_timers(vcpu);
7233 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7234 kvm_gen_update_masterclock(vcpu->kvm);
7235 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7236 kvm_gen_kvmclock_update(vcpu);
7237 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7238 r = kvm_guest_time_update(vcpu);
7242 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7243 kvm_mmu_sync_roots(vcpu);
7244 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7245 kvm_vcpu_flush_tlb(vcpu, true);
7246 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7247 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7251 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7252 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7253 vcpu->mmio_needed = 0;
7257 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7258 /* Page is swapped out. Do synthetic halt */
7259 vcpu->arch.apf.halted = true;
7263 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7264 record_steal_time(vcpu);
7265 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7267 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7269 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7270 kvm_pmu_handle_event(vcpu);
7271 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7272 kvm_pmu_deliver_pmi(vcpu);
7273 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7274 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7275 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7276 vcpu->arch.ioapic_handled_vectors)) {
7277 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7278 vcpu->run->eoi.vector =
7279 vcpu->arch.pending_ioapic_eoi;
7284 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7285 vcpu_scan_ioapic(vcpu);
7286 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7287 vcpu_load_eoi_exitmap(vcpu);
7288 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7289 kvm_vcpu_reload_apic_access_page(vcpu);
7290 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7291 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7292 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7296 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7297 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7298 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7302 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7303 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7304 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7310 * KVM_REQ_HV_STIMER has to be processed after
7311 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7312 * depend on the guest clock being up-to-date
7314 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7315 kvm_hv_process_stimers(vcpu);
7318 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7319 ++vcpu->stat.req_event;
7320 kvm_apic_accept_events(vcpu);
7321 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7326 if (inject_pending_event(vcpu, req_int_win) != 0)
7327 req_immediate_exit = true;
7329 /* Enable SMI/NMI/IRQ window open exits if needed.
7331 * SMIs have three cases:
7332 * 1) They can be nested, and then there is nothing to
7333 * do here because RSM will cause a vmexit anyway.
7334 * 2) There is an ISA-specific reason why SMI cannot be
7335 * injected, and the moment when this changes can be
7337 * 3) Or the SMI can be pending because
7338 * inject_pending_event has completed the injection
7339 * of an IRQ or NMI from the previous vmexit, and
7340 * then we request an immediate exit to inject the
7343 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7344 if (!kvm_x86_ops->enable_smi_window(vcpu))
7345 req_immediate_exit = true;
7346 if (vcpu->arch.nmi_pending)
7347 kvm_x86_ops->enable_nmi_window(vcpu);
7348 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7349 kvm_x86_ops->enable_irq_window(vcpu);
7350 WARN_ON(vcpu->arch.exception.pending);
7353 if (kvm_lapic_enabled(vcpu)) {
7354 update_cr8_intercept(vcpu);
7355 kvm_lapic_sync_to_vapic(vcpu);
7359 r = kvm_mmu_reload(vcpu);
7361 goto cancel_injection;
7366 kvm_x86_ops->prepare_guest_switch(vcpu);
7369 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7370 * IPI are then delayed after guest entry, which ensures that they
7371 * result in virtual interrupt delivery.
7373 local_irq_disable();
7374 vcpu->mode = IN_GUEST_MODE;
7376 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7379 * 1) We should set ->mode before checking ->requests. Please see
7380 * the comment in kvm_vcpu_exiting_guest_mode().
7382 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7383 * pairs with the memory barrier implicit in pi_test_and_set_on
7384 * (see vmx_deliver_posted_interrupt).
7386 * 3) This also orders the write to mode from any reads to the page
7387 * tables done while the VCPU is running. Please see the comment
7388 * in kvm_flush_remote_tlbs.
7390 smp_mb__after_srcu_read_unlock();
7393 * This handles the case where a posted interrupt was
7394 * notified with kvm_vcpu_kick.
7396 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7397 kvm_x86_ops->sync_pir_to_irr(vcpu);
7399 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7400 || need_resched() || signal_pending(current)) {
7401 vcpu->mode = OUTSIDE_GUEST_MODE;
7405 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7407 goto cancel_injection;
7410 kvm_load_guest_xcr0(vcpu);
7412 if (req_immediate_exit) {
7413 kvm_make_request(KVM_REQ_EVENT, vcpu);
7414 smp_send_reschedule(vcpu->cpu);
7417 trace_kvm_entry(vcpu->vcpu_id);
7418 if (lapic_timer_advance_ns)
7419 wait_lapic_expire(vcpu);
7420 guest_enter_irqoff();
7422 if (unlikely(vcpu->arch.switch_db_regs)) {
7424 set_debugreg(vcpu->arch.eff_db[0], 0);
7425 set_debugreg(vcpu->arch.eff_db[1], 1);
7426 set_debugreg(vcpu->arch.eff_db[2], 2);
7427 set_debugreg(vcpu->arch.eff_db[3], 3);
7428 set_debugreg(vcpu->arch.dr6, 6);
7429 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7432 kvm_x86_ops->run(vcpu);
7435 * Do this here before restoring debug registers on the host. And
7436 * since we do this before handling the vmexit, a DR access vmexit
7437 * can (a) read the correct value of the debug registers, (b) set
7438 * KVM_DEBUGREG_WONT_EXIT again.
7440 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
7441 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7442 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
7443 kvm_update_dr0123(vcpu);
7444 kvm_update_dr6(vcpu);
7445 kvm_update_dr7(vcpu);
7446 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7450 * If the guest has used debug registers, at least dr7
7451 * will be disabled while returning to the host.
7452 * If we don't have active breakpoints in the host, we don't
7453 * care about the messed up debug address registers. But if
7454 * we have some of them active, restore the old state.
7456 if (hw_breakpoint_active())
7457 hw_breakpoint_restore();
7459 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
7461 vcpu->mode = OUTSIDE_GUEST_MODE;
7464 kvm_put_guest_xcr0(vcpu);
7466 kvm_before_interrupt(vcpu);
7467 kvm_x86_ops->handle_external_intr(vcpu);
7468 kvm_after_interrupt(vcpu);
7472 guest_exit_irqoff();
7477 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7480 * Profile KVM exit RIPs:
7482 if (unlikely(prof_on == KVM_PROFILING)) {
7483 unsigned long rip = kvm_rip_read(vcpu);
7484 profile_hit(KVM_PROFILING, (void *)rip);
7487 if (unlikely(vcpu->arch.tsc_always_catchup))
7488 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7490 if (vcpu->arch.apic_attention)
7491 kvm_lapic_sync_from_vapic(vcpu);
7493 vcpu->arch.gpa_available = false;
7494 r = kvm_x86_ops->handle_exit(vcpu);
7498 kvm_x86_ops->cancel_injection(vcpu);
7499 if (unlikely(vcpu->arch.apic_attention))
7500 kvm_lapic_sync_from_vapic(vcpu);
7505 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7507 if (!kvm_arch_vcpu_runnable(vcpu) &&
7508 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7509 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7510 kvm_vcpu_block(vcpu);
7511 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7513 if (kvm_x86_ops->post_block)
7514 kvm_x86_ops->post_block(vcpu);
7516 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7520 kvm_apic_accept_events(vcpu);
7521 switch(vcpu->arch.mp_state) {
7522 case KVM_MP_STATE_HALTED:
7523 vcpu->arch.pv.pv_unhalted = false;
7524 vcpu->arch.mp_state =
7525 KVM_MP_STATE_RUNNABLE;
7526 case KVM_MP_STATE_RUNNABLE:
7527 vcpu->arch.apf.halted = false;
7529 case KVM_MP_STATE_INIT_RECEIVED:
7538 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7540 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7541 kvm_x86_ops->check_nested_events(vcpu, false);
7543 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7544 !vcpu->arch.apf.halted);
7547 static int vcpu_run(struct kvm_vcpu *vcpu)
7550 struct kvm *kvm = vcpu->kvm;
7552 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7555 if (kvm_vcpu_running(vcpu)) {
7556 r = vcpu_enter_guest(vcpu);
7558 r = vcpu_block(kvm, vcpu);
7564 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
7565 if (kvm_cpu_has_pending_timer(vcpu))
7566 kvm_inject_pending_timer_irqs(vcpu);
7568 if (dm_request_for_irq_injection(vcpu) &&
7569 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7571 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7572 ++vcpu->stat.request_irq_exits;
7576 kvm_check_async_pf_completion(vcpu);
7578 if (signal_pending(current)) {
7580 vcpu->run->exit_reason = KVM_EXIT_INTR;
7581 ++vcpu->stat.signal_exits;
7584 if (need_resched()) {
7585 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7587 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7591 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7596 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7599 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7600 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7601 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7602 if (r != EMULATE_DONE)
7607 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7609 BUG_ON(!vcpu->arch.pio.count);
7611 return complete_emulated_io(vcpu);
7615 * Implements the following, as a state machine:
7619 * for each mmio piece in the fragment
7627 * for each mmio piece in the fragment
7632 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7634 struct kvm_run *run = vcpu->run;
7635 struct kvm_mmio_fragment *frag;
7638 BUG_ON(!vcpu->mmio_needed);
7640 /* Complete previous fragment */
7641 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7642 len = min(8u, frag->len);
7643 if (!vcpu->mmio_is_write)
7644 memcpy(frag->data, run->mmio.data, len);
7646 if (frag->len <= 8) {
7647 /* Switch to the next fragment. */
7649 vcpu->mmio_cur_fragment++;
7651 /* Go forward to the next mmio piece. */
7657 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7658 vcpu->mmio_needed = 0;
7660 /* FIXME: return into emulator if single-stepping. */
7661 if (vcpu->mmio_is_write)
7663 vcpu->mmio_read_completed = 1;
7664 return complete_emulated_io(vcpu);
7667 run->exit_reason = KVM_EXIT_MMIO;
7668 run->mmio.phys_addr = frag->gpa;
7669 if (vcpu->mmio_is_write)
7670 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7671 run->mmio.len = min(8u, frag->len);
7672 run->mmio.is_write = vcpu->mmio_is_write;
7673 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7677 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7682 kvm_sigset_activate(vcpu);
7683 kvm_load_guest_fpu(vcpu);
7685 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7686 if (kvm_run->immediate_exit) {
7690 kvm_vcpu_block(vcpu);
7691 kvm_apic_accept_events(vcpu);
7692 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
7694 if (signal_pending(current)) {
7696 vcpu->run->exit_reason = KVM_EXIT_INTR;
7697 ++vcpu->stat.signal_exits;
7702 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7707 if (vcpu->run->kvm_dirty_regs) {
7708 r = sync_regs(vcpu);
7713 /* re-sync apic's tpr */
7714 if (!lapic_in_kernel(vcpu)) {
7715 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7721 if (unlikely(vcpu->arch.complete_userspace_io)) {
7722 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7723 vcpu->arch.complete_userspace_io = NULL;
7728 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7730 if (kvm_run->immediate_exit)
7736 kvm_put_guest_fpu(vcpu);
7737 if (vcpu->run->kvm_valid_regs)
7739 post_kvm_run_save(vcpu);
7740 kvm_sigset_deactivate(vcpu);
7746 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7748 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7750 * We are here if userspace calls get_regs() in the middle of
7751 * instruction emulation. Registers state needs to be copied
7752 * back from emulation context to vcpu. Userspace shouldn't do
7753 * that usually, but some bad designed PV devices (vmware
7754 * backdoor interface) need this to work
7756 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7757 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7759 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7760 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7761 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7762 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7763 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7764 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7765 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7766 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7767 #ifdef CONFIG_X86_64
7768 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7769 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7770 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7771 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7772 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7773 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7774 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7775 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7778 regs->rip = kvm_rip_read(vcpu);
7779 regs->rflags = kvm_get_rflags(vcpu);
7782 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7785 __get_regs(vcpu, regs);
7790 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7792 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7793 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7795 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7796 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7797 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7798 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7799 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7800 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7801 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7802 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7803 #ifdef CONFIG_X86_64
7804 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7805 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7806 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7807 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7808 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7809 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7810 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7811 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7814 kvm_rip_write(vcpu, regs->rip);
7815 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
7817 vcpu->arch.exception.pending = false;
7819 kvm_make_request(KVM_REQ_EVENT, vcpu);
7822 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7825 __set_regs(vcpu, regs);
7830 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7832 struct kvm_segment cs;
7834 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7838 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7840 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7844 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7845 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7846 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7847 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7848 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7849 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7851 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7852 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7854 kvm_x86_ops->get_idt(vcpu, &dt);
7855 sregs->idt.limit = dt.size;
7856 sregs->idt.base = dt.address;
7857 kvm_x86_ops->get_gdt(vcpu, &dt);
7858 sregs->gdt.limit = dt.size;
7859 sregs->gdt.base = dt.address;
7861 sregs->cr0 = kvm_read_cr0(vcpu);
7862 sregs->cr2 = vcpu->arch.cr2;
7863 sregs->cr3 = kvm_read_cr3(vcpu);
7864 sregs->cr4 = kvm_read_cr4(vcpu);
7865 sregs->cr8 = kvm_get_cr8(vcpu);
7866 sregs->efer = vcpu->arch.efer;
7867 sregs->apic_base = kvm_get_apic_base(vcpu);
7869 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7871 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
7872 set_bit(vcpu->arch.interrupt.nr,
7873 (unsigned long *)sregs->interrupt_bitmap);
7876 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7877 struct kvm_sregs *sregs)
7880 __get_sregs(vcpu, sregs);
7885 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7886 struct kvm_mp_state *mp_state)
7890 kvm_apic_accept_events(vcpu);
7891 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7892 vcpu->arch.pv.pv_unhalted)
7893 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7895 mp_state->mp_state = vcpu->arch.mp_state;
7901 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7902 struct kvm_mp_state *mp_state)
7908 if (!lapic_in_kernel(vcpu) &&
7909 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7912 /* INITs are latched while in SMM */
7913 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7914 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7915 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7918 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7919 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7920 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7922 vcpu->arch.mp_state = mp_state->mp_state;
7923 kvm_make_request(KVM_REQ_EVENT, vcpu);
7931 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7932 int reason, bool has_error_code, u32 error_code)
7934 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7937 init_emulate_ctxt(vcpu);
7939 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7940 has_error_code, error_code);
7943 return EMULATE_FAIL;
7945 kvm_rip_write(vcpu, ctxt->eip);
7946 kvm_set_rflags(vcpu, ctxt->eflags);
7947 kvm_make_request(KVM_REQ_EVENT, vcpu);
7948 return EMULATE_DONE;
7950 EXPORT_SYMBOL_GPL(kvm_task_switch);
7952 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7954 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
7956 * When EFER.LME and CR0.PG are set, the processor is in
7957 * 64-bit mode (though maybe in a 32-bit code segment).
7958 * CR4.PAE and EFER.LMA must be set.
7960 if (!(sregs->cr4 & X86_CR4_PAE)
7961 || !(sregs->efer & EFER_LMA))
7965 * Not in 64-bit mode: EFER.LMA is clear and the code
7966 * segment cannot be 64-bit.
7968 if (sregs->efer & EFER_LMA || sregs->cs.l)
7975 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7977 struct msr_data apic_base_msr;
7978 int mmu_reset_needed = 0;
7979 int cpuid_update_needed = 0;
7980 int pending_vec, max_bits, idx;
7984 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7985 (sregs->cr4 & X86_CR4_OSXSAVE))
7988 if (kvm_valid_sregs(vcpu, sregs))
7991 apic_base_msr.data = sregs->apic_base;
7992 apic_base_msr.host_initiated = true;
7993 if (kvm_set_apic_base(vcpu, &apic_base_msr))
7996 dt.size = sregs->idt.limit;
7997 dt.address = sregs->idt.base;
7998 kvm_x86_ops->set_idt(vcpu, &dt);
7999 dt.size = sregs->gdt.limit;
8000 dt.address = sregs->gdt.base;
8001 kvm_x86_ops->set_gdt(vcpu, &dt);
8003 vcpu->arch.cr2 = sregs->cr2;
8004 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8005 vcpu->arch.cr3 = sregs->cr3;
8006 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8008 kvm_set_cr8(vcpu, sregs->cr8);
8010 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8011 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8013 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8014 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8015 vcpu->arch.cr0 = sregs->cr0;
8017 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8018 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8019 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8020 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8021 if (cpuid_update_needed)
8022 kvm_update_cpuid(vcpu);
8024 idx = srcu_read_lock(&vcpu->kvm->srcu);
8025 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
8026 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8027 mmu_reset_needed = 1;
8029 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8031 if (mmu_reset_needed)
8032 kvm_mmu_reset_context(vcpu);
8034 max_bits = KVM_NR_INTERRUPTS;
8035 pending_vec = find_first_bit(
8036 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8037 if (pending_vec < max_bits) {
8038 kvm_queue_interrupt(vcpu, pending_vec, false);
8039 pr_debug("Set back pending irq %d\n", pending_vec);
8042 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8043 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8044 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8045 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8046 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8047 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8049 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8050 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8052 update_cr8_intercept(vcpu);
8054 /* Older userspace won't unhalt the vcpu on reset. */
8055 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8056 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8058 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8060 kvm_make_request(KVM_REQ_EVENT, vcpu);
8067 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8068 struct kvm_sregs *sregs)
8073 ret = __set_sregs(vcpu, sregs);
8078 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8079 struct kvm_guest_debug *dbg)
8081 unsigned long rflags;
8086 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8088 if (vcpu->arch.exception.pending)
8090 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8091 kvm_queue_exception(vcpu, DB_VECTOR);
8093 kvm_queue_exception(vcpu, BP_VECTOR);
8097 * Read rflags as long as potentially injected trace flags are still
8100 rflags = kvm_get_rflags(vcpu);
8102 vcpu->guest_debug = dbg->control;
8103 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8104 vcpu->guest_debug = 0;
8106 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8107 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8108 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8109 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8111 for (i = 0; i < KVM_NR_DB_REGS; i++)
8112 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8114 kvm_update_dr7(vcpu);
8116 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8117 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8118 get_segment_base(vcpu, VCPU_SREG_CS);
8121 * Trigger an rflags update that will inject or remove the trace
8124 kvm_set_rflags(vcpu, rflags);
8126 kvm_x86_ops->update_bp_intercept(vcpu);
8136 * Translate a guest virtual address to a guest physical address.
8138 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8139 struct kvm_translation *tr)
8141 unsigned long vaddr = tr->linear_address;
8147 idx = srcu_read_lock(&vcpu->kvm->srcu);
8148 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8149 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8150 tr->physical_address = gpa;
8151 tr->valid = gpa != UNMAPPED_GVA;
8159 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8161 struct fxregs_state *fxsave;
8165 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
8166 memcpy(fpu->fpr, fxsave->st_space, 128);
8167 fpu->fcw = fxsave->cwd;
8168 fpu->fsw = fxsave->swd;
8169 fpu->ftwx = fxsave->twd;
8170 fpu->last_opcode = fxsave->fop;
8171 fpu->last_ip = fxsave->rip;
8172 fpu->last_dp = fxsave->rdp;
8173 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8179 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8181 struct fxregs_state *fxsave;
8185 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
8187 memcpy(fxsave->st_space, fpu->fpr, 128);
8188 fxsave->cwd = fpu->fcw;
8189 fxsave->swd = fpu->fsw;
8190 fxsave->twd = fpu->ftwx;
8191 fxsave->fop = fpu->last_opcode;
8192 fxsave->rip = fpu->last_ip;
8193 fxsave->rdp = fpu->last_dp;
8194 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8200 static void store_regs(struct kvm_vcpu *vcpu)
8202 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8204 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8205 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8207 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8208 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8210 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8211 kvm_vcpu_ioctl_x86_get_vcpu_events(
8212 vcpu, &vcpu->run->s.regs.events);
8215 static int sync_regs(struct kvm_vcpu *vcpu)
8217 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8220 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8221 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8222 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8224 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8225 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8227 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8229 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8230 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8231 vcpu, &vcpu->run->s.regs.events))
8233 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8239 static void fx_init(struct kvm_vcpu *vcpu)
8241 fpstate_init(&vcpu->arch.guest_fpu.state);
8242 if (boot_cpu_has(X86_FEATURE_XSAVES))
8243 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
8244 host_xcr0 | XSTATE_COMPACTION_ENABLED;
8247 * Ensure guest xcr0 is valid for loading
8249 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8251 vcpu->arch.cr0 |= X86_CR0_ET;
8254 /* Swap (qemu) user FPU context for the guest FPU context. */
8255 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8258 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
8259 /* PKRU is separately restored in kvm_x86_ops->run. */
8260 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8261 ~XFEATURE_MASK_PKRU);
8266 /* When vcpu_run ends, restore user space FPU context. */
8267 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8270 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
8271 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8273 ++vcpu->stat.fpu_reload;
8277 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8279 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8281 kvmclock_reset(vcpu);
8283 kvm_x86_ops->vcpu_free(vcpu);
8284 free_cpumask_var(wbinvd_dirty_mask);
8287 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8290 struct kvm_vcpu *vcpu;
8292 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
8293 printk_once(KERN_WARNING
8294 "kvm: SMP vm created on host with unstable TSC; "
8295 "guest TSC will not be reliable\n");
8297 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8302 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8304 kvm_vcpu_mtrr_init(vcpu);
8306 kvm_vcpu_reset(vcpu, false);
8307 kvm_mmu_setup(vcpu);
8312 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
8314 struct msr_data msr;
8315 struct kvm *kvm = vcpu->kvm;
8317 kvm_hv_vcpu_postcreate(vcpu);
8319 if (mutex_lock_killable(&vcpu->mutex))
8323 msr.index = MSR_IA32_TSC;
8324 msr.host_initiated = true;
8325 kvm_write_tsc(vcpu, &msr);
8327 mutex_unlock(&vcpu->mutex);
8329 if (!kvmclock_periodic_sync)
8332 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8333 KVMCLOCK_SYNC_PERIOD);
8336 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
8338 vcpu->arch.apf.msr_val = 0;
8341 kvm_mmu_unload(vcpu);
8344 kvm_x86_ops->vcpu_free(vcpu);
8347 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
8349 kvm_lapic_reset(vcpu, init_event);
8351 vcpu->arch.hflags = 0;
8353 vcpu->arch.smi_pending = 0;
8354 vcpu->arch.smi_count = 0;
8355 atomic_set(&vcpu->arch.nmi_queued, 0);
8356 vcpu->arch.nmi_pending = 0;
8357 vcpu->arch.nmi_injected = false;
8358 kvm_clear_interrupt_queue(vcpu);
8359 kvm_clear_exception_queue(vcpu);
8360 vcpu->arch.exception.pending = false;
8362 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
8363 kvm_update_dr0123(vcpu);
8364 vcpu->arch.dr6 = DR6_INIT;
8365 kvm_update_dr6(vcpu);
8366 vcpu->arch.dr7 = DR7_FIXED_1;
8367 kvm_update_dr7(vcpu);
8371 kvm_make_request(KVM_REQ_EVENT, vcpu);
8372 vcpu->arch.apf.msr_val = 0;
8373 vcpu->arch.st.msr_val = 0;
8375 kvmclock_reset(vcpu);
8377 kvm_clear_async_pf_completion_queue(vcpu);
8378 kvm_async_pf_hash_reset(vcpu);
8379 vcpu->arch.apf.halted = false;
8381 if (kvm_mpx_supported()) {
8382 void *mpx_state_buffer;
8385 * To avoid have the INIT path from kvm_apic_has_events() that be
8386 * called with loaded FPU and does not let userspace fix the state.
8389 kvm_put_guest_fpu(vcpu);
8390 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8391 XFEATURE_MASK_BNDREGS);
8392 if (mpx_state_buffer)
8393 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8394 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8395 XFEATURE_MASK_BNDCSR);
8396 if (mpx_state_buffer)
8397 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
8399 kvm_load_guest_fpu(vcpu);
8403 kvm_pmu_reset(vcpu);
8404 vcpu->arch.smbase = 0x30000;
8406 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8407 vcpu->arch.msr_misc_features_enables = 0;
8409 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8412 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8413 vcpu->arch.regs_avail = ~0;
8414 vcpu->arch.regs_dirty = ~0;
8416 vcpu->arch.ia32_xss = 0;
8418 kvm_x86_ops->vcpu_reset(vcpu, init_event);
8421 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
8423 struct kvm_segment cs;
8425 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8426 cs.selector = vector << 8;
8427 cs.base = vector << 12;
8428 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8429 kvm_rip_write(vcpu, 0);
8432 int kvm_arch_hardware_enable(void)
8435 struct kvm_vcpu *vcpu;
8440 bool stable, backwards_tsc = false;
8442 kvm_shared_msr_cpu_online();
8443 ret = kvm_x86_ops->hardware_enable();
8447 local_tsc = rdtsc();
8448 stable = !kvm_check_tsc_unstable();
8449 list_for_each_entry(kvm, &vm_list, vm_list) {
8450 kvm_for_each_vcpu(i, vcpu, kvm) {
8451 if (!stable && vcpu->cpu == smp_processor_id())
8452 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8453 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8454 backwards_tsc = true;
8455 if (vcpu->arch.last_host_tsc > max_tsc)
8456 max_tsc = vcpu->arch.last_host_tsc;
8462 * Sometimes, even reliable TSCs go backwards. This happens on
8463 * platforms that reset TSC during suspend or hibernate actions, but
8464 * maintain synchronization. We must compensate. Fortunately, we can
8465 * detect that condition here, which happens early in CPU bringup,
8466 * before any KVM threads can be running. Unfortunately, we can't
8467 * bring the TSCs fully up to date with real time, as we aren't yet far
8468 * enough into CPU bringup that we know how much real time has actually
8469 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
8470 * variables that haven't been updated yet.
8472 * So we simply find the maximum observed TSC above, then record the
8473 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8474 * the adjustment will be applied. Note that we accumulate
8475 * adjustments, in case multiple suspend cycles happen before some VCPU
8476 * gets a chance to run again. In the event that no KVM threads get a
8477 * chance to run, we will miss the entire elapsed period, as we'll have
8478 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8479 * loose cycle time. This isn't too big a deal, since the loss will be
8480 * uniform across all VCPUs (not to mention the scenario is extremely
8481 * unlikely). It is possible that a second hibernate recovery happens
8482 * much faster than a first, causing the observed TSC here to be
8483 * smaller; this would require additional padding adjustment, which is
8484 * why we set last_host_tsc to the local tsc observed here.
8486 * N.B. - this code below runs only on platforms with reliable TSC,
8487 * as that is the only way backwards_tsc is set above. Also note
8488 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8489 * have the same delta_cyc adjustment applied if backwards_tsc
8490 * is detected. Note further, this adjustment is only done once,
8491 * as we reset last_host_tsc on all VCPUs to stop this from being
8492 * called multiple times (one for each physical CPU bringup).
8494 * Platforms with unreliable TSCs don't have to deal with this, they
8495 * will be compensated by the logic in vcpu_load, which sets the TSC to
8496 * catchup mode. This will catchup all VCPUs to real time, but cannot
8497 * guarantee that they stay in perfect synchronization.
8499 if (backwards_tsc) {
8500 u64 delta_cyc = max_tsc - local_tsc;
8501 list_for_each_entry(kvm, &vm_list, vm_list) {
8502 kvm->arch.backwards_tsc_observed = true;
8503 kvm_for_each_vcpu(i, vcpu, kvm) {
8504 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8505 vcpu->arch.last_host_tsc = local_tsc;
8506 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
8510 * We have to disable TSC offset matching.. if you were
8511 * booting a VM while issuing an S4 host suspend....
8512 * you may have some problem. Solving this issue is
8513 * left as an exercise to the reader.
8515 kvm->arch.last_tsc_nsec = 0;
8516 kvm->arch.last_tsc_write = 0;
8523 void kvm_arch_hardware_disable(void)
8525 kvm_x86_ops->hardware_disable();
8526 drop_user_return_notifiers();
8529 int kvm_arch_hardware_setup(void)
8533 r = kvm_x86_ops->hardware_setup();
8537 if (kvm_has_tsc_control) {
8539 * Make sure the user can only configure tsc_khz values that
8540 * fit into a signed integer.
8541 * A min value is not calculated needed because it will always
8542 * be 1 on all machines.
8544 u64 max = min(0x7fffffffULL,
8545 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8546 kvm_max_guest_tsc_khz = max;
8548 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
8551 kvm_init_msr_list();
8555 void kvm_arch_hardware_unsetup(void)
8557 kvm_x86_ops->hardware_unsetup();
8560 void kvm_arch_check_processor_compat(void *rtn)
8562 kvm_x86_ops->check_processor_compatibility(rtn);
8565 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8567 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8569 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8571 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8573 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
8576 struct static_key kvm_no_apic_vcpu __read_mostly;
8577 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
8579 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8584 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
8585 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
8586 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
8587 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8589 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
8591 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8596 vcpu->arch.pio_data = page_address(page);
8598 kvm_set_tsc_khz(vcpu, max_tsc_khz);
8600 r = kvm_mmu_create(vcpu);
8602 goto fail_free_pio_data;
8604 if (irqchip_in_kernel(vcpu->kvm)) {
8605 r = kvm_create_lapic(vcpu);
8607 goto fail_mmu_destroy;
8609 static_key_slow_inc(&kvm_no_apic_vcpu);
8611 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8613 if (!vcpu->arch.mce_banks) {
8615 goto fail_free_lapic;
8617 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8619 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8621 goto fail_free_mce_banks;
8626 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
8628 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8630 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8632 kvm_async_pf_hash_reset(vcpu);
8635 vcpu->arch.pending_external_vector = -1;
8636 vcpu->arch.preempted_in_kernel = false;
8638 kvm_hv_vcpu_init(vcpu);
8642 fail_free_mce_banks:
8643 kfree(vcpu->arch.mce_banks);
8645 kvm_free_lapic(vcpu);
8647 kvm_mmu_destroy(vcpu);
8649 free_page((unsigned long)vcpu->arch.pio_data);
8654 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8658 kvm_hv_vcpu_uninit(vcpu);
8659 kvm_pmu_destroy(vcpu);
8660 kfree(vcpu->arch.mce_banks);
8661 kvm_free_lapic(vcpu);
8662 idx = srcu_read_lock(&vcpu->kvm->srcu);
8663 kvm_mmu_destroy(vcpu);
8664 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8665 free_page((unsigned long)vcpu->arch.pio_data);
8666 if (!lapic_in_kernel(vcpu))
8667 static_key_slow_dec(&kvm_no_apic_vcpu);
8670 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8672 kvm_x86_ops->sched_in(vcpu, cpu);
8675 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
8680 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
8681 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
8682 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
8683 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
8684 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
8686 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8687 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
8688 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8689 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8690 &kvm->arch.irq_sources_bitmap);
8692 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
8693 mutex_init(&kvm->arch.apic_map_lock);
8694 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8696 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
8697 pvclock_update_vm_gtod_copy(kvm);
8699 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
8700 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
8702 kvm_hv_init_vm(kvm);
8703 kvm_page_track_init(kvm);
8704 kvm_mmu_init_vm(kvm);
8706 if (kvm_x86_ops->vm_init)
8707 return kvm_x86_ops->vm_init(kvm);
8712 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8715 kvm_mmu_unload(vcpu);
8719 static void kvm_free_vcpus(struct kvm *kvm)
8722 struct kvm_vcpu *vcpu;
8725 * Unpin any mmu pages first.
8727 kvm_for_each_vcpu(i, vcpu, kvm) {
8728 kvm_clear_async_pf_completion_queue(vcpu);
8729 kvm_unload_vcpu_mmu(vcpu);
8731 kvm_for_each_vcpu(i, vcpu, kvm)
8732 kvm_arch_vcpu_free(vcpu);
8734 mutex_lock(&kvm->lock);
8735 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8736 kvm->vcpus[i] = NULL;
8738 atomic_set(&kvm->online_vcpus, 0);
8739 mutex_unlock(&kvm->lock);
8742 void kvm_arch_sync_events(struct kvm *kvm)
8744 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
8745 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
8749 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8753 struct kvm_memslots *slots = kvm_memslots(kvm);
8754 struct kvm_memory_slot *slot, old;
8756 /* Called with kvm->slots_lock held. */
8757 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8760 slot = id_to_memslot(slots, id);
8766 * MAP_SHARED to prevent internal slot pages from being moved
8769 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8770 MAP_SHARED | MAP_ANONYMOUS, 0);
8771 if (IS_ERR((void *)hva))
8772 return PTR_ERR((void *)hva);
8781 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8782 struct kvm_userspace_memory_region m;
8784 m.slot = id | (i << 16);
8786 m.guest_phys_addr = gpa;
8787 m.userspace_addr = hva;
8788 m.memory_size = size;
8789 r = __kvm_set_memory_region(kvm, &m);
8795 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8799 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8801 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8805 mutex_lock(&kvm->slots_lock);
8806 r = __x86_set_memory_region(kvm, id, gpa, size);
8807 mutex_unlock(&kvm->slots_lock);
8811 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8813 void kvm_arch_destroy_vm(struct kvm *kvm)
8815 if (current->mm == kvm->mm) {
8817 * Free memory regions allocated on behalf of userspace,
8818 * unless the the memory map has changed due to process exit
8821 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8822 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8823 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8825 if (kvm_x86_ops->vm_destroy)
8826 kvm_x86_ops->vm_destroy(kvm);
8827 kvm_pic_destroy(kvm);
8828 kvm_ioapic_destroy(kvm);
8829 kvm_free_vcpus(kvm);
8830 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8831 kvm_mmu_uninit_vm(kvm);
8832 kvm_page_track_cleanup(kvm);
8833 kvm_hv_destroy_vm(kvm);
8836 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8837 struct kvm_memory_slot *dont)
8841 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8842 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8843 kvfree(free->arch.rmap[i]);
8844 free->arch.rmap[i] = NULL;
8849 if (!dont || free->arch.lpage_info[i - 1] !=
8850 dont->arch.lpage_info[i - 1]) {
8851 kvfree(free->arch.lpage_info[i - 1]);
8852 free->arch.lpage_info[i - 1] = NULL;
8856 kvm_page_track_free_memslot(free, dont);
8859 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8860 unsigned long npages)
8864 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8865 struct kvm_lpage_info *linfo;
8870 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8871 slot->base_gfn, level) + 1;
8873 slot->arch.rmap[i] =
8874 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
8876 if (!slot->arch.rmap[i])
8881 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
8885 slot->arch.lpage_info[i - 1] = linfo;
8887 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8888 linfo[0].disallow_lpage = 1;
8889 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8890 linfo[lpages - 1].disallow_lpage = 1;
8891 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8893 * If the gfn and userspace address are not aligned wrt each
8894 * other, or if explicitly asked to, disable large page
8895 * support for this slot
8897 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8898 !kvm_largepages_enabled()) {
8901 for (j = 0; j < lpages; ++j)
8902 linfo[j].disallow_lpage = 1;
8906 if (kvm_page_track_create_memslot(slot, npages))
8912 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8913 kvfree(slot->arch.rmap[i]);
8914 slot->arch.rmap[i] = NULL;
8918 kvfree(slot->arch.lpage_info[i - 1]);
8919 slot->arch.lpage_info[i - 1] = NULL;
8924 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8927 * memslots->generation has been incremented.
8928 * mmio generation may have reached its maximum value.
8930 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8933 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8934 struct kvm_memory_slot *memslot,
8935 const struct kvm_userspace_memory_region *mem,
8936 enum kvm_mr_change change)
8941 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8942 struct kvm_memory_slot *new)
8944 /* Still write protect RO slot */
8945 if (new->flags & KVM_MEM_READONLY) {
8946 kvm_mmu_slot_remove_write_access(kvm, new);
8951 * Call kvm_x86_ops dirty logging hooks when they are valid.
8953 * kvm_x86_ops->slot_disable_log_dirty is called when:
8955 * - KVM_MR_CREATE with dirty logging is disabled
8956 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8958 * The reason is, in case of PML, we need to set D-bit for any slots
8959 * with dirty logging disabled in order to eliminate unnecessary GPA
8960 * logging in PML buffer (and potential PML buffer full VMEXT). This
8961 * guarantees leaving PML enabled during guest's lifetime won't have
8962 * any additonal overhead from PML when guest is running with dirty
8963 * logging disabled for memory slots.
8965 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8966 * to dirty logging mode.
8968 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8970 * In case of write protect:
8972 * Write protect all pages for dirty logging.
8974 * All the sptes including the large sptes which point to this
8975 * slot are set to readonly. We can not create any new large
8976 * spte on this slot until the end of the logging.
8978 * See the comments in fast_page_fault().
8980 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8981 if (kvm_x86_ops->slot_enable_log_dirty)
8982 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8984 kvm_mmu_slot_remove_write_access(kvm, new);
8986 if (kvm_x86_ops->slot_disable_log_dirty)
8987 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8991 void kvm_arch_commit_memory_region(struct kvm *kvm,
8992 const struct kvm_userspace_memory_region *mem,
8993 const struct kvm_memory_slot *old,
8994 const struct kvm_memory_slot *new,
8995 enum kvm_mr_change change)
8997 int nr_mmu_pages = 0;
8999 if (!kvm->arch.n_requested_mmu_pages)
9000 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9003 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
9006 * Dirty logging tracks sptes in 4k granularity, meaning that large
9007 * sptes have to be split. If live migration is successful, the guest
9008 * in the source machine will be destroyed and large sptes will be
9009 * created in the destination. However, if the guest continues to run
9010 * in the source machine (for example if live migration fails), small
9011 * sptes will remain around and cause bad performance.
9013 * Scan sptes if dirty logging has been stopped, dropping those
9014 * which can be collapsed into a single large-page spte. Later
9015 * page faults will create the large-page sptes.
9017 if ((change != KVM_MR_DELETE) &&
9018 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9019 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9020 kvm_mmu_zap_collapsible_sptes(kvm, new);
9023 * Set up write protection and/or dirty logging for the new slot.
9025 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9026 * been zapped so no dirty logging staff is needed for old slot. For
9027 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9028 * new and it's also covered when dealing with the new slot.
9030 * FIXME: const-ify all uses of struct kvm_memory_slot.
9032 if (change != KVM_MR_DELETE)
9033 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9036 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9038 kvm_mmu_invalidate_zap_all_pages(kvm);
9041 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9042 struct kvm_memory_slot *slot)
9044 kvm_page_track_flush_slot(kvm, slot);
9047 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9049 if (!list_empty_careful(&vcpu->async_pf.done))
9052 if (kvm_apic_has_events(vcpu))
9055 if (vcpu->arch.pv.pv_unhalted)
9058 if (vcpu->arch.exception.pending)
9061 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9062 (vcpu->arch.nmi_pending &&
9063 kvm_x86_ops->nmi_allowed(vcpu)))
9066 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9067 (vcpu->arch.smi_pending && !is_smm(vcpu)))
9070 if (kvm_arch_interrupt_allowed(vcpu) &&
9071 kvm_cpu_has_interrupt(vcpu))
9074 if (kvm_hv_has_stimer_pending(vcpu))
9080 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9082 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9085 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9087 return vcpu->arch.preempted_in_kernel;
9090 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9092 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9095 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9097 return kvm_x86_ops->interrupt_allowed(vcpu);
9100 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9102 if (is_64_bit_mode(vcpu))
9103 return kvm_rip_read(vcpu);
9104 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9105 kvm_rip_read(vcpu));
9107 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9109 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9111 return kvm_get_linear_rip(vcpu) == linear_rip;
9113 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9115 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9117 unsigned long rflags;
9119 rflags = kvm_x86_ops->get_rflags(vcpu);
9120 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9121 rflags &= ~X86_EFLAGS_TF;
9124 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9126 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9128 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9129 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9130 rflags |= X86_EFLAGS_TF;
9131 kvm_x86_ops->set_rflags(vcpu, rflags);
9134 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9136 __kvm_set_rflags(vcpu, rflags);
9137 kvm_make_request(KVM_REQ_EVENT, vcpu);
9139 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9141 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9145 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
9149 r = kvm_mmu_reload(vcpu);
9153 if (!vcpu->arch.mmu.direct_map &&
9154 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9157 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9160 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9162 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9165 static inline u32 kvm_async_pf_next_probe(u32 key)
9167 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9170 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9172 u32 key = kvm_async_pf_hash_fn(gfn);
9174 while (vcpu->arch.apf.gfns[key] != ~0)
9175 key = kvm_async_pf_next_probe(key);
9177 vcpu->arch.apf.gfns[key] = gfn;
9180 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9183 u32 key = kvm_async_pf_hash_fn(gfn);
9185 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9186 (vcpu->arch.apf.gfns[key] != gfn &&
9187 vcpu->arch.apf.gfns[key] != ~0); i++)
9188 key = kvm_async_pf_next_probe(key);
9193 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9195 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9198 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9202 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9204 vcpu->arch.apf.gfns[i] = ~0;
9206 j = kvm_async_pf_next_probe(j);
9207 if (vcpu->arch.apf.gfns[j] == ~0)
9209 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9211 * k lies cyclically in ]i,j]
9213 * |....j i.k.| or |.k..j i...|
9215 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9216 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9221 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9224 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9228 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9231 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9235 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9236 struct kvm_async_pf *work)
9238 struct x86_exception fault;
9240 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
9241 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
9243 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9244 (vcpu->arch.apf.send_user_only &&
9245 kvm_x86_ops->get_cpl(vcpu) == 0))
9246 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9247 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
9248 fault.vector = PF_VECTOR;
9249 fault.error_code_valid = true;
9250 fault.error_code = 0;
9251 fault.nested_page_fault = false;
9252 fault.address = work->arch.token;
9253 fault.async_page_fault = true;
9254 kvm_inject_page_fault(vcpu, &fault);
9258 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9259 struct kvm_async_pf *work)
9261 struct x86_exception fault;
9264 if (work->wakeup_all)
9265 work->arch.token = ~0; /* broadcast wakeup */
9267 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
9268 trace_kvm_async_pf_ready(work->arch.token, work->gva);
9270 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9271 !apf_get_user(vcpu, &val)) {
9272 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9273 vcpu->arch.exception.pending &&
9274 vcpu->arch.exception.nr == PF_VECTOR &&
9275 !apf_put_user(vcpu, 0)) {
9276 vcpu->arch.exception.injected = false;
9277 vcpu->arch.exception.pending = false;
9278 vcpu->arch.exception.nr = 0;
9279 vcpu->arch.exception.has_error_code = false;
9280 vcpu->arch.exception.error_code = 0;
9281 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9282 fault.vector = PF_VECTOR;
9283 fault.error_code_valid = true;
9284 fault.error_code = 0;
9285 fault.nested_page_fault = false;
9286 fault.address = work->arch.token;
9287 fault.async_page_fault = true;
9288 kvm_inject_page_fault(vcpu, &fault);
9291 vcpu->arch.apf.halted = false;
9292 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9295 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9297 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9300 return kvm_can_do_async_pf(vcpu);
9303 void kvm_arch_start_assignment(struct kvm *kvm)
9305 atomic_inc(&kvm->arch.assigned_device_count);
9307 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9309 void kvm_arch_end_assignment(struct kvm *kvm)
9311 atomic_dec(&kvm->arch.assigned_device_count);
9313 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9315 bool kvm_arch_has_assigned_device(struct kvm *kvm)
9317 return atomic_read(&kvm->arch.assigned_device_count);
9319 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9321 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9323 atomic_inc(&kvm->arch.noncoherent_dma_count);
9325 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9327 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9329 atomic_dec(&kvm->arch.noncoherent_dma_count);
9331 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9333 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9335 return atomic_read(&kvm->arch.noncoherent_dma_count);
9337 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9339 bool kvm_arch_has_irq_bypass(void)
9341 return kvm_x86_ops->update_pi_irte != NULL;
9344 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9345 struct irq_bypass_producer *prod)
9347 struct kvm_kernel_irqfd *irqfd =
9348 container_of(cons, struct kvm_kernel_irqfd, consumer);
9350 irqfd->producer = prod;
9352 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9353 prod->irq, irqfd->gsi, 1);
9356 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9357 struct irq_bypass_producer *prod)
9360 struct kvm_kernel_irqfd *irqfd =
9361 container_of(cons, struct kvm_kernel_irqfd, consumer);
9363 WARN_ON(irqfd->producer != prod);
9364 irqfd->producer = NULL;
9367 * When producer of consumer is unregistered, we change back to
9368 * remapped mode, so we can re-use the current implementation
9369 * when the irq is masked/disabled or the consumer side (KVM
9370 * int this case doesn't want to receive the interrupts.
9372 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9374 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9375 " fails: %d\n", irqfd->consumer.token, ret);
9378 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9379 uint32_t guest_irq, bool set)
9381 if (!kvm_x86_ops->update_pi_irte)
9384 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9387 bool kvm_vector_hashing_enabled(void)
9389 return vector_hashing;
9391 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9393 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
9394 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
9395 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9396 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9397 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9398 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
9399 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
9400 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
9401 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
9402 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
9403 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
9404 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
9405 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
9406 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
9407 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
9408 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
9409 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
9410 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9411 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);