1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/cpufreq.h>
46 #include <linux/user-return-notifier.h>
47 #include <linux/srcu.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <linux/uaccess.h>
51 #include <linux/hash.h>
52 #include <linux/pci.h>
53 #include <linux/timekeeper_internal.h>
54 #include <linux/pvclock_gtod.h>
55 #include <linux/kvm_irqfd.h>
56 #include <linux/irqbypass.h>
57 #include <linux/sched/stat.h>
58 #include <linux/sched/isolation.h>
59 #include <linux/mem_encrypt.h>
60 #include <linux/entry-kvm.h>
61 #include <linux/suspend.h>
63 #include <trace/events/kvm.h>
65 #include <asm/debugreg.h>
70 #include <linux/kernel_stat.h>
71 #include <asm/fpu/api.h>
72 #include <asm/fpu/xcr.h>
73 #include <asm/fpu/xstate.h>
74 #include <asm/pvclock.h>
75 #include <asm/div64.h>
76 #include <asm/irq_remapping.h>
77 #include <asm/mshyperv.h>
78 #include <asm/hypervisor.h>
79 #include <asm/tlbflush.h>
80 #include <asm/intel_pt.h>
81 #include <asm/emulate_prefix.h>
83 #include <clocksource/hyperv_timer.h>
85 #define CREATE_TRACE_POINTS
88 #define MAX_IO_MSRS 256
89 #define KVM_MAX_MCE_BANKS 32
90 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
91 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
93 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
95 #define emul_to_vcpu(ctxt) \
96 ((struct kvm_vcpu *)(ctxt)->vcpu)
99 * - enable syscall per default because its emulated by KVM
100 * - enable LME and LMA per default on 64 bit KVM
104 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
106 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
109 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
111 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
113 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
115 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
116 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
118 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
119 static void process_nmi(struct kvm_vcpu *vcpu);
120 static void process_smi(struct kvm_vcpu *vcpu);
121 static void enter_smm(struct kvm_vcpu *vcpu);
122 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
123 static void store_regs(struct kvm_vcpu *vcpu);
124 static int sync_regs(struct kvm_vcpu *vcpu);
125 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
127 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
128 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
130 struct kvm_x86_ops kvm_x86_ops __read_mostly;
132 #define KVM_X86_OP(func) \
133 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
134 *(((struct kvm_x86_ops *)0)->func));
135 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
136 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
137 #include <asm/kvm-x86-ops.h>
138 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
139 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
141 static bool __read_mostly ignore_msrs = 0;
142 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
144 bool __read_mostly report_ignored_msrs = true;
145 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
146 EXPORT_SYMBOL_GPL(report_ignored_msrs);
148 unsigned int min_timer_period_us = 200;
149 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
151 static bool __read_mostly kvmclock_periodic_sync = true;
152 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
154 bool __read_mostly kvm_has_tsc_control;
155 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
156 u32 __read_mostly kvm_max_guest_tsc_khz;
157 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
158 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
159 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
160 u64 __read_mostly kvm_max_tsc_scaling_ratio;
161 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
162 u64 __read_mostly kvm_default_tsc_scaling_ratio;
163 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
164 bool __read_mostly kvm_has_bus_lock_exit;
165 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit);
167 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
168 static u32 __read_mostly tsc_tolerance_ppm = 250;
169 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
172 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
173 * adaptive tuning starting from default advancement of 1000ns. '0' disables
174 * advancement entirely. Any other value is used as-is and disables adaptive
175 * tuning, i.e. allows privileged userspace to set an exact advancement time.
177 static int __read_mostly lapic_timer_advance_ns = -1;
178 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
180 static bool __read_mostly vector_hashing = true;
181 module_param(vector_hashing, bool, S_IRUGO);
183 bool __read_mostly enable_vmware_backdoor = false;
184 module_param(enable_vmware_backdoor, bool, S_IRUGO);
185 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
187 static bool __read_mostly force_emulation_prefix = false;
188 module_param(force_emulation_prefix, bool, S_IRUGO);
190 int __read_mostly pi_inject_timer = -1;
191 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
193 /* Enable/disable PMU virtualization */
194 bool __read_mostly enable_pmu = true;
195 EXPORT_SYMBOL_GPL(enable_pmu);
196 module_param(enable_pmu, bool, 0444);
198 bool __read_mostly eager_page_split = true;
199 module_param(eager_page_split, bool, 0644);
202 * Restoring the host value for MSRs that are only consumed when running in
203 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
204 * returns to userspace, i.e. the kernel can run with the guest's value.
206 #define KVM_MAX_NR_USER_RETURN_MSRS 16
208 struct kvm_user_return_msrs {
209 struct user_return_notifier urn;
211 struct kvm_user_return_msr_values {
214 } values[KVM_MAX_NR_USER_RETURN_MSRS];
217 u32 __read_mostly kvm_nr_uret_msrs;
218 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
219 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
220 static struct kvm_user_return_msrs __percpu *user_return_msrs;
222 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
223 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
224 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
225 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
227 u64 __read_mostly host_efer;
228 EXPORT_SYMBOL_GPL(host_efer);
230 bool __read_mostly allow_smaller_maxphyaddr = 0;
231 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
233 bool __read_mostly enable_apicv = true;
234 EXPORT_SYMBOL_GPL(enable_apicv);
236 u64 __read_mostly host_xss;
237 EXPORT_SYMBOL_GPL(host_xss);
238 u64 __read_mostly supported_xss;
239 EXPORT_SYMBOL_GPL(supported_xss);
241 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
242 KVM_GENERIC_VM_STATS(),
243 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
244 STATS_DESC_COUNTER(VM, mmu_pte_write),
245 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
246 STATS_DESC_COUNTER(VM, mmu_flooded),
247 STATS_DESC_COUNTER(VM, mmu_recycled),
248 STATS_DESC_COUNTER(VM, mmu_cache_miss),
249 STATS_DESC_ICOUNTER(VM, mmu_unsync),
250 STATS_DESC_ICOUNTER(VM, pages_4k),
251 STATS_DESC_ICOUNTER(VM, pages_2m),
252 STATS_DESC_ICOUNTER(VM, pages_1g),
253 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
254 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
255 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
258 const struct kvm_stats_header kvm_vm_stats_header = {
259 .name_size = KVM_STATS_NAME_SIZE,
260 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
261 .id_offset = sizeof(struct kvm_stats_header),
262 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
263 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
264 sizeof(kvm_vm_stats_desc),
267 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
268 KVM_GENERIC_VCPU_STATS(),
269 STATS_DESC_COUNTER(VCPU, pf_fixed),
270 STATS_DESC_COUNTER(VCPU, pf_guest),
271 STATS_DESC_COUNTER(VCPU, tlb_flush),
272 STATS_DESC_COUNTER(VCPU, invlpg),
273 STATS_DESC_COUNTER(VCPU, exits),
274 STATS_DESC_COUNTER(VCPU, io_exits),
275 STATS_DESC_COUNTER(VCPU, mmio_exits),
276 STATS_DESC_COUNTER(VCPU, signal_exits),
277 STATS_DESC_COUNTER(VCPU, irq_window_exits),
278 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
279 STATS_DESC_COUNTER(VCPU, l1d_flush),
280 STATS_DESC_COUNTER(VCPU, halt_exits),
281 STATS_DESC_COUNTER(VCPU, request_irq_exits),
282 STATS_DESC_COUNTER(VCPU, irq_exits),
283 STATS_DESC_COUNTER(VCPU, host_state_reload),
284 STATS_DESC_COUNTER(VCPU, fpu_reload),
285 STATS_DESC_COUNTER(VCPU, insn_emulation),
286 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
287 STATS_DESC_COUNTER(VCPU, hypercalls),
288 STATS_DESC_COUNTER(VCPU, irq_injections),
289 STATS_DESC_COUNTER(VCPU, nmi_injections),
290 STATS_DESC_COUNTER(VCPU, req_event),
291 STATS_DESC_COUNTER(VCPU, nested_run),
292 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
293 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
294 STATS_DESC_ICOUNTER(VCPU, guest_mode)
297 const struct kvm_stats_header kvm_vcpu_stats_header = {
298 .name_size = KVM_STATS_NAME_SIZE,
299 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
300 .id_offset = sizeof(struct kvm_stats_header),
301 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
302 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
303 sizeof(kvm_vcpu_stats_desc),
306 u64 __read_mostly host_xcr0;
307 u64 __read_mostly supported_xcr0;
308 EXPORT_SYMBOL_GPL(supported_xcr0);
310 static struct kmem_cache *x86_emulator_cache;
313 * When called, it means the previous get/set msr reached an invalid msr.
314 * Return true if we want to ignore/silent this failed msr access.
316 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
318 const char *op = write ? "wrmsr" : "rdmsr";
321 if (report_ignored_msrs)
322 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
327 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
333 static struct kmem_cache *kvm_alloc_emulator_cache(void)
335 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
336 unsigned int size = sizeof(struct x86_emulate_ctxt);
338 return kmem_cache_create_usercopy("x86_emulator", size,
339 __alignof__(struct x86_emulate_ctxt),
340 SLAB_ACCOUNT, useroffset,
341 size - useroffset, NULL);
344 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
346 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
349 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
350 vcpu->arch.apf.gfns[i] = ~0;
353 static void kvm_on_user_return(struct user_return_notifier *urn)
356 struct kvm_user_return_msrs *msrs
357 = container_of(urn, struct kvm_user_return_msrs, urn);
358 struct kvm_user_return_msr_values *values;
362 * Disabling irqs at this point since the following code could be
363 * interrupted and executed through kvm_arch_hardware_disable()
365 local_irq_save(flags);
366 if (msrs->registered) {
367 msrs->registered = false;
368 user_return_notifier_unregister(urn);
370 local_irq_restore(flags);
371 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
372 values = &msrs->values[slot];
373 if (values->host != values->curr) {
374 wrmsrl(kvm_uret_msrs_list[slot], values->host);
375 values->curr = values->host;
380 static int kvm_probe_user_return_msr(u32 msr)
386 ret = rdmsrl_safe(msr, &val);
389 ret = wrmsrl_safe(msr, val);
395 int kvm_add_user_return_msr(u32 msr)
397 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
399 if (kvm_probe_user_return_msr(msr))
402 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
403 return kvm_nr_uret_msrs++;
405 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
407 int kvm_find_user_return_msr(u32 msr)
411 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
412 if (kvm_uret_msrs_list[i] == msr)
417 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
419 static void kvm_user_return_msr_cpu_online(void)
421 unsigned int cpu = smp_processor_id();
422 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
426 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
427 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
428 msrs->values[i].host = value;
429 msrs->values[i].curr = value;
433 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
435 unsigned int cpu = smp_processor_id();
436 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
439 value = (value & mask) | (msrs->values[slot].host & ~mask);
440 if (value == msrs->values[slot].curr)
442 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
446 msrs->values[slot].curr = value;
447 if (!msrs->registered) {
448 msrs->urn.on_user_return = kvm_on_user_return;
449 user_return_notifier_register(&msrs->urn);
450 msrs->registered = true;
454 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
456 static void drop_user_return_notifiers(void)
458 unsigned int cpu = smp_processor_id();
459 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
461 if (msrs->registered)
462 kvm_on_user_return(&msrs->urn);
465 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
467 return vcpu->arch.apic_base;
469 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
471 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
473 return kvm_apic_mode(kvm_get_apic_base(vcpu));
475 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
477 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
479 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
480 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
481 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
482 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
484 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
486 if (!msr_info->host_initiated) {
487 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
489 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
493 kvm_lapic_set_base(vcpu, msr_info->data);
494 kvm_recalculate_apic_map(vcpu->kvm);
497 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
500 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
502 * Hardware virtualization extension instructions may fault if a reboot turns
503 * off virtualization while processes are running. Usually after catching the
504 * fault we just panic; during reboot instead the instruction is ignored.
506 noinstr void kvm_spurious_fault(void)
508 /* Fault while not rebooting. We want the trace. */
509 BUG_ON(!kvm_rebooting);
511 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
513 #define EXCPT_BENIGN 0
514 #define EXCPT_CONTRIBUTORY 1
517 static int exception_class(int vector)
527 return EXCPT_CONTRIBUTORY;
534 #define EXCPT_FAULT 0
536 #define EXCPT_ABORT 2
537 #define EXCPT_INTERRUPT 3
539 static int exception_type(int vector)
543 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
544 return EXCPT_INTERRUPT;
548 /* #DB is trap, as instruction watchpoints are handled elsewhere */
549 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
552 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
555 /* Reserved exceptions will result in fault */
559 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
561 unsigned nr = vcpu->arch.exception.nr;
562 bool has_payload = vcpu->arch.exception.has_payload;
563 unsigned long payload = vcpu->arch.exception.payload;
571 * "Certain debug exceptions may clear bit 0-3. The
572 * remaining contents of the DR6 register are never
573 * cleared by the processor".
575 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
577 * In order to reflect the #DB exception payload in guest
578 * dr6, three components need to be considered: active low
579 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
581 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
582 * In the target guest dr6:
583 * FIXED_1 bits should always be set.
584 * Active low bits should be cleared if 1-setting in payload.
585 * Active high bits should be set if 1-setting in payload.
587 * Note, the payload is compatible with the pending debug
588 * exceptions/exit qualification under VMX, that active_low bits
589 * are active high in payload.
590 * So they need to be flipped for DR6.
592 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
593 vcpu->arch.dr6 |= payload;
594 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW;
597 * The #DB payload is defined as compatible with the 'pending
598 * debug exceptions' field under VMX, not DR6. While bit 12 is
599 * defined in the 'pending debug exceptions' field (enabled
600 * breakpoint), it is reserved and must be zero in DR6.
602 vcpu->arch.dr6 &= ~BIT(12);
605 vcpu->arch.cr2 = payload;
609 vcpu->arch.exception.has_payload = false;
610 vcpu->arch.exception.payload = 0;
612 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
614 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
615 unsigned nr, bool has_error, u32 error_code,
616 bool has_payload, unsigned long payload, bool reinject)
621 kvm_make_request(KVM_REQ_EVENT, vcpu);
623 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
627 * On vmentry, vcpu->arch.exception.pending is only
628 * true if an event injection was blocked by
629 * nested_run_pending. In that case, however,
630 * vcpu_enter_guest requests an immediate exit,
631 * and the guest shouldn't proceed far enough to
634 WARN_ON_ONCE(vcpu->arch.exception.pending);
635 vcpu->arch.exception.injected = true;
636 if (WARN_ON_ONCE(has_payload)) {
638 * A reinjected event has already
639 * delivered its payload.
645 vcpu->arch.exception.pending = true;
646 vcpu->arch.exception.injected = false;
648 vcpu->arch.exception.has_error_code = has_error;
649 vcpu->arch.exception.nr = nr;
650 vcpu->arch.exception.error_code = error_code;
651 vcpu->arch.exception.has_payload = has_payload;
652 vcpu->arch.exception.payload = payload;
653 if (!is_guest_mode(vcpu))
654 kvm_deliver_exception_payload(vcpu);
658 /* to check exception */
659 prev_nr = vcpu->arch.exception.nr;
660 if (prev_nr == DF_VECTOR) {
661 /* triple fault -> shutdown */
662 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
665 class1 = exception_class(prev_nr);
666 class2 = exception_class(nr);
667 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
668 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
670 * Generate double fault per SDM Table 5-5. Set
671 * exception.pending = true so that the double fault
672 * can trigger a nested vmexit.
674 vcpu->arch.exception.pending = true;
675 vcpu->arch.exception.injected = false;
676 vcpu->arch.exception.has_error_code = true;
677 vcpu->arch.exception.nr = DF_VECTOR;
678 vcpu->arch.exception.error_code = 0;
679 vcpu->arch.exception.has_payload = false;
680 vcpu->arch.exception.payload = 0;
682 /* replace previous exception with a new one in a hope
683 that instruction re-execution will regenerate lost
688 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
690 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
692 EXPORT_SYMBOL_GPL(kvm_queue_exception);
694 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
696 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
698 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
700 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
701 unsigned long payload)
703 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
705 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
707 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
708 u32 error_code, unsigned long payload)
710 kvm_multiple_exception(vcpu, nr, true, error_code,
711 true, payload, false);
714 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
717 kvm_inject_gp(vcpu, 0);
719 return kvm_skip_emulated_instruction(vcpu);
723 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
725 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
728 kvm_inject_gp(vcpu, 0);
732 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
733 EMULTYPE_COMPLETE_USER_EXIT);
736 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
738 ++vcpu->stat.pf_guest;
739 vcpu->arch.exception.nested_apf =
740 is_guest_mode(vcpu) && fault->async_page_fault;
741 if (vcpu->arch.exception.nested_apf) {
742 vcpu->arch.apf.nested_apf_token = fault->address;
743 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
745 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
749 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
751 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
752 struct x86_exception *fault)
754 struct kvm_mmu *fault_mmu;
755 WARN_ON_ONCE(fault->vector != PF_VECTOR);
757 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
761 * Invalidate the TLB entry for the faulting address, if it exists,
762 * else the access will fault indefinitely (and to emulate hardware).
764 if ((fault->error_code & PFERR_PRESENT_MASK) &&
765 !(fault->error_code & PFERR_RSVD_MASK))
766 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
767 fault_mmu->root.hpa);
769 fault_mmu->inject_page_fault(vcpu, fault);
770 return fault->nested_page_fault;
772 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
774 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
776 atomic_inc(&vcpu->arch.nmi_queued);
777 kvm_make_request(KVM_REQ_NMI, vcpu);
779 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
781 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
783 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
785 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
787 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
789 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
791 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
794 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
795 * a #GP and return false.
797 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
799 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
801 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
804 EXPORT_SYMBOL_GPL(kvm_require_cpl);
806 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
808 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
811 kvm_queue_exception(vcpu, UD_VECTOR);
814 EXPORT_SYMBOL_GPL(kvm_require_dr);
816 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
818 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
822 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
824 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
826 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
827 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
831 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
834 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
837 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
838 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
839 if (real_gpa == UNMAPPED_GVA)
842 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
843 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
844 cr3 & GENMASK(11, 5), sizeof(pdpte));
848 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
849 if ((pdpte[i] & PT_PRESENT_MASK) &&
850 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
856 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
857 * Shadow page roots need to be reconstructed instead.
859 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
860 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
862 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
863 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
864 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
865 vcpu->arch.pdptrs_from_userspace = false;
869 EXPORT_SYMBOL_GPL(load_pdptrs);
871 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
873 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
874 kvm_clear_async_pf_completion_queue(vcpu);
875 kvm_async_pf_hash_reset(vcpu);
878 * Clearing CR0.PG is defined to flush the TLB from the guest's
881 if (!(cr0 & X86_CR0_PG))
882 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
885 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
886 kvm_mmu_reset_context(vcpu);
888 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
889 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
890 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
891 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
893 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
895 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
897 unsigned long old_cr0 = kvm_read_cr0(vcpu);
902 if (cr0 & 0xffffffff00000000UL)
906 cr0 &= ~CR0_RESERVED_BITS;
908 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
911 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
915 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
916 (cr0 & X86_CR0_PG)) {
921 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
926 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
927 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
928 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
931 if (!(cr0 & X86_CR0_PG) &&
932 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)))
935 static_call(kvm_x86_set_cr0)(vcpu, cr0);
937 kvm_post_set_cr0(vcpu, old_cr0, cr0);
941 EXPORT_SYMBOL_GPL(kvm_set_cr0);
943 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
945 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
947 EXPORT_SYMBOL_GPL(kvm_lmsw);
949 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
951 if (vcpu->arch.guest_state_protected)
954 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
956 if (vcpu->arch.xcr0 != host_xcr0)
957 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
959 if (vcpu->arch.xsaves_enabled &&
960 vcpu->arch.ia32_xss != host_xss)
961 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
964 if (static_cpu_has(X86_FEATURE_PKU) &&
965 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
966 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
967 vcpu->arch.pkru != vcpu->arch.host_pkru)
968 write_pkru(vcpu->arch.pkru);
970 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
972 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
974 if (vcpu->arch.guest_state_protected)
977 if (static_cpu_has(X86_FEATURE_PKU) &&
978 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
979 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
980 vcpu->arch.pkru = rdpkru();
981 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
982 write_pkru(vcpu->arch.host_pkru);
985 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
987 if (vcpu->arch.xcr0 != host_xcr0)
988 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
990 if (vcpu->arch.xsaves_enabled &&
991 vcpu->arch.ia32_xss != host_xss)
992 wrmsrl(MSR_IA32_XSS, host_xss);
996 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
998 static inline u64 kvm_guest_supported_xcr0(struct kvm_vcpu *vcpu)
1000 return vcpu->arch.guest_fpu.fpstate->user_xfeatures;
1003 #ifdef CONFIG_X86_64
1004 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1006 return kvm_guest_supported_xcr0(vcpu) & XFEATURE_MASK_USER_DYNAMIC;
1010 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1013 u64 old_xcr0 = vcpu->arch.xcr0;
1016 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1017 if (index != XCR_XFEATURE_ENABLED_MASK)
1019 if (!(xcr0 & XFEATURE_MASK_FP))
1021 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1025 * Do not allow the guest to set bits that we do not support
1026 * saving. However, xcr0 bit 0 is always set, even if the
1027 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1029 valid_bits = kvm_guest_supported_xcr0(vcpu) | XFEATURE_MASK_FP;
1030 if (xcr0 & ~valid_bits)
1033 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1034 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1037 if (xcr0 & XFEATURE_MASK_AVX512) {
1038 if (!(xcr0 & XFEATURE_MASK_YMM))
1040 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1044 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1045 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1048 vcpu->arch.xcr0 = xcr0;
1050 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1051 kvm_update_cpuid_runtime(vcpu);
1055 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1057 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1058 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1059 kvm_inject_gp(vcpu, 0);
1063 return kvm_skip_emulated_instruction(vcpu);
1065 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1067 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1069 if (cr4 & cr4_reserved_bits)
1072 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1075 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1077 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
1079 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1081 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1082 kvm_mmu_reset_context(vcpu);
1085 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1086 * according to the SDM; however, stale prev_roots could be reused
1087 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1088 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1089 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1093 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1094 kvm_mmu_unload(vcpu);
1097 * The TLB has to be flushed for all PCIDs if any of the following
1098 * (architecturally required) changes happen:
1099 * - CR4.PCIDE is changed from 1 to 0
1100 * - CR4.PGE is toggled
1102 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1104 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1105 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1106 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1109 * The TLB has to be flushed for the current PCID if any of the
1110 * following (architecturally required) changes happen:
1111 * - CR4.SMEP is changed from 0 to 1
1112 * - CR4.PAE is toggled
1114 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1115 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1116 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1119 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1121 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1123 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1125 if (!kvm_is_valid_cr4(vcpu, cr4))
1128 if (is_long_mode(vcpu)) {
1129 if (!(cr4 & X86_CR4_PAE))
1131 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1133 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1134 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1135 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1138 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1139 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1142 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1143 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1147 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1149 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1153 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1155 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1157 struct kvm_mmu *mmu = vcpu->arch.mmu;
1158 unsigned long roots_to_free = 0;
1162 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1163 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1164 * also via the emulator. KVM's TDP page tables are not in the scope of
1165 * the invalidation, but the guest's TLB entries need to be flushed as
1166 * the CPU may have cached entries in its TLB for the target PCID.
1168 if (unlikely(tdp_enabled)) {
1169 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1174 * If neither the current CR3 nor any of the prev_roots use the given
1175 * PCID, then nothing needs to be done here because a resync will
1176 * happen anyway before switching to any other CR3.
1178 if (kvm_get_active_pcid(vcpu) == pcid) {
1179 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1180 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1184 * If PCID is disabled, there is no need to free prev_roots even if the
1185 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1188 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
1191 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1192 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1193 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1195 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1198 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1200 bool skip_tlb_flush = false;
1201 unsigned long pcid = 0;
1202 #ifdef CONFIG_X86_64
1203 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1206 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1207 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1208 pcid = cr3 & X86_CR3_PCID_MASK;
1212 /* PDPTRs are always reloaded for PAE paging. */
1213 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1214 goto handle_tlb_flush;
1217 * Do not condition the GPA check on long mode, this helper is used to
1218 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1219 * the current vCPU mode is accurate.
1221 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1224 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1227 if (cr3 != kvm_read_cr3(vcpu))
1228 kvm_mmu_new_pgd(vcpu, cr3);
1230 vcpu->arch.cr3 = cr3;
1231 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1232 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1236 * A load of CR3 that flushes the TLB flushes only the current PCID,
1237 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1238 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1239 * and it's impossible to use a non-zero PCID when PCID is disabled,
1240 * i.e. only PCID=0 can be relevant.
1242 if (!skip_tlb_flush)
1243 kvm_invalidate_pcid(vcpu, pcid);
1247 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1249 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1251 if (cr8 & CR8_RESERVED_BITS)
1253 if (lapic_in_kernel(vcpu))
1254 kvm_lapic_set_tpr(vcpu, cr8);
1256 vcpu->arch.cr8 = cr8;
1259 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1261 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1263 if (lapic_in_kernel(vcpu))
1264 return kvm_lapic_get_cr8(vcpu);
1266 return vcpu->arch.cr8;
1268 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1270 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1274 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1275 for (i = 0; i < KVM_NR_DB_REGS; i++)
1276 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1280 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1284 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1285 dr7 = vcpu->arch.guest_debug_dr7;
1287 dr7 = vcpu->arch.dr7;
1288 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1289 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1290 if (dr7 & DR7_BP_EN_MASK)
1291 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1293 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1295 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1297 u64 fixed = DR6_FIXED_1;
1299 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1302 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1303 fixed |= DR6_BUS_LOCK;
1307 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1309 size_t size = ARRAY_SIZE(vcpu->arch.db);
1313 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1314 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1315 vcpu->arch.eff_db[dr] = val;
1319 if (!kvm_dr6_valid(val))
1321 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1325 if (!kvm_dr7_valid(val))
1327 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1328 kvm_update_dr7(vcpu);
1334 EXPORT_SYMBOL_GPL(kvm_set_dr);
1336 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1338 size_t size = ARRAY_SIZE(vcpu->arch.db);
1342 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1346 *val = vcpu->arch.dr6;
1350 *val = vcpu->arch.dr7;
1354 EXPORT_SYMBOL_GPL(kvm_get_dr);
1356 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1358 u32 ecx = kvm_rcx_read(vcpu);
1361 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1362 kvm_inject_gp(vcpu, 0);
1366 kvm_rax_write(vcpu, (u32)data);
1367 kvm_rdx_write(vcpu, data >> 32);
1368 return kvm_skip_emulated_instruction(vcpu);
1370 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1373 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1374 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1376 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1377 * extract the supported MSRs from the related const lists.
1378 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1379 * capabilities of the host cpu. This capabilities test skips MSRs that are
1380 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1381 * may depend on host virtualization features rather than host cpu features.
1384 static const u32 msrs_to_save_all[] = {
1385 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1387 #ifdef CONFIG_X86_64
1388 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1390 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1391 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1393 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1394 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1395 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1396 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1397 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1398 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1399 MSR_IA32_UMWAIT_CONTROL,
1401 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1402 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1403 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1404 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1405 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1406 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1407 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1408 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1409 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1410 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1411 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1412 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1413 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1414 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1415 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1416 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1417 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1418 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1419 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1420 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1421 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1422 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1424 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1425 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1426 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1427 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1428 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1429 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1430 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1433 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1434 static unsigned num_msrs_to_save;
1436 static const u32 emulated_msrs_all[] = {
1437 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1438 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1439 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1440 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1441 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1442 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1443 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1445 HV_X64_MSR_VP_INDEX,
1446 HV_X64_MSR_VP_RUNTIME,
1447 HV_X64_MSR_SCONTROL,
1448 HV_X64_MSR_STIMER0_CONFIG,
1449 HV_X64_MSR_VP_ASSIST_PAGE,
1450 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1451 HV_X64_MSR_TSC_EMULATION_STATUS,
1452 HV_X64_MSR_SYNDBG_OPTIONS,
1453 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1454 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1455 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1457 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1458 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1460 MSR_IA32_TSC_ADJUST,
1461 MSR_IA32_TSC_DEADLINE,
1462 MSR_IA32_ARCH_CAPABILITIES,
1463 MSR_IA32_PERF_CAPABILITIES,
1464 MSR_IA32_MISC_ENABLE,
1465 MSR_IA32_MCG_STATUS,
1467 MSR_IA32_MCG_EXT_CTL,
1471 MSR_MISC_FEATURES_ENABLES,
1472 MSR_AMD64_VIRT_SPEC_CTRL,
1473 MSR_AMD64_TSC_RATIO,
1478 * The following list leaves out MSRs whose values are determined
1479 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1480 * We always support the "true" VMX control MSRs, even if the host
1481 * processor does not, so I am putting these registers here rather
1482 * than in msrs_to_save_all.
1485 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1486 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1487 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1488 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1490 MSR_IA32_VMX_CR0_FIXED0,
1491 MSR_IA32_VMX_CR4_FIXED0,
1492 MSR_IA32_VMX_VMCS_ENUM,
1493 MSR_IA32_VMX_PROCBASED_CTLS2,
1494 MSR_IA32_VMX_EPT_VPID_CAP,
1495 MSR_IA32_VMX_VMFUNC,
1498 MSR_KVM_POLL_CONTROL,
1501 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1502 static unsigned num_emulated_msrs;
1505 * List of msr numbers which are used to expose MSR-based features that
1506 * can be used by a hypervisor to validate requested CPU features.
1508 static const u32 msr_based_features_all[] = {
1510 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1511 MSR_IA32_VMX_PINBASED_CTLS,
1512 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1513 MSR_IA32_VMX_PROCBASED_CTLS,
1514 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1515 MSR_IA32_VMX_EXIT_CTLS,
1516 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1517 MSR_IA32_VMX_ENTRY_CTLS,
1519 MSR_IA32_VMX_CR0_FIXED0,
1520 MSR_IA32_VMX_CR0_FIXED1,
1521 MSR_IA32_VMX_CR4_FIXED0,
1522 MSR_IA32_VMX_CR4_FIXED1,
1523 MSR_IA32_VMX_VMCS_ENUM,
1524 MSR_IA32_VMX_PROCBASED_CTLS2,
1525 MSR_IA32_VMX_EPT_VPID_CAP,
1526 MSR_IA32_VMX_VMFUNC,
1530 MSR_IA32_ARCH_CAPABILITIES,
1531 MSR_IA32_PERF_CAPABILITIES,
1534 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1535 static unsigned int num_msr_based_features;
1537 static u64 kvm_get_arch_capabilities(void)
1541 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1542 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1545 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1546 * the nested hypervisor runs with NX huge pages. If it is not,
1547 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1548 * L1 guests, so it need not worry about its own (L2) guests.
1550 data |= ARCH_CAP_PSCHANGE_MC_NO;
1553 * If we're doing cache flushes (either "always" or "cond")
1554 * we will do one whenever the guest does a vmlaunch/vmresume.
1555 * If an outer hypervisor is doing the cache flush for us
1556 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1557 * capability to the guest too, and if EPT is disabled we're not
1558 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1559 * require a nested hypervisor to do a flush of its own.
1561 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1562 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1564 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1565 data |= ARCH_CAP_RDCL_NO;
1566 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1567 data |= ARCH_CAP_SSB_NO;
1568 if (!boot_cpu_has_bug(X86_BUG_MDS))
1569 data |= ARCH_CAP_MDS_NO;
1571 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1573 * If RTM=0 because the kernel has disabled TSX, the host might
1574 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1575 * and therefore knows that there cannot be TAA) but keep
1576 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1577 * and we want to allow migrating those guests to tsx=off hosts.
1579 data &= ~ARCH_CAP_TAA_NO;
1580 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1581 data |= ARCH_CAP_TAA_NO;
1584 * Nothing to do here; we emulate TSX_CTRL if present on the
1585 * host so the guest can choose between disabling TSX or
1586 * using VERW to clear CPU buffers.
1593 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1595 switch (msr->index) {
1596 case MSR_IA32_ARCH_CAPABILITIES:
1597 msr->data = kvm_get_arch_capabilities();
1599 case MSR_IA32_UCODE_REV:
1600 rdmsrl_safe(msr->index, &msr->data);
1603 return static_call(kvm_x86_get_msr_feature)(msr);
1608 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1610 struct kvm_msr_entry msr;
1614 r = kvm_get_msr_feature(&msr);
1616 if (r == KVM_MSR_RET_INVALID) {
1617 /* Unconditionally clear the output for simplicity */
1619 if (kvm_msr_ignored_check(index, 0, false))
1631 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1633 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1636 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1639 if (efer & (EFER_LME | EFER_LMA) &&
1640 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1643 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1649 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1651 if (efer & efer_reserved_bits)
1654 return __kvm_valid_efer(vcpu, efer);
1656 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1658 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1660 u64 old_efer = vcpu->arch.efer;
1661 u64 efer = msr_info->data;
1664 if (efer & efer_reserved_bits)
1667 if (!msr_info->host_initiated) {
1668 if (!__kvm_valid_efer(vcpu, efer))
1671 if (is_paging(vcpu) &&
1672 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1677 efer |= vcpu->arch.efer & EFER_LMA;
1679 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1685 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1686 kvm_mmu_reset_context(vcpu);
1691 void kvm_enable_efer_bits(u64 mask)
1693 efer_reserved_bits &= ~mask;
1695 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1697 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1699 struct kvm_x86_msr_filter *msr_filter;
1700 struct msr_bitmap_range *ranges;
1701 struct kvm *kvm = vcpu->kvm;
1706 /* x2APIC MSRs do not support filtering. */
1707 if (index >= 0x800 && index <= 0x8ff)
1710 idx = srcu_read_lock(&kvm->srcu);
1712 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1718 allowed = msr_filter->default_allow;
1719 ranges = msr_filter->ranges;
1721 for (i = 0; i < msr_filter->count; i++) {
1722 u32 start = ranges[i].base;
1723 u32 end = start + ranges[i].nmsrs;
1724 u32 flags = ranges[i].flags;
1725 unsigned long *bitmap = ranges[i].bitmap;
1727 if ((index >= start) && (index < end) && (flags & type)) {
1728 allowed = !!test_bit(index - start, bitmap);
1734 srcu_read_unlock(&kvm->srcu, idx);
1738 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1741 * Write @data into the MSR specified by @index. Select MSR specific fault
1742 * checks are bypassed if @host_initiated is %true.
1743 * Returns 0 on success, non-0 otherwise.
1744 * Assumes vcpu_load() was already called.
1746 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1747 bool host_initiated)
1749 struct msr_data msr;
1754 case MSR_KERNEL_GS_BASE:
1757 if (is_noncanonical_address(data, vcpu))
1760 case MSR_IA32_SYSENTER_EIP:
1761 case MSR_IA32_SYSENTER_ESP:
1763 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1764 * non-canonical address is written on Intel but not on
1765 * AMD (which ignores the top 32-bits, because it does
1766 * not implement 64-bit SYSENTER).
1768 * 64-bit code should hence be able to write a non-canonical
1769 * value on AMD. Making the address canonical ensures that
1770 * vmentry does not fail on Intel after writing a non-canonical
1771 * value, and that something deterministic happens if the guest
1772 * invokes 64-bit SYSENTER.
1774 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1777 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1780 if (!host_initiated &&
1781 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1782 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1786 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1787 * incomplete and conflicting architectural behavior. Current
1788 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1789 * reserved and always read as zeros. Enforce Intel's reserved
1790 * bits check if and only if the guest CPU is Intel, and clear
1791 * the bits in all other cases. This ensures cross-vendor
1792 * migration will provide consistent behavior for the guest.
1794 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1803 msr.host_initiated = host_initiated;
1805 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1808 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1809 u32 index, u64 data, bool host_initiated)
1811 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1813 if (ret == KVM_MSR_RET_INVALID)
1814 if (kvm_msr_ignored_check(index, data, true))
1821 * Read the MSR specified by @index into @data. Select MSR specific fault
1822 * checks are bypassed if @host_initiated is %true.
1823 * Returns 0 on success, non-0 otherwise.
1824 * Assumes vcpu_load() was already called.
1826 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1827 bool host_initiated)
1829 struct msr_data msr;
1834 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1837 if (!host_initiated &&
1838 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1839 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1845 msr.host_initiated = host_initiated;
1847 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1853 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1854 u32 index, u64 *data, bool host_initiated)
1856 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1858 if (ret == KVM_MSR_RET_INVALID) {
1859 /* Unconditionally clear *data for simplicity */
1861 if (kvm_msr_ignored_check(index, 0, false))
1868 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1870 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1871 return KVM_MSR_RET_FILTERED;
1872 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1875 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1877 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1878 return KVM_MSR_RET_FILTERED;
1879 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1882 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1884 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1886 EXPORT_SYMBOL_GPL(kvm_get_msr);
1888 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1890 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1892 EXPORT_SYMBOL_GPL(kvm_set_msr);
1894 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1896 if (!vcpu->run->msr.error) {
1897 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1898 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1902 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
1904 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
1907 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1909 complete_userspace_rdmsr(vcpu);
1910 return complete_emulated_msr_access(vcpu);
1913 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
1915 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
1918 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
1920 complete_userspace_rdmsr(vcpu);
1921 return complete_fast_msr_access(vcpu);
1924 static u64 kvm_msr_reason(int r)
1927 case KVM_MSR_RET_INVALID:
1928 return KVM_MSR_EXIT_REASON_UNKNOWN;
1929 case KVM_MSR_RET_FILTERED:
1930 return KVM_MSR_EXIT_REASON_FILTER;
1932 return KVM_MSR_EXIT_REASON_INVAL;
1936 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1937 u32 exit_reason, u64 data,
1938 int (*completion)(struct kvm_vcpu *vcpu),
1941 u64 msr_reason = kvm_msr_reason(r);
1943 /* Check if the user wanted to know about this MSR fault */
1944 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1947 vcpu->run->exit_reason = exit_reason;
1948 vcpu->run->msr.error = 0;
1949 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1950 vcpu->run->msr.reason = msr_reason;
1951 vcpu->run->msr.index = index;
1952 vcpu->run->msr.data = data;
1953 vcpu->arch.complete_userspace_io = completion;
1958 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1960 u32 ecx = kvm_rcx_read(vcpu);
1964 r = kvm_get_msr_with_filter(vcpu, ecx, &data);
1967 trace_kvm_msr_read(ecx, data);
1969 kvm_rax_write(vcpu, data & -1u);
1970 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1972 /* MSR read failed? See if we should ask user space */
1973 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
1974 complete_fast_rdmsr, r))
1976 trace_kvm_msr_read_ex(ecx);
1979 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
1981 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1983 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1985 u32 ecx = kvm_rcx_read(vcpu);
1986 u64 data = kvm_read_edx_eax(vcpu);
1989 r = kvm_set_msr_with_filter(vcpu, ecx, data);
1992 trace_kvm_msr_write(ecx, data);
1994 /* MSR write failed? See if we should ask user space */
1995 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
1996 complete_fast_msr_access, r))
1998 /* Signal all other negative errors to userspace */
2001 trace_kvm_msr_write_ex(ecx, data);
2004 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2006 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2008 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2010 return kvm_skip_emulated_instruction(vcpu);
2012 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop);
2014 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2016 /* Treat an INVD instruction as a NOP and just skip it. */
2017 return kvm_emulate_as_nop(vcpu);
2019 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2021 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2023 pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n");
2024 return kvm_emulate_as_nop(vcpu);
2026 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2028 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2030 kvm_queue_exception(vcpu, UD_VECTOR);
2033 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2035 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2037 pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n");
2038 return kvm_emulate_as_nop(vcpu);
2040 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2042 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2044 xfer_to_guest_mode_prepare();
2045 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2046 xfer_to_guest_mode_work_pending();
2050 * The fast path for frequent and performance sensitive wrmsr emulation,
2051 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2052 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2053 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2054 * other cases which must be called after interrupts are enabled on the host.
2056 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2058 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2061 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2062 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2063 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2064 ((u32)(data >> 32) != X2APIC_BROADCAST))
2065 return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2070 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2072 if (!kvm_can_use_hv_timer(vcpu))
2075 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2079 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2081 u32 msr = kvm_rcx_read(vcpu);
2083 fastpath_t ret = EXIT_FASTPATH_NONE;
2086 case APIC_BASE_MSR + (APIC_ICR >> 4):
2087 data = kvm_read_edx_eax(vcpu);
2088 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2089 kvm_skip_emulated_instruction(vcpu);
2090 ret = EXIT_FASTPATH_EXIT_HANDLED;
2093 case MSR_IA32_TSC_DEADLINE:
2094 data = kvm_read_edx_eax(vcpu);
2095 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2096 kvm_skip_emulated_instruction(vcpu);
2097 ret = EXIT_FASTPATH_REENTER_GUEST;
2104 if (ret != EXIT_FASTPATH_NONE)
2105 trace_kvm_msr_write(msr, data);
2109 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2112 * Adapt set_msr() to msr_io()'s calling convention
2114 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2116 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2119 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2121 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2124 #ifdef CONFIG_X86_64
2125 struct pvclock_clock {
2135 struct pvclock_gtod_data {
2138 struct pvclock_clock clock; /* extract of a clocksource struct */
2139 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2145 static struct pvclock_gtod_data pvclock_gtod_data;
2147 static void update_pvclock_gtod(struct timekeeper *tk)
2149 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2151 write_seqcount_begin(&vdata->seq);
2153 /* copy pvclock gtod data */
2154 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2155 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2156 vdata->clock.mask = tk->tkr_mono.mask;
2157 vdata->clock.mult = tk->tkr_mono.mult;
2158 vdata->clock.shift = tk->tkr_mono.shift;
2159 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2160 vdata->clock.offset = tk->tkr_mono.base;
2162 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2163 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2164 vdata->raw_clock.mask = tk->tkr_raw.mask;
2165 vdata->raw_clock.mult = tk->tkr_raw.mult;
2166 vdata->raw_clock.shift = tk->tkr_raw.shift;
2167 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2168 vdata->raw_clock.offset = tk->tkr_raw.base;
2170 vdata->wall_time_sec = tk->xtime_sec;
2172 vdata->offs_boot = tk->offs_boot;
2174 write_seqcount_end(&vdata->seq);
2177 static s64 get_kvmclock_base_ns(void)
2179 /* Count up from boot time, but with the frequency of the raw clock. */
2180 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2183 static s64 get_kvmclock_base_ns(void)
2185 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2186 return ktime_get_boottime_ns();
2190 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2194 struct pvclock_wall_clock wc;
2201 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2206 ++version; /* first time write, random junk */
2210 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2214 * The guest calculates current wall clock time by adding
2215 * system time (updated by kvm_guest_time_update below) to the
2216 * wall clock specified here. We do the reverse here.
2218 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
2220 wc.nsec = do_div(wall_nsec, 1000000000);
2221 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2222 wc.version = version;
2224 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2227 wc_sec_hi = wall_nsec >> 32;
2228 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2229 &wc_sec_hi, sizeof(wc_sec_hi));
2233 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2236 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2237 bool old_msr, bool host_initiated)
2239 struct kvm_arch *ka = &vcpu->kvm->arch;
2241 if (vcpu->vcpu_id == 0 && !host_initiated) {
2242 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2243 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2245 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2248 vcpu->arch.time = system_time;
2249 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2251 /* we verify if the enable bit is set... */
2252 vcpu->arch.pv_time_enabled = false;
2253 if (!(system_time & 1))
2256 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2257 &vcpu->arch.pv_time, system_time & ~1ULL,
2258 sizeof(struct pvclock_vcpu_time_info)))
2259 vcpu->arch.pv_time_enabled = true;
2264 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2266 do_shl32_div32(dividend, divisor);
2270 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2271 s8 *pshift, u32 *pmultiplier)
2279 scaled64 = scaled_hz;
2280 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2285 tps32 = (uint32_t)tps64;
2286 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2287 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2295 *pmultiplier = div_frac(scaled64, tps32);
2298 #ifdef CONFIG_X86_64
2299 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2302 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2303 static unsigned long max_tsc_khz;
2305 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2307 u64 v = (u64)khz * (1000000 + ppm);
2312 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2314 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2318 /* Guest TSC same frequency as host TSC? */
2320 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio);
2324 /* TSC scaling supported? */
2325 if (!kvm_has_tsc_control) {
2326 if (user_tsc_khz > tsc_khz) {
2327 vcpu->arch.tsc_catchup = 1;
2328 vcpu->arch.tsc_always_catchup = 1;
2331 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2336 /* TSC scaling required - calculate ratio */
2337 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2338 user_tsc_khz, tsc_khz);
2340 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2341 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2346 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2350 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2352 u32 thresh_lo, thresh_hi;
2353 int use_scaling = 0;
2355 /* tsc_khz can be zero if TSC calibration fails */
2356 if (user_tsc_khz == 0) {
2357 /* set tsc_scaling_ratio to a safe value */
2358 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio);
2362 /* Compute a scale to convert nanoseconds in TSC cycles */
2363 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2364 &vcpu->arch.virtual_tsc_shift,
2365 &vcpu->arch.virtual_tsc_mult);
2366 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2369 * Compute the variation in TSC rate which is acceptable
2370 * within the range of tolerance and decide if the
2371 * rate being applied is within that bounds of the hardware
2372 * rate. If so, no scaling or compensation need be done.
2374 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2375 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2376 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2377 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2380 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2383 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2385 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2386 vcpu->arch.virtual_tsc_mult,
2387 vcpu->arch.virtual_tsc_shift);
2388 tsc += vcpu->arch.this_tsc_write;
2392 #ifdef CONFIG_X86_64
2393 static inline int gtod_is_based_on_tsc(int mode)
2395 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2399 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2401 #ifdef CONFIG_X86_64
2403 struct kvm_arch *ka = &vcpu->kvm->arch;
2404 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2406 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2407 atomic_read(&vcpu->kvm->online_vcpus));
2410 * Once the masterclock is enabled, always perform request in
2411 * order to update it.
2413 * In order to enable masterclock, the host clocksource must be TSC
2414 * and the vcpus need to have matched TSCs. When that happens,
2415 * perform request to enable masterclock.
2417 if (ka->use_master_clock ||
2418 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2419 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2421 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2422 atomic_read(&vcpu->kvm->online_vcpus),
2423 ka->use_master_clock, gtod->clock.vclock_mode);
2428 * Multiply tsc by a fixed point number represented by ratio.
2430 * The most significant 64-N bits (mult) of ratio represent the
2431 * integral part of the fixed point number; the remaining N bits
2432 * (frac) represent the fractional part, ie. ratio represents a fixed
2433 * point number (mult + frac * 2^(-N)).
2435 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2437 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2439 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2442 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2446 if (ratio != kvm_default_tsc_scaling_ratio)
2447 _tsc = __scale_tsc(ratio, tsc);
2451 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2453 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2457 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2459 return target_tsc - tsc;
2462 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2464 return vcpu->arch.l1_tsc_offset +
2465 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2467 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2469 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2473 if (l2_multiplier == kvm_default_tsc_scaling_ratio)
2474 nested_offset = l1_offset;
2476 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2477 kvm_tsc_scaling_ratio_frac_bits);
2479 nested_offset += l2_offset;
2480 return nested_offset;
2482 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2484 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2486 if (l2_multiplier != kvm_default_tsc_scaling_ratio)
2487 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2488 kvm_tsc_scaling_ratio_frac_bits);
2490 return l1_multiplier;
2492 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2494 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2496 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2497 vcpu->arch.l1_tsc_offset,
2500 vcpu->arch.l1_tsc_offset = l1_offset;
2503 * If we are here because L1 chose not to trap WRMSR to TSC then
2504 * according to the spec this should set L1's TSC (as opposed to
2505 * setting L1's offset for L2).
2507 if (is_guest_mode(vcpu))
2508 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2510 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2511 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2513 vcpu->arch.tsc_offset = l1_offset;
2515 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset);
2518 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2520 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2522 /* Userspace is changing the multiplier while L2 is active */
2523 if (is_guest_mode(vcpu))
2524 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2526 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2528 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2530 if (kvm_has_tsc_control)
2531 static_call(kvm_x86_write_tsc_multiplier)(
2532 vcpu, vcpu->arch.tsc_scaling_ratio);
2535 static inline bool kvm_check_tsc_unstable(void)
2537 #ifdef CONFIG_X86_64
2539 * TSC is marked unstable when we're running on Hyper-V,
2540 * 'TSC page' clocksource is good.
2542 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2545 return check_tsc_unstable();
2549 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2550 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2553 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2554 u64 ns, bool matched)
2556 struct kvm *kvm = vcpu->kvm;
2558 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2561 * We also track th most recent recorded KHZ, write and time to
2562 * allow the matching interval to be extended at each write.
2564 kvm->arch.last_tsc_nsec = ns;
2565 kvm->arch.last_tsc_write = tsc;
2566 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2567 kvm->arch.last_tsc_offset = offset;
2569 vcpu->arch.last_guest_tsc = tsc;
2571 kvm_vcpu_write_tsc_offset(vcpu, offset);
2575 * We split periods of matched TSC writes into generations.
2576 * For each generation, we track the original measured
2577 * nanosecond time, offset, and write, so if TSCs are in
2578 * sync, we can match exact offset, and if not, we can match
2579 * exact software computation in compute_guest_tsc()
2581 * These values are tracked in kvm->arch.cur_xxx variables.
2583 kvm->arch.cur_tsc_generation++;
2584 kvm->arch.cur_tsc_nsec = ns;
2585 kvm->arch.cur_tsc_write = tsc;
2586 kvm->arch.cur_tsc_offset = offset;
2587 kvm->arch.nr_vcpus_matched_tsc = 0;
2588 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2589 kvm->arch.nr_vcpus_matched_tsc++;
2592 /* Keep track of which generation this VCPU has synchronized to */
2593 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2594 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2595 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2597 kvm_track_tsc_matching(vcpu);
2600 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2602 struct kvm *kvm = vcpu->kvm;
2603 u64 offset, ns, elapsed;
2604 unsigned long flags;
2605 bool matched = false;
2606 bool synchronizing = false;
2608 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2609 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2610 ns = get_kvmclock_base_ns();
2611 elapsed = ns - kvm->arch.last_tsc_nsec;
2613 if (vcpu->arch.virtual_tsc_khz) {
2616 * detection of vcpu initialization -- need to sync
2617 * with other vCPUs. This particularly helps to keep
2618 * kvm_clock stable after CPU hotplug
2620 synchronizing = true;
2622 u64 tsc_exp = kvm->arch.last_tsc_write +
2623 nsec_to_cycles(vcpu, elapsed);
2624 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2626 * Special case: TSC write with a small delta (1 second)
2627 * of virtual cycle time against real time is
2628 * interpreted as an attempt to synchronize the CPU.
2630 synchronizing = data < tsc_exp + tsc_hz &&
2631 data + tsc_hz > tsc_exp;
2636 * For a reliable TSC, we can match TSC offsets, and for an unstable
2637 * TSC, we add elapsed time in this computation. We could let the
2638 * compensation code attempt to catch up if we fall behind, but
2639 * it's better to try to match offsets from the beginning.
2641 if (synchronizing &&
2642 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2643 if (!kvm_check_tsc_unstable()) {
2644 offset = kvm->arch.cur_tsc_offset;
2646 u64 delta = nsec_to_cycles(vcpu, elapsed);
2648 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2653 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2654 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2657 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2660 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2661 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2664 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2666 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2667 WARN_ON(adjustment < 0);
2668 adjustment = kvm_scale_tsc((u64) adjustment,
2669 vcpu->arch.l1_tsc_scaling_ratio);
2670 adjust_tsc_offset_guest(vcpu, adjustment);
2673 #ifdef CONFIG_X86_64
2675 static u64 read_tsc(void)
2677 u64 ret = (u64)rdtsc_ordered();
2678 u64 last = pvclock_gtod_data.clock.cycle_last;
2680 if (likely(ret >= last))
2684 * GCC likes to generate cmov here, but this branch is extremely
2685 * predictable (it's just a function of time and the likely is
2686 * very likely) and there's a data dependence, so force GCC
2687 * to generate a branch instead. I don't barrier() because
2688 * we don't actually need a barrier, and if this function
2689 * ever gets inlined it will generate worse code.
2695 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2701 switch (clock->vclock_mode) {
2702 case VDSO_CLOCKMODE_HVCLOCK:
2703 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2705 if (tsc_pg_val != U64_MAX) {
2706 /* TSC page valid */
2707 *mode = VDSO_CLOCKMODE_HVCLOCK;
2708 v = (tsc_pg_val - clock->cycle_last) &
2711 /* TSC page invalid */
2712 *mode = VDSO_CLOCKMODE_NONE;
2715 case VDSO_CLOCKMODE_TSC:
2716 *mode = VDSO_CLOCKMODE_TSC;
2717 *tsc_timestamp = read_tsc();
2718 v = (*tsc_timestamp - clock->cycle_last) &
2722 *mode = VDSO_CLOCKMODE_NONE;
2725 if (*mode == VDSO_CLOCKMODE_NONE)
2726 *tsc_timestamp = v = 0;
2728 return v * clock->mult;
2731 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2733 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2739 seq = read_seqcount_begin(>od->seq);
2740 ns = gtod->raw_clock.base_cycles;
2741 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2742 ns >>= gtod->raw_clock.shift;
2743 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2744 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2750 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2752 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2758 seq = read_seqcount_begin(>od->seq);
2759 ts->tv_sec = gtod->wall_time_sec;
2760 ns = gtod->clock.base_cycles;
2761 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2762 ns >>= gtod->clock.shift;
2763 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2765 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2771 /* returns true if host is using TSC based clocksource */
2772 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2774 /* checked again under seqlock below */
2775 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2778 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2782 /* returns true if host is using TSC based clocksource */
2783 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2786 /* checked again under seqlock below */
2787 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2790 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2796 * Assuming a stable TSC across physical CPUS, and a stable TSC
2797 * across virtual CPUs, the following condition is possible.
2798 * Each numbered line represents an event visible to both
2799 * CPUs at the next numbered event.
2801 * "timespecX" represents host monotonic time. "tscX" represents
2804 * VCPU0 on CPU0 | VCPU1 on CPU1
2806 * 1. read timespec0,tsc0
2807 * 2. | timespec1 = timespec0 + N
2809 * 3. transition to guest | transition to guest
2810 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2811 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2812 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2814 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2817 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2819 * - 0 < N - M => M < N
2821 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2822 * always the case (the difference between two distinct xtime instances
2823 * might be smaller then the difference between corresponding TSC reads,
2824 * when updating guest vcpus pvclock areas).
2826 * To avoid that problem, do not allow visibility of distinct
2827 * system_timestamp/tsc_timestamp values simultaneously: use a master
2828 * copy of host monotonic time values. Update that master copy
2831 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2835 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2837 #ifdef CONFIG_X86_64
2838 struct kvm_arch *ka = &kvm->arch;
2840 bool host_tsc_clocksource, vcpus_matched;
2842 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2843 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2844 atomic_read(&kvm->online_vcpus));
2847 * If the host uses TSC clock, then passthrough TSC as stable
2850 host_tsc_clocksource = kvm_get_time_and_clockread(
2851 &ka->master_kernel_ns,
2852 &ka->master_cycle_now);
2854 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2855 && !ka->backwards_tsc_observed
2856 && !ka->boot_vcpu_runs_old_kvmclock;
2858 if (ka->use_master_clock)
2859 atomic_set(&kvm_guest_has_master_clock, 1);
2861 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2862 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2867 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2869 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2872 static void __kvm_start_pvclock_update(struct kvm *kvm)
2874 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
2875 write_seqcount_begin(&kvm->arch.pvclock_sc);
2878 static void kvm_start_pvclock_update(struct kvm *kvm)
2880 kvm_make_mclock_inprogress_request(kvm);
2882 /* no guest entries from this point */
2883 __kvm_start_pvclock_update(kvm);
2886 static void kvm_end_pvclock_update(struct kvm *kvm)
2888 struct kvm_arch *ka = &kvm->arch;
2889 struct kvm_vcpu *vcpu;
2892 write_seqcount_end(&ka->pvclock_sc);
2893 raw_spin_unlock_irq(&ka->tsc_write_lock);
2894 kvm_for_each_vcpu(i, vcpu, kvm)
2895 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2897 /* guest entries allowed */
2898 kvm_for_each_vcpu(i, vcpu, kvm)
2899 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2902 static void kvm_update_masterclock(struct kvm *kvm)
2904 kvm_hv_invalidate_tsc_page(kvm);
2905 kvm_start_pvclock_update(kvm);
2906 pvclock_update_vm_gtod_copy(kvm);
2907 kvm_end_pvclock_update(kvm);
2910 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
2911 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2913 struct kvm_arch *ka = &kvm->arch;
2914 struct pvclock_vcpu_time_info hv_clock;
2916 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2920 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) {
2921 #ifdef CONFIG_X86_64
2922 struct timespec64 ts;
2924 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
2925 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
2926 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
2929 data->host_tsc = rdtsc();
2931 data->flags |= KVM_CLOCK_TSC_STABLE;
2932 hv_clock.tsc_timestamp = ka->master_cycle_now;
2933 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2934 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2935 &hv_clock.tsc_shift,
2936 &hv_clock.tsc_to_system_mul);
2937 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
2939 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
2945 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2947 struct kvm_arch *ka = &kvm->arch;
2951 seq = read_seqcount_begin(&ka->pvclock_sc);
2952 __get_kvmclock(kvm, data);
2953 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
2956 u64 get_kvmclock_ns(struct kvm *kvm)
2958 struct kvm_clock_data data;
2960 get_kvmclock(kvm, &data);
2964 static void kvm_setup_pvclock_page(struct kvm_vcpu *v,
2965 struct gfn_to_hva_cache *cache,
2966 unsigned int offset)
2968 struct kvm_vcpu_arch *vcpu = &v->arch;
2969 struct pvclock_vcpu_time_info guest_hv_clock;
2971 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache,
2972 &guest_hv_clock, offset, sizeof(guest_hv_clock))))
2975 /* This VCPU is paused, but it's legal for a guest to read another
2976 * VCPU's kvmclock, so we really have to follow the specification where
2977 * it says that version is odd if data is being modified, and even after
2980 * Version field updates must be kept separate. This is because
2981 * kvm_write_guest_cached might use a "rep movs" instruction, and
2982 * writes within a string instruction are weakly ordered. So there
2983 * are three writes overall.
2985 * As a small optimization, only write the version field in the first
2986 * and third write. The vcpu->pv_time cache is still valid, because the
2987 * version field is the first in the struct.
2989 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2991 if (guest_hv_clock.version & 1)
2992 ++guest_hv_clock.version; /* first time write, random junk */
2994 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2995 kvm_write_guest_offset_cached(v->kvm, cache,
2996 &vcpu->hv_clock, offset,
2997 sizeof(vcpu->hv_clock.version));
3001 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3002 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
3004 if (vcpu->pvclock_set_guest_stopped_request) {
3005 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3006 vcpu->pvclock_set_guest_stopped_request = false;
3009 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3011 kvm_write_guest_offset_cached(v->kvm, cache,
3012 &vcpu->hv_clock, offset,
3013 sizeof(vcpu->hv_clock));
3017 vcpu->hv_clock.version++;
3018 kvm_write_guest_offset_cached(v->kvm, cache,
3019 &vcpu->hv_clock, offset,
3020 sizeof(vcpu->hv_clock.version));
3023 static int kvm_guest_time_update(struct kvm_vcpu *v)
3025 unsigned long flags, tgt_tsc_khz;
3027 struct kvm_vcpu_arch *vcpu = &v->arch;
3028 struct kvm_arch *ka = &v->kvm->arch;
3030 u64 tsc_timestamp, host_tsc;
3032 bool use_master_clock;
3038 * If the host uses TSC clock, then passthrough TSC as stable
3042 seq = read_seqcount_begin(&ka->pvclock_sc);
3043 use_master_clock = ka->use_master_clock;
3044 if (use_master_clock) {
3045 host_tsc = ka->master_cycle_now;
3046 kernel_ns = ka->master_kernel_ns;
3048 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3050 /* Keep irq disabled to prevent changes to the clock */
3051 local_irq_save(flags);
3052 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
3053 if (unlikely(tgt_tsc_khz == 0)) {
3054 local_irq_restore(flags);
3055 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3058 if (!use_master_clock) {
3060 kernel_ns = get_kvmclock_base_ns();
3063 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3066 * We may have to catch up the TSC to match elapsed wall clock
3067 * time for two reasons, even if kvmclock is used.
3068 * 1) CPU could have been running below the maximum TSC rate
3069 * 2) Broken TSC compensation resets the base at each VCPU
3070 * entry to avoid unknown leaps of TSC even when running
3071 * again on the same CPU. This may cause apparent elapsed
3072 * time to disappear, and the guest to stand still or run
3075 if (vcpu->tsc_catchup) {
3076 u64 tsc = compute_guest_tsc(v, kernel_ns);
3077 if (tsc > tsc_timestamp) {
3078 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3079 tsc_timestamp = tsc;
3083 local_irq_restore(flags);
3085 /* With all the info we got, fill in the values */
3087 if (kvm_has_tsc_control)
3088 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3089 v->arch.l1_tsc_scaling_ratio);
3091 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3092 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3093 &vcpu->hv_clock.tsc_shift,
3094 &vcpu->hv_clock.tsc_to_system_mul);
3095 vcpu->hw_tsc_khz = tgt_tsc_khz;
3098 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3099 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3100 vcpu->last_guest_tsc = tsc_timestamp;
3102 /* If the host uses TSC clocksource, then it is stable */
3104 if (use_master_clock)
3105 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3107 vcpu->hv_clock.flags = pvclock_flags;
3109 if (vcpu->pv_time_enabled)
3110 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0);
3111 if (vcpu->xen.vcpu_info_set)
3112 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache,
3113 offsetof(struct compat_vcpu_info, time));
3114 if (vcpu->xen.vcpu_time_info_set)
3115 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0);
3117 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3122 * kvmclock updates which are isolated to a given vcpu, such as
3123 * vcpu->cpu migration, should not allow system_timestamp from
3124 * the rest of the vcpus to remain static. Otherwise ntp frequency
3125 * correction applies to one vcpu's system_timestamp but not
3128 * So in those cases, request a kvmclock update for all vcpus.
3129 * We need to rate-limit these requests though, as they can
3130 * considerably slow guests that have a large number of vcpus.
3131 * The time for a remote vcpu to update its kvmclock is bound
3132 * by the delay we use to rate-limit the updates.
3135 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3137 static void kvmclock_update_fn(struct work_struct *work)
3140 struct delayed_work *dwork = to_delayed_work(work);
3141 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3142 kvmclock_update_work);
3143 struct kvm *kvm = container_of(ka, struct kvm, arch);
3144 struct kvm_vcpu *vcpu;
3146 kvm_for_each_vcpu(i, vcpu, kvm) {
3147 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3148 kvm_vcpu_kick(vcpu);
3152 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3154 struct kvm *kvm = v->kvm;
3156 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3157 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3158 KVMCLOCK_UPDATE_DELAY);
3161 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3163 static void kvmclock_sync_fn(struct work_struct *work)
3165 struct delayed_work *dwork = to_delayed_work(work);
3166 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3167 kvmclock_sync_work);
3168 struct kvm *kvm = container_of(ka, struct kvm, arch);
3170 if (!kvmclock_periodic_sync)
3173 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3174 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3175 KVMCLOCK_SYNC_PERIOD);
3179 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3181 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3183 /* McStatusWrEn enabled? */
3184 if (guest_cpuid_is_amd_or_hygon(vcpu))
3185 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3190 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3192 u64 mcg_cap = vcpu->arch.mcg_cap;
3193 unsigned bank_num = mcg_cap & 0xff;
3194 u32 msr = msr_info->index;
3195 u64 data = msr_info->data;
3198 case MSR_IA32_MCG_STATUS:
3199 vcpu->arch.mcg_status = data;
3201 case MSR_IA32_MCG_CTL:
3202 if (!(mcg_cap & MCG_CTL_P) &&
3203 (data || !msr_info->host_initiated))
3205 if (data != 0 && data != ~(u64)0)
3207 vcpu->arch.mcg_ctl = data;
3210 if (msr >= MSR_IA32_MC0_CTL &&
3211 msr < MSR_IA32_MCx_CTL(bank_num)) {
3212 u32 offset = array_index_nospec(
3213 msr - MSR_IA32_MC0_CTL,
3214 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3216 /* only 0 or all 1s can be written to IA32_MCi_CTL
3217 * some Linux kernels though clear bit 10 in bank 4 to
3218 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
3219 * this to avoid an uncatched #GP in the guest
3221 if ((offset & 0x3) == 0 &&
3222 data != 0 && (data | (1 << 10)) != ~(u64)0)
3226 if (!msr_info->host_initiated &&
3227 (offset & 0x3) == 1 && data != 0) {
3228 if (!can_set_mci_status(vcpu))
3232 vcpu->arch.mce_banks[offset] = data;
3240 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3242 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3244 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3247 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3249 gpa_t gpa = data & ~0x3f;
3251 /* Bits 4:5 are reserved, Should be zero */
3255 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3256 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3259 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3260 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3263 if (!lapic_in_kernel(vcpu))
3264 return data ? 1 : 0;
3266 vcpu->arch.apf.msr_en_val = data;
3268 if (!kvm_pv_async_pf_enabled(vcpu)) {
3269 kvm_clear_async_pf_completion_queue(vcpu);
3270 kvm_async_pf_hash_reset(vcpu);
3274 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3278 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3279 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3281 kvm_async_pf_wakeup_all(vcpu);
3286 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3288 /* Bits 8-63 are reserved */
3292 if (!lapic_in_kernel(vcpu))
3295 vcpu->arch.apf.msr_int_val = data;
3297 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3302 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3304 vcpu->arch.pv_time_enabled = false;
3305 vcpu->arch.time = 0;
3308 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3310 ++vcpu->stat.tlb_flush;
3311 static_call(kvm_x86_flush_tlb_all)(vcpu);
3314 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3316 ++vcpu->stat.tlb_flush;
3320 * A TLB flush on behalf of the guest is equivalent to
3321 * INVPCID(all), toggling CR4.PGE, etc., which requires
3322 * a forced sync of the shadow page tables. Ensure all the
3323 * roots are synced and the guest TLB in hardware is clean.
3325 kvm_mmu_sync_roots(vcpu);
3326 kvm_mmu_sync_prev_roots(vcpu);
3329 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3333 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3335 ++vcpu->stat.tlb_flush;
3336 static_call(kvm_x86_flush_tlb_current)(vcpu);
3340 * Service "local" TLB flush requests, which are specific to the current MMU
3341 * context. In addition to the generic event handling in vcpu_enter_guest(),
3342 * TLB flushes that are targeted at an MMU context also need to be serviced
3343 * prior before nested VM-Enter/VM-Exit.
3345 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3347 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3348 kvm_vcpu_flush_tlb_current(vcpu);
3350 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3351 kvm_vcpu_flush_tlb_guest(vcpu);
3353 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3355 static void record_steal_time(struct kvm_vcpu *vcpu)
3357 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3358 struct kvm_steal_time __user *st;
3359 struct kvm_memslots *slots;
3363 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3364 kvm_xen_runstate_set_running(vcpu);
3368 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3371 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3374 slots = kvm_memslots(vcpu->kvm);
3376 if (unlikely(slots->generation != ghc->generation ||
3377 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3378 gfn_t gfn = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3380 /* We rely on the fact that it fits in a single page. */
3381 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3383 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gfn, sizeof(*st)) ||
3384 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3388 st = (struct kvm_steal_time __user *)ghc->hva;
3390 * Doing a TLB flush here, on the guest's behalf, can avoid
3393 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3394 u8 st_preempted = 0;
3397 if (!user_access_begin(st, sizeof(*st)))
3400 asm volatile("1: xchgb %0, %2\n"
3403 _ASM_EXTABLE_UA(1b, 2b)
3404 : "+q" (st_preempted),
3406 "+m" (st->preempted));
3412 vcpu->arch.st.preempted = 0;
3414 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3415 st_preempted & KVM_VCPU_FLUSH_TLB);
3416 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3417 kvm_vcpu_flush_tlb_guest(vcpu);
3419 if (!user_access_begin(st, sizeof(*st)))
3422 if (!user_access_begin(st, sizeof(*st)))
3425 unsafe_put_user(0, &st->preempted, out);
3426 vcpu->arch.st.preempted = 0;
3429 unsafe_get_user(version, &st->version, out);
3431 version += 1; /* first time write, random junk */
3434 unsafe_put_user(version, &st->version, out);
3438 unsafe_get_user(steal, &st->steal, out);
3439 steal += current->sched_info.run_delay -
3440 vcpu->arch.st.last_steal;
3441 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3442 unsafe_put_user(steal, &st->steal, out);
3445 unsafe_put_user(version, &st->version, out);
3450 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3453 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3456 u32 msr = msr_info->index;
3457 u64 data = msr_info->data;
3459 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3460 return kvm_xen_write_hypercall_page(vcpu, data);
3463 case MSR_AMD64_NB_CFG:
3464 case MSR_IA32_UCODE_WRITE:
3465 case MSR_VM_HSAVE_PA:
3466 case MSR_AMD64_PATCH_LOADER:
3467 case MSR_AMD64_BU_CFG2:
3468 case MSR_AMD64_DC_CFG:
3469 case MSR_F15H_EX_CFG:
3472 case MSR_IA32_UCODE_REV:
3473 if (msr_info->host_initiated)
3474 vcpu->arch.microcode_version = data;
3476 case MSR_IA32_ARCH_CAPABILITIES:
3477 if (!msr_info->host_initiated)
3479 vcpu->arch.arch_capabilities = data;
3481 case MSR_IA32_PERF_CAPABILITIES: {
3482 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3484 if (!msr_info->host_initiated)
3486 if (kvm_get_msr_feature(&msr_ent))
3488 if (data & ~msr_ent.data)
3491 vcpu->arch.perf_capabilities = data;
3496 return set_efer(vcpu, msr_info);
3498 data &= ~(u64)0x40; /* ignore flush filter disable */
3499 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3500 data &= ~(u64)0x8; /* ignore TLB cache disable */
3502 /* Handle McStatusWrEn */
3503 if (data == BIT_ULL(18)) {
3504 vcpu->arch.msr_hwcr = data;
3505 } else if (data != 0) {
3506 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3511 case MSR_FAM10H_MMIO_CONF_BASE:
3513 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3518 case 0x200 ... 0x2ff:
3519 return kvm_mtrr_set_msr(vcpu, msr, data);
3520 case MSR_IA32_APICBASE:
3521 return kvm_set_apic_base(vcpu, msr_info);
3522 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3523 return kvm_x2apic_msr_write(vcpu, msr, data);
3524 case MSR_IA32_TSC_DEADLINE:
3525 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3527 case MSR_IA32_TSC_ADJUST:
3528 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3529 if (!msr_info->host_initiated) {
3530 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3531 adjust_tsc_offset_guest(vcpu, adj);
3532 /* Before back to guest, tsc_timestamp must be adjusted
3533 * as well, otherwise guest's percpu pvclock time could jump.
3535 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3537 vcpu->arch.ia32_tsc_adjust_msr = data;
3540 case MSR_IA32_MISC_ENABLE:
3541 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3542 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3543 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3545 vcpu->arch.ia32_misc_enable_msr = data;
3546 kvm_update_cpuid_runtime(vcpu);
3548 vcpu->arch.ia32_misc_enable_msr = data;
3551 case MSR_IA32_SMBASE:
3552 if (!msr_info->host_initiated)
3554 vcpu->arch.smbase = data;
3556 case MSR_IA32_POWER_CTL:
3557 vcpu->arch.msr_ia32_power_ctl = data;
3560 if (msr_info->host_initiated) {
3561 kvm_synchronize_tsc(vcpu, data);
3563 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3564 adjust_tsc_offset_guest(vcpu, adj);
3565 vcpu->arch.ia32_tsc_adjust_msr += adj;
3569 if (!msr_info->host_initiated &&
3570 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3573 * KVM supports exposing PT to the guest, but does not support
3574 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3575 * XSAVES/XRSTORS to save/restore PT MSRs.
3577 if (data & ~supported_xss)
3579 vcpu->arch.ia32_xss = data;
3580 kvm_update_cpuid_runtime(vcpu);
3583 if (!msr_info->host_initiated)
3585 vcpu->arch.smi_count = data;
3587 case MSR_KVM_WALL_CLOCK_NEW:
3588 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3591 vcpu->kvm->arch.wall_clock = data;
3592 kvm_write_wall_clock(vcpu->kvm, data, 0);
3594 case MSR_KVM_WALL_CLOCK:
3595 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3598 vcpu->kvm->arch.wall_clock = data;
3599 kvm_write_wall_clock(vcpu->kvm, data, 0);
3601 case MSR_KVM_SYSTEM_TIME_NEW:
3602 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3605 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3607 case MSR_KVM_SYSTEM_TIME:
3608 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3611 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3613 case MSR_KVM_ASYNC_PF_EN:
3614 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3617 if (kvm_pv_enable_async_pf(vcpu, data))
3620 case MSR_KVM_ASYNC_PF_INT:
3621 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3624 if (kvm_pv_enable_async_pf_int(vcpu, data))
3627 case MSR_KVM_ASYNC_PF_ACK:
3628 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3631 vcpu->arch.apf.pageready_pending = false;
3632 kvm_check_async_pf_completion(vcpu);
3635 case MSR_KVM_STEAL_TIME:
3636 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3639 if (unlikely(!sched_info_on()))
3642 if (data & KVM_STEAL_RESERVED_MASK)
3645 vcpu->arch.st.msr_val = data;
3647 if (!(data & KVM_MSR_ENABLED))
3650 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3653 case MSR_KVM_PV_EOI_EN:
3654 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3657 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
3661 case MSR_KVM_POLL_CONTROL:
3662 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3665 /* only enable bit supported */
3666 if (data & (-1ULL << 1))
3669 vcpu->arch.msr_kvm_poll_control = data;
3672 case MSR_IA32_MCG_CTL:
3673 case MSR_IA32_MCG_STATUS:
3674 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3675 return set_msr_mce(vcpu, msr_info);
3677 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3678 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3681 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3682 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3683 if (kvm_pmu_is_valid_msr(vcpu, msr))
3684 return kvm_pmu_set_msr(vcpu, msr_info);
3686 if (pr || data != 0)
3687 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3688 "0x%x data 0x%llx\n", msr, data);
3690 case MSR_K7_CLK_CTL:
3692 * Ignore all writes to this no longer documented MSR.
3693 * Writes are only relevant for old K7 processors,
3694 * all pre-dating SVM, but a recommended workaround from
3695 * AMD for these chips. It is possible to specify the
3696 * affected processor models on the command line, hence
3697 * the need to ignore the workaround.
3700 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3701 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3702 case HV_X64_MSR_SYNDBG_OPTIONS:
3703 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3704 case HV_X64_MSR_CRASH_CTL:
3705 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3706 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3707 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3708 case HV_X64_MSR_TSC_EMULATION_STATUS:
3709 return kvm_hv_set_msr_common(vcpu, msr, data,
3710 msr_info->host_initiated);
3711 case MSR_IA32_BBL_CR_CTL3:
3712 /* Drop writes to this legacy MSR -- see rdmsr
3713 * counterpart for further detail.
3715 if (report_ignored_msrs)
3716 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3719 case MSR_AMD64_OSVW_ID_LENGTH:
3720 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3722 vcpu->arch.osvw.length = data;
3724 case MSR_AMD64_OSVW_STATUS:
3725 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3727 vcpu->arch.osvw.status = data;
3729 case MSR_PLATFORM_INFO:
3730 if (!msr_info->host_initiated ||
3731 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3732 cpuid_fault_enabled(vcpu)))
3734 vcpu->arch.msr_platform_info = data;
3736 case MSR_MISC_FEATURES_ENABLES:
3737 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3738 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3739 !supports_cpuid_fault(vcpu)))
3741 vcpu->arch.msr_misc_features_enables = data;
3743 #ifdef CONFIG_X86_64
3745 if (!msr_info->host_initiated &&
3746 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3749 if (data & ~kvm_guest_supported_xfd(vcpu))
3752 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
3754 case MSR_IA32_XFD_ERR:
3755 if (!msr_info->host_initiated &&
3756 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3759 if (data & ~kvm_guest_supported_xfd(vcpu))
3762 vcpu->arch.guest_fpu.xfd_err = data;
3766 if (kvm_pmu_is_valid_msr(vcpu, msr))
3767 return kvm_pmu_set_msr(vcpu, msr_info);
3768 return KVM_MSR_RET_INVALID;
3772 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3774 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3777 u64 mcg_cap = vcpu->arch.mcg_cap;
3778 unsigned bank_num = mcg_cap & 0xff;
3781 case MSR_IA32_P5_MC_ADDR:
3782 case MSR_IA32_P5_MC_TYPE:
3785 case MSR_IA32_MCG_CAP:
3786 data = vcpu->arch.mcg_cap;
3788 case MSR_IA32_MCG_CTL:
3789 if (!(mcg_cap & MCG_CTL_P) && !host)
3791 data = vcpu->arch.mcg_ctl;
3793 case MSR_IA32_MCG_STATUS:
3794 data = vcpu->arch.mcg_status;
3797 if (msr >= MSR_IA32_MC0_CTL &&
3798 msr < MSR_IA32_MCx_CTL(bank_num)) {
3799 u32 offset = array_index_nospec(
3800 msr - MSR_IA32_MC0_CTL,
3801 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3803 data = vcpu->arch.mce_banks[offset];
3812 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3814 switch (msr_info->index) {
3815 case MSR_IA32_PLATFORM_ID:
3816 case MSR_IA32_EBL_CR_POWERON:
3817 case MSR_IA32_LASTBRANCHFROMIP:
3818 case MSR_IA32_LASTBRANCHTOIP:
3819 case MSR_IA32_LASTINTFROMIP:
3820 case MSR_IA32_LASTINTTOIP:
3821 case MSR_AMD64_SYSCFG:
3822 case MSR_K8_TSEG_ADDR:
3823 case MSR_K8_TSEG_MASK:
3824 case MSR_VM_HSAVE_PA:
3825 case MSR_K8_INT_PENDING_MSG:
3826 case MSR_AMD64_NB_CFG:
3827 case MSR_FAM10H_MMIO_CONF_BASE:
3828 case MSR_AMD64_BU_CFG2:
3829 case MSR_IA32_PERF_CTL:
3830 case MSR_AMD64_DC_CFG:
3831 case MSR_F15H_EX_CFG:
3833 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3834 * limit) MSRs. Just return 0, as we do not want to expose the host
3835 * data here. Do not conditionalize this on CPUID, as KVM does not do
3836 * so for existing CPU-specific MSRs.
3838 case MSR_RAPL_POWER_UNIT:
3839 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3840 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3841 case MSR_PKG_ENERGY_STATUS: /* Total package */
3842 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3845 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3846 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3847 return kvm_pmu_get_msr(vcpu, msr_info);
3848 if (!msr_info->host_initiated)
3852 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3853 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3854 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3855 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3856 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3857 return kvm_pmu_get_msr(vcpu, msr_info);
3860 case MSR_IA32_UCODE_REV:
3861 msr_info->data = vcpu->arch.microcode_version;
3863 case MSR_IA32_ARCH_CAPABILITIES:
3864 if (!msr_info->host_initiated &&
3865 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3867 msr_info->data = vcpu->arch.arch_capabilities;
3869 case MSR_IA32_PERF_CAPABILITIES:
3870 if (!msr_info->host_initiated &&
3871 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3873 msr_info->data = vcpu->arch.perf_capabilities;
3875 case MSR_IA32_POWER_CTL:
3876 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3878 case MSR_IA32_TSC: {
3880 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3881 * even when not intercepted. AMD manual doesn't explicitly
3882 * state this but appears to behave the same.
3884 * On userspace reads and writes, however, we unconditionally
3885 * return L1's TSC value to ensure backwards-compatible
3886 * behavior for migration.
3890 if (msr_info->host_initiated) {
3891 offset = vcpu->arch.l1_tsc_offset;
3892 ratio = vcpu->arch.l1_tsc_scaling_ratio;
3894 offset = vcpu->arch.tsc_offset;
3895 ratio = vcpu->arch.tsc_scaling_ratio;
3898 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
3902 case 0x200 ... 0x2ff:
3903 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3904 case 0xcd: /* fsb frequency */
3908 * MSR_EBC_FREQUENCY_ID
3909 * Conservative value valid for even the basic CPU models.
3910 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3911 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3912 * and 266MHz for model 3, or 4. Set Core Clock
3913 * Frequency to System Bus Frequency Ratio to 1 (bits
3914 * 31:24) even though these are only valid for CPU
3915 * models > 2, however guests may end up dividing or
3916 * multiplying by zero otherwise.
3918 case MSR_EBC_FREQUENCY_ID:
3919 msr_info->data = 1 << 24;
3921 case MSR_IA32_APICBASE:
3922 msr_info->data = kvm_get_apic_base(vcpu);
3924 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3925 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3926 case MSR_IA32_TSC_DEADLINE:
3927 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3929 case MSR_IA32_TSC_ADJUST:
3930 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3932 case MSR_IA32_MISC_ENABLE:
3933 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3935 case MSR_IA32_SMBASE:
3936 if (!msr_info->host_initiated)
3938 msr_info->data = vcpu->arch.smbase;
3941 msr_info->data = vcpu->arch.smi_count;
3943 case MSR_IA32_PERF_STATUS:
3944 /* TSC increment by tick */
3945 msr_info->data = 1000ULL;
3946 /* CPU multiplier */
3947 msr_info->data |= (((uint64_t)4ULL) << 40);
3950 msr_info->data = vcpu->arch.efer;
3952 case MSR_KVM_WALL_CLOCK:
3953 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3956 msr_info->data = vcpu->kvm->arch.wall_clock;
3958 case MSR_KVM_WALL_CLOCK_NEW:
3959 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3962 msr_info->data = vcpu->kvm->arch.wall_clock;
3964 case MSR_KVM_SYSTEM_TIME:
3965 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3968 msr_info->data = vcpu->arch.time;
3970 case MSR_KVM_SYSTEM_TIME_NEW:
3971 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3974 msr_info->data = vcpu->arch.time;
3976 case MSR_KVM_ASYNC_PF_EN:
3977 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3980 msr_info->data = vcpu->arch.apf.msr_en_val;
3982 case MSR_KVM_ASYNC_PF_INT:
3983 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3986 msr_info->data = vcpu->arch.apf.msr_int_val;
3988 case MSR_KVM_ASYNC_PF_ACK:
3989 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3994 case MSR_KVM_STEAL_TIME:
3995 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3998 msr_info->data = vcpu->arch.st.msr_val;
4000 case MSR_KVM_PV_EOI_EN:
4001 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4004 msr_info->data = vcpu->arch.pv_eoi.msr_val;
4006 case MSR_KVM_POLL_CONTROL:
4007 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4010 msr_info->data = vcpu->arch.msr_kvm_poll_control;
4012 case MSR_IA32_P5_MC_ADDR:
4013 case MSR_IA32_P5_MC_TYPE:
4014 case MSR_IA32_MCG_CAP:
4015 case MSR_IA32_MCG_CTL:
4016 case MSR_IA32_MCG_STATUS:
4017 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4018 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4019 msr_info->host_initiated);
4021 if (!msr_info->host_initiated &&
4022 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4024 msr_info->data = vcpu->arch.ia32_xss;
4026 case MSR_K7_CLK_CTL:
4028 * Provide expected ramp-up count for K7. All other
4029 * are set to zero, indicating minimum divisors for
4032 * This prevents guest kernels on AMD host with CPU
4033 * type 6, model 8 and higher from exploding due to
4034 * the rdmsr failing.
4036 msr_info->data = 0x20000000;
4038 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4039 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4040 case HV_X64_MSR_SYNDBG_OPTIONS:
4041 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4042 case HV_X64_MSR_CRASH_CTL:
4043 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4044 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4045 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4046 case HV_X64_MSR_TSC_EMULATION_STATUS:
4047 return kvm_hv_get_msr_common(vcpu,
4048 msr_info->index, &msr_info->data,
4049 msr_info->host_initiated);
4050 case MSR_IA32_BBL_CR_CTL3:
4051 /* This legacy MSR exists but isn't fully documented in current
4052 * silicon. It is however accessed by winxp in very narrow
4053 * scenarios where it sets bit #19, itself documented as
4054 * a "reserved" bit. Best effort attempt to source coherent
4055 * read data here should the balance of the register be
4056 * interpreted by the guest:
4058 * L2 cache control register 3: 64GB range, 256KB size,
4059 * enabled, latency 0x1, configured
4061 msr_info->data = 0xbe702111;
4063 case MSR_AMD64_OSVW_ID_LENGTH:
4064 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4066 msr_info->data = vcpu->arch.osvw.length;
4068 case MSR_AMD64_OSVW_STATUS:
4069 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4071 msr_info->data = vcpu->arch.osvw.status;
4073 case MSR_PLATFORM_INFO:
4074 if (!msr_info->host_initiated &&
4075 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4077 msr_info->data = vcpu->arch.msr_platform_info;
4079 case MSR_MISC_FEATURES_ENABLES:
4080 msr_info->data = vcpu->arch.msr_misc_features_enables;
4083 msr_info->data = vcpu->arch.msr_hwcr;
4085 #ifdef CONFIG_X86_64
4087 if (!msr_info->host_initiated &&
4088 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4091 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4093 case MSR_IA32_XFD_ERR:
4094 if (!msr_info->host_initiated &&
4095 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4098 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4102 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4103 return kvm_pmu_get_msr(vcpu, msr_info);
4104 return KVM_MSR_RET_INVALID;
4108 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4111 * Read or write a bunch of msrs. All parameters are kernel addresses.
4113 * @return number of msrs set successfully.
4115 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4116 struct kvm_msr_entry *entries,
4117 int (*do_msr)(struct kvm_vcpu *vcpu,
4118 unsigned index, u64 *data))
4122 for (i = 0; i < msrs->nmsrs; ++i)
4123 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4130 * Read or write a bunch of msrs. Parameters are user addresses.
4132 * @return number of msrs set successfully.
4134 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4135 int (*do_msr)(struct kvm_vcpu *vcpu,
4136 unsigned index, u64 *data),
4139 struct kvm_msrs msrs;
4140 struct kvm_msr_entry *entries;
4145 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4149 if (msrs.nmsrs >= MAX_IO_MSRS)
4152 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4153 entries = memdup_user(user_msrs->entries, size);
4154 if (IS_ERR(entries)) {
4155 r = PTR_ERR(entries);
4159 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
4164 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4175 static inline bool kvm_can_mwait_in_guest(void)
4177 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4178 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4179 boot_cpu_has(X86_FEATURE_ARAT);
4182 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4183 struct kvm_cpuid2 __user *cpuid_arg)
4185 struct kvm_cpuid2 cpuid;
4189 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4192 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4197 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4203 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4208 case KVM_CAP_IRQCHIP:
4210 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4211 case KVM_CAP_SET_TSS_ADDR:
4212 case KVM_CAP_EXT_CPUID:
4213 case KVM_CAP_EXT_EMUL_CPUID:
4214 case KVM_CAP_CLOCKSOURCE:
4216 case KVM_CAP_NOP_IO_DELAY:
4217 case KVM_CAP_MP_STATE:
4218 case KVM_CAP_SYNC_MMU:
4219 case KVM_CAP_USER_NMI:
4220 case KVM_CAP_REINJECT_CONTROL:
4221 case KVM_CAP_IRQ_INJECT_STATUS:
4222 case KVM_CAP_IOEVENTFD:
4223 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4225 case KVM_CAP_PIT_STATE2:
4226 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4227 case KVM_CAP_VCPU_EVENTS:
4228 case KVM_CAP_HYPERV:
4229 case KVM_CAP_HYPERV_VAPIC:
4230 case KVM_CAP_HYPERV_SPIN:
4231 case KVM_CAP_HYPERV_SYNIC:
4232 case KVM_CAP_HYPERV_SYNIC2:
4233 case KVM_CAP_HYPERV_VP_INDEX:
4234 case KVM_CAP_HYPERV_EVENTFD:
4235 case KVM_CAP_HYPERV_TLBFLUSH:
4236 case KVM_CAP_HYPERV_SEND_IPI:
4237 case KVM_CAP_HYPERV_CPUID:
4238 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4239 case KVM_CAP_SYS_HYPERV_CPUID:
4240 case KVM_CAP_PCI_SEGMENT:
4241 case KVM_CAP_DEBUGREGS:
4242 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4244 case KVM_CAP_ASYNC_PF:
4245 case KVM_CAP_ASYNC_PF_INT:
4246 case KVM_CAP_GET_TSC_KHZ:
4247 case KVM_CAP_KVMCLOCK_CTRL:
4248 case KVM_CAP_READONLY_MEM:
4249 case KVM_CAP_HYPERV_TIME:
4250 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4251 case KVM_CAP_TSC_DEADLINE_TIMER:
4252 case KVM_CAP_DISABLE_QUIRKS:
4253 case KVM_CAP_SET_BOOT_CPU_ID:
4254 case KVM_CAP_SPLIT_IRQCHIP:
4255 case KVM_CAP_IMMEDIATE_EXIT:
4256 case KVM_CAP_PMU_EVENT_FILTER:
4257 case KVM_CAP_GET_MSR_FEATURES:
4258 case KVM_CAP_MSR_PLATFORM_INFO:
4259 case KVM_CAP_EXCEPTION_PAYLOAD:
4260 case KVM_CAP_SET_GUEST_DEBUG:
4261 case KVM_CAP_LAST_CPU:
4262 case KVM_CAP_X86_USER_SPACE_MSR:
4263 case KVM_CAP_X86_MSR_FILTER:
4264 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4265 #ifdef CONFIG_X86_SGX_KVM
4266 case KVM_CAP_SGX_ATTRIBUTE:
4268 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4269 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4270 case KVM_CAP_SREGS2:
4271 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4272 case KVM_CAP_VCPU_ATTRIBUTES:
4273 case KVM_CAP_SYS_ATTRIBUTES:
4275 case KVM_CAP_ENABLE_CAP:
4278 case KVM_CAP_EXIT_HYPERCALL:
4279 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4281 case KVM_CAP_SET_GUEST_DEBUG2:
4282 return KVM_GUESTDBG_VALID_MASK;
4283 #ifdef CONFIG_KVM_XEN
4284 case KVM_CAP_XEN_HVM:
4285 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4286 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4287 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4288 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL;
4289 if (sched_info_on())
4290 r |= KVM_XEN_HVM_CONFIG_RUNSTATE;
4293 case KVM_CAP_SYNC_REGS:
4294 r = KVM_SYNC_X86_VALID_FIELDS;
4296 case KVM_CAP_ADJUST_CLOCK:
4297 r = KVM_CLOCK_VALID_FLAGS;
4299 case KVM_CAP_X86_DISABLE_EXITS:
4300 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
4301 KVM_X86_DISABLE_EXITS_CSTATE;
4302 if(kvm_can_mwait_in_guest())
4303 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4305 case KVM_CAP_X86_SMM:
4306 /* SMBASE is usually relocated above 1M on modern chipsets,
4307 * and SMM handlers might indeed rely on 4G segment limits,
4308 * so do not report SMM to be available if real mode is
4309 * emulated via vm86 mode. Still, do not go to great lengths
4310 * to avoid userspace's usage of the feature, because it is a
4311 * fringe case that is not enabled except via specific settings
4312 * of the module parameters.
4314 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4316 case KVM_CAP_NR_VCPUS:
4317 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4319 case KVM_CAP_MAX_VCPUS:
4322 case KVM_CAP_MAX_VCPU_ID:
4323 r = KVM_MAX_VCPU_IDS;
4325 case KVM_CAP_PV_MMU: /* obsolete */
4329 r = KVM_MAX_MCE_BANKS;
4332 r = boot_cpu_has(X86_FEATURE_XSAVE);
4334 case KVM_CAP_TSC_CONTROL:
4335 r = kvm_has_tsc_control;
4337 case KVM_CAP_X2APIC_API:
4338 r = KVM_X2APIC_API_VALID_FLAGS;
4340 case KVM_CAP_NESTED_STATE:
4341 r = kvm_x86_ops.nested_ops->get_state ?
4342 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4344 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4345 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
4347 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4348 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4350 case KVM_CAP_SMALLER_MAXPHYADDR:
4351 r = (int) allow_smaller_maxphyaddr;
4353 case KVM_CAP_STEAL_TIME:
4354 r = sched_info_on();
4356 case KVM_CAP_X86_BUS_LOCK_EXIT:
4357 if (kvm_has_bus_lock_exit)
4358 r = KVM_BUS_LOCK_DETECTION_OFF |
4359 KVM_BUS_LOCK_DETECTION_EXIT;
4363 case KVM_CAP_XSAVE2: {
4364 u64 guest_perm = xstate_get_guest_group_perm();
4366 r = xstate_required_size(supported_xcr0 & guest_perm, false);
4367 if (r < sizeof(struct kvm_xsave))
4368 r = sizeof(struct kvm_xsave);
4370 case KVM_CAP_PMU_CAPABILITY:
4371 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4374 case KVM_CAP_DISABLE_QUIRKS2:
4375 r = KVM_X86_VALID_QUIRKS;
4383 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4385 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4387 if ((u64)(unsigned long)uaddr != attr->addr)
4388 return ERR_PTR_USR(-EFAULT);
4392 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4394 u64 __user *uaddr = kvm_get_attr_addr(attr);
4400 return PTR_ERR(uaddr);
4402 switch (attr->attr) {
4403 case KVM_X86_XCOMP_GUEST_SUPP:
4404 if (put_user(supported_xcr0, uaddr))
4413 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4418 switch (attr->attr) {
4419 case KVM_X86_XCOMP_GUEST_SUPP:
4426 long kvm_arch_dev_ioctl(struct file *filp,
4427 unsigned int ioctl, unsigned long arg)
4429 void __user *argp = (void __user *)arg;
4433 case KVM_GET_MSR_INDEX_LIST: {
4434 struct kvm_msr_list __user *user_msr_list = argp;
4435 struct kvm_msr_list msr_list;
4439 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4442 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4443 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4446 if (n < msr_list.nmsrs)
4449 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4450 num_msrs_to_save * sizeof(u32)))
4452 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4454 num_emulated_msrs * sizeof(u32)))
4459 case KVM_GET_SUPPORTED_CPUID:
4460 case KVM_GET_EMULATED_CPUID: {
4461 struct kvm_cpuid2 __user *cpuid_arg = argp;
4462 struct kvm_cpuid2 cpuid;
4465 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4468 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4474 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4479 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4481 if (copy_to_user(argp, &kvm_mce_cap_supported,
4482 sizeof(kvm_mce_cap_supported)))
4486 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4487 struct kvm_msr_list __user *user_msr_list = argp;
4488 struct kvm_msr_list msr_list;
4492 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4495 msr_list.nmsrs = num_msr_based_features;
4496 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4499 if (n < msr_list.nmsrs)
4502 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4503 num_msr_based_features * sizeof(u32)))
4509 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4511 case KVM_GET_SUPPORTED_HV_CPUID:
4512 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4514 case KVM_GET_DEVICE_ATTR: {
4515 struct kvm_device_attr attr;
4517 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4519 r = kvm_x86_dev_get_attr(&attr);
4522 case KVM_HAS_DEVICE_ATTR: {
4523 struct kvm_device_attr attr;
4525 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4527 r = kvm_x86_dev_has_attr(&attr);
4538 static void wbinvd_ipi(void *garbage)
4543 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4545 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4548 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4550 /* Address WBINVD may be executed by guest */
4551 if (need_emulate_wbinvd(vcpu)) {
4552 if (static_call(kvm_x86_has_wbinvd_exit)())
4553 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4554 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4555 smp_call_function_single(vcpu->cpu,
4556 wbinvd_ipi, NULL, 1);
4559 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4561 /* Save host pkru register if supported */
4562 vcpu->arch.host_pkru = read_pkru();
4564 /* Apply any externally detected TSC adjustments (due to suspend) */
4565 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4566 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4567 vcpu->arch.tsc_offset_adjustment = 0;
4568 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4571 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4572 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4573 rdtsc() - vcpu->arch.last_host_tsc;
4575 mark_tsc_unstable("KVM discovered backwards TSC");
4577 if (kvm_check_tsc_unstable()) {
4578 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4579 vcpu->arch.last_guest_tsc);
4580 kvm_vcpu_write_tsc_offset(vcpu, offset);
4581 vcpu->arch.tsc_catchup = 1;
4584 if (kvm_lapic_hv_timer_in_use(vcpu))
4585 kvm_lapic_restart_hv_timer(vcpu);
4588 * On a host with synchronized TSC, there is no need to update
4589 * kvmclock on vcpu->cpu migration
4591 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4592 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4593 if (vcpu->cpu != cpu)
4594 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4598 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4601 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4603 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
4604 struct kvm_steal_time __user *st;
4605 struct kvm_memslots *slots;
4606 static const u8 preempted = KVM_VCPU_PREEMPTED;
4608 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4611 if (vcpu->arch.st.preempted)
4614 /* This happens on process exit */
4615 if (unlikely(current->mm != vcpu->kvm->mm))
4618 slots = kvm_memslots(vcpu->kvm);
4620 if (unlikely(slots->generation != ghc->generation ||
4621 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
4624 st = (struct kvm_steal_time __user *)ghc->hva;
4625 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
4627 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
4628 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4630 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
4633 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4637 if (vcpu->preempted && !vcpu->arch.guest_state_protected)
4638 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4641 * Take the srcu lock as memslots will be accessed to check the gfn
4642 * cache generation against the memslots generation.
4644 idx = srcu_read_lock(&vcpu->kvm->srcu);
4645 if (kvm_xen_msr_enabled(vcpu->kvm))
4646 kvm_xen_runstate_set_preempted(vcpu);
4648 kvm_steal_time_set_preempted(vcpu);
4649 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4651 static_call(kvm_x86_vcpu_put)(vcpu);
4652 vcpu->arch.last_host_tsc = rdtsc();
4655 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4656 struct kvm_lapic_state *s)
4658 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
4660 return kvm_apic_get_state(vcpu, s);
4663 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4664 struct kvm_lapic_state *s)
4668 r = kvm_apic_set_state(vcpu, s);
4671 update_cr8_intercept(vcpu);
4676 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4679 * We can accept userspace's request for interrupt injection
4680 * as long as we have a place to store the interrupt number.
4681 * The actual injection will happen when the CPU is able to
4682 * deliver the interrupt.
4684 if (kvm_cpu_has_extint(vcpu))
4687 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4688 return (!lapic_in_kernel(vcpu) ||
4689 kvm_apic_accept_pic_intr(vcpu));
4692 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4695 * Do not cause an interrupt window exit if an exception
4696 * is pending or an event needs reinjection; userspace
4697 * might want to inject the interrupt manually using KVM_SET_REGS
4698 * or KVM_SET_SREGS. For that to work, we must be at an
4699 * instruction boundary and with no events half-injected.
4701 return (kvm_arch_interrupt_allowed(vcpu) &&
4702 kvm_cpu_accept_dm_intr(vcpu) &&
4703 !kvm_event_needs_reinjection(vcpu) &&
4704 !vcpu->arch.exception.pending);
4707 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4708 struct kvm_interrupt *irq)
4710 if (irq->irq >= KVM_NR_INTERRUPTS)
4713 if (!irqchip_in_kernel(vcpu->kvm)) {
4714 kvm_queue_interrupt(vcpu, irq->irq, false);
4715 kvm_make_request(KVM_REQ_EVENT, vcpu);
4720 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4721 * fail for in-kernel 8259.
4723 if (pic_in_kernel(vcpu->kvm))
4726 if (vcpu->arch.pending_external_vector != -1)
4729 vcpu->arch.pending_external_vector = irq->irq;
4730 kvm_make_request(KVM_REQ_EVENT, vcpu);
4734 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4736 kvm_inject_nmi(vcpu);
4741 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4743 kvm_make_request(KVM_REQ_SMI, vcpu);
4748 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4749 struct kvm_tpr_access_ctl *tac)
4753 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4757 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4761 unsigned bank_num = mcg_cap & 0xff, bank;
4764 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4766 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4769 vcpu->arch.mcg_cap = mcg_cap;
4770 /* Init IA32_MCG_CTL to all 1s */
4771 if (mcg_cap & MCG_CTL_P)
4772 vcpu->arch.mcg_ctl = ~(u64)0;
4773 /* Init IA32_MCi_CTL to all 1s */
4774 for (bank = 0; bank < bank_num; bank++)
4775 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4777 static_call(kvm_x86_setup_mce)(vcpu);
4782 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4783 struct kvm_x86_mce *mce)
4785 u64 mcg_cap = vcpu->arch.mcg_cap;
4786 unsigned bank_num = mcg_cap & 0xff;
4787 u64 *banks = vcpu->arch.mce_banks;
4789 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4792 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4793 * reporting is disabled
4795 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4796 vcpu->arch.mcg_ctl != ~(u64)0)
4798 banks += 4 * mce->bank;
4800 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4801 * reporting is disabled for the bank
4803 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4805 if (mce->status & MCI_STATUS_UC) {
4806 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4807 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4808 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4811 if (banks[1] & MCI_STATUS_VAL)
4812 mce->status |= MCI_STATUS_OVER;
4813 banks[2] = mce->addr;
4814 banks[3] = mce->misc;
4815 vcpu->arch.mcg_status = mce->mcg_status;
4816 banks[1] = mce->status;
4817 kvm_queue_exception(vcpu, MC_VECTOR);
4818 } else if (!(banks[1] & MCI_STATUS_VAL)
4819 || !(banks[1] & MCI_STATUS_UC)) {
4820 if (banks[1] & MCI_STATUS_VAL)
4821 mce->status |= MCI_STATUS_OVER;
4822 banks[2] = mce->addr;
4823 banks[3] = mce->misc;
4824 banks[1] = mce->status;
4826 banks[1] |= MCI_STATUS_OVER;
4830 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4831 struct kvm_vcpu_events *events)
4835 if (kvm_check_request(KVM_REQ_SMI, vcpu))
4839 * In guest mode, payload delivery should be deferred,
4840 * so that the L1 hypervisor can intercept #PF before
4841 * CR2 is modified (or intercept #DB before DR6 is
4842 * modified under nVMX). Unless the per-VM capability,
4843 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4844 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4845 * opportunistically defer the exception payload, deliver it if the
4846 * capability hasn't been requested before processing a
4847 * KVM_GET_VCPU_EVENTS.
4849 if (!vcpu->kvm->arch.exception_payload_enabled &&
4850 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4851 kvm_deliver_exception_payload(vcpu);
4854 * The API doesn't provide the instruction length for software
4855 * exceptions, so don't report them. As long as the guest RIP
4856 * isn't advanced, we should expect to encounter the exception
4859 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4860 events->exception.injected = 0;
4861 events->exception.pending = 0;
4863 events->exception.injected = vcpu->arch.exception.injected;
4864 events->exception.pending = vcpu->arch.exception.pending;
4866 * For ABI compatibility, deliberately conflate
4867 * pending and injected exceptions when
4868 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4870 if (!vcpu->kvm->arch.exception_payload_enabled)
4871 events->exception.injected |=
4872 vcpu->arch.exception.pending;
4874 events->exception.nr = vcpu->arch.exception.nr;
4875 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4876 events->exception.error_code = vcpu->arch.exception.error_code;
4877 events->exception_has_payload = vcpu->arch.exception.has_payload;
4878 events->exception_payload = vcpu->arch.exception.payload;
4880 events->interrupt.injected =
4881 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4882 events->interrupt.nr = vcpu->arch.interrupt.nr;
4883 events->interrupt.soft = 0;
4884 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
4886 events->nmi.injected = vcpu->arch.nmi_injected;
4887 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4888 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
4889 events->nmi.pad = 0;
4891 events->sipi_vector = 0; /* never valid when reporting to user space */
4893 events->smi.smm = is_smm(vcpu);
4894 events->smi.pending = vcpu->arch.smi_pending;
4895 events->smi.smm_inside_nmi =
4896 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4897 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4899 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4900 | KVM_VCPUEVENT_VALID_SHADOW
4901 | KVM_VCPUEVENT_VALID_SMM);
4902 if (vcpu->kvm->arch.exception_payload_enabled)
4903 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4905 memset(&events->reserved, 0, sizeof(events->reserved));
4908 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm);
4910 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4911 struct kvm_vcpu_events *events)
4913 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4914 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4915 | KVM_VCPUEVENT_VALID_SHADOW
4916 | KVM_VCPUEVENT_VALID_SMM
4917 | KVM_VCPUEVENT_VALID_PAYLOAD))
4920 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4921 if (!vcpu->kvm->arch.exception_payload_enabled)
4923 if (events->exception.pending)
4924 events->exception.injected = 0;
4926 events->exception_has_payload = 0;
4928 events->exception.pending = 0;
4929 events->exception_has_payload = 0;
4932 if ((events->exception.injected || events->exception.pending) &&
4933 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4936 /* INITs are latched while in SMM */
4937 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4938 (events->smi.smm || events->smi.pending) &&
4939 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4943 vcpu->arch.exception.injected = events->exception.injected;
4944 vcpu->arch.exception.pending = events->exception.pending;
4945 vcpu->arch.exception.nr = events->exception.nr;
4946 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4947 vcpu->arch.exception.error_code = events->exception.error_code;
4948 vcpu->arch.exception.has_payload = events->exception_has_payload;
4949 vcpu->arch.exception.payload = events->exception_payload;
4951 vcpu->arch.interrupt.injected = events->interrupt.injected;
4952 vcpu->arch.interrupt.nr = events->interrupt.nr;
4953 vcpu->arch.interrupt.soft = events->interrupt.soft;
4954 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4955 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
4956 events->interrupt.shadow);
4958 vcpu->arch.nmi_injected = events->nmi.injected;
4959 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4960 vcpu->arch.nmi_pending = events->nmi.pending;
4961 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
4963 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4964 lapic_in_kernel(vcpu))
4965 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4967 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4968 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4969 kvm_x86_ops.nested_ops->leave_nested(vcpu);
4970 kvm_smm_changed(vcpu, events->smi.smm);
4973 vcpu->arch.smi_pending = events->smi.pending;
4975 if (events->smi.smm) {
4976 if (events->smi.smm_inside_nmi)
4977 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4979 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4982 if (lapic_in_kernel(vcpu)) {
4983 if (events->smi.latched_init)
4984 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4986 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4990 kvm_make_request(KVM_REQ_EVENT, vcpu);
4995 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4996 struct kvm_debugregs *dbgregs)
5000 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
5001 kvm_get_dr(vcpu, 6, &val);
5003 dbgregs->dr7 = vcpu->arch.dr7;
5005 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
5008 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5009 struct kvm_debugregs *dbgregs)
5014 if (!kvm_dr6_valid(dbgregs->dr6))
5016 if (!kvm_dr7_valid(dbgregs->dr7))
5019 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5020 kvm_update_dr0123(vcpu);
5021 vcpu->arch.dr6 = dbgregs->dr6;
5022 vcpu->arch.dr7 = dbgregs->dr7;
5023 kvm_update_dr7(vcpu);
5028 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5029 struct kvm_xsave *guest_xsave)
5031 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5034 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5035 guest_xsave->region,
5036 sizeof(guest_xsave->region),
5040 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5041 u8 *state, unsigned int size)
5043 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5046 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5047 state, size, vcpu->arch.pkru);
5050 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5051 struct kvm_xsave *guest_xsave)
5053 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5056 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5057 guest_xsave->region,
5058 supported_xcr0, &vcpu->arch.pkru);
5061 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5062 struct kvm_xcrs *guest_xcrs)
5064 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5065 guest_xcrs->nr_xcrs = 0;
5069 guest_xcrs->nr_xcrs = 1;
5070 guest_xcrs->flags = 0;
5071 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5072 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5075 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5076 struct kvm_xcrs *guest_xcrs)
5080 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5083 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5086 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5087 /* Only support XCR0 currently */
5088 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5089 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5090 guest_xcrs->xcrs[i].value);
5099 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5100 * stopped by the hypervisor. This function will be called from the host only.
5101 * EINVAL is returned when the host attempts to set the flag for a guest that
5102 * does not support pv clocks.
5104 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5106 if (!vcpu->arch.pv_time_enabled)
5108 vcpu->arch.pvclock_set_guest_stopped_request = true;
5109 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5113 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5114 struct kvm_device_attr *attr)
5118 switch (attr->attr) {
5119 case KVM_VCPU_TSC_OFFSET:
5129 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5130 struct kvm_device_attr *attr)
5132 u64 __user *uaddr = kvm_get_attr_addr(attr);
5136 return PTR_ERR(uaddr);
5138 switch (attr->attr) {
5139 case KVM_VCPU_TSC_OFFSET:
5141 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5152 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5153 struct kvm_device_attr *attr)
5155 u64 __user *uaddr = kvm_get_attr_addr(attr);
5156 struct kvm *kvm = vcpu->kvm;
5160 return PTR_ERR(uaddr);
5162 switch (attr->attr) {
5163 case KVM_VCPU_TSC_OFFSET: {
5164 u64 offset, tsc, ns;
5165 unsigned long flags;
5169 if (get_user(offset, uaddr))
5172 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5174 matched = (vcpu->arch.virtual_tsc_khz &&
5175 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5176 kvm->arch.last_tsc_offset == offset);
5178 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5179 ns = get_kvmclock_base_ns();
5181 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5182 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5194 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5198 struct kvm_device_attr attr;
5201 if (copy_from_user(&attr, argp, sizeof(attr)))
5204 if (attr.group != KVM_VCPU_TSC_CTRL)
5208 case KVM_HAS_DEVICE_ATTR:
5209 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5211 case KVM_GET_DEVICE_ATTR:
5212 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5214 case KVM_SET_DEVICE_ATTR:
5215 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5222 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5223 struct kvm_enable_cap *cap)
5226 uint16_t vmcs_version;
5227 void __user *user_ptr;
5233 case KVM_CAP_HYPERV_SYNIC2:
5238 case KVM_CAP_HYPERV_SYNIC:
5239 if (!irqchip_in_kernel(vcpu->kvm))
5241 return kvm_hv_activate_synic(vcpu, cap->cap ==
5242 KVM_CAP_HYPERV_SYNIC2);
5243 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5244 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5246 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5248 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5249 if (copy_to_user(user_ptr, &vmcs_version,
5250 sizeof(vmcs_version)))
5254 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5255 if (!kvm_x86_ops.enable_direct_tlbflush)
5258 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu);
5260 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5261 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5263 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5264 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5265 if (vcpu->arch.pv_cpuid.enforce)
5266 kvm_update_pv_runtime(vcpu);
5274 long kvm_arch_vcpu_ioctl(struct file *filp,
5275 unsigned int ioctl, unsigned long arg)
5277 struct kvm_vcpu *vcpu = filp->private_data;
5278 void __user *argp = (void __user *)arg;
5281 struct kvm_sregs2 *sregs2;
5282 struct kvm_lapic_state *lapic;
5283 struct kvm_xsave *xsave;
5284 struct kvm_xcrs *xcrs;
5292 case KVM_GET_LAPIC: {
5294 if (!lapic_in_kernel(vcpu))
5296 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5297 GFP_KERNEL_ACCOUNT);
5302 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5306 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5311 case KVM_SET_LAPIC: {
5313 if (!lapic_in_kernel(vcpu))
5315 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5316 if (IS_ERR(u.lapic)) {
5317 r = PTR_ERR(u.lapic);
5321 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5324 case KVM_INTERRUPT: {
5325 struct kvm_interrupt irq;
5328 if (copy_from_user(&irq, argp, sizeof(irq)))
5330 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5334 r = kvm_vcpu_ioctl_nmi(vcpu);
5338 r = kvm_vcpu_ioctl_smi(vcpu);
5341 case KVM_SET_CPUID: {
5342 struct kvm_cpuid __user *cpuid_arg = argp;
5343 struct kvm_cpuid cpuid;
5346 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5348 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5351 case KVM_SET_CPUID2: {
5352 struct kvm_cpuid2 __user *cpuid_arg = argp;
5353 struct kvm_cpuid2 cpuid;
5356 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5358 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5359 cpuid_arg->entries);
5362 case KVM_GET_CPUID2: {
5363 struct kvm_cpuid2 __user *cpuid_arg = argp;
5364 struct kvm_cpuid2 cpuid;
5367 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5369 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5370 cpuid_arg->entries);
5374 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5379 case KVM_GET_MSRS: {
5380 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5381 r = msr_io(vcpu, argp, do_get_msr, 1);
5382 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5385 case KVM_SET_MSRS: {
5386 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5387 r = msr_io(vcpu, argp, do_set_msr, 0);
5388 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5391 case KVM_TPR_ACCESS_REPORTING: {
5392 struct kvm_tpr_access_ctl tac;
5395 if (copy_from_user(&tac, argp, sizeof(tac)))
5397 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5401 if (copy_to_user(argp, &tac, sizeof(tac)))
5406 case KVM_SET_VAPIC_ADDR: {
5407 struct kvm_vapic_addr va;
5411 if (!lapic_in_kernel(vcpu))
5414 if (copy_from_user(&va, argp, sizeof(va)))
5416 idx = srcu_read_lock(&vcpu->kvm->srcu);
5417 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5418 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5421 case KVM_X86_SETUP_MCE: {
5425 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5427 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5430 case KVM_X86_SET_MCE: {
5431 struct kvm_x86_mce mce;
5434 if (copy_from_user(&mce, argp, sizeof(mce)))
5436 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5439 case KVM_GET_VCPU_EVENTS: {
5440 struct kvm_vcpu_events events;
5442 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5445 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5450 case KVM_SET_VCPU_EVENTS: {
5451 struct kvm_vcpu_events events;
5454 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5457 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5460 case KVM_GET_DEBUGREGS: {
5461 struct kvm_debugregs dbgregs;
5463 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5466 if (copy_to_user(argp, &dbgregs,
5467 sizeof(struct kvm_debugregs)))
5472 case KVM_SET_DEBUGREGS: {
5473 struct kvm_debugregs dbgregs;
5476 if (copy_from_user(&dbgregs, argp,
5477 sizeof(struct kvm_debugregs)))
5480 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
5483 case KVM_GET_XSAVE: {
5485 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
5488 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
5493 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
5496 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
5501 case KVM_SET_XSAVE: {
5502 int size = vcpu->arch.guest_fpu.uabi_size;
5504 u.xsave = memdup_user(argp, size);
5505 if (IS_ERR(u.xsave)) {
5506 r = PTR_ERR(u.xsave);
5510 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
5514 case KVM_GET_XSAVE2: {
5515 int size = vcpu->arch.guest_fpu.uabi_size;
5517 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
5522 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
5525 if (copy_to_user(argp, u.xsave, size))
5532 case KVM_GET_XCRS: {
5533 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
5538 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
5541 if (copy_to_user(argp, u.xcrs,
5542 sizeof(struct kvm_xcrs)))
5547 case KVM_SET_XCRS: {
5548 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
5549 if (IS_ERR(u.xcrs)) {
5550 r = PTR_ERR(u.xcrs);
5554 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
5557 case KVM_SET_TSC_KHZ: {
5561 user_tsc_khz = (u32)arg;
5563 if (kvm_has_tsc_control &&
5564 user_tsc_khz >= kvm_max_guest_tsc_khz)
5567 if (user_tsc_khz == 0)
5568 user_tsc_khz = tsc_khz;
5570 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
5575 case KVM_GET_TSC_KHZ: {
5576 r = vcpu->arch.virtual_tsc_khz;
5579 case KVM_KVMCLOCK_CTRL: {
5580 r = kvm_set_guest_paused(vcpu);
5583 case KVM_ENABLE_CAP: {
5584 struct kvm_enable_cap cap;
5587 if (copy_from_user(&cap, argp, sizeof(cap)))
5589 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
5592 case KVM_GET_NESTED_STATE: {
5593 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5597 if (!kvm_x86_ops.nested_ops->get_state)
5600 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
5602 if (get_user(user_data_size, &user_kvm_nested_state->size))
5605 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
5610 if (r > user_data_size) {
5611 if (put_user(r, &user_kvm_nested_state->size))
5621 case KVM_SET_NESTED_STATE: {
5622 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5623 struct kvm_nested_state kvm_state;
5627 if (!kvm_x86_ops.nested_ops->set_state)
5631 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5635 if (kvm_state.size < sizeof(kvm_state))
5638 if (kvm_state.flags &
5639 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5640 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5641 | KVM_STATE_NESTED_GIF_SET))
5644 /* nested_run_pending implies guest_mode. */
5645 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5646 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5649 idx = srcu_read_lock(&vcpu->kvm->srcu);
5650 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5651 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5654 case KVM_GET_SUPPORTED_HV_CPUID:
5655 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5657 #ifdef CONFIG_KVM_XEN
5658 case KVM_XEN_VCPU_GET_ATTR: {
5659 struct kvm_xen_vcpu_attr xva;
5662 if (copy_from_user(&xva, argp, sizeof(xva)))
5664 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
5665 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
5669 case KVM_XEN_VCPU_SET_ATTR: {
5670 struct kvm_xen_vcpu_attr xva;
5673 if (copy_from_user(&xva, argp, sizeof(xva)))
5675 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
5679 case KVM_GET_SREGS2: {
5680 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
5684 __get_sregs2(vcpu, u.sregs2);
5686 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
5691 case KVM_SET_SREGS2: {
5692 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
5693 if (IS_ERR(u.sregs2)) {
5694 r = PTR_ERR(u.sregs2);
5698 r = __set_sregs2(vcpu, u.sregs2);
5701 case KVM_HAS_DEVICE_ATTR:
5702 case KVM_GET_DEVICE_ATTR:
5703 case KVM_SET_DEVICE_ATTR:
5704 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
5716 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5718 return VM_FAULT_SIGBUS;
5721 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5725 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5727 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
5731 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5734 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
5737 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5738 unsigned long kvm_nr_mmu_pages)
5740 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5743 mutex_lock(&kvm->slots_lock);
5745 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5746 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5748 mutex_unlock(&kvm->slots_lock);
5752 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5754 return kvm->arch.n_max_mmu_pages;
5757 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5759 struct kvm_pic *pic = kvm->arch.vpic;
5763 switch (chip->chip_id) {
5764 case KVM_IRQCHIP_PIC_MASTER:
5765 memcpy(&chip->chip.pic, &pic->pics[0],
5766 sizeof(struct kvm_pic_state));
5768 case KVM_IRQCHIP_PIC_SLAVE:
5769 memcpy(&chip->chip.pic, &pic->pics[1],
5770 sizeof(struct kvm_pic_state));
5772 case KVM_IRQCHIP_IOAPIC:
5773 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5782 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5784 struct kvm_pic *pic = kvm->arch.vpic;
5788 switch (chip->chip_id) {
5789 case KVM_IRQCHIP_PIC_MASTER:
5790 spin_lock(&pic->lock);
5791 memcpy(&pic->pics[0], &chip->chip.pic,
5792 sizeof(struct kvm_pic_state));
5793 spin_unlock(&pic->lock);
5795 case KVM_IRQCHIP_PIC_SLAVE:
5796 spin_lock(&pic->lock);
5797 memcpy(&pic->pics[1], &chip->chip.pic,
5798 sizeof(struct kvm_pic_state));
5799 spin_unlock(&pic->lock);
5801 case KVM_IRQCHIP_IOAPIC:
5802 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5808 kvm_pic_update_irq(pic);
5812 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5814 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5816 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5818 mutex_lock(&kps->lock);
5819 memcpy(ps, &kps->channels, sizeof(*ps));
5820 mutex_unlock(&kps->lock);
5824 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5827 struct kvm_pit *pit = kvm->arch.vpit;
5829 mutex_lock(&pit->pit_state.lock);
5830 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5831 for (i = 0; i < 3; i++)
5832 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5833 mutex_unlock(&pit->pit_state.lock);
5837 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5839 mutex_lock(&kvm->arch.vpit->pit_state.lock);
5840 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5841 sizeof(ps->channels));
5842 ps->flags = kvm->arch.vpit->pit_state.flags;
5843 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5844 memset(&ps->reserved, 0, sizeof(ps->reserved));
5848 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5852 u32 prev_legacy, cur_legacy;
5853 struct kvm_pit *pit = kvm->arch.vpit;
5855 mutex_lock(&pit->pit_state.lock);
5856 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5857 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5858 if (!prev_legacy && cur_legacy)
5860 memcpy(&pit->pit_state.channels, &ps->channels,
5861 sizeof(pit->pit_state.channels));
5862 pit->pit_state.flags = ps->flags;
5863 for (i = 0; i < 3; i++)
5864 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5866 mutex_unlock(&pit->pit_state.lock);
5870 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5871 struct kvm_reinject_control *control)
5873 struct kvm_pit *pit = kvm->arch.vpit;
5875 /* pit->pit_state.lock was overloaded to prevent userspace from getting
5876 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5877 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
5879 mutex_lock(&pit->pit_state.lock);
5880 kvm_pit_set_reinject(pit, control->pit_reinject);
5881 mutex_unlock(&pit->pit_state.lock);
5886 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5890 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
5891 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
5892 * on all VM-Exits, thus we only need to kick running vCPUs to force a
5895 struct kvm_vcpu *vcpu;
5898 kvm_for_each_vcpu(i, vcpu, kvm)
5899 kvm_vcpu_kick(vcpu);
5902 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5905 if (!irqchip_in_kernel(kvm))
5908 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5909 irq_event->irq, irq_event->level,
5914 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5915 struct kvm_enable_cap *cap)
5923 case KVM_CAP_DISABLE_QUIRKS2:
5925 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
5928 case KVM_CAP_DISABLE_QUIRKS:
5929 kvm->arch.disabled_quirks = cap->args[0];
5932 case KVM_CAP_SPLIT_IRQCHIP: {
5933 mutex_lock(&kvm->lock);
5935 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5936 goto split_irqchip_unlock;
5938 if (irqchip_in_kernel(kvm))
5939 goto split_irqchip_unlock;
5940 if (kvm->created_vcpus)
5941 goto split_irqchip_unlock;
5942 r = kvm_setup_empty_irq_routing(kvm);
5944 goto split_irqchip_unlock;
5945 /* Pairs with irqchip_in_kernel. */
5947 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5948 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5949 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
5951 split_irqchip_unlock:
5952 mutex_unlock(&kvm->lock);
5955 case KVM_CAP_X2APIC_API:
5957 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5960 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5961 kvm->arch.x2apic_format = true;
5962 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5963 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5967 case KVM_CAP_X86_DISABLE_EXITS:
5969 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5972 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5973 kvm_can_mwait_in_guest())
5974 kvm->arch.mwait_in_guest = true;
5975 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5976 kvm->arch.hlt_in_guest = true;
5977 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5978 kvm->arch.pause_in_guest = true;
5979 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5980 kvm->arch.cstate_in_guest = true;
5983 case KVM_CAP_MSR_PLATFORM_INFO:
5984 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5987 case KVM_CAP_EXCEPTION_PAYLOAD:
5988 kvm->arch.exception_payload_enabled = cap->args[0];
5991 case KVM_CAP_X86_USER_SPACE_MSR:
5992 kvm->arch.user_space_msr_mask = cap->args[0];
5995 case KVM_CAP_X86_BUS_LOCK_EXIT:
5997 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
6000 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6001 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6004 if (kvm_has_bus_lock_exit &&
6005 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6006 kvm->arch.bus_lock_detection_enabled = true;
6009 #ifdef CONFIG_X86_SGX_KVM
6010 case KVM_CAP_SGX_ATTRIBUTE: {
6011 unsigned long allowed_attributes = 0;
6013 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6017 /* KVM only supports the PROVISIONKEY privileged attribute. */
6018 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6019 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6020 kvm->arch.sgx_provisioning_allowed = true;
6026 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6028 if (!kvm_x86_ops.vm_copy_enc_context_from)
6031 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6033 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6035 if (!kvm_x86_ops.vm_move_enc_context_from)
6038 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6040 case KVM_CAP_EXIT_HYPERCALL:
6041 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6045 kvm->arch.hypercall_exit_enabled = cap->args[0];
6048 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6050 if (cap->args[0] & ~1)
6052 kvm->arch.exit_on_emulation_error = cap->args[0];
6055 case KVM_CAP_PMU_CAPABILITY:
6057 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6060 mutex_lock(&kvm->lock);
6061 if (!kvm->created_vcpus) {
6062 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6065 mutex_unlock(&kvm->lock);
6074 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6076 struct kvm_x86_msr_filter *msr_filter;
6078 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6082 msr_filter->default_allow = default_allow;
6086 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6093 for (i = 0; i < msr_filter->count; i++)
6094 kfree(msr_filter->ranges[i].bitmap);
6099 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6100 struct kvm_msr_filter_range *user_range)
6102 unsigned long *bitmap = NULL;
6105 if (!user_range->nmsrs)
6108 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE))
6111 if (!user_range->flags)
6114 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6115 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6118 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6120 return PTR_ERR(bitmap);
6122 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6123 .flags = user_range->flags,
6124 .base = user_range->base,
6125 .nmsrs = user_range->nmsrs,
6129 msr_filter->count++;
6133 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
6135 struct kvm_msr_filter __user *user_msr_filter = argp;
6136 struct kvm_x86_msr_filter *new_filter, *old_filter;
6137 struct kvm_msr_filter filter;
6143 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
6146 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
6147 empty &= !filter.ranges[i].nmsrs;
6149 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
6150 if (empty && !default_allow)
6153 new_filter = kvm_alloc_msr_filter(default_allow);
6157 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6158 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]);
6160 kvm_free_msr_filter(new_filter);
6165 mutex_lock(&kvm->lock);
6167 /* The per-VM filter is protected by kvm->lock... */
6168 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1);
6170 rcu_assign_pointer(kvm->arch.msr_filter, new_filter);
6171 synchronize_srcu(&kvm->srcu);
6173 kvm_free_msr_filter(old_filter);
6175 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6176 mutex_unlock(&kvm->lock);
6181 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6182 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6184 struct kvm_vcpu *vcpu;
6188 mutex_lock(&kvm->lock);
6189 kvm_for_each_vcpu(i, vcpu, kvm) {
6190 if (!vcpu->arch.pv_time_enabled)
6193 ret = kvm_set_guest_paused(vcpu);
6195 kvm_err("Failed to pause guest VCPU%d: %d\n",
6196 vcpu->vcpu_id, ret);
6200 mutex_unlock(&kvm->lock);
6202 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6205 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6208 case PM_HIBERNATION_PREPARE:
6209 case PM_SUSPEND_PREPARE:
6210 return kvm_arch_suspend_notifier(kvm);
6215 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6217 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6219 struct kvm_clock_data data = { 0 };
6221 get_kvmclock(kvm, &data);
6222 if (copy_to_user(argp, &data, sizeof(data)))
6228 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6230 struct kvm_arch *ka = &kvm->arch;
6231 struct kvm_clock_data data;
6234 if (copy_from_user(&data, argp, sizeof(data)))
6238 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6239 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6241 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6244 kvm_hv_invalidate_tsc_page(kvm);
6245 kvm_start_pvclock_update(kvm);
6246 pvclock_update_vm_gtod_copy(kvm);
6249 * This pairs with kvm_guest_time_update(): when masterclock is
6250 * in use, we use master_kernel_ns + kvmclock_offset to set
6251 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6252 * is slightly ahead) here we risk going negative on unsigned
6253 * 'system_time' when 'data.clock' is very small.
6255 if (data.flags & KVM_CLOCK_REALTIME) {
6256 u64 now_real_ns = ktime_get_real_ns();
6259 * Avoid stepping the kvmclock backwards.
6261 if (now_real_ns > data.realtime)
6262 data.clock += now_real_ns - data.realtime;
6265 if (ka->use_master_clock)
6266 now_raw_ns = ka->master_kernel_ns;
6268 now_raw_ns = get_kvmclock_base_ns();
6269 ka->kvmclock_offset = data.clock - now_raw_ns;
6270 kvm_end_pvclock_update(kvm);
6274 long kvm_arch_vm_ioctl(struct file *filp,
6275 unsigned int ioctl, unsigned long arg)
6277 struct kvm *kvm = filp->private_data;
6278 void __user *argp = (void __user *)arg;
6281 * This union makes it completely explicit to gcc-3.x
6282 * that these two variables' stack usage should be
6283 * combined, not added together.
6286 struct kvm_pit_state ps;
6287 struct kvm_pit_state2 ps2;
6288 struct kvm_pit_config pit_config;
6292 case KVM_SET_TSS_ADDR:
6293 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6295 case KVM_SET_IDENTITY_MAP_ADDR: {
6298 mutex_lock(&kvm->lock);
6300 if (kvm->created_vcpus)
6301 goto set_identity_unlock;
6303 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6304 goto set_identity_unlock;
6305 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6306 set_identity_unlock:
6307 mutex_unlock(&kvm->lock);
6310 case KVM_SET_NR_MMU_PAGES:
6311 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6313 case KVM_GET_NR_MMU_PAGES:
6314 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
6316 case KVM_CREATE_IRQCHIP: {
6317 mutex_lock(&kvm->lock);
6320 if (irqchip_in_kernel(kvm))
6321 goto create_irqchip_unlock;
6324 if (kvm->created_vcpus)
6325 goto create_irqchip_unlock;
6327 r = kvm_pic_init(kvm);
6329 goto create_irqchip_unlock;
6331 r = kvm_ioapic_init(kvm);
6333 kvm_pic_destroy(kvm);
6334 goto create_irqchip_unlock;
6337 r = kvm_setup_default_irq_routing(kvm);
6339 kvm_ioapic_destroy(kvm);
6340 kvm_pic_destroy(kvm);
6341 goto create_irqchip_unlock;
6343 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6345 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
6346 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6347 create_irqchip_unlock:
6348 mutex_unlock(&kvm->lock);
6351 case KVM_CREATE_PIT:
6352 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
6354 case KVM_CREATE_PIT2:
6356 if (copy_from_user(&u.pit_config, argp,
6357 sizeof(struct kvm_pit_config)))
6360 mutex_lock(&kvm->lock);
6363 goto create_pit_unlock;
6365 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
6369 mutex_unlock(&kvm->lock);
6371 case KVM_GET_IRQCHIP: {
6372 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6373 struct kvm_irqchip *chip;
6375 chip = memdup_user(argp, sizeof(*chip));
6382 if (!irqchip_kernel(kvm))
6383 goto get_irqchip_out;
6384 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
6386 goto get_irqchip_out;
6388 if (copy_to_user(argp, chip, sizeof(*chip)))
6389 goto get_irqchip_out;
6395 case KVM_SET_IRQCHIP: {
6396 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6397 struct kvm_irqchip *chip;
6399 chip = memdup_user(argp, sizeof(*chip));
6406 if (!irqchip_kernel(kvm))
6407 goto set_irqchip_out;
6408 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
6415 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
6418 if (!kvm->arch.vpit)
6420 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
6424 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
6431 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
6433 mutex_lock(&kvm->lock);
6435 if (!kvm->arch.vpit)
6437 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
6439 mutex_unlock(&kvm->lock);
6442 case KVM_GET_PIT2: {
6444 if (!kvm->arch.vpit)
6446 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
6450 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
6455 case KVM_SET_PIT2: {
6457 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
6459 mutex_lock(&kvm->lock);
6461 if (!kvm->arch.vpit)
6463 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
6465 mutex_unlock(&kvm->lock);
6468 case KVM_REINJECT_CONTROL: {
6469 struct kvm_reinject_control control;
6471 if (copy_from_user(&control, argp, sizeof(control)))
6474 if (!kvm->arch.vpit)
6476 r = kvm_vm_ioctl_reinject(kvm, &control);
6479 case KVM_SET_BOOT_CPU_ID:
6481 mutex_lock(&kvm->lock);
6482 if (kvm->created_vcpus)
6485 kvm->arch.bsp_vcpu_id = arg;
6486 mutex_unlock(&kvm->lock);
6488 #ifdef CONFIG_KVM_XEN
6489 case KVM_XEN_HVM_CONFIG: {
6490 struct kvm_xen_hvm_config xhc;
6492 if (copy_from_user(&xhc, argp, sizeof(xhc)))
6494 r = kvm_xen_hvm_config(kvm, &xhc);
6497 case KVM_XEN_HVM_GET_ATTR: {
6498 struct kvm_xen_hvm_attr xha;
6501 if (copy_from_user(&xha, argp, sizeof(xha)))
6503 r = kvm_xen_hvm_get_attr(kvm, &xha);
6504 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
6508 case KVM_XEN_HVM_SET_ATTR: {
6509 struct kvm_xen_hvm_attr xha;
6512 if (copy_from_user(&xha, argp, sizeof(xha)))
6514 r = kvm_xen_hvm_set_attr(kvm, &xha);
6519 r = kvm_vm_ioctl_set_clock(kvm, argp);
6522 r = kvm_vm_ioctl_get_clock(kvm, argp);
6524 case KVM_MEMORY_ENCRYPT_OP: {
6526 if (!kvm_x86_ops.mem_enc_ioctl)
6529 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
6532 case KVM_MEMORY_ENCRYPT_REG_REGION: {
6533 struct kvm_enc_region region;
6536 if (copy_from_user(®ion, argp, sizeof(region)))
6540 if (!kvm_x86_ops.mem_enc_register_region)
6543 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
6546 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
6547 struct kvm_enc_region region;
6550 if (copy_from_user(®ion, argp, sizeof(region)))
6554 if (!kvm_x86_ops.mem_enc_unregister_region)
6557 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
6560 case KVM_HYPERV_EVENTFD: {
6561 struct kvm_hyperv_eventfd hvevfd;
6564 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
6566 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
6569 case KVM_SET_PMU_EVENT_FILTER:
6570 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
6572 case KVM_X86_SET_MSR_FILTER:
6573 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
6582 static void kvm_init_msr_list(void)
6584 struct x86_pmu_capability x86_pmu;
6588 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
6589 "Please update the fixed PMCs in msrs_to_saved_all[]");
6591 perf_get_x86_pmu_capability(&x86_pmu);
6593 num_msrs_to_save = 0;
6594 num_emulated_msrs = 0;
6595 num_msr_based_features = 0;
6597 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
6598 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
6602 * Even MSRs that are valid in the host may not be exposed
6603 * to the guests in some cases.
6605 switch (msrs_to_save_all[i]) {
6606 case MSR_IA32_BNDCFGS:
6607 if (!kvm_mpx_supported())
6611 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
6612 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
6615 case MSR_IA32_UMWAIT_CONTROL:
6616 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
6619 case MSR_IA32_RTIT_CTL:
6620 case MSR_IA32_RTIT_STATUS:
6621 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
6624 case MSR_IA32_RTIT_CR3_MATCH:
6625 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6626 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
6629 case MSR_IA32_RTIT_OUTPUT_BASE:
6630 case MSR_IA32_RTIT_OUTPUT_MASK:
6631 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6632 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
6633 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
6636 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
6637 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6638 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
6639 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
6642 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
6643 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
6644 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
6647 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
6648 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
6649 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
6653 case MSR_IA32_XFD_ERR:
6654 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
6661 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
6664 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
6665 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
6668 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
6671 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
6672 struct kvm_msr_entry msr;
6674 msr.index = msr_based_features_all[i];
6675 if (kvm_get_msr_feature(&msr))
6678 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
6682 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
6690 if (!(lapic_in_kernel(vcpu) &&
6691 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
6692 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
6703 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
6710 if (!(lapic_in_kernel(vcpu) &&
6711 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
6713 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
6715 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
6725 static void kvm_set_segment(struct kvm_vcpu *vcpu,
6726 struct kvm_segment *var, int seg)
6728 static_call(kvm_x86_set_segment)(vcpu, var, seg);
6731 void kvm_get_segment(struct kvm_vcpu *vcpu,
6732 struct kvm_segment *var, int seg)
6734 static_call(kvm_x86_get_segment)(vcpu, var, seg);
6737 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
6738 struct x86_exception *exception)
6740 struct kvm_mmu *mmu = vcpu->arch.mmu;
6743 BUG_ON(!mmu_is_nested(vcpu));
6745 /* NPT walks are always user-walks */
6746 access |= PFERR_USER_MASK;
6747 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
6752 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
6753 struct x86_exception *exception)
6755 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6757 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6758 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
6760 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
6762 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
6763 struct x86_exception *exception)
6765 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6767 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6768 access |= PFERR_FETCH_MASK;
6769 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
6772 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
6773 struct x86_exception *exception)
6775 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6777 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6778 access |= PFERR_WRITE_MASK;
6779 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
6781 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
6783 /* uses this to access any guest's mapped memory without checking CPL */
6784 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
6785 struct x86_exception *exception)
6787 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6789 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
6792 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6793 struct kvm_vcpu *vcpu, u64 access,
6794 struct x86_exception *exception)
6796 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6798 int r = X86EMUL_CONTINUE;
6801 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
6802 unsigned offset = addr & (PAGE_SIZE-1);
6803 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
6806 if (gpa == UNMAPPED_GVA)
6807 return X86EMUL_PROPAGATE_FAULT;
6808 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
6811 r = X86EMUL_IO_NEEDED;
6823 /* used for instruction fetching */
6824 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
6825 gva_t addr, void *val, unsigned int bytes,
6826 struct x86_exception *exception)
6828 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6829 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6830 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6834 /* Inline kvm_read_guest_virt_helper for speed. */
6835 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
6837 if (unlikely(gpa == UNMAPPED_GVA))
6838 return X86EMUL_PROPAGATE_FAULT;
6840 offset = addr & (PAGE_SIZE-1);
6841 if (WARN_ON(offset + bytes > PAGE_SIZE))
6842 bytes = (unsigned)PAGE_SIZE - offset;
6843 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
6845 if (unlikely(ret < 0))
6846 return X86EMUL_IO_NEEDED;
6848 return X86EMUL_CONTINUE;
6851 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
6852 gva_t addr, void *val, unsigned int bytes,
6853 struct x86_exception *exception)
6855 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6858 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
6859 * is returned, but our callers are not ready for that and they blindly
6860 * call kvm_inject_page_fault. Ensure that they at least do not leak
6861 * uninitialized kernel stack memory into cr2 and error code.
6863 memset(exception, 0, sizeof(*exception));
6864 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
6867 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
6869 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
6870 gva_t addr, void *val, unsigned int bytes,
6871 struct x86_exception *exception, bool system)
6873 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6877 access |= PFERR_IMPLICIT_ACCESS;
6878 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
6879 access |= PFERR_USER_MASK;
6881 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
6884 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
6885 unsigned long addr, void *val, unsigned int bytes)
6887 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6888 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
6890 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
6893 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6894 struct kvm_vcpu *vcpu, u64 access,
6895 struct x86_exception *exception)
6897 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6899 int r = X86EMUL_CONTINUE;
6902 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
6903 unsigned offset = addr & (PAGE_SIZE-1);
6904 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
6907 if (gpa == UNMAPPED_GVA)
6908 return X86EMUL_PROPAGATE_FAULT;
6909 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
6911 r = X86EMUL_IO_NEEDED;
6923 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
6924 unsigned int bytes, struct x86_exception *exception,
6927 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6928 u64 access = PFERR_WRITE_MASK;
6931 access |= PFERR_IMPLICIT_ACCESS;
6932 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
6933 access |= PFERR_USER_MASK;
6935 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6939 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
6940 unsigned int bytes, struct x86_exception *exception)
6942 /* kvm_write_guest_virt_system can pull in tons of pages. */
6943 vcpu->arch.l1tf_flush_l1d = true;
6945 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6946 PFERR_WRITE_MASK, exception);
6948 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
6950 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
6951 void *insn, int insn_len)
6953 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type,
6957 int handle_ud(struct kvm_vcpu *vcpu)
6959 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6960 int emul_type = EMULTYPE_TRAP_UD;
6961 char sig[5]; /* ud2; .ascii "kvm" */
6962 struct x86_exception e;
6964 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0)))
6967 if (force_emulation_prefix &&
6968 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
6969 sig, sizeof(sig), &e) == 0 &&
6970 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6971 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
6972 emul_type = EMULTYPE_TRAP_UD_FORCED;
6975 return kvm_emulate_instruction(vcpu, emul_type);
6977 EXPORT_SYMBOL_GPL(handle_ud);
6979 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6980 gpa_t gpa, bool write)
6982 /* For APIC access vmexit */
6983 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6986 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
6987 trace_vcpu_match_mmio(gva, gpa, write, true);
6994 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6995 gpa_t *gpa, struct x86_exception *exception,
6998 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6999 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7000 | (write ? PFERR_WRITE_MASK : 0);
7003 * currently PKRU is only applied to ept enabled guest so
7004 * there is no pkey in EPT page table for L1 guest or EPT
7005 * shadow page table for L2 guest.
7007 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7008 !permission_fault(vcpu, vcpu->arch.walk_mmu,
7009 vcpu->arch.mmio_access, 0, access))) {
7010 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7011 (gva & (PAGE_SIZE - 1));
7012 trace_vcpu_match_mmio(gva, *gpa, write, false);
7016 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7018 if (*gpa == UNMAPPED_GVA)
7021 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7024 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7025 const void *val, int bytes)
7029 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7032 kvm_page_track_write(vcpu, gpa, val, bytes);
7036 struct read_write_emulator_ops {
7037 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7039 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7040 void *val, int bytes);
7041 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7042 int bytes, void *val);
7043 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7044 void *val, int bytes);
7048 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7050 if (vcpu->mmio_read_completed) {
7051 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7052 vcpu->mmio_fragments[0].gpa, val);
7053 vcpu->mmio_read_completed = 0;
7060 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7061 void *val, int bytes)
7063 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7066 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7067 void *val, int bytes)
7069 return emulator_write_phys(vcpu, gpa, val, bytes);
7072 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7074 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7075 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7078 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7079 void *val, int bytes)
7081 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7082 return X86EMUL_IO_NEEDED;
7085 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7086 void *val, int bytes)
7088 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7090 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7091 return X86EMUL_CONTINUE;
7094 static const struct read_write_emulator_ops read_emultor = {
7095 .read_write_prepare = read_prepare,
7096 .read_write_emulate = read_emulate,
7097 .read_write_mmio = vcpu_mmio_read,
7098 .read_write_exit_mmio = read_exit_mmio,
7101 static const struct read_write_emulator_ops write_emultor = {
7102 .read_write_emulate = write_emulate,
7103 .read_write_mmio = write_mmio,
7104 .read_write_exit_mmio = write_exit_mmio,
7108 static int emulator_read_write_onepage(unsigned long addr, void *val,
7110 struct x86_exception *exception,
7111 struct kvm_vcpu *vcpu,
7112 const struct read_write_emulator_ops *ops)
7116 bool write = ops->write;
7117 struct kvm_mmio_fragment *frag;
7118 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7121 * If the exit was due to a NPF we may already have a GPA.
7122 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7123 * Note, this cannot be used on string operations since string
7124 * operation using rep will only have the initial GPA from the NPF
7127 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7128 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7129 gpa = ctxt->gpa_val;
7130 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7132 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7134 return X86EMUL_PROPAGATE_FAULT;
7137 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7138 return X86EMUL_CONTINUE;
7141 * Is this MMIO handled locally?
7143 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7144 if (handled == bytes)
7145 return X86EMUL_CONTINUE;
7151 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7152 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7156 return X86EMUL_CONTINUE;
7159 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7161 void *val, unsigned int bytes,
7162 struct x86_exception *exception,
7163 const struct read_write_emulator_ops *ops)
7165 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7169 if (ops->read_write_prepare &&
7170 ops->read_write_prepare(vcpu, val, bytes))
7171 return X86EMUL_CONTINUE;
7173 vcpu->mmio_nr_fragments = 0;
7175 /* Crossing a page boundary? */
7176 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7179 now = -addr & ~PAGE_MASK;
7180 rc = emulator_read_write_onepage(addr, val, now, exception,
7183 if (rc != X86EMUL_CONTINUE)
7186 if (ctxt->mode != X86EMUL_MODE_PROT64)
7192 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7194 if (rc != X86EMUL_CONTINUE)
7197 if (!vcpu->mmio_nr_fragments)
7200 gpa = vcpu->mmio_fragments[0].gpa;
7202 vcpu->mmio_needed = 1;
7203 vcpu->mmio_cur_fragment = 0;
7205 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7206 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7207 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7208 vcpu->run->mmio.phys_addr = gpa;
7210 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7213 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7217 struct x86_exception *exception)
7219 return emulator_read_write(ctxt, addr, val, bytes,
7220 exception, &read_emultor);
7223 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7227 struct x86_exception *exception)
7229 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7230 exception, &write_emultor);
7233 #define CMPXCHG_TYPE(t, ptr, old, new) \
7234 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
7236 #ifdef CONFIG_X86_64
7237 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
7239 # define CMPXCHG64(ptr, old, new) \
7240 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
7243 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7248 struct x86_exception *exception)
7250 struct kvm_host_map map;
7251 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7257 /* guests cmpxchg8b have to be emulated atomically */
7258 if (bytes > 8 || (bytes & (bytes - 1)))
7261 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7263 if (gpa == UNMAPPED_GVA ||
7264 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7268 * Emulate the atomic as a straight write to avoid #AC if SLD is
7269 * enabled in the host and the access splits a cache line.
7271 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7272 page_line_mask = ~(cache_line_size() - 1);
7274 page_line_mask = PAGE_MASK;
7276 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7279 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
7282 kaddr = map.hva + offset_in_page(gpa);
7286 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
7289 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
7292 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
7295 exchanged = CMPXCHG64(kaddr, old, new);
7301 kvm_vcpu_unmap(vcpu, &map, true);
7304 return X86EMUL_CMPXCHG_FAILED;
7306 kvm_page_track_write(vcpu, gpa, new, bytes);
7308 return X86EMUL_CONTINUE;
7311 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
7313 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
7316 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
7320 for (i = 0; i < vcpu->arch.pio.count; i++) {
7321 if (vcpu->arch.pio.in)
7322 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
7323 vcpu->arch.pio.size, pd);
7325 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
7326 vcpu->arch.pio.port, vcpu->arch.pio.size,
7330 pd += vcpu->arch.pio.size;
7335 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
7336 unsigned short port,
7337 unsigned int count, bool in)
7339 vcpu->arch.pio.port = port;
7340 vcpu->arch.pio.in = in;
7341 vcpu->arch.pio.count = count;
7342 vcpu->arch.pio.size = size;
7344 if (!kernel_pio(vcpu, vcpu->arch.pio_data))
7347 vcpu->run->exit_reason = KVM_EXIT_IO;
7348 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
7349 vcpu->run->io.size = size;
7350 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
7351 vcpu->run->io.count = count;
7352 vcpu->run->io.port = port;
7357 static int __emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7358 unsigned short port, unsigned int count)
7360 WARN_ON(vcpu->arch.pio.count);
7361 memset(vcpu->arch.pio_data, 0, size * count);
7362 return emulator_pio_in_out(vcpu, size, port, count, true);
7365 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
7367 int size = vcpu->arch.pio.size;
7368 unsigned count = vcpu->arch.pio.count;
7369 memcpy(val, vcpu->arch.pio_data, size * count);
7370 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
7371 vcpu->arch.pio.count = 0;
7374 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7375 unsigned short port, void *val, unsigned int count)
7377 if (vcpu->arch.pio.count) {
7379 * Complete a previous iteration that required userspace I/O.
7380 * Note, @count isn't guaranteed to match pio.count as userspace
7381 * can modify ECX before rerunning the vCPU. Ignore any such
7382 * shenanigans as KVM doesn't support modifying the rep count,
7383 * and the emulator ensures @count doesn't overflow the buffer.
7386 int r = __emulator_pio_in(vcpu, size, port, count);
7390 /* Results already available, fall through. */
7393 complete_emulator_pio_in(vcpu, val);
7397 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
7398 int size, unsigned short port, void *val,
7401 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
7405 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
7406 unsigned short port, const void *val,
7411 memcpy(vcpu->arch.pio_data, val, size * count);
7412 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
7413 ret = emulator_pio_in_out(vcpu, size, port, count, false);
7415 vcpu->arch.pio.count = 0;
7420 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
7421 int size, unsigned short port,
7422 const void *val, unsigned int count)
7424 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
7427 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
7429 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
7432 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
7434 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
7437 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
7439 if (!need_emulate_wbinvd(vcpu))
7440 return X86EMUL_CONTINUE;
7442 if (static_call(kvm_x86_has_wbinvd_exit)()) {
7443 int cpu = get_cpu();
7445 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
7446 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
7447 wbinvd_ipi, NULL, 1);
7449 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
7452 return X86EMUL_CONTINUE;
7455 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
7457 kvm_emulate_wbinvd_noskip(vcpu);
7458 return kvm_skip_emulated_instruction(vcpu);
7460 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
7464 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
7466 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
7469 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
7470 unsigned long *dest)
7472 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
7475 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
7476 unsigned long value)
7479 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
7482 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
7484 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
7487 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
7489 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7490 unsigned long value;
7494 value = kvm_read_cr0(vcpu);
7497 value = vcpu->arch.cr2;
7500 value = kvm_read_cr3(vcpu);
7503 value = kvm_read_cr4(vcpu);
7506 value = kvm_get_cr8(vcpu);
7509 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7516 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
7518 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7523 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
7526 vcpu->arch.cr2 = val;
7529 res = kvm_set_cr3(vcpu, val);
7532 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
7535 res = kvm_set_cr8(vcpu, val);
7538 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7545 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
7547 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
7550 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7552 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
7555 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7557 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
7560 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7562 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
7565 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7567 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
7570 static unsigned long emulator_get_cached_segment_base(
7571 struct x86_emulate_ctxt *ctxt, int seg)
7573 return get_segment_base(emul_to_vcpu(ctxt), seg);
7576 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
7577 struct desc_struct *desc, u32 *base3,
7580 struct kvm_segment var;
7582 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
7583 *selector = var.selector;
7586 memset(desc, 0, sizeof(*desc));
7594 set_desc_limit(desc, var.limit);
7595 set_desc_base(desc, (unsigned long)var.base);
7596 #ifdef CONFIG_X86_64
7598 *base3 = var.base >> 32;
7600 desc->type = var.type;
7602 desc->dpl = var.dpl;
7603 desc->p = var.present;
7604 desc->avl = var.avl;
7612 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
7613 struct desc_struct *desc, u32 base3,
7616 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7617 struct kvm_segment var;
7619 var.selector = selector;
7620 var.base = get_desc_base(desc);
7621 #ifdef CONFIG_X86_64
7622 var.base |= ((u64)base3) << 32;
7624 var.limit = get_desc_limit(desc);
7626 var.limit = (var.limit << 12) | 0xfff;
7627 var.type = desc->type;
7628 var.dpl = desc->dpl;
7633 var.avl = desc->avl;
7634 var.present = desc->p;
7635 var.unusable = !var.present;
7638 kvm_set_segment(vcpu, &var, seg);
7642 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
7643 u32 msr_index, u64 *pdata)
7645 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7648 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
7650 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
7651 complete_emulated_rdmsr, r)) {
7652 /* Bounce to user space */
7653 return X86EMUL_IO_NEEDED;
7659 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
7660 u32 msr_index, u64 data)
7662 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7665 r = kvm_set_msr_with_filter(vcpu, msr_index, data);
7667 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
7668 complete_emulated_msr_access, r)) {
7669 /* Bounce to user space */
7670 return X86EMUL_IO_NEEDED;
7676 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
7677 u32 msr_index, u64 *pdata)
7679 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
7682 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
7683 u32 msr_index, u64 data)
7685 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
7688 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
7690 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7692 return vcpu->arch.smbase;
7695 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
7697 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7699 vcpu->arch.smbase = smbase;
7702 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
7705 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
7710 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
7711 u32 pmc, u64 *pdata)
7713 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
7716 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
7718 emul_to_vcpu(ctxt)->arch.halt_request = 1;
7721 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
7722 struct x86_instruction_info *info,
7723 enum x86_intercept_stage stage)
7725 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
7729 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
7730 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
7733 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
7736 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
7738 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
7741 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
7743 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
7746 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
7748 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
7751 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
7753 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
7756 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
7758 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
7761 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
7763 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
7766 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
7768 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
7771 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
7773 return emul_to_vcpu(ctxt)->arch.hflags;
7776 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt)
7778 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7780 kvm_smm_changed(vcpu, false);
7783 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt,
7784 const char *smstate)
7786 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate);
7789 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
7791 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
7794 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
7796 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
7799 static const struct x86_emulate_ops emulate_ops = {
7800 .read_gpr = emulator_read_gpr,
7801 .write_gpr = emulator_write_gpr,
7802 .read_std = emulator_read_std,
7803 .write_std = emulator_write_std,
7804 .read_phys = kvm_read_guest_phys_system,
7805 .fetch = kvm_fetch_guest_virt,
7806 .read_emulated = emulator_read_emulated,
7807 .write_emulated = emulator_write_emulated,
7808 .cmpxchg_emulated = emulator_cmpxchg_emulated,
7809 .invlpg = emulator_invlpg,
7810 .pio_in_emulated = emulator_pio_in_emulated,
7811 .pio_out_emulated = emulator_pio_out_emulated,
7812 .get_segment = emulator_get_segment,
7813 .set_segment = emulator_set_segment,
7814 .get_cached_segment_base = emulator_get_cached_segment_base,
7815 .get_gdt = emulator_get_gdt,
7816 .get_idt = emulator_get_idt,
7817 .set_gdt = emulator_set_gdt,
7818 .set_idt = emulator_set_idt,
7819 .get_cr = emulator_get_cr,
7820 .set_cr = emulator_set_cr,
7821 .cpl = emulator_get_cpl,
7822 .get_dr = emulator_get_dr,
7823 .set_dr = emulator_set_dr,
7824 .get_smbase = emulator_get_smbase,
7825 .set_smbase = emulator_set_smbase,
7826 .set_msr_with_filter = emulator_set_msr_with_filter,
7827 .get_msr_with_filter = emulator_get_msr_with_filter,
7828 .set_msr = emulator_set_msr,
7829 .get_msr = emulator_get_msr,
7830 .check_pmc = emulator_check_pmc,
7831 .read_pmc = emulator_read_pmc,
7832 .halt = emulator_halt,
7833 .wbinvd = emulator_wbinvd,
7834 .fix_hypercall = emulator_fix_hypercall,
7835 .intercept = emulator_intercept,
7836 .get_cpuid = emulator_get_cpuid,
7837 .guest_has_long_mode = emulator_guest_has_long_mode,
7838 .guest_has_movbe = emulator_guest_has_movbe,
7839 .guest_has_fxsr = emulator_guest_has_fxsr,
7840 .guest_has_rdpid = emulator_guest_has_rdpid,
7841 .set_nmi_mask = emulator_set_nmi_mask,
7842 .get_hflags = emulator_get_hflags,
7843 .exiting_smm = emulator_exiting_smm,
7844 .leave_smm = emulator_leave_smm,
7845 .triple_fault = emulator_triple_fault,
7846 .set_xcr = emulator_set_xcr,
7849 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
7851 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
7853 * an sti; sti; sequence only disable interrupts for the first
7854 * instruction. So, if the last instruction, be it emulated or
7855 * not, left the system with the INT_STI flag enabled, it
7856 * means that the last instruction is an sti. We should not
7857 * leave the flag on in this case. The same goes for mov ss
7859 if (int_shadow & mask)
7861 if (unlikely(int_shadow || mask)) {
7862 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
7864 kvm_make_request(KVM_REQ_EVENT, vcpu);
7868 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
7870 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7871 if (ctxt->exception.vector == PF_VECTOR)
7872 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
7874 if (ctxt->exception.error_code_valid)
7875 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
7876 ctxt->exception.error_code);
7878 kvm_queue_exception(vcpu, ctxt->exception.vector);
7882 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
7884 struct x86_emulate_ctxt *ctxt;
7886 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
7888 pr_err("kvm: failed to allocate vcpu's emulator\n");
7893 ctxt->ops = &emulate_ops;
7894 vcpu->arch.emulate_ctxt = ctxt;
7899 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
7901 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7904 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
7906 ctxt->gpa_available = false;
7907 ctxt->eflags = kvm_get_rflags(vcpu);
7908 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
7910 ctxt->eip = kvm_rip_read(vcpu);
7911 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
7912 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
7913 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
7914 cs_db ? X86EMUL_MODE_PROT32 :
7915 X86EMUL_MODE_PROT16;
7916 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
7917 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
7918 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
7920 ctxt->interruptibility = 0;
7921 ctxt->have_exception = false;
7922 ctxt->exception.vector = -1;
7923 ctxt->perm_ok = false;
7925 init_decode_cache(ctxt);
7926 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7929 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
7931 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7934 init_emulate_ctxt(vcpu);
7938 ctxt->_eip = ctxt->eip + inc_eip;
7939 ret = emulate_int_real(ctxt, irq);
7941 if (ret != X86EMUL_CONTINUE) {
7942 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7944 ctxt->eip = ctxt->_eip;
7945 kvm_rip_write(vcpu, ctxt->eip);
7946 kvm_set_rflags(vcpu, ctxt->eflags);
7949 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
7951 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
7952 u8 ndata, u8 *insn_bytes, u8 insn_size)
7954 struct kvm_run *run = vcpu->run;
7959 * Zero the whole array used to retrieve the exit info, as casting to
7960 * u32 for select entries will leave some chunks uninitialized.
7962 memset(&info, 0, sizeof(info));
7964 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
7965 &info[2], (u32 *)&info[3],
7968 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7969 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
7972 * There's currently space for 13 entries, but 5 are used for the exit
7973 * reason and info. Restrict to 4 to reduce the maintenance burden
7974 * when expanding kvm_run.emulation_failure in the future.
7976 if (WARN_ON_ONCE(ndata > 4))
7979 /* Always include the flags as a 'data' entry. */
7981 run->emulation_failure.flags = 0;
7984 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
7985 sizeof(run->emulation_failure.insn_bytes) != 16));
7987 run->emulation_failure.flags |=
7988 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
7989 run->emulation_failure.insn_size = insn_size;
7990 memset(run->emulation_failure.insn_bytes, 0x90,
7991 sizeof(run->emulation_failure.insn_bytes));
7992 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
7995 memcpy(&run->internal.data[info_start], info, sizeof(info));
7996 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
7997 ndata * sizeof(data[0]));
7999 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8002 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8004 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8006 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8007 ctxt->fetch.end - ctxt->fetch.data);
8010 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8013 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8015 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8017 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8019 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8021 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8023 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8025 struct kvm *kvm = vcpu->kvm;
8027 ++vcpu->stat.insn_emulation_fail;
8028 trace_kvm_emulate_insn_failed(vcpu);
8030 if (emulation_type & EMULTYPE_VMWARE_GP) {
8031 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8035 if (kvm->arch.exit_on_emulation_error ||
8036 (emulation_type & EMULTYPE_SKIP)) {
8037 prepare_emulation_ctxt_failure_exit(vcpu);
8041 kvm_queue_exception(vcpu, UD_VECTOR);
8043 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8044 prepare_emulation_ctxt_failure_exit(vcpu);
8051 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8052 bool write_fault_to_shadow_pgtable,
8055 gpa_t gpa = cr2_or_gpa;
8058 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8061 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8062 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8065 if (!vcpu->arch.mmu->direct_map) {
8067 * Write permission should be allowed since only
8068 * write access need to be emulated.
8070 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8073 * If the mapping is invalid in guest, let cpu retry
8074 * it to generate fault.
8076 if (gpa == UNMAPPED_GVA)
8081 * Do not retry the unhandleable instruction if it faults on the
8082 * readonly host memory, otherwise it will goto a infinite loop:
8083 * retry instruction -> write #PF -> emulation fail -> retry
8084 * instruction -> ...
8086 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8089 * If the instruction failed on the error pfn, it can not be fixed,
8090 * report the error to userspace.
8092 if (is_error_noslot_pfn(pfn))
8095 kvm_release_pfn_clean(pfn);
8097 /* The instructions are well-emulated on direct mmu. */
8098 if (vcpu->arch.mmu->direct_map) {
8099 unsigned int indirect_shadow_pages;
8101 write_lock(&vcpu->kvm->mmu_lock);
8102 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8103 write_unlock(&vcpu->kvm->mmu_lock);
8105 if (indirect_shadow_pages)
8106 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8112 * if emulation was due to access to shadowed page table
8113 * and it failed try to unshadow page and re-enter the
8114 * guest to let CPU execute the instruction.
8116 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8119 * If the access faults on its page table, it can not
8120 * be fixed by unprotecting shadow page and it should
8121 * be reported to userspace.
8123 return !write_fault_to_shadow_pgtable;
8126 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8127 gpa_t cr2_or_gpa, int emulation_type)
8129 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8130 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8132 last_retry_eip = vcpu->arch.last_retry_eip;
8133 last_retry_addr = vcpu->arch.last_retry_addr;
8136 * If the emulation is caused by #PF and it is non-page_table
8137 * writing instruction, it means the VM-EXIT is caused by shadow
8138 * page protected, we can zap the shadow page and retry this
8139 * instruction directly.
8141 * Note: if the guest uses a non-page-table modifying instruction
8142 * on the PDE that points to the instruction, then we will unmap
8143 * the instruction and go to an infinite loop. So, we cache the
8144 * last retried eip and the last fault address, if we meet the eip
8145 * and the address again, we can break out of the potential infinite
8148 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8150 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8153 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8154 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8157 if (x86_page_table_writing_insn(ctxt))
8160 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8163 vcpu->arch.last_retry_eip = ctxt->eip;
8164 vcpu->arch.last_retry_addr = cr2_or_gpa;
8166 if (!vcpu->arch.mmu->direct_map)
8167 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8169 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8174 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8175 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8177 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm)
8179 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm);
8182 vcpu->arch.hflags |= HF_SMM_MASK;
8184 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK);
8186 /* Process a latched INIT or SMI, if any. */
8187 kvm_make_request(KVM_REQ_EVENT, vcpu);
8190 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band,
8191 * on SMM exit we still need to reload them from
8194 vcpu->arch.pdptrs_from_userspace = false;
8197 kvm_mmu_reset_context(vcpu);
8200 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8209 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8210 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8215 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8217 struct kvm_run *kvm_run = vcpu->run;
8219 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8220 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8221 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8222 kvm_run->debug.arch.exception = DB_VECTOR;
8223 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8226 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8230 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8232 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8235 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8239 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8242 * rflags is the old, "raw" value of the flags. The new value has
8243 * not been saved yet.
8245 * This is correct even for TF set by the guest, because "the
8246 * processor will not generate this exception after the instruction
8247 * that sets the TF flag".
8249 if (unlikely(rflags & X86_EFLAGS_TF))
8250 r = kvm_vcpu_do_singlestep(vcpu);
8253 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8255 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
8257 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8258 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8259 struct kvm_run *kvm_run = vcpu->run;
8260 unsigned long eip = kvm_get_linear_rip(vcpu);
8261 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8262 vcpu->arch.guest_debug_dr7,
8266 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8267 kvm_run->debug.arch.pc = eip;
8268 kvm_run->debug.arch.exception = DB_VECTOR;
8269 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8275 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8276 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
8277 unsigned long eip = kvm_get_linear_rip(vcpu);
8278 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8283 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
8292 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
8294 switch (ctxt->opcode_len) {
8301 case 0xe6: /* OUT */
8305 case 0x6c: /* INS */
8307 case 0x6e: /* OUTS */
8314 case 0x33: /* RDPMC */
8324 * Decode to be emulated instruction. Return EMULATION_OK if success.
8326 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
8327 void *insn, int insn_len)
8329 int r = EMULATION_OK;
8330 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8332 init_emulate_ctxt(vcpu);
8335 * We will reenter on the same instruction since we do not set
8336 * complete_userspace_io. This does not handle watchpoints yet,
8337 * those would be handled in the emulate_ops.
8339 if (!(emulation_type & EMULTYPE_SKIP) &&
8340 kvm_vcpu_check_breakpoint(vcpu, &r))
8343 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
8345 trace_kvm_emulate_insn_start(vcpu);
8346 ++vcpu->stat.insn_emulation;
8350 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
8352 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8353 int emulation_type, void *insn, int insn_len)
8356 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8357 bool writeback = true;
8358 bool write_fault_to_spt;
8360 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len)))
8363 vcpu->arch.l1tf_flush_l1d = true;
8366 * Clear write_fault_to_shadow_pgtable here to ensure it is
8369 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
8370 vcpu->arch.write_fault_to_shadow_pgtable = false;
8372 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8373 kvm_clear_exception_queue(vcpu);
8375 r = x86_decode_emulated_instruction(vcpu, emulation_type,
8377 if (r != EMULATION_OK) {
8378 if ((emulation_type & EMULTYPE_TRAP_UD) ||
8379 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
8380 kvm_queue_exception(vcpu, UD_VECTOR);
8383 if (reexecute_instruction(vcpu, cr2_or_gpa,
8387 if (ctxt->have_exception) {
8389 * #UD should result in just EMULATION_FAILED, and trap-like
8390 * exception should not be encountered during decode.
8392 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
8393 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8394 inject_emulated_exception(vcpu);
8397 return handle_emulation_failure(vcpu, emulation_type);
8401 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
8402 !is_vmware_backdoor_opcode(ctxt)) {
8403 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8408 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
8409 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
8410 * The caller is responsible for updating interruptibility state and
8411 * injecting single-step #DBs.
8413 if (emulation_type & EMULTYPE_SKIP) {
8414 if (ctxt->mode != X86EMUL_MODE_PROT64)
8415 ctxt->eip = (u32)ctxt->_eip;
8417 ctxt->eip = ctxt->_eip;
8419 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
8424 kvm_rip_write(vcpu, ctxt->eip);
8425 if (ctxt->eflags & X86_EFLAGS_RF)
8426 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
8430 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
8433 /* this is needed for vmware backdoor interface to work since it
8434 changes registers values during IO operation */
8435 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
8436 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8437 emulator_invalidate_register_cache(ctxt);
8441 if (emulation_type & EMULTYPE_PF) {
8442 /* Save the faulting GPA (cr2) in the address field */
8443 ctxt->exception.address = cr2_or_gpa;
8445 /* With shadow page tables, cr2 contains a GVA or nGPA. */
8446 if (vcpu->arch.mmu->direct_map) {
8447 ctxt->gpa_available = true;
8448 ctxt->gpa_val = cr2_or_gpa;
8451 /* Sanitize the address out of an abundance of paranoia. */
8452 ctxt->exception.address = 0;
8455 r = x86_emulate_insn(ctxt);
8457 if (r == EMULATION_INTERCEPTED)
8460 if (r == EMULATION_FAILED) {
8461 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
8465 return handle_emulation_failure(vcpu, emulation_type);
8468 if (ctxt->have_exception) {
8470 if (inject_emulated_exception(vcpu))
8472 } else if (vcpu->arch.pio.count) {
8473 if (!vcpu->arch.pio.in) {
8474 /* FIXME: return into emulator if single-stepping. */
8475 vcpu->arch.pio.count = 0;
8478 vcpu->arch.complete_userspace_io = complete_emulated_pio;
8481 } else if (vcpu->mmio_needed) {
8482 ++vcpu->stat.mmio_exits;
8484 if (!vcpu->mmio_is_write)
8487 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8488 } else if (vcpu->arch.complete_userspace_io) {
8491 } else if (r == EMULATION_RESTART)
8498 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8499 toggle_interruptibility(vcpu, ctxt->interruptibility);
8500 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8501 if (!ctxt->have_exception ||
8502 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
8503 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8504 if (ctxt->is_branch)
8505 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
8506 kvm_rip_write(vcpu, ctxt->eip);
8507 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
8508 r = kvm_vcpu_do_singlestep(vcpu);
8509 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
8510 __kvm_set_rflags(vcpu, ctxt->eflags);
8514 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
8515 * do nothing, and it will be requested again as soon as
8516 * the shadow expires. But we still need to check here,
8517 * because POPF has no interrupt shadow.
8519 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
8520 kvm_make_request(KVM_REQ_EVENT, vcpu);
8522 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
8527 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
8529 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
8531 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
8533 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
8534 void *insn, int insn_len)
8536 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
8538 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
8540 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
8542 vcpu->arch.pio.count = 0;
8546 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
8548 vcpu->arch.pio.count = 0;
8550 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
8553 return kvm_skip_emulated_instruction(vcpu);
8556 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
8557 unsigned short port)
8559 unsigned long val = kvm_rax_read(vcpu);
8560 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
8566 * Workaround userspace that relies on old KVM behavior of %rip being
8567 * incremented prior to exiting to userspace to handle "OUT 0x7e".
8570 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
8571 vcpu->arch.complete_userspace_io =
8572 complete_fast_pio_out_port_0x7e;
8573 kvm_skip_emulated_instruction(vcpu);
8575 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8576 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
8581 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
8585 /* We should only ever be called with arch.pio.count equal to 1 */
8586 BUG_ON(vcpu->arch.pio.count != 1);
8588 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
8589 vcpu->arch.pio.count = 0;
8593 /* For size less than 4 we merge, else we zero extend */
8594 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8597 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
8598 * the copy and tracing
8600 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
8601 kvm_rax_write(vcpu, val);
8603 return kvm_skip_emulated_instruction(vcpu);
8606 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
8607 unsigned short port)
8612 /* For size less than 4 we merge, else we zero extend */
8613 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8615 ret = emulator_pio_in(vcpu, size, port, &val, 1);
8617 kvm_rax_write(vcpu, val);
8621 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8622 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
8627 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
8632 ret = kvm_fast_pio_in(vcpu, size, port);
8634 ret = kvm_fast_pio_out(vcpu, size, port);
8635 return ret && kvm_skip_emulated_instruction(vcpu);
8637 EXPORT_SYMBOL_GPL(kvm_fast_pio);
8639 static int kvmclock_cpu_down_prep(unsigned int cpu)
8641 __this_cpu_write(cpu_tsc_khz, 0);
8645 static void tsc_khz_changed(void *data)
8647 struct cpufreq_freqs *freq = data;
8648 unsigned long khz = 0;
8652 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
8653 khz = cpufreq_quick_get(raw_smp_processor_id());
8656 __this_cpu_write(cpu_tsc_khz, khz);
8659 #ifdef CONFIG_X86_64
8660 static void kvm_hyperv_tsc_notifier(void)
8665 mutex_lock(&kvm_lock);
8666 list_for_each_entry(kvm, &vm_list, vm_list)
8667 kvm_make_mclock_inprogress_request(kvm);
8669 /* no guest entries from this point */
8670 hyperv_stop_tsc_emulation();
8672 /* TSC frequency always matches when on Hyper-V */
8673 for_each_present_cpu(cpu)
8674 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
8675 kvm_max_guest_tsc_khz = tsc_khz;
8677 list_for_each_entry(kvm, &vm_list, vm_list) {
8678 __kvm_start_pvclock_update(kvm);
8679 pvclock_update_vm_gtod_copy(kvm);
8680 kvm_end_pvclock_update(kvm);
8683 mutex_unlock(&kvm_lock);
8687 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
8690 struct kvm_vcpu *vcpu;
8695 * We allow guests to temporarily run on slowing clocks,
8696 * provided we notify them after, or to run on accelerating
8697 * clocks, provided we notify them before. Thus time never
8700 * However, we have a problem. We can't atomically update
8701 * the frequency of a given CPU from this function; it is
8702 * merely a notifier, which can be called from any CPU.
8703 * Changing the TSC frequency at arbitrary points in time
8704 * requires a recomputation of local variables related to
8705 * the TSC for each VCPU. We must flag these local variables
8706 * to be updated and be sure the update takes place with the
8707 * new frequency before any guests proceed.
8709 * Unfortunately, the combination of hotplug CPU and frequency
8710 * change creates an intractable locking scenario; the order
8711 * of when these callouts happen is undefined with respect to
8712 * CPU hotplug, and they can race with each other. As such,
8713 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
8714 * undefined; you can actually have a CPU frequency change take
8715 * place in between the computation of X and the setting of the
8716 * variable. To protect against this problem, all updates of
8717 * the per_cpu tsc_khz variable are done in an interrupt
8718 * protected IPI, and all callers wishing to update the value
8719 * must wait for a synchronous IPI to complete (which is trivial
8720 * if the caller is on the CPU already). This establishes the
8721 * necessary total order on variable updates.
8723 * Note that because a guest time update may take place
8724 * anytime after the setting of the VCPU's request bit, the
8725 * correct TSC value must be set before the request. However,
8726 * to ensure the update actually makes it to any guest which
8727 * starts running in hardware virtualization between the set
8728 * and the acquisition of the spinlock, we must also ping the
8729 * CPU after setting the request bit.
8733 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
8735 mutex_lock(&kvm_lock);
8736 list_for_each_entry(kvm, &vm_list, vm_list) {
8737 kvm_for_each_vcpu(i, vcpu, kvm) {
8738 if (vcpu->cpu != cpu)
8740 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8741 if (vcpu->cpu != raw_smp_processor_id())
8745 mutex_unlock(&kvm_lock);
8747 if (freq->old < freq->new && send_ipi) {
8749 * We upscale the frequency. Must make the guest
8750 * doesn't see old kvmclock values while running with
8751 * the new frequency, otherwise we risk the guest sees
8752 * time go backwards.
8754 * In case we update the frequency for another cpu
8755 * (which might be in guest context) send an interrupt
8756 * to kick the cpu out of guest context. Next time
8757 * guest context is entered kvmclock will be updated,
8758 * so the guest will not see stale values.
8760 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
8764 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
8767 struct cpufreq_freqs *freq = data;
8770 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
8772 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
8775 for_each_cpu(cpu, freq->policy->cpus)
8776 __kvmclock_cpufreq_notifier(freq, cpu);
8781 static struct notifier_block kvmclock_cpufreq_notifier_block = {
8782 .notifier_call = kvmclock_cpufreq_notifier
8785 static int kvmclock_cpu_online(unsigned int cpu)
8787 tsc_khz_changed(NULL);
8791 static void kvm_timer_init(void)
8793 max_tsc_khz = tsc_khz;
8795 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
8796 #ifdef CONFIG_CPU_FREQ
8797 struct cpufreq_policy *policy;
8801 policy = cpufreq_cpu_get(cpu);
8803 if (policy->cpuinfo.max_freq)
8804 max_tsc_khz = policy->cpuinfo.max_freq;
8805 cpufreq_cpu_put(policy);
8809 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
8810 CPUFREQ_TRANSITION_NOTIFIER);
8813 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
8814 kvmclock_cpu_online, kvmclock_cpu_down_prep);
8817 #ifdef CONFIG_X86_64
8818 static void pvclock_gtod_update_fn(struct work_struct *work)
8821 struct kvm_vcpu *vcpu;
8824 mutex_lock(&kvm_lock);
8825 list_for_each_entry(kvm, &vm_list, vm_list)
8826 kvm_for_each_vcpu(i, vcpu, kvm)
8827 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
8828 atomic_set(&kvm_guest_has_master_clock, 0);
8829 mutex_unlock(&kvm_lock);
8832 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
8835 * Indirection to move queue_work() out of the tk_core.seq write held
8836 * region to prevent possible deadlocks against time accessors which
8837 * are invoked with work related locks held.
8839 static void pvclock_irq_work_fn(struct irq_work *w)
8841 queue_work(system_long_wq, &pvclock_gtod_work);
8844 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
8847 * Notification about pvclock gtod data update.
8849 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
8852 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
8853 struct timekeeper *tk = priv;
8855 update_pvclock_gtod(tk);
8858 * Disable master clock if host does not trust, or does not use,
8859 * TSC based clocksource. Delegate queue_work() to irq_work as
8860 * this is invoked with tk_core.seq write held.
8862 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
8863 atomic_read(&kvm_guest_has_master_clock) != 0)
8864 irq_work_queue(&pvclock_irq_work);
8868 static struct notifier_block pvclock_gtod_notifier = {
8869 .notifier_call = pvclock_gtod_notify,
8873 int kvm_arch_init(void *opaque)
8875 struct kvm_x86_init_ops *ops = opaque;
8878 if (kvm_x86_ops.hardware_enable) {
8879 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name);
8884 if (!ops->cpu_has_kvm_support()) {
8885 pr_err_ratelimited("kvm: no hardware support for '%s'\n",
8886 ops->runtime_ops->name);
8890 if (ops->disabled_by_bios()) {
8891 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n",
8892 ops->runtime_ops->name);
8898 * KVM explicitly assumes that the guest has an FPU and
8899 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
8900 * vCPU's FPU state as a fxregs_state struct.
8902 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
8903 printk(KERN_ERR "kvm: inadequate fpu\n");
8908 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
8909 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
8916 x86_emulator_cache = kvm_alloc_emulator_cache();
8917 if (!x86_emulator_cache) {
8918 pr_err("kvm: failed to allocate cache for x86 emulator\n");
8922 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
8923 if (!user_return_msrs) {
8924 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
8925 goto out_free_x86_emulator_cache;
8927 kvm_nr_uret_msrs = 0;
8929 r = kvm_mmu_module_init();
8931 goto out_free_percpu;
8935 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
8936 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
8937 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
8940 if (pi_inject_timer == -1)
8941 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
8942 #ifdef CONFIG_X86_64
8943 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
8945 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
8946 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
8952 free_percpu(user_return_msrs);
8953 out_free_x86_emulator_cache:
8954 kmem_cache_destroy(x86_emulator_cache);
8959 void kvm_arch_exit(void)
8961 #ifdef CONFIG_X86_64
8962 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
8963 clear_hv_tscchange_cb();
8967 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
8968 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
8969 CPUFREQ_TRANSITION_NOTIFIER);
8970 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
8971 #ifdef CONFIG_X86_64
8972 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
8973 irq_work_sync(&pvclock_irq_work);
8974 cancel_work_sync(&pvclock_gtod_work);
8976 kvm_x86_ops.hardware_enable = NULL;
8977 kvm_mmu_module_exit();
8978 free_percpu(user_return_msrs);
8979 kmem_cache_destroy(x86_emulator_cache);
8980 #ifdef CONFIG_KVM_XEN
8981 static_key_deferred_flush(&kvm_xen_enabled);
8982 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
8986 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
8989 * The vCPU has halted, e.g. executed HLT. Update the run state if the
8990 * local APIC is in-kernel, the run loop will detect the non-runnable
8991 * state and halt the vCPU. Exit to userspace if the local APIC is
8992 * managed by userspace, in which case userspace is responsible for
8993 * handling wake events.
8995 ++vcpu->stat.halt_exits;
8996 if (lapic_in_kernel(vcpu)) {
8997 vcpu->arch.mp_state = state;
9000 vcpu->run->exit_reason = reason;
9005 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9007 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9009 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9011 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9013 int ret = kvm_skip_emulated_instruction(vcpu);
9015 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9016 * KVM_EXIT_DEBUG here.
9018 return kvm_emulate_halt_noskip(vcpu) && ret;
9020 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9022 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9024 int ret = kvm_skip_emulated_instruction(vcpu);
9026 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9027 KVM_EXIT_AP_RESET_HOLD) && ret;
9029 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9031 #ifdef CONFIG_X86_64
9032 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9033 unsigned long clock_type)
9035 struct kvm_clock_pairing clock_pairing;
9036 struct timespec64 ts;
9040 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9041 return -KVM_EOPNOTSUPP;
9044 * When tsc is in permanent catchup mode guests won't be able to use
9045 * pvclock_read_retry loop to get consistent view of pvclock
9047 if (vcpu->arch.tsc_always_catchup)
9048 return -KVM_EOPNOTSUPP;
9050 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9051 return -KVM_EOPNOTSUPP;
9053 clock_pairing.sec = ts.tv_sec;
9054 clock_pairing.nsec = ts.tv_nsec;
9055 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9056 clock_pairing.flags = 0;
9057 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9060 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9061 sizeof(struct kvm_clock_pairing)))
9069 * kvm_pv_kick_cpu_op: Kick a vcpu.
9071 * @apicid - apicid of vcpu to be kicked.
9073 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9075 struct kvm_lapic_irq lapic_irq;
9077 lapic_irq.shorthand = APIC_DEST_NOSHORT;
9078 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
9079 lapic_irq.level = 0;
9080 lapic_irq.dest_id = apicid;
9081 lapic_irq.msi_redir_hint = false;
9083 lapic_irq.delivery_mode = APIC_DM_REMRD;
9084 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9087 bool kvm_apicv_activated(struct kvm *kvm)
9089 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9091 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9094 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9095 enum kvm_apicv_inhibit reason, bool set)
9098 __set_bit(reason, inhibits);
9100 __clear_bit(reason, inhibits);
9102 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9105 static void kvm_apicv_init(struct kvm *kvm)
9107 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9109 init_rwsem(&kvm->arch.apicv_update_lock);
9111 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9114 set_or_clear_apicv_inhibit(inhibits,
9115 APICV_INHIBIT_REASON_ABSENT, true);
9118 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9120 struct kvm_vcpu *target = NULL;
9121 struct kvm_apic_map *map;
9123 vcpu->stat.directed_yield_attempted++;
9125 if (single_task_running())
9129 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9131 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9132 target = map->phys_map[dest_id]->vcpu;
9136 if (!target || !READ_ONCE(target->ready))
9139 /* Ignore requests to yield to self */
9143 if (kvm_vcpu_yield_to(target) <= 0)
9146 vcpu->stat.directed_yield_successful++;
9152 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
9154 u64 ret = vcpu->run->hypercall.ret;
9156 if (!is_64_bit_mode(vcpu))
9158 kvm_rax_write(vcpu, ret);
9159 ++vcpu->stat.hypercalls;
9160 return kvm_skip_emulated_instruction(vcpu);
9163 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
9165 unsigned long nr, a0, a1, a2, a3, ret;
9168 if (kvm_xen_hypercall_enabled(vcpu->kvm))
9169 return kvm_xen_hypercall(vcpu);
9171 if (kvm_hv_hypercall_enabled(vcpu))
9172 return kvm_hv_hypercall(vcpu);
9174 nr = kvm_rax_read(vcpu);
9175 a0 = kvm_rbx_read(vcpu);
9176 a1 = kvm_rcx_read(vcpu);
9177 a2 = kvm_rdx_read(vcpu);
9178 a3 = kvm_rsi_read(vcpu);
9180 trace_kvm_hypercall(nr, a0, a1, a2, a3);
9182 op_64_bit = is_64_bit_hypercall(vcpu);
9191 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
9199 case KVM_HC_VAPIC_POLL_IRQ:
9202 case KVM_HC_KICK_CPU:
9203 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
9206 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
9207 kvm_sched_yield(vcpu, a1);
9210 #ifdef CONFIG_X86_64
9211 case KVM_HC_CLOCK_PAIRING:
9212 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
9215 case KVM_HC_SEND_IPI:
9216 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
9219 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
9221 case KVM_HC_SCHED_YIELD:
9222 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
9225 kvm_sched_yield(vcpu, a0);
9228 case KVM_HC_MAP_GPA_RANGE: {
9229 u64 gpa = a0, npages = a1, attrs = a2;
9232 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
9235 if (!PAGE_ALIGNED(gpa) || !npages ||
9236 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
9241 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
9242 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
9243 vcpu->run->hypercall.args[0] = gpa;
9244 vcpu->run->hypercall.args[1] = npages;
9245 vcpu->run->hypercall.args[2] = attrs;
9246 vcpu->run->hypercall.longmode = op_64_bit;
9247 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
9257 kvm_rax_write(vcpu, ret);
9259 ++vcpu->stat.hypercalls;
9260 return kvm_skip_emulated_instruction(vcpu);
9262 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
9264 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
9266 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
9267 char instruction[3];
9268 unsigned long rip = kvm_rip_read(vcpu);
9270 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
9272 return emulator_write_emulated(ctxt, rip, instruction, 3,
9276 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
9278 return vcpu->run->request_interrupt_window &&
9279 likely(!pic_in_kernel(vcpu->kvm));
9282 /* Called within kvm->srcu read side. */
9283 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
9285 struct kvm_run *kvm_run = vcpu->run;
9287 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
9288 kvm_run->cr8 = kvm_get_cr8(vcpu);
9289 kvm_run->apic_base = kvm_get_apic_base(vcpu);
9291 kvm_run->ready_for_interrupt_injection =
9292 pic_in_kernel(vcpu->kvm) ||
9293 kvm_vcpu_ready_for_interrupt_injection(vcpu);
9296 kvm_run->flags |= KVM_RUN_X86_SMM;
9299 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
9303 if (!kvm_x86_ops.update_cr8_intercept)
9306 if (!lapic_in_kernel(vcpu))
9309 if (vcpu->arch.apicv_active)
9312 if (!vcpu->arch.apic->vapic_addr)
9313 max_irr = kvm_lapic_find_highest_irr(vcpu);
9320 tpr = kvm_lapic_get_cr8(vcpu);
9322 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
9326 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
9328 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9329 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9333 return kvm_x86_ops.nested_ops->check_events(vcpu);
9336 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
9338 if (vcpu->arch.exception.error_code && !is_protmode(vcpu))
9339 vcpu->arch.exception.error_code = false;
9340 static_call(kvm_x86_queue_exception)(vcpu);
9343 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
9346 bool can_inject = true;
9348 /* try to reinject previous events if any */
9350 if (vcpu->arch.exception.injected) {
9351 kvm_inject_exception(vcpu);
9355 * Do not inject an NMI or interrupt if there is a pending
9356 * exception. Exceptions and interrupts are recognized at
9357 * instruction boundaries, i.e. the start of an instruction.
9358 * Trap-like exceptions, e.g. #DB, have higher priority than
9359 * NMIs and interrupts, i.e. traps are recognized before an
9360 * NMI/interrupt that's pending on the same instruction.
9361 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
9362 * priority, but are only generated (pended) during instruction
9363 * execution, i.e. a pending fault-like exception means the
9364 * fault occurred on the *previous* instruction and must be
9365 * serviced prior to recognizing any new events in order to
9366 * fully complete the previous instruction.
9368 else if (!vcpu->arch.exception.pending) {
9369 if (vcpu->arch.nmi_injected) {
9370 static_call(kvm_x86_inject_nmi)(vcpu);
9372 } else if (vcpu->arch.interrupt.injected) {
9373 static_call(kvm_x86_inject_irq)(vcpu);
9378 WARN_ON_ONCE(vcpu->arch.exception.injected &&
9379 vcpu->arch.exception.pending);
9382 * Call check_nested_events() even if we reinjected a previous event
9383 * in order for caller to determine if it should require immediate-exit
9384 * from L2 to L1 due to pending L1 events which require exit
9387 if (is_guest_mode(vcpu)) {
9388 r = kvm_check_nested_events(vcpu);
9393 /* try to inject new event if pending */
9394 if (vcpu->arch.exception.pending) {
9395 trace_kvm_inj_exception(vcpu->arch.exception.nr,
9396 vcpu->arch.exception.has_error_code,
9397 vcpu->arch.exception.error_code);
9399 vcpu->arch.exception.pending = false;
9400 vcpu->arch.exception.injected = true;
9402 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
9403 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
9406 if (vcpu->arch.exception.nr == DB_VECTOR) {
9407 kvm_deliver_exception_payload(vcpu);
9408 if (vcpu->arch.dr7 & DR7_GD) {
9409 vcpu->arch.dr7 &= ~DR7_GD;
9410 kvm_update_dr7(vcpu);
9414 kvm_inject_exception(vcpu);
9418 /* Don't inject interrupts if the user asked to avoid doing so */
9419 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
9423 * Finally, inject interrupt events. If an event cannot be injected
9424 * due to architectural conditions (e.g. IF=0) a window-open exit
9425 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
9426 * and can architecturally be injected, but we cannot do it right now:
9427 * an interrupt could have arrived just now and we have to inject it
9428 * as a vmexit, or there could already an event in the queue, which is
9429 * indicated by can_inject. In that case we request an immediate exit
9430 * in order to make progress and get back here for another iteration.
9431 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
9433 if (vcpu->arch.smi_pending) {
9434 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
9438 vcpu->arch.smi_pending = false;
9439 ++vcpu->arch.smi_count;
9443 static_call(kvm_x86_enable_smi_window)(vcpu);
9446 if (vcpu->arch.nmi_pending) {
9447 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
9451 --vcpu->arch.nmi_pending;
9452 vcpu->arch.nmi_injected = true;
9453 static_call(kvm_x86_inject_nmi)(vcpu);
9455 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
9457 if (vcpu->arch.nmi_pending)
9458 static_call(kvm_x86_enable_nmi_window)(vcpu);
9461 if (kvm_cpu_has_injectable_intr(vcpu)) {
9462 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
9466 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
9467 static_call(kvm_x86_inject_irq)(vcpu);
9468 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
9470 if (kvm_cpu_has_injectable_intr(vcpu))
9471 static_call(kvm_x86_enable_irq_window)(vcpu);
9474 if (is_guest_mode(vcpu) &&
9475 kvm_x86_ops.nested_ops->hv_timer_pending &&
9476 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
9477 *req_immediate_exit = true;
9479 WARN_ON(vcpu->arch.exception.pending);
9484 *req_immediate_exit = true;
9490 static void process_nmi(struct kvm_vcpu *vcpu)
9495 * x86 is limited to one NMI running, and one NMI pending after it.
9496 * If an NMI is already in progress, limit further NMIs to just one.
9497 * Otherwise, allow two (and we'll inject the first one immediately).
9499 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
9502 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
9503 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
9504 kvm_make_request(KVM_REQ_EVENT, vcpu);
9507 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
9510 flags |= seg->g << 23;
9511 flags |= seg->db << 22;
9512 flags |= seg->l << 21;
9513 flags |= seg->avl << 20;
9514 flags |= seg->present << 15;
9515 flags |= seg->dpl << 13;
9516 flags |= seg->s << 12;
9517 flags |= seg->type << 8;
9521 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
9523 struct kvm_segment seg;
9526 kvm_get_segment(vcpu, &seg, n);
9527 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
9530 offset = 0x7f84 + n * 12;
9532 offset = 0x7f2c + (n - 3) * 12;
9534 put_smstate(u32, buf, offset + 8, seg.base);
9535 put_smstate(u32, buf, offset + 4, seg.limit);
9536 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
9539 #ifdef CONFIG_X86_64
9540 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
9542 struct kvm_segment seg;
9546 kvm_get_segment(vcpu, &seg, n);
9547 offset = 0x7e00 + n * 16;
9549 flags = enter_smm_get_segment_flags(&seg) >> 8;
9550 put_smstate(u16, buf, offset, seg.selector);
9551 put_smstate(u16, buf, offset + 2, flags);
9552 put_smstate(u32, buf, offset + 4, seg.limit);
9553 put_smstate(u64, buf, offset + 8, seg.base);
9557 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
9560 struct kvm_segment seg;
9564 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
9565 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
9566 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
9567 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
9569 for (i = 0; i < 8; i++)
9570 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i));
9572 kvm_get_dr(vcpu, 6, &val);
9573 put_smstate(u32, buf, 0x7fcc, (u32)val);
9574 kvm_get_dr(vcpu, 7, &val);
9575 put_smstate(u32, buf, 0x7fc8, (u32)val);
9577 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
9578 put_smstate(u32, buf, 0x7fc4, seg.selector);
9579 put_smstate(u32, buf, 0x7f64, seg.base);
9580 put_smstate(u32, buf, 0x7f60, seg.limit);
9581 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
9583 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
9584 put_smstate(u32, buf, 0x7fc0, seg.selector);
9585 put_smstate(u32, buf, 0x7f80, seg.base);
9586 put_smstate(u32, buf, 0x7f7c, seg.limit);
9587 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
9589 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9590 put_smstate(u32, buf, 0x7f74, dt.address);
9591 put_smstate(u32, buf, 0x7f70, dt.size);
9593 static_call(kvm_x86_get_idt)(vcpu, &dt);
9594 put_smstate(u32, buf, 0x7f58, dt.address);
9595 put_smstate(u32, buf, 0x7f54, dt.size);
9597 for (i = 0; i < 6; i++)
9598 enter_smm_save_seg_32(vcpu, buf, i);
9600 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
9603 put_smstate(u32, buf, 0x7efc, 0x00020000);
9604 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
9607 #ifdef CONFIG_X86_64
9608 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
9611 struct kvm_segment seg;
9615 for (i = 0; i < 16; i++)
9616 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i));
9618 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
9619 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
9621 kvm_get_dr(vcpu, 6, &val);
9622 put_smstate(u64, buf, 0x7f68, val);
9623 kvm_get_dr(vcpu, 7, &val);
9624 put_smstate(u64, buf, 0x7f60, val);
9626 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
9627 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
9628 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
9630 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
9633 put_smstate(u32, buf, 0x7efc, 0x00020064);
9635 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
9637 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
9638 put_smstate(u16, buf, 0x7e90, seg.selector);
9639 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
9640 put_smstate(u32, buf, 0x7e94, seg.limit);
9641 put_smstate(u64, buf, 0x7e98, seg.base);
9643 static_call(kvm_x86_get_idt)(vcpu, &dt);
9644 put_smstate(u32, buf, 0x7e84, dt.size);
9645 put_smstate(u64, buf, 0x7e88, dt.address);
9647 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
9648 put_smstate(u16, buf, 0x7e70, seg.selector);
9649 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
9650 put_smstate(u32, buf, 0x7e74, seg.limit);
9651 put_smstate(u64, buf, 0x7e78, seg.base);
9653 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9654 put_smstate(u32, buf, 0x7e64, dt.size);
9655 put_smstate(u64, buf, 0x7e68, dt.address);
9657 for (i = 0; i < 6; i++)
9658 enter_smm_save_seg_64(vcpu, buf, i);
9662 static void enter_smm(struct kvm_vcpu *vcpu)
9664 struct kvm_segment cs, ds;
9669 memset(buf, 0, 512);
9670 #ifdef CONFIG_X86_64
9671 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
9672 enter_smm_save_state_64(vcpu, buf);
9675 enter_smm_save_state_32(vcpu, buf);
9678 * Give enter_smm() a chance to make ISA-specific changes to the vCPU
9679 * state (e.g. leave guest mode) after we've saved the state into the
9680 * SMM state-save area.
9682 static_call(kvm_x86_enter_smm)(vcpu, buf);
9684 kvm_smm_changed(vcpu, true);
9685 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
9687 if (static_call(kvm_x86_get_nmi_mask)(vcpu))
9688 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
9690 static_call(kvm_x86_set_nmi_mask)(vcpu, true);
9692 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
9693 kvm_rip_write(vcpu, 0x8000);
9695 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
9696 static_call(kvm_x86_set_cr0)(vcpu, cr0);
9697 vcpu->arch.cr0 = cr0;
9699 static_call(kvm_x86_set_cr4)(vcpu, 0);
9701 /* Undocumented: IDT limit is set to zero on entry to SMM. */
9702 dt.address = dt.size = 0;
9703 static_call(kvm_x86_set_idt)(vcpu, &dt);
9705 kvm_set_dr(vcpu, 7, DR7_FIXED_1);
9707 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
9708 cs.base = vcpu->arch.smbase;
9713 cs.limit = ds.limit = 0xffffffff;
9714 cs.type = ds.type = 0x3;
9715 cs.dpl = ds.dpl = 0;
9720 cs.avl = ds.avl = 0;
9721 cs.present = ds.present = 1;
9722 cs.unusable = ds.unusable = 0;
9723 cs.padding = ds.padding = 0;
9725 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9726 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
9727 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
9728 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
9729 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
9730 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
9732 #ifdef CONFIG_X86_64
9733 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
9734 static_call(kvm_x86_set_efer)(vcpu, 0);
9737 kvm_update_cpuid_runtime(vcpu);
9738 kvm_mmu_reset_context(vcpu);
9741 static void process_smi(struct kvm_vcpu *vcpu)
9743 vcpu->arch.smi_pending = true;
9744 kvm_make_request(KVM_REQ_EVENT, vcpu);
9747 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
9748 unsigned long *vcpu_bitmap)
9750 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
9753 void kvm_make_scan_ioapic_request(struct kvm *kvm)
9755 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
9758 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
9762 if (!lapic_in_kernel(vcpu))
9765 down_read(&vcpu->kvm->arch.apicv_update_lock);
9767 activate = kvm_apicv_activated(vcpu->kvm);
9768 if (vcpu->arch.apicv_active == activate)
9771 vcpu->arch.apicv_active = activate;
9772 kvm_apic_update_apicv(vcpu);
9773 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
9776 * When APICv gets disabled, we may still have injected interrupts
9777 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
9778 * still active when the interrupt got accepted. Make sure
9779 * inject_pending_event() is called to check for that.
9781 if (!vcpu->arch.apicv_active)
9782 kvm_make_request(KVM_REQ_EVENT, vcpu);
9785 up_read(&vcpu->kvm->arch.apicv_update_lock);
9787 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
9789 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
9790 enum kvm_apicv_inhibit reason, bool set)
9792 unsigned long old, new;
9794 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
9796 if (!static_call(kvm_x86_check_apicv_inhibit_reasons)(reason))
9799 old = new = kvm->arch.apicv_inhibit_reasons;
9801 set_or_clear_apicv_inhibit(&new, reason, set);
9803 if (!!old != !!new) {
9805 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
9806 * false positives in the sanity check WARN in svm_vcpu_run().
9807 * This task will wait for all vCPUs to ack the kick IRQ before
9808 * updating apicv_inhibit_reasons, and all other vCPUs will
9809 * block on acquiring apicv_update_lock so that vCPUs can't
9810 * redo svm_vcpu_run() without seeing the new inhibit state.
9812 * Note, holding apicv_update_lock and taking it in the read
9813 * side (handling the request) also prevents other vCPUs from
9814 * servicing the request with a stale apicv_inhibit_reasons.
9816 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
9817 kvm->arch.apicv_inhibit_reasons = new;
9819 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
9820 kvm_zap_gfn_range(kvm, gfn, gfn+1);
9823 kvm->arch.apicv_inhibit_reasons = new;
9827 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
9828 enum kvm_apicv_inhibit reason, bool set)
9833 down_write(&kvm->arch.apicv_update_lock);
9834 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
9835 up_write(&kvm->arch.apicv_update_lock);
9837 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
9839 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
9841 if (!kvm_apic_present(vcpu))
9844 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
9846 if (irqchip_split(vcpu->kvm))
9847 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
9849 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
9850 if (ioapic_in_kernel(vcpu->kvm))
9851 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
9854 if (is_guest_mode(vcpu))
9855 vcpu->arch.load_eoi_exitmap_pending = true;
9857 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
9860 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
9862 u64 eoi_exit_bitmap[4];
9864 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
9867 if (to_hv_vcpu(vcpu)) {
9868 bitmap_or((ulong *)eoi_exit_bitmap,
9869 vcpu->arch.ioapic_handled_vectors,
9870 to_hv_synic(vcpu)->vec_bitmap, 256);
9871 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
9875 static_call_cond(kvm_x86_load_eoi_exitmap)(
9876 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
9879 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
9880 unsigned long start, unsigned long end)
9882 unsigned long apic_address;
9885 * The physical address of apic access page is stored in the VMCS.
9886 * Update it when it becomes invalid.
9888 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
9889 if (start <= apic_address && apic_address < end)
9890 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
9893 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
9895 if (!lapic_in_kernel(vcpu))
9898 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
9901 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
9903 smp_send_reschedule(vcpu->cpu);
9905 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
9908 * Called within kvm->srcu read side.
9909 * Returns 1 to let vcpu_run() continue the guest execution loop without
9910 * exiting to the userspace. Otherwise, the value will be returned to the
9913 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
9917 dm_request_for_irq_injection(vcpu) &&
9918 kvm_cpu_accept_dm_intr(vcpu);
9919 fastpath_t exit_fastpath;
9921 bool req_immediate_exit = false;
9923 /* Forbid vmenter if vcpu dirty ring is soft-full */
9924 if (unlikely(vcpu->kvm->dirty_ring_size &&
9925 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
9926 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
9927 trace_kvm_dirty_ring_exit(vcpu);
9932 if (kvm_request_pending(vcpu)) {
9933 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
9937 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
9938 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
9943 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
9944 kvm_mmu_free_obsolete_roots(vcpu);
9945 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
9946 __kvm_migrate_timers(vcpu);
9947 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
9948 kvm_update_masterclock(vcpu->kvm);
9949 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
9950 kvm_gen_kvmclock_update(vcpu);
9951 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
9952 r = kvm_guest_time_update(vcpu);
9956 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
9957 kvm_mmu_sync_roots(vcpu);
9958 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
9959 kvm_mmu_load_pgd(vcpu);
9960 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
9961 kvm_vcpu_flush_tlb_all(vcpu);
9963 /* Flushing all ASIDs flushes the current ASID... */
9964 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
9966 kvm_service_local_tlb_flush_requests(vcpu);
9968 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
9969 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
9973 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9974 if (is_guest_mode(vcpu)) {
9975 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9977 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
9978 vcpu->mmio_needed = 0;
9983 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
9984 /* Page is swapped out. Do synthetic halt */
9985 vcpu->arch.apf.halted = true;
9989 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
9990 record_steal_time(vcpu);
9991 if (kvm_check_request(KVM_REQ_SMI, vcpu))
9993 if (kvm_check_request(KVM_REQ_NMI, vcpu))
9995 if (kvm_check_request(KVM_REQ_PMU, vcpu))
9996 kvm_pmu_handle_event(vcpu);
9997 if (kvm_check_request(KVM_REQ_PMI, vcpu))
9998 kvm_pmu_deliver_pmi(vcpu);
9999 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10000 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10001 if (test_bit(vcpu->arch.pending_ioapic_eoi,
10002 vcpu->arch.ioapic_handled_vectors)) {
10003 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10004 vcpu->run->eoi.vector =
10005 vcpu->arch.pending_ioapic_eoi;
10010 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10011 vcpu_scan_ioapic(vcpu);
10012 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10013 vcpu_load_eoi_exitmap(vcpu);
10014 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10015 kvm_vcpu_reload_apic_access_page(vcpu);
10016 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10017 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10018 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10022 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10023 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10024 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10028 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10029 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10031 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10032 vcpu->run->hyperv = hv_vcpu->exit;
10038 * KVM_REQ_HV_STIMER has to be processed after
10039 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10040 * depend on the guest clock being up-to-date
10042 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10043 kvm_hv_process_stimers(vcpu);
10044 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10045 kvm_vcpu_update_apicv(vcpu);
10046 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10047 kvm_check_async_pf_completion(vcpu);
10048 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10049 static_call(kvm_x86_msr_filter_changed)(vcpu);
10051 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10052 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10055 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10056 kvm_xen_has_interrupt(vcpu)) {
10057 ++vcpu->stat.req_event;
10058 r = kvm_apic_accept_events(vcpu);
10063 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10068 r = inject_pending_event(vcpu, &req_immediate_exit);
10074 static_call(kvm_x86_enable_irq_window)(vcpu);
10076 if (kvm_lapic_enabled(vcpu)) {
10077 update_cr8_intercept(vcpu);
10078 kvm_lapic_sync_to_vapic(vcpu);
10082 r = kvm_mmu_reload(vcpu);
10084 goto cancel_injection;
10089 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10092 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10093 * IPI are then delayed after guest entry, which ensures that they
10094 * result in virtual interrupt delivery.
10096 local_irq_disable();
10098 /* Store vcpu->apicv_active before vcpu->mode. */
10099 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10101 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
10104 * 1) We should set ->mode before checking ->requests. Please see
10105 * the comment in kvm_vcpu_exiting_guest_mode().
10107 * 2) For APICv, we should set ->mode before checking PID.ON. This
10108 * pairs with the memory barrier implicit in pi_test_and_set_on
10109 * (see vmx_deliver_posted_interrupt).
10111 * 3) This also orders the write to mode from any reads to the page
10112 * tables done while the VCPU is running. Please see the comment
10113 * in kvm_flush_remote_tlbs.
10115 smp_mb__after_srcu_read_unlock();
10118 * Process pending posted interrupts to handle the case where the
10119 * notification IRQ arrived in the host, or was never sent (because the
10120 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10121 * status, KVM doesn't update assigned devices when APICv is inhibited,
10122 * i.e. they can post interrupts even if APICv is temporarily disabled.
10124 if (kvm_lapic_enabled(vcpu))
10125 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10127 if (kvm_vcpu_exit_request(vcpu)) {
10128 vcpu->mode = OUTSIDE_GUEST_MODE;
10130 local_irq_enable();
10132 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10134 goto cancel_injection;
10137 if (req_immediate_exit) {
10138 kvm_make_request(KVM_REQ_EVENT, vcpu);
10139 static_call(kvm_x86_request_immediate_exit)(vcpu);
10142 fpregs_assert_state_consistent();
10143 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10144 switch_fpu_return();
10146 if (vcpu->arch.guest_fpu.xfd_err)
10147 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10149 if (unlikely(vcpu->arch.switch_db_regs)) {
10150 set_debugreg(0, 7);
10151 set_debugreg(vcpu->arch.eff_db[0], 0);
10152 set_debugreg(vcpu->arch.eff_db[1], 1);
10153 set_debugreg(vcpu->arch.eff_db[2], 2);
10154 set_debugreg(vcpu->arch.eff_db[3], 3);
10155 } else if (unlikely(hw_breakpoint_active())) {
10156 set_debugreg(0, 7);
10159 guest_timing_enter_irqoff();
10163 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10164 * update must kick and wait for all vCPUs before toggling the
10165 * per-VM state, and responsing vCPUs must wait for the update
10166 * to complete before servicing KVM_REQ_APICV_UPDATE.
10168 WARN_ON_ONCE(kvm_apicv_activated(vcpu->kvm) != kvm_vcpu_apicv_active(vcpu));
10170 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10171 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10174 if (kvm_lapic_enabled(vcpu))
10175 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10177 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10178 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10184 * Do this here before restoring debug registers on the host. And
10185 * since we do this before handling the vmexit, a DR access vmexit
10186 * can (a) read the correct value of the debug registers, (b) set
10187 * KVM_DEBUGREG_WONT_EXIT again.
10189 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
10190 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
10191 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
10192 kvm_update_dr0123(vcpu);
10193 kvm_update_dr7(vcpu);
10197 * If the guest has used debug registers, at least dr7
10198 * will be disabled while returning to the host.
10199 * If we don't have active breakpoints in the host, we don't
10200 * care about the messed up debug address registers. But if
10201 * we have some of them active, restore the old state.
10203 if (hw_breakpoint_active())
10204 hw_breakpoint_restore();
10206 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
10207 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
10209 vcpu->mode = OUTSIDE_GUEST_MODE;
10213 * Sync xfd before calling handle_exit_irqoff() which may
10214 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
10215 * in #NM irqoff handler).
10217 if (vcpu->arch.xfd_no_write_intercept)
10218 fpu_sync_guest_vmexit_xfd_state();
10220 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
10222 if (vcpu->arch.guest_fpu.xfd_err)
10223 wrmsrl(MSR_IA32_XFD_ERR, 0);
10226 * Consume any pending interrupts, including the possible source of
10227 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
10228 * An instruction is required after local_irq_enable() to fully unblock
10229 * interrupts on processors that implement an interrupt shadow, the
10230 * stat.exits increment will do nicely.
10232 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
10233 local_irq_enable();
10234 ++vcpu->stat.exits;
10235 local_irq_disable();
10236 kvm_after_interrupt(vcpu);
10239 * Wait until after servicing IRQs to account guest time so that any
10240 * ticks that occurred while running the guest are properly accounted
10241 * to the guest. Waiting until IRQs are enabled degrades the accuracy
10242 * of accounting via context tracking, but the loss of accuracy is
10243 * acceptable for all known use cases.
10245 guest_timing_exit_irqoff();
10247 if (lapic_in_kernel(vcpu)) {
10248 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
10249 if (delta != S64_MIN) {
10250 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
10251 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
10255 local_irq_enable();
10258 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10261 * Profile KVM exit RIPs:
10263 if (unlikely(prof_on == KVM_PROFILING)) {
10264 unsigned long rip = kvm_rip_read(vcpu);
10265 profile_hit(KVM_PROFILING, (void *)rip);
10268 if (unlikely(vcpu->arch.tsc_always_catchup))
10269 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10271 if (vcpu->arch.apic_attention)
10272 kvm_lapic_sync_from_vapic(vcpu);
10274 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
10278 if (req_immediate_exit)
10279 kvm_make_request(KVM_REQ_EVENT, vcpu);
10280 static_call(kvm_x86_cancel_injection)(vcpu);
10281 if (unlikely(vcpu->arch.apic_attention))
10282 kvm_lapic_sync_from_vapic(vcpu);
10287 /* Called within kvm->srcu read side. */
10288 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
10292 if (!kvm_arch_vcpu_runnable(vcpu)) {
10294 * Switch to the software timer before halt-polling/blocking as
10295 * the guest's timer may be a break event for the vCPU, and the
10296 * hypervisor timer runs only when the CPU is in guest mode.
10297 * Switch before halt-polling so that KVM recognizes an expired
10298 * timer before blocking.
10300 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
10302 kvm_lapic_switch_to_sw_timer(vcpu);
10304 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10305 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10306 kvm_vcpu_halt(vcpu);
10308 kvm_vcpu_block(vcpu);
10309 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
10312 kvm_lapic_switch_to_hv_timer(vcpu);
10314 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
10318 if (kvm_apic_accept_events(vcpu) < 0)
10320 switch(vcpu->arch.mp_state) {
10321 case KVM_MP_STATE_HALTED:
10322 case KVM_MP_STATE_AP_RESET_HOLD:
10323 vcpu->arch.pv.pv_unhalted = false;
10324 vcpu->arch.mp_state =
10325 KVM_MP_STATE_RUNNABLE;
10327 case KVM_MP_STATE_RUNNABLE:
10328 vcpu->arch.apf.halted = false;
10330 case KVM_MP_STATE_INIT_RECEIVED:
10338 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
10340 if (is_guest_mode(vcpu))
10341 kvm_check_nested_events(vcpu);
10343 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
10344 !vcpu->arch.apf.halted);
10347 /* Called within kvm->srcu read side. */
10348 static int vcpu_run(struct kvm_vcpu *vcpu)
10351 struct kvm *kvm = vcpu->kvm;
10353 vcpu->arch.l1tf_flush_l1d = true;
10356 if (kvm_vcpu_running(vcpu)) {
10357 r = vcpu_enter_guest(vcpu);
10359 r = vcpu_block(kvm, vcpu);
10365 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
10366 if (kvm_cpu_has_pending_timer(vcpu))
10367 kvm_inject_pending_timer_irqs(vcpu);
10369 if (dm_request_for_irq_injection(vcpu) &&
10370 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
10372 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
10373 ++vcpu->stat.request_irq_exits;
10377 if (__xfer_to_guest_mode_work_pending()) {
10378 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10379 r = xfer_to_guest_mode_handle_work(vcpu);
10380 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
10389 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
10393 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10394 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
10395 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
10399 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
10401 BUG_ON(!vcpu->arch.pio.count);
10403 return complete_emulated_io(vcpu);
10407 * Implements the following, as a state machine:
10410 * for each fragment
10411 * for each mmio piece in the fragment
10418 * for each fragment
10419 * for each mmio piece in the fragment
10424 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
10426 struct kvm_run *run = vcpu->run;
10427 struct kvm_mmio_fragment *frag;
10430 BUG_ON(!vcpu->mmio_needed);
10432 /* Complete previous fragment */
10433 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
10434 len = min(8u, frag->len);
10435 if (!vcpu->mmio_is_write)
10436 memcpy(frag->data, run->mmio.data, len);
10438 if (frag->len <= 8) {
10439 /* Switch to the next fragment. */
10441 vcpu->mmio_cur_fragment++;
10443 /* Go forward to the next mmio piece. */
10449 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
10450 vcpu->mmio_needed = 0;
10452 /* FIXME: return into emulator if single-stepping. */
10453 if (vcpu->mmio_is_write)
10455 vcpu->mmio_read_completed = 1;
10456 return complete_emulated_io(vcpu);
10459 run->exit_reason = KVM_EXIT_MMIO;
10460 run->mmio.phys_addr = frag->gpa;
10461 if (vcpu->mmio_is_write)
10462 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
10463 run->mmio.len = min(8u, frag->len);
10464 run->mmio.is_write = vcpu->mmio_is_write;
10465 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
10469 /* Swap (qemu) user FPU context for the guest FPU context. */
10470 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
10472 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
10473 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
10477 /* When vcpu_run ends, restore user space FPU context. */
10478 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
10480 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
10481 ++vcpu->stat.fpu_reload;
10485 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
10487 struct kvm_run *kvm_run = vcpu->run;
10488 struct kvm *kvm = vcpu->kvm;
10492 kvm_sigset_activate(vcpu);
10493 kvm_run->flags = 0;
10494 kvm_load_guest_fpu(vcpu);
10496 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10497 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
10498 if (kvm_run->immediate_exit) {
10503 * It should be impossible for the hypervisor timer to be in
10504 * use before KVM has ever run the vCPU.
10506 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu));
10508 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10509 kvm_vcpu_block(vcpu);
10510 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
10512 if (kvm_apic_accept_events(vcpu) < 0) {
10516 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
10518 if (signal_pending(current)) {
10520 kvm_run->exit_reason = KVM_EXIT_INTR;
10521 ++vcpu->stat.signal_exits;
10526 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
10527 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
10532 if (kvm_run->kvm_dirty_regs) {
10533 r = sync_regs(vcpu);
10538 /* re-sync apic's tpr */
10539 if (!lapic_in_kernel(vcpu)) {
10540 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
10546 if (unlikely(vcpu->arch.complete_userspace_io)) {
10547 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
10548 vcpu->arch.complete_userspace_io = NULL;
10553 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
10555 if (kvm_run->immediate_exit) {
10560 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
10564 r = vcpu_run(vcpu);
10567 kvm_put_guest_fpu(vcpu);
10568 if (kvm_run->kvm_valid_regs)
10570 post_kvm_run_save(vcpu);
10571 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10573 kvm_sigset_deactivate(vcpu);
10578 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10580 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
10582 * We are here if userspace calls get_regs() in the middle of
10583 * instruction emulation. Registers state needs to be copied
10584 * back from emulation context to vcpu. Userspace shouldn't do
10585 * that usually, but some bad designed PV devices (vmware
10586 * backdoor interface) need this to work
10588 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
10589 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10591 regs->rax = kvm_rax_read(vcpu);
10592 regs->rbx = kvm_rbx_read(vcpu);
10593 regs->rcx = kvm_rcx_read(vcpu);
10594 regs->rdx = kvm_rdx_read(vcpu);
10595 regs->rsi = kvm_rsi_read(vcpu);
10596 regs->rdi = kvm_rdi_read(vcpu);
10597 regs->rsp = kvm_rsp_read(vcpu);
10598 regs->rbp = kvm_rbp_read(vcpu);
10599 #ifdef CONFIG_X86_64
10600 regs->r8 = kvm_r8_read(vcpu);
10601 regs->r9 = kvm_r9_read(vcpu);
10602 regs->r10 = kvm_r10_read(vcpu);
10603 regs->r11 = kvm_r11_read(vcpu);
10604 regs->r12 = kvm_r12_read(vcpu);
10605 regs->r13 = kvm_r13_read(vcpu);
10606 regs->r14 = kvm_r14_read(vcpu);
10607 regs->r15 = kvm_r15_read(vcpu);
10610 regs->rip = kvm_rip_read(vcpu);
10611 regs->rflags = kvm_get_rflags(vcpu);
10614 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10617 __get_regs(vcpu, regs);
10622 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10624 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
10625 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10627 kvm_rax_write(vcpu, regs->rax);
10628 kvm_rbx_write(vcpu, regs->rbx);
10629 kvm_rcx_write(vcpu, regs->rcx);
10630 kvm_rdx_write(vcpu, regs->rdx);
10631 kvm_rsi_write(vcpu, regs->rsi);
10632 kvm_rdi_write(vcpu, regs->rdi);
10633 kvm_rsp_write(vcpu, regs->rsp);
10634 kvm_rbp_write(vcpu, regs->rbp);
10635 #ifdef CONFIG_X86_64
10636 kvm_r8_write(vcpu, regs->r8);
10637 kvm_r9_write(vcpu, regs->r9);
10638 kvm_r10_write(vcpu, regs->r10);
10639 kvm_r11_write(vcpu, regs->r11);
10640 kvm_r12_write(vcpu, regs->r12);
10641 kvm_r13_write(vcpu, regs->r13);
10642 kvm_r14_write(vcpu, regs->r14);
10643 kvm_r15_write(vcpu, regs->r15);
10646 kvm_rip_write(vcpu, regs->rip);
10647 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
10649 vcpu->arch.exception.pending = false;
10651 kvm_make_request(KVM_REQ_EVENT, vcpu);
10654 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10657 __set_regs(vcpu, regs);
10662 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10664 struct desc_ptr dt;
10666 if (vcpu->arch.guest_state_protected)
10667 goto skip_protected_regs;
10669 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
10670 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
10671 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
10672 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
10673 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
10674 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
10676 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
10677 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
10679 static_call(kvm_x86_get_idt)(vcpu, &dt);
10680 sregs->idt.limit = dt.size;
10681 sregs->idt.base = dt.address;
10682 static_call(kvm_x86_get_gdt)(vcpu, &dt);
10683 sregs->gdt.limit = dt.size;
10684 sregs->gdt.base = dt.address;
10686 sregs->cr2 = vcpu->arch.cr2;
10687 sregs->cr3 = kvm_read_cr3(vcpu);
10689 skip_protected_regs:
10690 sregs->cr0 = kvm_read_cr0(vcpu);
10691 sregs->cr4 = kvm_read_cr4(vcpu);
10692 sregs->cr8 = kvm_get_cr8(vcpu);
10693 sregs->efer = vcpu->arch.efer;
10694 sregs->apic_base = kvm_get_apic_base(vcpu);
10697 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10699 __get_sregs_common(vcpu, sregs);
10701 if (vcpu->arch.guest_state_protected)
10704 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
10705 set_bit(vcpu->arch.interrupt.nr,
10706 (unsigned long *)sregs->interrupt_bitmap);
10709 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
10713 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
10715 if (vcpu->arch.guest_state_protected)
10718 if (is_pae_paging(vcpu)) {
10719 for (i = 0 ; i < 4 ; i++)
10720 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
10721 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
10725 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
10726 struct kvm_sregs *sregs)
10729 __get_sregs(vcpu, sregs);
10734 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
10735 struct kvm_mp_state *mp_state)
10740 if (kvm_mpx_supported())
10741 kvm_load_guest_fpu(vcpu);
10743 r = kvm_apic_accept_events(vcpu);
10748 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
10749 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
10750 vcpu->arch.pv.pv_unhalted)
10751 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
10753 mp_state->mp_state = vcpu->arch.mp_state;
10756 if (kvm_mpx_supported())
10757 kvm_put_guest_fpu(vcpu);
10762 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
10763 struct kvm_mp_state *mp_state)
10769 if (!lapic_in_kernel(vcpu) &&
10770 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
10774 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
10775 * INIT state; latched init should be reported using
10776 * KVM_SET_VCPU_EVENTS, so reject it here.
10778 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
10779 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
10780 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
10783 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
10784 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
10785 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
10787 vcpu->arch.mp_state = mp_state->mp_state;
10788 kvm_make_request(KVM_REQ_EVENT, vcpu);
10796 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
10797 int reason, bool has_error_code, u32 error_code)
10799 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
10802 init_emulate_ctxt(vcpu);
10804 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
10805 has_error_code, error_code);
10807 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
10808 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
10809 vcpu->run->internal.ndata = 0;
10813 kvm_rip_write(vcpu, ctxt->eip);
10814 kvm_set_rflags(vcpu, ctxt->eflags);
10817 EXPORT_SYMBOL_GPL(kvm_task_switch);
10819 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10821 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
10823 * When EFER.LME and CR0.PG are set, the processor is in
10824 * 64-bit mode (though maybe in a 32-bit code segment).
10825 * CR4.PAE and EFER.LMA must be set.
10827 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
10829 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
10833 * Not in 64-bit mode: EFER.LMA is clear and the code
10834 * segment cannot be 64-bit.
10836 if (sregs->efer & EFER_LMA || sregs->cs.l)
10840 return kvm_is_valid_cr4(vcpu, sregs->cr4);
10843 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
10844 int *mmu_reset_needed, bool update_pdptrs)
10846 struct msr_data apic_base_msr;
10848 struct desc_ptr dt;
10850 if (!kvm_is_valid_sregs(vcpu, sregs))
10853 apic_base_msr.data = sregs->apic_base;
10854 apic_base_msr.host_initiated = true;
10855 if (kvm_set_apic_base(vcpu, &apic_base_msr))
10858 if (vcpu->arch.guest_state_protected)
10861 dt.size = sregs->idt.limit;
10862 dt.address = sregs->idt.base;
10863 static_call(kvm_x86_set_idt)(vcpu, &dt);
10864 dt.size = sregs->gdt.limit;
10865 dt.address = sregs->gdt.base;
10866 static_call(kvm_x86_set_gdt)(vcpu, &dt);
10868 vcpu->arch.cr2 = sregs->cr2;
10869 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
10870 vcpu->arch.cr3 = sregs->cr3;
10871 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
10872 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
10874 kvm_set_cr8(vcpu, sregs->cr8);
10876 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
10877 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
10879 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
10880 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
10881 vcpu->arch.cr0 = sregs->cr0;
10883 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
10884 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
10886 if (update_pdptrs) {
10887 idx = srcu_read_lock(&vcpu->kvm->srcu);
10888 if (is_pae_paging(vcpu)) {
10889 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
10890 *mmu_reset_needed = 1;
10892 srcu_read_unlock(&vcpu->kvm->srcu, idx);
10895 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
10896 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
10897 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
10898 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
10899 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
10900 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
10902 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
10903 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
10905 update_cr8_intercept(vcpu);
10907 /* Older userspace won't unhalt the vcpu on reset. */
10908 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
10909 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
10910 !is_protmode(vcpu))
10911 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10916 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10918 int pending_vec, max_bits;
10919 int mmu_reset_needed = 0;
10920 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
10925 if (mmu_reset_needed)
10926 kvm_mmu_reset_context(vcpu);
10928 max_bits = KVM_NR_INTERRUPTS;
10929 pending_vec = find_first_bit(
10930 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
10932 if (pending_vec < max_bits) {
10933 kvm_queue_interrupt(vcpu, pending_vec, false);
10934 pr_debug("Set back pending irq %d\n", pending_vec);
10935 kvm_make_request(KVM_REQ_EVENT, vcpu);
10940 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
10942 int mmu_reset_needed = 0;
10943 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
10944 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
10945 !(sregs2->efer & EFER_LMA);
10948 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
10951 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
10954 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
10955 &mmu_reset_needed, !valid_pdptrs);
10959 if (valid_pdptrs) {
10960 for (i = 0; i < 4 ; i++)
10961 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
10963 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
10964 mmu_reset_needed = 1;
10965 vcpu->arch.pdptrs_from_userspace = true;
10967 if (mmu_reset_needed)
10968 kvm_mmu_reset_context(vcpu);
10972 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
10973 struct kvm_sregs *sregs)
10978 ret = __set_sregs(vcpu, sregs);
10983 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
10986 struct kvm_vcpu *vcpu;
10989 down_write(&kvm->arch.apicv_update_lock);
10991 kvm_for_each_vcpu(i, vcpu, kvm) {
10992 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
10997 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
10998 up_write(&kvm->arch.apicv_update_lock);
11001 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11002 struct kvm_guest_debug *dbg)
11004 unsigned long rflags;
11007 if (vcpu->arch.guest_state_protected)
11012 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11014 if (vcpu->arch.exception.pending)
11016 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11017 kvm_queue_exception(vcpu, DB_VECTOR);
11019 kvm_queue_exception(vcpu, BP_VECTOR);
11023 * Read rflags as long as potentially injected trace flags are still
11026 rflags = kvm_get_rflags(vcpu);
11028 vcpu->guest_debug = dbg->control;
11029 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11030 vcpu->guest_debug = 0;
11032 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11033 for (i = 0; i < KVM_NR_DB_REGS; ++i)
11034 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11035 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11037 for (i = 0; i < KVM_NR_DB_REGS; i++)
11038 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11040 kvm_update_dr7(vcpu);
11042 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11043 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11046 * Trigger an rflags update that will inject or remove the trace
11049 kvm_set_rflags(vcpu, rflags);
11051 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11053 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11063 * Translate a guest virtual address to a guest physical address.
11065 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11066 struct kvm_translation *tr)
11068 unsigned long vaddr = tr->linear_address;
11074 idx = srcu_read_lock(&vcpu->kvm->srcu);
11075 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11076 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11077 tr->physical_address = gpa;
11078 tr->valid = gpa != UNMAPPED_GVA;
11086 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11088 struct fxregs_state *fxsave;
11090 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11095 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11096 memcpy(fpu->fpr, fxsave->st_space, 128);
11097 fpu->fcw = fxsave->cwd;
11098 fpu->fsw = fxsave->swd;
11099 fpu->ftwx = fxsave->twd;
11100 fpu->last_opcode = fxsave->fop;
11101 fpu->last_ip = fxsave->rip;
11102 fpu->last_dp = fxsave->rdp;
11103 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11109 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11111 struct fxregs_state *fxsave;
11113 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11118 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11120 memcpy(fxsave->st_space, fpu->fpr, 128);
11121 fxsave->cwd = fpu->fcw;
11122 fxsave->swd = fpu->fsw;
11123 fxsave->twd = fpu->ftwx;
11124 fxsave->fop = fpu->last_opcode;
11125 fxsave->rip = fpu->last_ip;
11126 fxsave->rdp = fpu->last_dp;
11127 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11133 static void store_regs(struct kvm_vcpu *vcpu)
11135 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
11137 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
11138 __get_regs(vcpu, &vcpu->run->s.regs.regs);
11140 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
11141 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
11143 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
11144 kvm_vcpu_ioctl_x86_get_vcpu_events(
11145 vcpu, &vcpu->run->s.regs.events);
11148 static int sync_regs(struct kvm_vcpu *vcpu)
11150 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
11151 __set_regs(vcpu, &vcpu->run->s.regs.regs);
11152 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
11154 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
11155 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
11157 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
11159 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
11160 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
11161 vcpu, &vcpu->run->s.regs.events))
11163 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
11169 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
11171 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
11172 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
11173 "guest TSC will not be reliable\n");
11178 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
11183 vcpu->arch.last_vmentry_cpu = -1;
11184 vcpu->arch.regs_avail = ~0;
11185 vcpu->arch.regs_dirty = ~0;
11187 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
11188 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11190 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
11192 r = kvm_mmu_create(vcpu);
11196 if (irqchip_in_kernel(vcpu->kvm)) {
11197 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
11199 goto fail_mmu_destroy;
11200 if (kvm_apicv_activated(vcpu->kvm))
11201 vcpu->arch.apicv_active = true;
11203 static_branch_inc(&kvm_has_noapic_vcpu);
11207 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
11209 goto fail_free_lapic;
11210 vcpu->arch.pio_data = page_address(page);
11212 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
11213 GFP_KERNEL_ACCOUNT);
11214 if (!vcpu->arch.mce_banks)
11215 goto fail_free_pio_data;
11216 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
11218 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
11219 GFP_KERNEL_ACCOUNT))
11220 goto fail_free_mce_banks;
11222 if (!alloc_emulate_ctxt(vcpu))
11223 goto free_wbinvd_dirty_mask;
11225 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
11226 pr_err("kvm: failed to allocate vcpu's fpu\n");
11227 goto free_emulate_ctxt;
11230 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
11231 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
11233 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
11235 kvm_async_pf_hash_reset(vcpu);
11236 kvm_pmu_init(vcpu);
11238 vcpu->arch.pending_external_vector = -1;
11239 vcpu->arch.preempted_in_kernel = false;
11241 #if IS_ENABLED(CONFIG_HYPERV)
11242 vcpu->arch.hv_root_tdp = INVALID_PAGE;
11245 r = static_call(kvm_x86_vcpu_create)(vcpu);
11247 goto free_guest_fpu;
11249 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
11250 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
11251 kvm_vcpu_mtrr_init(vcpu);
11253 kvm_set_tsc_khz(vcpu, max_tsc_khz);
11254 kvm_vcpu_reset(vcpu, false);
11255 kvm_init_mmu(vcpu);
11260 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11262 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11263 free_wbinvd_dirty_mask:
11264 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11265 fail_free_mce_banks:
11266 kfree(vcpu->arch.mce_banks);
11267 fail_free_pio_data:
11268 free_page((unsigned long)vcpu->arch.pio_data);
11270 kvm_free_lapic(vcpu);
11272 kvm_mmu_destroy(vcpu);
11276 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
11278 struct kvm *kvm = vcpu->kvm;
11280 if (mutex_lock_killable(&vcpu->mutex))
11283 kvm_synchronize_tsc(vcpu, 0);
11286 /* poll control enabled by default */
11287 vcpu->arch.msr_kvm_poll_control = 1;
11289 mutex_unlock(&vcpu->mutex);
11291 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
11292 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
11293 KVMCLOCK_SYNC_PERIOD);
11296 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
11300 kvmclock_reset(vcpu);
11302 static_call(kvm_x86_vcpu_free)(vcpu);
11304 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11305 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11306 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11308 kvm_hv_vcpu_uninit(vcpu);
11309 kvm_pmu_destroy(vcpu);
11310 kfree(vcpu->arch.mce_banks);
11311 kvm_free_lapic(vcpu);
11312 idx = srcu_read_lock(&vcpu->kvm->srcu);
11313 kvm_mmu_destroy(vcpu);
11314 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11315 free_page((unsigned long)vcpu->arch.pio_data);
11316 kvfree(vcpu->arch.cpuid_entries);
11317 if (!lapic_in_kernel(vcpu))
11318 static_branch_dec(&kvm_has_noapic_vcpu);
11321 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
11323 struct kvm_cpuid_entry2 *cpuid_0x1;
11324 unsigned long old_cr0 = kvm_read_cr0(vcpu);
11325 unsigned long new_cr0;
11328 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
11329 * to handle side effects. RESET emulation hits those flows and relies
11330 * on emulated/virtualized registers, including those that are loaded
11331 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
11332 * to detect improper or missing initialization.
11334 WARN_ON_ONCE(!init_event &&
11335 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
11337 kvm_lapic_reset(vcpu, init_event);
11339 vcpu->arch.hflags = 0;
11341 vcpu->arch.smi_pending = 0;
11342 vcpu->arch.smi_count = 0;
11343 atomic_set(&vcpu->arch.nmi_queued, 0);
11344 vcpu->arch.nmi_pending = 0;
11345 vcpu->arch.nmi_injected = false;
11346 kvm_clear_interrupt_queue(vcpu);
11347 kvm_clear_exception_queue(vcpu);
11349 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
11350 kvm_update_dr0123(vcpu);
11351 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
11352 vcpu->arch.dr7 = DR7_FIXED_1;
11353 kvm_update_dr7(vcpu);
11355 vcpu->arch.cr2 = 0;
11357 kvm_make_request(KVM_REQ_EVENT, vcpu);
11358 vcpu->arch.apf.msr_en_val = 0;
11359 vcpu->arch.apf.msr_int_val = 0;
11360 vcpu->arch.st.msr_val = 0;
11362 kvmclock_reset(vcpu);
11364 kvm_clear_async_pf_completion_queue(vcpu);
11365 kvm_async_pf_hash_reset(vcpu);
11366 vcpu->arch.apf.halted = false;
11368 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
11369 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
11372 * To avoid have the INIT path from kvm_apic_has_events() that be
11373 * called with loaded FPU and does not let userspace fix the state.
11376 kvm_put_guest_fpu(vcpu);
11378 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
11379 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
11382 kvm_load_guest_fpu(vcpu);
11386 kvm_pmu_reset(vcpu);
11387 vcpu->arch.smbase = 0x30000;
11389 vcpu->arch.msr_misc_features_enables = 0;
11391 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
11392 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
11395 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
11396 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
11397 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
11400 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
11401 * if no CPUID match is found. Note, it's impossible to get a match at
11402 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
11403 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
11404 * on RESET. But, go through the motions in case that's ever remedied.
11406 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1, 0);
11407 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
11409 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
11411 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
11412 kvm_rip_write(vcpu, 0xfff0);
11414 vcpu->arch.cr3 = 0;
11415 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11418 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
11419 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
11420 * (or qualify) that with a footnote stating that CD/NW are preserved.
11422 new_cr0 = X86_CR0_ET;
11424 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
11426 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
11428 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
11429 static_call(kvm_x86_set_cr4)(vcpu, 0);
11430 static_call(kvm_x86_set_efer)(vcpu, 0);
11431 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11434 * On the standard CR0/CR4/EFER modification paths, there are several
11435 * complex conditions determining whether the MMU has to be reset and/or
11436 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
11437 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
11438 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
11439 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
11441 if (old_cr0 & X86_CR0_PG) {
11442 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11443 kvm_mmu_reset_context(vcpu);
11447 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
11448 * APM states the TLBs are untouched by INIT, but it also states that
11449 * the TLBs are flushed on "External initialization of the processor."
11450 * Flush the guest TLB regardless of vendor, there is no meaningful
11451 * benefit in relying on the guest to flush the TLB immediately after
11452 * INIT. A spurious TLB flush is benign and likely negligible from a
11453 * performance perspective.
11456 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11458 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
11460 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
11462 struct kvm_segment cs;
11464 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
11465 cs.selector = vector << 8;
11466 cs.base = vector << 12;
11467 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
11468 kvm_rip_write(vcpu, 0);
11470 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
11472 int kvm_arch_hardware_enable(void)
11475 struct kvm_vcpu *vcpu;
11480 bool stable, backwards_tsc = false;
11482 kvm_user_return_msr_cpu_online();
11483 ret = static_call(kvm_x86_hardware_enable)();
11487 local_tsc = rdtsc();
11488 stable = !kvm_check_tsc_unstable();
11489 list_for_each_entry(kvm, &vm_list, vm_list) {
11490 kvm_for_each_vcpu(i, vcpu, kvm) {
11491 if (!stable && vcpu->cpu == smp_processor_id())
11492 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
11493 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
11494 backwards_tsc = true;
11495 if (vcpu->arch.last_host_tsc > max_tsc)
11496 max_tsc = vcpu->arch.last_host_tsc;
11502 * Sometimes, even reliable TSCs go backwards. This happens on
11503 * platforms that reset TSC during suspend or hibernate actions, but
11504 * maintain synchronization. We must compensate. Fortunately, we can
11505 * detect that condition here, which happens early in CPU bringup,
11506 * before any KVM threads can be running. Unfortunately, we can't
11507 * bring the TSCs fully up to date with real time, as we aren't yet far
11508 * enough into CPU bringup that we know how much real time has actually
11509 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
11510 * variables that haven't been updated yet.
11512 * So we simply find the maximum observed TSC above, then record the
11513 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
11514 * the adjustment will be applied. Note that we accumulate
11515 * adjustments, in case multiple suspend cycles happen before some VCPU
11516 * gets a chance to run again. In the event that no KVM threads get a
11517 * chance to run, we will miss the entire elapsed period, as we'll have
11518 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
11519 * loose cycle time. This isn't too big a deal, since the loss will be
11520 * uniform across all VCPUs (not to mention the scenario is extremely
11521 * unlikely). It is possible that a second hibernate recovery happens
11522 * much faster than a first, causing the observed TSC here to be
11523 * smaller; this would require additional padding adjustment, which is
11524 * why we set last_host_tsc to the local tsc observed here.
11526 * N.B. - this code below runs only on platforms with reliable TSC,
11527 * as that is the only way backwards_tsc is set above. Also note
11528 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
11529 * have the same delta_cyc adjustment applied if backwards_tsc
11530 * is detected. Note further, this adjustment is only done once,
11531 * as we reset last_host_tsc on all VCPUs to stop this from being
11532 * called multiple times (one for each physical CPU bringup).
11534 * Platforms with unreliable TSCs don't have to deal with this, they
11535 * will be compensated by the logic in vcpu_load, which sets the TSC to
11536 * catchup mode. This will catchup all VCPUs to real time, but cannot
11537 * guarantee that they stay in perfect synchronization.
11539 if (backwards_tsc) {
11540 u64 delta_cyc = max_tsc - local_tsc;
11541 list_for_each_entry(kvm, &vm_list, vm_list) {
11542 kvm->arch.backwards_tsc_observed = true;
11543 kvm_for_each_vcpu(i, vcpu, kvm) {
11544 vcpu->arch.tsc_offset_adjustment += delta_cyc;
11545 vcpu->arch.last_host_tsc = local_tsc;
11546 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
11550 * We have to disable TSC offset matching.. if you were
11551 * booting a VM while issuing an S4 host suspend....
11552 * you may have some problem. Solving this issue is
11553 * left as an exercise to the reader.
11555 kvm->arch.last_tsc_nsec = 0;
11556 kvm->arch.last_tsc_write = 0;
11563 void kvm_arch_hardware_disable(void)
11565 static_call(kvm_x86_hardware_disable)();
11566 drop_user_return_notifiers();
11569 int kvm_arch_hardware_setup(void *opaque)
11571 struct kvm_x86_init_ops *ops = opaque;
11574 rdmsrl_safe(MSR_EFER, &host_efer);
11576 if (boot_cpu_has(X86_FEATURE_XSAVES))
11577 rdmsrl(MSR_IA32_XSS, host_xss);
11579 r = ops->hardware_setup();
11583 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
11584 kvm_ops_static_call_update();
11586 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
11588 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
11591 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
11592 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
11593 #undef __kvm_cpu_cap_has
11595 if (kvm_has_tsc_control) {
11597 * Make sure the user can only configure tsc_khz values that
11598 * fit into a signed integer.
11599 * A min value is not calculated because it will always
11600 * be 1 on all machines.
11602 u64 max = min(0x7fffffffULL,
11603 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
11604 kvm_max_guest_tsc_khz = max;
11606 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
11607 kvm_init_msr_list();
11611 void kvm_arch_hardware_unsetup(void)
11613 kvm_unregister_perf_callbacks();
11615 static_call(kvm_x86_hardware_unsetup)();
11618 int kvm_arch_check_processor_compat(void *opaque)
11620 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
11621 struct kvm_x86_init_ops *ops = opaque;
11623 WARN_ON(!irqs_disabled());
11625 if (__cr4_reserved_bits(cpu_has, c) !=
11626 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
11629 return ops->check_processor_compatibility();
11632 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
11634 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
11636 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
11638 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
11640 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
11643 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
11644 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
11646 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
11648 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
11650 vcpu->arch.l1tf_flush_l1d = true;
11651 if (pmu->version && unlikely(pmu->event_count)) {
11652 pmu->need_cleanup = true;
11653 kvm_make_request(KVM_REQ_PMU, vcpu);
11655 static_call(kvm_x86_sched_in)(vcpu, cpu);
11658 void kvm_arch_free_vm(struct kvm *kvm)
11660 kfree(to_kvm_hv(kvm)->hv_pa_pg);
11661 __kvm_arch_free_vm(kvm);
11665 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
11668 unsigned long flags;
11673 ret = kvm_page_track_init(kvm);
11677 ret = kvm_mmu_init_vm(kvm);
11679 goto out_page_track;
11681 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
11682 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
11683 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
11685 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
11686 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
11687 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
11688 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
11689 &kvm->arch.irq_sources_bitmap);
11691 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
11692 mutex_init(&kvm->arch.apic_map_lock);
11693 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
11694 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
11696 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
11697 pvclock_update_vm_gtod_copy(kvm);
11698 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
11700 kvm->arch.guest_can_read_msr_platform_info = true;
11701 kvm->arch.enable_pmu = enable_pmu;
11703 #if IS_ENABLED(CONFIG_HYPERV)
11704 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
11705 kvm->arch.hv_root_tdp = INVALID_PAGE;
11708 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
11709 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
11711 kvm_apicv_init(kvm);
11712 kvm_hv_init_vm(kvm);
11713 kvm_xen_init_vm(kvm);
11715 return static_call(kvm_x86_vm_init)(kvm);
11718 kvm_page_track_cleanup(kvm);
11723 int kvm_arch_post_init_vm(struct kvm *kvm)
11725 return kvm_mmu_post_init_vm(kvm);
11728 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
11731 kvm_mmu_unload(vcpu);
11735 static void kvm_free_vcpus(struct kvm *kvm)
11738 struct kvm_vcpu *vcpu;
11741 * Unpin any mmu pages first.
11743 kvm_for_each_vcpu(i, vcpu, kvm) {
11744 kvm_clear_async_pf_completion_queue(vcpu);
11745 kvm_unload_vcpu_mmu(vcpu);
11748 kvm_destroy_vcpus(kvm);
11751 void kvm_arch_sync_events(struct kvm *kvm)
11753 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
11754 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
11759 * __x86_set_memory_region: Setup KVM internal memory slot
11761 * @kvm: the kvm pointer to the VM.
11762 * @id: the slot ID to setup.
11763 * @gpa: the GPA to install the slot (unused when @size == 0).
11764 * @size: the size of the slot. Set to zero to uninstall a slot.
11766 * This function helps to setup a KVM internal memory slot. Specify
11767 * @size > 0 to install a new slot, while @size == 0 to uninstall a
11768 * slot. The return code can be one of the following:
11770 * HVA: on success (uninstall will return a bogus HVA)
11773 * The caller should always use IS_ERR() to check the return value
11774 * before use. Note, the KVM internal memory slots are guaranteed to
11775 * remain valid and unchanged until the VM is destroyed, i.e., the
11776 * GPA->HVA translation will not change. However, the HVA is a user
11777 * address, i.e. its accessibility is not guaranteed, and must be
11778 * accessed via __copy_{to,from}_user().
11780 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
11784 unsigned long hva, old_npages;
11785 struct kvm_memslots *slots = kvm_memslots(kvm);
11786 struct kvm_memory_slot *slot;
11788 /* Called with kvm->slots_lock held. */
11789 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
11790 return ERR_PTR_USR(-EINVAL);
11792 slot = id_to_memslot(slots, id);
11794 if (slot && slot->npages)
11795 return ERR_PTR_USR(-EEXIST);
11798 * MAP_SHARED to prevent internal slot pages from being moved
11801 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
11802 MAP_SHARED | MAP_ANONYMOUS, 0);
11803 if (IS_ERR((void *)hva))
11804 return (void __user *)hva;
11806 if (!slot || !slot->npages)
11809 old_npages = slot->npages;
11810 hva = slot->userspace_addr;
11813 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
11814 struct kvm_userspace_memory_region m;
11816 m.slot = id | (i << 16);
11818 m.guest_phys_addr = gpa;
11819 m.userspace_addr = hva;
11820 m.memory_size = size;
11821 r = __kvm_set_memory_region(kvm, &m);
11823 return ERR_PTR_USR(r);
11827 vm_munmap(hva, old_npages * PAGE_SIZE);
11829 return (void __user *)hva;
11831 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
11833 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
11835 kvm_mmu_pre_destroy_vm(kvm);
11838 void kvm_arch_destroy_vm(struct kvm *kvm)
11840 if (current->mm == kvm->mm) {
11842 * Free memory regions allocated on behalf of userspace,
11843 * unless the the memory map has changed due to process exit
11846 mutex_lock(&kvm->slots_lock);
11847 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
11849 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
11851 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
11852 mutex_unlock(&kvm->slots_lock);
11854 static_call_cond(kvm_x86_vm_destroy)(kvm);
11855 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
11856 kvm_pic_destroy(kvm);
11857 kvm_ioapic_destroy(kvm);
11858 kvm_free_vcpus(kvm);
11859 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
11860 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
11861 kvm_mmu_uninit_vm(kvm);
11862 kvm_page_track_cleanup(kvm);
11863 kvm_xen_destroy_vm(kvm);
11864 kvm_hv_destroy_vm(kvm);
11867 static void memslot_rmap_free(struct kvm_memory_slot *slot)
11871 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
11872 kvfree(slot->arch.rmap[i]);
11873 slot->arch.rmap[i] = NULL;
11877 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
11881 memslot_rmap_free(slot);
11883 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
11884 kvfree(slot->arch.lpage_info[i - 1]);
11885 slot->arch.lpage_info[i - 1] = NULL;
11888 kvm_page_track_free_memslot(slot);
11891 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
11893 const int sz = sizeof(*slot->arch.rmap[0]);
11896 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
11898 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
11900 if (slot->arch.rmap[i])
11903 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
11904 if (!slot->arch.rmap[i]) {
11905 memslot_rmap_free(slot);
11913 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
11914 struct kvm_memory_slot *slot)
11916 unsigned long npages = slot->npages;
11920 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
11921 * old arrays will be freed by __kvm_set_memory_region() if installing
11922 * the new memslot is successful.
11924 memset(&slot->arch, 0, sizeof(slot->arch));
11926 if (kvm_memslots_have_rmaps(kvm)) {
11927 r = memslot_rmap_alloc(slot, npages);
11932 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
11933 struct kvm_lpage_info *linfo;
11934 unsigned long ugfn;
11938 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
11940 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
11944 slot->arch.lpage_info[i - 1] = linfo;
11946 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
11947 linfo[0].disallow_lpage = 1;
11948 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
11949 linfo[lpages - 1].disallow_lpage = 1;
11950 ugfn = slot->userspace_addr >> PAGE_SHIFT;
11952 * If the gfn and userspace address are not aligned wrt each
11953 * other, disable large page support for this slot.
11955 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
11958 for (j = 0; j < lpages; ++j)
11959 linfo[j].disallow_lpage = 1;
11963 if (kvm_page_track_create_memslot(kvm, slot, npages))
11969 memslot_rmap_free(slot);
11971 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
11972 kvfree(slot->arch.lpage_info[i - 1]);
11973 slot->arch.lpage_info[i - 1] = NULL;
11978 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
11980 struct kvm_vcpu *vcpu;
11984 * memslots->generation has been incremented.
11985 * mmio generation may have reached its maximum value.
11987 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
11989 /* Force re-initialization of steal_time cache */
11990 kvm_for_each_vcpu(i, vcpu, kvm)
11991 kvm_vcpu_kick(vcpu);
11994 int kvm_arch_prepare_memory_region(struct kvm *kvm,
11995 const struct kvm_memory_slot *old,
11996 struct kvm_memory_slot *new,
11997 enum kvm_mr_change change)
11999 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
12000 return kvm_alloc_memslot_metadata(kvm, new);
12002 if (change == KVM_MR_FLAGS_ONLY)
12003 memcpy(&new->arch, &old->arch, sizeof(old->arch));
12004 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12011 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12013 struct kvm_arch *ka = &kvm->arch;
12015 if (!kvm_x86_ops.cpu_dirty_log_size)
12018 if ((enable && ++ka->cpu_dirty_logging_count == 1) ||
12019 (!enable && --ka->cpu_dirty_logging_count == 0))
12020 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12022 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0);
12025 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12026 struct kvm_memory_slot *old,
12027 const struct kvm_memory_slot *new,
12028 enum kvm_mr_change change)
12030 u32 old_flags = old ? old->flags : 0;
12031 u32 new_flags = new ? new->flags : 0;
12032 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12035 * Update CPU dirty logging if dirty logging is being toggled. This
12036 * applies to all operations.
12038 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12039 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12042 * Nothing more to do for RO slots (which can't be dirtied and can't be
12043 * made writable) or CREATE/MOVE/DELETE of a slot.
12045 * For a memslot with dirty logging disabled:
12046 * CREATE: No dirty mappings will already exist.
12047 * MOVE/DELETE: The old mappings will already have been cleaned up by
12048 * kvm_arch_flush_shadow_memslot()
12050 * For a memslot with dirty logging enabled:
12051 * CREATE: No shadow pages exist, thus nothing to write-protect
12052 * and no dirty bits to clear.
12053 * MOVE/DELETE: The old mappings will already have been cleaned up by
12054 * kvm_arch_flush_shadow_memslot().
12056 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12060 * READONLY and non-flags changes were filtered out above, and the only
12061 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12062 * logging isn't being toggled on or off.
12064 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12067 if (!log_dirty_pages) {
12069 * Dirty logging tracks sptes in 4k granularity, meaning that
12070 * large sptes have to be split. If live migration succeeds,
12071 * the guest in the source machine will be destroyed and large
12072 * sptes will be created in the destination. However, if the
12073 * guest continues to run in the source machine (for example if
12074 * live migration fails), small sptes will remain around and
12075 * cause bad performance.
12077 * Scan sptes if dirty logging has been stopped, dropping those
12078 * which can be collapsed into a single large-page spte. Later
12079 * page faults will create the large-page sptes.
12081 kvm_mmu_zap_collapsible_sptes(kvm, new);
12084 * Initially-all-set does not require write protecting any page,
12085 * because they're all assumed to be dirty.
12087 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12090 if (READ_ONCE(eager_page_split))
12091 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12093 if (kvm_x86_ops.cpu_dirty_log_size) {
12094 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12095 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12097 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12102 void kvm_arch_commit_memory_region(struct kvm *kvm,
12103 struct kvm_memory_slot *old,
12104 const struct kvm_memory_slot *new,
12105 enum kvm_mr_change change)
12107 if (!kvm->arch.n_requested_mmu_pages &&
12108 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
12109 unsigned long nr_mmu_pages;
12111 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
12112 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
12113 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
12116 kvm_mmu_slot_apply_flags(kvm, old, new, change);
12118 /* Free the arrays associated with the old memslot. */
12119 if (change == KVM_MR_MOVE)
12120 kvm_arch_free_memslot(kvm, old);
12123 void kvm_arch_flush_shadow_all(struct kvm *kvm)
12125 kvm_mmu_zap_all(kvm);
12128 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
12129 struct kvm_memory_slot *slot)
12131 kvm_page_track_flush_slot(kvm, slot);
12134 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
12136 return (is_guest_mode(vcpu) &&
12137 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
12140 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
12142 if (!list_empty_careful(&vcpu->async_pf.done))
12145 if (kvm_apic_has_events(vcpu))
12148 if (vcpu->arch.pv.pv_unhalted)
12151 if (vcpu->arch.exception.pending)
12154 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12155 (vcpu->arch.nmi_pending &&
12156 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
12159 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
12160 (vcpu->arch.smi_pending &&
12161 static_call(kvm_x86_smi_allowed)(vcpu, false)))
12164 if (kvm_arch_interrupt_allowed(vcpu) &&
12165 (kvm_cpu_has_interrupt(vcpu) ||
12166 kvm_guest_apic_has_interrupt(vcpu)))
12169 if (kvm_hv_has_stimer_pending(vcpu))
12172 if (is_guest_mode(vcpu) &&
12173 kvm_x86_ops.nested_ops->hv_timer_pending &&
12174 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
12180 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
12182 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
12185 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
12187 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
12193 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
12195 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
12198 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12199 kvm_test_request(KVM_REQ_SMI, vcpu) ||
12200 kvm_test_request(KVM_REQ_EVENT, vcpu))
12203 return kvm_arch_dy_has_pending_interrupt(vcpu);
12206 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
12208 if (vcpu->arch.guest_state_protected)
12211 return vcpu->arch.preempted_in_kernel;
12214 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
12216 return kvm_rip_read(vcpu);
12219 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
12221 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
12224 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
12226 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
12229 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
12231 /* Can't read the RIP when guest state is protected, just return 0 */
12232 if (vcpu->arch.guest_state_protected)
12235 if (is_64_bit_mode(vcpu))
12236 return kvm_rip_read(vcpu);
12237 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
12238 kvm_rip_read(vcpu));
12240 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
12242 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
12244 return kvm_get_linear_rip(vcpu) == linear_rip;
12246 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
12248 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
12250 unsigned long rflags;
12252 rflags = static_call(kvm_x86_get_rflags)(vcpu);
12253 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
12254 rflags &= ~X86_EFLAGS_TF;
12257 EXPORT_SYMBOL_GPL(kvm_get_rflags);
12259 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12261 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
12262 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
12263 rflags |= X86_EFLAGS_TF;
12264 static_call(kvm_x86_set_rflags)(vcpu, rflags);
12267 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12269 __kvm_set_rflags(vcpu, rflags);
12270 kvm_make_request(KVM_REQ_EVENT, vcpu);
12272 EXPORT_SYMBOL_GPL(kvm_set_rflags);
12274 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
12278 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
12282 r = kvm_mmu_reload(vcpu);
12286 if (!vcpu->arch.mmu->direct_map &&
12287 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
12290 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
12293 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
12295 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
12297 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
12300 static inline u32 kvm_async_pf_next_probe(u32 key)
12302 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
12305 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12307 u32 key = kvm_async_pf_hash_fn(gfn);
12309 while (vcpu->arch.apf.gfns[key] != ~0)
12310 key = kvm_async_pf_next_probe(key);
12312 vcpu->arch.apf.gfns[key] = gfn;
12315 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
12318 u32 key = kvm_async_pf_hash_fn(gfn);
12320 for (i = 0; i < ASYNC_PF_PER_VCPU &&
12321 (vcpu->arch.apf.gfns[key] != gfn &&
12322 vcpu->arch.apf.gfns[key] != ~0); i++)
12323 key = kvm_async_pf_next_probe(key);
12328 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12330 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
12333 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12337 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
12339 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
12343 vcpu->arch.apf.gfns[i] = ~0;
12345 j = kvm_async_pf_next_probe(j);
12346 if (vcpu->arch.apf.gfns[j] == ~0)
12348 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
12350 * k lies cyclically in ]i,j]
12352 * |....j i.k.| or |.k..j i...|
12354 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
12355 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
12360 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
12362 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
12364 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
12368 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
12370 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12372 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12373 &token, offset, sizeof(token));
12376 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
12378 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12381 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12382 &val, offset, sizeof(val)))
12388 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
12391 if (!kvm_pv_async_pf_enabled(vcpu))
12394 if (vcpu->arch.apf.send_user_only &&
12395 static_call(kvm_x86_get_cpl)(vcpu) == 0)
12398 if (is_guest_mode(vcpu)) {
12400 * L1 needs to opt into the special #PF vmexits that are
12401 * used to deliver async page faults.
12403 return vcpu->arch.apf.delivery_as_pf_vmexit;
12406 * Play it safe in case the guest temporarily disables paging.
12407 * The real mode IDT in particular is unlikely to have a #PF
12410 return is_paging(vcpu);
12414 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
12416 if (unlikely(!lapic_in_kernel(vcpu) ||
12417 kvm_event_needs_reinjection(vcpu) ||
12418 vcpu->arch.exception.pending))
12421 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
12425 * If interrupts are off we cannot even use an artificial
12428 return kvm_arch_interrupt_allowed(vcpu);
12431 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
12432 struct kvm_async_pf *work)
12434 struct x86_exception fault;
12436 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
12437 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
12439 if (kvm_can_deliver_async_pf(vcpu) &&
12440 !apf_put_user_notpresent(vcpu)) {
12441 fault.vector = PF_VECTOR;
12442 fault.error_code_valid = true;
12443 fault.error_code = 0;
12444 fault.nested_page_fault = false;
12445 fault.address = work->arch.token;
12446 fault.async_page_fault = true;
12447 kvm_inject_page_fault(vcpu, &fault);
12451 * It is not possible to deliver a paravirtualized asynchronous
12452 * page fault, but putting the guest in an artificial halt state
12453 * can be beneficial nevertheless: if an interrupt arrives, we
12454 * can deliver it timely and perhaps the guest will schedule
12455 * another process. When the instruction that triggered a page
12456 * fault is retried, hopefully the page will be ready in the host.
12458 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
12463 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
12464 struct kvm_async_pf *work)
12466 struct kvm_lapic_irq irq = {
12467 .delivery_mode = APIC_DM_FIXED,
12468 .vector = vcpu->arch.apf.vec
12471 if (work->wakeup_all)
12472 work->arch.token = ~0; /* broadcast wakeup */
12474 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
12475 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
12477 if ((work->wakeup_all || work->notpresent_injected) &&
12478 kvm_pv_async_pf_enabled(vcpu) &&
12479 !apf_put_user_ready(vcpu, work->arch.token)) {
12480 vcpu->arch.apf.pageready_pending = true;
12481 kvm_apic_set_irq(vcpu, &irq, NULL);
12484 vcpu->arch.apf.halted = false;
12485 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12488 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
12490 kvm_make_request(KVM_REQ_APF_READY, vcpu);
12491 if (!vcpu->arch.apf.pageready_pending)
12492 kvm_vcpu_kick(vcpu);
12495 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
12497 if (!kvm_pv_async_pf_enabled(vcpu))
12500 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
12503 void kvm_arch_start_assignment(struct kvm *kvm)
12505 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
12506 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
12508 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
12510 void kvm_arch_end_assignment(struct kvm *kvm)
12512 atomic_dec(&kvm->arch.assigned_device_count);
12514 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
12516 bool kvm_arch_has_assigned_device(struct kvm *kvm)
12518 return atomic_read(&kvm->arch.assigned_device_count);
12520 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
12522 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
12524 atomic_inc(&kvm->arch.noncoherent_dma_count);
12526 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
12528 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
12530 atomic_dec(&kvm->arch.noncoherent_dma_count);
12532 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
12534 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
12536 return atomic_read(&kvm->arch.noncoherent_dma_count);
12538 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
12540 bool kvm_arch_has_irq_bypass(void)
12545 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
12546 struct irq_bypass_producer *prod)
12548 struct kvm_kernel_irqfd *irqfd =
12549 container_of(cons, struct kvm_kernel_irqfd, consumer);
12552 irqfd->producer = prod;
12553 kvm_arch_start_assignment(irqfd->kvm);
12554 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
12555 prod->irq, irqfd->gsi, 1);
12558 kvm_arch_end_assignment(irqfd->kvm);
12563 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
12564 struct irq_bypass_producer *prod)
12567 struct kvm_kernel_irqfd *irqfd =
12568 container_of(cons, struct kvm_kernel_irqfd, consumer);
12570 WARN_ON(irqfd->producer != prod);
12571 irqfd->producer = NULL;
12574 * When producer of consumer is unregistered, we change back to
12575 * remapped mode, so we can re-use the current implementation
12576 * when the irq is masked/disabled or the consumer side (KVM
12577 * int this case doesn't want to receive the interrupts.
12579 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
12581 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
12582 " fails: %d\n", irqfd->consumer.token, ret);
12584 kvm_arch_end_assignment(irqfd->kvm);
12587 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
12588 uint32_t guest_irq, bool set)
12590 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
12593 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
12594 struct kvm_kernel_irq_routing_entry *new)
12596 if (new->type != KVM_IRQ_ROUTING_MSI)
12599 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
12602 bool kvm_vector_hashing_enabled(void)
12604 return vector_hashing;
12607 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
12609 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
12611 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
12614 int kvm_spec_ctrl_test_value(u64 value)
12617 * test that setting IA32_SPEC_CTRL to given value
12618 * is allowed by the host processor
12622 unsigned long flags;
12625 local_irq_save(flags);
12627 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
12629 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
12632 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
12634 local_irq_restore(flags);
12638 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
12640 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
12642 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
12643 struct x86_exception fault;
12644 u64 access = error_code &
12645 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
12647 if (!(error_code & PFERR_PRESENT_MASK) ||
12648 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != UNMAPPED_GVA) {
12650 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
12651 * tables probably do not match the TLB. Just proceed
12652 * with the error code that the processor gave.
12654 fault.vector = PF_VECTOR;
12655 fault.error_code_valid = true;
12656 fault.error_code = error_code;
12657 fault.nested_page_fault = false;
12658 fault.address = gva;
12660 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
12662 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
12665 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
12666 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
12667 * indicates whether exit to userspace is needed.
12669 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
12670 struct x86_exception *e)
12672 if (r == X86EMUL_PROPAGATE_FAULT) {
12673 kvm_inject_emulated_page_fault(vcpu, e);
12678 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
12679 * while handling a VMX instruction KVM could've handled the request
12680 * correctly by exiting to userspace and performing I/O but there
12681 * doesn't seem to be a real use-case behind such requests, just return
12682 * KVM_EXIT_INTERNAL_ERROR for now.
12684 kvm_prepare_emulation_failure_exit(vcpu);
12688 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
12690 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
12693 struct x86_exception e;
12700 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
12701 if (r != X86EMUL_CONTINUE)
12702 return kvm_handle_memory_failure(vcpu, r, &e);
12704 if (operand.pcid >> 12 != 0) {
12705 kvm_inject_gp(vcpu, 0);
12709 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
12712 case INVPCID_TYPE_INDIV_ADDR:
12713 if ((!pcid_enabled && (operand.pcid != 0)) ||
12714 is_noncanonical_address(operand.gla, vcpu)) {
12715 kvm_inject_gp(vcpu, 0);
12718 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
12719 return kvm_skip_emulated_instruction(vcpu);
12721 case INVPCID_TYPE_SINGLE_CTXT:
12722 if (!pcid_enabled && (operand.pcid != 0)) {
12723 kvm_inject_gp(vcpu, 0);
12727 kvm_invalidate_pcid(vcpu, operand.pcid);
12728 return kvm_skip_emulated_instruction(vcpu);
12730 case INVPCID_TYPE_ALL_NON_GLOBAL:
12732 * Currently, KVM doesn't mark global entries in the shadow
12733 * page tables, so a non-global flush just degenerates to a
12734 * global flush. If needed, we could optimize this later by
12735 * keeping track of global entries in shadow page tables.
12739 case INVPCID_TYPE_ALL_INCL_GLOBAL:
12740 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12741 return kvm_skip_emulated_instruction(vcpu);
12744 kvm_inject_gp(vcpu, 0);
12748 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
12750 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
12752 struct kvm_run *run = vcpu->run;
12753 struct kvm_mmio_fragment *frag;
12756 BUG_ON(!vcpu->mmio_needed);
12758 /* Complete previous fragment */
12759 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
12760 len = min(8u, frag->len);
12761 if (!vcpu->mmio_is_write)
12762 memcpy(frag->data, run->mmio.data, len);
12764 if (frag->len <= 8) {
12765 /* Switch to the next fragment. */
12767 vcpu->mmio_cur_fragment++;
12769 /* Go forward to the next mmio piece. */
12775 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
12776 vcpu->mmio_needed = 0;
12778 // VMG change, at this point, we're always done
12779 // RIP has already been advanced
12783 // More MMIO is needed
12784 run->mmio.phys_addr = frag->gpa;
12785 run->mmio.len = min(8u, frag->len);
12786 run->mmio.is_write = vcpu->mmio_is_write;
12787 if (run->mmio.is_write)
12788 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
12789 run->exit_reason = KVM_EXIT_MMIO;
12791 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
12796 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
12800 struct kvm_mmio_fragment *frag;
12805 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
12806 if (handled == bytes)
12813 /*TODO: Check if need to increment number of frags */
12814 frag = vcpu->mmio_fragments;
12815 vcpu->mmio_nr_fragments = 1;
12820 vcpu->mmio_needed = 1;
12821 vcpu->mmio_cur_fragment = 0;
12823 vcpu->run->mmio.phys_addr = gpa;
12824 vcpu->run->mmio.len = min(8u, frag->len);
12825 vcpu->run->mmio.is_write = 1;
12826 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
12827 vcpu->run->exit_reason = KVM_EXIT_MMIO;
12829 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
12833 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
12835 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
12839 struct kvm_mmio_fragment *frag;
12844 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
12845 if (handled == bytes)
12852 /*TODO: Check if need to increment number of frags */
12853 frag = vcpu->mmio_fragments;
12854 vcpu->mmio_nr_fragments = 1;
12859 vcpu->mmio_needed = 1;
12860 vcpu->mmio_cur_fragment = 0;
12862 vcpu->run->mmio.phys_addr = gpa;
12863 vcpu->run->mmio.len = min(8u, frag->len);
12864 vcpu->run->mmio.is_write = 0;
12865 vcpu->run->exit_reason = KVM_EXIT_MMIO;
12867 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
12871 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
12873 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
12874 unsigned int port);
12876 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
12878 int size = vcpu->arch.pio.size;
12879 int port = vcpu->arch.pio.port;
12881 vcpu->arch.pio.count = 0;
12882 if (vcpu->arch.sev_pio_count)
12883 return kvm_sev_es_outs(vcpu, size, port);
12887 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
12891 unsigned int count =
12892 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
12893 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
12895 /* memcpy done already by emulator_pio_out. */
12896 vcpu->arch.sev_pio_count -= count;
12897 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size;
12901 /* Emulation done by the kernel. */
12902 if (!vcpu->arch.sev_pio_count)
12906 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
12910 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
12911 unsigned int port);
12913 static void advance_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
12915 unsigned count = vcpu->arch.pio.count;
12916 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
12917 vcpu->arch.sev_pio_count -= count;
12918 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size;
12921 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
12923 int size = vcpu->arch.pio.size;
12924 int port = vcpu->arch.pio.port;
12926 advance_sev_es_emulated_ins(vcpu);
12927 if (vcpu->arch.sev_pio_count)
12928 return kvm_sev_es_ins(vcpu, size, port);
12932 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
12936 unsigned int count =
12937 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
12938 if (!__emulator_pio_in(vcpu, size, port, count))
12941 /* Emulation done by the kernel. */
12942 advance_sev_es_emulated_ins(vcpu);
12943 if (!vcpu->arch.sev_pio_count)
12947 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
12951 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
12952 unsigned int port, void *data, unsigned int count,
12955 vcpu->arch.sev_pio_data = data;
12956 vcpu->arch.sev_pio_count = count;
12957 return in ? kvm_sev_es_ins(vcpu, size, port)
12958 : kvm_sev_es_outs(vcpu, size, port);
12960 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
12962 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
12963 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
12964 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
12965 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
12966 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
12967 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
12968 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
12969 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
12970 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
12971 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
12972 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
12973 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
12974 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
12975 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
12976 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
12977 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
12978 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
12979 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
12980 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
12981 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
12982 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
12983 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
12984 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
12985 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
12986 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
12987 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
12988 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);