2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include <linux/nospec.h>
38 #include "kvm_cache_regs.h"
45 #include <asm/virtext.h>
47 #include <asm/fpu/internal.h>
48 #include <asm/perf_event.h>
49 #include <asm/debugreg.h>
50 #include <asm/kexec.h>
52 #include <asm/irq_remapping.h>
53 #include <asm/mmu_context.h>
54 #include <asm/spec-ctrl.h>
55 #include <asm/mshyperv.h>
59 #include "vmx_evmcs.h"
61 #define __ex(x) __kvm_handle_fault_on_reboot(x)
62 #define __ex_clear(x, reg) \
63 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
65 MODULE_AUTHOR("Qumranet");
66 MODULE_LICENSE("GPL");
68 static const struct x86_cpu_id vmx_cpu_id[] = {
69 X86_FEATURE_MATCH(X86_FEATURE_VMX),
72 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
74 static bool __read_mostly enable_vpid = 1;
75 module_param_named(vpid, enable_vpid, bool, 0444);
77 static bool __read_mostly enable_vnmi = 1;
78 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
80 static bool __read_mostly flexpriority_enabled = 1;
81 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
83 static bool __read_mostly enable_ept = 1;
84 module_param_named(ept, enable_ept, bool, S_IRUGO);
86 static bool __read_mostly enable_unrestricted_guest = 1;
87 module_param_named(unrestricted_guest,
88 enable_unrestricted_guest, bool, S_IRUGO);
90 static bool __read_mostly enable_ept_ad_bits = 1;
91 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
93 static bool __read_mostly emulate_invalid_guest_state = true;
94 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
96 static bool __read_mostly fasteoi = 1;
97 module_param(fasteoi, bool, S_IRUGO);
99 static bool __read_mostly enable_apicv = 1;
100 module_param(enable_apicv, bool, S_IRUGO);
102 static bool __read_mostly enable_shadow_vmcs = 1;
103 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
105 * If nested=1, nested virtualization is supported, i.e., guests may use
106 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
107 * use VMX instructions.
109 static bool __read_mostly nested = 0;
110 module_param(nested, bool, S_IRUGO);
112 static u64 __read_mostly host_xss;
114 static bool __read_mostly enable_pml = 1;
115 module_param_named(pml, enable_pml, bool, S_IRUGO);
119 #define MSR_TYPE_RW 3
121 #define MSR_BITMAP_MODE_X2APIC 1
122 #define MSR_BITMAP_MODE_X2APIC_APICV 2
123 #define MSR_BITMAP_MODE_LM 4
125 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
127 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
128 static int __read_mostly cpu_preemption_timer_multi;
129 static bool __read_mostly enable_preemption_timer = 1;
131 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
134 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
135 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
136 #define KVM_VM_CR0_ALWAYS_ON \
137 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
138 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
139 #define KVM_CR4_GUEST_OWNED_BITS \
140 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
141 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
143 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
144 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
145 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
147 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
149 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
152 * Hyper-V requires all of these, so mark them as supported even though
153 * they are just treated the same as all-context.
155 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
156 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
157 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
158 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
159 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
162 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
163 * ple_gap: upper bound on the amount of time between two successive
164 * executions of PAUSE in a loop. Also indicate if ple enabled.
165 * According to test, this time is usually smaller than 128 cycles.
166 * ple_window: upper bound on the amount of time a guest is allowed to execute
167 * in a PAUSE loop. Tests indicate that most spinlocks are held for
168 * less than 2^12 cycles
169 * Time is measured based on a counter that runs at the same rate as the TSC,
170 * refer SDM volume 3b section 21.6.13 & 22.1.3.
172 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
174 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
175 module_param(ple_window, uint, 0444);
177 /* Default doubles per-vcpu window every exit. */
178 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
179 module_param(ple_window_grow, uint, 0444);
181 /* Default resets per-vcpu window every exit to ple_window. */
182 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
183 module_param(ple_window_shrink, uint, 0444);
185 /* Default is to compute the maximum so we can never overflow. */
186 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
187 module_param(ple_window_max, uint, 0444);
189 extern const ulong vmx_return;
194 unsigned int tss_addr;
195 bool ept_identity_pagetable_done;
196 gpa_t ept_identity_map_addr;
199 #define NR_AUTOLOAD_MSRS 8
208 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
209 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
210 * loaded on this CPU (so we can clear them if the CPU goes down).
214 struct vmcs *shadow_vmcs;
217 bool nmi_known_unmasked;
218 unsigned long vmcs_host_cr3; /* May not match real cr3 */
219 unsigned long vmcs_host_cr4; /* May not match real cr4 */
220 /* Support for vnmi-less CPUs */
221 int soft_vnmi_blocked;
223 s64 vnmi_blocked_time;
224 unsigned long *msr_bitmap;
225 struct list_head loaded_vmcss_on_cpu_link;
228 struct shared_msr_entry {
235 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
236 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
237 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
238 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
239 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
240 * More than one of these structures may exist, if L1 runs multiple L2 guests.
241 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
242 * underlying hardware which will be used to run L2.
243 * This structure is packed to ensure that its layout is identical across
244 * machines (necessary for live migration).
246 * IMPORTANT: Changing the layout of existing fields in this structure
247 * will break save/restore compatibility with older kvm releases. When
248 * adding new fields, either use space in the reserved padding* arrays
249 * or add the new fields to the end of the structure.
251 typedef u64 natural_width;
252 struct __packed vmcs12 {
253 /* According to the Intel spec, a VMCS region must start with the
254 * following two fields. Then follow implementation-specific data.
259 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
260 u32 padding[7]; /* room for future expansion */
265 u64 vm_exit_msr_store_addr;
266 u64 vm_exit_msr_load_addr;
267 u64 vm_entry_msr_load_addr;
269 u64 virtual_apic_page_addr;
270 u64 apic_access_addr;
271 u64 posted_intr_desc_addr;
273 u64 eoi_exit_bitmap0;
274 u64 eoi_exit_bitmap1;
275 u64 eoi_exit_bitmap2;
276 u64 eoi_exit_bitmap3;
278 u64 guest_physical_address;
279 u64 vmcs_link_pointer;
280 u64 guest_ia32_debugctl;
283 u64 guest_ia32_perf_global_ctrl;
291 u64 host_ia32_perf_global_ctrl;
294 u64 vm_function_control;
295 u64 eptp_list_address;
297 u64 padding64[3]; /* room for future expansion */
299 * To allow migration of L1 (complete with its L2 guests) between
300 * machines of different natural widths (32 or 64 bit), we cannot have
301 * unsigned long fields with no explict size. We use u64 (aliased
302 * natural_width) instead. Luckily, x86 is little-endian.
304 natural_width cr0_guest_host_mask;
305 natural_width cr4_guest_host_mask;
306 natural_width cr0_read_shadow;
307 natural_width cr4_read_shadow;
308 natural_width cr3_target_value0;
309 natural_width cr3_target_value1;
310 natural_width cr3_target_value2;
311 natural_width cr3_target_value3;
312 natural_width exit_qualification;
313 natural_width guest_linear_address;
314 natural_width guest_cr0;
315 natural_width guest_cr3;
316 natural_width guest_cr4;
317 natural_width guest_es_base;
318 natural_width guest_cs_base;
319 natural_width guest_ss_base;
320 natural_width guest_ds_base;
321 natural_width guest_fs_base;
322 natural_width guest_gs_base;
323 natural_width guest_ldtr_base;
324 natural_width guest_tr_base;
325 natural_width guest_gdtr_base;
326 natural_width guest_idtr_base;
327 natural_width guest_dr7;
328 natural_width guest_rsp;
329 natural_width guest_rip;
330 natural_width guest_rflags;
331 natural_width guest_pending_dbg_exceptions;
332 natural_width guest_sysenter_esp;
333 natural_width guest_sysenter_eip;
334 natural_width host_cr0;
335 natural_width host_cr3;
336 natural_width host_cr4;
337 natural_width host_fs_base;
338 natural_width host_gs_base;
339 natural_width host_tr_base;
340 natural_width host_gdtr_base;
341 natural_width host_idtr_base;
342 natural_width host_ia32_sysenter_esp;
343 natural_width host_ia32_sysenter_eip;
344 natural_width host_rsp;
345 natural_width host_rip;
346 natural_width paddingl[8]; /* room for future expansion */
347 u32 pin_based_vm_exec_control;
348 u32 cpu_based_vm_exec_control;
349 u32 exception_bitmap;
350 u32 page_fault_error_code_mask;
351 u32 page_fault_error_code_match;
352 u32 cr3_target_count;
353 u32 vm_exit_controls;
354 u32 vm_exit_msr_store_count;
355 u32 vm_exit_msr_load_count;
356 u32 vm_entry_controls;
357 u32 vm_entry_msr_load_count;
358 u32 vm_entry_intr_info_field;
359 u32 vm_entry_exception_error_code;
360 u32 vm_entry_instruction_len;
362 u32 secondary_vm_exec_control;
363 u32 vm_instruction_error;
365 u32 vm_exit_intr_info;
366 u32 vm_exit_intr_error_code;
367 u32 idt_vectoring_info_field;
368 u32 idt_vectoring_error_code;
369 u32 vm_exit_instruction_len;
370 u32 vmx_instruction_info;
377 u32 guest_ldtr_limit;
379 u32 guest_gdtr_limit;
380 u32 guest_idtr_limit;
381 u32 guest_es_ar_bytes;
382 u32 guest_cs_ar_bytes;
383 u32 guest_ss_ar_bytes;
384 u32 guest_ds_ar_bytes;
385 u32 guest_fs_ar_bytes;
386 u32 guest_gs_ar_bytes;
387 u32 guest_ldtr_ar_bytes;
388 u32 guest_tr_ar_bytes;
389 u32 guest_interruptibility_info;
390 u32 guest_activity_state;
391 u32 guest_sysenter_cs;
392 u32 host_ia32_sysenter_cs;
393 u32 vmx_preemption_timer_value;
394 u32 padding32[7]; /* room for future expansion */
395 u16 virtual_processor_id;
397 u16 guest_es_selector;
398 u16 guest_cs_selector;
399 u16 guest_ss_selector;
400 u16 guest_ds_selector;
401 u16 guest_fs_selector;
402 u16 guest_gs_selector;
403 u16 guest_ldtr_selector;
404 u16 guest_tr_selector;
405 u16 guest_intr_status;
406 u16 host_es_selector;
407 u16 host_cs_selector;
408 u16 host_ss_selector;
409 u16 host_ds_selector;
410 u16 host_fs_selector;
411 u16 host_gs_selector;
412 u16 host_tr_selector;
417 * For save/restore compatibility, the vmcs12 field offsets must not change.
419 #define CHECK_OFFSET(field, loc) \
420 BUILD_BUG_ON_MSG(offsetof(struct vmcs12, field) != (loc), \
421 "Offset of " #field " in struct vmcs12 has changed.")
423 static inline void vmx_check_vmcs12_offsets(void) {
424 CHECK_OFFSET(revision_id, 0);
425 CHECK_OFFSET(abort, 4);
426 CHECK_OFFSET(launch_state, 8);
427 CHECK_OFFSET(io_bitmap_a, 40);
428 CHECK_OFFSET(io_bitmap_b, 48);
429 CHECK_OFFSET(msr_bitmap, 56);
430 CHECK_OFFSET(vm_exit_msr_store_addr, 64);
431 CHECK_OFFSET(vm_exit_msr_load_addr, 72);
432 CHECK_OFFSET(vm_entry_msr_load_addr, 80);
433 CHECK_OFFSET(tsc_offset, 88);
434 CHECK_OFFSET(virtual_apic_page_addr, 96);
435 CHECK_OFFSET(apic_access_addr, 104);
436 CHECK_OFFSET(posted_intr_desc_addr, 112);
437 CHECK_OFFSET(ept_pointer, 120);
438 CHECK_OFFSET(eoi_exit_bitmap0, 128);
439 CHECK_OFFSET(eoi_exit_bitmap1, 136);
440 CHECK_OFFSET(eoi_exit_bitmap2, 144);
441 CHECK_OFFSET(eoi_exit_bitmap3, 152);
442 CHECK_OFFSET(xss_exit_bitmap, 160);
443 CHECK_OFFSET(guest_physical_address, 168);
444 CHECK_OFFSET(vmcs_link_pointer, 176);
445 CHECK_OFFSET(guest_ia32_debugctl, 184);
446 CHECK_OFFSET(guest_ia32_pat, 192);
447 CHECK_OFFSET(guest_ia32_efer, 200);
448 CHECK_OFFSET(guest_ia32_perf_global_ctrl, 208);
449 CHECK_OFFSET(guest_pdptr0, 216);
450 CHECK_OFFSET(guest_pdptr1, 224);
451 CHECK_OFFSET(guest_pdptr2, 232);
452 CHECK_OFFSET(guest_pdptr3, 240);
453 CHECK_OFFSET(guest_bndcfgs, 248);
454 CHECK_OFFSET(host_ia32_pat, 256);
455 CHECK_OFFSET(host_ia32_efer, 264);
456 CHECK_OFFSET(host_ia32_perf_global_ctrl, 272);
457 CHECK_OFFSET(vmread_bitmap, 280);
458 CHECK_OFFSET(vmwrite_bitmap, 288);
459 CHECK_OFFSET(vm_function_control, 296);
460 CHECK_OFFSET(eptp_list_address, 304);
461 CHECK_OFFSET(pml_address, 312);
462 CHECK_OFFSET(cr0_guest_host_mask, 344);
463 CHECK_OFFSET(cr4_guest_host_mask, 352);
464 CHECK_OFFSET(cr0_read_shadow, 360);
465 CHECK_OFFSET(cr4_read_shadow, 368);
466 CHECK_OFFSET(cr3_target_value0, 376);
467 CHECK_OFFSET(cr3_target_value1, 384);
468 CHECK_OFFSET(cr3_target_value2, 392);
469 CHECK_OFFSET(cr3_target_value3, 400);
470 CHECK_OFFSET(exit_qualification, 408);
471 CHECK_OFFSET(guest_linear_address, 416);
472 CHECK_OFFSET(guest_cr0, 424);
473 CHECK_OFFSET(guest_cr3, 432);
474 CHECK_OFFSET(guest_cr4, 440);
475 CHECK_OFFSET(guest_es_base, 448);
476 CHECK_OFFSET(guest_cs_base, 456);
477 CHECK_OFFSET(guest_ss_base, 464);
478 CHECK_OFFSET(guest_ds_base, 472);
479 CHECK_OFFSET(guest_fs_base, 480);
480 CHECK_OFFSET(guest_gs_base, 488);
481 CHECK_OFFSET(guest_ldtr_base, 496);
482 CHECK_OFFSET(guest_tr_base, 504);
483 CHECK_OFFSET(guest_gdtr_base, 512);
484 CHECK_OFFSET(guest_idtr_base, 520);
485 CHECK_OFFSET(guest_dr7, 528);
486 CHECK_OFFSET(guest_rsp, 536);
487 CHECK_OFFSET(guest_rip, 544);
488 CHECK_OFFSET(guest_rflags, 552);
489 CHECK_OFFSET(guest_pending_dbg_exceptions, 560);
490 CHECK_OFFSET(guest_sysenter_esp, 568);
491 CHECK_OFFSET(guest_sysenter_eip, 576);
492 CHECK_OFFSET(host_cr0, 584);
493 CHECK_OFFSET(host_cr3, 592);
494 CHECK_OFFSET(host_cr4, 600);
495 CHECK_OFFSET(host_fs_base, 608);
496 CHECK_OFFSET(host_gs_base, 616);
497 CHECK_OFFSET(host_tr_base, 624);
498 CHECK_OFFSET(host_gdtr_base, 632);
499 CHECK_OFFSET(host_idtr_base, 640);
500 CHECK_OFFSET(host_ia32_sysenter_esp, 648);
501 CHECK_OFFSET(host_ia32_sysenter_eip, 656);
502 CHECK_OFFSET(host_rsp, 664);
503 CHECK_OFFSET(host_rip, 672);
504 CHECK_OFFSET(pin_based_vm_exec_control, 744);
505 CHECK_OFFSET(cpu_based_vm_exec_control, 748);
506 CHECK_OFFSET(exception_bitmap, 752);
507 CHECK_OFFSET(page_fault_error_code_mask, 756);
508 CHECK_OFFSET(page_fault_error_code_match, 760);
509 CHECK_OFFSET(cr3_target_count, 764);
510 CHECK_OFFSET(vm_exit_controls, 768);
511 CHECK_OFFSET(vm_exit_msr_store_count, 772);
512 CHECK_OFFSET(vm_exit_msr_load_count, 776);
513 CHECK_OFFSET(vm_entry_controls, 780);
514 CHECK_OFFSET(vm_entry_msr_load_count, 784);
515 CHECK_OFFSET(vm_entry_intr_info_field, 788);
516 CHECK_OFFSET(vm_entry_exception_error_code, 792);
517 CHECK_OFFSET(vm_entry_instruction_len, 796);
518 CHECK_OFFSET(tpr_threshold, 800);
519 CHECK_OFFSET(secondary_vm_exec_control, 804);
520 CHECK_OFFSET(vm_instruction_error, 808);
521 CHECK_OFFSET(vm_exit_reason, 812);
522 CHECK_OFFSET(vm_exit_intr_info, 816);
523 CHECK_OFFSET(vm_exit_intr_error_code, 820);
524 CHECK_OFFSET(idt_vectoring_info_field, 824);
525 CHECK_OFFSET(idt_vectoring_error_code, 828);
526 CHECK_OFFSET(vm_exit_instruction_len, 832);
527 CHECK_OFFSET(vmx_instruction_info, 836);
528 CHECK_OFFSET(guest_es_limit, 840);
529 CHECK_OFFSET(guest_cs_limit, 844);
530 CHECK_OFFSET(guest_ss_limit, 848);
531 CHECK_OFFSET(guest_ds_limit, 852);
532 CHECK_OFFSET(guest_fs_limit, 856);
533 CHECK_OFFSET(guest_gs_limit, 860);
534 CHECK_OFFSET(guest_ldtr_limit, 864);
535 CHECK_OFFSET(guest_tr_limit, 868);
536 CHECK_OFFSET(guest_gdtr_limit, 872);
537 CHECK_OFFSET(guest_idtr_limit, 876);
538 CHECK_OFFSET(guest_es_ar_bytes, 880);
539 CHECK_OFFSET(guest_cs_ar_bytes, 884);
540 CHECK_OFFSET(guest_ss_ar_bytes, 888);
541 CHECK_OFFSET(guest_ds_ar_bytes, 892);
542 CHECK_OFFSET(guest_fs_ar_bytes, 896);
543 CHECK_OFFSET(guest_gs_ar_bytes, 900);
544 CHECK_OFFSET(guest_ldtr_ar_bytes, 904);
545 CHECK_OFFSET(guest_tr_ar_bytes, 908);
546 CHECK_OFFSET(guest_interruptibility_info, 912);
547 CHECK_OFFSET(guest_activity_state, 916);
548 CHECK_OFFSET(guest_sysenter_cs, 920);
549 CHECK_OFFSET(host_ia32_sysenter_cs, 924);
550 CHECK_OFFSET(vmx_preemption_timer_value, 928);
551 CHECK_OFFSET(virtual_processor_id, 960);
552 CHECK_OFFSET(posted_intr_nv, 962);
553 CHECK_OFFSET(guest_es_selector, 964);
554 CHECK_OFFSET(guest_cs_selector, 966);
555 CHECK_OFFSET(guest_ss_selector, 968);
556 CHECK_OFFSET(guest_ds_selector, 970);
557 CHECK_OFFSET(guest_fs_selector, 972);
558 CHECK_OFFSET(guest_gs_selector, 974);
559 CHECK_OFFSET(guest_ldtr_selector, 976);
560 CHECK_OFFSET(guest_tr_selector, 978);
561 CHECK_OFFSET(guest_intr_status, 980);
562 CHECK_OFFSET(host_es_selector, 982);
563 CHECK_OFFSET(host_cs_selector, 984);
564 CHECK_OFFSET(host_ss_selector, 986);
565 CHECK_OFFSET(host_ds_selector, 988);
566 CHECK_OFFSET(host_fs_selector, 990);
567 CHECK_OFFSET(host_gs_selector, 992);
568 CHECK_OFFSET(host_tr_selector, 994);
569 CHECK_OFFSET(guest_pml_index, 996);
573 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
574 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
575 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
577 * IMPORTANT: Changing this value will break save/restore compatibility with
578 * older kvm releases.
580 #define VMCS12_REVISION 0x11e57ed0
583 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
584 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
585 * current implementation, 4K are reserved to avoid future complications.
587 #define VMCS12_SIZE 0x1000
590 * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
591 * supported VMCS12 field encoding.
593 #define VMCS12_MAX_FIELD_INDEX 0x17
595 struct nested_vmx_msrs {
597 * We only store the "true" versions of the VMX capability MSRs. We
598 * generate the "non-true" versions by setting the must-be-1 bits
599 * according to the SDM.
601 u32 procbased_ctls_low;
602 u32 procbased_ctls_high;
603 u32 secondary_ctls_low;
604 u32 secondary_ctls_high;
605 u32 pinbased_ctls_low;
606 u32 pinbased_ctls_high;
625 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
626 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
629 /* Has the level1 guest done vmxon? */
634 /* The guest-physical address of the current VMCS L1 keeps for L2 */
637 * Cache of the guest's VMCS, existing outside of guest memory.
638 * Loaded from guest memory during VMPTRLD. Flushed to guest
639 * memory during VMCLEAR and VMPTRLD.
641 struct vmcs12 *cached_vmcs12;
643 * Indicates if the shadow vmcs must be updated with the
644 * data hold by vmcs12
646 bool sync_shadow_vmcs;
649 bool change_vmcs01_virtual_apic_mode;
651 /* L2 must run next, and mustn't decide to exit to L1. */
652 bool nested_run_pending;
654 struct loaded_vmcs vmcs02;
657 * Guest pages referred to in the vmcs02 with host-physical
658 * pointers, so we must keep them pinned while L2 runs.
660 struct page *apic_access_page;
661 struct page *virtual_apic_page;
662 struct page *pi_desc_page;
663 struct pi_desc *pi_desc;
667 struct hrtimer preemption_timer;
668 bool preemption_timer_expired;
670 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
676 struct nested_vmx_msrs msrs;
678 /* SMM related state */
680 /* in VMX operation on SMM entry? */
682 /* in guest mode on SMM entry? */
687 #define POSTED_INTR_ON 0
688 #define POSTED_INTR_SN 1
690 /* Posted-Interrupt Descriptor */
692 u32 pir[8]; /* Posted interrupt requested */
695 /* bit 256 - Outstanding Notification */
697 /* bit 257 - Suppress Notification */
699 /* bit 271:258 - Reserved */
701 /* bit 279:272 - Notification Vector */
703 /* bit 287:280 - Reserved */
705 /* bit 319:288 - Notification Destination */
713 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
715 return test_and_set_bit(POSTED_INTR_ON,
716 (unsigned long *)&pi_desc->control);
719 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
721 return test_and_clear_bit(POSTED_INTR_ON,
722 (unsigned long *)&pi_desc->control);
725 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
727 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
730 static inline void pi_clear_sn(struct pi_desc *pi_desc)
732 return clear_bit(POSTED_INTR_SN,
733 (unsigned long *)&pi_desc->control);
736 static inline void pi_set_sn(struct pi_desc *pi_desc)
738 return set_bit(POSTED_INTR_SN,
739 (unsigned long *)&pi_desc->control);
742 static inline void pi_clear_on(struct pi_desc *pi_desc)
744 clear_bit(POSTED_INTR_ON,
745 (unsigned long *)&pi_desc->control);
748 static inline int pi_test_on(struct pi_desc *pi_desc)
750 return test_bit(POSTED_INTR_ON,
751 (unsigned long *)&pi_desc->control);
754 static inline int pi_test_sn(struct pi_desc *pi_desc)
756 return test_bit(POSTED_INTR_SN,
757 (unsigned long *)&pi_desc->control);
761 struct kvm_vcpu vcpu;
762 unsigned long host_rsp;
766 u32 idt_vectoring_info;
768 struct shared_msr_entry *guest_msrs;
771 unsigned long host_idt_base;
773 u64 msr_host_kernel_gs_base;
774 u64 msr_guest_kernel_gs_base;
777 u64 arch_capabilities;
780 u32 vm_entry_controls_shadow;
781 u32 vm_exit_controls_shadow;
782 u32 secondary_exec_control;
785 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
786 * non-nested (L1) guest, it always points to vmcs01. For a nested
787 * guest (L2), it points to a different VMCS.
789 struct loaded_vmcs vmcs01;
790 struct loaded_vmcs *loaded_vmcs;
791 bool __launched; /* temporary, used in vmx_vcpu_run */
792 struct msr_autoload {
794 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
795 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
799 u16 fs_sel, gs_sel, ldt_sel;
803 int gs_ldt_reload_needed;
804 int fs_reload_needed;
805 u64 msr_host_bndcfgs;
810 struct kvm_segment segs[8];
813 u32 bitmask; /* 4 bits per segment (1 bit per field) */
814 struct kvm_save_segment {
822 bool emulation_required;
826 /* Posted interrupt descriptor */
827 struct pi_desc pi_desc;
829 /* Support for a guest hypervisor (nested VMX) */
830 struct nested_vmx nested;
832 /* Dynamic PLE window. */
834 bool ple_window_dirty;
836 /* Support for PML */
837 #define PML_ENTITY_NUM 512
840 /* apic deadline value in host tsc */
843 u64 current_tsc_ratio;
847 unsigned long host_debugctlmsr;
850 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
851 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
852 * in msr_ia32_feature_control_valid_bits.
854 u64 msr_ia32_feature_control;
855 u64 msr_ia32_feature_control_valid_bits;
858 enum segment_cache_field {
867 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
869 return container_of(kvm, struct kvm_vmx, kvm);
872 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
874 return container_of(vcpu, struct vcpu_vmx, vcpu);
877 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
879 return &(to_vmx(vcpu)->pi_desc);
882 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
883 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
884 #define FIELD(number, name) [ROL16(number, 6)] = VMCS12_OFFSET(name)
885 #define FIELD64(number, name) \
886 FIELD(number, name), \
887 [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
890 static u16 shadow_read_only_fields[] = {
891 #define SHADOW_FIELD_RO(x) x,
892 #include "vmx_shadow_fields.h"
894 static int max_shadow_read_only_fields =
895 ARRAY_SIZE(shadow_read_only_fields);
897 static u16 shadow_read_write_fields[] = {
898 #define SHADOW_FIELD_RW(x) x,
899 #include "vmx_shadow_fields.h"
901 static int max_shadow_read_write_fields =
902 ARRAY_SIZE(shadow_read_write_fields);
904 static const unsigned short vmcs_field_to_offset_table[] = {
905 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
906 FIELD(POSTED_INTR_NV, posted_intr_nv),
907 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
908 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
909 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
910 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
911 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
912 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
913 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
914 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
915 FIELD(GUEST_INTR_STATUS, guest_intr_status),
916 FIELD(GUEST_PML_INDEX, guest_pml_index),
917 FIELD(HOST_ES_SELECTOR, host_es_selector),
918 FIELD(HOST_CS_SELECTOR, host_cs_selector),
919 FIELD(HOST_SS_SELECTOR, host_ss_selector),
920 FIELD(HOST_DS_SELECTOR, host_ds_selector),
921 FIELD(HOST_FS_SELECTOR, host_fs_selector),
922 FIELD(HOST_GS_SELECTOR, host_gs_selector),
923 FIELD(HOST_TR_SELECTOR, host_tr_selector),
924 FIELD64(IO_BITMAP_A, io_bitmap_a),
925 FIELD64(IO_BITMAP_B, io_bitmap_b),
926 FIELD64(MSR_BITMAP, msr_bitmap),
927 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
928 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
929 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
930 FIELD64(PML_ADDRESS, pml_address),
931 FIELD64(TSC_OFFSET, tsc_offset),
932 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
933 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
934 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
935 FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
936 FIELD64(EPT_POINTER, ept_pointer),
937 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
938 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
939 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
940 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
941 FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
942 FIELD64(VMREAD_BITMAP, vmread_bitmap),
943 FIELD64(VMWRITE_BITMAP, vmwrite_bitmap),
944 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
945 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
946 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
947 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
948 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
949 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
950 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
951 FIELD64(GUEST_PDPTR0, guest_pdptr0),
952 FIELD64(GUEST_PDPTR1, guest_pdptr1),
953 FIELD64(GUEST_PDPTR2, guest_pdptr2),
954 FIELD64(GUEST_PDPTR3, guest_pdptr3),
955 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
956 FIELD64(HOST_IA32_PAT, host_ia32_pat),
957 FIELD64(HOST_IA32_EFER, host_ia32_efer),
958 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
959 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
960 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
961 FIELD(EXCEPTION_BITMAP, exception_bitmap),
962 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
963 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
964 FIELD(CR3_TARGET_COUNT, cr3_target_count),
965 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
966 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
967 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
968 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
969 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
970 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
971 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
972 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
973 FIELD(TPR_THRESHOLD, tpr_threshold),
974 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
975 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
976 FIELD(VM_EXIT_REASON, vm_exit_reason),
977 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
978 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
979 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
980 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
981 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
982 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
983 FIELD(GUEST_ES_LIMIT, guest_es_limit),
984 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
985 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
986 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
987 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
988 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
989 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
990 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
991 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
992 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
993 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
994 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
995 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
996 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
997 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
998 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
999 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
1000 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
1001 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
1002 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
1003 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
1004 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
1005 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
1006 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
1007 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
1008 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
1009 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
1010 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
1011 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
1012 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
1013 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
1014 FIELD(EXIT_QUALIFICATION, exit_qualification),
1015 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
1016 FIELD(GUEST_CR0, guest_cr0),
1017 FIELD(GUEST_CR3, guest_cr3),
1018 FIELD(GUEST_CR4, guest_cr4),
1019 FIELD(GUEST_ES_BASE, guest_es_base),
1020 FIELD(GUEST_CS_BASE, guest_cs_base),
1021 FIELD(GUEST_SS_BASE, guest_ss_base),
1022 FIELD(GUEST_DS_BASE, guest_ds_base),
1023 FIELD(GUEST_FS_BASE, guest_fs_base),
1024 FIELD(GUEST_GS_BASE, guest_gs_base),
1025 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
1026 FIELD(GUEST_TR_BASE, guest_tr_base),
1027 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
1028 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
1029 FIELD(GUEST_DR7, guest_dr7),
1030 FIELD(GUEST_RSP, guest_rsp),
1031 FIELD(GUEST_RIP, guest_rip),
1032 FIELD(GUEST_RFLAGS, guest_rflags),
1033 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
1034 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
1035 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
1036 FIELD(HOST_CR0, host_cr0),
1037 FIELD(HOST_CR3, host_cr3),
1038 FIELD(HOST_CR4, host_cr4),
1039 FIELD(HOST_FS_BASE, host_fs_base),
1040 FIELD(HOST_GS_BASE, host_gs_base),
1041 FIELD(HOST_TR_BASE, host_tr_base),
1042 FIELD(HOST_GDTR_BASE, host_gdtr_base),
1043 FIELD(HOST_IDTR_BASE, host_idtr_base),
1044 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
1045 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
1046 FIELD(HOST_RSP, host_rsp),
1047 FIELD(HOST_RIP, host_rip),
1050 static inline short vmcs_field_to_offset(unsigned long field)
1052 const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
1053 unsigned short offset;
1059 index = ROL16(field, 6);
1063 index = array_index_nospec(index, size);
1064 offset = vmcs_field_to_offset_table[index];
1070 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
1072 return to_vmx(vcpu)->nested.cached_vmcs12;
1075 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
1076 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
1077 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
1078 static bool vmx_xsaves_supported(void);
1079 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1080 struct kvm_segment *var, int seg);
1081 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1082 struct kvm_segment *var, int seg);
1083 static bool guest_state_valid(struct kvm_vcpu *vcpu);
1084 static u32 vmx_segment_access_rights(struct kvm_segment *var);
1085 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
1086 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
1087 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
1088 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
1090 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
1091 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
1094 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
1095 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
1097 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1098 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1100 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
1103 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1104 * can find which vCPU should be waken up.
1106 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
1107 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
1115 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
1117 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
1118 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
1120 static bool cpu_has_load_ia32_efer;
1121 static bool cpu_has_load_perf_global_ctrl;
1123 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
1124 static DEFINE_SPINLOCK(vmx_vpid_lock);
1126 static struct vmcs_config {
1131 u32 pin_based_exec_ctrl;
1132 u32 cpu_based_exec_ctrl;
1133 u32 cpu_based_2nd_exec_ctrl;
1136 struct nested_vmx_msrs nested;
1139 static struct vmx_capability {
1144 #define VMX_SEGMENT_FIELD(seg) \
1145 [VCPU_SREG_##seg] = { \
1146 .selector = GUEST_##seg##_SELECTOR, \
1147 .base = GUEST_##seg##_BASE, \
1148 .limit = GUEST_##seg##_LIMIT, \
1149 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1152 static const struct kvm_vmx_segment_field {
1157 } kvm_vmx_segment_fields[] = {
1158 VMX_SEGMENT_FIELD(CS),
1159 VMX_SEGMENT_FIELD(DS),
1160 VMX_SEGMENT_FIELD(ES),
1161 VMX_SEGMENT_FIELD(FS),
1162 VMX_SEGMENT_FIELD(GS),
1163 VMX_SEGMENT_FIELD(SS),
1164 VMX_SEGMENT_FIELD(TR),
1165 VMX_SEGMENT_FIELD(LDTR),
1168 static u64 host_efer;
1170 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1173 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1174 * away by decrementing the array size.
1176 static const u32 vmx_msr_index[] = {
1177 #ifdef CONFIG_X86_64
1178 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1180 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1183 DEFINE_STATIC_KEY_FALSE(enable_evmcs);
1185 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1187 #define KVM_EVMCS_VERSION 1
1189 #if IS_ENABLED(CONFIG_HYPERV)
1190 static bool __read_mostly enlightened_vmcs = true;
1191 module_param(enlightened_vmcs, bool, 0444);
1193 static inline void evmcs_write64(unsigned long field, u64 value)
1196 int offset = get_evmcs_offset(field, &clean_field);
1201 *(u64 *)((char *)current_evmcs + offset) = value;
1203 current_evmcs->hv_clean_fields &= ~clean_field;
1206 static inline void evmcs_write32(unsigned long field, u32 value)
1209 int offset = get_evmcs_offset(field, &clean_field);
1214 *(u32 *)((char *)current_evmcs + offset) = value;
1215 current_evmcs->hv_clean_fields &= ~clean_field;
1218 static inline void evmcs_write16(unsigned long field, u16 value)
1221 int offset = get_evmcs_offset(field, &clean_field);
1226 *(u16 *)((char *)current_evmcs + offset) = value;
1227 current_evmcs->hv_clean_fields &= ~clean_field;
1230 static inline u64 evmcs_read64(unsigned long field)
1232 int offset = get_evmcs_offset(field, NULL);
1237 return *(u64 *)((char *)current_evmcs + offset);
1240 static inline u32 evmcs_read32(unsigned long field)
1242 int offset = get_evmcs_offset(field, NULL);
1247 return *(u32 *)((char *)current_evmcs + offset);
1250 static inline u16 evmcs_read16(unsigned long field)
1252 int offset = get_evmcs_offset(field, NULL);
1257 return *(u16 *)((char *)current_evmcs + offset);
1260 static inline void evmcs_touch_msr_bitmap(void)
1262 if (unlikely(!current_evmcs))
1265 if (current_evmcs->hv_enlightenments_control.msr_bitmap)
1266 current_evmcs->hv_clean_fields &=
1267 ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP;
1270 static void evmcs_load(u64 phys_addr)
1272 struct hv_vp_assist_page *vp_ap =
1273 hv_get_vp_assist_page(smp_processor_id());
1275 vp_ap->current_nested_vmcs = phys_addr;
1276 vp_ap->enlighten_vmentry = 1;
1279 static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
1282 * Enlightened VMCSv1 doesn't support these:
1284 * POSTED_INTR_NV = 0x00000002,
1285 * GUEST_INTR_STATUS = 0x00000810,
1286 * APIC_ACCESS_ADDR = 0x00002014,
1287 * POSTED_INTR_DESC_ADDR = 0x00002016,
1288 * EOI_EXIT_BITMAP0 = 0x0000201c,
1289 * EOI_EXIT_BITMAP1 = 0x0000201e,
1290 * EOI_EXIT_BITMAP2 = 0x00002020,
1291 * EOI_EXIT_BITMAP3 = 0x00002022,
1293 vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
1294 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1295 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1296 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1297 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1298 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1299 ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
1302 * GUEST_PML_INDEX = 0x00000812,
1303 * PML_ADDRESS = 0x0000200e,
1305 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML;
1307 /* VM_FUNCTION_CONTROL = 0x00002018, */
1308 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC;
1311 * EPTP_LIST_ADDRESS = 0x00002024,
1312 * VMREAD_BITMAP = 0x00002026,
1313 * VMWRITE_BITMAP = 0x00002028,
1315 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS;
1318 * TSC_MULTIPLIER = 0x00002032,
1320 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING;
1323 * PLE_GAP = 0x00004020,
1324 * PLE_WINDOW = 0x00004022,
1326 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1329 * VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
1331 vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
1334 * GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
1335 * HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
1337 vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
1338 vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
1341 * Currently unsupported in KVM:
1342 * GUEST_IA32_RTIT_CTL = 0x00002814,
1345 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1346 static inline void evmcs_write64(unsigned long field, u64 value) {}
1347 static inline void evmcs_write32(unsigned long field, u32 value) {}
1348 static inline void evmcs_write16(unsigned long field, u16 value) {}
1349 static inline u64 evmcs_read64(unsigned long field) { return 0; }
1350 static inline u32 evmcs_read32(unsigned long field) { return 0; }
1351 static inline u16 evmcs_read16(unsigned long field) { return 0; }
1352 static inline void evmcs_load(u64 phys_addr) {}
1353 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
1354 static inline void evmcs_touch_msr_bitmap(void) {}
1355 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1357 static inline bool is_exception_n(u32 intr_info, u8 vector)
1359 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1360 INTR_INFO_VALID_MASK)) ==
1361 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1364 static inline bool is_debug(u32 intr_info)
1366 return is_exception_n(intr_info, DB_VECTOR);
1369 static inline bool is_breakpoint(u32 intr_info)
1371 return is_exception_n(intr_info, BP_VECTOR);
1374 static inline bool is_page_fault(u32 intr_info)
1376 return is_exception_n(intr_info, PF_VECTOR);
1379 static inline bool is_no_device(u32 intr_info)
1381 return is_exception_n(intr_info, NM_VECTOR);
1384 static inline bool is_invalid_opcode(u32 intr_info)
1386 return is_exception_n(intr_info, UD_VECTOR);
1389 static inline bool is_gp_fault(u32 intr_info)
1391 return is_exception_n(intr_info, GP_VECTOR);
1394 static inline bool is_external_interrupt(u32 intr_info)
1396 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1397 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1400 static inline bool is_machine_check(u32 intr_info)
1402 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1403 INTR_INFO_VALID_MASK)) ==
1404 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1407 /* Undocumented: icebp/int1 */
1408 static inline bool is_icebp(u32 intr_info)
1410 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1411 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1414 static inline bool cpu_has_vmx_msr_bitmap(void)
1416 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1419 static inline bool cpu_has_vmx_tpr_shadow(void)
1421 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1424 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1426 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1429 static inline bool cpu_has_secondary_exec_ctrls(void)
1431 return vmcs_config.cpu_based_exec_ctrl &
1432 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1435 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1437 return vmcs_config.cpu_based_2nd_exec_ctrl &
1438 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1441 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1443 return vmcs_config.cpu_based_2nd_exec_ctrl &
1444 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1447 static inline bool cpu_has_vmx_apic_register_virt(void)
1449 return vmcs_config.cpu_based_2nd_exec_ctrl &
1450 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1453 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1455 return vmcs_config.cpu_based_2nd_exec_ctrl &
1456 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1460 * Comment's format: document - errata name - stepping - processor name.
1462 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1464 static u32 vmx_preemption_cpu_tfms[] = {
1465 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1467 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1468 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1469 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1471 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1473 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1474 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1476 * 320767.pdf - AAP86 - B1 -
1477 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1480 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1482 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1484 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1486 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1487 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1488 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1492 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1494 u32 eax = cpuid_eax(0x00000001), i;
1496 /* Clear the reserved bits */
1497 eax &= ~(0x3U << 14 | 0xfU << 28);
1498 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1499 if (eax == vmx_preemption_cpu_tfms[i])
1505 static inline bool cpu_has_vmx_preemption_timer(void)
1507 return vmcs_config.pin_based_exec_ctrl &
1508 PIN_BASED_VMX_PREEMPTION_TIMER;
1511 static inline bool cpu_has_vmx_posted_intr(void)
1513 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1514 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1517 static inline bool cpu_has_vmx_apicv(void)
1519 return cpu_has_vmx_apic_register_virt() &&
1520 cpu_has_vmx_virtual_intr_delivery() &&
1521 cpu_has_vmx_posted_intr();
1524 static inline bool cpu_has_vmx_flexpriority(void)
1526 return cpu_has_vmx_tpr_shadow() &&
1527 cpu_has_vmx_virtualize_apic_accesses();
1530 static inline bool cpu_has_vmx_ept_execute_only(void)
1532 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1535 static inline bool cpu_has_vmx_ept_2m_page(void)
1537 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1540 static inline bool cpu_has_vmx_ept_1g_page(void)
1542 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1545 static inline bool cpu_has_vmx_ept_4levels(void)
1547 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1550 static inline bool cpu_has_vmx_ept_mt_wb(void)
1552 return vmx_capability.ept & VMX_EPTP_WB_BIT;
1555 static inline bool cpu_has_vmx_ept_5levels(void)
1557 return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1560 static inline bool cpu_has_vmx_ept_ad_bits(void)
1562 return vmx_capability.ept & VMX_EPT_AD_BIT;
1565 static inline bool cpu_has_vmx_invept_context(void)
1567 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1570 static inline bool cpu_has_vmx_invept_global(void)
1572 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1575 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
1577 return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT;
1580 static inline bool cpu_has_vmx_invvpid_single(void)
1582 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1585 static inline bool cpu_has_vmx_invvpid_global(void)
1587 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1590 static inline bool cpu_has_vmx_invvpid(void)
1592 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1595 static inline bool cpu_has_vmx_ept(void)
1597 return vmcs_config.cpu_based_2nd_exec_ctrl &
1598 SECONDARY_EXEC_ENABLE_EPT;
1601 static inline bool cpu_has_vmx_unrestricted_guest(void)
1603 return vmcs_config.cpu_based_2nd_exec_ctrl &
1604 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1607 static inline bool cpu_has_vmx_ple(void)
1609 return vmcs_config.cpu_based_2nd_exec_ctrl &
1610 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1613 static inline bool cpu_has_vmx_basic_inout(void)
1615 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1618 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1620 return flexpriority_enabled && lapic_in_kernel(vcpu);
1623 static inline bool cpu_has_vmx_vpid(void)
1625 return vmcs_config.cpu_based_2nd_exec_ctrl &
1626 SECONDARY_EXEC_ENABLE_VPID;
1629 static inline bool cpu_has_vmx_rdtscp(void)
1631 return vmcs_config.cpu_based_2nd_exec_ctrl &
1632 SECONDARY_EXEC_RDTSCP;
1635 static inline bool cpu_has_vmx_invpcid(void)
1637 return vmcs_config.cpu_based_2nd_exec_ctrl &
1638 SECONDARY_EXEC_ENABLE_INVPCID;
1641 static inline bool cpu_has_virtual_nmis(void)
1643 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1646 static inline bool cpu_has_vmx_wbinvd_exit(void)
1648 return vmcs_config.cpu_based_2nd_exec_ctrl &
1649 SECONDARY_EXEC_WBINVD_EXITING;
1652 static inline bool cpu_has_vmx_shadow_vmcs(void)
1655 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1656 /* check if the cpu supports writing r/o exit information fields */
1657 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1660 return vmcs_config.cpu_based_2nd_exec_ctrl &
1661 SECONDARY_EXEC_SHADOW_VMCS;
1664 static inline bool cpu_has_vmx_pml(void)
1666 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1669 static inline bool cpu_has_vmx_tsc_scaling(void)
1671 return vmcs_config.cpu_based_2nd_exec_ctrl &
1672 SECONDARY_EXEC_TSC_SCALING;
1675 static inline bool cpu_has_vmx_vmfunc(void)
1677 return vmcs_config.cpu_based_2nd_exec_ctrl &
1678 SECONDARY_EXEC_ENABLE_VMFUNC;
1681 static bool vmx_umip_emulated(void)
1683 return vmcs_config.cpu_based_2nd_exec_ctrl &
1684 SECONDARY_EXEC_DESC;
1687 static inline bool report_flexpriority(void)
1689 return flexpriority_enabled;
1692 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1694 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
1698 * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
1699 * to modify any valid field of the VMCS, or are the VM-exit
1700 * information fields read-only?
1702 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
1704 return to_vmx(vcpu)->nested.msrs.misc_low &
1705 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
1708 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)
1710 return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS;
1713 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu)
1715 return to_vmx(vcpu)->nested.msrs.procbased_ctls_high &
1716 CPU_BASED_MONITOR_TRAP_FLAG;
1719 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1721 return vmcs12->cpu_based_vm_exec_control & bit;
1724 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1726 return (vmcs12->cpu_based_vm_exec_control &
1727 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1728 (vmcs12->secondary_vm_exec_control & bit);
1731 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1733 return vmcs12->pin_based_vm_exec_control &
1734 PIN_BASED_VMX_PREEMPTION_TIMER;
1737 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
1739 return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
1742 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1744 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1747 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1749 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1752 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1754 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1757 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1759 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1762 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1764 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1767 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1769 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1772 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1774 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1777 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1779 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1782 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1784 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1787 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1789 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1792 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1794 return nested_cpu_has_vmfunc(vmcs12) &&
1795 (vmcs12->vm_function_control &
1796 VMX_VMFUNC_EPTP_SWITCHING);
1799 static inline bool is_nmi(u32 intr_info)
1801 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1802 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1805 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1807 unsigned long exit_qualification);
1808 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1809 struct vmcs12 *vmcs12,
1810 u32 reason, unsigned long qualification);
1812 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1816 for (i = 0; i < vmx->nmsrs; ++i)
1817 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1822 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1828 } operand = { vpid, 0, gva };
1830 asm volatile (__ex(ASM_VMX_INVVPID)
1831 /* CF==1 or ZF==1 --> rc = -1 */
1832 "; ja 1f ; ud2 ; 1:"
1833 : : "a"(&operand), "c"(ext) : "cc", "memory");
1836 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1840 } operand = {eptp, gpa};
1842 asm volatile (__ex(ASM_VMX_INVEPT)
1843 /* CF==1 or ZF==1 --> rc = -1 */
1844 "; ja 1f ; ud2 ; 1:\n"
1845 : : "a" (&operand), "c" (ext) : "cc", "memory");
1848 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1852 i = __find_msr_index(vmx, msr);
1854 return &vmx->guest_msrs[i];
1858 static void vmcs_clear(struct vmcs *vmcs)
1860 u64 phys_addr = __pa(vmcs);
1863 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1864 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1867 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1871 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1873 vmcs_clear(loaded_vmcs->vmcs);
1874 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1875 vmcs_clear(loaded_vmcs->shadow_vmcs);
1876 loaded_vmcs->cpu = -1;
1877 loaded_vmcs->launched = 0;
1880 static void vmcs_load(struct vmcs *vmcs)
1882 u64 phys_addr = __pa(vmcs);
1885 if (static_branch_unlikely(&enable_evmcs))
1886 return evmcs_load(phys_addr);
1888 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1889 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1892 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1896 #ifdef CONFIG_KEXEC_CORE
1898 * This bitmap is used to indicate whether the vmclear
1899 * operation is enabled on all cpus. All disabled by
1902 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1904 static inline void crash_enable_local_vmclear(int cpu)
1906 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1909 static inline void crash_disable_local_vmclear(int cpu)
1911 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1914 static inline int crash_local_vmclear_enabled(int cpu)
1916 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1919 static void crash_vmclear_local_loaded_vmcss(void)
1921 int cpu = raw_smp_processor_id();
1922 struct loaded_vmcs *v;
1924 if (!crash_local_vmclear_enabled(cpu))
1927 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1928 loaded_vmcss_on_cpu_link)
1929 vmcs_clear(v->vmcs);
1932 static inline void crash_enable_local_vmclear(int cpu) { }
1933 static inline void crash_disable_local_vmclear(int cpu) { }
1934 #endif /* CONFIG_KEXEC_CORE */
1936 static void __loaded_vmcs_clear(void *arg)
1938 struct loaded_vmcs *loaded_vmcs = arg;
1939 int cpu = raw_smp_processor_id();
1941 if (loaded_vmcs->cpu != cpu)
1942 return; /* vcpu migration can race with cpu offline */
1943 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1944 per_cpu(current_vmcs, cpu) = NULL;
1945 crash_disable_local_vmclear(cpu);
1946 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1949 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1950 * is before setting loaded_vmcs->vcpu to -1 which is done in
1951 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1952 * then adds the vmcs into percpu list before it is deleted.
1956 loaded_vmcs_init(loaded_vmcs);
1957 crash_enable_local_vmclear(cpu);
1960 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1962 int cpu = loaded_vmcs->cpu;
1965 smp_call_function_single(cpu,
1966 __loaded_vmcs_clear, loaded_vmcs, 1);
1969 static inline void vpid_sync_vcpu_single(int vpid)
1974 if (cpu_has_vmx_invvpid_single())
1975 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1978 static inline void vpid_sync_vcpu_global(void)
1980 if (cpu_has_vmx_invvpid_global())
1981 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1984 static inline void vpid_sync_context(int vpid)
1986 if (cpu_has_vmx_invvpid_single())
1987 vpid_sync_vcpu_single(vpid);
1989 vpid_sync_vcpu_global();
1992 static inline void ept_sync_global(void)
1994 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1997 static inline void ept_sync_context(u64 eptp)
1999 if (cpu_has_vmx_invept_context())
2000 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
2005 static __always_inline void vmcs_check16(unsigned long field)
2007 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2008 "16-bit accessor invalid for 64-bit field");
2009 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2010 "16-bit accessor invalid for 64-bit high field");
2011 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2012 "16-bit accessor invalid for 32-bit high field");
2013 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2014 "16-bit accessor invalid for natural width field");
2017 static __always_inline void vmcs_check32(unsigned long field)
2019 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2020 "32-bit accessor invalid for 16-bit field");
2021 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2022 "32-bit accessor invalid for natural width field");
2025 static __always_inline void vmcs_check64(unsigned long field)
2027 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2028 "64-bit accessor invalid for 16-bit field");
2029 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2030 "64-bit accessor invalid for 64-bit high field");
2031 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2032 "64-bit accessor invalid for 32-bit field");
2033 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2034 "64-bit accessor invalid for natural width field");
2037 static __always_inline void vmcs_checkl(unsigned long field)
2039 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2040 "Natural width accessor invalid for 16-bit field");
2041 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2042 "Natural width accessor invalid for 64-bit field");
2043 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2044 "Natural width accessor invalid for 64-bit high field");
2045 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2046 "Natural width accessor invalid for 32-bit field");
2049 static __always_inline unsigned long __vmcs_readl(unsigned long field)
2051 unsigned long value;
2053 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
2054 : "=a"(value) : "d"(field) : "cc");
2058 static __always_inline u16 vmcs_read16(unsigned long field)
2060 vmcs_check16(field);
2061 if (static_branch_unlikely(&enable_evmcs))
2062 return evmcs_read16(field);
2063 return __vmcs_readl(field);
2066 static __always_inline u32 vmcs_read32(unsigned long field)
2068 vmcs_check32(field);
2069 if (static_branch_unlikely(&enable_evmcs))
2070 return evmcs_read32(field);
2071 return __vmcs_readl(field);
2074 static __always_inline u64 vmcs_read64(unsigned long field)
2076 vmcs_check64(field);
2077 if (static_branch_unlikely(&enable_evmcs))
2078 return evmcs_read64(field);
2079 #ifdef CONFIG_X86_64
2080 return __vmcs_readl(field);
2082 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
2086 static __always_inline unsigned long vmcs_readl(unsigned long field)
2089 if (static_branch_unlikely(&enable_evmcs))
2090 return evmcs_read64(field);
2091 return __vmcs_readl(field);
2094 static noinline void vmwrite_error(unsigned long field, unsigned long value)
2096 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
2097 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
2101 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
2105 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
2106 : "=q"(error) : "a"(value), "d"(field) : "cc");
2107 if (unlikely(error))
2108 vmwrite_error(field, value);
2111 static __always_inline void vmcs_write16(unsigned long field, u16 value)
2113 vmcs_check16(field);
2114 if (static_branch_unlikely(&enable_evmcs))
2115 return evmcs_write16(field, value);
2117 __vmcs_writel(field, value);
2120 static __always_inline void vmcs_write32(unsigned long field, u32 value)
2122 vmcs_check32(field);
2123 if (static_branch_unlikely(&enable_evmcs))
2124 return evmcs_write32(field, value);
2126 __vmcs_writel(field, value);
2129 static __always_inline void vmcs_write64(unsigned long field, u64 value)
2131 vmcs_check64(field);
2132 if (static_branch_unlikely(&enable_evmcs))
2133 return evmcs_write64(field, value);
2135 __vmcs_writel(field, value);
2136 #ifndef CONFIG_X86_64
2138 __vmcs_writel(field+1, value >> 32);
2142 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2145 if (static_branch_unlikely(&enable_evmcs))
2146 return evmcs_write64(field, value);
2148 __vmcs_writel(field, value);
2151 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2153 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2154 "vmcs_clear_bits does not support 64-bit fields");
2155 if (static_branch_unlikely(&enable_evmcs))
2156 return evmcs_write32(field, evmcs_read32(field) & ~mask);
2158 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2161 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2163 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2164 "vmcs_set_bits does not support 64-bit fields");
2165 if (static_branch_unlikely(&enable_evmcs))
2166 return evmcs_write32(field, evmcs_read32(field) | mask);
2168 __vmcs_writel(field, __vmcs_readl(field) | mask);
2171 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
2173 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
2176 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
2178 vmcs_write32(VM_ENTRY_CONTROLS, val);
2179 vmx->vm_entry_controls_shadow = val;
2182 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
2184 if (vmx->vm_entry_controls_shadow != val)
2185 vm_entry_controls_init(vmx, val);
2188 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
2190 return vmx->vm_entry_controls_shadow;
2194 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2196 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
2199 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2201 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
2204 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
2206 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
2209 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
2211 vmcs_write32(VM_EXIT_CONTROLS, val);
2212 vmx->vm_exit_controls_shadow = val;
2215 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2217 if (vmx->vm_exit_controls_shadow != val)
2218 vm_exit_controls_init(vmx, val);
2221 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2223 return vmx->vm_exit_controls_shadow;
2227 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2229 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2232 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2234 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2237 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2239 vmx->segment_cache.bitmask = 0;
2242 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2246 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2248 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2249 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2250 vmx->segment_cache.bitmask = 0;
2252 ret = vmx->segment_cache.bitmask & mask;
2253 vmx->segment_cache.bitmask |= mask;
2257 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2259 u16 *p = &vmx->segment_cache.seg[seg].selector;
2261 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2262 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2266 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2268 ulong *p = &vmx->segment_cache.seg[seg].base;
2270 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2271 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2275 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2277 u32 *p = &vmx->segment_cache.seg[seg].limit;
2279 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2280 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2284 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2286 u32 *p = &vmx->segment_cache.seg[seg].ar;
2288 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2289 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2293 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2297 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2298 (1u << DB_VECTOR) | (1u << AC_VECTOR);
2300 * Guest access to VMware backdoor ports could legitimately
2301 * trigger #GP because of TSS I/O permission bitmap.
2302 * We intercept those #GP and allow access to them anyway
2305 if (enable_vmware_backdoor)
2306 eb |= (1u << GP_VECTOR);
2307 if ((vcpu->guest_debug &
2308 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2309 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2310 eb |= 1u << BP_VECTOR;
2311 if (to_vmx(vcpu)->rmode.vm86_active)
2314 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2316 /* When we are running a nested L2 guest and L1 specified for it a
2317 * certain exception bitmap, we must trap the same exceptions and pass
2318 * them to L1. When running L2, we will only handle the exceptions
2319 * specified above if L1 did not want them.
2321 if (is_guest_mode(vcpu))
2322 eb |= get_vmcs12(vcpu)->exception_bitmap;
2324 vmcs_write32(EXCEPTION_BITMAP, eb);
2328 * Check if MSR is intercepted for currently loaded MSR bitmap.
2330 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2332 unsigned long *msr_bitmap;
2333 int f = sizeof(unsigned long);
2335 if (!cpu_has_vmx_msr_bitmap())
2338 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2340 if (msr <= 0x1fff) {
2341 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2342 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2344 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2351 * Check if MSR is intercepted for L01 MSR bitmap.
2353 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2355 unsigned long *msr_bitmap;
2356 int f = sizeof(unsigned long);
2358 if (!cpu_has_vmx_msr_bitmap())
2361 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2363 if (msr <= 0x1fff) {
2364 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2365 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2367 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2373 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2374 unsigned long entry, unsigned long exit)
2376 vm_entry_controls_clearbit(vmx, entry);
2377 vm_exit_controls_clearbit(vmx, exit);
2380 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2383 struct msr_autoload *m = &vmx->msr_autoload;
2387 if (cpu_has_load_ia32_efer) {
2388 clear_atomic_switch_msr_special(vmx,
2389 VM_ENTRY_LOAD_IA32_EFER,
2390 VM_EXIT_LOAD_IA32_EFER);
2394 case MSR_CORE_PERF_GLOBAL_CTRL:
2395 if (cpu_has_load_perf_global_ctrl) {
2396 clear_atomic_switch_msr_special(vmx,
2397 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2398 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2404 for (i = 0; i < m->nr; ++i)
2405 if (m->guest[i].index == msr)
2411 m->guest[i] = m->guest[m->nr];
2412 m->host[i] = m->host[m->nr];
2413 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2414 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2417 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2418 unsigned long entry, unsigned long exit,
2419 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2420 u64 guest_val, u64 host_val)
2422 vmcs_write64(guest_val_vmcs, guest_val);
2423 vmcs_write64(host_val_vmcs, host_val);
2424 vm_entry_controls_setbit(vmx, entry);
2425 vm_exit_controls_setbit(vmx, exit);
2428 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2429 u64 guest_val, u64 host_val)
2432 struct msr_autoload *m = &vmx->msr_autoload;
2436 if (cpu_has_load_ia32_efer) {
2437 add_atomic_switch_msr_special(vmx,
2438 VM_ENTRY_LOAD_IA32_EFER,
2439 VM_EXIT_LOAD_IA32_EFER,
2442 guest_val, host_val);
2446 case MSR_CORE_PERF_GLOBAL_CTRL:
2447 if (cpu_has_load_perf_global_ctrl) {
2448 add_atomic_switch_msr_special(vmx,
2449 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2450 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2451 GUEST_IA32_PERF_GLOBAL_CTRL,
2452 HOST_IA32_PERF_GLOBAL_CTRL,
2453 guest_val, host_val);
2457 case MSR_IA32_PEBS_ENABLE:
2458 /* PEBS needs a quiescent period after being disabled (to write
2459 * a record). Disabling PEBS through VMX MSR swapping doesn't
2460 * provide that period, so a CPU could write host's record into
2463 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2466 for (i = 0; i < m->nr; ++i)
2467 if (m->guest[i].index == msr)
2470 if (i == NR_AUTOLOAD_MSRS) {
2471 printk_once(KERN_WARNING "Not enough msr switch entries. "
2472 "Can't add msr %x\n", msr);
2474 } else if (i == m->nr) {
2476 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2477 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2480 m->guest[i].index = msr;
2481 m->guest[i].value = guest_val;
2482 m->host[i].index = msr;
2483 m->host[i].value = host_val;
2486 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2488 u64 guest_efer = vmx->vcpu.arch.efer;
2489 u64 ignore_bits = 0;
2493 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2494 * host CPUID is more efficient than testing guest CPUID
2495 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2497 if (boot_cpu_has(X86_FEATURE_SMEP))
2498 guest_efer |= EFER_NX;
2499 else if (!(guest_efer & EFER_NX))
2500 ignore_bits |= EFER_NX;
2504 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2506 ignore_bits |= EFER_SCE;
2507 #ifdef CONFIG_X86_64
2508 ignore_bits |= EFER_LMA | EFER_LME;
2509 /* SCE is meaningful only in long mode on Intel */
2510 if (guest_efer & EFER_LMA)
2511 ignore_bits &= ~(u64)EFER_SCE;
2514 clear_atomic_switch_msr(vmx, MSR_EFER);
2517 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2518 * On CPUs that support "load IA32_EFER", always switch EFER
2519 * atomically, since it's faster than switching it manually.
2521 if (cpu_has_load_ia32_efer ||
2522 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2523 if (!(guest_efer & EFER_LMA))
2524 guest_efer &= ~EFER_LME;
2525 if (guest_efer != host_efer)
2526 add_atomic_switch_msr(vmx, MSR_EFER,
2527 guest_efer, host_efer);
2530 guest_efer &= ~ignore_bits;
2531 guest_efer |= host_efer & ignore_bits;
2533 vmx->guest_msrs[efer_offset].data = guest_efer;
2534 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2540 #ifdef CONFIG_X86_32
2542 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2543 * VMCS rather than the segment table. KVM uses this helper to figure
2544 * out the current bases to poke them into the VMCS before entry.
2546 static unsigned long segment_base(u16 selector)
2548 struct desc_struct *table;
2551 if (!(selector & ~SEGMENT_RPL_MASK))
2554 table = get_current_gdt_ro();
2556 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2557 u16 ldt_selector = kvm_read_ldt();
2559 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2562 table = (struct desc_struct *)segment_base(ldt_selector);
2564 v = get_desc_base(&table[selector >> 3]);
2569 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2571 struct vcpu_vmx *vmx = to_vmx(vcpu);
2572 #ifdef CONFIG_X86_64
2573 int cpu = raw_smp_processor_id();
2577 if (vmx->host_state.loaded)
2580 vmx->host_state.loaded = 1;
2582 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2583 * allow segment selectors with cpl > 0 or ti == 1.
2585 vmx->host_state.ldt_sel = kvm_read_ldt();
2586 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2588 #ifdef CONFIG_X86_64
2589 save_fsgs_for_kvm();
2590 vmx->host_state.fs_sel = current->thread.fsindex;
2591 vmx->host_state.gs_sel = current->thread.gsindex;
2593 savesegment(fs, vmx->host_state.fs_sel);
2594 savesegment(gs, vmx->host_state.gs_sel);
2596 if (!(vmx->host_state.fs_sel & 7)) {
2597 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2598 vmx->host_state.fs_reload_needed = 0;
2600 vmcs_write16(HOST_FS_SELECTOR, 0);
2601 vmx->host_state.fs_reload_needed = 1;
2603 if (!(vmx->host_state.gs_sel & 7))
2604 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2606 vmcs_write16(HOST_GS_SELECTOR, 0);
2607 vmx->host_state.gs_ldt_reload_needed = 1;
2610 #ifdef CONFIG_X86_64
2611 savesegment(ds, vmx->host_state.ds_sel);
2612 savesegment(es, vmx->host_state.es_sel);
2614 vmcs_writel(HOST_FS_BASE, current->thread.fsbase);
2615 vmcs_writel(HOST_GS_BASE, cpu_kernelmode_gs_base(cpu));
2617 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
2618 if (is_long_mode(&vmx->vcpu))
2619 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2621 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2622 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2624 if (boot_cpu_has(X86_FEATURE_MPX))
2625 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2626 for (i = 0; i < vmx->save_nmsrs; ++i)
2627 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2628 vmx->guest_msrs[i].data,
2629 vmx->guest_msrs[i].mask);
2632 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2634 if (!vmx->host_state.loaded)
2637 ++vmx->vcpu.stat.host_state_reload;
2638 vmx->host_state.loaded = 0;
2639 #ifdef CONFIG_X86_64
2640 if (is_long_mode(&vmx->vcpu))
2641 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2643 if (vmx->host_state.gs_ldt_reload_needed) {
2644 kvm_load_ldt(vmx->host_state.ldt_sel);
2645 #ifdef CONFIG_X86_64
2646 load_gs_index(vmx->host_state.gs_sel);
2648 loadsegment(gs, vmx->host_state.gs_sel);
2651 if (vmx->host_state.fs_reload_needed)
2652 loadsegment(fs, vmx->host_state.fs_sel);
2653 #ifdef CONFIG_X86_64
2654 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2655 loadsegment(ds, vmx->host_state.ds_sel);
2656 loadsegment(es, vmx->host_state.es_sel);
2659 invalidate_tss_limit();
2660 #ifdef CONFIG_X86_64
2661 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2663 if (vmx->host_state.msr_host_bndcfgs)
2664 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2665 load_fixmap_gdt(raw_smp_processor_id());
2668 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2671 __vmx_load_host_state(vmx);
2675 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2677 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2678 struct pi_desc old, new;
2682 * In case of hot-plug or hot-unplug, we may have to undo
2683 * vmx_vcpu_pi_put even if there is no assigned device. And we
2684 * always keep PI.NDST up to date for simplicity: it makes the
2685 * code easier, and CPU migration is not a fast path.
2687 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2691 * First handle the simple case where no cmpxchg is necessary; just
2692 * allow posting non-urgent interrupts.
2694 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2695 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2696 * expects the VCPU to be on the blocked_vcpu_list that matches
2699 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2701 pi_clear_sn(pi_desc);
2705 /* The full case. */
2707 old.control = new.control = pi_desc->control;
2709 dest = cpu_physical_id(cpu);
2711 if (x2apic_enabled())
2714 new.ndst = (dest << 8) & 0xFF00;
2717 } while (cmpxchg64(&pi_desc->control, old.control,
2718 new.control) != old.control);
2721 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2723 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2724 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2728 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2729 * vcpu mutex is already taken.
2731 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2733 struct vcpu_vmx *vmx = to_vmx(vcpu);
2734 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2736 if (!already_loaded) {
2737 loaded_vmcs_clear(vmx->loaded_vmcs);
2738 local_irq_disable();
2739 crash_disable_local_vmclear(cpu);
2742 * Read loaded_vmcs->cpu should be before fetching
2743 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2744 * See the comments in __loaded_vmcs_clear().
2748 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2749 &per_cpu(loaded_vmcss_on_cpu, cpu));
2750 crash_enable_local_vmclear(cpu);
2754 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2755 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2756 vmcs_load(vmx->loaded_vmcs->vmcs);
2757 indirect_branch_prediction_barrier();
2760 if (!already_loaded) {
2761 void *gdt = get_current_gdt_ro();
2762 unsigned long sysenter_esp;
2764 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2767 * Linux uses per-cpu TSS and GDT, so set these when switching
2768 * processors. See 22.2.4.
2770 vmcs_writel(HOST_TR_BASE,
2771 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2772 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
2775 * VM exits change the host TR limit to 0x67 after a VM
2776 * exit. This is okay, since 0x67 covers everything except
2777 * the IO bitmap and have have code to handle the IO bitmap
2778 * being lost after a VM exit.
2780 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2782 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2783 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2785 vmx->loaded_vmcs->cpu = cpu;
2788 /* Setup TSC multiplier */
2789 if (kvm_has_tsc_control &&
2790 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2791 decache_tsc_multiplier(vmx);
2793 vmx_vcpu_pi_load(vcpu, cpu);
2794 vmx->host_pkru = read_pkru();
2795 vmx->host_debugctlmsr = get_debugctlmsr();
2798 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2800 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2802 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2803 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2804 !kvm_vcpu_apicv_active(vcpu))
2807 /* Set SN when the vCPU is preempted */
2808 if (vcpu->preempted)
2812 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2814 vmx_vcpu_pi_put(vcpu);
2816 __vmx_load_host_state(to_vmx(vcpu));
2819 static bool emulation_required(struct kvm_vcpu *vcpu)
2821 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2824 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2827 * Return the cr0 value that a nested guest would read. This is a combination
2828 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2829 * its hypervisor (cr0_read_shadow).
2831 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2833 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2834 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2836 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2838 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2839 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2842 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2844 unsigned long rflags, save_rflags;
2846 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2847 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2848 rflags = vmcs_readl(GUEST_RFLAGS);
2849 if (to_vmx(vcpu)->rmode.vm86_active) {
2850 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2851 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2852 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2854 to_vmx(vcpu)->rflags = rflags;
2856 return to_vmx(vcpu)->rflags;
2859 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2861 unsigned long old_rflags = vmx_get_rflags(vcpu);
2863 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2864 to_vmx(vcpu)->rflags = rflags;
2865 if (to_vmx(vcpu)->rmode.vm86_active) {
2866 to_vmx(vcpu)->rmode.save_rflags = rflags;
2867 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2869 vmcs_writel(GUEST_RFLAGS, rflags);
2871 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2872 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2875 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2877 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2880 if (interruptibility & GUEST_INTR_STATE_STI)
2881 ret |= KVM_X86_SHADOW_INT_STI;
2882 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2883 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2888 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2890 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2891 u32 interruptibility = interruptibility_old;
2893 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2895 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2896 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2897 else if (mask & KVM_X86_SHADOW_INT_STI)
2898 interruptibility |= GUEST_INTR_STATE_STI;
2900 if ((interruptibility != interruptibility_old))
2901 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2904 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2908 rip = kvm_rip_read(vcpu);
2909 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2910 kvm_rip_write(vcpu, rip);
2912 /* skipping an emulated instruction also counts */
2913 vmx_set_interrupt_shadow(vcpu, 0);
2916 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2917 unsigned long exit_qual)
2919 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2920 unsigned int nr = vcpu->arch.exception.nr;
2921 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2923 if (vcpu->arch.exception.has_error_code) {
2924 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2925 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2928 if (kvm_exception_is_soft(nr))
2929 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2931 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2933 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2934 vmx_get_nmi_mask(vcpu))
2935 intr_info |= INTR_INFO_UNBLOCK_NMI;
2937 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2941 * KVM wants to inject page-faults which it got to the guest. This function
2942 * checks whether in a nested guest, we need to inject them to L1 or L2.
2944 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2946 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2947 unsigned int nr = vcpu->arch.exception.nr;
2949 if (nr == PF_VECTOR) {
2950 if (vcpu->arch.exception.nested_apf) {
2951 *exit_qual = vcpu->arch.apf.nested_apf_token;
2955 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2956 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2957 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2958 * can be written only when inject_pending_event runs. This should be
2959 * conditional on a new capability---if the capability is disabled,
2960 * kvm_multiple_exception would write the ancillary information to
2961 * CR2 or DR6, for backwards ABI-compatibility.
2963 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2964 vcpu->arch.exception.error_code)) {
2965 *exit_qual = vcpu->arch.cr2;
2969 if (vmcs12->exception_bitmap & (1u << nr)) {
2970 if (nr == DB_VECTOR)
2971 *exit_qual = vcpu->arch.dr6;
2981 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
2984 * Ensure that we clear the HLT state in the VMCS. We don't need to
2985 * explicitly skip the instruction because if the HLT state is set,
2986 * then the instruction is already executing and RIP has already been
2989 if (kvm_hlt_in_guest(vcpu->kvm) &&
2990 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
2991 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2994 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2996 struct vcpu_vmx *vmx = to_vmx(vcpu);
2997 unsigned nr = vcpu->arch.exception.nr;
2998 bool has_error_code = vcpu->arch.exception.has_error_code;
2999 u32 error_code = vcpu->arch.exception.error_code;
3000 u32 intr_info = nr | INTR_INFO_VALID_MASK;
3002 if (has_error_code) {
3003 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
3004 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3007 if (vmx->rmode.vm86_active) {
3009 if (kvm_exception_is_soft(nr))
3010 inc_eip = vcpu->arch.event_exit_inst_len;
3011 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
3012 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3016 WARN_ON_ONCE(vmx->emulation_required);
3018 if (kvm_exception_is_soft(nr)) {
3019 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3020 vmx->vcpu.arch.event_exit_inst_len);
3021 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3023 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3025 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
3027 vmx_clear_hlt(vcpu);
3030 static bool vmx_rdtscp_supported(void)
3032 return cpu_has_vmx_rdtscp();
3035 static bool vmx_invpcid_supported(void)
3037 return cpu_has_vmx_invpcid() && enable_ept;
3041 * Swap MSR entry in host/guest MSR entry array.
3043 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
3045 struct shared_msr_entry tmp;
3047 tmp = vmx->guest_msrs[to];
3048 vmx->guest_msrs[to] = vmx->guest_msrs[from];
3049 vmx->guest_msrs[from] = tmp;
3053 * Set up the vmcs to automatically save and restore system
3054 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
3055 * mode, as fiddling with msrs is very expensive.
3057 static void setup_msrs(struct vcpu_vmx *vmx)
3059 int save_nmsrs, index;
3062 #ifdef CONFIG_X86_64
3063 if (is_long_mode(&vmx->vcpu)) {
3064 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
3066 move_msr_up(vmx, index, save_nmsrs++);
3067 index = __find_msr_index(vmx, MSR_LSTAR);
3069 move_msr_up(vmx, index, save_nmsrs++);
3070 index = __find_msr_index(vmx, MSR_CSTAR);
3072 move_msr_up(vmx, index, save_nmsrs++);
3073 index = __find_msr_index(vmx, MSR_TSC_AUX);
3074 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
3075 move_msr_up(vmx, index, save_nmsrs++);
3077 * MSR_STAR is only needed on long mode guests, and only
3078 * if efer.sce is enabled.
3080 index = __find_msr_index(vmx, MSR_STAR);
3081 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
3082 move_msr_up(vmx, index, save_nmsrs++);
3085 index = __find_msr_index(vmx, MSR_EFER);
3086 if (index >= 0 && update_transition_efer(vmx, index))
3087 move_msr_up(vmx, index, save_nmsrs++);
3089 vmx->save_nmsrs = save_nmsrs;
3091 if (cpu_has_vmx_msr_bitmap())
3092 vmx_update_msr_bitmap(&vmx->vcpu);
3095 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
3097 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3099 if (is_guest_mode(vcpu) &&
3100 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
3101 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
3103 return vcpu->arch.tsc_offset;
3107 * writes 'offset' into guest's timestamp counter offset register
3109 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
3111 if (is_guest_mode(vcpu)) {
3113 * We're here if L1 chose not to trap WRMSR to TSC. According
3114 * to the spec, this should set L1's TSC; The offset that L1
3115 * set for L2 remains unchanged, and still needs to be added
3116 * to the newly set TSC to get L2's TSC.
3118 struct vmcs12 *vmcs12;
3119 /* recalculate vmcs02.TSC_OFFSET: */
3120 vmcs12 = get_vmcs12(vcpu);
3121 vmcs_write64(TSC_OFFSET, offset +
3122 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
3123 vmcs12->tsc_offset : 0));
3125 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
3126 vmcs_read64(TSC_OFFSET), offset);
3127 vmcs_write64(TSC_OFFSET, offset);
3132 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
3133 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
3134 * all guests if the "nested" module option is off, and can also be disabled
3135 * for a single guest by disabling its VMX cpuid bit.
3137 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
3139 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
3143 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
3144 * returned for the various VMX controls MSRs when nested VMX is enabled.
3145 * The same values should also be used to verify that vmcs12 control fields are
3146 * valid during nested entry from L1 to L2.
3147 * Each of these control msrs has a low and high 32-bit half: A low bit is on
3148 * if the corresponding bit in the (32-bit) control field *must* be on, and a
3149 * bit in the high half is on if the corresponding bit in the control field
3150 * may be on. See also vmx_control_verify().
3152 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
3155 memset(msrs, 0, sizeof(*msrs));
3160 * Note that as a general rule, the high half of the MSRs (bits in
3161 * the control fields which may be 1) should be initialized by the
3162 * intersection of the underlying hardware's MSR (i.e., features which
3163 * can be supported) and the list of features we want to expose -
3164 * because they are known to be properly supported in our code.
3165 * Also, usually, the low half of the MSRs (bits which must be 1) can
3166 * be set to 0, meaning that L1 may turn off any of these bits. The
3167 * reason is that if one of these bits is necessary, it will appear
3168 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
3169 * fields of vmcs01 and vmcs02, will turn these bits off - and
3170 * nested_vmx_exit_reflected() will not pass related exits to L1.
3171 * These rules have exceptions below.
3174 /* pin-based controls */
3175 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
3176 msrs->pinbased_ctls_low,
3177 msrs->pinbased_ctls_high);
3178 msrs->pinbased_ctls_low |=
3179 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3180 msrs->pinbased_ctls_high &=
3181 PIN_BASED_EXT_INTR_MASK |
3182 PIN_BASED_NMI_EXITING |
3183 PIN_BASED_VIRTUAL_NMIS |
3184 (apicv ? PIN_BASED_POSTED_INTR : 0);
3185 msrs->pinbased_ctls_high |=
3186 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3187 PIN_BASED_VMX_PREEMPTION_TIMER;
3190 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
3191 msrs->exit_ctls_low,
3192 msrs->exit_ctls_high);
3193 msrs->exit_ctls_low =
3194 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3196 msrs->exit_ctls_high &=
3197 #ifdef CONFIG_X86_64
3198 VM_EXIT_HOST_ADDR_SPACE_SIZE |
3200 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
3201 msrs->exit_ctls_high |=
3202 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
3203 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
3204 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
3206 if (kvm_mpx_supported())
3207 msrs->exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
3209 /* We support free control of debug control saving. */
3210 msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
3212 /* entry controls */
3213 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
3214 msrs->entry_ctls_low,
3215 msrs->entry_ctls_high);
3216 msrs->entry_ctls_low =
3217 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3218 msrs->entry_ctls_high &=
3219 #ifdef CONFIG_X86_64
3220 VM_ENTRY_IA32E_MODE |
3222 VM_ENTRY_LOAD_IA32_PAT;
3223 msrs->entry_ctls_high |=
3224 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3225 if (kvm_mpx_supported())
3226 msrs->entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
3228 /* We support free control of debug control loading. */
3229 msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3231 /* cpu-based controls */
3232 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3233 msrs->procbased_ctls_low,
3234 msrs->procbased_ctls_high);
3235 msrs->procbased_ctls_low =
3236 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3237 msrs->procbased_ctls_high &=
3238 CPU_BASED_VIRTUAL_INTR_PENDING |
3239 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3240 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3241 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3242 CPU_BASED_CR3_STORE_EXITING |
3243 #ifdef CONFIG_X86_64
3244 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3246 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3247 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3248 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3249 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3250 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3252 * We can allow some features even when not supported by the
3253 * hardware. For example, L1 can specify an MSR bitmap - and we
3254 * can use it to avoid exits to L1 - even when L0 runs L2
3255 * without MSR bitmaps.
3257 msrs->procbased_ctls_high |=
3258 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3259 CPU_BASED_USE_MSR_BITMAPS;
3261 /* We support free control of CR3 access interception. */
3262 msrs->procbased_ctls_low &=
3263 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3266 * secondary cpu-based controls. Do not include those that
3267 * depend on CPUID bits, they are added later by vmx_cpuid_update.
3269 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3270 msrs->secondary_ctls_low,
3271 msrs->secondary_ctls_high);
3272 msrs->secondary_ctls_low = 0;
3273 msrs->secondary_ctls_high &=
3274 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3275 SECONDARY_EXEC_DESC |
3276 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3277 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3278 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3279 SECONDARY_EXEC_WBINVD_EXITING;
3282 /* nested EPT: emulate EPT also to L1 */
3283 msrs->secondary_ctls_high |=
3284 SECONDARY_EXEC_ENABLE_EPT;
3285 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3286 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3287 if (cpu_has_vmx_ept_execute_only())
3289 VMX_EPT_EXECUTE_ONLY_BIT;
3290 msrs->ept_caps &= vmx_capability.ept;
3291 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3292 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3293 VMX_EPT_1GB_PAGE_BIT;
3294 if (enable_ept_ad_bits) {
3295 msrs->secondary_ctls_high |=
3296 SECONDARY_EXEC_ENABLE_PML;
3297 msrs->ept_caps |= VMX_EPT_AD_BIT;
3301 if (cpu_has_vmx_vmfunc()) {
3302 msrs->secondary_ctls_high |=
3303 SECONDARY_EXEC_ENABLE_VMFUNC;
3305 * Advertise EPTP switching unconditionally
3306 * since we emulate it
3309 msrs->vmfunc_controls =
3310 VMX_VMFUNC_EPTP_SWITCHING;
3314 * Old versions of KVM use the single-context version without
3315 * checking for support, so declare that it is supported even
3316 * though it is treated as global context. The alternative is
3317 * not failing the single-context invvpid, and it is worse.
3320 msrs->secondary_ctls_high |=
3321 SECONDARY_EXEC_ENABLE_VPID;
3322 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
3323 VMX_VPID_EXTENT_SUPPORTED_MASK;
3326 if (enable_unrestricted_guest)
3327 msrs->secondary_ctls_high |=
3328 SECONDARY_EXEC_UNRESTRICTED_GUEST;
3330 /* miscellaneous data */
3331 rdmsr(MSR_IA32_VMX_MISC,
3334 msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
3336 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
3337 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3338 VMX_MISC_ACTIVITY_HLT;
3339 msrs->misc_high = 0;
3342 * This MSR reports some information about VMX support. We
3343 * should return information about the VMX we emulate for the
3344 * guest, and the VMCS structure we give it - not about the
3345 * VMX support of the underlying hardware.
3349 VMX_BASIC_TRUE_CTLS |
3350 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3351 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3353 if (cpu_has_vmx_basic_inout())
3354 msrs->basic |= VMX_BASIC_INOUT;
3357 * These MSRs specify bits which the guest must keep fixed on
3358 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3359 * We picked the standard core2 setting.
3361 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3362 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
3363 msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
3364 msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
3366 /* These MSRs specify bits which the guest must keep fixed off. */
3367 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
3368 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
3370 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3371 msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
3375 * if fixed0[i] == 1: val[i] must be 1
3376 * if fixed1[i] == 0: val[i] must be 0
3378 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3380 return ((val & fixed1) | fixed0) == val;
3383 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3385 return fixed_bits_valid(control, low, high);
3388 static inline u64 vmx_control_msr(u32 low, u32 high)
3390 return low | ((u64)high << 32);
3393 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3398 return (superset | subset) == superset;
3401 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3403 const u64 feature_and_reserved =
3404 /* feature (except bit 48; see below) */
3405 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3407 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3408 u64 vmx_basic = vmx->nested.msrs.basic;
3410 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3414 * KVM does not emulate a version of VMX that constrains physical
3415 * addresses of VMX structures (e.g. VMCS) to 32-bits.
3417 if (data & BIT_ULL(48))
3420 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3421 vmx_basic_vmcs_revision_id(data))
3424 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3427 vmx->nested.msrs.basic = data;
3432 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3437 switch (msr_index) {
3438 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3439 lowp = &vmx->nested.msrs.pinbased_ctls_low;
3440 highp = &vmx->nested.msrs.pinbased_ctls_high;
3442 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3443 lowp = &vmx->nested.msrs.procbased_ctls_low;
3444 highp = &vmx->nested.msrs.procbased_ctls_high;
3446 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3447 lowp = &vmx->nested.msrs.exit_ctls_low;
3448 highp = &vmx->nested.msrs.exit_ctls_high;
3450 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3451 lowp = &vmx->nested.msrs.entry_ctls_low;
3452 highp = &vmx->nested.msrs.entry_ctls_high;
3454 case MSR_IA32_VMX_PROCBASED_CTLS2:
3455 lowp = &vmx->nested.msrs.secondary_ctls_low;
3456 highp = &vmx->nested.msrs.secondary_ctls_high;
3462 supported = vmx_control_msr(*lowp, *highp);
3464 /* Check must-be-1 bits are still 1. */
3465 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3468 /* Check must-be-0 bits are still 0. */
3469 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3473 *highp = data >> 32;
3477 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3479 const u64 feature_and_reserved_bits =
3481 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3482 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3484 GENMASK_ULL(13, 9) | BIT_ULL(31);
3487 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
3488 vmx->nested.msrs.misc_high);
3490 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3493 if ((vmx->nested.msrs.pinbased_ctls_high &
3494 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3495 vmx_misc_preemption_timer_rate(data) !=
3496 vmx_misc_preemption_timer_rate(vmx_misc))
3499 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3502 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3505 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3508 vmx->nested.msrs.misc_low = data;
3509 vmx->nested.msrs.misc_high = data >> 32;
3512 * If L1 has read-only VM-exit information fields, use the
3513 * less permissive vmx_vmwrite_bitmap to specify write
3514 * permissions for the shadow VMCS.
3516 if (enable_shadow_vmcs && !nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
3517 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
3522 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3524 u64 vmx_ept_vpid_cap;
3526 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
3527 vmx->nested.msrs.vpid_caps);
3529 /* Every bit is either reserved or a feature bit. */
3530 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3533 vmx->nested.msrs.ept_caps = data;
3534 vmx->nested.msrs.vpid_caps = data >> 32;
3538 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3542 switch (msr_index) {
3543 case MSR_IA32_VMX_CR0_FIXED0:
3544 msr = &vmx->nested.msrs.cr0_fixed0;
3546 case MSR_IA32_VMX_CR4_FIXED0:
3547 msr = &vmx->nested.msrs.cr4_fixed0;
3554 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3555 * must be 1 in the restored value.
3557 if (!is_bitwise_subset(data, *msr, -1ULL))
3565 * Called when userspace is restoring VMX MSRs.
3567 * Returns 0 on success, non-0 otherwise.
3569 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3571 struct vcpu_vmx *vmx = to_vmx(vcpu);
3574 * Don't allow changes to the VMX capability MSRs while the vCPU
3575 * is in VMX operation.
3577 if (vmx->nested.vmxon)
3580 switch (msr_index) {
3581 case MSR_IA32_VMX_BASIC:
3582 return vmx_restore_vmx_basic(vmx, data);
3583 case MSR_IA32_VMX_PINBASED_CTLS:
3584 case MSR_IA32_VMX_PROCBASED_CTLS:
3585 case MSR_IA32_VMX_EXIT_CTLS:
3586 case MSR_IA32_VMX_ENTRY_CTLS:
3588 * The "non-true" VMX capability MSRs are generated from the
3589 * "true" MSRs, so we do not support restoring them directly.
3591 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3592 * should restore the "true" MSRs with the must-be-1 bits
3593 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3594 * DEFAULT SETTINGS".
3597 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3598 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3599 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3600 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3601 case MSR_IA32_VMX_PROCBASED_CTLS2:
3602 return vmx_restore_control_msr(vmx, msr_index, data);
3603 case MSR_IA32_VMX_MISC:
3604 return vmx_restore_vmx_misc(vmx, data);
3605 case MSR_IA32_VMX_CR0_FIXED0:
3606 case MSR_IA32_VMX_CR4_FIXED0:
3607 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3608 case MSR_IA32_VMX_CR0_FIXED1:
3609 case MSR_IA32_VMX_CR4_FIXED1:
3611 * These MSRs are generated based on the vCPU's CPUID, so we
3612 * do not support restoring them directly.
3615 case MSR_IA32_VMX_EPT_VPID_CAP:
3616 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3617 case MSR_IA32_VMX_VMCS_ENUM:
3618 vmx->nested.msrs.vmcs_enum = data;
3622 * The rest of the VMX capability MSRs do not support restore.
3628 /* Returns 0 on success, non-0 otherwise. */
3629 static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
3631 switch (msr_index) {
3632 case MSR_IA32_VMX_BASIC:
3633 *pdata = msrs->basic;
3635 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3636 case MSR_IA32_VMX_PINBASED_CTLS:
3637 *pdata = vmx_control_msr(
3638 msrs->pinbased_ctls_low,
3639 msrs->pinbased_ctls_high);
3640 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3641 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3643 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3644 case MSR_IA32_VMX_PROCBASED_CTLS:
3645 *pdata = vmx_control_msr(
3646 msrs->procbased_ctls_low,
3647 msrs->procbased_ctls_high);
3648 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3649 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3651 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3652 case MSR_IA32_VMX_EXIT_CTLS:
3653 *pdata = vmx_control_msr(
3654 msrs->exit_ctls_low,
3655 msrs->exit_ctls_high);
3656 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3657 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3659 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3660 case MSR_IA32_VMX_ENTRY_CTLS:
3661 *pdata = vmx_control_msr(
3662 msrs->entry_ctls_low,
3663 msrs->entry_ctls_high);
3664 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3665 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3667 case MSR_IA32_VMX_MISC:
3668 *pdata = vmx_control_msr(
3672 case MSR_IA32_VMX_CR0_FIXED0:
3673 *pdata = msrs->cr0_fixed0;
3675 case MSR_IA32_VMX_CR0_FIXED1:
3676 *pdata = msrs->cr0_fixed1;
3678 case MSR_IA32_VMX_CR4_FIXED0:
3679 *pdata = msrs->cr4_fixed0;
3681 case MSR_IA32_VMX_CR4_FIXED1:
3682 *pdata = msrs->cr4_fixed1;
3684 case MSR_IA32_VMX_VMCS_ENUM:
3685 *pdata = msrs->vmcs_enum;
3687 case MSR_IA32_VMX_PROCBASED_CTLS2:
3688 *pdata = vmx_control_msr(
3689 msrs->secondary_ctls_low,
3690 msrs->secondary_ctls_high);
3692 case MSR_IA32_VMX_EPT_VPID_CAP:
3693 *pdata = msrs->ept_caps |
3694 ((u64)msrs->vpid_caps << 32);
3696 case MSR_IA32_VMX_VMFUNC:
3697 *pdata = msrs->vmfunc_controls;
3706 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3709 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3711 return !(val & ~valid_bits);
3714 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
3716 switch (msr->index) {
3717 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3720 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
3729 * Reads an msr value (of 'msr_index') into 'pdata'.
3730 * Returns 0 on success, non-0 otherwise.
3731 * Assumes vcpu_load() was already called.
3733 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3735 struct vcpu_vmx *vmx = to_vmx(vcpu);
3736 struct shared_msr_entry *msr;
3738 switch (msr_info->index) {
3739 #ifdef CONFIG_X86_64
3741 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3744 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3746 case MSR_KERNEL_GS_BASE:
3747 vmx_load_host_state(vmx);
3748 msr_info->data = vmx->msr_guest_kernel_gs_base;
3752 return kvm_get_msr_common(vcpu, msr_info);
3753 case MSR_IA32_SPEC_CTRL:
3754 if (!msr_info->host_initiated &&
3755 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3758 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3760 case MSR_IA32_ARCH_CAPABILITIES:
3761 if (!msr_info->host_initiated &&
3762 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3764 msr_info->data = to_vmx(vcpu)->arch_capabilities;
3766 case MSR_IA32_SYSENTER_CS:
3767 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3769 case MSR_IA32_SYSENTER_EIP:
3770 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3772 case MSR_IA32_SYSENTER_ESP:
3773 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3775 case MSR_IA32_BNDCFGS:
3776 if (!kvm_mpx_supported() ||
3777 (!msr_info->host_initiated &&
3778 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3780 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3782 case MSR_IA32_MCG_EXT_CTL:
3783 if (!msr_info->host_initiated &&
3784 !(vmx->msr_ia32_feature_control &
3785 FEATURE_CONTROL_LMCE))
3787 msr_info->data = vcpu->arch.mcg_ext_ctl;
3789 case MSR_IA32_FEATURE_CONTROL:
3790 msr_info->data = vmx->msr_ia32_feature_control;
3792 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3793 if (!nested_vmx_allowed(vcpu))
3795 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
3798 if (!vmx_xsaves_supported())
3800 msr_info->data = vcpu->arch.ia32_xss;
3803 if (!msr_info->host_initiated &&
3804 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3806 /* Otherwise falls through */
3808 msr = find_msr_entry(vmx, msr_info->index);
3810 msr_info->data = msr->data;
3813 return kvm_get_msr_common(vcpu, msr_info);
3819 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3822 * Writes msr value into into the appropriate "register".
3823 * Returns 0 on success, non-0 otherwise.
3824 * Assumes vcpu_load() was already called.
3826 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3828 struct vcpu_vmx *vmx = to_vmx(vcpu);
3829 struct shared_msr_entry *msr;
3831 u32 msr_index = msr_info->index;
3832 u64 data = msr_info->data;
3834 switch (msr_index) {
3836 ret = kvm_set_msr_common(vcpu, msr_info);
3838 #ifdef CONFIG_X86_64
3840 vmx_segment_cache_clear(vmx);
3841 vmcs_writel(GUEST_FS_BASE, data);
3844 vmx_segment_cache_clear(vmx);
3845 vmcs_writel(GUEST_GS_BASE, data);
3847 case MSR_KERNEL_GS_BASE:
3848 vmx_load_host_state(vmx);
3849 vmx->msr_guest_kernel_gs_base = data;
3852 case MSR_IA32_SYSENTER_CS:
3853 vmcs_write32(GUEST_SYSENTER_CS, data);
3855 case MSR_IA32_SYSENTER_EIP:
3856 vmcs_writel(GUEST_SYSENTER_EIP, data);
3858 case MSR_IA32_SYSENTER_ESP:
3859 vmcs_writel(GUEST_SYSENTER_ESP, data);
3861 case MSR_IA32_BNDCFGS:
3862 if (!kvm_mpx_supported() ||
3863 (!msr_info->host_initiated &&
3864 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3866 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3867 (data & MSR_IA32_BNDCFGS_RSVD))
3869 vmcs_write64(GUEST_BNDCFGS, data);
3871 case MSR_IA32_SPEC_CTRL:
3872 if (!msr_info->host_initiated &&
3873 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3876 /* The STIBP bit doesn't fault even if it's not advertised */
3877 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
3880 vmx->spec_ctrl = data;
3887 * When it's written (to non-zero) for the first time, pass
3891 * The handling of the MSR bitmap for L2 guests is done in
3892 * nested_vmx_merge_msr_bitmap. We should not touch the
3893 * vmcs02.msr_bitmap here since it gets completely overwritten
3894 * in the merging. We update the vmcs01 here for L1 as well
3895 * since it will end up touching the MSR anyway now.
3897 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3901 case MSR_IA32_PRED_CMD:
3902 if (!msr_info->host_initiated &&
3903 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3906 if (data & ~PRED_CMD_IBPB)
3912 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3916 * When it's written (to non-zero) for the first time, pass
3920 * The handling of the MSR bitmap for L2 guests is done in
3921 * nested_vmx_merge_msr_bitmap. We should not touch the
3922 * vmcs02.msr_bitmap here since it gets completely overwritten
3925 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3928 case MSR_IA32_ARCH_CAPABILITIES:
3929 if (!msr_info->host_initiated)
3931 vmx->arch_capabilities = data;
3933 case MSR_IA32_CR_PAT:
3934 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3935 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3937 vmcs_write64(GUEST_IA32_PAT, data);
3938 vcpu->arch.pat = data;
3941 ret = kvm_set_msr_common(vcpu, msr_info);
3943 case MSR_IA32_TSC_ADJUST:
3944 ret = kvm_set_msr_common(vcpu, msr_info);
3946 case MSR_IA32_MCG_EXT_CTL:
3947 if ((!msr_info->host_initiated &&
3948 !(to_vmx(vcpu)->msr_ia32_feature_control &
3949 FEATURE_CONTROL_LMCE)) ||
3950 (data & ~MCG_EXT_CTL_LMCE_EN))
3952 vcpu->arch.mcg_ext_ctl = data;
3954 case MSR_IA32_FEATURE_CONTROL:
3955 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3956 (to_vmx(vcpu)->msr_ia32_feature_control &
3957 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3959 vmx->msr_ia32_feature_control = data;
3960 if (msr_info->host_initiated && data == 0)
3961 vmx_leave_nested(vcpu);
3963 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3964 if (!msr_info->host_initiated)
3965 return 1; /* they are read-only */
3966 if (!nested_vmx_allowed(vcpu))
3968 return vmx_set_vmx_msr(vcpu, msr_index, data);
3970 if (!vmx_xsaves_supported())
3973 * The only supported bit as of Skylake is bit 8, but
3974 * it is not supported on KVM.
3978 vcpu->arch.ia32_xss = data;
3979 if (vcpu->arch.ia32_xss != host_xss)
3980 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3981 vcpu->arch.ia32_xss, host_xss);
3983 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3986 if (!msr_info->host_initiated &&
3987 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3989 /* Check reserved bit, higher 32 bits should be zero */
3990 if ((data >> 32) != 0)
3992 /* Otherwise falls through */
3994 msr = find_msr_entry(vmx, msr_index);
3996 u64 old_msr_data = msr->data;
3998 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
4000 ret = kvm_set_shared_msr(msr->index, msr->data,
4004 msr->data = old_msr_data;
4008 ret = kvm_set_msr_common(vcpu, msr_info);
4014 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
4016 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
4019 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
4022 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
4024 case VCPU_EXREG_PDPTR:
4026 ept_save_pdptrs(vcpu);
4033 static __init int cpu_has_kvm_support(void)
4035 return cpu_has_vmx();
4038 static __init int vmx_disabled_by_bios(void)
4042 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
4043 if (msr & FEATURE_CONTROL_LOCKED) {
4044 /* launched w/ TXT and VMX disabled */
4045 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4048 /* launched w/o TXT and VMX only enabled w/ TXT */
4049 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4050 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4051 && !tboot_enabled()) {
4052 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
4053 "activate TXT before enabling KVM\n");
4056 /* launched w/o TXT and VMX disabled */
4057 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4058 && !tboot_enabled())
4065 static void kvm_cpu_vmxon(u64 addr)
4067 cr4_set_bits(X86_CR4_VMXE);
4068 intel_pt_handle_vmx(1);
4070 asm volatile (ASM_VMX_VMXON_RAX
4071 : : "a"(&addr), "m"(addr)
4075 static int hardware_enable(void)
4077 int cpu = raw_smp_processor_id();
4078 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
4081 if (cr4_read_shadow() & X86_CR4_VMXE)
4085 * This can happen if we hot-added a CPU but failed to allocate
4086 * VP assist page for it.
4088 if (static_branch_unlikely(&enable_evmcs) &&
4089 !hv_get_vp_assist_page(cpu))
4092 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
4093 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
4094 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
4097 * Now we can enable the vmclear operation in kdump
4098 * since the loaded_vmcss_on_cpu list on this cpu
4099 * has been initialized.
4101 * Though the cpu is not in VMX operation now, there
4102 * is no problem to enable the vmclear operation
4103 * for the loaded_vmcss_on_cpu list is empty!
4105 crash_enable_local_vmclear(cpu);
4107 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
4109 test_bits = FEATURE_CONTROL_LOCKED;
4110 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4111 if (tboot_enabled())
4112 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
4114 if ((old & test_bits) != test_bits) {
4115 /* enable and lock */
4116 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
4118 kvm_cpu_vmxon(phys_addr);
4125 static void vmclear_local_loaded_vmcss(void)
4127 int cpu = raw_smp_processor_id();
4128 struct loaded_vmcs *v, *n;
4130 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
4131 loaded_vmcss_on_cpu_link)
4132 __loaded_vmcs_clear(v);
4136 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
4139 static void kvm_cpu_vmxoff(void)
4141 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
4143 intel_pt_handle_vmx(0);
4144 cr4_clear_bits(X86_CR4_VMXE);
4147 static void hardware_disable(void)
4149 vmclear_local_loaded_vmcss();
4153 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
4154 u32 msr, u32 *result)
4156 u32 vmx_msr_low, vmx_msr_high;
4157 u32 ctl = ctl_min | ctl_opt;
4159 rdmsr(msr, vmx_msr_low, vmx_msr_high);
4161 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
4162 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
4164 /* Ensure minimum (required) set of control bits are supported. */
4172 static __init bool allow_1_setting(u32 msr, u32 ctl)
4174 u32 vmx_msr_low, vmx_msr_high;
4176 rdmsr(msr, vmx_msr_low, vmx_msr_high);
4177 return vmx_msr_high & ctl;
4180 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
4182 u32 vmx_msr_low, vmx_msr_high;
4183 u32 min, opt, min2, opt2;
4184 u32 _pin_based_exec_control = 0;
4185 u32 _cpu_based_exec_control = 0;
4186 u32 _cpu_based_2nd_exec_control = 0;
4187 u32 _vmexit_control = 0;
4188 u32 _vmentry_control = 0;
4190 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
4191 min = CPU_BASED_HLT_EXITING |
4192 #ifdef CONFIG_X86_64
4193 CPU_BASED_CR8_LOAD_EXITING |
4194 CPU_BASED_CR8_STORE_EXITING |
4196 CPU_BASED_CR3_LOAD_EXITING |
4197 CPU_BASED_CR3_STORE_EXITING |
4198 CPU_BASED_UNCOND_IO_EXITING |
4199 CPU_BASED_MOV_DR_EXITING |
4200 CPU_BASED_USE_TSC_OFFSETING |
4201 CPU_BASED_MWAIT_EXITING |
4202 CPU_BASED_MONITOR_EXITING |
4203 CPU_BASED_INVLPG_EXITING |
4204 CPU_BASED_RDPMC_EXITING;
4206 opt = CPU_BASED_TPR_SHADOW |
4207 CPU_BASED_USE_MSR_BITMAPS |
4208 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
4209 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
4210 &_cpu_based_exec_control) < 0)
4212 #ifdef CONFIG_X86_64
4213 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4214 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
4215 ~CPU_BASED_CR8_STORE_EXITING;
4217 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
4219 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4220 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4221 SECONDARY_EXEC_WBINVD_EXITING |
4222 SECONDARY_EXEC_ENABLE_VPID |
4223 SECONDARY_EXEC_ENABLE_EPT |
4224 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4225 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
4226 SECONDARY_EXEC_DESC |
4227 SECONDARY_EXEC_RDTSCP |
4228 SECONDARY_EXEC_ENABLE_INVPCID |
4229 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4230 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4231 SECONDARY_EXEC_SHADOW_VMCS |
4232 SECONDARY_EXEC_XSAVES |
4233 SECONDARY_EXEC_RDSEED_EXITING |
4234 SECONDARY_EXEC_RDRAND_EXITING |
4235 SECONDARY_EXEC_ENABLE_PML |
4236 SECONDARY_EXEC_TSC_SCALING |
4237 SECONDARY_EXEC_ENABLE_VMFUNC;
4238 if (adjust_vmx_controls(min2, opt2,
4239 MSR_IA32_VMX_PROCBASED_CTLS2,
4240 &_cpu_based_2nd_exec_control) < 0)
4243 #ifndef CONFIG_X86_64
4244 if (!(_cpu_based_2nd_exec_control &
4245 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
4246 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
4249 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4250 _cpu_based_2nd_exec_control &= ~(
4251 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4252 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4253 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4255 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
4256 &vmx_capability.ept, &vmx_capability.vpid);
4258 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
4259 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4261 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
4262 CPU_BASED_CR3_STORE_EXITING |
4263 CPU_BASED_INVLPG_EXITING);
4264 } else if (vmx_capability.ept) {
4265 vmx_capability.ept = 0;
4266 pr_warn_once("EPT CAP should not exist if not support "
4267 "1-setting enable EPT VM-execution control\n");
4269 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
4270 vmx_capability.vpid) {
4271 vmx_capability.vpid = 0;
4272 pr_warn_once("VPID CAP should not exist if not support "
4273 "1-setting enable VPID VM-execution control\n");
4276 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4277 #ifdef CONFIG_X86_64
4278 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4280 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4281 VM_EXIT_CLEAR_BNDCFGS;
4282 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4283 &_vmexit_control) < 0)
4286 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4287 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4288 PIN_BASED_VMX_PREEMPTION_TIMER;
4289 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4290 &_pin_based_exec_control) < 0)
4293 if (cpu_has_broken_vmx_preemption_timer())
4294 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4295 if (!(_cpu_based_2nd_exec_control &
4296 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4297 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4299 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4300 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4301 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4302 &_vmentry_control) < 0)
4305 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4307 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4308 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4311 #ifdef CONFIG_X86_64
4312 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4313 if (vmx_msr_high & (1u<<16))
4317 /* Require Write-Back (WB) memory type for VMCS accesses. */
4318 if (((vmx_msr_high >> 18) & 15) != 6)
4321 vmcs_conf->size = vmx_msr_high & 0x1fff;
4322 vmcs_conf->order = get_order(vmcs_conf->size);
4323 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4325 /* KVM supports Enlightened VMCS v1 only */
4326 if (static_branch_unlikely(&enable_evmcs))
4327 vmcs_conf->revision_id = KVM_EVMCS_VERSION;
4329 vmcs_conf->revision_id = vmx_msr_low;
4331 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4332 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4333 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4334 vmcs_conf->vmexit_ctrl = _vmexit_control;
4335 vmcs_conf->vmentry_ctrl = _vmentry_control;
4337 if (static_branch_unlikely(&enable_evmcs))
4338 evmcs_sanitize_exec_ctrls(vmcs_conf);
4340 cpu_has_load_ia32_efer =
4341 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4342 VM_ENTRY_LOAD_IA32_EFER)
4343 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4344 VM_EXIT_LOAD_IA32_EFER);
4346 cpu_has_load_perf_global_ctrl =
4347 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4348 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4349 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4350 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4353 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4354 * but due to errata below it can't be used. Workaround is to use
4355 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4357 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4362 * BC86,AAY89,BD102 (model 44)
4366 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4367 switch (boot_cpu_data.x86_model) {
4373 cpu_has_load_perf_global_ctrl = false;
4374 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4375 "does not work properly. Using workaround\n");
4382 if (boot_cpu_has(X86_FEATURE_XSAVES))
4383 rdmsrl(MSR_IA32_XSS, host_xss);
4388 static struct vmcs *alloc_vmcs_cpu(int cpu)
4390 int node = cpu_to_node(cpu);
4394 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4397 vmcs = page_address(pages);
4398 memset(vmcs, 0, vmcs_config.size);
4399 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
4403 static void free_vmcs(struct vmcs *vmcs)
4405 free_pages((unsigned long)vmcs, vmcs_config.order);
4409 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4411 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4413 if (!loaded_vmcs->vmcs)
4415 loaded_vmcs_clear(loaded_vmcs);
4416 free_vmcs(loaded_vmcs->vmcs);
4417 loaded_vmcs->vmcs = NULL;
4418 if (loaded_vmcs->msr_bitmap)
4419 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4420 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4423 static struct vmcs *alloc_vmcs(void)
4425 return alloc_vmcs_cpu(raw_smp_processor_id());
4428 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4430 loaded_vmcs->vmcs = alloc_vmcs();
4431 if (!loaded_vmcs->vmcs)
4434 loaded_vmcs->shadow_vmcs = NULL;
4435 loaded_vmcs_init(loaded_vmcs);
4437 if (cpu_has_vmx_msr_bitmap()) {
4438 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4439 if (!loaded_vmcs->msr_bitmap)
4441 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4443 if (IS_ENABLED(CONFIG_HYPERV) &&
4444 static_branch_unlikely(&enable_evmcs) &&
4445 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
4446 struct hv_enlightened_vmcs *evmcs =
4447 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
4449 evmcs->hv_enlightenments_control.msr_bitmap = 1;
4455 free_loaded_vmcs(loaded_vmcs);
4459 static void free_kvm_area(void)
4463 for_each_possible_cpu(cpu) {
4464 free_vmcs(per_cpu(vmxarea, cpu));
4465 per_cpu(vmxarea, cpu) = NULL;
4469 enum vmcs_field_width {
4470 VMCS_FIELD_WIDTH_U16 = 0,
4471 VMCS_FIELD_WIDTH_U64 = 1,
4472 VMCS_FIELD_WIDTH_U32 = 2,
4473 VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
4476 static inline int vmcs_field_width(unsigned long field)
4478 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
4479 return VMCS_FIELD_WIDTH_U32;
4480 return (field >> 13) & 0x3 ;
4483 static inline int vmcs_field_readonly(unsigned long field)
4485 return (((field >> 10) & 0x3) == 1);
4488 static void init_vmcs_shadow_fields(void)
4492 for (i = j = 0; i < max_shadow_read_only_fields; i++) {
4493 u16 field = shadow_read_only_fields[i];
4494 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4495 (i + 1 == max_shadow_read_only_fields ||
4496 shadow_read_only_fields[i + 1] != field + 1))
4497 pr_err("Missing field from shadow_read_only_field %x\n",
4500 clear_bit(field, vmx_vmread_bitmap);
4501 #ifdef CONFIG_X86_64
4506 shadow_read_only_fields[j] = field;
4509 max_shadow_read_only_fields = j;
4511 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4512 u16 field = shadow_read_write_fields[i];
4513 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4514 (i + 1 == max_shadow_read_write_fields ||
4515 shadow_read_write_fields[i + 1] != field + 1))
4516 pr_err("Missing field from shadow_read_write_field %x\n",
4520 * PML and the preemption timer can be emulated, but the
4521 * processor cannot vmwrite to fields that don't exist
4525 case GUEST_PML_INDEX:
4526 if (!cpu_has_vmx_pml())
4529 case VMX_PREEMPTION_TIMER_VALUE:
4530 if (!cpu_has_vmx_preemption_timer())
4533 case GUEST_INTR_STATUS:
4534 if (!cpu_has_vmx_apicv())
4541 clear_bit(field, vmx_vmwrite_bitmap);
4542 clear_bit(field, vmx_vmread_bitmap);
4543 #ifdef CONFIG_X86_64
4548 shadow_read_write_fields[j] = field;
4551 max_shadow_read_write_fields = j;
4554 static __init int alloc_kvm_area(void)
4558 for_each_possible_cpu(cpu) {
4561 vmcs = alloc_vmcs_cpu(cpu);
4567 per_cpu(vmxarea, cpu) = vmcs;
4572 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4573 struct kvm_segment *save)
4575 if (!emulate_invalid_guest_state) {
4577 * CS and SS RPL should be equal during guest entry according
4578 * to VMX spec, but in reality it is not always so. Since vcpu
4579 * is in the middle of the transition from real mode to
4580 * protected mode it is safe to assume that RPL 0 is a good
4583 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4584 save->selector &= ~SEGMENT_RPL_MASK;
4585 save->dpl = save->selector & SEGMENT_RPL_MASK;
4588 vmx_set_segment(vcpu, save, seg);
4591 static void enter_pmode(struct kvm_vcpu *vcpu)
4593 unsigned long flags;
4594 struct vcpu_vmx *vmx = to_vmx(vcpu);
4597 * Update real mode segment cache. It may be not up-to-date if sement
4598 * register was written while vcpu was in a guest mode.
4600 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4601 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4602 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4603 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4604 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4605 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4607 vmx->rmode.vm86_active = 0;
4609 vmx_segment_cache_clear(vmx);
4611 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4613 flags = vmcs_readl(GUEST_RFLAGS);
4614 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4615 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4616 vmcs_writel(GUEST_RFLAGS, flags);
4618 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4619 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4621 update_exception_bitmap(vcpu);
4623 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4624 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4625 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4626 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4627 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4628 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4631 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4633 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4634 struct kvm_segment var = *save;
4637 if (seg == VCPU_SREG_CS)
4640 if (!emulate_invalid_guest_state) {
4641 var.selector = var.base >> 4;
4642 var.base = var.base & 0xffff0;
4652 if (save->base & 0xf)
4653 printk_once(KERN_WARNING "kvm: segment base is not "
4654 "paragraph aligned when entering "
4655 "protected mode (seg=%d)", seg);
4658 vmcs_write16(sf->selector, var.selector);
4659 vmcs_writel(sf->base, var.base);
4660 vmcs_write32(sf->limit, var.limit);
4661 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4664 static void enter_rmode(struct kvm_vcpu *vcpu)
4666 unsigned long flags;
4667 struct vcpu_vmx *vmx = to_vmx(vcpu);
4668 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
4670 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4671 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4672 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4673 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4674 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4675 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4676 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4678 vmx->rmode.vm86_active = 1;
4681 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4682 * vcpu. Warn the user that an update is overdue.
4684 if (!kvm_vmx->tss_addr)
4685 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4686 "called before entering vcpu\n");
4688 vmx_segment_cache_clear(vmx);
4690 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
4691 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4692 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4694 flags = vmcs_readl(GUEST_RFLAGS);
4695 vmx->rmode.save_rflags = flags;
4697 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4699 vmcs_writel(GUEST_RFLAGS, flags);
4700 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4701 update_exception_bitmap(vcpu);
4703 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4704 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4705 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4706 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4707 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4708 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4710 kvm_mmu_reset_context(vcpu);
4713 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4715 struct vcpu_vmx *vmx = to_vmx(vcpu);
4716 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4722 * Force kernel_gs_base reloading before EFER changes, as control
4723 * of this msr depends on is_long_mode().
4725 vmx_load_host_state(to_vmx(vcpu));
4726 vcpu->arch.efer = efer;
4727 if (efer & EFER_LMA) {
4728 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4731 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4733 msr->data = efer & ~EFER_LME;
4738 #ifdef CONFIG_X86_64
4740 static void enter_lmode(struct kvm_vcpu *vcpu)
4744 vmx_segment_cache_clear(to_vmx(vcpu));
4746 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4747 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4748 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4750 vmcs_write32(GUEST_TR_AR_BYTES,
4751 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4752 | VMX_AR_TYPE_BUSY_64_TSS);
4754 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4757 static void exit_lmode(struct kvm_vcpu *vcpu)
4759 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4760 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4765 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
4766 bool invalidate_gpa)
4768 if (enable_ept && (invalidate_gpa || !enable_vpid)) {
4769 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4771 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4773 vpid_sync_context(vpid);
4777 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
4779 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
4782 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4784 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4786 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4787 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4790 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4792 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
4793 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4794 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4797 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4799 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4801 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4802 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4805 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4807 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4809 if (!test_bit(VCPU_EXREG_PDPTR,
4810 (unsigned long *)&vcpu->arch.regs_dirty))
4813 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4814 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4815 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4816 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4817 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4821 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4823 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4825 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4826 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4827 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4828 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4829 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4832 __set_bit(VCPU_EXREG_PDPTR,
4833 (unsigned long *)&vcpu->arch.regs_avail);
4834 __set_bit(VCPU_EXREG_PDPTR,
4835 (unsigned long *)&vcpu->arch.regs_dirty);
4838 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4840 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4841 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4842 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4844 if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
4845 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4846 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4847 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4849 return fixed_bits_valid(val, fixed0, fixed1);
4852 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4854 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4855 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4857 return fixed_bits_valid(val, fixed0, fixed1);
4860 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4862 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
4863 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
4865 return fixed_bits_valid(val, fixed0, fixed1);
4868 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4869 #define nested_guest_cr4_valid nested_cr4_valid
4870 #define nested_host_cr4_valid nested_cr4_valid
4872 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4874 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4876 struct kvm_vcpu *vcpu)
4878 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4879 vmx_decache_cr3(vcpu);
4880 if (!(cr0 & X86_CR0_PG)) {
4881 /* From paging/starting to nonpaging */
4882 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4883 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4884 (CPU_BASED_CR3_LOAD_EXITING |
4885 CPU_BASED_CR3_STORE_EXITING));
4886 vcpu->arch.cr0 = cr0;
4887 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4888 } else if (!is_paging(vcpu)) {
4889 /* From nonpaging to paging */
4890 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4891 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4892 ~(CPU_BASED_CR3_LOAD_EXITING |
4893 CPU_BASED_CR3_STORE_EXITING));
4894 vcpu->arch.cr0 = cr0;
4895 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4898 if (!(cr0 & X86_CR0_WP))
4899 *hw_cr0 &= ~X86_CR0_WP;
4902 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4904 struct vcpu_vmx *vmx = to_vmx(vcpu);
4905 unsigned long hw_cr0;
4907 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4908 if (enable_unrestricted_guest)
4909 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4911 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4913 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4916 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4920 #ifdef CONFIG_X86_64
4921 if (vcpu->arch.efer & EFER_LME) {
4922 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4924 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4929 if (enable_ept && !enable_unrestricted_guest)
4930 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4932 vmcs_writel(CR0_READ_SHADOW, cr0);
4933 vmcs_writel(GUEST_CR0, hw_cr0);
4934 vcpu->arch.cr0 = cr0;
4936 /* depends on vcpu->arch.cr0 to be set to a new value */
4937 vmx->emulation_required = emulation_required(vcpu);
4940 static int get_ept_level(struct kvm_vcpu *vcpu)
4942 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4947 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4949 u64 eptp = VMX_EPTP_MT_WB;
4951 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4953 if (enable_ept_ad_bits &&
4954 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4955 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4956 eptp |= (root_hpa & PAGE_MASK);
4961 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4963 unsigned long guest_cr3;
4968 eptp = construct_eptp(vcpu, cr3);
4969 vmcs_write64(EPT_POINTER, eptp);
4970 if (enable_unrestricted_guest || is_paging(vcpu) ||
4971 is_guest_mode(vcpu))
4972 guest_cr3 = kvm_read_cr3(vcpu);
4974 guest_cr3 = to_kvm_vmx(vcpu->kvm)->ept_identity_map_addr;
4975 ept_load_pdptrs(vcpu);
4978 vmx_flush_tlb(vcpu, true);
4979 vmcs_writel(GUEST_CR3, guest_cr3);
4982 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4985 * Pass through host's Machine Check Enable value to hw_cr4, which
4986 * is in force while we are in guest mode. Do not let guests control
4987 * this bit, even if host CR4.MCE == 0.
4989 unsigned long hw_cr4;
4991 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
4992 if (enable_unrestricted_guest)
4993 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
4994 else if (to_vmx(vcpu)->rmode.vm86_active)
4995 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
4997 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
4999 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
5000 if (cr4 & X86_CR4_UMIP) {
5001 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5002 SECONDARY_EXEC_DESC);
5003 hw_cr4 &= ~X86_CR4_UMIP;
5004 } else if (!is_guest_mode(vcpu) ||
5005 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
5006 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5007 SECONDARY_EXEC_DESC);
5010 if (cr4 & X86_CR4_VMXE) {
5012 * To use VMXON (and later other VMX instructions), a guest
5013 * must first be able to turn on cr4.VMXE (see handle_vmon()).
5014 * So basically the check on whether to allow nested VMX
5017 if (!nested_vmx_allowed(vcpu))
5021 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5024 vcpu->arch.cr4 = cr4;
5026 if (!enable_unrestricted_guest) {
5028 if (!is_paging(vcpu)) {
5029 hw_cr4 &= ~X86_CR4_PAE;
5030 hw_cr4 |= X86_CR4_PSE;
5031 } else if (!(cr4 & X86_CR4_PAE)) {
5032 hw_cr4 &= ~X86_CR4_PAE;
5037 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
5038 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
5039 * to be manually disabled when guest switches to non-paging
5042 * If !enable_unrestricted_guest, the CPU is always running
5043 * with CR0.PG=1 and CR4 needs to be modified.
5044 * If enable_unrestricted_guest, the CPU automatically
5045 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
5047 if (!is_paging(vcpu))
5048 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
5051 vmcs_writel(CR4_READ_SHADOW, cr4);
5052 vmcs_writel(GUEST_CR4, hw_cr4);
5056 static void vmx_get_segment(struct kvm_vcpu *vcpu,
5057 struct kvm_segment *var, int seg)
5059 struct vcpu_vmx *vmx = to_vmx(vcpu);
5062 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5063 *var = vmx->rmode.segs[seg];
5064 if (seg == VCPU_SREG_TR
5065 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
5067 var->base = vmx_read_guest_seg_base(vmx, seg);
5068 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5071 var->base = vmx_read_guest_seg_base(vmx, seg);
5072 var->limit = vmx_read_guest_seg_limit(vmx, seg);
5073 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5074 ar = vmx_read_guest_seg_ar(vmx, seg);
5075 var->unusable = (ar >> 16) & 1;
5076 var->type = ar & 15;
5077 var->s = (ar >> 4) & 1;
5078 var->dpl = (ar >> 5) & 3;
5080 * Some userspaces do not preserve unusable property. Since usable
5081 * segment has to be present according to VMX spec we can use present
5082 * property to amend userspace bug by making unusable segment always
5083 * nonpresent. vmx_segment_access_rights() already marks nonpresent
5084 * segment as unusable.
5086 var->present = !var->unusable;
5087 var->avl = (ar >> 12) & 1;
5088 var->l = (ar >> 13) & 1;
5089 var->db = (ar >> 14) & 1;
5090 var->g = (ar >> 15) & 1;
5093 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
5095 struct kvm_segment s;
5097 if (to_vmx(vcpu)->rmode.vm86_active) {
5098 vmx_get_segment(vcpu, &s, seg);
5101 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
5104 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
5106 struct vcpu_vmx *vmx = to_vmx(vcpu);
5108 if (unlikely(vmx->rmode.vm86_active))
5111 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
5112 return VMX_AR_DPL(ar);
5116 static u32 vmx_segment_access_rights(struct kvm_segment *var)
5120 if (var->unusable || !var->present)
5123 ar = var->type & 15;
5124 ar |= (var->s & 1) << 4;
5125 ar |= (var->dpl & 3) << 5;
5126 ar |= (var->present & 1) << 7;
5127 ar |= (var->avl & 1) << 12;
5128 ar |= (var->l & 1) << 13;
5129 ar |= (var->db & 1) << 14;
5130 ar |= (var->g & 1) << 15;
5136 static void vmx_set_segment(struct kvm_vcpu *vcpu,
5137 struct kvm_segment *var, int seg)
5139 struct vcpu_vmx *vmx = to_vmx(vcpu);
5140 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5142 vmx_segment_cache_clear(vmx);
5144 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5145 vmx->rmode.segs[seg] = *var;
5146 if (seg == VCPU_SREG_TR)
5147 vmcs_write16(sf->selector, var->selector);
5149 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
5153 vmcs_writel(sf->base, var->base);
5154 vmcs_write32(sf->limit, var->limit);
5155 vmcs_write16(sf->selector, var->selector);
5158 * Fix the "Accessed" bit in AR field of segment registers for older
5160 * IA32 arch specifies that at the time of processor reset the
5161 * "Accessed" bit in the AR field of segment registers is 1. And qemu
5162 * is setting it to 0 in the userland code. This causes invalid guest
5163 * state vmexit when "unrestricted guest" mode is turned on.
5164 * Fix for this setup issue in cpu_reset is being pushed in the qemu
5165 * tree. Newer qemu binaries with that qemu fix would not need this
5168 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
5169 var->type |= 0x1; /* Accessed */
5171 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
5174 vmx->emulation_required = emulation_required(vcpu);
5177 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5179 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
5181 *db = (ar >> 14) & 1;
5182 *l = (ar >> 13) & 1;
5185 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5187 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
5188 dt->address = vmcs_readl(GUEST_IDTR_BASE);
5191 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5193 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
5194 vmcs_writel(GUEST_IDTR_BASE, dt->address);
5197 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5199 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
5200 dt->address = vmcs_readl(GUEST_GDTR_BASE);
5203 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5205 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
5206 vmcs_writel(GUEST_GDTR_BASE, dt->address);
5209 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
5211 struct kvm_segment var;
5214 vmx_get_segment(vcpu, &var, seg);
5216 if (seg == VCPU_SREG_CS)
5218 ar = vmx_segment_access_rights(&var);
5220 if (var.base != (var.selector << 4))
5222 if (var.limit != 0xffff)
5230 static bool code_segment_valid(struct kvm_vcpu *vcpu)
5232 struct kvm_segment cs;
5233 unsigned int cs_rpl;
5235 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5236 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
5240 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
5244 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
5245 if (cs.dpl > cs_rpl)
5248 if (cs.dpl != cs_rpl)
5254 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5258 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
5260 struct kvm_segment ss;
5261 unsigned int ss_rpl;
5263 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5264 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
5268 if (ss.type != 3 && ss.type != 7)
5272 if (ss.dpl != ss_rpl) /* DPL != RPL */
5280 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
5282 struct kvm_segment var;
5285 vmx_get_segment(vcpu, &var, seg);
5286 rpl = var.selector & SEGMENT_RPL_MASK;
5294 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
5295 if (var.dpl < rpl) /* DPL < RPL */
5299 /* TODO: Add other members to kvm_segment_field to allow checking for other access
5305 static bool tr_valid(struct kvm_vcpu *vcpu)
5307 struct kvm_segment tr;
5309 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
5313 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
5315 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
5323 static bool ldtr_valid(struct kvm_vcpu *vcpu)
5325 struct kvm_segment ldtr;
5327 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
5331 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
5341 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5343 struct kvm_segment cs, ss;
5345 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5346 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5348 return ((cs.selector & SEGMENT_RPL_MASK) ==
5349 (ss.selector & SEGMENT_RPL_MASK));
5353 * Check if guest state is valid. Returns true if valid, false if
5355 * We assume that registers are always usable
5357 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5359 if (enable_unrestricted_guest)
5362 /* real mode guest state checks */
5363 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5364 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5366 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5368 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5370 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5372 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5374 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5377 /* protected mode guest state checks */
5378 if (!cs_ss_rpl_check(vcpu))
5380 if (!code_segment_valid(vcpu))
5382 if (!stack_segment_valid(vcpu))
5384 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5386 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5388 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5390 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5392 if (!tr_valid(vcpu))
5394 if (!ldtr_valid(vcpu))
5398 * - Add checks on RIP
5399 * - Add checks on RFLAGS
5405 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5407 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5410 static int init_rmode_tss(struct kvm *kvm)
5416 idx = srcu_read_lock(&kvm->srcu);
5417 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
5418 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5421 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5422 r = kvm_write_guest_page(kvm, fn++, &data,
5423 TSS_IOPB_BASE_OFFSET, sizeof(u16));
5426 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5429 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5433 r = kvm_write_guest_page(kvm, fn, &data,
5434 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5437 srcu_read_unlock(&kvm->srcu, idx);
5441 static int init_rmode_identity_map(struct kvm *kvm)
5443 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
5445 kvm_pfn_t identity_map_pfn;
5448 /* Protect kvm_vmx->ept_identity_pagetable_done. */
5449 mutex_lock(&kvm->slots_lock);
5451 if (likely(kvm_vmx->ept_identity_pagetable_done))
5454 if (!kvm_vmx->ept_identity_map_addr)
5455 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5456 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
5458 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5459 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
5463 idx = srcu_read_lock(&kvm->srcu);
5464 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5467 /* Set up identity-mapping pagetable for EPT in real mode */
5468 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5469 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5470 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5471 r = kvm_write_guest_page(kvm, identity_map_pfn,
5472 &tmp, i * sizeof(tmp), sizeof(tmp));
5476 kvm_vmx->ept_identity_pagetable_done = true;
5479 srcu_read_unlock(&kvm->srcu, idx);
5482 mutex_unlock(&kvm->slots_lock);
5486 static void seg_setup(int seg)
5488 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5491 vmcs_write16(sf->selector, 0);
5492 vmcs_writel(sf->base, 0);
5493 vmcs_write32(sf->limit, 0xffff);
5495 if (seg == VCPU_SREG_CS)
5496 ar |= 0x08; /* code segment */
5498 vmcs_write32(sf->ar_bytes, ar);
5501 static int alloc_apic_access_page(struct kvm *kvm)
5506 mutex_lock(&kvm->slots_lock);
5507 if (kvm->arch.apic_access_page_done)
5509 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5510 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5514 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5515 if (is_error_page(page)) {
5521 * Do not pin the page in memory, so that memory hot-unplug
5522 * is able to migrate it.
5525 kvm->arch.apic_access_page_done = true;
5527 mutex_unlock(&kvm->slots_lock);
5531 static int allocate_vpid(void)
5537 spin_lock(&vmx_vpid_lock);
5538 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5539 if (vpid < VMX_NR_VPIDS)
5540 __set_bit(vpid, vmx_vpid_bitmap);
5543 spin_unlock(&vmx_vpid_lock);
5547 static void free_vpid(int vpid)
5549 if (!enable_vpid || vpid == 0)
5551 spin_lock(&vmx_vpid_lock);
5552 __clear_bit(vpid, vmx_vpid_bitmap);
5553 spin_unlock(&vmx_vpid_lock);
5556 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5559 int f = sizeof(unsigned long);
5561 if (!cpu_has_vmx_msr_bitmap())
5564 if (static_branch_unlikely(&enable_evmcs))
5565 evmcs_touch_msr_bitmap();
5568 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5569 * have the write-low and read-high bitmap offsets the wrong way round.
5570 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5572 if (msr <= 0x1fff) {
5573 if (type & MSR_TYPE_R)
5575 __clear_bit(msr, msr_bitmap + 0x000 / f);
5577 if (type & MSR_TYPE_W)
5579 __clear_bit(msr, msr_bitmap + 0x800 / f);
5581 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5583 if (type & MSR_TYPE_R)
5585 __clear_bit(msr, msr_bitmap + 0x400 / f);
5587 if (type & MSR_TYPE_W)
5589 __clear_bit(msr, msr_bitmap + 0xc00 / f);
5594 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5597 int f = sizeof(unsigned long);
5599 if (!cpu_has_vmx_msr_bitmap())
5602 if (static_branch_unlikely(&enable_evmcs))
5603 evmcs_touch_msr_bitmap();
5606 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5607 * have the write-low and read-high bitmap offsets the wrong way round.
5608 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5610 if (msr <= 0x1fff) {
5611 if (type & MSR_TYPE_R)
5613 __set_bit(msr, msr_bitmap + 0x000 / f);
5615 if (type & MSR_TYPE_W)
5617 __set_bit(msr, msr_bitmap + 0x800 / f);
5619 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5621 if (type & MSR_TYPE_R)
5623 __set_bit(msr, msr_bitmap + 0x400 / f);
5625 if (type & MSR_TYPE_W)
5627 __set_bit(msr, msr_bitmap + 0xc00 / f);
5632 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5633 u32 msr, int type, bool value)
5636 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
5638 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
5642 * If a msr is allowed by L0, we should check whether it is allowed by L1.
5643 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5645 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
5646 unsigned long *msr_bitmap_nested,
5649 int f = sizeof(unsigned long);
5652 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5653 * have the write-low and read-high bitmap offsets the wrong way round.
5654 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5656 if (msr <= 0x1fff) {
5657 if (type & MSR_TYPE_R &&
5658 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
5660 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
5662 if (type & MSR_TYPE_W &&
5663 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
5665 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
5667 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5669 if (type & MSR_TYPE_R &&
5670 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
5672 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
5674 if (type & MSR_TYPE_W &&
5675 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
5677 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
5682 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5686 if (cpu_has_secondary_exec_ctrls() &&
5687 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5688 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5689 mode |= MSR_BITMAP_MODE_X2APIC;
5690 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5691 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5694 if (is_long_mode(vcpu))
5695 mode |= MSR_BITMAP_MODE_LM;
5700 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5702 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5707 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5708 unsigned word = msr / BITS_PER_LONG;
5709 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5710 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5713 if (mode & MSR_BITMAP_MODE_X2APIC) {
5715 * TPR reads and writes can be virtualized even if virtual interrupt
5716 * delivery is not in use.
5718 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5719 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5720 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5721 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5722 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5727 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
5729 struct vcpu_vmx *vmx = to_vmx(vcpu);
5730 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5731 u8 mode = vmx_msr_bitmap_mode(vcpu);
5732 u8 changed = mode ^ vmx->msr_bitmap_mode;
5737 vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5738 !(mode & MSR_BITMAP_MODE_LM));
5740 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5741 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5743 vmx->msr_bitmap_mode = mode;
5746 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5748 return enable_apicv;
5751 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5753 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5757 * Don't need to mark the APIC access page dirty; it is never
5758 * written to by the CPU during APIC virtualization.
5761 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5762 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5763 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5766 if (nested_cpu_has_posted_intr(vmcs12)) {
5767 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5768 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5773 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5775 struct vcpu_vmx *vmx = to_vmx(vcpu);
5780 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5783 vmx->nested.pi_pending = false;
5784 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5787 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5788 if (max_irr != 256) {
5789 vapic_page = kmap(vmx->nested.virtual_apic_page);
5790 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
5791 vapic_page, &max_irr);
5792 kunmap(vmx->nested.virtual_apic_page);
5794 status = vmcs_read16(GUEST_INTR_STATUS);
5795 if ((u8)max_irr > ((u8)status & 0xff)) {
5797 status |= (u8)max_irr;
5798 vmcs_write16(GUEST_INTR_STATUS, status);
5802 nested_mark_vmcs12_pages_dirty(vcpu);
5805 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5809 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5811 if (vcpu->mode == IN_GUEST_MODE) {
5813 * The vector of interrupt to be delivered to vcpu had
5814 * been set in PIR before this function.
5816 * Following cases will be reached in this block, and
5817 * we always send a notification event in all cases as
5820 * Case 1: vcpu keeps in non-root mode. Sending a
5821 * notification event posts the interrupt to vcpu.
5823 * Case 2: vcpu exits to root mode and is still
5824 * runnable. PIR will be synced to vIRR before the
5825 * next vcpu entry. Sending a notification event in
5826 * this case has no effect, as vcpu is not in root
5829 * Case 3: vcpu exits to root mode and is blocked.
5830 * vcpu_block() has already synced PIR to vIRR and
5831 * never blocks vcpu if vIRR is not cleared. Therefore,
5832 * a blocked vcpu here does not wait for any requested
5833 * interrupts in PIR, and sending a notification event
5834 * which has no effect is safe here.
5837 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5844 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5847 struct vcpu_vmx *vmx = to_vmx(vcpu);
5849 if (is_guest_mode(vcpu) &&
5850 vector == vmx->nested.posted_intr_nv) {
5852 * If a posted intr is not recognized by hardware,
5853 * we will accomplish it in the next vmentry.
5855 vmx->nested.pi_pending = true;
5856 kvm_make_request(KVM_REQ_EVENT, vcpu);
5857 /* the PIR and ON have been set by L1. */
5858 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
5859 kvm_vcpu_kick(vcpu);
5865 * Send interrupt to vcpu via posted interrupt way.
5866 * 1. If target vcpu is running(non-root mode), send posted interrupt
5867 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5868 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5869 * interrupt from PIR in next vmentry.
5871 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5873 struct vcpu_vmx *vmx = to_vmx(vcpu);
5876 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5880 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5883 /* If a previous notification has sent the IPI, nothing to do. */
5884 if (pi_test_and_set_on(&vmx->pi_desc))
5887 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5888 kvm_vcpu_kick(vcpu);
5892 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5893 * will not change in the lifetime of the guest.
5894 * Note that host-state that does change is set elsewhere. E.g., host-state
5895 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5897 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5902 unsigned long cr0, cr3, cr4;
5905 WARN_ON(cr0 & X86_CR0_TS);
5906 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
5909 * Save the most likely value for this task's CR3 in the VMCS.
5910 * We can't use __get_current_cr3_fast() because we're not atomic.
5913 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5914 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5916 /* Save the most likely value for this task's CR4 in the VMCS. */
5917 cr4 = cr4_read_shadow();
5918 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5919 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5921 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
5922 #ifdef CONFIG_X86_64
5924 * Load null selectors, so we can avoid reloading them in
5925 * __vmx_load_host_state(), in case userspace uses the null selectors
5926 * too (the expected case).
5928 vmcs_write16(HOST_DS_SELECTOR, 0);
5929 vmcs_write16(HOST_ES_SELECTOR, 0);
5931 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5932 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5934 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5935 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5938 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
5939 vmx->host_idt_base = dt.address;
5941 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5943 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5944 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5945 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5946 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5948 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5949 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5950 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5954 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5956 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5958 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5959 if (is_guest_mode(&vmx->vcpu))
5960 vmx->vcpu.arch.cr4_guest_owned_bits &=
5961 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5962 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5965 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5967 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5969 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5970 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5973 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
5975 /* Enable the preemption timer dynamically */
5976 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5977 return pin_based_exec_ctrl;
5980 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5982 struct vcpu_vmx *vmx = to_vmx(vcpu);
5984 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5985 if (cpu_has_secondary_exec_ctrls()) {
5986 if (kvm_vcpu_apicv_active(vcpu))
5987 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5988 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5989 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5991 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5992 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5993 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5996 if (cpu_has_vmx_msr_bitmap())
5997 vmx_update_msr_bitmap(vcpu);
6000 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
6002 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
6004 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
6005 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
6007 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
6008 exec_control &= ~CPU_BASED_TPR_SHADOW;
6009 #ifdef CONFIG_X86_64
6010 exec_control |= CPU_BASED_CR8_STORE_EXITING |
6011 CPU_BASED_CR8_LOAD_EXITING;
6015 exec_control |= CPU_BASED_CR3_STORE_EXITING |
6016 CPU_BASED_CR3_LOAD_EXITING |
6017 CPU_BASED_INVLPG_EXITING;
6018 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
6019 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
6020 CPU_BASED_MONITOR_EXITING);
6021 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
6022 exec_control &= ~CPU_BASED_HLT_EXITING;
6023 return exec_control;
6026 static bool vmx_rdrand_supported(void)
6028 return vmcs_config.cpu_based_2nd_exec_ctrl &
6029 SECONDARY_EXEC_RDRAND_EXITING;
6032 static bool vmx_rdseed_supported(void)
6034 return vmcs_config.cpu_based_2nd_exec_ctrl &
6035 SECONDARY_EXEC_RDSEED_EXITING;
6038 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
6040 struct kvm_vcpu *vcpu = &vmx->vcpu;
6042 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
6044 if (!cpu_need_virtualize_apic_accesses(vcpu))
6045 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6047 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
6049 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
6050 enable_unrestricted_guest = 0;
6051 /* Enable INVPCID for non-ept guests may cause performance regression. */
6052 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6054 if (!enable_unrestricted_guest)
6055 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
6056 if (kvm_pause_in_guest(vmx->vcpu.kvm))
6057 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
6058 if (!kvm_vcpu_apicv_active(vcpu))
6059 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
6060 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6061 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6063 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
6064 * in vmx_set_cr4. */
6065 exec_control &= ~SECONDARY_EXEC_DESC;
6067 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
6069 We can NOT enable shadow_vmcs here because we don't have yet
6072 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6075 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
6077 if (vmx_xsaves_supported()) {
6078 /* Exposing XSAVES only when XSAVE is exposed */
6079 bool xsaves_enabled =
6080 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
6081 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
6083 if (!xsaves_enabled)
6084 exec_control &= ~SECONDARY_EXEC_XSAVES;
6088 vmx->nested.msrs.secondary_ctls_high |=
6089 SECONDARY_EXEC_XSAVES;
6091 vmx->nested.msrs.secondary_ctls_high &=
6092 ~SECONDARY_EXEC_XSAVES;
6096 if (vmx_rdtscp_supported()) {
6097 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
6098 if (!rdtscp_enabled)
6099 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6103 vmx->nested.msrs.secondary_ctls_high |=
6104 SECONDARY_EXEC_RDTSCP;
6106 vmx->nested.msrs.secondary_ctls_high &=
6107 ~SECONDARY_EXEC_RDTSCP;
6111 if (vmx_invpcid_supported()) {
6112 /* Exposing INVPCID only when PCID is exposed */
6113 bool invpcid_enabled =
6114 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
6115 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
6117 if (!invpcid_enabled) {
6118 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6119 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
6123 if (invpcid_enabled)
6124 vmx->nested.msrs.secondary_ctls_high |=
6125 SECONDARY_EXEC_ENABLE_INVPCID;
6127 vmx->nested.msrs.secondary_ctls_high &=
6128 ~SECONDARY_EXEC_ENABLE_INVPCID;
6132 if (vmx_rdrand_supported()) {
6133 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
6135 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
6139 vmx->nested.msrs.secondary_ctls_high |=
6140 SECONDARY_EXEC_RDRAND_EXITING;
6142 vmx->nested.msrs.secondary_ctls_high &=
6143 ~SECONDARY_EXEC_RDRAND_EXITING;
6147 if (vmx_rdseed_supported()) {
6148 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
6150 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
6154 vmx->nested.msrs.secondary_ctls_high |=
6155 SECONDARY_EXEC_RDSEED_EXITING;
6157 vmx->nested.msrs.secondary_ctls_high &=
6158 ~SECONDARY_EXEC_RDSEED_EXITING;
6162 vmx->secondary_exec_control = exec_control;
6165 static void ept_set_mmio_spte_mask(void)
6168 * EPT Misconfigurations can be generated if the value of bits 2:0
6169 * of an EPT paging-structure entry is 110b (write/execute).
6171 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
6172 VMX_EPT_MISCONFIG_WX_VALUE);
6175 #define VMX_XSS_EXIT_BITMAP 0
6177 * Sets up the vmcs for emulated real mode.
6179 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
6181 #ifdef CONFIG_X86_64
6186 if (enable_shadow_vmcs) {
6188 * At vCPU creation, "VMWRITE to any supported field
6189 * in the VMCS" is supported, so use the more
6190 * permissive vmx_vmread_bitmap to specify both read
6191 * and write permissions for the shadow VMCS.
6193 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6194 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmread_bitmap));
6196 if (cpu_has_vmx_msr_bitmap())
6197 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
6199 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
6202 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6203 vmx->hv_deadline_tsc = -1;
6205 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6207 if (cpu_has_secondary_exec_ctrls()) {
6208 vmx_compute_secondary_exec_control(vmx);
6209 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6210 vmx->secondary_exec_control);
6213 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
6214 vmcs_write64(EOI_EXIT_BITMAP0, 0);
6215 vmcs_write64(EOI_EXIT_BITMAP1, 0);
6216 vmcs_write64(EOI_EXIT_BITMAP2, 0);
6217 vmcs_write64(EOI_EXIT_BITMAP3, 0);
6219 vmcs_write16(GUEST_INTR_STATUS, 0);
6221 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6222 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
6225 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
6226 vmcs_write32(PLE_GAP, ple_gap);
6227 vmx->ple_window = ple_window;
6228 vmx->ple_window_dirty = true;
6231 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
6232 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6233 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
6235 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
6236 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6237 vmx_set_constant_host_state(vmx);
6238 #ifdef CONFIG_X86_64
6239 rdmsrl(MSR_FS_BASE, a);
6240 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
6241 rdmsrl(MSR_GS_BASE, a);
6242 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
6244 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
6245 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6248 if (cpu_has_vmx_vmfunc())
6249 vmcs_write64(VM_FUNCTION_CONTROL, 0);
6251 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
6252 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
6253 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
6254 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6255 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6257 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6258 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6260 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6261 u32 index = vmx_msr_index[i];
6262 u32 data_low, data_high;
6265 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6267 if (wrmsr_safe(index, data_low, data_high) < 0)
6269 vmx->guest_msrs[j].index = i;
6270 vmx->guest_msrs[j].data = 0;
6271 vmx->guest_msrs[j].mask = -1ull;
6275 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
6276 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
6278 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6280 /* 22.2.1, 20.8.1 */
6281 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
6283 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
6284 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
6286 set_cr4_guest_host_mask(vmx);
6288 if (vmx_xsaves_supported())
6289 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
6292 ASSERT(vmx->pml_pg);
6293 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
6294 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6298 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
6300 struct vcpu_vmx *vmx = to_vmx(vcpu);
6301 struct msr_data apic_base_msr;
6304 vmx->rmode.vm86_active = 0;
6307 vcpu->arch.microcode_version = 0x100000000ULL;
6308 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
6309 kvm_set_cr8(vcpu, 0);
6312 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6313 MSR_IA32_APICBASE_ENABLE;
6314 if (kvm_vcpu_is_reset_bsp(vcpu))
6315 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6316 apic_base_msr.host_initiated = true;
6317 kvm_set_apic_base(vcpu, &apic_base_msr);
6320 vmx_segment_cache_clear(vmx);
6322 seg_setup(VCPU_SREG_CS);
6323 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6324 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6326 seg_setup(VCPU_SREG_DS);
6327 seg_setup(VCPU_SREG_ES);
6328 seg_setup(VCPU_SREG_FS);
6329 seg_setup(VCPU_SREG_GS);
6330 seg_setup(VCPU_SREG_SS);
6332 vmcs_write16(GUEST_TR_SELECTOR, 0);
6333 vmcs_writel(GUEST_TR_BASE, 0);
6334 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6335 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6337 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6338 vmcs_writel(GUEST_LDTR_BASE, 0);
6339 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6340 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6343 vmcs_write32(GUEST_SYSENTER_CS, 0);
6344 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6345 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6346 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6349 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6350 kvm_rip_write(vcpu, 0xfff0);
6352 vmcs_writel(GUEST_GDTR_BASE, 0);
6353 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6355 vmcs_writel(GUEST_IDTR_BASE, 0);
6356 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6358 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6359 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6360 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6361 if (kvm_mpx_supported())
6362 vmcs_write64(GUEST_BNDCFGS, 0);
6366 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
6368 if (cpu_has_vmx_tpr_shadow() && !init_event) {
6369 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6370 if (cpu_need_tpr_shadow(vcpu))
6371 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6372 __pa(vcpu->arch.apic->regs));
6373 vmcs_write32(TPR_THRESHOLD, 0);
6376 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6379 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6381 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6382 vmx->vcpu.arch.cr0 = cr0;
6383 vmx_set_cr0(vcpu, cr0); /* enter rmode */
6384 vmx_set_cr4(vcpu, 0);
6385 vmx_set_efer(vcpu, 0);
6387 update_exception_bitmap(vcpu);
6389 vpid_sync_context(vmx->vpid);
6391 vmx_clear_hlt(vcpu);
6395 * In nested virtualization, check if L1 asked to exit on external interrupts.
6396 * For most existing hypervisors, this will always return true.
6398 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6400 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6401 PIN_BASED_EXT_INTR_MASK;
6405 * In nested virtualization, check if L1 has set
6406 * VM_EXIT_ACK_INTR_ON_EXIT
6408 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6410 return get_vmcs12(vcpu)->vm_exit_controls &
6411 VM_EXIT_ACK_INTR_ON_EXIT;
6414 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6416 return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
6419 static void enable_irq_window(struct kvm_vcpu *vcpu)
6421 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6422 CPU_BASED_VIRTUAL_INTR_PENDING);
6425 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6428 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6429 enable_irq_window(vcpu);
6433 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6434 CPU_BASED_VIRTUAL_NMI_PENDING);
6437 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6439 struct vcpu_vmx *vmx = to_vmx(vcpu);
6441 int irq = vcpu->arch.interrupt.nr;
6443 trace_kvm_inj_virq(irq);
6445 ++vcpu->stat.irq_injections;
6446 if (vmx->rmode.vm86_active) {
6448 if (vcpu->arch.interrupt.soft)
6449 inc_eip = vcpu->arch.event_exit_inst_len;
6450 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6451 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6454 intr = irq | INTR_INFO_VALID_MASK;
6455 if (vcpu->arch.interrupt.soft) {
6456 intr |= INTR_TYPE_SOFT_INTR;
6457 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6458 vmx->vcpu.arch.event_exit_inst_len);
6460 intr |= INTR_TYPE_EXT_INTR;
6461 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6463 vmx_clear_hlt(vcpu);
6466 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6468 struct vcpu_vmx *vmx = to_vmx(vcpu);
6472 * Tracking the NMI-blocked state in software is built upon
6473 * finding the next open IRQ window. This, in turn, depends on
6474 * well-behaving guests: They have to keep IRQs disabled at
6475 * least as long as the NMI handler runs. Otherwise we may
6476 * cause NMI nesting, maybe breaking the guest. But as this is
6477 * highly unlikely, we can live with the residual risk.
6479 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6480 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6483 ++vcpu->stat.nmi_injections;
6484 vmx->loaded_vmcs->nmi_known_unmasked = false;
6486 if (vmx->rmode.vm86_active) {
6487 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6488 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6492 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6493 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6495 vmx_clear_hlt(vcpu);
6498 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6500 struct vcpu_vmx *vmx = to_vmx(vcpu);
6504 return vmx->loaded_vmcs->soft_vnmi_blocked;
6505 if (vmx->loaded_vmcs->nmi_known_unmasked)
6507 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6508 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6512 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6514 struct vcpu_vmx *vmx = to_vmx(vcpu);
6517 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6518 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6519 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6522 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6524 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6525 GUEST_INTR_STATE_NMI);
6527 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6528 GUEST_INTR_STATE_NMI);
6532 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6534 if (to_vmx(vcpu)->nested.nested_run_pending)
6538 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6541 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6542 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6543 | GUEST_INTR_STATE_NMI));
6546 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6548 return (!to_vmx(vcpu)->nested.nested_run_pending &&
6549 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6550 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6551 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6554 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6558 if (enable_unrestricted_guest)
6561 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6565 to_kvm_vmx(kvm)->tss_addr = addr;
6566 return init_rmode_tss(kvm);
6569 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
6571 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
6575 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6580 * Update instruction length as we may reinject the exception
6581 * from user space while in guest debugging mode.
6583 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6584 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6585 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6589 if (vcpu->guest_debug &
6590 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6607 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6608 int vec, u32 err_code)
6611 * Instruction with address size override prefix opcode 0x67
6612 * Cause the #SS fault with 0 error code in VM86 mode.
6614 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6615 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6616 if (vcpu->arch.halt_request) {
6617 vcpu->arch.halt_request = 0;
6618 return kvm_vcpu_halt(vcpu);
6626 * Forward all other exceptions that are valid in real mode.
6627 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6628 * the required debugging infrastructure rework.
6630 kvm_queue_exception(vcpu, vec);
6635 * Trigger machine check on the host. We assume all the MSRs are already set up
6636 * by the CPU and that we still run on the same CPU as the MCE occurred on.
6637 * We pass a fake environment to the machine check handler because we want
6638 * the guest to be always treated like user space, no matter what context
6639 * it used internally.
6641 static void kvm_machine_check(void)
6643 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6644 struct pt_regs regs = {
6645 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
6646 .flags = X86_EFLAGS_IF,
6649 do_machine_check(®s, 0);
6653 static int handle_machine_check(struct kvm_vcpu *vcpu)
6655 /* already handled by vcpu_run */
6659 static int handle_exception(struct kvm_vcpu *vcpu)
6661 struct vcpu_vmx *vmx = to_vmx(vcpu);
6662 struct kvm_run *kvm_run = vcpu->run;
6663 u32 intr_info, ex_no, error_code;
6664 unsigned long cr2, rip, dr6;
6666 enum emulation_result er;
6668 vect_info = vmx->idt_vectoring_info;
6669 intr_info = vmx->exit_intr_info;
6671 if (is_machine_check(intr_info))
6672 return handle_machine_check(vcpu);
6674 if (is_nmi(intr_info))
6675 return 1; /* already handled by vmx_vcpu_run() */
6677 if (is_invalid_opcode(intr_info))
6678 return handle_ud(vcpu);
6681 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6682 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6684 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
6685 WARN_ON_ONCE(!enable_vmware_backdoor);
6686 er = emulate_instruction(vcpu,
6687 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
6688 if (er == EMULATE_USER_EXIT)
6690 else if (er != EMULATE_DONE)
6691 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
6696 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6697 * MMIO, it is better to report an internal error.
6698 * See the comments in vmx_handle_exit.
6700 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
6701 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
6702 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6703 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
6704 vcpu->run->internal.ndata = 3;
6705 vcpu->run->internal.data[0] = vect_info;
6706 vcpu->run->internal.data[1] = intr_info;
6707 vcpu->run->internal.data[2] = error_code;
6711 if (is_page_fault(intr_info)) {
6712 cr2 = vmcs_readl(EXIT_QUALIFICATION);
6713 /* EPT won't cause page fault directly */
6714 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
6715 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6718 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
6720 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
6721 return handle_rmode_exception(vcpu, ex_no, error_code);
6725 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
6728 dr6 = vmcs_readl(EXIT_QUALIFICATION);
6729 if (!(vcpu->guest_debug &
6730 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
6731 vcpu->arch.dr6 &= ~15;
6732 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6733 if (is_icebp(intr_info))
6734 skip_emulated_instruction(vcpu);
6736 kvm_queue_exception(vcpu, DB_VECTOR);
6739 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
6740 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
6744 * Update instruction length as we may reinject #BP from
6745 * user space while in guest debugging mode. Reading it for
6746 * #DB as well causes no harm, it is not used in that case.
6748 vmx->vcpu.arch.event_exit_inst_len =
6749 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6750 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6751 rip = kvm_rip_read(vcpu);
6752 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
6753 kvm_run->debug.arch.exception = ex_no;
6756 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6757 kvm_run->ex.exception = ex_no;
6758 kvm_run->ex.error_code = error_code;
6764 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6766 ++vcpu->stat.irq_exits;
6770 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6772 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6773 vcpu->mmio_needed = 0;
6777 static int handle_io(struct kvm_vcpu *vcpu)
6779 unsigned long exit_qualification;
6780 int size, in, string;
6783 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6784 string = (exit_qualification & 16) != 0;
6786 ++vcpu->stat.io_exits;
6789 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6791 port = exit_qualification >> 16;
6792 size = (exit_qualification & 7) + 1;
6793 in = (exit_qualification & 8) != 0;
6795 return kvm_fast_pio(vcpu, size, port, in);
6799 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6802 * Patch in the VMCALL instruction:
6804 hypercall[0] = 0x0f;
6805 hypercall[1] = 0x01;
6806 hypercall[2] = 0xc1;
6809 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6810 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6812 if (is_guest_mode(vcpu)) {
6813 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6814 unsigned long orig_val = val;
6817 * We get here when L2 changed cr0 in a way that did not change
6818 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6819 * but did change L0 shadowed bits. So we first calculate the
6820 * effective cr0 value that L1 would like to write into the
6821 * hardware. It consists of the L2-owned bits from the new
6822 * value combined with the L1-owned bits from L1's guest_cr0.
6824 val = (val & ~vmcs12->cr0_guest_host_mask) |
6825 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6827 if (!nested_guest_cr0_valid(vcpu, val))
6830 if (kvm_set_cr0(vcpu, val))
6832 vmcs_writel(CR0_READ_SHADOW, orig_val);
6835 if (to_vmx(vcpu)->nested.vmxon &&
6836 !nested_host_cr0_valid(vcpu, val))
6839 return kvm_set_cr0(vcpu, val);
6843 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6845 if (is_guest_mode(vcpu)) {
6846 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6847 unsigned long orig_val = val;
6849 /* analogously to handle_set_cr0 */
6850 val = (val & ~vmcs12->cr4_guest_host_mask) |
6851 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6852 if (kvm_set_cr4(vcpu, val))
6854 vmcs_writel(CR4_READ_SHADOW, orig_val);
6857 return kvm_set_cr4(vcpu, val);
6860 static int handle_desc(struct kvm_vcpu *vcpu)
6862 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
6863 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6866 static int handle_cr(struct kvm_vcpu *vcpu)
6868 unsigned long exit_qualification, val;
6874 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6875 cr = exit_qualification & 15;
6876 reg = (exit_qualification >> 8) & 15;
6877 switch ((exit_qualification >> 4) & 3) {
6878 case 0: /* mov to cr */
6879 val = kvm_register_readl(vcpu, reg);
6880 trace_kvm_cr_write(cr, val);
6883 err = handle_set_cr0(vcpu, val);
6884 return kvm_complete_insn_gp(vcpu, err);
6886 WARN_ON_ONCE(enable_unrestricted_guest);
6887 err = kvm_set_cr3(vcpu, val);
6888 return kvm_complete_insn_gp(vcpu, err);
6890 err = handle_set_cr4(vcpu, val);
6891 return kvm_complete_insn_gp(vcpu, err);
6893 u8 cr8_prev = kvm_get_cr8(vcpu);
6895 err = kvm_set_cr8(vcpu, cr8);
6896 ret = kvm_complete_insn_gp(vcpu, err);
6897 if (lapic_in_kernel(vcpu))
6899 if (cr8_prev <= cr8)
6902 * TODO: we might be squashing a
6903 * KVM_GUESTDBG_SINGLESTEP-triggered
6904 * KVM_EXIT_DEBUG here.
6906 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6912 WARN_ONCE(1, "Guest should always own CR0.TS");
6913 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6914 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6915 return kvm_skip_emulated_instruction(vcpu);
6916 case 1: /*mov from cr*/
6919 WARN_ON_ONCE(enable_unrestricted_guest);
6920 val = kvm_read_cr3(vcpu);
6921 kvm_register_write(vcpu, reg, val);
6922 trace_kvm_cr_read(cr, val);
6923 return kvm_skip_emulated_instruction(vcpu);
6925 val = kvm_get_cr8(vcpu);
6926 kvm_register_write(vcpu, reg, val);
6927 trace_kvm_cr_read(cr, val);
6928 return kvm_skip_emulated_instruction(vcpu);
6932 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6933 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6934 kvm_lmsw(vcpu, val);
6936 return kvm_skip_emulated_instruction(vcpu);
6940 vcpu->run->exit_reason = 0;
6941 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6942 (int)(exit_qualification >> 4) & 3, cr);
6946 static int handle_dr(struct kvm_vcpu *vcpu)
6948 unsigned long exit_qualification;
6951 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6952 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6954 /* First, if DR does not exist, trigger UD */
6955 if (!kvm_require_dr(vcpu, dr))
6958 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6959 if (!kvm_require_cpl(vcpu, 0))
6961 dr7 = vmcs_readl(GUEST_DR7);
6964 * As the vm-exit takes precedence over the debug trap, we
6965 * need to emulate the latter, either for the host or the
6966 * guest debugging itself.
6968 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6969 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6970 vcpu->run->debug.arch.dr7 = dr7;
6971 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6972 vcpu->run->debug.arch.exception = DB_VECTOR;
6973 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6976 vcpu->arch.dr6 &= ~15;
6977 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6978 kvm_queue_exception(vcpu, DB_VECTOR);
6983 if (vcpu->guest_debug == 0) {
6984 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6985 CPU_BASED_MOV_DR_EXITING);
6988 * No more DR vmexits; force a reload of the debug registers
6989 * and reenter on this instruction. The next vmexit will
6990 * retrieve the full state of the debug registers.
6992 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6996 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6997 if (exit_qualification & TYPE_MOV_FROM_DR) {
7000 if (kvm_get_dr(vcpu, dr, &val))
7002 kvm_register_write(vcpu, reg, val);
7004 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
7007 return kvm_skip_emulated_instruction(vcpu);
7010 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
7012 return vcpu->arch.dr6;
7015 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
7019 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
7021 get_debugreg(vcpu->arch.db[0], 0);
7022 get_debugreg(vcpu->arch.db[1], 1);
7023 get_debugreg(vcpu->arch.db[2], 2);
7024 get_debugreg(vcpu->arch.db[3], 3);
7025 get_debugreg(vcpu->arch.dr6, 6);
7026 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
7028 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
7029 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
7032 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
7034 vmcs_writel(GUEST_DR7, val);
7037 static int handle_cpuid(struct kvm_vcpu *vcpu)
7039 return kvm_emulate_cpuid(vcpu);
7042 static int handle_rdmsr(struct kvm_vcpu *vcpu)
7044 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7045 struct msr_data msr_info;
7047 msr_info.index = ecx;
7048 msr_info.host_initiated = false;
7049 if (vmx_get_msr(vcpu, &msr_info)) {
7050 trace_kvm_msr_read_ex(ecx);
7051 kvm_inject_gp(vcpu, 0);
7055 trace_kvm_msr_read(ecx, msr_info.data);
7057 /* FIXME: handling of bits 32:63 of rax, rdx */
7058 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
7059 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
7060 return kvm_skip_emulated_instruction(vcpu);
7063 static int handle_wrmsr(struct kvm_vcpu *vcpu)
7065 struct msr_data msr;
7066 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7067 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
7068 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
7072 msr.host_initiated = false;
7073 if (kvm_set_msr(vcpu, &msr) != 0) {
7074 trace_kvm_msr_write_ex(ecx, data);
7075 kvm_inject_gp(vcpu, 0);
7079 trace_kvm_msr_write(ecx, data);
7080 return kvm_skip_emulated_instruction(vcpu);
7083 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
7085 kvm_apic_update_ppr(vcpu);
7089 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
7091 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7092 CPU_BASED_VIRTUAL_INTR_PENDING);
7094 kvm_make_request(KVM_REQ_EVENT, vcpu);
7096 ++vcpu->stat.irq_window_exits;
7100 static int handle_halt(struct kvm_vcpu *vcpu)
7102 return kvm_emulate_halt(vcpu);
7105 static int handle_vmcall(struct kvm_vcpu *vcpu)
7107 return kvm_emulate_hypercall(vcpu);
7110 static int handle_invd(struct kvm_vcpu *vcpu)
7112 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7115 static int handle_invlpg(struct kvm_vcpu *vcpu)
7117 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7119 kvm_mmu_invlpg(vcpu, exit_qualification);
7120 return kvm_skip_emulated_instruction(vcpu);
7123 static int handle_rdpmc(struct kvm_vcpu *vcpu)
7127 err = kvm_rdpmc(vcpu);
7128 return kvm_complete_insn_gp(vcpu, err);
7131 static int handle_wbinvd(struct kvm_vcpu *vcpu)
7133 return kvm_emulate_wbinvd(vcpu);
7136 static int handle_xsetbv(struct kvm_vcpu *vcpu)
7138 u64 new_bv = kvm_read_edx_eax(vcpu);
7139 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
7141 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
7142 return kvm_skip_emulated_instruction(vcpu);
7146 static int handle_xsaves(struct kvm_vcpu *vcpu)
7148 kvm_skip_emulated_instruction(vcpu);
7149 WARN(1, "this should never happen\n");
7153 static int handle_xrstors(struct kvm_vcpu *vcpu)
7155 kvm_skip_emulated_instruction(vcpu);
7156 WARN(1, "this should never happen\n");
7160 static int handle_apic_access(struct kvm_vcpu *vcpu)
7162 if (likely(fasteoi)) {
7163 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7164 int access_type, offset;
7166 access_type = exit_qualification & APIC_ACCESS_TYPE;
7167 offset = exit_qualification & APIC_ACCESS_OFFSET;
7169 * Sane guest uses MOV to write EOI, with written value
7170 * not cared. So make a short-circuit here by avoiding
7171 * heavy instruction emulation.
7173 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
7174 (offset == APIC_EOI)) {
7175 kvm_lapic_set_eoi(vcpu);
7176 return kvm_skip_emulated_instruction(vcpu);
7179 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7182 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
7184 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7185 int vector = exit_qualification & 0xff;
7187 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
7188 kvm_apic_set_eoi_accelerated(vcpu, vector);
7192 static int handle_apic_write(struct kvm_vcpu *vcpu)
7194 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7195 u32 offset = exit_qualification & 0xfff;
7197 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
7198 kvm_apic_write_nodecode(vcpu, offset);
7202 static int handle_task_switch(struct kvm_vcpu *vcpu)
7204 struct vcpu_vmx *vmx = to_vmx(vcpu);
7205 unsigned long exit_qualification;
7206 bool has_error_code = false;
7209 int reason, type, idt_v, idt_index;
7211 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7212 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
7213 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
7215 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7217 reason = (u32)exit_qualification >> 30;
7218 if (reason == TASK_SWITCH_GATE && idt_v) {
7220 case INTR_TYPE_NMI_INTR:
7221 vcpu->arch.nmi_injected = false;
7222 vmx_set_nmi_mask(vcpu, true);
7224 case INTR_TYPE_EXT_INTR:
7225 case INTR_TYPE_SOFT_INTR:
7226 kvm_clear_interrupt_queue(vcpu);
7228 case INTR_TYPE_HARD_EXCEPTION:
7229 if (vmx->idt_vectoring_info &
7230 VECTORING_INFO_DELIVER_CODE_MASK) {
7231 has_error_code = true;
7233 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7236 case INTR_TYPE_SOFT_EXCEPTION:
7237 kvm_clear_exception_queue(vcpu);
7243 tss_selector = exit_qualification;
7245 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
7246 type != INTR_TYPE_EXT_INTR &&
7247 type != INTR_TYPE_NMI_INTR))
7248 skip_emulated_instruction(vcpu);
7250 if (kvm_task_switch(vcpu, tss_selector,
7251 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
7252 has_error_code, error_code) == EMULATE_FAIL) {
7253 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7254 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7255 vcpu->run->internal.ndata = 0;
7260 * TODO: What about debug traps on tss switch?
7261 * Are we supposed to inject them and update dr6?
7267 static int handle_ept_violation(struct kvm_vcpu *vcpu)
7269 unsigned long exit_qualification;
7273 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7276 * EPT violation happened while executing iret from NMI,
7277 * "blocked by NMI" bit has to be set before next VM entry.
7278 * There are errata that may cause this bit to not be set:
7281 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7283 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7284 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
7286 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7287 trace_kvm_page_fault(gpa, exit_qualification);
7289 /* Is it a read fault? */
7290 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
7291 ? PFERR_USER_MASK : 0;
7292 /* Is it a write fault? */
7293 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
7294 ? PFERR_WRITE_MASK : 0;
7295 /* Is it a fetch fault? */
7296 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
7297 ? PFERR_FETCH_MASK : 0;
7298 /* ept page table entry is present? */
7299 error_code |= (exit_qualification &
7300 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
7301 EPT_VIOLATION_EXECUTABLE))
7302 ? PFERR_PRESENT_MASK : 0;
7304 error_code |= (exit_qualification & 0x100) != 0 ?
7305 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
7307 vcpu->arch.exit_qualification = exit_qualification;
7308 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
7311 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
7316 * A nested guest cannot optimize MMIO vmexits, because we have an
7317 * nGPA here instead of the required GPA.
7319 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7320 if (!is_guest_mode(vcpu) &&
7321 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
7322 trace_kvm_fast_mmio(gpa);
7324 * Doing kvm_skip_emulated_instruction() depends on undefined
7325 * behavior: Intel's manual doesn't mandate
7326 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7327 * occurs and while on real hardware it was observed to be set,
7328 * other hypervisors (namely Hyper-V) don't set it, we end up
7329 * advancing IP with some random value. Disable fast mmio when
7330 * running nested and keep it for real hardware in hope that
7331 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7333 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7334 return kvm_skip_emulated_instruction(vcpu);
7336 return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP,
7337 NULL, 0) == EMULATE_DONE;
7340 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7343 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7345 WARN_ON_ONCE(!enable_vnmi);
7346 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7347 CPU_BASED_VIRTUAL_NMI_PENDING);
7348 ++vcpu->stat.nmi_window_exits;
7349 kvm_make_request(KVM_REQ_EVENT, vcpu);
7354 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7356 struct vcpu_vmx *vmx = to_vmx(vcpu);
7357 enum emulation_result err = EMULATE_DONE;
7360 bool intr_window_requested;
7361 unsigned count = 130;
7364 * We should never reach the point where we are emulating L2
7365 * due to invalid guest state as that means we incorrectly
7366 * allowed a nested VMEntry with an invalid vmcs12.
7368 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
7370 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7371 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7373 while (vmx->emulation_required && count-- != 0) {
7374 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7375 return handle_interrupt_window(&vmx->vcpu);
7377 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7380 err = emulate_instruction(vcpu, 0);
7382 if (err == EMULATE_USER_EXIT) {
7383 ++vcpu->stat.mmio_exits;
7388 if (err != EMULATE_DONE)
7389 goto emulation_error;
7391 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7392 vcpu->arch.exception.pending)
7393 goto emulation_error;
7395 if (vcpu->arch.halt_request) {
7396 vcpu->arch.halt_request = 0;
7397 ret = kvm_vcpu_halt(vcpu);
7401 if (signal_pending(current))
7411 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7412 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7413 vcpu->run->internal.ndata = 0;
7417 static void grow_ple_window(struct kvm_vcpu *vcpu)
7419 struct vcpu_vmx *vmx = to_vmx(vcpu);
7420 int old = vmx->ple_window;
7422 vmx->ple_window = __grow_ple_window(old, ple_window,
7426 if (vmx->ple_window != old)
7427 vmx->ple_window_dirty = true;
7429 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7432 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7434 struct vcpu_vmx *vmx = to_vmx(vcpu);
7435 int old = vmx->ple_window;
7437 vmx->ple_window = __shrink_ple_window(old, ple_window,
7441 if (vmx->ple_window != old)
7442 vmx->ple_window_dirty = true;
7444 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7448 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7450 static void wakeup_handler(void)
7452 struct kvm_vcpu *vcpu;
7453 int cpu = smp_processor_id();
7455 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7456 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7457 blocked_vcpu_list) {
7458 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7460 if (pi_test_on(pi_desc) == 1)
7461 kvm_vcpu_kick(vcpu);
7463 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7466 static void vmx_enable_tdp(void)
7468 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7469 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7470 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7471 0ull, VMX_EPT_EXECUTABLE_MASK,
7472 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7473 VMX_EPT_RWX_MASK, 0ull);
7475 ept_set_mmio_spte_mask();
7479 static __init int hardware_setup(void)
7483 rdmsrl_safe(MSR_EFER, &host_efer);
7485 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7486 kvm_define_shared_msr(i, vmx_msr_index[i]);
7488 for (i = 0; i < VMX_BITMAP_NR; i++) {
7489 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7494 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7495 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7497 if (setup_vmcs_config(&vmcs_config) < 0) {
7502 if (boot_cpu_has(X86_FEATURE_NX))
7503 kvm_enable_efer_bits(EFER_NX);
7505 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7506 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7509 if (!cpu_has_vmx_ept() ||
7510 !cpu_has_vmx_ept_4levels() ||
7511 !cpu_has_vmx_ept_mt_wb() ||
7512 !cpu_has_vmx_invept_global())
7515 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7516 enable_ept_ad_bits = 0;
7518 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7519 enable_unrestricted_guest = 0;
7521 if (!cpu_has_vmx_flexpriority())
7522 flexpriority_enabled = 0;
7524 if (!cpu_has_virtual_nmis())
7528 * set_apic_access_page_addr() is used to reload apic access
7529 * page upon invalidation. No need to do anything if not
7530 * using the APIC_ACCESS_ADDR VMCS field.
7532 if (!flexpriority_enabled)
7533 kvm_x86_ops->set_apic_access_page_addr = NULL;
7535 if (!cpu_has_vmx_tpr_shadow())
7536 kvm_x86_ops->update_cr8_intercept = NULL;
7538 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7539 kvm_disable_largepages();
7541 if (!cpu_has_vmx_ple()) {
7544 ple_window_grow = 0;
7546 ple_window_shrink = 0;
7549 if (!cpu_has_vmx_apicv()) {
7551 kvm_x86_ops->sync_pir_to_irr = NULL;
7554 if (cpu_has_vmx_tsc_scaling()) {
7555 kvm_has_tsc_control = true;
7556 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7557 kvm_tsc_scaling_ratio_frac_bits = 48;
7560 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7568 * Only enable PML when hardware supports PML feature, and both EPT
7569 * and EPT A/D bit features are enabled -- PML depends on them to work.
7571 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7575 kvm_x86_ops->slot_enable_log_dirty = NULL;
7576 kvm_x86_ops->slot_disable_log_dirty = NULL;
7577 kvm_x86_ops->flush_log_dirty = NULL;
7578 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7581 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7584 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7585 cpu_preemption_timer_multi =
7586 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7588 kvm_x86_ops->set_hv_timer = NULL;
7589 kvm_x86_ops->cancel_hv_timer = NULL;
7592 if (!cpu_has_vmx_shadow_vmcs())
7593 enable_shadow_vmcs = 0;
7594 if (enable_shadow_vmcs)
7595 init_vmcs_shadow_fields();
7597 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7598 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv);
7600 kvm_mce_cap_supported |= MCG_LMCE_P;
7602 return alloc_kvm_area();
7605 for (i = 0; i < VMX_BITMAP_NR; i++)
7606 free_page((unsigned long)vmx_bitmap[i]);
7611 static __exit void hardware_unsetup(void)
7615 for (i = 0; i < VMX_BITMAP_NR; i++)
7616 free_page((unsigned long)vmx_bitmap[i]);
7622 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7623 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7625 static int handle_pause(struct kvm_vcpu *vcpu)
7627 if (!kvm_pause_in_guest(vcpu->kvm))
7628 grow_ple_window(vcpu);
7631 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7632 * VM-execution control is ignored if CPL > 0. OTOH, KVM
7633 * never set PAUSE_EXITING and just set PLE if supported,
7634 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7636 kvm_vcpu_on_spin(vcpu, true);
7637 return kvm_skip_emulated_instruction(vcpu);
7640 static int handle_nop(struct kvm_vcpu *vcpu)
7642 return kvm_skip_emulated_instruction(vcpu);
7645 static int handle_mwait(struct kvm_vcpu *vcpu)
7647 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
7648 return handle_nop(vcpu);
7651 static int handle_invalid_op(struct kvm_vcpu *vcpu)
7653 kvm_queue_exception(vcpu, UD_VECTOR);
7657 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
7662 static int handle_monitor(struct kvm_vcpu *vcpu)
7664 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
7665 return handle_nop(vcpu);
7669 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7670 * set the success or error code of an emulated VMX instruction, as specified
7671 * by Vol 2B, VMX Instruction Reference, "Conventions".
7673 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7675 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7676 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7677 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7680 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7682 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7683 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7684 X86_EFLAGS_SF | X86_EFLAGS_OF))
7688 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7689 u32 vm_instruction_error)
7691 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7693 * failValid writes the error number to the current VMCS, which
7694 * can't be done there isn't a current VMCS.
7696 nested_vmx_failInvalid(vcpu);
7699 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7700 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7701 X86_EFLAGS_SF | X86_EFLAGS_OF))
7703 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7705 * We don't need to force a shadow sync because
7706 * VM_INSTRUCTION_ERROR is not shadowed
7710 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7712 /* TODO: not to reset guest simply here. */
7713 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7714 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7717 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7719 struct vcpu_vmx *vmx =
7720 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7722 vmx->nested.preemption_timer_expired = true;
7723 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7724 kvm_vcpu_kick(&vmx->vcpu);
7726 return HRTIMER_NORESTART;
7730 * Decode the memory-address operand of a vmx instruction, as recorded on an
7731 * exit caused by such an instruction (run by a guest hypervisor).
7732 * On success, returns 0. When the operand is invalid, returns 1 and throws
7735 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7736 unsigned long exit_qualification,
7737 u32 vmx_instruction_info, bool wr, gva_t *ret)
7741 struct kvm_segment s;
7744 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7745 * Execution", on an exit, vmx_instruction_info holds most of the
7746 * addressing components of the operand. Only the displacement part
7747 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7748 * For how an actual address is calculated from all these components,
7749 * refer to Vol. 1, "Operand Addressing".
7751 int scaling = vmx_instruction_info & 3;
7752 int addr_size = (vmx_instruction_info >> 7) & 7;
7753 bool is_reg = vmx_instruction_info & (1u << 10);
7754 int seg_reg = (vmx_instruction_info >> 15) & 7;
7755 int index_reg = (vmx_instruction_info >> 18) & 0xf;
7756 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7757 int base_reg = (vmx_instruction_info >> 23) & 0xf;
7758 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
7761 kvm_queue_exception(vcpu, UD_VECTOR);
7765 /* Addr = segment_base + offset */
7766 /* offset = base + [index * scale] + displacement */
7767 off = exit_qualification; /* holds the displacement */
7769 off += kvm_register_read(vcpu, base_reg);
7771 off += kvm_register_read(vcpu, index_reg)<<scaling;
7772 vmx_get_segment(vcpu, &s, seg_reg);
7773 *ret = s.base + off;
7775 if (addr_size == 1) /* 32 bit */
7778 /* Checks for #GP/#SS exceptions. */
7780 if (is_long_mode(vcpu)) {
7781 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7782 * non-canonical form. This is the only check on the memory
7783 * destination for long mode!
7785 exn = is_noncanonical_address(*ret, vcpu);
7786 } else if (is_protmode(vcpu)) {
7787 /* Protected mode: apply checks for segment validity in the
7789 * - segment type check (#GP(0) may be thrown)
7790 * - usability check (#GP(0)/#SS(0))
7791 * - limit check (#GP(0)/#SS(0))
7794 /* #GP(0) if the destination operand is located in a
7795 * read-only data segment or any code segment.
7797 exn = ((s.type & 0xa) == 0 || (s.type & 8));
7799 /* #GP(0) if the source operand is located in an
7800 * execute-only code segment
7802 exn = ((s.type & 0xa) == 8);
7804 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7807 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7809 exn = (s.unusable != 0);
7810 /* Protected mode: #GP(0)/#SS(0) if the memory
7811 * operand is outside the segment limit.
7813 exn = exn || (off + sizeof(u64) > s.limit);
7816 kvm_queue_exception_e(vcpu,
7817 seg_reg == VCPU_SREG_SS ?
7818 SS_VECTOR : GP_VECTOR,
7826 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7829 struct x86_exception e;
7831 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7832 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7835 if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) {
7836 kvm_inject_page_fault(vcpu, &e);
7843 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7845 struct vcpu_vmx *vmx = to_vmx(vcpu);
7846 struct vmcs *shadow_vmcs;
7849 r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7853 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7854 if (!vmx->nested.cached_vmcs12)
7855 goto out_cached_vmcs12;
7857 if (enable_shadow_vmcs) {
7858 shadow_vmcs = alloc_vmcs();
7860 goto out_shadow_vmcs;
7861 /* mark vmcs as shadow */
7862 shadow_vmcs->revision_id |= (1u << 31);
7863 /* init shadow vmcs */
7864 vmcs_clear(shadow_vmcs);
7865 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7868 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7869 HRTIMER_MODE_REL_PINNED);
7870 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7872 vmx->nested.vmxon = true;
7876 kfree(vmx->nested.cached_vmcs12);
7879 free_loaded_vmcs(&vmx->nested.vmcs02);
7886 * Emulate the VMXON instruction.
7887 * Currently, we just remember that VMX is active, and do not save or even
7888 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7889 * do not currently need to store anything in that guest-allocated memory
7890 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7891 * argument is different from the VMXON pointer (which the spec says they do).
7893 static int handle_vmon(struct kvm_vcpu *vcpu)
7898 struct vcpu_vmx *vmx = to_vmx(vcpu);
7899 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7900 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7903 * The Intel VMX Instruction Reference lists a bunch of bits that are
7904 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7905 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7906 * Otherwise, we should fail with #UD. But most faulting conditions
7907 * have already been checked by hardware, prior to the VM-exit for
7908 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7909 * that bit set to 1 in non-root mode.
7911 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7912 kvm_queue_exception(vcpu, UD_VECTOR);
7916 /* CPL=0 must be checked manually. */
7917 if (vmx_get_cpl(vcpu)) {
7918 kvm_queue_exception(vcpu, UD_VECTOR);
7922 if (vmx->nested.vmxon) {
7923 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7924 return kvm_skip_emulated_instruction(vcpu);
7927 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7928 != VMXON_NEEDED_FEATURES) {
7929 kvm_inject_gp(vcpu, 0);
7933 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7938 * The first 4 bytes of VMXON region contain the supported
7939 * VMCS revision identifier
7941 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7942 * which replaces physical address width with 32
7944 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7945 nested_vmx_failInvalid(vcpu);
7946 return kvm_skip_emulated_instruction(vcpu);
7949 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7950 if (is_error_page(page)) {
7951 nested_vmx_failInvalid(vcpu);
7952 return kvm_skip_emulated_instruction(vcpu);
7954 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7956 kvm_release_page_clean(page);
7957 nested_vmx_failInvalid(vcpu);
7958 return kvm_skip_emulated_instruction(vcpu);
7961 kvm_release_page_clean(page);
7963 vmx->nested.vmxon_ptr = vmptr;
7964 ret = enter_vmx_operation(vcpu);
7968 nested_vmx_succeed(vcpu);
7969 return kvm_skip_emulated_instruction(vcpu);
7973 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7974 * for running VMX instructions (except VMXON, whose prerequisites are
7975 * slightly different). It also specifies what exception to inject otherwise.
7976 * Note that many of these exceptions have priority over VM exits, so they
7977 * don't have to be checked again here.
7979 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7981 if (vmx_get_cpl(vcpu)) {
7982 kvm_queue_exception(vcpu, UD_VECTOR);
7986 if (!to_vmx(vcpu)->nested.vmxon) {
7987 kvm_queue_exception(vcpu, UD_VECTOR);
7993 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7995 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7996 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7999 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
8001 if (vmx->nested.current_vmptr == -1ull)
8004 if (enable_shadow_vmcs) {
8005 /* copy to memory all shadowed fields in case
8006 they were modified */
8007 copy_shadow_to_vmcs12(vmx);
8008 vmx->nested.sync_shadow_vmcs = false;
8009 vmx_disable_shadow_vmcs(vmx);
8011 vmx->nested.posted_intr_nv = -1;
8013 /* Flush VMCS12 to guest memory */
8014 kvm_vcpu_write_guest_page(&vmx->vcpu,
8015 vmx->nested.current_vmptr >> PAGE_SHIFT,
8016 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
8018 vmx->nested.current_vmptr = -1ull;
8022 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
8023 * just stops using VMX.
8025 static void free_nested(struct vcpu_vmx *vmx)
8027 if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
8030 vmx->nested.vmxon = false;
8031 vmx->nested.smm.vmxon = false;
8032 free_vpid(vmx->nested.vpid02);
8033 vmx->nested.posted_intr_nv = -1;
8034 vmx->nested.current_vmptr = -1ull;
8035 if (enable_shadow_vmcs) {
8036 vmx_disable_shadow_vmcs(vmx);
8037 vmcs_clear(vmx->vmcs01.shadow_vmcs);
8038 free_vmcs(vmx->vmcs01.shadow_vmcs);
8039 vmx->vmcs01.shadow_vmcs = NULL;
8041 kfree(vmx->nested.cached_vmcs12);
8042 /* Unpin physical memory we referred to in the vmcs02 */
8043 if (vmx->nested.apic_access_page) {
8044 kvm_release_page_dirty(vmx->nested.apic_access_page);
8045 vmx->nested.apic_access_page = NULL;
8047 if (vmx->nested.virtual_apic_page) {
8048 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
8049 vmx->nested.virtual_apic_page = NULL;
8051 if (vmx->nested.pi_desc_page) {
8052 kunmap(vmx->nested.pi_desc_page);
8053 kvm_release_page_dirty(vmx->nested.pi_desc_page);
8054 vmx->nested.pi_desc_page = NULL;
8055 vmx->nested.pi_desc = NULL;
8058 free_loaded_vmcs(&vmx->nested.vmcs02);
8061 /* Emulate the VMXOFF instruction */
8062 static int handle_vmoff(struct kvm_vcpu *vcpu)
8064 if (!nested_vmx_check_permission(vcpu))
8066 free_nested(to_vmx(vcpu));
8067 nested_vmx_succeed(vcpu);
8068 return kvm_skip_emulated_instruction(vcpu);
8071 /* Emulate the VMCLEAR instruction */
8072 static int handle_vmclear(struct kvm_vcpu *vcpu)
8074 struct vcpu_vmx *vmx = to_vmx(vcpu);
8078 if (!nested_vmx_check_permission(vcpu))
8081 if (nested_vmx_get_vmptr(vcpu, &vmptr))
8084 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8085 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
8086 return kvm_skip_emulated_instruction(vcpu);
8089 if (vmptr == vmx->nested.vmxon_ptr) {
8090 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
8091 return kvm_skip_emulated_instruction(vcpu);
8094 if (vmptr == vmx->nested.current_vmptr)
8095 nested_release_vmcs12(vmx);
8097 kvm_vcpu_write_guest(vcpu,
8098 vmptr + offsetof(struct vmcs12, launch_state),
8099 &zero, sizeof(zero));
8101 nested_vmx_succeed(vcpu);
8102 return kvm_skip_emulated_instruction(vcpu);
8105 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
8107 /* Emulate the VMLAUNCH instruction */
8108 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
8110 return nested_vmx_run(vcpu, true);
8113 /* Emulate the VMRESUME instruction */
8114 static int handle_vmresume(struct kvm_vcpu *vcpu)
8117 return nested_vmx_run(vcpu, false);
8121 * Read a vmcs12 field. Since these can have varying lengths and we return
8122 * one type, we chose the biggest type (u64) and zero-extend the return value
8123 * to that size. Note that the caller, handle_vmread, might need to use only
8124 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
8125 * 64-bit fields are to be returned).
8127 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
8128 unsigned long field, u64 *ret)
8130 short offset = vmcs_field_to_offset(field);
8136 p = ((char *)(get_vmcs12(vcpu))) + offset;
8138 switch (vmcs_field_width(field)) {
8139 case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8140 *ret = *((natural_width *)p);
8142 case VMCS_FIELD_WIDTH_U16:
8145 case VMCS_FIELD_WIDTH_U32:
8148 case VMCS_FIELD_WIDTH_U64:
8158 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
8159 unsigned long field, u64 field_value){
8160 short offset = vmcs_field_to_offset(field);
8161 char *p = ((char *) get_vmcs12(vcpu)) + offset;
8165 switch (vmcs_field_width(field)) {
8166 case VMCS_FIELD_WIDTH_U16:
8167 *(u16 *)p = field_value;
8169 case VMCS_FIELD_WIDTH_U32:
8170 *(u32 *)p = field_value;
8172 case VMCS_FIELD_WIDTH_U64:
8173 *(u64 *)p = field_value;
8175 case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8176 *(natural_width *)p = field_value;
8186 * Copy the writable VMCS shadow fields back to the VMCS12, in case
8187 * they have been modified by the L1 guest. Note that the "read-only"
8188 * VM-exit information fields are actually writable if the vCPU is
8189 * configured to support "VMWRITE to any supported field in the VMCS."
8191 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
8193 const u16 *fields[] = {
8194 shadow_read_write_fields,
8195 shadow_read_only_fields
8197 const int max_fields[] = {
8198 max_shadow_read_write_fields,
8199 max_shadow_read_only_fields
8202 unsigned long field;
8204 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8208 vmcs_load(shadow_vmcs);
8210 for (q = 0; q < ARRAY_SIZE(fields); q++) {
8211 for (i = 0; i < max_fields[q]; i++) {
8212 field = fields[q][i];
8213 field_value = __vmcs_readl(field);
8214 vmcs12_write_any(&vmx->vcpu, field, field_value);
8217 * Skip the VM-exit information fields if they are read-only.
8219 if (!nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
8223 vmcs_clear(shadow_vmcs);
8224 vmcs_load(vmx->loaded_vmcs->vmcs);
8229 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
8231 const u16 *fields[] = {
8232 shadow_read_write_fields,
8233 shadow_read_only_fields
8235 const int max_fields[] = {
8236 max_shadow_read_write_fields,
8237 max_shadow_read_only_fields
8240 unsigned long field;
8241 u64 field_value = 0;
8242 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8244 vmcs_load(shadow_vmcs);
8246 for (q = 0; q < ARRAY_SIZE(fields); q++) {
8247 for (i = 0; i < max_fields[q]; i++) {
8248 field = fields[q][i];
8249 vmcs12_read_any(&vmx->vcpu, field, &field_value);
8250 __vmcs_writel(field, field_value);
8254 vmcs_clear(shadow_vmcs);
8255 vmcs_load(vmx->loaded_vmcs->vmcs);
8259 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
8260 * used before) all generate the same failure when it is missing.
8262 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
8264 struct vcpu_vmx *vmx = to_vmx(vcpu);
8265 if (vmx->nested.current_vmptr == -1ull) {
8266 nested_vmx_failInvalid(vcpu);
8272 static int handle_vmread(struct kvm_vcpu *vcpu)
8274 unsigned long field;
8276 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8277 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8280 if (!nested_vmx_check_permission(vcpu))
8283 if (!nested_vmx_check_vmcs12(vcpu))
8284 return kvm_skip_emulated_instruction(vcpu);
8286 /* Decode instruction info and find the field to read */
8287 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8288 /* Read the field, zero-extended to a u64 field_value */
8289 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
8290 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8291 return kvm_skip_emulated_instruction(vcpu);
8294 * Now copy part of this value to register or memory, as requested.
8295 * Note that the number of bits actually copied is 32 or 64 depending
8296 * on the guest's mode (32 or 64 bit), not on the given field's length.
8298 if (vmx_instruction_info & (1u << 10)) {
8299 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
8302 if (get_vmx_mem_address(vcpu, exit_qualification,
8303 vmx_instruction_info, true, &gva))
8305 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
8306 kvm_write_guest_virt_system(vcpu, gva, &field_value,
8307 (is_long_mode(vcpu) ? 8 : 4), NULL);
8310 nested_vmx_succeed(vcpu);
8311 return kvm_skip_emulated_instruction(vcpu);
8315 static int handle_vmwrite(struct kvm_vcpu *vcpu)
8317 unsigned long field;
8319 struct vcpu_vmx *vmx = to_vmx(vcpu);
8320 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8321 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8323 /* The value to write might be 32 or 64 bits, depending on L1's long
8324 * mode, and eventually we need to write that into a field of several
8325 * possible lengths. The code below first zero-extends the value to 64
8326 * bit (field_value), and then copies only the appropriate number of
8327 * bits into the vmcs12 field.
8329 u64 field_value = 0;
8330 struct x86_exception e;
8332 if (!nested_vmx_check_permission(vcpu))
8335 if (!nested_vmx_check_vmcs12(vcpu))
8336 return kvm_skip_emulated_instruction(vcpu);
8338 if (vmx_instruction_info & (1u << 10))
8339 field_value = kvm_register_readl(vcpu,
8340 (((vmx_instruction_info) >> 3) & 0xf));
8342 if (get_vmx_mem_address(vcpu, exit_qualification,
8343 vmx_instruction_info, false, &gva))
8345 if (kvm_read_guest_virt(vcpu, gva, &field_value,
8346 (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
8347 kvm_inject_page_fault(vcpu, &e);
8353 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8355 * If the vCPU supports "VMWRITE to any supported field in the
8356 * VMCS," then the "read-only" fields are actually read/write.
8358 if (vmcs_field_readonly(field) &&
8359 !nested_cpu_has_vmwrite_any_field(vcpu)) {
8360 nested_vmx_failValid(vcpu,
8361 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
8362 return kvm_skip_emulated_instruction(vcpu);
8365 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
8366 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8367 return kvm_skip_emulated_instruction(vcpu);
8371 #define SHADOW_FIELD_RW(x) case x:
8372 #include "vmx_shadow_fields.h"
8374 * The fields that can be updated by L1 without a vmexit are
8375 * always updated in the vmcs02, the others go down the slow
8376 * path of prepare_vmcs02.
8380 vmx->nested.dirty_vmcs12 = true;
8384 nested_vmx_succeed(vcpu);
8385 return kvm_skip_emulated_instruction(vcpu);
8388 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
8390 vmx->nested.current_vmptr = vmptr;
8391 if (enable_shadow_vmcs) {
8392 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
8393 SECONDARY_EXEC_SHADOW_VMCS);
8394 vmcs_write64(VMCS_LINK_POINTER,
8395 __pa(vmx->vmcs01.shadow_vmcs));
8396 vmx->nested.sync_shadow_vmcs = true;
8398 vmx->nested.dirty_vmcs12 = true;
8401 /* Emulate the VMPTRLD instruction */
8402 static int handle_vmptrld(struct kvm_vcpu *vcpu)
8404 struct vcpu_vmx *vmx = to_vmx(vcpu);
8407 if (!nested_vmx_check_permission(vcpu))
8410 if (nested_vmx_get_vmptr(vcpu, &vmptr))
8413 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8414 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
8415 return kvm_skip_emulated_instruction(vcpu);
8418 if (vmptr == vmx->nested.vmxon_ptr) {
8419 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
8420 return kvm_skip_emulated_instruction(vcpu);
8423 if (vmx->nested.current_vmptr != vmptr) {
8424 struct vmcs12 *new_vmcs12;
8426 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8427 if (is_error_page(page)) {
8428 nested_vmx_failInvalid(vcpu);
8429 return kvm_skip_emulated_instruction(vcpu);
8431 new_vmcs12 = kmap(page);
8432 if (new_vmcs12->revision_id != VMCS12_REVISION) {
8434 kvm_release_page_clean(page);
8435 nested_vmx_failValid(vcpu,
8436 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
8437 return kvm_skip_emulated_instruction(vcpu);
8440 nested_release_vmcs12(vmx);
8442 * Load VMCS12 from guest memory since it is not already
8445 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
8447 kvm_release_page_clean(page);
8449 set_current_vmptr(vmx, vmptr);
8452 nested_vmx_succeed(vcpu);
8453 return kvm_skip_emulated_instruction(vcpu);
8456 /* Emulate the VMPTRST instruction */
8457 static int handle_vmptrst(struct kvm_vcpu *vcpu)
8459 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8460 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8462 struct x86_exception e;
8464 if (!nested_vmx_check_permission(vcpu))
8467 if (get_vmx_mem_address(vcpu, exit_qualification,
8468 vmx_instruction_info, true, &vmcs_gva))
8470 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
8471 if (kvm_write_guest_virt_system(vcpu, vmcs_gva,
8472 (void *)&to_vmx(vcpu)->nested.current_vmptr,
8474 kvm_inject_page_fault(vcpu, &e);
8477 nested_vmx_succeed(vcpu);
8478 return kvm_skip_emulated_instruction(vcpu);
8481 /* Emulate the INVEPT instruction */
8482 static int handle_invept(struct kvm_vcpu *vcpu)
8484 struct vcpu_vmx *vmx = to_vmx(vcpu);
8485 u32 vmx_instruction_info, types;
8488 struct x86_exception e;
8493 if (!(vmx->nested.msrs.secondary_ctls_high &
8494 SECONDARY_EXEC_ENABLE_EPT) ||
8495 !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
8496 kvm_queue_exception(vcpu, UD_VECTOR);
8500 if (!nested_vmx_check_permission(vcpu))
8503 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8504 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8506 types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
8508 if (type >= 32 || !(types & (1 << type))) {
8509 nested_vmx_failValid(vcpu,
8510 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8511 return kvm_skip_emulated_instruction(vcpu);
8514 /* According to the Intel VMX instruction reference, the memory
8515 * operand is read even if it isn't needed (e.g., for type==global)
8517 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8518 vmx_instruction_info, false, &gva))
8520 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8521 kvm_inject_page_fault(vcpu, &e);
8526 case VMX_EPT_EXTENT_GLOBAL:
8528 * TODO: track mappings and invalidate
8529 * single context requests appropriately
8531 case VMX_EPT_EXTENT_CONTEXT:
8532 kvm_mmu_sync_roots(vcpu);
8533 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
8534 nested_vmx_succeed(vcpu);
8541 return kvm_skip_emulated_instruction(vcpu);
8544 static int handle_invvpid(struct kvm_vcpu *vcpu)
8546 struct vcpu_vmx *vmx = to_vmx(vcpu);
8547 u32 vmx_instruction_info;
8548 unsigned long type, types;
8550 struct x86_exception e;
8556 if (!(vmx->nested.msrs.secondary_ctls_high &
8557 SECONDARY_EXEC_ENABLE_VPID) ||
8558 !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
8559 kvm_queue_exception(vcpu, UD_VECTOR);
8563 if (!nested_vmx_check_permission(vcpu))
8566 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8567 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8569 types = (vmx->nested.msrs.vpid_caps &
8570 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
8572 if (type >= 32 || !(types & (1 << type))) {
8573 nested_vmx_failValid(vcpu,
8574 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8575 return kvm_skip_emulated_instruction(vcpu);
8578 /* according to the intel vmx instruction reference, the memory
8579 * operand is read even if it isn't needed (e.g., for type==global)
8581 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8582 vmx_instruction_info, false, &gva))
8584 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8585 kvm_inject_page_fault(vcpu, &e);
8588 if (operand.vpid >> 16) {
8589 nested_vmx_failValid(vcpu,
8590 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8591 return kvm_skip_emulated_instruction(vcpu);
8595 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
8596 if (!operand.vpid ||
8597 is_noncanonical_address(operand.gla, vcpu)) {
8598 nested_vmx_failValid(vcpu,
8599 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8600 return kvm_skip_emulated_instruction(vcpu);
8602 if (cpu_has_vmx_invvpid_individual_addr() &&
8603 vmx->nested.vpid02) {
8604 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR,
8605 vmx->nested.vpid02, operand.gla);
8607 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8609 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
8610 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
8611 if (!operand.vpid) {
8612 nested_vmx_failValid(vcpu,
8613 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8614 return kvm_skip_emulated_instruction(vcpu);
8616 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8618 case VMX_VPID_EXTENT_ALL_CONTEXT:
8619 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8623 return kvm_skip_emulated_instruction(vcpu);
8626 nested_vmx_succeed(vcpu);
8628 return kvm_skip_emulated_instruction(vcpu);
8631 static int handle_pml_full(struct kvm_vcpu *vcpu)
8633 unsigned long exit_qualification;
8635 trace_kvm_pml_full(vcpu->vcpu_id);
8637 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8640 * PML buffer FULL happened while executing iret from NMI,
8641 * "blocked by NMI" bit has to be set before next VM entry.
8643 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
8645 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
8646 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8647 GUEST_INTR_STATE_NMI);
8650 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8651 * here.., and there's no userspace involvement needed for PML.
8656 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8658 kvm_lapic_expired_hv_timer(vcpu);
8662 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8664 struct vcpu_vmx *vmx = to_vmx(vcpu);
8665 int maxphyaddr = cpuid_maxphyaddr(vcpu);
8667 /* Check for memory type validity */
8668 switch (address & VMX_EPTP_MT_MASK) {
8669 case VMX_EPTP_MT_UC:
8670 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))
8673 case VMX_EPTP_MT_WB:
8674 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))
8681 /* only 4 levels page-walk length are valid */
8682 if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8685 /* Reserved bits should not be set */
8686 if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8689 /* AD, if set, should be supported */
8690 if (address & VMX_EPTP_AD_ENABLE_BIT) {
8691 if (!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))
8698 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8699 struct vmcs12 *vmcs12)
8701 u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8703 bool accessed_dirty;
8704 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8706 if (!nested_cpu_has_eptp_switching(vmcs12) ||
8707 !nested_cpu_has_ept(vmcs12))
8710 if (index >= VMFUNC_EPTP_ENTRIES)
8714 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8715 &address, index * 8, 8))
8718 accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8721 * If the (L2) guest does a vmfunc to the currently
8722 * active ept pointer, we don't have to do anything else
8724 if (vmcs12->ept_pointer != address) {
8725 if (!valid_ept_address(vcpu, address))
8728 kvm_mmu_unload(vcpu);
8729 mmu->ept_ad = accessed_dirty;
8730 mmu->base_role.ad_disabled = !accessed_dirty;
8731 vmcs12->ept_pointer = address;
8733 * TODO: Check what's the correct approach in case
8734 * mmu reload fails. Currently, we just let the next
8735 * reload potentially fail
8737 kvm_mmu_reload(vcpu);
8743 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8745 struct vcpu_vmx *vmx = to_vmx(vcpu);
8746 struct vmcs12 *vmcs12;
8747 u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8750 * VMFUNC is only supported for nested guests, but we always enable the
8751 * secondary control for simplicity; for non-nested mode, fake that we
8752 * didn't by injecting #UD.
8754 if (!is_guest_mode(vcpu)) {
8755 kvm_queue_exception(vcpu, UD_VECTOR);
8759 vmcs12 = get_vmcs12(vcpu);
8760 if ((vmcs12->vm_function_control & (1 << function)) == 0)
8765 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8771 return kvm_skip_emulated_instruction(vcpu);
8774 nested_vmx_vmexit(vcpu, vmx->exit_reason,
8775 vmcs_read32(VM_EXIT_INTR_INFO),
8776 vmcs_readl(EXIT_QUALIFICATION));
8781 * The exit handlers return 1 if the exit was handled fully and guest execution
8782 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8783 * to be done to userspace and return 0.
8785 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8786 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
8787 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
8788 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
8789 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
8790 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
8791 [EXIT_REASON_CR_ACCESS] = handle_cr,
8792 [EXIT_REASON_DR_ACCESS] = handle_dr,
8793 [EXIT_REASON_CPUID] = handle_cpuid,
8794 [EXIT_REASON_MSR_READ] = handle_rdmsr,
8795 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
8796 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
8797 [EXIT_REASON_HLT] = handle_halt,
8798 [EXIT_REASON_INVD] = handle_invd,
8799 [EXIT_REASON_INVLPG] = handle_invlpg,
8800 [EXIT_REASON_RDPMC] = handle_rdpmc,
8801 [EXIT_REASON_VMCALL] = handle_vmcall,
8802 [EXIT_REASON_VMCLEAR] = handle_vmclear,
8803 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
8804 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
8805 [EXIT_REASON_VMPTRST] = handle_vmptrst,
8806 [EXIT_REASON_VMREAD] = handle_vmread,
8807 [EXIT_REASON_VMRESUME] = handle_vmresume,
8808 [EXIT_REASON_VMWRITE] = handle_vmwrite,
8809 [EXIT_REASON_VMOFF] = handle_vmoff,
8810 [EXIT_REASON_VMON] = handle_vmon,
8811 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
8812 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
8813 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
8814 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
8815 [EXIT_REASON_WBINVD] = handle_wbinvd,
8816 [EXIT_REASON_XSETBV] = handle_xsetbv,
8817 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
8818 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
8819 [EXIT_REASON_GDTR_IDTR] = handle_desc,
8820 [EXIT_REASON_LDTR_TR] = handle_desc,
8821 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
8822 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
8823 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
8824 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
8825 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
8826 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
8827 [EXIT_REASON_INVEPT] = handle_invept,
8828 [EXIT_REASON_INVVPID] = handle_invvpid,
8829 [EXIT_REASON_RDRAND] = handle_invalid_op,
8830 [EXIT_REASON_RDSEED] = handle_invalid_op,
8831 [EXIT_REASON_XSAVES] = handle_xsaves,
8832 [EXIT_REASON_XRSTORS] = handle_xrstors,
8833 [EXIT_REASON_PML_FULL] = handle_pml_full,
8834 [EXIT_REASON_VMFUNC] = handle_vmfunc,
8835 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
8838 static const int kvm_vmx_max_exit_handlers =
8839 ARRAY_SIZE(kvm_vmx_exit_handlers);
8841 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8842 struct vmcs12 *vmcs12)
8844 unsigned long exit_qualification;
8845 gpa_t bitmap, last_bitmap;
8850 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8851 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8853 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8855 port = exit_qualification >> 16;
8856 size = (exit_qualification & 7) + 1;
8858 last_bitmap = (gpa_t)-1;
8863 bitmap = vmcs12->io_bitmap_a;
8864 else if (port < 0x10000)
8865 bitmap = vmcs12->io_bitmap_b;
8868 bitmap += (port & 0x7fff) / 8;
8870 if (last_bitmap != bitmap)
8871 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8873 if (b & (1 << (port & 7)))
8878 last_bitmap = bitmap;
8885 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8886 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8887 * disinterest in the current event (read or write a specific MSR) by using an
8888 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8890 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8891 struct vmcs12 *vmcs12, u32 exit_reason)
8893 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8896 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8900 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8901 * for the four combinations of read/write and low/high MSR numbers.
8902 * First we need to figure out which of the four to use:
8904 bitmap = vmcs12->msr_bitmap;
8905 if (exit_reason == EXIT_REASON_MSR_WRITE)
8907 if (msr_index >= 0xc0000000) {
8908 msr_index -= 0xc0000000;
8912 /* Then read the msr_index'th bit from this bitmap: */
8913 if (msr_index < 1024*8) {
8915 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8917 return 1 & (b >> (msr_index & 7));
8919 return true; /* let L1 handle the wrong parameter */
8923 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8924 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8925 * intercept (via guest_host_mask etc.) the current event.
8927 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8928 struct vmcs12 *vmcs12)
8930 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8931 int cr = exit_qualification & 15;
8935 switch ((exit_qualification >> 4) & 3) {
8936 case 0: /* mov to cr */
8937 reg = (exit_qualification >> 8) & 15;
8938 val = kvm_register_readl(vcpu, reg);
8941 if (vmcs12->cr0_guest_host_mask &
8942 (val ^ vmcs12->cr0_read_shadow))
8946 if ((vmcs12->cr3_target_count >= 1 &&
8947 vmcs12->cr3_target_value0 == val) ||
8948 (vmcs12->cr3_target_count >= 2 &&
8949 vmcs12->cr3_target_value1 == val) ||
8950 (vmcs12->cr3_target_count >= 3 &&
8951 vmcs12->cr3_target_value2 == val) ||
8952 (vmcs12->cr3_target_count >= 4 &&
8953 vmcs12->cr3_target_value3 == val))
8955 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8959 if (vmcs12->cr4_guest_host_mask &
8960 (vmcs12->cr4_read_shadow ^ val))
8964 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8970 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8971 (vmcs12->cr0_read_shadow & X86_CR0_TS))
8974 case 1: /* mov from cr */
8977 if (vmcs12->cpu_based_vm_exec_control &
8978 CPU_BASED_CR3_STORE_EXITING)
8982 if (vmcs12->cpu_based_vm_exec_control &
8983 CPU_BASED_CR8_STORE_EXITING)
8990 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8991 * cr0. Other attempted changes are ignored, with no exit.
8993 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8994 if (vmcs12->cr0_guest_host_mask & 0xe &
8995 (val ^ vmcs12->cr0_read_shadow))
8997 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8998 !(vmcs12->cr0_read_shadow & 0x1) &&
9007 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
9008 * should handle it ourselves in L0 (and then continue L2). Only call this
9009 * when in is_guest_mode (L2).
9011 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
9013 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9014 struct vcpu_vmx *vmx = to_vmx(vcpu);
9015 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9017 if (vmx->nested.nested_run_pending)
9020 if (unlikely(vmx->fail)) {
9021 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
9022 vmcs_read32(VM_INSTRUCTION_ERROR));
9027 * The host physical addresses of some pages of guest memory
9028 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
9029 * Page). The CPU may write to these pages via their host
9030 * physical address while L2 is running, bypassing any
9031 * address-translation-based dirty tracking (e.g. EPT write
9034 * Mark them dirty on every exit from L2 to prevent them from
9035 * getting out of sync with dirty tracking.
9037 nested_mark_vmcs12_pages_dirty(vcpu);
9039 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
9040 vmcs_readl(EXIT_QUALIFICATION),
9041 vmx->idt_vectoring_info,
9043 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9046 switch (exit_reason) {
9047 case EXIT_REASON_EXCEPTION_NMI:
9048 if (is_nmi(intr_info))
9050 else if (is_page_fault(intr_info))
9051 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
9052 else if (is_no_device(intr_info) &&
9053 !(vmcs12->guest_cr0 & X86_CR0_TS))
9055 else if (is_debug(intr_info) &&
9057 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
9059 else if (is_breakpoint(intr_info) &&
9060 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
9062 return vmcs12->exception_bitmap &
9063 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
9064 case EXIT_REASON_EXTERNAL_INTERRUPT:
9066 case EXIT_REASON_TRIPLE_FAULT:
9068 case EXIT_REASON_PENDING_INTERRUPT:
9069 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
9070 case EXIT_REASON_NMI_WINDOW:
9071 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
9072 case EXIT_REASON_TASK_SWITCH:
9074 case EXIT_REASON_CPUID:
9076 case EXIT_REASON_HLT:
9077 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
9078 case EXIT_REASON_INVD:
9080 case EXIT_REASON_INVLPG:
9081 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9082 case EXIT_REASON_RDPMC:
9083 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
9084 case EXIT_REASON_RDRAND:
9085 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
9086 case EXIT_REASON_RDSEED:
9087 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
9088 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
9089 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
9090 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
9091 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
9092 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
9093 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
9094 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
9095 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
9097 * VMX instructions trap unconditionally. This allows L1 to
9098 * emulate them for its L2 guest, i.e., allows 3-level nesting!
9101 case EXIT_REASON_CR_ACCESS:
9102 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
9103 case EXIT_REASON_DR_ACCESS:
9104 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
9105 case EXIT_REASON_IO_INSTRUCTION:
9106 return nested_vmx_exit_handled_io(vcpu, vmcs12);
9107 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
9108 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
9109 case EXIT_REASON_MSR_READ:
9110 case EXIT_REASON_MSR_WRITE:
9111 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
9112 case EXIT_REASON_INVALID_STATE:
9114 case EXIT_REASON_MWAIT_INSTRUCTION:
9115 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
9116 case EXIT_REASON_MONITOR_TRAP_FLAG:
9117 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
9118 case EXIT_REASON_MONITOR_INSTRUCTION:
9119 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
9120 case EXIT_REASON_PAUSE_INSTRUCTION:
9121 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
9122 nested_cpu_has2(vmcs12,
9123 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
9124 case EXIT_REASON_MCE_DURING_VMENTRY:
9126 case EXIT_REASON_TPR_BELOW_THRESHOLD:
9127 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
9128 case EXIT_REASON_APIC_ACCESS:
9129 case EXIT_REASON_APIC_WRITE:
9130 case EXIT_REASON_EOI_INDUCED:
9132 * The controls for "virtualize APIC accesses," "APIC-
9133 * register virtualization," and "virtual-interrupt
9134 * delivery" only come from vmcs12.
9137 case EXIT_REASON_EPT_VIOLATION:
9139 * L0 always deals with the EPT violation. If nested EPT is
9140 * used, and the nested mmu code discovers that the address is
9141 * missing in the guest EPT table (EPT12), the EPT violation
9142 * will be injected with nested_ept_inject_page_fault()
9145 case EXIT_REASON_EPT_MISCONFIG:
9147 * L2 never uses directly L1's EPT, but rather L0's own EPT
9148 * table (shadow on EPT) or a merged EPT table that L0 built
9149 * (EPT on EPT). So any problems with the structure of the
9150 * table is L0's fault.
9153 case EXIT_REASON_INVPCID:
9155 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
9156 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9157 case EXIT_REASON_WBINVD:
9158 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
9159 case EXIT_REASON_XSETBV:
9161 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
9163 * This should never happen, since it is not possible to
9164 * set XSS to a non-zero value---neither in L1 nor in L2.
9165 * If if it were, XSS would have to be checked against
9166 * the XSS exit bitmap in vmcs12.
9168 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
9169 case EXIT_REASON_PREEMPTION_TIMER:
9171 case EXIT_REASON_PML_FULL:
9172 /* We emulate PML support to L1. */
9174 case EXIT_REASON_VMFUNC:
9175 /* VM functions are emulated through L2->L0 vmexits. */
9182 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
9184 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9187 * At this point, the exit interruption info in exit_intr_info
9188 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
9189 * we need to query the in-kernel LAPIC.
9191 WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
9192 if ((exit_intr_info &
9193 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9194 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
9195 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9196 vmcs12->vm_exit_intr_error_code =
9197 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9200 nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
9201 vmcs_readl(EXIT_QUALIFICATION));
9205 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
9207 *info1 = vmcs_readl(EXIT_QUALIFICATION);
9208 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
9211 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
9214 __free_page(vmx->pml_pg);
9219 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
9221 struct vcpu_vmx *vmx = to_vmx(vcpu);
9225 pml_idx = vmcs_read16(GUEST_PML_INDEX);
9227 /* Do nothing if PML buffer is empty */
9228 if (pml_idx == (PML_ENTITY_NUM - 1))
9231 /* PML index always points to next available PML buffer entity */
9232 if (pml_idx >= PML_ENTITY_NUM)
9237 pml_buf = page_address(vmx->pml_pg);
9238 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
9241 gpa = pml_buf[pml_idx];
9242 WARN_ON(gpa & (PAGE_SIZE - 1));
9243 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
9246 /* reset PML index */
9247 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
9251 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
9252 * Called before reporting dirty_bitmap to userspace.
9254 static void kvm_flush_pml_buffers(struct kvm *kvm)
9257 struct kvm_vcpu *vcpu;
9259 * We only need to kick vcpu out of guest mode here, as PML buffer
9260 * is flushed at beginning of all VMEXITs, and it's obvious that only
9261 * vcpus running in guest are possible to have unflushed GPAs in PML
9264 kvm_for_each_vcpu(i, vcpu, kvm)
9265 kvm_vcpu_kick(vcpu);
9268 static void vmx_dump_sel(char *name, uint32_t sel)
9270 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
9271 name, vmcs_read16(sel),
9272 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
9273 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
9274 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
9277 static void vmx_dump_dtsel(char *name, uint32_t limit)
9279 pr_err("%s limit=0x%08x, base=0x%016lx\n",
9280 name, vmcs_read32(limit),
9281 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
9284 static void dump_vmcs(void)
9286 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
9287 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
9288 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
9289 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
9290 u32 secondary_exec_control = 0;
9291 unsigned long cr4 = vmcs_readl(GUEST_CR4);
9292 u64 efer = vmcs_read64(GUEST_IA32_EFER);
9295 if (cpu_has_secondary_exec_ctrls())
9296 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9298 pr_err("*** Guest State ***\n");
9299 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9300 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
9301 vmcs_readl(CR0_GUEST_HOST_MASK));
9302 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9303 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
9304 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
9305 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
9306 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
9308 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
9309 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
9310 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
9311 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
9313 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
9314 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
9315 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
9316 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
9317 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9318 vmcs_readl(GUEST_SYSENTER_ESP),
9319 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
9320 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
9321 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
9322 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
9323 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
9324 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
9325 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
9326 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
9327 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
9328 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
9329 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
9330 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
9331 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
9332 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9333 efer, vmcs_read64(GUEST_IA32_PAT));
9334 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
9335 vmcs_read64(GUEST_IA32_DEBUGCTL),
9336 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
9337 if (cpu_has_load_perf_global_ctrl &&
9338 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
9339 pr_err("PerfGlobCtl = 0x%016llx\n",
9340 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
9341 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
9342 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
9343 pr_err("Interruptibility = %08x ActivityState = %08x\n",
9344 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
9345 vmcs_read32(GUEST_ACTIVITY_STATE));
9346 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
9347 pr_err("InterruptStatus = %04x\n",
9348 vmcs_read16(GUEST_INTR_STATUS));
9350 pr_err("*** Host State ***\n");
9351 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
9352 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
9353 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9354 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
9355 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
9356 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
9357 vmcs_read16(HOST_TR_SELECTOR));
9358 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9359 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
9360 vmcs_readl(HOST_TR_BASE));
9361 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9362 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
9363 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9364 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
9365 vmcs_readl(HOST_CR4));
9366 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9367 vmcs_readl(HOST_IA32_SYSENTER_ESP),
9368 vmcs_read32(HOST_IA32_SYSENTER_CS),
9369 vmcs_readl(HOST_IA32_SYSENTER_EIP));
9370 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
9371 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9372 vmcs_read64(HOST_IA32_EFER),
9373 vmcs_read64(HOST_IA32_PAT));
9374 if (cpu_has_load_perf_global_ctrl &&
9375 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9376 pr_err("PerfGlobCtl = 0x%016llx\n",
9377 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
9379 pr_err("*** Control State ***\n");
9380 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
9381 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
9382 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
9383 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
9384 vmcs_read32(EXCEPTION_BITMAP),
9385 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
9386 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
9387 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
9388 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9389 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
9390 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
9391 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
9392 vmcs_read32(VM_EXIT_INTR_INFO),
9393 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9394 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
9395 pr_err(" reason=%08x qualification=%016lx\n",
9396 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
9397 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
9398 vmcs_read32(IDT_VECTORING_INFO_FIELD),
9399 vmcs_read32(IDT_VECTORING_ERROR_CODE));
9400 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
9401 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
9402 pr_err("TSC Multiplier = 0x%016llx\n",
9403 vmcs_read64(TSC_MULTIPLIER));
9404 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
9405 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9406 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
9407 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
9408 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
9409 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
9410 n = vmcs_read32(CR3_TARGET_COUNT);
9411 for (i = 0; i + 1 < n; i += 4)
9412 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
9413 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
9414 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
9416 pr_err("CR3 target%u=%016lx\n",
9417 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
9418 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
9419 pr_err("PLE Gap=%08x Window=%08x\n",
9420 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
9421 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
9422 pr_err("Virtual processor ID = 0x%04x\n",
9423 vmcs_read16(VIRTUAL_PROCESSOR_ID));
9427 * The guest has exited. See if we can fix it or if we need userspace
9430 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
9432 struct vcpu_vmx *vmx = to_vmx(vcpu);
9433 u32 exit_reason = vmx->exit_reason;
9434 u32 vectoring_info = vmx->idt_vectoring_info;
9436 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
9439 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
9440 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
9441 * querying dirty_bitmap, we only need to kick all vcpus out of guest
9442 * mode as if vcpus is in root mode, the PML buffer must has been
9446 vmx_flush_pml_buffer(vcpu);
9448 /* If guest state is invalid, start emulating */
9449 if (vmx->emulation_required)
9450 return handle_invalid_guest_state(vcpu);
9452 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
9453 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9455 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
9457 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9458 vcpu->run->fail_entry.hardware_entry_failure_reason
9463 if (unlikely(vmx->fail)) {
9464 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9465 vcpu->run->fail_entry.hardware_entry_failure_reason
9466 = vmcs_read32(VM_INSTRUCTION_ERROR);
9472 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
9473 * delivery event since it indicates guest is accessing MMIO.
9474 * The vm-exit can be triggered again after return to guest that
9475 * will cause infinite loop.
9477 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
9478 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
9479 exit_reason != EXIT_REASON_EPT_VIOLATION &&
9480 exit_reason != EXIT_REASON_PML_FULL &&
9481 exit_reason != EXIT_REASON_TASK_SWITCH)) {
9482 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9483 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
9484 vcpu->run->internal.ndata = 3;
9485 vcpu->run->internal.data[0] = vectoring_info;
9486 vcpu->run->internal.data[1] = exit_reason;
9487 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
9488 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
9489 vcpu->run->internal.ndata++;
9490 vcpu->run->internal.data[3] =
9491 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9496 if (unlikely(!enable_vnmi &&
9497 vmx->loaded_vmcs->soft_vnmi_blocked)) {
9498 if (vmx_interrupt_allowed(vcpu)) {
9499 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9500 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
9501 vcpu->arch.nmi_pending) {
9503 * This CPU don't support us in finding the end of an
9504 * NMI-blocked window if the guest runs with IRQs
9505 * disabled. So we pull the trigger after 1 s of
9506 * futile waiting, but inform the user about this.
9508 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
9509 "state on VCPU %d after 1 s timeout\n",
9510 __func__, vcpu->vcpu_id);
9511 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9515 if (exit_reason < kvm_vmx_max_exit_handlers
9516 && kvm_vmx_exit_handlers[exit_reason])
9517 return kvm_vmx_exit_handlers[exit_reason](vcpu);
9519 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
9521 kvm_queue_exception(vcpu, UD_VECTOR);
9526 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
9528 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9530 if (is_guest_mode(vcpu) &&
9531 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9534 if (irr == -1 || tpr < irr) {
9535 vmcs_write32(TPR_THRESHOLD, 0);
9539 vmcs_write32(TPR_THRESHOLD, irr);
9542 static void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
9544 u32 sec_exec_control;
9546 if (!lapic_in_kernel(vcpu))
9549 /* Postpone execution until vmcs01 is the current VMCS. */
9550 if (is_guest_mode(vcpu)) {
9551 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
9555 if (!cpu_need_tpr_shadow(vcpu))
9558 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9559 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9560 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
9562 switch (kvm_get_apic_mode(vcpu)) {
9563 case LAPIC_MODE_INVALID:
9564 WARN_ONCE(true, "Invalid local APIC state");
9565 case LAPIC_MODE_DISABLED:
9567 case LAPIC_MODE_XAPIC:
9568 if (flexpriority_enabled) {
9570 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9571 vmx_flush_tlb(vcpu, true);
9574 case LAPIC_MODE_X2APIC:
9575 if (cpu_has_vmx_virtualize_x2apic_mode())
9577 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9580 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
9582 vmx_update_msr_bitmap(vcpu);
9585 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
9587 if (!is_guest_mode(vcpu)) {
9588 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9589 vmx_flush_tlb(vcpu, true);
9593 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
9601 status = vmcs_read16(GUEST_INTR_STATUS);
9603 if (max_isr != old) {
9605 status |= max_isr << 8;
9606 vmcs_write16(GUEST_INTR_STATUS, status);
9610 static void vmx_set_rvi(int vector)
9618 status = vmcs_read16(GUEST_INTR_STATUS);
9619 old = (u8)status & 0xff;
9620 if ((u8)vector != old) {
9622 status |= (u8)vector;
9623 vmcs_write16(GUEST_INTR_STATUS, status);
9627 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
9630 * When running L2, updating RVI is only relevant when
9631 * vmcs12 virtual-interrupt-delivery enabled.
9632 * However, it can be enabled only when L1 also
9633 * intercepts external-interrupts and in that case
9634 * we should not update vmcs02 RVI but instead intercept
9635 * interrupt. Therefore, do nothing when running L2.
9637 if (!is_guest_mode(vcpu))
9638 vmx_set_rvi(max_irr);
9641 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
9643 struct vcpu_vmx *vmx = to_vmx(vcpu);
9645 bool max_irr_updated;
9647 WARN_ON(!vcpu->arch.apicv_active);
9648 if (pi_test_on(&vmx->pi_desc)) {
9649 pi_clear_on(&vmx->pi_desc);
9651 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9652 * But on x86 this is just a compiler barrier anyway.
9654 smp_mb__after_atomic();
9656 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
9659 * If we are running L2 and L1 has a new pending interrupt
9660 * which can be injected, we should re-evaluate
9661 * what should be done with this new L1 interrupt.
9662 * If L1 intercepts external-interrupts, we should
9663 * exit from L2 to L1. Otherwise, interrupt should be
9664 * delivered directly to L2.
9666 if (is_guest_mode(vcpu) && max_irr_updated) {
9667 if (nested_exit_on_intr(vcpu))
9668 kvm_vcpu_exiting_guest_mode(vcpu);
9670 kvm_make_request(KVM_REQ_EVENT, vcpu);
9673 max_irr = kvm_lapic_find_highest_irr(vcpu);
9675 vmx_hwapic_irr_update(vcpu, max_irr);
9679 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
9681 if (!kvm_vcpu_apicv_active(vcpu))
9684 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9685 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9686 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9687 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9690 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9692 struct vcpu_vmx *vmx = to_vmx(vcpu);
9694 pi_clear_on(&vmx->pi_desc);
9695 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9698 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9700 u32 exit_intr_info = 0;
9701 u16 basic_exit_reason = (u16)vmx->exit_reason;
9703 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9704 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9707 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9708 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9709 vmx->exit_intr_info = exit_intr_info;
9711 /* if exit due to PF check for async PF */
9712 if (is_page_fault(exit_intr_info))
9713 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9715 /* Handle machine checks before interrupts are enabled */
9716 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9717 is_machine_check(exit_intr_info))
9718 kvm_machine_check();
9720 /* We need to handle NMIs before interrupts are enabled */
9721 if (is_nmi(exit_intr_info)) {
9722 kvm_before_interrupt(&vmx->vcpu);
9724 kvm_after_interrupt(&vmx->vcpu);
9728 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9730 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9732 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9733 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9734 unsigned int vector;
9735 unsigned long entry;
9737 struct vcpu_vmx *vmx = to_vmx(vcpu);
9738 #ifdef CONFIG_X86_64
9742 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9743 desc = (gate_desc *)vmx->host_idt_base + vector;
9744 entry = gate_offset(desc);
9746 #ifdef CONFIG_X86_64
9747 "mov %%" _ASM_SP ", %[sp]\n\t"
9748 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9753 __ASM_SIZE(push) " $%c[cs]\n\t"
9756 #ifdef CONFIG_X86_64
9761 THUNK_TARGET(entry),
9762 [ss]"i"(__KERNEL_DS),
9763 [cs]"i"(__KERNEL_CS)
9767 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9769 static bool vmx_has_emulated_msr(int index)
9772 case MSR_IA32_SMBASE:
9774 * We cannot do SMM unless we can run the guest in big
9777 return enable_unrestricted_guest || emulate_invalid_guest_state;
9778 case MSR_AMD64_VIRT_SPEC_CTRL:
9779 /* This is AMD only. */
9786 static bool vmx_mpx_supported(void)
9788 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9789 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9792 static bool vmx_xsaves_supported(void)
9794 return vmcs_config.cpu_based_2nd_exec_ctrl &
9795 SECONDARY_EXEC_XSAVES;
9798 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9803 bool idtv_info_valid;
9805 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9808 if (vmx->loaded_vmcs->nmi_known_unmasked)
9811 * Can't use vmx->exit_intr_info since we're not sure what
9812 * the exit reason is.
9814 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9815 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9816 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9818 * SDM 3: 27.7.1.2 (September 2008)
9819 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9820 * a guest IRET fault.
9821 * SDM 3: 23.2.2 (September 2008)
9822 * Bit 12 is undefined in any of the following cases:
9823 * If the VM exit sets the valid bit in the IDT-vectoring
9824 * information field.
9825 * If the VM exit is due to a double fault.
9827 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9828 vector != DF_VECTOR && !idtv_info_valid)
9829 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9830 GUEST_INTR_STATE_NMI);
9832 vmx->loaded_vmcs->nmi_known_unmasked =
9833 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9834 & GUEST_INTR_STATE_NMI);
9835 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
9836 vmx->loaded_vmcs->vnmi_blocked_time +=
9837 ktime_to_ns(ktime_sub(ktime_get(),
9838 vmx->loaded_vmcs->entry_time));
9841 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9842 u32 idt_vectoring_info,
9843 int instr_len_field,
9844 int error_code_field)
9848 bool idtv_info_valid;
9850 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9852 vcpu->arch.nmi_injected = false;
9853 kvm_clear_exception_queue(vcpu);
9854 kvm_clear_interrupt_queue(vcpu);
9856 if (!idtv_info_valid)
9859 kvm_make_request(KVM_REQ_EVENT, vcpu);
9861 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9862 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9865 case INTR_TYPE_NMI_INTR:
9866 vcpu->arch.nmi_injected = true;
9868 * SDM 3: 27.7.1.2 (September 2008)
9869 * Clear bit "block by NMI" before VM entry if a NMI
9872 vmx_set_nmi_mask(vcpu, false);
9874 case INTR_TYPE_SOFT_EXCEPTION:
9875 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9877 case INTR_TYPE_HARD_EXCEPTION:
9878 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9879 u32 err = vmcs_read32(error_code_field);
9880 kvm_requeue_exception_e(vcpu, vector, err);
9882 kvm_requeue_exception(vcpu, vector);
9884 case INTR_TYPE_SOFT_INTR:
9885 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9887 case INTR_TYPE_EXT_INTR:
9888 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9895 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9897 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9898 VM_EXIT_INSTRUCTION_LEN,
9899 IDT_VECTORING_ERROR_CODE);
9902 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9904 __vmx_complete_interrupts(vcpu,
9905 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9906 VM_ENTRY_INSTRUCTION_LEN,
9907 VM_ENTRY_EXCEPTION_ERROR_CODE);
9909 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9912 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9915 struct perf_guest_switch_msr *msrs;
9917 msrs = perf_guest_get_msrs(&nr_msrs);
9922 for (i = 0; i < nr_msrs; i++)
9923 if (msrs[i].host == msrs[i].guest)
9924 clear_atomic_switch_msr(vmx, msrs[i].msr);
9926 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9930 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9932 struct vcpu_vmx *vmx = to_vmx(vcpu);
9936 if (vmx->hv_deadline_tsc == -1)
9940 if (vmx->hv_deadline_tsc > tscl)
9941 /* sure to be 32 bit only because checked on set_hv_timer */
9942 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9943 cpu_preemption_timer_multi);
9947 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9950 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9952 struct vcpu_vmx *vmx = to_vmx(vcpu);
9953 unsigned long cr3, cr4, evmcs_rsp;
9955 /* Record the guest's net vcpu time for enforced NMI injections. */
9956 if (unlikely(!enable_vnmi &&
9957 vmx->loaded_vmcs->soft_vnmi_blocked))
9958 vmx->loaded_vmcs->entry_time = ktime_get();
9960 /* Don't enter VMX if guest state is invalid, let the exit handler
9961 start emulation until we arrive back to a valid state */
9962 if (vmx->emulation_required)
9965 if (vmx->ple_window_dirty) {
9966 vmx->ple_window_dirty = false;
9967 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9970 if (vmx->nested.sync_shadow_vmcs) {
9971 copy_vmcs12_to_shadow(vmx);
9972 vmx->nested.sync_shadow_vmcs = false;
9975 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9976 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9977 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9978 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9980 cr3 = __get_current_cr3_fast();
9981 if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9982 vmcs_writel(HOST_CR3, cr3);
9983 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9986 cr4 = cr4_read_shadow();
9987 if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9988 vmcs_writel(HOST_CR4, cr4);
9989 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9992 /* When single-stepping over STI and MOV SS, we must clear the
9993 * corresponding interruptibility bits in the guest state. Otherwise
9994 * vmentry fails as it then expects bit 14 (BS) in pending debug
9995 * exceptions being set, but that's not correct for the guest debugging
9997 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9998 vmx_set_interrupt_shadow(vcpu, 0);
10000 if (static_cpu_has(X86_FEATURE_PKU) &&
10001 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
10002 vcpu->arch.pkru != vmx->host_pkru)
10003 __write_pkru(vcpu->arch.pkru);
10005 atomic_switch_perf_msrs(vmx);
10007 vmx_arm_hv_timer(vcpu);
10010 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
10011 * it's non-zero. Since vmentry is serialising on affected CPUs, there
10012 * is no need to worry about the conditional branch over the wrmsr
10013 * being speculatively taken.
10015 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
10017 vmx->__launched = vmx->loaded_vmcs->launched;
10019 evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
10020 (unsigned long)¤t_evmcs->host_rsp : 0;
10023 /* Store host registers */
10024 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
10025 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
10026 "push %%" _ASM_CX " \n\t"
10027 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10029 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10030 /* Avoid VMWRITE when Enlightened VMCS is in use */
10031 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
10033 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
10036 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
10038 /* Reload cr2 if changed */
10039 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
10040 "mov %%cr2, %%" _ASM_DX " \n\t"
10041 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
10043 "mov %%" _ASM_AX", %%cr2 \n\t"
10045 /* Check if vmlaunch of vmresume is needed */
10046 "cmpl $0, %c[launched](%0) \n\t"
10047 /* Load guest registers. Don't clobber flags. */
10048 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
10049 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
10050 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
10051 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
10052 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
10053 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
10054 #ifdef CONFIG_X86_64
10055 "mov %c[r8](%0), %%r8 \n\t"
10056 "mov %c[r9](%0), %%r9 \n\t"
10057 "mov %c[r10](%0), %%r10 \n\t"
10058 "mov %c[r11](%0), %%r11 \n\t"
10059 "mov %c[r12](%0), %%r12 \n\t"
10060 "mov %c[r13](%0), %%r13 \n\t"
10061 "mov %c[r14](%0), %%r14 \n\t"
10062 "mov %c[r15](%0), %%r15 \n\t"
10064 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
10066 /* Enter guest mode */
10068 __ex(ASM_VMX_VMLAUNCH) "\n\t"
10070 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
10072 /* Save guest registers, load host registers, keep flags */
10073 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
10075 "setbe %c[fail](%0)\n\t"
10076 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
10077 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
10078 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
10079 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
10080 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
10081 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
10082 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
10083 #ifdef CONFIG_X86_64
10084 "mov %%r8, %c[r8](%0) \n\t"
10085 "mov %%r9, %c[r9](%0) \n\t"
10086 "mov %%r10, %c[r10](%0) \n\t"
10087 "mov %%r11, %c[r11](%0) \n\t"
10088 "mov %%r12, %c[r12](%0) \n\t"
10089 "mov %%r13, %c[r13](%0) \n\t"
10090 "mov %%r14, %c[r14](%0) \n\t"
10091 "mov %%r15, %c[r15](%0) \n\t"
10092 "xor %%r8d, %%r8d \n\t"
10093 "xor %%r9d, %%r9d \n\t"
10094 "xor %%r10d, %%r10d \n\t"
10095 "xor %%r11d, %%r11d \n\t"
10096 "xor %%r12d, %%r12d \n\t"
10097 "xor %%r13d, %%r13d \n\t"
10098 "xor %%r14d, %%r14d \n\t"
10099 "xor %%r15d, %%r15d \n\t"
10101 "mov %%cr2, %%" _ASM_AX " \n\t"
10102 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
10104 "xor %%eax, %%eax \n\t"
10105 "xor %%ebx, %%ebx \n\t"
10106 "xor %%esi, %%esi \n\t"
10107 "xor %%edi, %%edi \n\t"
10108 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
10109 ".pushsection .rodata \n\t"
10110 ".global vmx_return \n\t"
10111 "vmx_return: " _ASM_PTR " 2b \n\t"
10113 : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
10114 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
10115 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
10116 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
10117 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
10118 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
10119 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
10120 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
10121 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
10122 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
10123 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
10124 #ifdef CONFIG_X86_64
10125 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
10126 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
10127 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
10128 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
10129 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
10130 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
10131 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
10132 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
10134 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
10135 [wordsize]"i"(sizeof(ulong))
10137 #ifdef CONFIG_X86_64
10138 , "rax", "rbx", "rdi"
10139 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
10141 , "eax", "ebx", "edi"
10146 * We do not use IBRS in the kernel. If this vCPU has used the
10147 * SPEC_CTRL MSR it may have left it on; save the value and
10148 * turn it off. This is much more efficient than blindly adding
10149 * it to the atomic save/restore list. Especially as the former
10150 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
10152 * For non-nested case:
10153 * If the L01 MSR bitmap does not intercept the MSR, then we need to
10157 * If the L02 MSR bitmap does not intercept the MSR, then we need to
10160 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
10161 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
10163 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
10165 /* Eliminate branch target predictions from guest mode */
10168 /* All fields are clean at this point */
10169 if (static_branch_unlikely(&enable_evmcs))
10170 current_evmcs->hv_clean_fields |=
10171 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
10173 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
10174 if (vmx->host_debugctlmsr)
10175 update_debugctlmsr(vmx->host_debugctlmsr);
10177 #ifndef CONFIG_X86_64
10179 * The sysexit path does not restore ds/es, so we must set them to
10180 * a reasonable value ourselves.
10182 * We can't defer this to vmx_load_host_state() since that function
10183 * may be executed in interrupt context, which saves and restore segments
10184 * around it, nullifying its effect.
10186 loadsegment(ds, __USER_DS);
10187 loadsegment(es, __USER_DS);
10190 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
10191 | (1 << VCPU_EXREG_RFLAGS)
10192 | (1 << VCPU_EXREG_PDPTR)
10193 | (1 << VCPU_EXREG_SEGMENTS)
10194 | (1 << VCPU_EXREG_CR3));
10195 vcpu->arch.regs_dirty = 0;
10198 * eager fpu is enabled if PKEY is supported and CR4 is switched
10199 * back on host, so it is safe to read guest PKRU from current
10202 if (static_cpu_has(X86_FEATURE_PKU) &&
10203 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
10204 vcpu->arch.pkru = __read_pkru();
10205 if (vcpu->arch.pkru != vmx->host_pkru)
10206 __write_pkru(vmx->host_pkru);
10209 vmx->nested.nested_run_pending = 0;
10210 vmx->idt_vectoring_info = 0;
10212 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
10213 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10216 vmx->loaded_vmcs->launched = 1;
10217 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
10219 vmx_complete_atomic_exit(vmx);
10220 vmx_recover_nmi_blocking(vmx);
10221 vmx_complete_interrupts(vmx);
10223 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
10225 static struct kvm *vmx_vm_alloc(void)
10227 struct kvm_vmx *kvm_vmx = vzalloc(sizeof(struct kvm_vmx));
10228 return &kvm_vmx->kvm;
10231 static void vmx_vm_free(struct kvm *kvm)
10233 vfree(to_kvm_vmx(kvm));
10236 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
10238 struct vcpu_vmx *vmx = to_vmx(vcpu);
10241 if (vmx->loaded_vmcs == vmcs)
10245 vmx->loaded_vmcs = vmcs;
10246 vmx_vcpu_put(vcpu);
10247 vmx_vcpu_load(vcpu, cpu);
10252 * Ensure that the current vmcs of the logical processor is the
10253 * vmcs01 of the vcpu before calling free_nested().
10255 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
10257 struct vcpu_vmx *vmx = to_vmx(vcpu);
10260 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10265 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
10267 struct vcpu_vmx *vmx = to_vmx(vcpu);
10270 vmx_destroy_pml_buffer(vmx);
10271 free_vpid(vmx->vpid);
10272 leave_guest_mode(vcpu);
10273 vmx_free_vcpu_nested(vcpu);
10274 free_loaded_vmcs(vmx->loaded_vmcs);
10275 kfree(vmx->guest_msrs);
10276 kvm_vcpu_uninit(vcpu);
10277 kmem_cache_free(kvm_vcpu_cache, vmx);
10280 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
10283 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
10284 unsigned long *msr_bitmap;
10288 return ERR_PTR(-ENOMEM);
10290 vmx->vpid = allocate_vpid();
10292 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
10299 * If PML is turned on, failure on enabling PML just results in failure
10300 * of creating the vcpu, therefore we can simplify PML logic (by
10301 * avoiding dealing with cases, such as enabling PML partially on vcpus
10302 * for the guest, etc.
10305 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
10310 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
10311 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
10314 if (!vmx->guest_msrs)
10317 err = alloc_loaded_vmcs(&vmx->vmcs01);
10321 msr_bitmap = vmx->vmcs01.msr_bitmap;
10322 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
10323 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
10324 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
10325 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
10326 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
10327 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
10328 vmx->msr_bitmap_mode = 0;
10330 vmx->loaded_vmcs = &vmx->vmcs01;
10332 vmx_vcpu_load(&vmx->vcpu, cpu);
10333 vmx->vcpu.cpu = cpu;
10334 vmx_vcpu_setup(vmx);
10335 vmx_vcpu_put(&vmx->vcpu);
10337 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10338 err = alloc_apic_access_page(kvm);
10343 if (enable_ept && !enable_unrestricted_guest) {
10344 err = init_rmode_identity_map(kvm);
10350 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
10351 kvm_vcpu_apicv_active(&vmx->vcpu));
10352 vmx->nested.vpid02 = allocate_vpid();
10355 vmx->nested.posted_intr_nv = -1;
10356 vmx->nested.current_vmptr = -1ull;
10358 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
10361 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
10362 * or POSTED_INTR_WAKEUP_VECTOR.
10364 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
10365 vmx->pi_desc.sn = 1;
10370 free_vpid(vmx->nested.vpid02);
10371 free_loaded_vmcs(vmx->loaded_vmcs);
10373 kfree(vmx->guest_msrs);
10375 vmx_destroy_pml_buffer(vmx);
10377 kvm_vcpu_uninit(&vmx->vcpu);
10379 free_vpid(vmx->vpid);
10380 kmem_cache_free(kvm_vcpu_cache, vmx);
10381 return ERR_PTR(err);
10384 static int vmx_vm_init(struct kvm *kvm)
10387 kvm->arch.pause_in_guest = true;
10391 static void __init vmx_check_processor_compat(void *rtn)
10393 struct vmcs_config vmcs_conf;
10396 if (setup_vmcs_config(&vmcs_conf) < 0)
10397 *(int *)rtn = -EIO;
10398 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, enable_apicv);
10399 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
10400 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
10401 smp_processor_id());
10402 *(int *)rtn = -EIO;
10406 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
10411 /* For VT-d and EPT combination
10412 * 1. MMIO: always map as UC
10413 * 2. EPT with VT-d:
10414 * a. VT-d without snooping control feature: can't guarantee the
10415 * result, try to trust guest.
10416 * b. VT-d with snooping control feature: snooping control feature of
10417 * VT-d engine can guarantee the cache correctness. Just set it
10418 * to WB to keep consistent with host. So the same as item 3.
10419 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
10420 * consistent with host MTRR
10423 cache = MTRR_TYPE_UNCACHABLE;
10427 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
10428 ipat = VMX_EPT_IPAT_BIT;
10429 cache = MTRR_TYPE_WRBACK;
10433 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
10434 ipat = VMX_EPT_IPAT_BIT;
10435 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
10436 cache = MTRR_TYPE_WRBACK;
10438 cache = MTRR_TYPE_UNCACHABLE;
10442 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
10445 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
10448 static int vmx_get_lpage_level(void)
10450 if (enable_ept && !cpu_has_vmx_ept_1g_page())
10451 return PT_DIRECTORY_LEVEL;
10453 /* For shadow and EPT supported 1GB page */
10454 return PT_PDPE_LEVEL;
10457 static void vmcs_set_secondary_exec_control(u32 new_ctl)
10460 * These bits in the secondary execution controls field
10461 * are dynamic, the others are mostly based on the hypervisor
10462 * architecture and the guest's CPUID. Do not touch the
10466 SECONDARY_EXEC_SHADOW_VMCS |
10467 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
10468 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10469 SECONDARY_EXEC_DESC;
10471 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
10473 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
10474 (new_ctl & ~mask) | (cur_ctl & mask));
10478 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
10479 * (indicating "allowed-1") if they are supported in the guest's CPUID.
10481 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
10483 struct vcpu_vmx *vmx = to_vmx(vcpu);
10484 struct kvm_cpuid_entry2 *entry;
10486 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
10487 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
10489 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
10490 if (entry && (entry->_reg & (_cpuid_mask))) \
10491 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
10494 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
10495 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
10496 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
10497 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
10498 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
10499 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
10500 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
10501 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
10502 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
10503 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
10504 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
10505 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
10506 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
10507 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
10508 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
10510 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
10511 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
10512 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
10513 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
10514 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
10515 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
10517 #undef cr4_fixed1_update
10520 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
10522 struct vcpu_vmx *vmx = to_vmx(vcpu);
10524 if (cpu_has_secondary_exec_ctrls()) {
10525 vmx_compute_secondary_exec_control(vmx);
10526 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
10529 if (nested_vmx_allowed(vcpu))
10530 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
10531 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10533 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
10534 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10536 if (nested_vmx_allowed(vcpu))
10537 nested_vmx_cr_fixed1_bits_update(vcpu);
10540 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
10542 if (func == 1 && nested)
10543 entry->ecx |= bit(X86_FEATURE_VMX);
10546 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
10547 struct x86_exception *fault)
10549 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10550 struct vcpu_vmx *vmx = to_vmx(vcpu);
10552 unsigned long exit_qualification = vcpu->arch.exit_qualification;
10554 if (vmx->nested.pml_full) {
10555 exit_reason = EXIT_REASON_PML_FULL;
10556 vmx->nested.pml_full = false;
10557 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
10558 } else if (fault->error_code & PFERR_RSVD_MASK)
10559 exit_reason = EXIT_REASON_EPT_MISCONFIG;
10561 exit_reason = EXIT_REASON_EPT_VIOLATION;
10563 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
10564 vmcs12->guest_physical_address = fault->address;
10567 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
10569 return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
10572 /* Callbacks for nested_ept_init_mmu_context: */
10574 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
10576 /* return the page table to be shadowed - in our case, EPT12 */
10577 return get_vmcs12(vcpu)->ept_pointer;
10580 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
10582 WARN_ON(mmu_is_nested(vcpu));
10583 if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
10586 kvm_mmu_unload(vcpu);
10587 kvm_init_shadow_ept_mmu(vcpu,
10588 to_vmx(vcpu)->nested.msrs.ept_caps &
10589 VMX_EPT_EXECUTE_ONLY_BIT,
10590 nested_ept_ad_enabled(vcpu));
10591 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
10592 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
10593 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
10595 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
10599 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
10601 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
10604 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
10607 bool inequality, bit;
10609 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
10611 (error_code & vmcs12->page_fault_error_code_mask) !=
10612 vmcs12->page_fault_error_code_match;
10613 return inequality ^ bit;
10616 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
10617 struct x86_exception *fault)
10619 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10621 WARN_ON(!is_guest_mode(vcpu));
10623 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
10624 !to_vmx(vcpu)->nested.nested_run_pending) {
10625 vmcs12->vm_exit_intr_error_code = fault->error_code;
10626 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10627 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
10628 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
10631 kvm_inject_page_fault(vcpu, fault);
10635 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10636 struct vmcs12 *vmcs12);
10638 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
10639 struct vmcs12 *vmcs12)
10641 struct vcpu_vmx *vmx = to_vmx(vcpu);
10645 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10647 * Translate L1 physical address to host physical
10648 * address for vmcs02. Keep the page pinned, so this
10649 * physical address remains valid. We keep a reference
10650 * to it so we can release it later.
10652 if (vmx->nested.apic_access_page) { /* shouldn't happen */
10653 kvm_release_page_dirty(vmx->nested.apic_access_page);
10654 vmx->nested.apic_access_page = NULL;
10656 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
10658 * If translation failed, no matter: This feature asks
10659 * to exit when accessing the given address, and if it
10660 * can never be accessed, this feature won't do
10663 if (!is_error_page(page)) {
10664 vmx->nested.apic_access_page = page;
10665 hpa = page_to_phys(vmx->nested.apic_access_page);
10666 vmcs_write64(APIC_ACCESS_ADDR, hpa);
10668 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
10669 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10673 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
10674 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
10675 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
10676 vmx->nested.virtual_apic_page = NULL;
10678 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
10681 * If translation failed, VM entry will fail because
10682 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10683 * Failing the vm entry is _not_ what the processor
10684 * does but it's basically the only possibility we
10685 * have. We could still enter the guest if CR8 load
10686 * exits are enabled, CR8 store exits are enabled, and
10687 * virtualize APIC access is disabled; in this case
10688 * the processor would never use the TPR shadow and we
10689 * could simply clear the bit from the execution
10690 * control. But such a configuration is useless, so
10691 * let's keep the code simple.
10693 if (!is_error_page(page)) {
10694 vmx->nested.virtual_apic_page = page;
10695 hpa = page_to_phys(vmx->nested.virtual_apic_page);
10696 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
10700 if (nested_cpu_has_posted_intr(vmcs12)) {
10701 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
10702 kunmap(vmx->nested.pi_desc_page);
10703 kvm_release_page_dirty(vmx->nested.pi_desc_page);
10704 vmx->nested.pi_desc_page = NULL;
10706 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
10707 if (is_error_page(page))
10709 vmx->nested.pi_desc_page = page;
10710 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
10711 vmx->nested.pi_desc =
10712 (struct pi_desc *)((void *)vmx->nested.pi_desc +
10713 (unsigned long)(vmcs12->posted_intr_desc_addr &
10715 vmcs_write64(POSTED_INTR_DESC_ADDR,
10716 page_to_phys(vmx->nested.pi_desc_page) +
10717 (unsigned long)(vmcs12->posted_intr_desc_addr &
10720 if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
10721 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
10722 CPU_BASED_USE_MSR_BITMAPS);
10724 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
10725 CPU_BASED_USE_MSR_BITMAPS);
10728 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
10730 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
10731 struct vcpu_vmx *vmx = to_vmx(vcpu);
10733 if (vcpu->arch.virtual_tsc_khz == 0)
10736 /* Make sure short timeouts reliably trigger an immediate vmexit.
10737 * hrtimer_start does not guarantee this. */
10738 if (preemption_timeout <= 1) {
10739 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
10743 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10744 preemption_timeout *= 1000000;
10745 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
10746 hrtimer_start(&vmx->nested.preemption_timer,
10747 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
10750 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
10751 struct vmcs12 *vmcs12)
10753 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
10756 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
10757 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
10763 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
10764 struct vmcs12 *vmcs12)
10766 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10769 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10775 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10776 struct vmcs12 *vmcs12)
10778 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10781 if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10788 * Merge L0's and L1's MSR bitmap, return false to indicate that
10789 * we do not use the hardware.
10791 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10792 struct vmcs12 *vmcs12)
10796 unsigned long *msr_bitmap_l1;
10797 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
10799 * pred_cmd & spec_ctrl are trying to verify two things:
10801 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10802 * ensures that we do not accidentally generate an L02 MSR bitmap
10803 * from the L12 MSR bitmap that is too permissive.
10804 * 2. That L1 or L2s have actually used the MSR. This avoids
10805 * unnecessarily merging of the bitmap if the MSR is unused. This
10806 * works properly because we only update the L01 MSR bitmap lazily.
10807 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10808 * updated to reflect this when L1 (or its L2s) actually write to
10811 bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
10812 bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
10814 /* Nothing to do if the MSR bitmap is not in use. */
10815 if (!cpu_has_vmx_msr_bitmap() ||
10816 !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10819 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10820 !pred_cmd && !spec_ctrl)
10823 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10824 if (is_error_page(page))
10827 msr_bitmap_l1 = (unsigned long *)kmap(page);
10828 if (nested_cpu_has_apic_reg_virt(vmcs12)) {
10830 * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
10831 * just lets the processor take the value from the virtual-APIC page;
10832 * take those 256 bits directly from the L1 bitmap.
10834 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10835 unsigned word = msr / BITS_PER_LONG;
10836 msr_bitmap_l0[word] = msr_bitmap_l1[word];
10837 msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10840 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10841 unsigned word = msr / BITS_PER_LONG;
10842 msr_bitmap_l0[word] = ~0;
10843 msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10847 nested_vmx_disable_intercept_for_msr(
10848 msr_bitmap_l1, msr_bitmap_l0,
10849 X2APIC_MSR(APIC_TASKPRI),
10852 if (nested_cpu_has_vid(vmcs12)) {
10853 nested_vmx_disable_intercept_for_msr(
10854 msr_bitmap_l1, msr_bitmap_l0,
10855 X2APIC_MSR(APIC_EOI),
10857 nested_vmx_disable_intercept_for_msr(
10858 msr_bitmap_l1, msr_bitmap_l0,
10859 X2APIC_MSR(APIC_SELF_IPI),
10864 nested_vmx_disable_intercept_for_msr(
10865 msr_bitmap_l1, msr_bitmap_l0,
10866 MSR_IA32_SPEC_CTRL,
10867 MSR_TYPE_R | MSR_TYPE_W);
10870 nested_vmx_disable_intercept_for_msr(
10871 msr_bitmap_l1, msr_bitmap_l0,
10876 kvm_release_page_clean(page);
10881 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
10882 struct vmcs12 *vmcs12)
10884 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
10885 !page_address_valid(vcpu, vmcs12->apic_access_addr))
10891 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10892 struct vmcs12 *vmcs12)
10894 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10895 !nested_cpu_has_apic_reg_virt(vmcs12) &&
10896 !nested_cpu_has_vid(vmcs12) &&
10897 !nested_cpu_has_posted_intr(vmcs12))
10901 * If virtualize x2apic mode is enabled,
10902 * virtualize apic access must be disabled.
10904 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10905 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10909 * If virtual interrupt delivery is enabled,
10910 * we must exit on external interrupts.
10912 if (nested_cpu_has_vid(vmcs12) &&
10913 !nested_exit_on_intr(vcpu))
10917 * bits 15:8 should be zero in posted_intr_nv,
10918 * the descriptor address has been already checked
10919 * in nested_get_vmcs12_pages.
10921 if (nested_cpu_has_posted_intr(vmcs12) &&
10922 (!nested_cpu_has_vid(vmcs12) ||
10923 !nested_exit_intr_ack_set(vcpu) ||
10924 vmcs12->posted_intr_nv & 0xff00))
10927 /* tpr shadow is needed by all apicv features. */
10928 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10934 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10935 unsigned long count_field,
10936 unsigned long addr_field)
10941 if (vmcs12_read_any(vcpu, count_field, &count) ||
10942 vmcs12_read_any(vcpu, addr_field, &addr)) {
10948 maxphyaddr = cpuid_maxphyaddr(vcpu);
10949 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10950 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10951 pr_debug_ratelimited(
10952 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10953 addr_field, maxphyaddr, count, addr);
10959 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10960 struct vmcs12 *vmcs12)
10962 if (vmcs12->vm_exit_msr_load_count == 0 &&
10963 vmcs12->vm_exit_msr_store_count == 0 &&
10964 vmcs12->vm_entry_msr_load_count == 0)
10965 return 0; /* Fast path */
10966 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10967 VM_EXIT_MSR_LOAD_ADDR) ||
10968 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10969 VM_EXIT_MSR_STORE_ADDR) ||
10970 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10971 VM_ENTRY_MSR_LOAD_ADDR))
10976 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10977 struct vmcs12 *vmcs12)
10979 u64 address = vmcs12->pml_address;
10980 int maxphyaddr = cpuid_maxphyaddr(vcpu);
10982 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10983 if (!nested_cpu_has_ept(vmcs12) ||
10984 !IS_ALIGNED(address, 4096) ||
10985 address >> maxphyaddr)
10992 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10993 struct vmx_msr_entry *e)
10995 /* x2APIC MSR accesses are not allowed */
10996 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10998 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10999 e->index == MSR_IA32_UCODE_REV)
11001 if (e->reserved != 0)
11006 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
11007 struct vmx_msr_entry *e)
11009 if (e->index == MSR_FS_BASE ||
11010 e->index == MSR_GS_BASE ||
11011 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
11012 nested_vmx_msr_check_common(vcpu, e))
11017 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
11018 struct vmx_msr_entry *e)
11020 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
11021 nested_vmx_msr_check_common(vcpu, e))
11027 * Load guest's/host's msr at nested entry/exit.
11028 * return 0 for success, entry index for failure.
11030 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11033 struct vmx_msr_entry e;
11034 struct msr_data msr;
11036 msr.host_initiated = false;
11037 for (i = 0; i < count; i++) {
11038 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
11040 pr_debug_ratelimited(
11041 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11042 __func__, i, gpa + i * sizeof(e));
11045 if (nested_vmx_load_msr_check(vcpu, &e)) {
11046 pr_debug_ratelimited(
11047 "%s check failed (%u, 0x%x, 0x%x)\n",
11048 __func__, i, e.index, e.reserved);
11051 msr.index = e.index;
11052 msr.data = e.value;
11053 if (kvm_set_msr(vcpu, &msr)) {
11054 pr_debug_ratelimited(
11055 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11056 __func__, i, e.index, e.value);
11065 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11068 struct vmx_msr_entry e;
11070 for (i = 0; i < count; i++) {
11071 struct msr_data msr_info;
11072 if (kvm_vcpu_read_guest(vcpu,
11073 gpa + i * sizeof(e),
11074 &e, 2 * sizeof(u32))) {
11075 pr_debug_ratelimited(
11076 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11077 __func__, i, gpa + i * sizeof(e));
11080 if (nested_vmx_store_msr_check(vcpu, &e)) {
11081 pr_debug_ratelimited(
11082 "%s check failed (%u, 0x%x, 0x%x)\n",
11083 __func__, i, e.index, e.reserved);
11086 msr_info.host_initiated = false;
11087 msr_info.index = e.index;
11088 if (kvm_get_msr(vcpu, &msr_info)) {
11089 pr_debug_ratelimited(
11090 "%s cannot read MSR (%u, 0x%x)\n",
11091 __func__, i, e.index);
11094 if (kvm_vcpu_write_guest(vcpu,
11095 gpa + i * sizeof(e) +
11096 offsetof(struct vmx_msr_entry, value),
11097 &msr_info.data, sizeof(msr_info.data))) {
11098 pr_debug_ratelimited(
11099 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11100 __func__, i, e.index, msr_info.data);
11107 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
11109 unsigned long invalid_mask;
11111 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
11112 return (val & invalid_mask) == 0;
11116 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
11117 * emulating VM entry into a guest with EPT enabled.
11118 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11119 * is assigned to entry_failure_code on failure.
11121 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
11122 u32 *entry_failure_code)
11124 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
11125 if (!nested_cr3_valid(vcpu, cr3)) {
11126 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11131 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
11132 * must not be dereferenced.
11134 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
11136 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
11137 *entry_failure_code = ENTRY_FAIL_PDPTE;
11142 vcpu->arch.cr3 = cr3;
11143 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
11146 kvm_mmu_reset_context(vcpu);
11150 static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11152 struct vcpu_vmx *vmx = to_vmx(vcpu);
11154 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
11155 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
11156 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
11157 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
11158 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
11159 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
11160 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
11161 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
11162 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
11163 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
11164 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
11165 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
11166 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
11167 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
11168 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
11169 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
11170 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
11171 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
11172 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
11173 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
11174 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
11175 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
11176 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
11177 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
11178 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
11179 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
11180 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
11181 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
11182 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
11183 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
11184 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
11186 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
11187 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
11188 vmcs12->guest_pending_dbg_exceptions);
11189 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
11190 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
11192 if (nested_cpu_has_xsaves(vmcs12))
11193 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
11194 vmcs_write64(VMCS_LINK_POINTER, -1ull);
11196 if (cpu_has_vmx_posted_intr())
11197 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
11200 * Whether page-faults are trapped is determined by a combination of
11201 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
11202 * If enable_ept, L0 doesn't care about page faults and we should
11203 * set all of these to L1's desires. However, if !enable_ept, L0 does
11204 * care about (at least some) page faults, and because it is not easy
11205 * (if at all possible?) to merge L0 and L1's desires, we simply ask
11206 * to exit on each and every L2 page fault. This is done by setting
11207 * MASK=MATCH=0 and (see below) EB.PF=1.
11208 * Note that below we don't need special code to set EB.PF beyond the
11209 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
11210 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
11211 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
11213 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
11214 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
11215 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
11216 enable_ept ? vmcs12->page_fault_error_code_match : 0);
11218 /* All VMFUNCs are currently emulated through L0 vmexits. */
11219 if (cpu_has_vmx_vmfunc())
11220 vmcs_write64(VM_FUNCTION_CONTROL, 0);
11222 if (cpu_has_vmx_apicv()) {
11223 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
11224 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
11225 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
11226 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
11230 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
11231 * Some constant fields are set here by vmx_set_constant_host_state().
11232 * Other fields are different per CPU, and will be set later when
11233 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
11235 vmx_set_constant_host_state(vmx);
11238 * Set the MSR load/store lists to match L0's settings.
11240 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
11241 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11242 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
11243 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11244 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
11246 set_cr4_guest_host_mask(vmx);
11248 if (vmx_mpx_supported())
11249 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
11252 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
11253 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
11255 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
11259 * L1 may access the L2's PDPTR, so save them to construct vmcs12
11262 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
11263 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
11264 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
11265 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
11268 if (cpu_has_vmx_msr_bitmap())
11269 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
11273 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
11274 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
11275 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
11276 * guest in a way that will both be appropriate to L1's requests, and our
11277 * needs. In addition to modifying the active vmcs (which is vmcs02), this
11278 * function also has additional necessary side-effects, like setting various
11279 * vcpu->arch fields.
11280 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11281 * is assigned to entry_failure_code on failure.
11283 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11284 u32 *entry_failure_code)
11286 struct vcpu_vmx *vmx = to_vmx(vcpu);
11287 u32 exec_control, vmcs12_exec_ctrl;
11289 if (vmx->nested.dirty_vmcs12) {
11290 prepare_vmcs02_full(vcpu, vmcs12);
11291 vmx->nested.dirty_vmcs12 = false;
11295 * First, the fields that are shadowed. This must be kept in sync
11296 * with vmx_shadow_fields.h.
11299 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
11300 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
11301 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
11302 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
11303 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
11306 * Not in vmcs02: GUEST_PML_INDEX, HOST_FS_SELECTOR, HOST_GS_SELECTOR,
11307 * HOST_FS_BASE, HOST_GS_BASE.
11310 if (vmx->nested.nested_run_pending &&
11311 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
11312 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
11313 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
11315 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
11316 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
11318 if (vmx->nested.nested_run_pending) {
11319 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
11320 vmcs12->vm_entry_intr_info_field);
11321 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
11322 vmcs12->vm_entry_exception_error_code);
11323 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
11324 vmcs12->vm_entry_instruction_len);
11325 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
11326 vmcs12->guest_interruptibility_info);
11327 vmx->loaded_vmcs->nmi_known_unmasked =
11328 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
11330 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
11332 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
11334 exec_control = vmcs12->pin_based_vm_exec_control;
11336 /* Preemption timer setting is only taken from vmcs01. */
11337 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11338 exec_control |= vmcs_config.pin_based_exec_ctrl;
11339 if (vmx->hv_deadline_tsc == -1)
11340 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11342 /* Posted interrupts setting is only taken from vmcs12. */
11343 if (nested_cpu_has_posted_intr(vmcs12)) {
11344 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
11345 vmx->nested.pi_pending = false;
11347 exec_control &= ~PIN_BASED_POSTED_INTR;
11350 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
11352 vmx->nested.preemption_timer_expired = false;
11353 if (nested_cpu_has_preemption_timer(vmcs12))
11354 vmx_start_preemption_timer(vcpu);
11356 if (cpu_has_secondary_exec_ctrls()) {
11357 exec_control = vmx->secondary_exec_control;
11359 /* Take the following fields only from vmcs12 */
11360 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
11361 SECONDARY_EXEC_ENABLE_INVPCID |
11362 SECONDARY_EXEC_RDTSCP |
11363 SECONDARY_EXEC_XSAVES |
11364 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
11365 SECONDARY_EXEC_APIC_REGISTER_VIRT |
11366 SECONDARY_EXEC_ENABLE_VMFUNC);
11367 if (nested_cpu_has(vmcs12,
11368 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
11369 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
11370 ~SECONDARY_EXEC_ENABLE_PML;
11371 exec_control |= vmcs12_exec_ctrl;
11374 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
11375 vmcs_write16(GUEST_INTR_STATUS,
11376 vmcs12->guest_intr_status);
11379 * Write an illegal value to APIC_ACCESS_ADDR. Later,
11380 * nested_get_vmcs12_pages will either fix it up or
11381 * remove the VM execution control.
11383 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
11384 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
11386 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
11390 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
11391 * entry, but only if the current (host) sp changed from the value
11392 * we wrote last (vmx->host_rsp). This cache is no longer relevant
11393 * if we switch vmcs, and rather than hold a separate cache per vmcs,
11394 * here we just force the write to happen on entry.
11398 exec_control = vmx_exec_control(vmx); /* L0's desires */
11399 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
11400 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
11401 exec_control &= ~CPU_BASED_TPR_SHADOW;
11402 exec_control |= vmcs12->cpu_based_vm_exec_control;
11405 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
11406 * nested_get_vmcs12_pages can't fix it up, the illegal value
11407 * will result in a VM entry failure.
11409 if (exec_control & CPU_BASED_TPR_SHADOW) {
11410 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
11411 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
11413 #ifdef CONFIG_X86_64
11414 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
11415 CPU_BASED_CR8_STORE_EXITING;
11420 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
11421 * for I/O port accesses.
11423 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
11424 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
11426 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
11428 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
11429 * bitwise-or of what L1 wants to trap for L2, and what we want to
11430 * trap. Note that CR0.TS also needs updating - we do this later.
11432 update_exception_bitmap(vcpu);
11433 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
11434 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
11436 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
11437 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
11438 * bits are further modified by vmx_set_efer() below.
11440 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
11442 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
11443 * emulated by vmx_set_efer(), below.
11445 vm_entry_controls_init(vmx,
11446 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
11447 ~VM_ENTRY_IA32E_MODE) |
11448 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
11450 if (vmx->nested.nested_run_pending &&
11451 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
11452 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
11453 vcpu->arch.pat = vmcs12->guest_ia32_pat;
11454 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
11455 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
11458 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11460 if (kvm_has_tsc_control)
11461 decache_tsc_multiplier(vmx);
11465 * There is no direct mapping between vpid02 and vpid12, the
11466 * vpid02 is per-vCPU for L0 and reused while the value of
11467 * vpid12 is changed w/ one invvpid during nested vmentry.
11468 * The vpid12 is allocated by L1 for L2, so it will not
11469 * influence global bitmap(for vpid01 and vpid02 allocation)
11470 * even if spawn a lot of nested vCPUs.
11472 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
11473 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
11474 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
11475 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
11478 vmx_flush_tlb(vcpu, true);
11484 * Conceptually we want to copy the PML address and index from
11485 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
11486 * since we always flush the log on each vmexit, this happens
11487 * to be equivalent to simply resetting the fields in vmcs02.
11489 ASSERT(vmx->pml_pg);
11490 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
11491 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
11494 if (nested_cpu_has_ept(vmcs12)) {
11495 if (nested_ept_init_mmu_context(vcpu)) {
11496 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11499 } else if (nested_cpu_has2(vmcs12,
11500 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11501 vmx_flush_tlb(vcpu, true);
11505 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
11506 * bits which we consider mandatory enabled.
11507 * The CR0_READ_SHADOW is what L2 should have expected to read given
11508 * the specifications by L1; It's not enough to take
11509 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
11510 * have more bits than L1 expected.
11512 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
11513 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
11515 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
11516 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
11518 if (vmx->nested.nested_run_pending &&
11519 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
11520 vcpu->arch.efer = vmcs12->guest_ia32_efer;
11521 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
11522 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11524 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11525 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
11526 vmx_set_efer(vcpu, vcpu->arch.efer);
11529 * Guest state is invalid and unrestricted guest is disabled,
11530 * which means L1 attempted VMEntry to L2 with invalid state.
11531 * Fail the VMEntry.
11533 if (vmx->emulation_required) {
11534 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11538 /* Shadow page tables on either EPT or shadow page tables. */
11539 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
11540 entry_failure_code))
11544 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
11546 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
11547 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
11551 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
11553 if (!nested_cpu_has_nmi_exiting(vmcs12) &&
11554 nested_cpu_has_virtual_nmis(vmcs12))
11557 if (!nested_cpu_has_virtual_nmis(vmcs12) &&
11558 nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING))
11564 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11566 struct vcpu_vmx *vmx = to_vmx(vcpu);
11568 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
11569 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
11570 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11572 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
11573 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11575 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
11576 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11578 if (nested_vmx_check_apic_access_controls(vcpu, vmcs12))
11579 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11581 if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
11582 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11584 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
11585 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11587 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
11588 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11590 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
11591 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11593 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
11594 vmx->nested.msrs.procbased_ctls_low,
11595 vmx->nested.msrs.procbased_ctls_high) ||
11596 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
11597 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
11598 vmx->nested.msrs.secondary_ctls_low,
11599 vmx->nested.msrs.secondary_ctls_high)) ||
11600 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
11601 vmx->nested.msrs.pinbased_ctls_low,
11602 vmx->nested.msrs.pinbased_ctls_high) ||
11603 !vmx_control_verify(vmcs12->vm_exit_controls,
11604 vmx->nested.msrs.exit_ctls_low,
11605 vmx->nested.msrs.exit_ctls_high) ||
11606 !vmx_control_verify(vmcs12->vm_entry_controls,
11607 vmx->nested.msrs.entry_ctls_low,
11608 vmx->nested.msrs.entry_ctls_high))
11609 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11611 if (nested_vmx_check_nmi_controls(vmcs12))
11612 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11614 if (nested_cpu_has_vmfunc(vmcs12)) {
11615 if (vmcs12->vm_function_control &
11616 ~vmx->nested.msrs.vmfunc_controls)
11617 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11619 if (nested_cpu_has_eptp_switching(vmcs12)) {
11620 if (!nested_cpu_has_ept(vmcs12) ||
11621 !page_address_valid(vcpu, vmcs12->eptp_list_address))
11622 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11626 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
11627 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11629 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
11630 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
11631 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
11632 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
11635 * From the Intel SDM, volume 3:
11636 * Fields relevant to VM-entry event injection must be set properly.
11637 * These fields are the VM-entry interruption-information field, the
11638 * VM-entry exception error code, and the VM-entry instruction length.
11640 if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) {
11641 u32 intr_info = vmcs12->vm_entry_intr_info_field;
11642 u8 vector = intr_info & INTR_INFO_VECTOR_MASK;
11643 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK;
11644 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK;
11645 bool should_have_error_code;
11646 bool urg = nested_cpu_has2(vmcs12,
11647 SECONDARY_EXEC_UNRESTRICTED_GUEST);
11648 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE;
11650 /* VM-entry interruption-info field: interruption type */
11651 if (intr_type == INTR_TYPE_RESERVED ||
11652 (intr_type == INTR_TYPE_OTHER_EVENT &&
11653 !nested_cpu_supports_monitor_trap_flag(vcpu)))
11654 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11656 /* VM-entry interruption-info field: vector */
11657 if ((intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) ||
11658 (intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) ||
11659 (intr_type == INTR_TYPE_OTHER_EVENT && vector != 0))
11660 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11662 /* VM-entry interruption-info field: deliver error code */
11663 should_have_error_code =
11664 intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode &&
11665 x86_exception_has_error_code(vector);
11666 if (has_error_code != should_have_error_code)
11667 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11669 /* VM-entry exception error code */
11670 if (has_error_code &&
11671 vmcs12->vm_entry_exception_error_code & GENMASK(31, 15))
11672 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11674 /* VM-entry interruption-info field: reserved bits */
11675 if (intr_info & INTR_INFO_RESVD_BITS_MASK)
11676 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11678 /* VM-entry instruction length */
11679 switch (intr_type) {
11680 case INTR_TYPE_SOFT_EXCEPTION:
11681 case INTR_TYPE_SOFT_INTR:
11682 case INTR_TYPE_PRIV_SW_EXCEPTION:
11683 if ((vmcs12->vm_entry_instruction_len > 15) ||
11684 (vmcs12->vm_entry_instruction_len == 0 &&
11685 !nested_cpu_has_zero_length_injection(vcpu)))
11686 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11693 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11698 *exit_qual = ENTRY_FAIL_DEFAULT;
11700 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
11701 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
11704 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
11705 vmcs12->vmcs_link_pointer != -1ull) {
11706 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
11711 * If the load IA32_EFER VM-entry control is 1, the following checks
11712 * are performed on the field for the IA32_EFER MSR:
11713 * - Bits reserved in the IA32_EFER MSR must be 0.
11714 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11715 * the IA-32e mode guest VM-exit control. It must also be identical
11716 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11719 if (to_vmx(vcpu)->nested.nested_run_pending &&
11720 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
11721 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
11722 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
11723 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
11724 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
11725 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
11730 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11731 * IA32_EFER MSR must be 0 in the field for that register. In addition,
11732 * the values of the LMA and LME bits in the field must each be that of
11733 * the host address-space size VM-exit control.
11735 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
11736 ia32e = (vmcs12->vm_exit_controls &
11737 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
11738 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
11739 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
11740 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
11744 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
11745 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
11746 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
11752 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu)
11754 struct vcpu_vmx *vmx = to_vmx(vcpu);
11755 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11760 enter_guest_mode(vcpu);
11762 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
11763 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11765 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
11766 vmx_segment_cache_clear(vmx);
11768 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11769 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
11771 r = EXIT_REASON_INVALID_STATE;
11772 if (prepare_vmcs02(vcpu, vmcs12, &exit_qual))
11775 nested_get_vmcs12_pages(vcpu, vmcs12);
11777 r = EXIT_REASON_MSR_LOAD_FAIL;
11778 msr_entry_idx = nested_vmx_load_msr(vcpu,
11779 vmcs12->vm_entry_msr_load_addr,
11780 vmcs12->vm_entry_msr_load_count);
11785 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11786 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11787 * returned as far as L1 is concerned. It will only return (and set
11788 * the success flag) when L2 exits (see nested_vmx_vmexit()).
11793 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11794 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
11795 leave_guest_mode(vcpu);
11796 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11797 nested_vmx_entry_failure(vcpu, vmcs12, r, exit_qual);
11802 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11803 * for running an L2 nested guest.
11805 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
11807 struct vmcs12 *vmcs12;
11808 struct vcpu_vmx *vmx = to_vmx(vcpu);
11809 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
11813 if (!nested_vmx_check_permission(vcpu))
11816 if (!nested_vmx_check_vmcs12(vcpu))
11819 vmcs12 = get_vmcs12(vcpu);
11821 if (enable_shadow_vmcs)
11822 copy_shadow_to_vmcs12(vmx);
11825 * The nested entry process starts with enforcing various prerequisites
11826 * on vmcs12 as required by the Intel SDM, and act appropriately when
11827 * they fail: As the SDM explains, some conditions should cause the
11828 * instruction to fail, while others will cause the instruction to seem
11829 * to succeed, but return an EXIT_REASON_INVALID_STATE.
11830 * To speed up the normal (success) code path, we should avoid checking
11831 * for misconfigurations which will anyway be caught by the processor
11832 * when using the merged vmcs02.
11834 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
11835 nested_vmx_failValid(vcpu,
11836 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
11840 if (vmcs12->launch_state == launch) {
11841 nested_vmx_failValid(vcpu,
11842 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11843 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
11847 ret = check_vmentry_prereqs(vcpu, vmcs12);
11849 nested_vmx_failValid(vcpu, ret);
11854 * After this point, the trap flag no longer triggers a singlestep trap
11855 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11856 * This is not 100% correct; for performance reasons, we delegate most
11857 * of the checks on host state to the processor. If those fail,
11858 * the singlestep trap is missed.
11860 skip_emulated_instruction(vcpu);
11862 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
11864 nested_vmx_entry_failure(vcpu, vmcs12,
11865 EXIT_REASON_INVALID_STATE, exit_qual);
11870 * We're finally done with prerequisite checking, and can start with
11871 * the nested entry.
11874 vmx->nested.nested_run_pending = 1;
11875 ret = enter_vmx_non_root_mode(vcpu);
11877 vmx->nested.nested_run_pending = 0;
11882 * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
11883 * by event injection, halt vcpu.
11885 if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
11886 !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK)) {
11887 vmx->nested.nested_run_pending = 0;
11888 return kvm_vcpu_halt(vcpu);
11893 return kvm_skip_emulated_instruction(vcpu);
11897 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11898 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11899 * This function returns the new value we should put in vmcs12.guest_cr0.
11900 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11901 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11902 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11903 * didn't trap the bit, because if L1 did, so would L0).
11904 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11905 * been modified by L2, and L1 knows it. So just leave the old value of
11906 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11907 * isn't relevant, because if L0 traps this bit it can set it to anything.
11908 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11909 * changed these bits, and therefore they need to be updated, but L0
11910 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11911 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11913 static inline unsigned long
11914 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11917 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
11918 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
11919 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
11920 vcpu->arch.cr0_guest_owned_bits));
11923 static inline unsigned long
11924 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11927 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
11928 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
11929 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
11930 vcpu->arch.cr4_guest_owned_bits));
11933 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
11934 struct vmcs12 *vmcs12)
11939 if (vcpu->arch.exception.injected) {
11940 nr = vcpu->arch.exception.nr;
11941 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11943 if (kvm_exception_is_soft(nr)) {
11944 vmcs12->vm_exit_instruction_len =
11945 vcpu->arch.event_exit_inst_len;
11946 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11948 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11950 if (vcpu->arch.exception.has_error_code) {
11951 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11952 vmcs12->idt_vectoring_error_code =
11953 vcpu->arch.exception.error_code;
11956 vmcs12->idt_vectoring_info_field = idt_vectoring;
11957 } else if (vcpu->arch.nmi_injected) {
11958 vmcs12->idt_vectoring_info_field =
11959 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11960 } else if (vcpu->arch.interrupt.injected) {
11961 nr = vcpu->arch.interrupt.nr;
11962 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11964 if (vcpu->arch.interrupt.soft) {
11965 idt_vectoring |= INTR_TYPE_SOFT_INTR;
11966 vmcs12->vm_entry_instruction_len =
11967 vcpu->arch.event_exit_inst_len;
11969 idt_vectoring |= INTR_TYPE_EXT_INTR;
11971 vmcs12->idt_vectoring_info_field = idt_vectoring;
11975 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
11977 struct vcpu_vmx *vmx = to_vmx(vcpu);
11978 unsigned long exit_qual;
11979 bool block_nested_events =
11980 vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
11982 if (vcpu->arch.exception.pending &&
11983 nested_vmx_check_exception(vcpu, &exit_qual)) {
11984 if (block_nested_events)
11986 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11990 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11991 vmx->nested.preemption_timer_expired) {
11992 if (block_nested_events)
11994 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11998 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11999 if (block_nested_events)
12001 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
12002 NMI_VECTOR | INTR_TYPE_NMI_INTR |
12003 INTR_INFO_VALID_MASK, 0);
12005 * The NMI-triggered VM exit counts as injection:
12006 * clear this one and block further NMIs.
12008 vcpu->arch.nmi_pending = 0;
12009 vmx_set_nmi_mask(vcpu, true);
12013 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
12014 nested_exit_on_intr(vcpu)) {
12015 if (block_nested_events)
12017 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
12021 vmx_complete_nested_posted_interrupt(vcpu);
12025 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
12027 ktime_t remaining =
12028 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
12031 if (ktime_to_ns(remaining) <= 0)
12034 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
12035 do_div(value, 1000000);
12036 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
12040 * Update the guest state fields of vmcs12 to reflect changes that
12041 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
12042 * VM-entry controls is also updated, since this is really a guest
12045 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12047 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
12048 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
12050 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
12051 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
12052 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
12054 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
12055 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
12056 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
12057 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
12058 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
12059 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
12060 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
12061 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
12062 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
12063 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
12064 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
12065 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
12066 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
12067 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
12068 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
12069 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
12070 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
12071 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
12072 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
12073 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
12074 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
12075 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
12076 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
12077 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
12078 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
12079 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
12080 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
12081 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
12082 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
12083 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
12084 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
12085 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
12086 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
12087 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
12088 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
12089 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
12091 vmcs12->guest_interruptibility_info =
12092 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
12093 vmcs12->guest_pending_dbg_exceptions =
12094 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
12095 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
12096 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
12098 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
12100 if (nested_cpu_has_preemption_timer(vmcs12)) {
12101 if (vmcs12->vm_exit_controls &
12102 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
12103 vmcs12->vmx_preemption_timer_value =
12104 vmx_get_preemption_timer_value(vcpu);
12105 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
12109 * In some cases (usually, nested EPT), L2 is allowed to change its
12110 * own CR3 without exiting. If it has changed it, we must keep it.
12111 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
12112 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
12114 * Additionally, restore L2's PDPTR to vmcs12.
12117 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
12118 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
12119 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
12120 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
12121 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
12124 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
12126 if (nested_cpu_has_vid(vmcs12))
12127 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
12129 vmcs12->vm_entry_controls =
12130 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
12131 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
12133 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
12134 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
12135 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
12138 /* TODO: These cannot have changed unless we have MSR bitmaps and
12139 * the relevant bit asks not to trap the change */
12140 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
12141 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
12142 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
12143 vmcs12->guest_ia32_efer = vcpu->arch.efer;
12144 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
12145 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
12146 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
12147 if (kvm_mpx_supported())
12148 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
12152 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
12153 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
12154 * and this function updates it to reflect the changes to the guest state while
12155 * L2 was running (and perhaps made some exits which were handled directly by L0
12156 * without going back to L1), and to reflect the exit reason.
12157 * Note that we do not have to copy here all VMCS fields, just those that
12158 * could have changed by the L2 guest or the exit - i.e., the guest-state and
12159 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
12160 * which already writes to vmcs12 directly.
12162 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12163 u32 exit_reason, u32 exit_intr_info,
12164 unsigned long exit_qualification)
12166 /* update guest state fields: */
12167 sync_vmcs12(vcpu, vmcs12);
12169 /* update exit information fields: */
12171 vmcs12->vm_exit_reason = exit_reason;
12172 vmcs12->exit_qualification = exit_qualification;
12173 vmcs12->vm_exit_intr_info = exit_intr_info;
12175 vmcs12->idt_vectoring_info_field = 0;
12176 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
12177 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
12179 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
12180 vmcs12->launch_state = 1;
12182 /* vm_entry_intr_info_field is cleared on exit. Emulate this
12183 * instead of reading the real value. */
12184 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
12187 * Transfer the event that L0 or L1 may wanted to inject into
12188 * L2 to IDT_VECTORING_INFO_FIELD.
12190 vmcs12_save_pending_event(vcpu, vmcs12);
12194 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
12195 * preserved above and would only end up incorrectly in L1.
12197 vcpu->arch.nmi_injected = false;
12198 kvm_clear_exception_queue(vcpu);
12199 kvm_clear_interrupt_queue(vcpu);
12202 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
12203 struct vmcs12 *vmcs12)
12205 u32 entry_failure_code;
12207 nested_ept_uninit_mmu_context(vcpu);
12210 * Only PDPTE load can fail as the value of cr3 was checked on entry and
12211 * couldn't have changed.
12213 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
12214 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
12217 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
12221 * A part of what we need to when the nested L2 guest exits and we want to
12222 * run its L1 parent, is to reset L1's guest state to the host state specified
12224 * This function is to be called not only on normal nested exit, but also on
12225 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
12226 * Failures During or After Loading Guest State").
12227 * This function should be called when the active VMCS is L1's (vmcs01).
12229 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
12230 struct vmcs12 *vmcs12)
12232 struct kvm_segment seg;
12234 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
12235 vcpu->arch.efer = vmcs12->host_ia32_efer;
12236 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
12237 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
12239 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
12240 vmx_set_efer(vcpu, vcpu->arch.efer);
12242 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
12243 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
12244 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
12246 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
12247 * actually changed, because vmx_set_cr0 refers to efer set above.
12249 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
12250 * (KVM doesn't change it);
12252 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
12253 vmx_set_cr0(vcpu, vmcs12->host_cr0);
12255 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
12256 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
12257 vmx_set_cr4(vcpu, vmcs12->host_cr4);
12259 load_vmcs12_mmu_host_state(vcpu, vmcs12);
12262 * If vmcs01 don't use VPID, CPU flushes TLB on every
12263 * VMEntry/VMExit. Thus, no need to flush TLB.
12265 * If vmcs12 uses VPID, TLB entries populated by L2 are
12266 * tagged with vmx->nested.vpid02 while L1 entries are tagged
12267 * with vmx->vpid. Thus, no need to flush TLB.
12269 * Therefore, flush TLB only in case vmcs01 uses VPID and
12270 * vmcs12 don't use VPID as in this case L1 & L2 TLB entries
12271 * are both tagged with vmx->vpid.
12274 !(nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02)) {
12275 vmx_flush_tlb(vcpu, true);
12278 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
12279 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
12280 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
12281 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
12282 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
12283 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
12284 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
12286 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
12287 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
12288 vmcs_write64(GUEST_BNDCFGS, 0);
12290 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
12291 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
12292 vcpu->arch.pat = vmcs12->host_ia32_pat;
12294 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
12295 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
12296 vmcs12->host_ia32_perf_global_ctrl);
12298 /* Set L1 segment info according to Intel SDM
12299 27.5.2 Loading Host Segment and Descriptor-Table Registers */
12300 seg = (struct kvm_segment) {
12302 .limit = 0xFFFFFFFF,
12303 .selector = vmcs12->host_cs_selector,
12309 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
12313 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
12314 seg = (struct kvm_segment) {
12316 .limit = 0xFFFFFFFF,
12323 seg.selector = vmcs12->host_ds_selector;
12324 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
12325 seg.selector = vmcs12->host_es_selector;
12326 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
12327 seg.selector = vmcs12->host_ss_selector;
12328 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
12329 seg.selector = vmcs12->host_fs_selector;
12330 seg.base = vmcs12->host_fs_base;
12331 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
12332 seg.selector = vmcs12->host_gs_selector;
12333 seg.base = vmcs12->host_gs_base;
12334 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
12335 seg = (struct kvm_segment) {
12336 .base = vmcs12->host_tr_base,
12338 .selector = vmcs12->host_tr_selector,
12342 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
12344 kvm_set_dr(vcpu, 7, 0x400);
12345 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
12347 if (cpu_has_vmx_msr_bitmap())
12348 vmx_update_msr_bitmap(vcpu);
12350 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
12351 vmcs12->vm_exit_msr_load_count))
12352 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
12356 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
12357 * and modify vmcs12 to make it see what it would expect to see there if
12358 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
12360 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
12361 u32 exit_intr_info,
12362 unsigned long exit_qualification)
12364 struct vcpu_vmx *vmx = to_vmx(vcpu);
12365 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12367 /* trying to cancel vmlaunch/vmresume is a bug */
12368 WARN_ON_ONCE(vmx->nested.nested_run_pending);
12371 * The only expected VM-instruction error is "VM entry with
12372 * invalid control field(s)." Anything else indicates a
12375 WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
12376 VMXERR_ENTRY_INVALID_CONTROL_FIELD));
12378 leave_guest_mode(vcpu);
12380 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12381 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
12383 if (likely(!vmx->fail)) {
12384 if (exit_reason == -1)
12385 sync_vmcs12(vcpu, vmcs12);
12387 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
12388 exit_qualification);
12390 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
12391 vmcs12->vm_exit_msr_store_count))
12392 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
12395 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12396 vm_entry_controls_reset_shadow(vmx);
12397 vm_exit_controls_reset_shadow(vmx);
12398 vmx_segment_cache_clear(vmx);
12400 /* Update any VMCS fields that might have changed while L2 ran */
12401 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
12402 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
12403 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
12404 if (vmx->hv_deadline_tsc == -1)
12405 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12406 PIN_BASED_VMX_PREEMPTION_TIMER);
12408 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12409 PIN_BASED_VMX_PREEMPTION_TIMER);
12410 if (kvm_has_tsc_control)
12411 decache_tsc_multiplier(vmx);
12413 if (vmx->nested.change_vmcs01_virtual_apic_mode) {
12414 vmx->nested.change_vmcs01_virtual_apic_mode = false;
12415 vmx_set_virtual_apic_mode(vcpu);
12416 } else if (!nested_cpu_has_ept(vmcs12) &&
12417 nested_cpu_has2(vmcs12,
12418 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
12419 vmx_flush_tlb(vcpu, true);
12422 /* This is needed for same reason as it was needed in prepare_vmcs02 */
12425 /* Unpin physical memory we referred to in vmcs02 */
12426 if (vmx->nested.apic_access_page) {
12427 kvm_release_page_dirty(vmx->nested.apic_access_page);
12428 vmx->nested.apic_access_page = NULL;
12430 if (vmx->nested.virtual_apic_page) {
12431 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
12432 vmx->nested.virtual_apic_page = NULL;
12434 if (vmx->nested.pi_desc_page) {
12435 kunmap(vmx->nested.pi_desc_page);
12436 kvm_release_page_dirty(vmx->nested.pi_desc_page);
12437 vmx->nested.pi_desc_page = NULL;
12438 vmx->nested.pi_desc = NULL;
12442 * We are now running in L2, mmu_notifier will force to reload the
12443 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
12445 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
12447 if (enable_shadow_vmcs && exit_reason != -1)
12448 vmx->nested.sync_shadow_vmcs = true;
12450 /* in case we halted in L2 */
12451 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12453 if (likely(!vmx->fail)) {
12455 * TODO: SDM says that with acknowledge interrupt on
12456 * exit, bit 31 of the VM-exit interrupt information
12457 * (valid interrupt) is always set to 1 on
12458 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
12459 * need kvm_cpu_has_interrupt(). See the commit
12460 * message for details.
12462 if (nested_exit_intr_ack_set(vcpu) &&
12463 exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
12464 kvm_cpu_has_interrupt(vcpu)) {
12465 int irq = kvm_cpu_get_interrupt(vcpu);
12467 vmcs12->vm_exit_intr_info = irq |
12468 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
12471 if (exit_reason != -1)
12472 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
12473 vmcs12->exit_qualification,
12474 vmcs12->idt_vectoring_info_field,
12475 vmcs12->vm_exit_intr_info,
12476 vmcs12->vm_exit_intr_error_code,
12479 load_vmcs12_host_state(vcpu, vmcs12);
12485 * After an early L2 VM-entry failure, we're now back
12486 * in L1 which thinks it just finished a VMLAUNCH or
12487 * VMRESUME instruction, so we need to set the failure
12488 * flag and the VM-instruction error field of the VMCS
12491 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
12493 load_vmcs12_mmu_host_state(vcpu, vmcs12);
12496 * The emulated instruction was already skipped in
12497 * nested_vmx_run, but the updated RIP was never
12498 * written back to the vmcs01.
12500 skip_emulated_instruction(vcpu);
12505 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
12507 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
12509 if (is_guest_mode(vcpu)) {
12510 to_vmx(vcpu)->nested.nested_run_pending = 0;
12511 nested_vmx_vmexit(vcpu, -1, 0, 0);
12513 free_nested(to_vmx(vcpu));
12517 * L1's failure to enter L2 is a subset of a normal exit, as explained in
12518 * 23.7 "VM-entry failures during or after loading guest state" (this also
12519 * lists the acceptable exit-reason and exit-qualification parameters).
12520 * It should only be called before L2 actually succeeded to run, and when
12521 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
12523 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
12524 struct vmcs12 *vmcs12,
12525 u32 reason, unsigned long qualification)
12527 load_vmcs12_host_state(vcpu, vmcs12);
12528 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
12529 vmcs12->exit_qualification = qualification;
12530 nested_vmx_succeed(vcpu);
12531 if (enable_shadow_vmcs)
12532 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
12535 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
12536 struct x86_instruction_info *info,
12537 enum x86_intercept_stage stage)
12539 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12540 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
12543 * RDPID causes #UD if disabled through secondary execution controls.
12544 * Because it is marked as EmulateOnUD, we need to intercept it here.
12546 if (info->intercept == x86_intercept_rdtscp &&
12547 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
12548 ctxt->exception.vector = UD_VECTOR;
12549 ctxt->exception.error_code_valid = false;
12550 return X86EMUL_PROPAGATE_FAULT;
12553 /* TODO: check more intercepts... */
12554 return X86EMUL_CONTINUE;
12557 #ifdef CONFIG_X86_64
12558 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
12559 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
12560 u64 divisor, u64 *result)
12562 u64 low = a << shift, high = a >> (64 - shift);
12564 /* To avoid the overflow on divq */
12565 if (high >= divisor)
12568 /* Low hold the result, high hold rem which is discarded */
12569 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
12570 "rm" (divisor), "0" (low), "1" (high));
12576 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
12578 struct vcpu_vmx *vmx;
12579 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
12581 if (kvm_mwait_in_guest(vcpu->kvm))
12582 return -EOPNOTSUPP;
12584 vmx = to_vmx(vcpu);
12586 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
12587 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
12588 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns);
12590 if (delta_tsc > lapic_timer_advance_cycles)
12591 delta_tsc -= lapic_timer_advance_cycles;
12595 /* Convert to host delta tsc if tsc scaling is enabled */
12596 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
12597 u64_shl_div_u64(delta_tsc,
12598 kvm_tsc_scaling_ratio_frac_bits,
12599 vcpu->arch.tsc_scaling_ratio,
12604 * If the delta tsc can't fit in the 32 bit after the multi shift,
12605 * we can't use the preemption timer.
12606 * It's possible that it fits on later vmentries, but checking
12607 * on every vmentry is costly so we just use an hrtimer.
12609 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
12612 vmx->hv_deadline_tsc = tscl + delta_tsc;
12613 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12614 PIN_BASED_VMX_PREEMPTION_TIMER);
12616 return delta_tsc == 0;
12619 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
12621 struct vcpu_vmx *vmx = to_vmx(vcpu);
12622 vmx->hv_deadline_tsc = -1;
12623 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12624 PIN_BASED_VMX_PREEMPTION_TIMER);
12628 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
12630 if (!kvm_pause_in_guest(vcpu->kvm))
12631 shrink_ple_window(vcpu);
12634 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
12635 struct kvm_memory_slot *slot)
12637 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
12638 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
12641 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
12642 struct kvm_memory_slot *slot)
12644 kvm_mmu_slot_set_dirty(kvm, slot);
12647 static void vmx_flush_log_dirty(struct kvm *kvm)
12649 kvm_flush_pml_buffers(kvm);
12652 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
12654 struct vmcs12 *vmcs12;
12655 struct vcpu_vmx *vmx = to_vmx(vcpu);
12657 struct page *page = NULL;
12660 if (is_guest_mode(vcpu)) {
12661 WARN_ON_ONCE(vmx->nested.pml_full);
12664 * Check if PML is enabled for the nested guest.
12665 * Whether eptp bit 6 is set is already checked
12666 * as part of A/D emulation.
12668 vmcs12 = get_vmcs12(vcpu);
12669 if (!nested_cpu_has_pml(vmcs12))
12672 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
12673 vmx->nested.pml_full = true;
12677 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
12679 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
12680 if (is_error_page(page))
12683 pml_address = kmap(page);
12684 pml_address[vmcs12->guest_pml_index--] = gpa;
12686 kvm_release_page_clean(page);
12692 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
12693 struct kvm_memory_slot *memslot,
12694 gfn_t offset, unsigned long mask)
12696 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
12699 static void __pi_post_block(struct kvm_vcpu *vcpu)
12701 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12702 struct pi_desc old, new;
12706 old.control = new.control = pi_desc->control;
12707 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
12708 "Wakeup handler not enabled while the VCPU is blocked\n");
12710 dest = cpu_physical_id(vcpu->cpu);
12712 if (x2apic_enabled())
12715 new.ndst = (dest << 8) & 0xFF00;
12717 /* set 'NV' to 'notification vector' */
12718 new.nv = POSTED_INTR_VECTOR;
12719 } while (cmpxchg64(&pi_desc->control, old.control,
12720 new.control) != old.control);
12722 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
12723 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12724 list_del(&vcpu->blocked_vcpu_list);
12725 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12726 vcpu->pre_pcpu = -1;
12731 * This routine does the following things for vCPU which is going
12732 * to be blocked if VT-d PI is enabled.
12733 * - Store the vCPU to the wakeup list, so when interrupts happen
12734 * we can find the right vCPU to wake up.
12735 * - Change the Posted-interrupt descriptor as below:
12736 * 'NDST' <-- vcpu->pre_pcpu
12737 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12738 * - If 'ON' is set during this process, which means at least one
12739 * interrupt is posted for this vCPU, we cannot block it, in
12740 * this case, return 1, otherwise, return 0.
12743 static int pi_pre_block(struct kvm_vcpu *vcpu)
12746 struct pi_desc old, new;
12747 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12749 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
12750 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12751 !kvm_vcpu_apicv_active(vcpu))
12754 WARN_ON(irqs_disabled());
12755 local_irq_disable();
12756 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
12757 vcpu->pre_pcpu = vcpu->cpu;
12758 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12759 list_add_tail(&vcpu->blocked_vcpu_list,
12760 &per_cpu(blocked_vcpu_on_cpu,
12762 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12766 old.control = new.control = pi_desc->control;
12768 WARN((pi_desc->sn == 1),
12769 "Warning: SN field of posted-interrupts "
12770 "is set before blocking\n");
12773 * Since vCPU can be preempted during this process,
12774 * vcpu->cpu could be different with pre_pcpu, we
12775 * need to set pre_pcpu as the destination of wakeup
12776 * notification event, then we can find the right vCPU
12777 * to wakeup in wakeup handler if interrupts happen
12778 * when the vCPU is in blocked state.
12780 dest = cpu_physical_id(vcpu->pre_pcpu);
12782 if (x2apic_enabled())
12785 new.ndst = (dest << 8) & 0xFF00;
12787 /* set 'NV' to 'wakeup vector' */
12788 new.nv = POSTED_INTR_WAKEUP_VECTOR;
12789 } while (cmpxchg64(&pi_desc->control, old.control,
12790 new.control) != old.control);
12792 /* We should not block the vCPU if an interrupt is posted for it. */
12793 if (pi_test_on(pi_desc) == 1)
12794 __pi_post_block(vcpu);
12796 local_irq_enable();
12797 return (vcpu->pre_pcpu == -1);
12800 static int vmx_pre_block(struct kvm_vcpu *vcpu)
12802 if (pi_pre_block(vcpu))
12805 if (kvm_lapic_hv_timer_in_use(vcpu))
12806 kvm_lapic_switch_to_sw_timer(vcpu);
12811 static void pi_post_block(struct kvm_vcpu *vcpu)
12813 if (vcpu->pre_pcpu == -1)
12816 WARN_ON(irqs_disabled());
12817 local_irq_disable();
12818 __pi_post_block(vcpu);
12819 local_irq_enable();
12822 static void vmx_post_block(struct kvm_vcpu *vcpu)
12824 if (kvm_x86_ops->set_hv_timer)
12825 kvm_lapic_switch_to_hv_timer(vcpu);
12827 pi_post_block(vcpu);
12831 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12834 * @host_irq: host irq of the interrupt
12835 * @guest_irq: gsi of the interrupt
12836 * @set: set or unset PI
12837 * returns 0 on success, < 0 on failure
12839 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
12840 uint32_t guest_irq, bool set)
12842 struct kvm_kernel_irq_routing_entry *e;
12843 struct kvm_irq_routing_table *irq_rt;
12844 struct kvm_lapic_irq irq;
12845 struct kvm_vcpu *vcpu;
12846 struct vcpu_data vcpu_info;
12849 if (!kvm_arch_has_assigned_device(kvm) ||
12850 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12851 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
12854 idx = srcu_read_lock(&kvm->irq_srcu);
12855 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
12856 if (guest_irq >= irq_rt->nr_rt_entries ||
12857 hlist_empty(&irq_rt->map[guest_irq])) {
12858 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12859 guest_irq, irq_rt->nr_rt_entries);
12863 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
12864 if (e->type != KVM_IRQ_ROUTING_MSI)
12867 * VT-d PI cannot support posting multicast/broadcast
12868 * interrupts to a vCPU, we still use interrupt remapping
12869 * for these kind of interrupts.
12871 * For lowest-priority interrupts, we only support
12872 * those with single CPU as the destination, e.g. user
12873 * configures the interrupts via /proc/irq or uses
12874 * irqbalance to make the interrupts single-CPU.
12876 * We will support full lowest-priority interrupt later.
12879 kvm_set_msi_irq(kvm, e, &irq);
12880 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
12882 * Make sure the IRTE is in remapped mode if
12883 * we don't handle it in posted mode.
12885 ret = irq_set_vcpu_affinity(host_irq, NULL);
12888 "failed to back to remapped mode, irq: %u\n",
12896 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
12897 vcpu_info.vector = irq.vector;
12899 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
12900 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
12903 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
12905 ret = irq_set_vcpu_affinity(host_irq, NULL);
12908 printk(KERN_INFO "%s: failed to update PI IRTE\n",
12916 srcu_read_unlock(&kvm->irq_srcu, idx);
12920 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
12922 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
12923 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
12924 FEATURE_CONTROL_LMCE;
12926 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
12927 ~FEATURE_CONTROL_LMCE;
12930 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
12932 /* we need a nested vmexit to enter SMM, postpone if run is pending */
12933 if (to_vmx(vcpu)->nested.nested_run_pending)
12938 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
12940 struct vcpu_vmx *vmx = to_vmx(vcpu);
12942 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
12943 if (vmx->nested.smm.guest_mode)
12944 nested_vmx_vmexit(vcpu, -1, 0, 0);
12946 vmx->nested.smm.vmxon = vmx->nested.vmxon;
12947 vmx->nested.vmxon = false;
12948 vmx_clear_hlt(vcpu);
12952 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
12954 struct vcpu_vmx *vmx = to_vmx(vcpu);
12957 if (vmx->nested.smm.vmxon) {
12958 vmx->nested.vmxon = true;
12959 vmx->nested.smm.vmxon = false;
12962 if (vmx->nested.smm.guest_mode) {
12963 vcpu->arch.hflags &= ~HF_SMM_MASK;
12964 ret = enter_vmx_non_root_mode(vcpu);
12965 vcpu->arch.hflags |= HF_SMM_MASK;
12969 vmx->nested.smm.guest_mode = false;
12974 static int enable_smi_window(struct kvm_vcpu *vcpu)
12979 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
12980 .cpu_has_kvm_support = cpu_has_kvm_support,
12981 .disabled_by_bios = vmx_disabled_by_bios,
12982 .hardware_setup = hardware_setup,
12983 .hardware_unsetup = hardware_unsetup,
12984 .check_processor_compatibility = vmx_check_processor_compat,
12985 .hardware_enable = hardware_enable,
12986 .hardware_disable = hardware_disable,
12987 .cpu_has_accelerated_tpr = report_flexpriority,
12988 .has_emulated_msr = vmx_has_emulated_msr,
12990 .vm_init = vmx_vm_init,
12991 .vm_alloc = vmx_vm_alloc,
12992 .vm_free = vmx_vm_free,
12994 .vcpu_create = vmx_create_vcpu,
12995 .vcpu_free = vmx_free_vcpu,
12996 .vcpu_reset = vmx_vcpu_reset,
12998 .prepare_guest_switch = vmx_save_host_state,
12999 .vcpu_load = vmx_vcpu_load,
13000 .vcpu_put = vmx_vcpu_put,
13002 .update_bp_intercept = update_exception_bitmap,
13003 .get_msr_feature = vmx_get_msr_feature,
13004 .get_msr = vmx_get_msr,
13005 .set_msr = vmx_set_msr,
13006 .get_segment_base = vmx_get_segment_base,
13007 .get_segment = vmx_get_segment,
13008 .set_segment = vmx_set_segment,
13009 .get_cpl = vmx_get_cpl,
13010 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
13011 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
13012 .decache_cr3 = vmx_decache_cr3,
13013 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
13014 .set_cr0 = vmx_set_cr0,
13015 .set_cr3 = vmx_set_cr3,
13016 .set_cr4 = vmx_set_cr4,
13017 .set_efer = vmx_set_efer,
13018 .get_idt = vmx_get_idt,
13019 .set_idt = vmx_set_idt,
13020 .get_gdt = vmx_get_gdt,
13021 .set_gdt = vmx_set_gdt,
13022 .get_dr6 = vmx_get_dr6,
13023 .set_dr6 = vmx_set_dr6,
13024 .set_dr7 = vmx_set_dr7,
13025 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
13026 .cache_reg = vmx_cache_reg,
13027 .get_rflags = vmx_get_rflags,
13028 .set_rflags = vmx_set_rflags,
13030 .tlb_flush = vmx_flush_tlb,
13032 .run = vmx_vcpu_run,
13033 .handle_exit = vmx_handle_exit,
13034 .skip_emulated_instruction = skip_emulated_instruction,
13035 .set_interrupt_shadow = vmx_set_interrupt_shadow,
13036 .get_interrupt_shadow = vmx_get_interrupt_shadow,
13037 .patch_hypercall = vmx_patch_hypercall,
13038 .set_irq = vmx_inject_irq,
13039 .set_nmi = vmx_inject_nmi,
13040 .queue_exception = vmx_queue_exception,
13041 .cancel_injection = vmx_cancel_injection,
13042 .interrupt_allowed = vmx_interrupt_allowed,
13043 .nmi_allowed = vmx_nmi_allowed,
13044 .get_nmi_mask = vmx_get_nmi_mask,
13045 .set_nmi_mask = vmx_set_nmi_mask,
13046 .enable_nmi_window = enable_nmi_window,
13047 .enable_irq_window = enable_irq_window,
13048 .update_cr8_intercept = update_cr8_intercept,
13049 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
13050 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
13051 .get_enable_apicv = vmx_get_enable_apicv,
13052 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
13053 .load_eoi_exitmap = vmx_load_eoi_exitmap,
13054 .apicv_post_state_restore = vmx_apicv_post_state_restore,
13055 .hwapic_irr_update = vmx_hwapic_irr_update,
13056 .hwapic_isr_update = vmx_hwapic_isr_update,
13057 .sync_pir_to_irr = vmx_sync_pir_to_irr,
13058 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
13060 .set_tss_addr = vmx_set_tss_addr,
13061 .set_identity_map_addr = vmx_set_identity_map_addr,
13062 .get_tdp_level = get_ept_level,
13063 .get_mt_mask = vmx_get_mt_mask,
13065 .get_exit_info = vmx_get_exit_info,
13067 .get_lpage_level = vmx_get_lpage_level,
13069 .cpuid_update = vmx_cpuid_update,
13071 .rdtscp_supported = vmx_rdtscp_supported,
13072 .invpcid_supported = vmx_invpcid_supported,
13074 .set_supported_cpuid = vmx_set_supported_cpuid,
13076 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
13078 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
13079 .write_tsc_offset = vmx_write_tsc_offset,
13081 .set_tdp_cr3 = vmx_set_cr3,
13083 .check_intercept = vmx_check_intercept,
13084 .handle_external_intr = vmx_handle_external_intr,
13085 .mpx_supported = vmx_mpx_supported,
13086 .xsaves_supported = vmx_xsaves_supported,
13087 .umip_emulated = vmx_umip_emulated,
13089 .check_nested_events = vmx_check_nested_events,
13091 .sched_in = vmx_sched_in,
13093 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
13094 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
13095 .flush_log_dirty = vmx_flush_log_dirty,
13096 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
13097 .write_log_dirty = vmx_write_pml_buffer,
13099 .pre_block = vmx_pre_block,
13100 .post_block = vmx_post_block,
13102 .pmu_ops = &intel_pmu_ops,
13104 .update_pi_irte = vmx_update_pi_irte,
13106 #ifdef CONFIG_X86_64
13107 .set_hv_timer = vmx_set_hv_timer,
13108 .cancel_hv_timer = vmx_cancel_hv_timer,
13111 .setup_mce = vmx_setup_mce,
13113 .smi_allowed = vmx_smi_allowed,
13114 .pre_enter_smm = vmx_pre_enter_smm,
13115 .pre_leave_smm = vmx_pre_leave_smm,
13116 .enable_smi_window = enable_smi_window,
13119 static int __init vmx_init(void)
13123 #if IS_ENABLED(CONFIG_HYPERV)
13125 * Enlightened VMCS usage should be recommended and the host needs
13126 * to support eVMCS v1 or above. We can also disable eVMCS support
13127 * with module parameter.
13129 if (enlightened_vmcs &&
13130 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
13131 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
13132 KVM_EVMCS_VERSION) {
13135 /* Check that we have assist pages on all online CPUs */
13136 for_each_online_cpu(cpu) {
13137 if (!hv_get_vp_assist_page(cpu)) {
13138 enlightened_vmcs = false;
13143 if (enlightened_vmcs) {
13144 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
13145 static_branch_enable(&enable_evmcs);
13148 enlightened_vmcs = false;
13152 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
13153 __alignof__(struct vcpu_vmx), THIS_MODULE);
13157 #ifdef CONFIG_KEXEC_CORE
13158 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
13159 crash_vmclear_local_loaded_vmcss);
13161 vmx_check_vmcs12_offsets();
13166 static void __exit vmx_exit(void)
13168 #ifdef CONFIG_KEXEC_CORE
13169 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
13175 #if IS_ENABLED(CONFIG_HYPERV)
13176 if (static_branch_unlikely(&enable_evmcs)) {
13178 struct hv_vp_assist_page *vp_ap;
13180 * Reset everything to support using non-enlightened VMCS
13181 * access later (e.g. when we reload the module with
13182 * enlightened_vmcs=0)
13184 for_each_online_cpu(cpu) {
13185 vp_ap = hv_get_vp_assist_page(cpu);
13190 vp_ap->current_nested_vmcs = 0;
13191 vp_ap->enlighten_vmentry = 0;
13194 static_branch_disable(&enable_evmcs);
13199 module_init(vmx_init)
13200 module_exit(vmx_exit)