arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include <linux/nospec.h>
  38 #include "kvm_cache_regs.h"
  39 #include "x86.h"
  40
  41 #include <asm/cpu.h>
  42 #include <asm/io.h>
  43 #include <asm/desc.h>
  44 #include <asm/vmx.h>
  45 #include <asm/virtext.h>
  46 #include <asm/mce.h>
  47 #include <asm/fpu/internal.h>
  48 #include <asm/perf_event.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kexec.h>
  51 #include <asm/apic.h>
  52 #include <asm/irq_remapping.h>
  53 #include <asm/mmu_context.h>
  54 #include <asm/nospec-branch.h>
  55 #include <asm/mshyperv.h>
  56
  57 #include "trace.h"
  58 #include "pmu.h"
  59 #include "vmx_evmcs.h"
  60
  61 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  62 #define __ex_clear(x, reg) \
  63         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  64
  65 MODULE_AUTHOR("Qumranet");
  66 MODULE_LICENSE("GPL");
  67
  68 static const struct x86_cpu_id vmx_cpu_id[] = {
  69         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  70         {}
  71 };
  72 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  73
  74 static bool __read_mostly enable_vpid = 1;
  75 module_param_named(vpid, enable_vpid, bool, 0444);
  76
  77 static bool __read_mostly enable_vnmi = 1;
  78 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  79
  80 static bool __read_mostly flexpriority_enabled = 1;
  81 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  82
  83 static bool __read_mostly enable_ept = 1;
  84 module_param_named(ept, enable_ept, bool, S_IRUGO);
  85
  86 static bool __read_mostly enable_unrestricted_guest = 1;
  87 module_param_named(unrestricted_guest,
  88                         enable_unrestricted_guest, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_ept_ad_bits = 1;
  91 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  92
  93 static bool __read_mostly emulate_invalid_guest_state = true;
  94 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  95
  96 static bool __read_mostly fasteoi = 1;
  97 module_param(fasteoi, bool, S_IRUGO);
  98
  99 static bool __read_mostly enable_apicv = 1;
 100 module_param(enable_apicv, bool, S_IRUGO);
 101
 102 static bool __read_mostly enable_shadow_vmcs = 1;
 103 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
 104 /*
 105  * If nested=1, nested virtualization is supported, i.e., guests may use
 106  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 107  * use VMX instructions.
 108  */
 109 static bool __read_mostly nested = 0;
 110 module_param(nested, bool, S_IRUGO);
 111
 112 static u64 __read_mostly host_xss;
 113
 114 static bool __read_mostly enable_pml = 1;
 115 module_param_named(pml, enable_pml, bool, S_IRUGO);
 116
 117 #define MSR_TYPE_R      1
 118 #define MSR_TYPE_W      2
 119 #define MSR_TYPE_RW     3
 120
 121 #define MSR_BITMAP_MODE_X2APIC          1
 122 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 123 #define MSR_BITMAP_MODE_LM              4
 124
 125 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 126
 127 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 128 static int __read_mostly cpu_preemption_timer_multi;
 129 static bool __read_mostly enable_preemption_timer = 1;
 130 #ifdef CONFIG_X86_64
 131 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 132 #endif
 133
 134 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 135 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 136 #define KVM_VM_CR0_ALWAYS_ON                            \
 137         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 138          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 139 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 140         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 141          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 142
 143 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 144 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 145 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 146
 147 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 148
 149 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 150
 151 /*
 152  * Hyper-V requires all of these, so mark them as supported even though
 153  * they are just treated the same as all-context.
 154  */
 155 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 156         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 157         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 158         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 159         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 160
 161 /*
 162  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 163  * ple_gap:    upper bound on the amount of time between two successive
 164  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 165  *             According to test, this time is usually smaller than 128 cycles.
 166  * ple_window: upper bound on the amount of time a guest is allowed to execute
 167  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 168  *             less than 2^12 cycles
 169  * Time is measured based on a counter that runs at the same rate as the TSC,
 170  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 171  */
 172 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 173
 174 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 175 module_param(ple_window, uint, 0444);
 176
 177 /* Default doubles per-vcpu window every exit. */
 178 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 179 module_param(ple_window_grow, uint, 0444);
 180
 181 /* Default resets per-vcpu window every exit to ple_window. */
 182 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 183 module_param(ple_window_shrink, uint, 0444);
 184
 185 /* Default is to compute the maximum so we can never overflow. */
 186 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 187 module_param(ple_window_max, uint, 0444);
 188
 189 extern const ulong vmx_return;
 190
 191 struct kvm_vmx {
 192         struct kvm kvm;
 193
 194         unsigned int tss_addr;
 195         bool ept_identity_pagetable_done;
 196         gpa_t ept_identity_map_addr;
 197 };
 198
 199 #define NR_AUTOLOAD_MSRS 8
 200
 201 struct vmcs {
 202         u32 revision_id;
 203         u32 abort;
 204         char data[0];
 205 };
 206
 207 /*
 208  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 209  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 210  * loaded on this CPU (so we can clear them if the CPU goes down).
 211  */
 212 struct loaded_vmcs {
 213         struct vmcs *vmcs;
 214         struct vmcs *shadow_vmcs;
 215         int cpu;
 216         bool launched;
 217         bool nmi_known_unmasked;
 218         unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 219         unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 220         /* Support for vnmi-less CPUs */
 221         int soft_vnmi_blocked;
 222         ktime_t entry_time;
 223         s64 vnmi_blocked_time;
 224         unsigned long *msr_bitmap;
 225         struct list_head loaded_vmcss_on_cpu_link;
 226 };
 227
 228 struct shared_msr_entry {
 229         unsigned index;
 230         u64 data;
 231         u64 mask;
 232 };
 233
 234 /*
 235  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 236  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 237  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 238  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 239  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 240  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 241  * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
 242  * underlying hardware which will be used to run L2.
 243  * This structure is packed to ensure that its layout is identical across
 244  * machines (necessary for live migration).
 245  * If there are changes in this struct, VMCS12_REVISION must be changed.
 246  */
 247 typedef u64 natural_width;
 248 struct __packed vmcs12 {
 249         /* According to the Intel spec, a VMCS region must start with the
 250          * following two fields. Then follow implementation-specific data.
 251          */
 252         u32 revision_id;
 253         u32 abort;
 254
 255         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 256         u32 padding[7]; /* room for future expansion */
 257
 258         u64 io_bitmap_a;
 259         u64 io_bitmap_b;
 260         u64 msr_bitmap;
 261         u64 vm_exit_msr_store_addr;
 262         u64 vm_exit_msr_load_addr;
 263         u64 vm_entry_msr_load_addr;
 264         u64 tsc_offset;
 265         u64 virtual_apic_page_addr;
 266         u64 apic_access_addr;
 267         u64 posted_intr_desc_addr;
 268         u64 vm_function_control;
 269         u64 ept_pointer;
 270         u64 eoi_exit_bitmap0;
 271         u64 eoi_exit_bitmap1;
 272         u64 eoi_exit_bitmap2;
 273         u64 eoi_exit_bitmap3;
 274         u64 eptp_list_address;
 275         u64 xss_exit_bitmap;
 276         u64 guest_physical_address;
 277         u64 vmcs_link_pointer;
 278         u64 pml_address;
 279         u64 guest_ia32_debugctl;
 280         u64 guest_ia32_pat;
 281         u64 guest_ia32_efer;
 282         u64 guest_ia32_perf_global_ctrl;
 283         u64 guest_pdptr0;
 284         u64 guest_pdptr1;
 285         u64 guest_pdptr2;
 286         u64 guest_pdptr3;
 287         u64 guest_bndcfgs;
 288         u64 host_ia32_pat;
 289         u64 host_ia32_efer;
 290         u64 host_ia32_perf_global_ctrl;
 291         u64 padding64[8]; /* room for future expansion */
 292         /*
 293          * To allow migration of L1 (complete with its L2 guests) between
 294          * machines of different natural widths (32 or 64 bit), we cannot have
 295          * unsigned long fields with no explict size. We use u64 (aliased
 296          * natural_width) instead. Luckily, x86 is little-endian.
 297          */
 298         natural_width cr0_guest_host_mask;
 299         natural_width cr4_guest_host_mask;
 300         natural_width cr0_read_shadow;
 301         natural_width cr4_read_shadow;
 302         natural_width cr3_target_value0;
 303         natural_width cr3_target_value1;
 304         natural_width cr3_target_value2;
 305         natural_width cr3_target_value3;
 306         natural_width exit_qualification;
 307         natural_width guest_linear_address;
 308         natural_width guest_cr0;
 309         natural_width guest_cr3;
 310         natural_width guest_cr4;
 311         natural_width guest_es_base;
 312         natural_width guest_cs_base;
 313         natural_width guest_ss_base;
 314         natural_width guest_ds_base;
 315         natural_width guest_fs_base;
 316         natural_width guest_gs_base;
 317         natural_width guest_ldtr_base;
 318         natural_width guest_tr_base;
 319         natural_width guest_gdtr_base;
 320         natural_width guest_idtr_base;
 321         natural_width guest_dr7;
 322         natural_width guest_rsp;
 323         natural_width guest_rip;
 324         natural_width guest_rflags;
 325         natural_width guest_pending_dbg_exceptions;
 326         natural_width guest_sysenter_esp;
 327         natural_width guest_sysenter_eip;
 328         natural_width host_cr0;
 329         natural_width host_cr3;
 330         natural_width host_cr4;
 331         natural_width host_fs_base;
 332         natural_width host_gs_base;
 333         natural_width host_tr_base;
 334         natural_width host_gdtr_base;
 335         natural_width host_idtr_base;
 336         natural_width host_ia32_sysenter_esp;
 337         natural_width host_ia32_sysenter_eip;
 338         natural_width host_rsp;
 339         natural_width host_rip;
 340         natural_width paddingl[8]; /* room for future expansion */
 341         u32 pin_based_vm_exec_control;
 342         u32 cpu_based_vm_exec_control;
 343         u32 exception_bitmap;
 344         u32 page_fault_error_code_mask;
 345         u32 page_fault_error_code_match;
 346         u32 cr3_target_count;
 347         u32 vm_exit_controls;
 348         u32 vm_exit_msr_store_count;
 349         u32 vm_exit_msr_load_count;
 350         u32 vm_entry_controls;
 351         u32 vm_entry_msr_load_count;
 352         u32 vm_entry_intr_info_field;
 353         u32 vm_entry_exception_error_code;
 354         u32 vm_entry_instruction_len;
 355         u32 tpr_threshold;
 356         u32 secondary_vm_exec_control;
 357         u32 vm_instruction_error;
 358         u32 vm_exit_reason;
 359         u32 vm_exit_intr_info;
 360         u32 vm_exit_intr_error_code;
 361         u32 idt_vectoring_info_field;
 362         u32 idt_vectoring_error_code;
 363         u32 vm_exit_instruction_len;
 364         u32 vmx_instruction_info;
 365         u32 guest_es_limit;
 366         u32 guest_cs_limit;
 367         u32 guest_ss_limit;
 368         u32 guest_ds_limit;
 369         u32 guest_fs_limit;
 370         u32 guest_gs_limit;
 371         u32 guest_ldtr_limit;
 372         u32 guest_tr_limit;
 373         u32 guest_gdtr_limit;
 374         u32 guest_idtr_limit;
 375         u32 guest_es_ar_bytes;
 376         u32 guest_cs_ar_bytes;
 377         u32 guest_ss_ar_bytes;
 378         u32 guest_ds_ar_bytes;
 379         u32 guest_fs_ar_bytes;
 380         u32 guest_gs_ar_bytes;
 381         u32 guest_ldtr_ar_bytes;
 382         u32 guest_tr_ar_bytes;
 383         u32 guest_interruptibility_info;
 384         u32 guest_activity_state;
 385         u32 guest_sysenter_cs;
 386         u32 host_ia32_sysenter_cs;
 387         u32 vmx_preemption_timer_value;
 388         u32 padding32[7]; /* room for future expansion */
 389         u16 virtual_processor_id;
 390         u16 posted_intr_nv;
 391         u16 guest_es_selector;
 392         u16 guest_cs_selector;
 393         u16 guest_ss_selector;
 394         u16 guest_ds_selector;
 395         u16 guest_fs_selector;
 396         u16 guest_gs_selector;
 397         u16 guest_ldtr_selector;
 398         u16 guest_tr_selector;
 399         u16 guest_intr_status;
 400         u16 guest_pml_index;
 401         u16 host_es_selector;
 402         u16 host_cs_selector;
 403         u16 host_ss_selector;
 404         u16 host_ds_selector;
 405         u16 host_fs_selector;
 406         u16 host_gs_selector;
 407         u16 host_tr_selector;
 408 };
 409
 410 /*
 411  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 412  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 413  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 414  */
 415 #define VMCS12_REVISION 0x11e57ed0
 416
 417 /*
 418  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 419  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 420  * current implementation, 4K are reserved to avoid future complications.
 421  */
 422 #define VMCS12_SIZE 0x1000
 423
 424 /*
 425  * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
 426  * supported VMCS12 field encoding.
 427  */
 428 #define VMCS12_MAX_FIELD_INDEX 0x17
 429
 430 struct nested_vmx_msrs {
 431         /*
 432          * We only store the "true" versions of the VMX capability MSRs. We
 433          * generate the "non-true" versions by setting the must-be-1 bits
 434          * according to the SDM.
 435          */
 436         u32 procbased_ctls_low;
 437         u32 procbased_ctls_high;
 438         u32 secondary_ctls_low;
 439         u32 secondary_ctls_high;
 440         u32 pinbased_ctls_low;
 441         u32 pinbased_ctls_high;
 442         u32 exit_ctls_low;
 443         u32 exit_ctls_high;
 444         u32 entry_ctls_low;
 445         u32 entry_ctls_high;
 446         u32 misc_low;
 447         u32 misc_high;
 448         u32 ept_caps;
 449         u32 vpid_caps;
 450         u64 basic;
 451         u64 cr0_fixed0;
 452         u64 cr0_fixed1;
 453         u64 cr4_fixed0;
 454         u64 cr4_fixed1;
 455         u64 vmcs_enum;
 456         u64 vmfunc_controls;
 457 };
 458
 459 /*
 460  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 461  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 462  */
 463 struct nested_vmx {
 464         /* Has the level1 guest done vmxon? */
 465         bool vmxon;
 466         gpa_t vmxon_ptr;
 467         bool pml_full;
 468
 469         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 470         gpa_t current_vmptr;
 471         /*
 472          * Cache of the guest's VMCS, existing outside of guest memory.
 473          * Loaded from guest memory during VMPTRLD. Flushed to guest
 474          * memory during VMCLEAR and VMPTRLD.
 475          */
 476         struct vmcs12 *cached_vmcs12;
 477         /*
 478          * Indicates if the shadow vmcs must be updated with the
 479          * data hold by vmcs12
 480          */
 481         bool sync_shadow_vmcs;
 482         bool dirty_vmcs12;
 483
 484         bool change_vmcs01_virtual_x2apic_mode;
 485         /* L2 must run next, and mustn't decide to exit to L1. */
 486         bool nested_run_pending;
 487
 488         struct loaded_vmcs vmcs02;
 489
 490         /*
 491          * Guest pages referred to in the vmcs02 with host-physical
 492          * pointers, so we must keep them pinned while L2 runs.
 493          */
 494         struct page *apic_access_page;
 495         struct page *virtual_apic_page;
 496         struct page *pi_desc_page;
 497         struct pi_desc *pi_desc;
 498         bool pi_pending;
 499         u16 posted_intr_nv;
 500
 501         struct hrtimer preemption_timer;
 502         bool preemption_timer_expired;
 503
 504         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 505         u64 vmcs01_debugctl;
 506
 507         u16 vpid02;
 508         u16 last_vpid;
 509
 510         struct nested_vmx_msrs msrs;
 511
 512         /* SMM related state */
 513         struct {
 514                 /* in VMX operation on SMM entry? */
 515                 bool vmxon;
 516                 /* in guest mode on SMM entry? */
 517                 bool guest_mode;
 518         } smm;
 519 };
 520
 521 #define POSTED_INTR_ON  0
 522 #define POSTED_INTR_SN  1
 523
 524 /* Posted-Interrupt Descriptor */
 525 struct pi_desc {
 526         u32 pir[8];     /* Posted interrupt requested */
 527         union {
 528                 struct {
 529                                 /* bit 256 - Outstanding Notification */
 530                         u16     on      : 1,
 531                                 /* bit 257 - Suppress Notification */
 532                                 sn      : 1,
 533                                 /* bit 271:258 - Reserved */
 534                                 rsvd_1  : 14;
 535                                 /* bit 279:272 - Notification Vector */
 536                         u8      nv;
 537                                 /* bit 287:280 - Reserved */
 538                         u8      rsvd_2;
 539                                 /* bit 319:288 - Notification Destination */
 540                         u32     ndst;
 541                 };
 542                 u64 control;
 543         };
 544         u32 rsvd[6];
 545 } __aligned(64);
 546
 547 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 548 {
 549         return test_and_set_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 554 {
 555         return test_and_clear_bit(POSTED_INTR_ON,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 560 {
 561         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 562 }
 563
 564 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 565 {
 566         return clear_bit(POSTED_INTR_SN,
 567                         (unsigned long *)&pi_desc->control);
 568 }
 569
 570 static inline void pi_set_sn(struct pi_desc *pi_desc)
 571 {
 572         return set_bit(POSTED_INTR_SN,
 573                         (unsigned long *)&pi_desc->control);
 574 }
 575
 576 static inline void pi_clear_on(struct pi_desc *pi_desc)
 577 {
 578         clear_bit(POSTED_INTR_ON,
 579                   (unsigned long *)&pi_desc->control);
 580 }
 581
 582 static inline int pi_test_on(struct pi_desc *pi_desc)
 583 {
 584         return test_bit(POSTED_INTR_ON,
 585                         (unsigned long *)&pi_desc->control);
 586 }
 587
 588 static inline int pi_test_sn(struct pi_desc *pi_desc)
 589 {
 590         return test_bit(POSTED_INTR_SN,
 591                         (unsigned long *)&pi_desc->control);
 592 }
 593
 594 struct vcpu_vmx {
 595         struct kvm_vcpu       vcpu;
 596         unsigned long         host_rsp;
 597         u8                    fail;
 598         u8                    msr_bitmap_mode;
 599         u32                   exit_intr_info;
 600         u32                   idt_vectoring_info;
 601         ulong                 rflags;
 602         struct shared_msr_entry *guest_msrs;
 603         int                   nmsrs;
 604         int                   save_nmsrs;
 605         unsigned long         host_idt_base;
 606 #ifdef CONFIG_X86_64
 607         u64                   msr_host_kernel_gs_base;
 608         u64                   msr_guest_kernel_gs_base;
 609 #endif
 610
 611         u64                   arch_capabilities;
 612         u64                   spec_ctrl;
 613
 614         u32 vm_entry_controls_shadow;
 615         u32 vm_exit_controls_shadow;
 616         u32 secondary_exec_control;
 617
 618         /*
 619          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 620          * non-nested (L1) guest, it always points to vmcs01. For a nested
 621          * guest (L2), it points to a different VMCS.
 622          */
 623         struct loaded_vmcs    vmcs01;
 624         struct loaded_vmcs   *loaded_vmcs;
 625         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 626         struct msr_autoload {
 627                 unsigned nr;
 628                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 629                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 630         } msr_autoload;
 631         struct {
 632                 int           loaded;
 633                 u16           fs_sel, gs_sel, ldt_sel;
 634 #ifdef CONFIG_X86_64
 635                 u16           ds_sel, es_sel;
 636 #endif
 637                 int           gs_ldt_reload_needed;
 638                 int           fs_reload_needed;
 639                 u64           msr_host_bndcfgs;
 640         } host_state;
 641         struct {
 642                 int vm86_active;
 643                 ulong save_rflags;
 644                 struct kvm_segment segs[8];
 645         } rmode;
 646         struct {
 647                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 648                 struct kvm_save_segment {
 649                         u16 selector;
 650                         unsigned long base;
 651                         u32 limit;
 652                         u32 ar;
 653                 } seg[8];
 654         } segment_cache;
 655         int vpid;
 656         bool emulation_required;
 657
 658         u32 exit_reason;
 659
 660         /* Posted interrupt descriptor */
 661         struct pi_desc pi_desc;
 662
 663         /* Support for a guest hypervisor (nested VMX) */
 664         struct nested_vmx nested;
 665
 666         /* Dynamic PLE window. */
 667         int ple_window;
 668         bool ple_window_dirty;
 669
 670         /* Support for PML */
 671 #define PML_ENTITY_NUM          512
 672         struct page *pml_pg;
 673
 674         /* apic deadline value in host tsc */
 675         u64 hv_deadline_tsc;
 676
 677         u64 current_tsc_ratio;
 678
 679         u32 host_pkru;
 680
 681         unsigned long host_debugctlmsr;
 682
 683         /*
 684          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 685          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 686          * in msr_ia32_feature_control_valid_bits.
 687          */
 688         u64 msr_ia32_feature_control;
 689         u64 msr_ia32_feature_control_valid_bits;
 690 };
 691
 692 enum segment_cache_field {
 693         SEG_FIELD_SEL = 0,
 694         SEG_FIELD_BASE = 1,
 695         SEG_FIELD_LIMIT = 2,
 696         SEG_FIELD_AR = 3,
 697
 698         SEG_FIELD_NR = 4
 699 };
 700
 701 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
 702 {
 703         return container_of(kvm, struct kvm_vmx, kvm);
 704 }
 705
 706 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 707 {
 708         return container_of(vcpu, struct vcpu_vmx, vcpu);
 709 }
 710
 711 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 712 {
 713         return &(to_vmx(vcpu)->pi_desc);
 714 }
 715
 716 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
 717 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 718 #define FIELD(number, name)     [ROL16(number, 6)] = VMCS12_OFFSET(name)
 719 #define FIELD64(number, name)                                           \
 720         FIELD(number, name),                                            \
 721         [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
 722
 723
 724 static u16 shadow_read_only_fields[] = {
 725 #define SHADOW_FIELD_RO(x) x,
 726 #include "vmx_shadow_fields.h"
 727 };
 728 static int max_shadow_read_only_fields =
 729         ARRAY_SIZE(shadow_read_only_fields);
 730
 731 static u16 shadow_read_write_fields[] = {
 732 #define SHADOW_FIELD_RW(x) x,
 733 #include "vmx_shadow_fields.h"
 734 };
 735 static int max_shadow_read_write_fields =
 736         ARRAY_SIZE(shadow_read_write_fields);
 737
 738 static const unsigned short vmcs_field_to_offset_table[] = {
 739         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 740         FIELD(POSTED_INTR_NV, posted_intr_nv),
 741         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 742         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 743         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 744         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 745         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 746         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 747         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 748         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 749         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 750         FIELD(GUEST_PML_INDEX, guest_pml_index),
 751         FIELD(HOST_ES_SELECTOR, host_es_selector),
 752         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 753         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 754         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 755         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 756         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 757         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 758         FIELD64(IO_BITMAP_A, io_bitmap_a),
 759         FIELD64(IO_BITMAP_B, io_bitmap_b),
 760         FIELD64(MSR_BITMAP, msr_bitmap),
 761         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 762         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 763         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 764         FIELD64(TSC_OFFSET, tsc_offset),
 765         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 766         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 767         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 768         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
 769         FIELD64(EPT_POINTER, ept_pointer),
 770         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 771         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 772         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 773         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 774         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
 775         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 776         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 777         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 778         FIELD64(PML_ADDRESS, pml_address),
 779         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 780         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 781         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 782         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 783         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 784         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 785         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 786         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 787         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 788         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 789         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 790         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 791         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 792         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 793         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 794         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 795         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 796         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 797         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 798         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 799         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 800         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 801         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 802         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 803         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 804         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 805         FIELD(TPR_THRESHOLD, tpr_threshold),
 806         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 807         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 808         FIELD(VM_EXIT_REASON, vm_exit_reason),
 809         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 810         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 811         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 812         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 813         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 814         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 815         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 816         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 817         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 818         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 819         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 820         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 821         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 822         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 823         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 824         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 825         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 826         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 827         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 828         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 829         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 830         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 831         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 832         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 833         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 834         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 835         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 836         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 837         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 838         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 839         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 840         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 841         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 842         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 843         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 844         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 845         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 846         FIELD(EXIT_QUALIFICATION, exit_qualification),
 847         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 848         FIELD(GUEST_CR0, guest_cr0),
 849         FIELD(GUEST_CR3, guest_cr3),
 850         FIELD(GUEST_CR4, guest_cr4),
 851         FIELD(GUEST_ES_BASE, guest_es_base),
 852         FIELD(GUEST_CS_BASE, guest_cs_base),
 853         FIELD(GUEST_SS_BASE, guest_ss_base),
 854         FIELD(GUEST_DS_BASE, guest_ds_base),
 855         FIELD(GUEST_FS_BASE, guest_fs_base),
 856         FIELD(GUEST_GS_BASE, guest_gs_base),
 857         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 858         FIELD(GUEST_TR_BASE, guest_tr_base),
 859         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 860         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 861         FIELD(GUEST_DR7, guest_dr7),
 862         FIELD(GUEST_RSP, guest_rsp),
 863         FIELD(GUEST_RIP, guest_rip),
 864         FIELD(GUEST_RFLAGS, guest_rflags),
 865         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 866         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 867         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 868         FIELD(HOST_CR0, host_cr0),
 869         FIELD(HOST_CR3, host_cr3),
 870         FIELD(HOST_CR4, host_cr4),
 871         FIELD(HOST_FS_BASE, host_fs_base),
 872         FIELD(HOST_GS_BASE, host_gs_base),
 873         FIELD(HOST_TR_BASE, host_tr_base),
 874         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 875         FIELD(HOST_IDTR_BASE, host_idtr_base),
 876         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 877         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 878         FIELD(HOST_RSP, host_rsp),
 879         FIELD(HOST_RIP, host_rip),
 880 };
 881
 882 static inline short vmcs_field_to_offset(unsigned long field)
 883 {
 884         const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
 885         unsigned short offset;
 886         unsigned index;
 887
 888         if (field >> 15)
 889                 return -ENOENT;
 890
 891         index = ROL16(field, 6);
 892         if (index >= size)
 893                 return -ENOENT;
 894
 895         index = array_index_nospec(index, size);
 896         offset = vmcs_field_to_offset_table[index];
 897         if (offset == 0)
 898                 return -ENOENT;
 899         return offset;
 900 }
 901
 902 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 903 {
 904         return to_vmx(vcpu)->nested.cached_vmcs12;
 905 }
 906
 907 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
 908 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 909 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 910 static bool vmx_xsaves_supported(void);
 911 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 912                             struct kvm_segment *var, int seg);
 913 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 914                             struct kvm_segment *var, int seg);
 915 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 916 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 917 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 918 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 919 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 920 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
 921                                             u16 error_code);
 922 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
 923 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 924                                                           u32 msr, int type);
 925
 926 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 927 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 928 /*
 929  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 930  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 931  */
 932 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 933
 934 /*
 935  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 936  * can find which vCPU should be waken up.
 937  */
 938 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 939 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 940
 941 enum {
 942         VMX_VMREAD_BITMAP,
 943         VMX_VMWRITE_BITMAP,
 944         VMX_BITMAP_NR
 945 };
 946
 947 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 948
 949 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 950 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 951
 952 static bool cpu_has_load_ia32_efer;
 953 static bool cpu_has_load_perf_global_ctrl;
 954
 955 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 956 static DEFINE_SPINLOCK(vmx_vpid_lock);
 957
 958 static struct vmcs_config {
 959         int size;
 960         int order;
 961         u32 basic_cap;
 962         u32 revision_id;
 963         u32 pin_based_exec_ctrl;
 964         u32 cpu_based_exec_ctrl;
 965         u32 cpu_based_2nd_exec_ctrl;
 966         u32 vmexit_ctrl;
 967         u32 vmentry_ctrl;
 968         struct nested_vmx_msrs nested;
 969 } vmcs_config;
 970
 971 static struct vmx_capability {
 972         u32 ept;
 973         u32 vpid;
 974 } vmx_capability;
 975
 976 #define VMX_SEGMENT_FIELD(seg)                                  \
 977         [VCPU_SREG_##seg] = {                                   \
 978                 .selector = GUEST_##seg##_SELECTOR,             \
 979                 .base = GUEST_##seg##_BASE,                     \
 980                 .limit = GUEST_##seg##_LIMIT,                   \
 981                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 982         }
 983
 984 static const struct kvm_vmx_segment_field {
 985         unsigned selector;
 986         unsigned base;
 987         unsigned limit;
 988         unsigned ar_bytes;
 989 } kvm_vmx_segment_fields[] = {
 990         VMX_SEGMENT_FIELD(CS),
 991         VMX_SEGMENT_FIELD(DS),
 992         VMX_SEGMENT_FIELD(ES),
 993         VMX_SEGMENT_FIELD(FS),
 994         VMX_SEGMENT_FIELD(GS),
 995         VMX_SEGMENT_FIELD(SS),
 996         VMX_SEGMENT_FIELD(TR),
 997         VMX_SEGMENT_FIELD(LDTR),
 998 };
 999
1000 static u64 host_efer;
1001
1002 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1003
1004 /*
1005  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1006  * away by decrementing the array size.
1007  */
1008 static const u32 vmx_msr_index[] = {
1009 #ifdef CONFIG_X86_64
1010         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1011 #endif
1012         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1013 };
1014
1015 DEFINE_STATIC_KEY_FALSE(enable_evmcs);
1016
1017 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1018
1019 #define KVM_EVMCS_VERSION 1
1020
1021 #if IS_ENABLED(CONFIG_HYPERV)
1022 static bool __read_mostly enlightened_vmcs = true;
1023 module_param(enlightened_vmcs, bool, 0444);
1024
1025 static inline void evmcs_write64(unsigned long field, u64 value)
1026 {
1027         u16 clean_field;
1028         int offset = get_evmcs_offset(field, &clean_field);
1029
1030         if (offset < 0)
1031                 return;
1032
1033         *(u64 *)((char *)current_evmcs + offset) = value;
1034
1035         current_evmcs->hv_clean_fields &= ~clean_field;
1036 }
1037
1038 static inline void evmcs_write32(unsigned long field, u32 value)
1039 {
1040         u16 clean_field;
1041         int offset = get_evmcs_offset(field, &clean_field);
1042
1043         if (offset < 0)
1044                 return;
1045
1046         *(u32 *)((char *)current_evmcs + offset) = value;
1047         current_evmcs->hv_clean_fields &= ~clean_field;
1048 }
1049
1050 static inline void evmcs_write16(unsigned long field, u16 value)
1051 {
1052         u16 clean_field;
1053         int offset = get_evmcs_offset(field, &clean_field);
1054
1055         if (offset < 0)
1056                 return;
1057
1058         *(u16 *)((char *)current_evmcs + offset) = value;
1059         current_evmcs->hv_clean_fields &= ~clean_field;
1060 }
1061
1062 static inline u64 evmcs_read64(unsigned long field)
1063 {
1064         int offset = get_evmcs_offset(field, NULL);
1065
1066         if (offset < 0)
1067                 return 0;
1068
1069         return *(u64 *)((char *)current_evmcs + offset);
1070 }
1071
1072 static inline u32 evmcs_read32(unsigned long field)
1073 {
1074         int offset = get_evmcs_offset(field, NULL);
1075
1076         if (offset < 0)
1077                 return 0;
1078
1079         return *(u32 *)((char *)current_evmcs + offset);
1080 }
1081
1082 static inline u16 evmcs_read16(unsigned long field)
1083 {
1084         int offset = get_evmcs_offset(field, NULL);
1085
1086         if (offset < 0)
1087                 return 0;
1088
1089         return *(u16 *)((char *)current_evmcs + offset);
1090 }
1091
1092 static void evmcs_load(u64 phys_addr)
1093 {
1094         struct hv_vp_assist_page *vp_ap =
1095                 hv_get_vp_assist_page(smp_processor_id());
1096
1097         vp_ap->current_nested_vmcs = phys_addr;
1098         vp_ap->enlighten_vmentry = 1;
1099 }
1100
1101 static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
1102 {
1103         /*
1104          * Enlightened VMCSv1 doesn't support these:
1105          *
1106          *      POSTED_INTR_NV                  = 0x00000002,
1107          *      GUEST_INTR_STATUS               = 0x00000810,
1108          *      APIC_ACCESS_ADDR                = 0x00002014,
1109          *      POSTED_INTR_DESC_ADDR           = 0x00002016,
1110          *      EOI_EXIT_BITMAP0                = 0x0000201c,
1111          *      EOI_EXIT_BITMAP1                = 0x0000201e,
1112          *      EOI_EXIT_BITMAP2                = 0x00002020,
1113          *      EOI_EXIT_BITMAP3                = 0x00002022,
1114          */
1115         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
1116         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1117                 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1118         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1119                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1120         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1121                 ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
1122
1123         /*
1124          *      GUEST_PML_INDEX                 = 0x00000812,
1125          *      PML_ADDRESS                     = 0x0000200e,
1126          */
1127         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML;
1128
1129         /*      VM_FUNCTION_CONTROL             = 0x00002018, */
1130         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC;
1131
1132         /*
1133          *      EPTP_LIST_ADDRESS               = 0x00002024,
1134          *      VMREAD_BITMAP                   = 0x00002026,
1135          *      VMWRITE_BITMAP                  = 0x00002028,
1136          */
1137         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS;
1138
1139         /*
1140          *      TSC_MULTIPLIER                  = 0x00002032,
1141          */
1142         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING;
1143
1144         /*
1145          *      PLE_GAP                         = 0x00004020,
1146          *      PLE_WINDOW                      = 0x00004022,
1147          */
1148         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1149
1150         /*
1151          *      VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
1152          */
1153         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
1154
1155         /*
1156          *      GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
1157          *      HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
1158          */
1159         vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
1160         vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
1161
1162         /*
1163          * Currently unsupported in KVM:
1164          *      GUEST_IA32_RTIT_CTL             = 0x00002814,
1165          */
1166 }
1167 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1168 static inline void evmcs_write64(unsigned long field, u64 value) {}
1169 static inline void evmcs_write32(unsigned long field, u32 value) {}
1170 static inline void evmcs_write16(unsigned long field, u16 value) {}
1171 static inline u64 evmcs_read64(unsigned long field) { return 0; }
1172 static inline u32 evmcs_read32(unsigned long field) { return 0; }
1173 static inline u16 evmcs_read16(unsigned long field) { return 0; }
1174 static inline void evmcs_load(u64 phys_addr) {}
1175 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
1176 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1177
1178 static inline bool is_exception_n(u32 intr_info, u8 vector)
1179 {
1180         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1181                              INTR_INFO_VALID_MASK)) ==
1182                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1183 }
1184
1185 static inline bool is_debug(u32 intr_info)
1186 {
1187         return is_exception_n(intr_info, DB_VECTOR);
1188 }
1189
1190 static inline bool is_breakpoint(u32 intr_info)
1191 {
1192         return is_exception_n(intr_info, BP_VECTOR);
1193 }
1194
1195 static inline bool is_page_fault(u32 intr_info)
1196 {
1197         return is_exception_n(intr_info, PF_VECTOR);
1198 }
1199
1200 static inline bool is_no_device(u32 intr_info)
1201 {
1202         return is_exception_n(intr_info, NM_VECTOR);
1203 }
1204
1205 static inline bool is_invalid_opcode(u32 intr_info)
1206 {
1207         return is_exception_n(intr_info, UD_VECTOR);
1208 }
1209
1210 static inline bool is_gp_fault(u32 intr_info)
1211 {
1212         return is_exception_n(intr_info, GP_VECTOR);
1213 }
1214
1215 static inline bool is_external_interrupt(u32 intr_info)
1216 {
1217         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1218                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1219 }
1220
1221 static inline bool is_machine_check(u32 intr_info)
1222 {
1223         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1224                              INTR_INFO_VALID_MASK)) ==
1225                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1226 }
1227
1228 /* Undocumented: icebp/int1 */
1229 static inline bool is_icebp(u32 intr_info)
1230 {
1231         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1232                 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1233 }
1234
1235 static inline bool cpu_has_vmx_msr_bitmap(void)
1236 {
1237         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1238 }
1239
1240 static inline bool cpu_has_vmx_tpr_shadow(void)
1241 {
1242         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1243 }
1244
1245 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1246 {
1247         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1248 }
1249
1250 static inline bool cpu_has_secondary_exec_ctrls(void)
1251 {
1252         return vmcs_config.cpu_based_exec_ctrl &
1253                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1254 }
1255
1256 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1257 {
1258         return vmcs_config.cpu_based_2nd_exec_ctrl &
1259                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1260 }
1261
1262 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1263 {
1264         return vmcs_config.cpu_based_2nd_exec_ctrl &
1265                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1266 }
1267
1268 static inline bool cpu_has_vmx_apic_register_virt(void)
1269 {
1270         return vmcs_config.cpu_based_2nd_exec_ctrl &
1271                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1272 }
1273
1274 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1275 {
1276         return vmcs_config.cpu_based_2nd_exec_ctrl &
1277                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1278 }
1279
1280 /*
1281  * Comment's format: document - errata name - stepping - processor name.
1282  * Refer from
1283  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1284  */
1285 static u32 vmx_preemption_cpu_tfms[] = {
1286 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1287 0x000206E6,
1288 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1289 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1290 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1291 0x00020652,
1292 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1293 0x00020655,
1294 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1295 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1296 /*
1297  * 320767.pdf - AAP86  - B1 -
1298  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1299  */
1300 0x000106E5,
1301 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1302 0x000106A0,
1303 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1304 0x000106A1,
1305 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1306 0x000106A4,
1307  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1308  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1309  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1310 0x000106A5,
1311 };
1312
1313 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1314 {
1315         u32 eax = cpuid_eax(0x00000001), i;
1316
1317         /* Clear the reserved bits */
1318         eax &= ~(0x3U << 14 | 0xfU << 28);
1319         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1320                 if (eax == vmx_preemption_cpu_tfms[i])
1321                         return true;
1322
1323         return false;
1324 }
1325
1326 static inline bool cpu_has_vmx_preemption_timer(void)
1327 {
1328         return vmcs_config.pin_based_exec_ctrl &
1329                 PIN_BASED_VMX_PREEMPTION_TIMER;
1330 }
1331
1332 static inline bool cpu_has_vmx_posted_intr(void)
1333 {
1334         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1335                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1336 }
1337
1338 static inline bool cpu_has_vmx_apicv(void)
1339 {
1340         return cpu_has_vmx_apic_register_virt() &&
1341                 cpu_has_vmx_virtual_intr_delivery() &&
1342                 cpu_has_vmx_posted_intr();
1343 }
1344
1345 static inline bool cpu_has_vmx_flexpriority(void)
1346 {
1347         return cpu_has_vmx_tpr_shadow() &&
1348                 cpu_has_vmx_virtualize_apic_accesses();
1349 }
1350
1351 static inline bool cpu_has_vmx_ept_execute_only(void)
1352 {
1353         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1354 }
1355
1356 static inline bool cpu_has_vmx_ept_2m_page(void)
1357 {
1358         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1359 }
1360
1361 static inline bool cpu_has_vmx_ept_1g_page(void)
1362 {
1363         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1364 }
1365
1366 static inline bool cpu_has_vmx_ept_4levels(void)
1367 {
1368         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1369 }
1370
1371 static inline bool cpu_has_vmx_ept_mt_wb(void)
1372 {
1373         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1374 }
1375
1376 static inline bool cpu_has_vmx_ept_5levels(void)
1377 {
1378         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1379 }
1380
1381 static inline bool cpu_has_vmx_ept_ad_bits(void)
1382 {
1383         return vmx_capability.ept & VMX_EPT_AD_BIT;
1384 }
1385
1386 static inline bool cpu_has_vmx_invept_context(void)
1387 {
1388         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1389 }
1390
1391 static inline bool cpu_has_vmx_invept_global(void)
1392 {
1393         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1394 }
1395
1396 static inline bool cpu_has_vmx_invvpid_single(void)
1397 {
1398         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1399 }
1400
1401 static inline bool cpu_has_vmx_invvpid_global(void)
1402 {
1403         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1404 }
1405
1406 static inline bool cpu_has_vmx_invvpid(void)
1407 {
1408         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1409 }
1410
1411 static inline bool cpu_has_vmx_ept(void)
1412 {
1413         return vmcs_config.cpu_based_2nd_exec_ctrl &
1414                 SECONDARY_EXEC_ENABLE_EPT;
1415 }
1416
1417 static inline bool cpu_has_vmx_unrestricted_guest(void)
1418 {
1419         return vmcs_config.cpu_based_2nd_exec_ctrl &
1420                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1421 }
1422
1423 static inline bool cpu_has_vmx_ple(void)
1424 {
1425         return vmcs_config.cpu_based_2nd_exec_ctrl &
1426                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1427 }
1428
1429 static inline bool cpu_has_vmx_basic_inout(void)
1430 {
1431         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1432 }
1433
1434 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1435 {
1436         return flexpriority_enabled && lapic_in_kernel(vcpu);
1437 }
1438
1439 static inline bool cpu_has_vmx_vpid(void)
1440 {
1441         return vmcs_config.cpu_based_2nd_exec_ctrl &
1442                 SECONDARY_EXEC_ENABLE_VPID;
1443 }
1444
1445 static inline bool cpu_has_vmx_rdtscp(void)
1446 {
1447         return vmcs_config.cpu_based_2nd_exec_ctrl &
1448                 SECONDARY_EXEC_RDTSCP;
1449 }
1450
1451 static inline bool cpu_has_vmx_invpcid(void)
1452 {
1453         return vmcs_config.cpu_based_2nd_exec_ctrl &
1454                 SECONDARY_EXEC_ENABLE_INVPCID;
1455 }
1456
1457 static inline bool cpu_has_virtual_nmis(void)
1458 {
1459         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1460 }
1461
1462 static inline bool cpu_has_vmx_wbinvd_exit(void)
1463 {
1464         return vmcs_config.cpu_based_2nd_exec_ctrl &
1465                 SECONDARY_EXEC_WBINVD_EXITING;
1466 }
1467
1468 static inline bool cpu_has_vmx_shadow_vmcs(void)
1469 {
1470         u64 vmx_msr;
1471         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1472         /* check if the cpu supports writing r/o exit information fields */
1473         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1474                 return false;
1475
1476         return vmcs_config.cpu_based_2nd_exec_ctrl &
1477                 SECONDARY_EXEC_SHADOW_VMCS;
1478 }
1479
1480 static inline bool cpu_has_vmx_pml(void)
1481 {
1482         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1483 }
1484
1485 static inline bool cpu_has_vmx_tsc_scaling(void)
1486 {
1487         return vmcs_config.cpu_based_2nd_exec_ctrl &
1488                 SECONDARY_EXEC_TSC_SCALING;
1489 }
1490
1491 static inline bool cpu_has_vmx_vmfunc(void)
1492 {
1493         return vmcs_config.cpu_based_2nd_exec_ctrl &
1494                 SECONDARY_EXEC_ENABLE_VMFUNC;
1495 }
1496
1497 static inline bool report_flexpriority(void)
1498 {
1499         return flexpriority_enabled;
1500 }
1501
1502 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1503 {
1504         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
1505 }
1506
1507 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1508 {
1509         return vmcs12->cpu_based_vm_exec_control & bit;
1510 }
1511
1512 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1513 {
1514         return (vmcs12->cpu_based_vm_exec_control &
1515                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1516                 (vmcs12->secondary_vm_exec_control & bit);
1517 }
1518
1519 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1520 {
1521         return vmcs12->pin_based_vm_exec_control &
1522                 PIN_BASED_VMX_PREEMPTION_TIMER;
1523 }
1524
1525 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
1526 {
1527         return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
1528 }
1529
1530 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1531 {
1532         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1533 }
1534
1535 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1536 {
1537         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1538 }
1539
1540 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1541 {
1542         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1543 }
1544
1545 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1546 {
1547         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1548 }
1549
1550 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1551 {
1552         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1553 }
1554
1555 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1556 {
1557         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1558 }
1559
1560 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1561 {
1562         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1563 }
1564
1565 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1566 {
1567         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1568 }
1569
1570 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1571 {
1572         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1573 }
1574
1575 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1576 {
1577         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1578 }
1579
1580 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1581 {
1582         return nested_cpu_has_vmfunc(vmcs12) &&
1583                 (vmcs12->vm_function_control &
1584                  VMX_VMFUNC_EPTP_SWITCHING);
1585 }
1586
1587 static inline bool is_nmi(u32 intr_info)
1588 {
1589         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1590                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1591 }
1592
1593 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1594                               u32 exit_intr_info,
1595                               unsigned long exit_qualification);
1596 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1597                         struct vmcs12 *vmcs12,
1598                         u32 reason, unsigned long qualification);
1599
1600 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1601 {
1602         int i;
1603
1604         for (i = 0; i < vmx->nmsrs; ++i)
1605                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1606                         return i;
1607         return -1;
1608 }
1609
1610 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1611 {
1612     struct {
1613         u64 vpid : 16;
1614         u64 rsvd : 48;
1615         u64 gva;
1616     } operand = { vpid, 0, gva };
1617
1618     asm volatile (__ex(ASM_VMX_INVVPID)
1619                   /* CF==1 or ZF==1 --> rc = -1 */
1620                   "; ja 1f ; ud2 ; 1:"
1621                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1622 }
1623
1624 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1625 {
1626         struct {
1627                 u64 eptp, gpa;
1628         } operand = {eptp, gpa};
1629
1630         asm volatile (__ex(ASM_VMX_INVEPT)
1631                         /* CF==1 or ZF==1 --> rc = -1 */
1632                         "; ja 1f ; ud2 ; 1:\n"
1633                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1634 }
1635
1636 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1637 {
1638         int i;
1639
1640         i = __find_msr_index(vmx, msr);
1641         if (i >= 0)
1642                 return &vmx->guest_msrs[i];
1643         return NULL;
1644 }
1645
1646 static void vmcs_clear(struct vmcs *vmcs)
1647 {
1648         u64 phys_addr = __pa(vmcs);
1649         u8 error;
1650
1651         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1652                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1653                       : "cc", "memory");
1654         if (error)
1655                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1656                        vmcs, phys_addr);
1657 }
1658
1659 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1660 {
1661         vmcs_clear(loaded_vmcs->vmcs);
1662         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1663                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1664         loaded_vmcs->cpu = -1;
1665         loaded_vmcs->launched = 0;
1666 }
1667
1668 static void vmcs_load(struct vmcs *vmcs)
1669 {
1670         u64 phys_addr = __pa(vmcs);
1671         u8 error;
1672
1673         if (static_branch_unlikely(&enable_evmcs))
1674                 return evmcs_load(phys_addr);
1675
1676         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1677                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1678                         : "cc", "memory");
1679         if (error)
1680                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1681                        vmcs, phys_addr);
1682 }
1683
1684 #ifdef CONFIG_KEXEC_CORE
1685 /*
1686  * This bitmap is used to indicate whether the vmclear
1687  * operation is enabled on all cpus. All disabled by
1688  * default.
1689  */
1690 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1691
1692 static inline void crash_enable_local_vmclear(int cpu)
1693 {
1694         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1695 }
1696
1697 static inline void crash_disable_local_vmclear(int cpu)
1698 {
1699         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1700 }
1701
1702 static inline int crash_local_vmclear_enabled(int cpu)
1703 {
1704         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1705 }
1706
1707 static void crash_vmclear_local_loaded_vmcss(void)
1708 {
1709         int cpu = raw_smp_processor_id();
1710         struct loaded_vmcs *v;
1711
1712         if (!crash_local_vmclear_enabled(cpu))
1713                 return;
1714
1715         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1716                             loaded_vmcss_on_cpu_link)
1717                 vmcs_clear(v->vmcs);
1718 }
1719 #else
1720 static inline void crash_enable_local_vmclear(int cpu) { }
1721 static inline void crash_disable_local_vmclear(int cpu) { }
1722 #endif /* CONFIG_KEXEC_CORE */
1723
1724 static void __loaded_vmcs_clear(void *arg)
1725 {
1726         struct loaded_vmcs *loaded_vmcs = arg;
1727         int cpu = raw_smp_processor_id();
1728
1729         if (loaded_vmcs->cpu != cpu)
1730                 return; /* vcpu migration can race with cpu offline */
1731         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1732                 per_cpu(current_vmcs, cpu) = NULL;
1733         crash_disable_local_vmclear(cpu);
1734         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1735
1736         /*
1737          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1738          * is before setting loaded_vmcs->vcpu to -1 which is done in
1739          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1740          * then adds the vmcs into percpu list before it is deleted.
1741          */
1742         smp_wmb();
1743
1744         loaded_vmcs_init(loaded_vmcs);
1745         crash_enable_local_vmclear(cpu);
1746 }
1747
1748 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1749 {
1750         int cpu = loaded_vmcs->cpu;
1751
1752         if (cpu != -1)
1753                 smp_call_function_single(cpu,
1754                          __loaded_vmcs_clear, loaded_vmcs, 1);
1755 }
1756
1757 static inline void vpid_sync_vcpu_single(int vpid)
1758 {
1759         if (vpid == 0)
1760                 return;
1761
1762         if (cpu_has_vmx_invvpid_single())
1763                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1764 }
1765
1766 static inline void vpid_sync_vcpu_global(void)
1767 {
1768         if (cpu_has_vmx_invvpid_global())
1769                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1770 }
1771
1772 static inline void vpid_sync_context(int vpid)
1773 {
1774         if (cpu_has_vmx_invvpid_single())
1775                 vpid_sync_vcpu_single(vpid);
1776         else
1777                 vpid_sync_vcpu_global();
1778 }
1779
1780 static inline void ept_sync_global(void)
1781 {
1782         __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1783 }
1784
1785 static inline void ept_sync_context(u64 eptp)
1786 {
1787         if (cpu_has_vmx_invept_context())
1788                 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1789         else
1790                 ept_sync_global();
1791 }
1792
1793 static __always_inline void vmcs_check16(unsigned long field)
1794 {
1795         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1796                          "16-bit accessor invalid for 64-bit field");
1797         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1798                          "16-bit accessor invalid for 64-bit high field");
1799         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1800                          "16-bit accessor invalid for 32-bit high field");
1801         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1802                          "16-bit accessor invalid for natural width field");
1803 }
1804
1805 static __always_inline void vmcs_check32(unsigned long field)
1806 {
1807         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1808                          "32-bit accessor invalid for 16-bit field");
1809         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1810                          "32-bit accessor invalid for natural width field");
1811 }
1812
1813 static __always_inline void vmcs_check64(unsigned long field)
1814 {
1815         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1816                          "64-bit accessor invalid for 16-bit field");
1817         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1818                          "64-bit accessor invalid for 64-bit high field");
1819         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1820                          "64-bit accessor invalid for 32-bit field");
1821         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1822                          "64-bit accessor invalid for natural width field");
1823 }
1824
1825 static __always_inline void vmcs_checkl(unsigned long field)
1826 {
1827         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1828                          "Natural width accessor invalid for 16-bit field");
1829         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1830                          "Natural width accessor invalid for 64-bit field");
1831         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1832                          "Natural width accessor invalid for 64-bit high field");
1833         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1834                          "Natural width accessor invalid for 32-bit field");
1835 }
1836
1837 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1838 {
1839         unsigned long value;
1840
1841         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1842                       : "=a"(value) : "d"(field) : "cc");
1843         return value;
1844 }
1845
1846 static __always_inline u16 vmcs_read16(unsigned long field)
1847 {
1848         vmcs_check16(field);
1849         if (static_branch_unlikely(&enable_evmcs))
1850                 return evmcs_read16(field);
1851         return __vmcs_readl(field);
1852 }
1853
1854 static __always_inline u32 vmcs_read32(unsigned long field)
1855 {
1856         vmcs_check32(field);
1857         if (static_branch_unlikely(&enable_evmcs))
1858                 return evmcs_read32(field);
1859         return __vmcs_readl(field);
1860 }
1861
1862 static __always_inline u64 vmcs_read64(unsigned long field)
1863 {
1864         vmcs_check64(field);
1865         if (static_branch_unlikely(&enable_evmcs))
1866                 return evmcs_read64(field);
1867 #ifdef CONFIG_X86_64
1868         return __vmcs_readl(field);
1869 #else
1870         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1871 #endif
1872 }
1873
1874 static __always_inline unsigned long vmcs_readl(unsigned long field)
1875 {
1876         vmcs_checkl(field);
1877         if (static_branch_unlikely(&enable_evmcs))
1878                 return evmcs_read64(field);
1879         return __vmcs_readl(field);
1880 }
1881
1882 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1883 {
1884         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1885                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1886         dump_stack();
1887 }
1888
1889 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1890 {
1891         u8 error;
1892
1893         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1894                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1895         if (unlikely(error))
1896                 vmwrite_error(field, value);
1897 }
1898
1899 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1900 {
1901         vmcs_check16(field);
1902         if (static_branch_unlikely(&enable_evmcs))
1903                 return evmcs_write16(field, value);
1904
1905         __vmcs_writel(field, value);
1906 }
1907
1908 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1909 {
1910         vmcs_check32(field);
1911         if (static_branch_unlikely(&enable_evmcs))
1912                 return evmcs_write32(field, value);
1913
1914         __vmcs_writel(field, value);
1915 }
1916
1917 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1918 {
1919         vmcs_check64(field);
1920         if (static_branch_unlikely(&enable_evmcs))
1921                 return evmcs_write64(field, value);
1922
1923         __vmcs_writel(field, value);
1924 #ifndef CONFIG_X86_64
1925         asm volatile ("");
1926         __vmcs_writel(field+1, value >> 32);
1927 #endif
1928 }
1929
1930 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1931 {
1932         vmcs_checkl(field);
1933         if (static_branch_unlikely(&enable_evmcs))
1934                 return evmcs_write64(field, value);
1935
1936         __vmcs_writel(field, value);
1937 }
1938
1939 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1940 {
1941         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1942                          "vmcs_clear_bits does not support 64-bit fields");
1943         if (static_branch_unlikely(&enable_evmcs))
1944                 return evmcs_write32(field, evmcs_read32(field) & ~mask);
1945
1946         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1947 }
1948
1949 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1950 {
1951         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1952                          "vmcs_set_bits does not support 64-bit fields");
1953         if (static_branch_unlikely(&enable_evmcs))
1954                 return evmcs_write32(field, evmcs_read32(field) | mask);
1955
1956         __vmcs_writel(field, __vmcs_readl(field) | mask);
1957 }
1958
1959 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1960 {
1961         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1962 }
1963
1964 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1965 {
1966         vmcs_write32(VM_ENTRY_CONTROLS, val);
1967         vmx->vm_entry_controls_shadow = val;
1968 }
1969
1970 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1971 {
1972         if (vmx->vm_entry_controls_shadow != val)
1973                 vm_entry_controls_init(vmx, val);
1974 }
1975
1976 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1977 {
1978         return vmx->vm_entry_controls_shadow;
1979 }
1980
1981
1982 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1983 {
1984         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1985 }
1986
1987 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1988 {
1989         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1990 }
1991
1992 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1993 {
1994         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1995 }
1996
1997 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1998 {
1999         vmcs_write32(VM_EXIT_CONTROLS, val);
2000         vmx->vm_exit_controls_shadow = val;
2001 }
2002
2003 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2004 {
2005         if (vmx->vm_exit_controls_shadow != val)
2006                 vm_exit_controls_init(vmx, val);
2007 }
2008
2009 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2010 {
2011         return vmx->vm_exit_controls_shadow;
2012 }
2013
2014
2015 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2016 {
2017         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2018 }
2019
2020 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2021 {
2022         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2023 }
2024
2025 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2026 {
2027         vmx->segment_cache.bitmask = 0;
2028 }
2029
2030 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2031                                        unsigned field)
2032 {
2033         bool ret;
2034         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2035
2036         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2037                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2038                 vmx->segment_cache.bitmask = 0;
2039         }
2040         ret = vmx->segment_cache.bitmask & mask;
2041         vmx->segment_cache.bitmask |= mask;
2042         return ret;
2043 }
2044
2045 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2046 {
2047         u16 *p = &vmx->segment_cache.seg[seg].selector;
2048
2049         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2050                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2051         return *p;
2052 }
2053
2054 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2055 {
2056         ulong *p = &vmx->segment_cache.seg[seg].base;
2057
2058         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2059                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2060         return *p;
2061 }
2062
2063 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2064 {
2065         u32 *p = &vmx->segment_cache.seg[seg].limit;
2066
2067         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2068                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2069         return *p;
2070 }
2071
2072 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2073 {
2074         u32 *p = &vmx->segment_cache.seg[seg].ar;
2075
2076         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2077                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2078         return *p;
2079 }
2080
2081 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2082 {
2083         u32 eb;
2084
2085         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2086              (1u << DB_VECTOR) | (1u << AC_VECTOR);
2087         /*
2088          * Guest access to VMware backdoor ports could legitimately
2089          * trigger #GP because of TSS I/O permission bitmap.
2090          * We intercept those #GP and allow access to them anyway
2091          * as VMware does.
2092          */
2093         if (enable_vmware_backdoor)
2094                 eb |= (1u << GP_VECTOR);
2095         if ((vcpu->guest_debug &
2096              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2097             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2098                 eb |= 1u << BP_VECTOR;
2099         if (to_vmx(vcpu)->rmode.vm86_active)
2100                 eb = ~0;
2101         if (enable_ept)
2102                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2103
2104         /* When we are running a nested L2 guest and L1 specified for it a
2105          * certain exception bitmap, we must trap the same exceptions and pass
2106          * them to L1. When running L2, we will only handle the exceptions
2107          * specified above if L1 did not want them.
2108          */
2109         if (is_guest_mode(vcpu))
2110                 eb |= get_vmcs12(vcpu)->exception_bitmap;
2111
2112         vmcs_write32(EXCEPTION_BITMAP, eb);
2113 }
2114
2115 /*
2116  * Check if MSR is intercepted for currently loaded MSR bitmap.
2117  */
2118 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2119 {
2120         unsigned long *msr_bitmap;
2121         int f = sizeof(unsigned long);
2122
2123         if (!cpu_has_vmx_msr_bitmap())
2124                 return true;
2125
2126         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2127
2128         if (msr <= 0x1fff) {
2129                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2130         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2131                 msr &= 0x1fff;
2132                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2133         }
2134
2135         return true;
2136 }
2137
2138 /*
2139  * Check if MSR is intercepted for L01 MSR bitmap.
2140  */
2141 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2142 {
2143         unsigned long *msr_bitmap;
2144         int f = sizeof(unsigned long);
2145
2146         if (!cpu_has_vmx_msr_bitmap())
2147                 return true;
2148
2149         msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2150
2151         if (msr <= 0x1fff) {
2152                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2153         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2154                 msr &= 0x1fff;
2155                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2156         }
2157
2158         return true;
2159 }
2160
2161 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2162                 unsigned long entry, unsigned long exit)
2163 {
2164         vm_entry_controls_clearbit(vmx, entry);
2165         vm_exit_controls_clearbit(vmx, exit);
2166 }
2167
2168 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2169 {
2170         unsigned i;
2171         struct msr_autoload *m = &vmx->msr_autoload;
2172
2173         switch (msr) {
2174         case MSR_EFER:
2175                 if (cpu_has_load_ia32_efer) {
2176                         clear_atomic_switch_msr_special(vmx,
2177                                         VM_ENTRY_LOAD_IA32_EFER,
2178                                         VM_EXIT_LOAD_IA32_EFER);
2179                         return;
2180                 }
2181                 break;
2182         case MSR_CORE_PERF_GLOBAL_CTRL:
2183                 if (cpu_has_load_perf_global_ctrl) {
2184                         clear_atomic_switch_msr_special(vmx,
2185                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2186                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2187                         return;
2188                 }
2189                 break;
2190         }
2191
2192         for (i = 0; i < m->nr; ++i)
2193                 if (m->guest[i].index == msr)
2194                         break;
2195
2196         if (i == m->nr)
2197                 return;
2198         --m->nr;
2199         m->guest[i] = m->guest[m->nr];
2200         m->host[i] = m->host[m->nr];
2201         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2202         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2203 }
2204
2205 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2206                 unsigned long entry, unsigned long exit,
2207                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2208                 u64 guest_val, u64 host_val)
2209 {
2210         vmcs_write64(guest_val_vmcs, guest_val);
2211         vmcs_write64(host_val_vmcs, host_val);
2212         vm_entry_controls_setbit(vmx, entry);
2213         vm_exit_controls_setbit(vmx, exit);
2214 }
2215
2216 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2217                                   u64 guest_val, u64 host_val)
2218 {
2219         unsigned i;
2220         struct msr_autoload *m = &vmx->msr_autoload;
2221
2222         switch (msr) {
2223         case MSR_EFER:
2224                 if (cpu_has_load_ia32_efer) {
2225                         add_atomic_switch_msr_special(vmx,
2226                                         VM_ENTRY_LOAD_IA32_EFER,
2227                                         VM_EXIT_LOAD_IA32_EFER,
2228                                         GUEST_IA32_EFER,
2229                                         HOST_IA32_EFER,
2230                                         guest_val, host_val);
2231                         return;
2232                 }
2233                 break;
2234         case MSR_CORE_PERF_GLOBAL_CTRL:
2235                 if (cpu_has_load_perf_global_ctrl) {
2236                         add_atomic_switch_msr_special(vmx,
2237                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2238                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2239                                         GUEST_IA32_PERF_GLOBAL_CTRL,
2240                                         HOST_IA32_PERF_GLOBAL_CTRL,
2241                                         guest_val, host_val);
2242                         return;
2243                 }
2244                 break;
2245         case MSR_IA32_PEBS_ENABLE:
2246                 /* PEBS needs a quiescent period after being disabled (to write
2247                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
2248                  * provide that period, so a CPU could write host's record into
2249                  * guest's memory.
2250                  */
2251                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2252         }
2253
2254         for (i = 0; i < m->nr; ++i)
2255                 if (m->guest[i].index == msr)
2256                         break;
2257
2258         if (i == NR_AUTOLOAD_MSRS) {
2259                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2260                                 "Can't add msr %x\n", msr);
2261                 return;
2262         } else if (i == m->nr) {
2263                 ++m->nr;
2264                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2265                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2266         }
2267
2268         m->guest[i].index = msr;
2269         m->guest[i].value = guest_val;
2270         m->host[i].index = msr;
2271         m->host[i].value = host_val;
2272 }
2273
2274 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2275 {
2276         u64 guest_efer = vmx->vcpu.arch.efer;
2277         u64 ignore_bits = 0;
2278
2279         if (!enable_ept) {
2280                 /*
2281                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2282                  * host CPUID is more efficient than testing guest CPUID
2283                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2284                  */
2285                 if (boot_cpu_has(X86_FEATURE_SMEP))
2286                         guest_efer |= EFER_NX;
2287                 else if (!(guest_efer & EFER_NX))
2288                         ignore_bits |= EFER_NX;
2289         }
2290
2291         /*
2292          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2293          */
2294         ignore_bits |= EFER_SCE;
2295 #ifdef CONFIG_X86_64
2296         ignore_bits |= EFER_LMA | EFER_LME;
2297         /* SCE is meaningful only in long mode on Intel */
2298         if (guest_efer & EFER_LMA)
2299                 ignore_bits &= ~(u64)EFER_SCE;
2300 #endif
2301
2302         clear_atomic_switch_msr(vmx, MSR_EFER);
2303
2304         /*
2305          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2306          * On CPUs that support "load IA32_EFER", always switch EFER
2307          * atomically, since it's faster than switching it manually.
2308          */
2309         if (cpu_has_load_ia32_efer ||
2310             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2311                 if (!(guest_efer & EFER_LMA))
2312                         guest_efer &= ~EFER_LME;
2313                 if (guest_efer != host_efer)
2314                         add_atomic_switch_msr(vmx, MSR_EFER,
2315                                               guest_efer, host_efer);
2316                 return false;
2317         } else {
2318                 guest_efer &= ~ignore_bits;
2319                 guest_efer |= host_efer & ignore_bits;
2320
2321                 vmx->guest_msrs[efer_offset].data = guest_efer;
2322                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2323
2324                 return true;
2325         }
2326 }
2327
2328 #ifdef CONFIG_X86_32
2329 /*
2330  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2331  * VMCS rather than the segment table.  KVM uses this helper to figure
2332  * out the current bases to poke them into the VMCS before entry.
2333  */
2334 static unsigned long segment_base(u16 selector)
2335 {
2336         struct desc_struct *table;
2337         unsigned long v;
2338
2339         if (!(selector & ~SEGMENT_RPL_MASK))
2340                 return 0;
2341
2342         table = get_current_gdt_ro();
2343
2344         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2345                 u16 ldt_selector = kvm_read_ldt();
2346
2347                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2348                         return 0;
2349
2350                 table = (struct desc_struct *)segment_base(ldt_selector);
2351         }
2352         v = get_desc_base(&table[selector >> 3]);
2353         return v;
2354 }
2355 #endif
2356
2357 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2358 {
2359         struct vcpu_vmx *vmx = to_vmx(vcpu);
2360 #ifdef CONFIG_X86_64
2361         int cpu = raw_smp_processor_id();
2362 #endif
2363         int i;
2364
2365         if (vmx->host_state.loaded)
2366                 return;
2367
2368         vmx->host_state.loaded = 1;
2369         /*
2370          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2371          * allow segment selectors with cpl > 0 or ti == 1.
2372          */
2373         vmx->host_state.ldt_sel = kvm_read_ldt();
2374         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2375
2376 #ifdef CONFIG_X86_64
2377         save_fsgs_for_kvm();
2378         vmx->host_state.fs_sel = current->thread.fsindex;
2379         vmx->host_state.gs_sel = current->thread.gsindex;
2380 #else
2381         savesegment(fs, vmx->host_state.fs_sel);
2382         savesegment(gs, vmx->host_state.gs_sel);
2383 #endif
2384         if (!(vmx->host_state.fs_sel & 7)) {
2385                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2386                 vmx->host_state.fs_reload_needed = 0;
2387         } else {
2388                 vmcs_write16(HOST_FS_SELECTOR, 0);
2389                 vmx->host_state.fs_reload_needed = 1;
2390         }
2391         if (!(vmx->host_state.gs_sel & 7))
2392                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2393         else {
2394                 vmcs_write16(HOST_GS_SELECTOR, 0);
2395                 vmx->host_state.gs_ldt_reload_needed = 1;
2396         }
2397
2398 #ifdef CONFIG_X86_64
2399         savesegment(ds, vmx->host_state.ds_sel);
2400         savesegment(es, vmx->host_state.es_sel);
2401
2402         vmcs_writel(HOST_FS_BASE, current->thread.fsbase);
2403         vmcs_writel(HOST_GS_BASE, cpu_kernelmode_gs_base(cpu));
2404
2405         vmx->msr_host_kernel_gs_base = current->thread.gsbase;
2406         if (is_long_mode(&vmx->vcpu))
2407                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2408 #else
2409         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2410         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2411 #endif
2412         if (boot_cpu_has(X86_FEATURE_MPX))
2413                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2414         for (i = 0; i < vmx->save_nmsrs; ++i)
2415                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2416                                    vmx->guest_msrs[i].data,
2417                                    vmx->guest_msrs[i].mask);
2418 }
2419
2420 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2421 {
2422         if (!vmx->host_state.loaded)
2423                 return;
2424
2425         ++vmx->vcpu.stat.host_state_reload;
2426         vmx->host_state.loaded = 0;
2427 #ifdef CONFIG_X86_64
2428         if (is_long_mode(&vmx->vcpu))
2429                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2430 #endif
2431         if (vmx->host_state.gs_ldt_reload_needed) {
2432                 kvm_load_ldt(vmx->host_state.ldt_sel);
2433 #ifdef CONFIG_X86_64
2434                 load_gs_index(vmx->host_state.gs_sel);
2435 #else
2436                 loadsegment(gs, vmx->host_state.gs_sel);
2437 #endif
2438         }
2439         if (vmx->host_state.fs_reload_needed)
2440                 loadsegment(fs, vmx->host_state.fs_sel);
2441 #ifdef CONFIG_X86_64
2442         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2443                 loadsegment(ds, vmx->host_state.ds_sel);
2444                 loadsegment(es, vmx->host_state.es_sel);
2445         }
2446 #endif
2447         invalidate_tss_limit();
2448 #ifdef CONFIG_X86_64
2449         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2450 #endif
2451         if (vmx->host_state.msr_host_bndcfgs)
2452                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2453         load_fixmap_gdt(raw_smp_processor_id());
2454 }
2455
2456 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2457 {
2458         preempt_disable();
2459         __vmx_load_host_state(vmx);
2460         preempt_enable();
2461 }
2462
2463 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2464 {
2465         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2466         struct pi_desc old, new;
2467         unsigned int dest;
2468
2469         /*
2470          * In case of hot-plug or hot-unplug, we may have to undo
2471          * vmx_vcpu_pi_put even if there is no assigned device.  And we
2472          * always keep PI.NDST up to date for simplicity: it makes the
2473          * code easier, and CPU migration is not a fast path.
2474          */
2475         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2476                 return;
2477
2478         /*
2479          * First handle the simple case where no cmpxchg is necessary; just
2480          * allow posting non-urgent interrupts.
2481          *
2482          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2483          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2484          * expects the VCPU to be on the blocked_vcpu_list that matches
2485          * PI.NDST.
2486          */
2487         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2488             vcpu->cpu == cpu) {
2489                 pi_clear_sn(pi_desc);
2490                 return;
2491         }
2492
2493         /* The full case.  */
2494         do {
2495                 old.control = new.control = pi_desc->control;
2496
2497                 dest = cpu_physical_id(cpu);
2498
2499                 if (x2apic_enabled())
2500                         new.ndst = dest;
2501                 else
2502                         new.ndst = (dest << 8) & 0xFF00;
2503
2504                 new.sn = 0;
2505         } while (cmpxchg64(&pi_desc->control, old.control,
2506                            new.control) != old.control);
2507 }
2508
2509 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2510 {
2511         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2512         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2513 }
2514
2515 /*
2516  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2517  * vcpu mutex is already taken.
2518  */
2519 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2520 {
2521         struct vcpu_vmx *vmx = to_vmx(vcpu);
2522         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2523
2524         if (!already_loaded) {
2525                 loaded_vmcs_clear(vmx->loaded_vmcs);
2526                 local_irq_disable();
2527                 crash_disable_local_vmclear(cpu);
2528
2529                 /*
2530                  * Read loaded_vmcs->cpu should be before fetching
2531                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2532                  * See the comments in __loaded_vmcs_clear().
2533                  */
2534                 smp_rmb();
2535
2536                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2537                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2538                 crash_enable_local_vmclear(cpu);
2539                 local_irq_enable();
2540         }
2541
2542         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2543                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2544                 vmcs_load(vmx->loaded_vmcs->vmcs);
2545                 indirect_branch_prediction_barrier();
2546         }
2547
2548         if (!already_loaded) {
2549                 void *gdt = get_current_gdt_ro();
2550                 unsigned long sysenter_esp;
2551
2552                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2553
2554                 /*
2555                  * Linux uses per-cpu TSS and GDT, so set these when switching
2556                  * processors.  See 22.2.4.
2557                  */
2558                 vmcs_writel(HOST_TR_BASE,
2559                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2560                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2561
2562                 /*
2563                  * VM exits change the host TR limit to 0x67 after a VM
2564                  * exit.  This is okay, since 0x67 covers everything except
2565                  * the IO bitmap and have have code to handle the IO bitmap
2566                  * being lost after a VM exit.
2567                  */
2568                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2569
2570                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2571                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2572
2573                 vmx->loaded_vmcs->cpu = cpu;
2574         }
2575
2576         /* Setup TSC multiplier */
2577         if (kvm_has_tsc_control &&
2578             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2579                 decache_tsc_multiplier(vmx);
2580
2581         vmx_vcpu_pi_load(vcpu, cpu);
2582         vmx->host_pkru = read_pkru();
2583         vmx->host_debugctlmsr = get_debugctlmsr();
2584 }
2585
2586 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2587 {
2588         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2589
2590         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2591                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2592                 !kvm_vcpu_apicv_active(vcpu))
2593                 return;
2594
2595         /* Set SN when the vCPU is preempted */
2596         if (vcpu->preempted)
2597                 pi_set_sn(pi_desc);
2598 }
2599
2600 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2601 {
2602         vmx_vcpu_pi_put(vcpu);
2603
2604         __vmx_load_host_state(to_vmx(vcpu));
2605 }
2606
2607 static bool emulation_required(struct kvm_vcpu *vcpu)
2608 {
2609         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2610 }
2611
2612 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2613
2614 /*
2615  * Return the cr0 value that a nested guest would read. This is a combination
2616  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2617  * its hypervisor (cr0_read_shadow).
2618  */
2619 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2620 {
2621         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2622                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2623 }
2624 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2625 {
2626         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2627                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2628 }
2629
2630 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2631 {
2632         unsigned long rflags, save_rflags;
2633
2634         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2635                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2636                 rflags = vmcs_readl(GUEST_RFLAGS);
2637                 if (to_vmx(vcpu)->rmode.vm86_active) {
2638                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2639                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2640                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2641                 }
2642                 to_vmx(vcpu)->rflags = rflags;
2643         }
2644         return to_vmx(vcpu)->rflags;
2645 }
2646
2647 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2648 {
2649         unsigned long old_rflags = vmx_get_rflags(vcpu);
2650
2651         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2652         to_vmx(vcpu)->rflags = rflags;
2653         if (to_vmx(vcpu)->rmode.vm86_active) {
2654                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2655                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2656         }
2657         vmcs_writel(GUEST_RFLAGS, rflags);
2658
2659         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2660                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2661 }
2662
2663 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2664 {
2665         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2666         int ret = 0;
2667
2668         if (interruptibility & GUEST_INTR_STATE_STI)
2669                 ret |= KVM_X86_SHADOW_INT_STI;
2670         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2671                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2672
2673         return ret;
2674 }
2675
2676 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2677 {
2678         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2679         u32 interruptibility = interruptibility_old;
2680
2681         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2682
2683         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2684                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2685         else if (mask & KVM_X86_SHADOW_INT_STI)
2686                 interruptibility |= GUEST_INTR_STATE_STI;
2687
2688         if ((interruptibility != interruptibility_old))
2689                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2690 }
2691
2692 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2693 {
2694         unsigned long rip;
2695
2696         rip = kvm_rip_read(vcpu);
2697         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2698         kvm_rip_write(vcpu, rip);
2699
2700         /* skipping an emulated instruction also counts */
2701         vmx_set_interrupt_shadow(vcpu, 0);
2702 }
2703
2704 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2705                                                unsigned long exit_qual)
2706 {
2707         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2708         unsigned int nr = vcpu->arch.exception.nr;
2709         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2710
2711         if (vcpu->arch.exception.has_error_code) {
2712                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2713                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2714         }
2715
2716         if (kvm_exception_is_soft(nr))
2717                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2718         else
2719                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2720
2721         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2722             vmx_get_nmi_mask(vcpu))
2723                 intr_info |= INTR_INFO_UNBLOCK_NMI;
2724
2725         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2726 }
2727
2728 /*
2729  * KVM wants to inject page-faults which it got to the guest. This function
2730  * checks whether in a nested guest, we need to inject them to L1 or L2.
2731  */
2732 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2733 {
2734         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2735         unsigned int nr = vcpu->arch.exception.nr;
2736
2737         if (nr == PF_VECTOR) {
2738                 if (vcpu->arch.exception.nested_apf) {
2739                         *exit_qual = vcpu->arch.apf.nested_apf_token;
2740                         return 1;
2741                 }
2742                 /*
2743                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2744                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
2745                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2746                  * can be written only when inject_pending_event runs.  This should be
2747                  * conditional on a new capability---if the capability is disabled,
2748                  * kvm_multiple_exception would write the ancillary information to
2749                  * CR2 or DR6, for backwards ABI-compatibility.
2750                  */
2751                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2752                                                     vcpu->arch.exception.error_code)) {
2753                         *exit_qual = vcpu->arch.cr2;
2754                         return 1;
2755                 }
2756         } else {
2757                 if (vmcs12->exception_bitmap & (1u << nr)) {
2758                         if (nr == DB_VECTOR)
2759                                 *exit_qual = vcpu->arch.dr6;
2760                         else
2761                                 *exit_qual = 0;
2762                         return 1;
2763                 }
2764         }
2765
2766         return 0;
2767 }
2768
2769 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
2770 {
2771         /*
2772          * Ensure that we clear the HLT state in the VMCS.  We don't need to
2773          * explicitly skip the instruction because if the HLT state is set,
2774          * then the instruction is already executing and RIP has already been
2775          * advanced.
2776          */
2777         if (kvm_hlt_in_guest(vcpu->kvm) &&
2778                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
2779                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2780 }
2781
2782 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2783 {
2784         struct vcpu_vmx *vmx = to_vmx(vcpu);
2785         unsigned nr = vcpu->arch.exception.nr;
2786         bool has_error_code = vcpu->arch.exception.has_error_code;
2787         u32 error_code = vcpu->arch.exception.error_code;
2788         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2789
2790         if (has_error_code) {
2791                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2792                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2793         }
2794
2795         if (vmx->rmode.vm86_active) {
2796                 int inc_eip = 0;
2797                 if (kvm_exception_is_soft(nr))
2798                         inc_eip = vcpu->arch.event_exit_inst_len;
2799                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2800                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2801                 return;
2802         }
2803
2804         WARN_ON_ONCE(vmx->emulation_required);
2805
2806         if (kvm_exception_is_soft(nr)) {
2807                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2808                              vmx->vcpu.arch.event_exit_inst_len);
2809                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2810         } else
2811                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2812
2813         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2814
2815         vmx_clear_hlt(vcpu);
2816 }
2817
2818 static bool vmx_rdtscp_supported(void)
2819 {
2820         return cpu_has_vmx_rdtscp();
2821 }
2822
2823 static bool vmx_invpcid_supported(void)
2824 {
2825         return cpu_has_vmx_invpcid() && enable_ept;
2826 }
2827
2828 /*
2829  * Swap MSR entry in host/guest MSR entry array.
2830  */
2831 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2832 {
2833         struct shared_msr_entry tmp;
2834
2835         tmp = vmx->guest_msrs[to];
2836         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2837         vmx->guest_msrs[from] = tmp;
2838 }
2839
2840 /*
2841  * Set up the vmcs to automatically save and restore system
2842  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2843  * mode, as fiddling with msrs is very expensive.
2844  */
2845 static void setup_msrs(struct vcpu_vmx *vmx)
2846 {
2847         int save_nmsrs, index;
2848
2849         save_nmsrs = 0;
2850 #ifdef CONFIG_X86_64
2851         if (is_long_mode(&vmx->vcpu)) {
2852                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2853                 if (index >= 0)
2854                         move_msr_up(vmx, index, save_nmsrs++);
2855                 index = __find_msr_index(vmx, MSR_LSTAR);
2856                 if (index >= 0)
2857                         move_msr_up(vmx, index, save_nmsrs++);
2858                 index = __find_msr_index(vmx, MSR_CSTAR);
2859                 if (index >= 0)
2860                         move_msr_up(vmx, index, save_nmsrs++);
2861                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2862                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2863                         move_msr_up(vmx, index, save_nmsrs++);
2864                 /*
2865                  * MSR_STAR is only needed on long mode guests, and only
2866                  * if efer.sce is enabled.
2867                  */
2868                 index = __find_msr_index(vmx, MSR_STAR);
2869                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2870                         move_msr_up(vmx, index, save_nmsrs++);
2871         }
2872 #endif
2873         index = __find_msr_index(vmx, MSR_EFER);
2874         if (index >= 0 && update_transition_efer(vmx, index))
2875                 move_msr_up(vmx, index, save_nmsrs++);
2876
2877         vmx->save_nmsrs = save_nmsrs;
2878
2879         if (cpu_has_vmx_msr_bitmap())
2880                 vmx_update_msr_bitmap(&vmx->vcpu);
2881 }
2882
2883 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
2884 {
2885         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2886
2887         if (is_guest_mode(vcpu) &&
2888             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
2889                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
2890
2891         return vcpu->arch.tsc_offset;
2892 }
2893
2894 /*
2895  * writes 'offset' into guest's timestamp counter offset register
2896  */
2897 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2898 {
2899         if (is_guest_mode(vcpu)) {
2900                 /*
2901                  * We're here if L1 chose not to trap WRMSR to TSC. According
2902                  * to the spec, this should set L1's TSC; The offset that L1
2903                  * set for L2 remains unchanged, and still needs to be added
2904                  * to the newly set TSC to get L2's TSC.
2905                  */
2906                 struct vmcs12 *vmcs12;
2907                 /* recalculate vmcs02.TSC_OFFSET: */
2908                 vmcs12 = get_vmcs12(vcpu);
2909                 vmcs_write64(TSC_OFFSET, offset +
2910                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2911                          vmcs12->tsc_offset : 0));
2912         } else {
2913                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2914                                            vmcs_read64(TSC_OFFSET), offset);
2915                 vmcs_write64(TSC_OFFSET, offset);
2916         }
2917 }
2918
2919 /*
2920  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2921  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2922  * all guests if the "nested" module option is off, and can also be disabled
2923  * for a single guest by disabling its VMX cpuid bit.
2924  */
2925 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2926 {
2927         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2928 }
2929
2930 /*
2931  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2932  * returned for the various VMX controls MSRs when nested VMX is enabled.
2933  * The same values should also be used to verify that vmcs12 control fields are
2934  * valid during nested entry from L1 to L2.
2935  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2936  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2937  * bit in the high half is on if the corresponding bit in the control field
2938  * may be on. See also vmx_control_verify().
2939  */
2940 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
2941 {
2942         if (!nested) {
2943                 memset(msrs, 0, sizeof(*msrs));
2944                 return;
2945         }
2946
2947         /*
2948          * Note that as a general rule, the high half of the MSRs (bits in
2949          * the control fields which may be 1) should be initialized by the
2950          * intersection of the underlying hardware's MSR (i.e., features which
2951          * can be supported) and the list of features we want to expose -
2952          * because they are known to be properly supported in our code.
2953          * Also, usually, the low half of the MSRs (bits which must be 1) can
2954          * be set to 0, meaning that L1 may turn off any of these bits. The
2955          * reason is that if one of these bits is necessary, it will appear
2956          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2957          * fields of vmcs01 and vmcs02, will turn these bits off - and
2958          * nested_vmx_exit_reflected() will not pass related exits to L1.
2959          * These rules have exceptions below.
2960          */
2961
2962         /* pin-based controls */
2963         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2964                 msrs->pinbased_ctls_low,
2965                 msrs->pinbased_ctls_high);
2966         msrs->pinbased_ctls_low |=
2967                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2968         msrs->pinbased_ctls_high &=
2969                 PIN_BASED_EXT_INTR_MASK |
2970                 PIN_BASED_NMI_EXITING |
2971                 PIN_BASED_VIRTUAL_NMIS |
2972                 (apicv ? PIN_BASED_POSTED_INTR : 0);
2973         msrs->pinbased_ctls_high |=
2974                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2975                 PIN_BASED_VMX_PREEMPTION_TIMER;
2976
2977         /* exit controls */
2978         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2979                 msrs->exit_ctls_low,
2980                 msrs->exit_ctls_high);
2981         msrs->exit_ctls_low =
2982                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2983
2984         msrs->exit_ctls_high &=
2985 #ifdef CONFIG_X86_64
2986                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2987 #endif
2988                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2989         msrs->exit_ctls_high |=
2990                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2991                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2992                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2993
2994         if (kvm_mpx_supported())
2995                 msrs->exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2996
2997         /* We support free control of debug control saving. */
2998         msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2999
3000         /* entry controls */
3001         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
3002                 msrs->entry_ctls_low,
3003                 msrs->entry_ctls_high);
3004         msrs->entry_ctls_low =
3005                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3006         msrs->entry_ctls_high &=
3007 #ifdef CONFIG_X86_64
3008                 VM_ENTRY_IA32E_MODE |
3009 #endif
3010                 VM_ENTRY_LOAD_IA32_PAT;
3011         msrs->entry_ctls_high |=
3012                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3013         if (kvm_mpx_supported())
3014                 msrs->entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
3015
3016         /* We support free control of debug control loading. */
3017         msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3018
3019         /* cpu-based controls */
3020         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3021                 msrs->procbased_ctls_low,
3022                 msrs->procbased_ctls_high);
3023         msrs->procbased_ctls_low =
3024                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3025         msrs->procbased_ctls_high &=
3026                 CPU_BASED_VIRTUAL_INTR_PENDING |
3027                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3028                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3029                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3030                 CPU_BASED_CR3_STORE_EXITING |
3031 #ifdef CONFIG_X86_64
3032                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3033 #endif
3034                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3035                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3036                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3037                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3038                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3039         /*
3040          * We can allow some features even when not supported by the
3041          * hardware. For example, L1 can specify an MSR bitmap - and we
3042          * can use it to avoid exits to L1 - even when L0 runs L2
3043          * without MSR bitmaps.
3044          */
3045         msrs->procbased_ctls_high |=
3046                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3047                 CPU_BASED_USE_MSR_BITMAPS;
3048
3049         /* We support free control of CR3 access interception. */
3050         msrs->procbased_ctls_low &=
3051                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3052
3053         /*
3054          * secondary cpu-based controls.  Do not include those that
3055          * depend on CPUID bits, they are added later by vmx_cpuid_update.
3056          */
3057         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3058                 msrs->secondary_ctls_low,
3059                 msrs->secondary_ctls_high);
3060         msrs->secondary_ctls_low = 0;
3061         msrs->secondary_ctls_high &=
3062                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3063                 SECONDARY_EXEC_DESC |
3064                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3065                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3066                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3067                 SECONDARY_EXEC_WBINVD_EXITING;
3068
3069         if (enable_ept) {
3070                 /* nested EPT: emulate EPT also to L1 */
3071                 msrs->secondary_ctls_high |=
3072                         SECONDARY_EXEC_ENABLE_EPT;
3073                 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3074                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3075                 if (cpu_has_vmx_ept_execute_only())
3076                         msrs->ept_caps |=
3077                                 VMX_EPT_EXECUTE_ONLY_BIT;
3078                 msrs->ept_caps &= vmx_capability.ept;
3079                 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3080                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3081                         VMX_EPT_1GB_PAGE_BIT;
3082                 if (enable_ept_ad_bits) {
3083                         msrs->secondary_ctls_high |=
3084                                 SECONDARY_EXEC_ENABLE_PML;
3085                         msrs->ept_caps |= VMX_EPT_AD_BIT;
3086                 }
3087         }
3088
3089         if (cpu_has_vmx_vmfunc()) {
3090                 msrs->secondary_ctls_high |=
3091                         SECONDARY_EXEC_ENABLE_VMFUNC;
3092                 /*
3093                  * Advertise EPTP switching unconditionally
3094                  * since we emulate it
3095                  */
3096                 if (enable_ept)
3097                         msrs->vmfunc_controls =
3098                                 VMX_VMFUNC_EPTP_SWITCHING;
3099         }
3100
3101         /*
3102          * Old versions of KVM use the single-context version without
3103          * checking for support, so declare that it is supported even
3104          * though it is treated as global context.  The alternative is
3105          * not failing the single-context invvpid, and it is worse.
3106          */
3107         if (enable_vpid) {
3108                 msrs->secondary_ctls_high |=
3109                         SECONDARY_EXEC_ENABLE_VPID;
3110                 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
3111                         VMX_VPID_EXTENT_SUPPORTED_MASK;
3112         }
3113
3114         if (enable_unrestricted_guest)
3115                 msrs->secondary_ctls_high |=
3116                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
3117
3118         /* miscellaneous data */
3119         rdmsr(MSR_IA32_VMX_MISC,
3120                 msrs->misc_low,
3121                 msrs->misc_high);
3122         msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
3123         msrs->misc_low |=
3124                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3125                 VMX_MISC_ACTIVITY_HLT;
3126         msrs->misc_high = 0;
3127
3128         /*
3129          * This MSR reports some information about VMX support. We
3130          * should return information about the VMX we emulate for the
3131          * guest, and the VMCS structure we give it - not about the
3132          * VMX support of the underlying hardware.
3133          */
3134         msrs->basic =
3135                 VMCS12_REVISION |
3136                 VMX_BASIC_TRUE_CTLS |
3137                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3138                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3139
3140         if (cpu_has_vmx_basic_inout())
3141                 msrs->basic |= VMX_BASIC_INOUT;
3142
3143         /*
3144          * These MSRs specify bits which the guest must keep fixed on
3145          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3146          * We picked the standard core2 setting.
3147          */
3148 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3149 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
3150         msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
3151         msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
3152
3153         /* These MSRs specify bits which the guest must keep fixed off. */
3154         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
3155         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
3156
3157         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3158         msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
3159 }
3160
3161 /*
3162  * if fixed0[i] == 1: val[i] must be 1
3163  * if fixed1[i] == 0: val[i] must be 0
3164  */
3165 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3166 {
3167         return ((val & fixed1) | fixed0) == val;
3168 }
3169
3170 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3171 {
3172         return fixed_bits_valid(control, low, high);
3173 }
3174
3175 static inline u64 vmx_control_msr(u32 low, u32 high)
3176 {
3177         return low | ((u64)high << 32);
3178 }
3179
3180 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3181 {
3182         superset &= mask;
3183         subset &= mask;
3184
3185         return (superset | subset) == superset;
3186 }
3187
3188 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3189 {
3190         const u64 feature_and_reserved =
3191                 /* feature (except bit 48; see below) */
3192                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3193                 /* reserved */
3194                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3195         u64 vmx_basic = vmx->nested.msrs.basic;
3196
3197         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3198                 return -EINVAL;
3199
3200         /*
3201          * KVM does not emulate a version of VMX that constrains physical
3202          * addresses of VMX structures (e.g. VMCS) to 32-bits.
3203          */
3204         if (data & BIT_ULL(48))
3205                 return -EINVAL;
3206
3207         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3208             vmx_basic_vmcs_revision_id(data))
3209                 return -EINVAL;
3210
3211         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3212                 return -EINVAL;
3213
3214         vmx->nested.msrs.basic = data;
3215         return 0;
3216 }
3217
3218 static int
3219 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3220 {
3221         u64 supported;
3222         u32 *lowp, *highp;
3223
3224         switch (msr_index) {
3225         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3226                 lowp = &vmx->nested.msrs.pinbased_ctls_low;
3227                 highp = &vmx->nested.msrs.pinbased_ctls_high;
3228                 break;
3229         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3230                 lowp = &vmx->nested.msrs.procbased_ctls_low;
3231                 highp = &vmx->nested.msrs.procbased_ctls_high;
3232                 break;
3233         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3234                 lowp = &vmx->nested.msrs.exit_ctls_low;
3235                 highp = &vmx->nested.msrs.exit_ctls_high;
3236                 break;
3237         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3238                 lowp = &vmx->nested.msrs.entry_ctls_low;
3239                 highp = &vmx->nested.msrs.entry_ctls_high;
3240                 break;
3241         case MSR_IA32_VMX_PROCBASED_CTLS2:
3242                 lowp = &vmx->nested.msrs.secondary_ctls_low;
3243                 highp = &vmx->nested.msrs.secondary_ctls_high;
3244                 break;
3245         default:
3246                 BUG();
3247         }
3248
3249         supported = vmx_control_msr(*lowp, *highp);
3250
3251         /* Check must-be-1 bits are still 1. */
3252         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3253                 return -EINVAL;
3254
3255         /* Check must-be-0 bits are still 0. */
3256         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3257                 return -EINVAL;
3258
3259         *lowp = data;
3260         *highp = data >> 32;
3261         return 0;
3262 }
3263
3264 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3265 {
3266         const u64 feature_and_reserved_bits =
3267                 /* feature */
3268                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3269                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3270                 /* reserved */
3271                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3272         u64 vmx_misc;
3273
3274         vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
3275                                    vmx->nested.msrs.misc_high);
3276
3277         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3278                 return -EINVAL;
3279
3280         if ((vmx->nested.msrs.pinbased_ctls_high &
3281              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3282             vmx_misc_preemption_timer_rate(data) !=
3283             vmx_misc_preemption_timer_rate(vmx_misc))
3284                 return -EINVAL;
3285
3286         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3287                 return -EINVAL;
3288
3289         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3290                 return -EINVAL;
3291
3292         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3293                 return -EINVAL;
3294
3295         vmx->nested.msrs.misc_low = data;
3296         vmx->nested.msrs.misc_high = data >> 32;
3297         return 0;
3298 }
3299
3300 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3301 {
3302         u64 vmx_ept_vpid_cap;
3303
3304         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
3305                                            vmx->nested.msrs.vpid_caps);
3306
3307         /* Every bit is either reserved or a feature bit. */
3308         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3309                 return -EINVAL;
3310
3311         vmx->nested.msrs.ept_caps = data;
3312         vmx->nested.msrs.vpid_caps = data >> 32;
3313         return 0;
3314 }
3315
3316 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3317 {
3318         u64 *msr;
3319
3320         switch (msr_index) {
3321         case MSR_IA32_VMX_CR0_FIXED0:
3322                 msr = &vmx->nested.msrs.cr0_fixed0;
3323                 break;
3324         case MSR_IA32_VMX_CR4_FIXED0:
3325                 msr = &vmx->nested.msrs.cr4_fixed0;
3326                 break;
3327         default:
3328                 BUG();
3329         }
3330
3331         /*
3332          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3333          * must be 1 in the restored value.
3334          */
3335         if (!is_bitwise_subset(data, *msr, -1ULL))
3336                 return -EINVAL;
3337
3338         *msr = data;
3339         return 0;
3340 }
3341
3342 /*
3343  * Called when userspace is restoring VMX MSRs.
3344  *
3345  * Returns 0 on success, non-0 otherwise.
3346  */
3347 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3348 {
3349         struct vcpu_vmx *vmx = to_vmx(vcpu);
3350
3351         switch (msr_index) {
3352         case MSR_IA32_VMX_BASIC:
3353                 return vmx_restore_vmx_basic(vmx, data);
3354         case MSR_IA32_VMX_PINBASED_CTLS:
3355         case MSR_IA32_VMX_PROCBASED_CTLS:
3356         case MSR_IA32_VMX_EXIT_CTLS:
3357         case MSR_IA32_VMX_ENTRY_CTLS:
3358                 /*
3359                  * The "non-true" VMX capability MSRs are generated from the
3360                  * "true" MSRs, so we do not support restoring them directly.
3361                  *
3362                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3363                  * should restore the "true" MSRs with the must-be-1 bits
3364                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3365                  * DEFAULT SETTINGS".
3366                  */
3367                 return -EINVAL;
3368         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3369         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3370         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3371         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3372         case MSR_IA32_VMX_PROCBASED_CTLS2:
3373                 return vmx_restore_control_msr(vmx, msr_index, data);
3374         case MSR_IA32_VMX_MISC:
3375                 return vmx_restore_vmx_misc(vmx, data);
3376         case MSR_IA32_VMX_CR0_FIXED0:
3377         case MSR_IA32_VMX_CR4_FIXED0:
3378                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3379         case MSR_IA32_VMX_CR0_FIXED1:
3380         case MSR_IA32_VMX_CR4_FIXED1:
3381                 /*
3382                  * These MSRs are generated based on the vCPU's CPUID, so we
3383                  * do not support restoring them directly.
3384                  */
3385                 return -EINVAL;
3386         case MSR_IA32_VMX_EPT_VPID_CAP:
3387                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3388         case MSR_IA32_VMX_VMCS_ENUM:
3389                 vmx->nested.msrs.vmcs_enum = data;
3390                 return 0;
3391         default:
3392                 /*
3393                  * The rest of the VMX capability MSRs do not support restore.
3394                  */
3395                 return -EINVAL;
3396         }
3397 }
3398
3399 /* Returns 0 on success, non-0 otherwise. */
3400 static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
3401 {
3402         switch (msr_index) {
3403         case MSR_IA32_VMX_BASIC:
3404                 *pdata = msrs->basic;
3405                 break;
3406         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3407         case MSR_IA32_VMX_PINBASED_CTLS:
3408                 *pdata = vmx_control_msr(
3409                         msrs->pinbased_ctls_low,
3410                         msrs->pinbased_ctls_high);
3411                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3412                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3413                 break;
3414         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3415         case MSR_IA32_VMX_PROCBASED_CTLS:
3416                 *pdata = vmx_control_msr(
3417                         msrs->procbased_ctls_low,
3418                         msrs->procbased_ctls_high);
3419                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3420                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3421                 break;
3422         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3423         case MSR_IA32_VMX_EXIT_CTLS:
3424                 *pdata = vmx_control_msr(
3425                         msrs->exit_ctls_low,
3426                         msrs->exit_ctls_high);
3427                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3428                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3429                 break;
3430         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3431         case MSR_IA32_VMX_ENTRY_CTLS:
3432                 *pdata = vmx_control_msr(
3433                         msrs->entry_ctls_low,
3434                         msrs->entry_ctls_high);
3435                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3436                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3437                 break;
3438         case MSR_IA32_VMX_MISC:
3439                 *pdata = vmx_control_msr(
3440                         msrs->misc_low,
3441                         msrs->misc_high);
3442                 break;
3443         case MSR_IA32_VMX_CR0_FIXED0:
3444                 *pdata = msrs->cr0_fixed0;
3445                 break;
3446         case MSR_IA32_VMX_CR0_FIXED1:
3447                 *pdata = msrs->cr0_fixed1;
3448                 break;
3449         case MSR_IA32_VMX_CR4_FIXED0:
3450                 *pdata = msrs->cr4_fixed0;
3451                 break;
3452         case MSR_IA32_VMX_CR4_FIXED1:
3453                 *pdata = msrs->cr4_fixed1;
3454                 break;
3455         case MSR_IA32_VMX_VMCS_ENUM:
3456                 *pdata = msrs->vmcs_enum;
3457                 break;
3458         case MSR_IA32_VMX_PROCBASED_CTLS2:
3459                 *pdata = vmx_control_msr(
3460                         msrs->secondary_ctls_low,
3461                         msrs->secondary_ctls_high);
3462                 break;
3463         case MSR_IA32_VMX_EPT_VPID_CAP:
3464                 *pdata = msrs->ept_caps |
3465                         ((u64)msrs->vpid_caps << 32);
3466                 break;
3467         case MSR_IA32_VMX_VMFUNC:
3468                 *pdata = msrs->vmfunc_controls;
3469                 break;
3470         default:
3471                 return 1;
3472         }
3473
3474         return 0;
3475 }
3476
3477 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3478                                                  uint64_t val)
3479 {
3480         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3481
3482         return !(val & ~valid_bits);
3483 }
3484
3485 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
3486 {
3487         switch (msr->index) {
3488         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3489                 if (!nested)
3490                         return 1;
3491                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
3492         default:
3493                 return 1;
3494         }
3495
3496         return 0;
3497 }
3498
3499 /*
3500  * Reads an msr value (of 'msr_index') into 'pdata'.
3501  * Returns 0 on success, non-0 otherwise.
3502  * Assumes vcpu_load() was already called.
3503  */
3504 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3505 {
3506         struct vcpu_vmx *vmx = to_vmx(vcpu);
3507         struct shared_msr_entry *msr;
3508
3509         switch (msr_info->index) {
3510 #ifdef CONFIG_X86_64
3511         case MSR_FS_BASE:
3512                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3513                 break;
3514         case MSR_GS_BASE:
3515                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3516                 break;
3517         case MSR_KERNEL_GS_BASE:
3518                 vmx_load_host_state(vmx);
3519                 msr_info->data = vmx->msr_guest_kernel_gs_base;
3520                 break;
3521 #endif
3522         case MSR_EFER:
3523                 return kvm_get_msr_common(vcpu, msr_info);
3524         case MSR_IA32_SPEC_CTRL:
3525                 if (!msr_info->host_initiated &&
3526                     !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
3527                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3528                         return 1;
3529
3530                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3531                 break;
3532         case MSR_IA32_ARCH_CAPABILITIES:
3533                 if (!msr_info->host_initiated &&
3534                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3535                         return 1;
3536                 msr_info->data = to_vmx(vcpu)->arch_capabilities;
3537                 break;
3538         case MSR_IA32_SYSENTER_CS:
3539                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3540                 break;
3541         case MSR_IA32_SYSENTER_EIP:
3542                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3543                 break;
3544         case MSR_IA32_SYSENTER_ESP:
3545                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3546                 break;
3547         case MSR_IA32_BNDCFGS:
3548                 if (!kvm_mpx_supported() ||
3549                     (!msr_info->host_initiated &&
3550                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3551                         return 1;
3552                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3553                 break;
3554         case MSR_IA32_MCG_EXT_CTL:
3555                 if (!msr_info->host_initiated &&
3556                     !(vmx->msr_ia32_feature_control &
3557                       FEATURE_CONTROL_LMCE))
3558                         return 1;
3559                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3560                 break;
3561         case MSR_IA32_FEATURE_CONTROL:
3562                 msr_info->data = vmx->msr_ia32_feature_control;
3563                 break;
3564         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3565                 if (!nested_vmx_allowed(vcpu))
3566                         return 1;
3567                 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
3568                                        &msr_info->data);
3569         case MSR_IA32_XSS:
3570                 if (!vmx_xsaves_supported())
3571                         return 1;
3572                 msr_info->data = vcpu->arch.ia32_xss;
3573                 break;
3574         case MSR_TSC_AUX:
3575                 if (!msr_info->host_initiated &&
3576                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3577                         return 1;
3578                 /* Otherwise falls through */
3579         default:
3580                 msr = find_msr_entry(vmx, msr_info->index);
3581                 if (msr) {
3582                         msr_info->data = msr->data;
3583                         break;
3584                 }
3585                 return kvm_get_msr_common(vcpu, msr_info);
3586         }
3587
3588         return 0;
3589 }
3590
3591 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3592
3593 /*
3594  * Writes msr value into into the appropriate "register".
3595  * Returns 0 on success, non-0 otherwise.
3596  * Assumes vcpu_load() was already called.
3597  */
3598 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3599 {
3600         struct vcpu_vmx *vmx = to_vmx(vcpu);
3601         struct shared_msr_entry *msr;
3602         int ret = 0;
3603         u32 msr_index = msr_info->index;
3604         u64 data = msr_info->data;
3605
3606         switch (msr_index) {
3607         case MSR_EFER:
3608                 ret = kvm_set_msr_common(vcpu, msr_info);
3609                 break;
3610 #ifdef CONFIG_X86_64
3611         case MSR_FS_BASE:
3612                 vmx_segment_cache_clear(vmx);
3613                 vmcs_writel(GUEST_FS_BASE, data);
3614                 break;
3615         case MSR_GS_BASE:
3616                 vmx_segment_cache_clear(vmx);
3617                 vmcs_writel(GUEST_GS_BASE, data);
3618                 break;
3619         case MSR_KERNEL_GS_BASE:
3620                 vmx_load_host_state(vmx);
3621                 vmx->msr_guest_kernel_gs_base = data;
3622                 break;
3623 #endif
3624         case MSR_IA32_SYSENTER_CS:
3625                 vmcs_write32(GUEST_SYSENTER_CS, data);
3626                 break;
3627         case MSR_IA32_SYSENTER_EIP:
3628                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3629                 break;
3630         case MSR_IA32_SYSENTER_ESP:
3631                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3632                 break;
3633         case MSR_IA32_BNDCFGS:
3634                 if (!kvm_mpx_supported() ||
3635                     (!msr_info->host_initiated &&
3636                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3637                         return 1;
3638                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3639                     (data & MSR_IA32_BNDCFGS_RSVD))
3640                         return 1;
3641                 vmcs_write64(GUEST_BNDCFGS, data);
3642                 break;
3643         case MSR_IA32_SPEC_CTRL:
3644                 if (!msr_info->host_initiated &&
3645                     !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
3646                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3647                         return 1;
3648
3649                 /* The STIBP bit doesn't fault even if it's not advertised */
3650                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP))
3651                         return 1;
3652
3653                 vmx->spec_ctrl = data;
3654
3655                 if (!data)
3656                         break;
3657
3658                 /*
3659                  * For non-nested:
3660                  * When it's written (to non-zero) for the first time, pass
3661                  * it through.
3662                  *
3663                  * For nested:
3664                  * The handling of the MSR bitmap for L2 guests is done in
3665                  * nested_vmx_merge_msr_bitmap. We should not touch the
3666                  * vmcs02.msr_bitmap here since it gets completely overwritten
3667                  * in the merging. We update the vmcs01 here for L1 as well
3668                  * since it will end up touching the MSR anyway now.
3669                  */
3670                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3671                                               MSR_IA32_SPEC_CTRL,
3672                                               MSR_TYPE_RW);
3673                 break;
3674         case MSR_IA32_PRED_CMD:
3675                 if (!msr_info->host_initiated &&
3676                     !guest_cpuid_has(vcpu, X86_FEATURE_IBPB) &&
3677                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3678                         return 1;
3679
3680                 if (data & ~PRED_CMD_IBPB)
3681                         return 1;
3682
3683                 if (!data)
3684                         break;
3685
3686                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3687
3688                 /*
3689                  * For non-nested:
3690                  * When it's written (to non-zero) for the first time, pass
3691                  * it through.
3692                  *
3693                  * For nested:
3694                  * The handling of the MSR bitmap for L2 guests is done in
3695                  * nested_vmx_merge_msr_bitmap. We should not touch the
3696                  * vmcs02.msr_bitmap here since it gets completely overwritten
3697                  * in the merging.
3698                  */
3699                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3700                                               MSR_TYPE_W);
3701                 break;
3702         case MSR_IA32_ARCH_CAPABILITIES:
3703                 if (!msr_info->host_initiated)
3704                         return 1;
3705                 vmx->arch_capabilities = data;
3706                 break;
3707         case MSR_IA32_CR_PAT:
3708                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3709                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3710                                 return 1;
3711                         vmcs_write64(GUEST_IA32_PAT, data);
3712                         vcpu->arch.pat = data;
3713                         break;
3714                 }
3715                 ret = kvm_set_msr_common(vcpu, msr_info);
3716                 break;
3717         case MSR_IA32_TSC_ADJUST:
3718                 ret = kvm_set_msr_common(vcpu, msr_info);
3719                 break;
3720         case MSR_IA32_MCG_EXT_CTL:
3721                 if ((!msr_info->host_initiated &&
3722                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3723                        FEATURE_CONTROL_LMCE)) ||
3724                     (data & ~MCG_EXT_CTL_LMCE_EN))
3725                         return 1;
3726                 vcpu->arch.mcg_ext_ctl = data;
3727                 break;
3728         case MSR_IA32_FEATURE_CONTROL:
3729                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3730                     (to_vmx(vcpu)->msr_ia32_feature_control &
3731                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3732                         return 1;
3733                 vmx->msr_ia32_feature_control = data;
3734                 if (msr_info->host_initiated && data == 0)
3735                         vmx_leave_nested(vcpu);
3736                 break;
3737         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3738                 if (!msr_info->host_initiated)
3739                         return 1; /* they are read-only */
3740                 if (!nested_vmx_allowed(vcpu))
3741                         return 1;
3742                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3743         case MSR_IA32_XSS:
3744                 if (!vmx_xsaves_supported())
3745                         return 1;
3746                 /*
3747                  * The only supported bit as of Skylake is bit 8, but
3748                  * it is not supported on KVM.
3749                  */
3750                 if (data != 0)
3751                         return 1;
3752                 vcpu->arch.ia32_xss = data;
3753                 if (vcpu->arch.ia32_xss != host_xss)
3754                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3755                                 vcpu->arch.ia32_xss, host_xss);
3756                 else
3757                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3758                 break;
3759         case MSR_TSC_AUX:
3760                 if (!msr_info->host_initiated &&
3761                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3762                         return 1;
3763                 /* Check reserved bit, higher 32 bits should be zero */
3764                 if ((data >> 32) != 0)
3765                         return 1;
3766                 /* Otherwise falls through */
3767         default:
3768                 msr = find_msr_entry(vmx, msr_index);
3769                 if (msr) {
3770                         u64 old_msr_data = msr->data;
3771                         msr->data = data;
3772                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3773                                 preempt_disable();
3774                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3775                                                          msr->mask);
3776                                 preempt_enable();
3777                                 if (ret)
3778                                         msr->data = old_msr_data;
3779                         }
3780                         break;
3781                 }
3782                 ret = kvm_set_msr_common(vcpu, msr_info);
3783         }
3784
3785         return ret;
3786 }
3787
3788 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3789 {
3790         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3791         switch (reg) {
3792         case VCPU_REGS_RSP:
3793                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3794                 break;
3795         case VCPU_REGS_RIP:
3796                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3797                 break;
3798         case VCPU_EXREG_PDPTR:
3799                 if (enable_ept)
3800                         ept_save_pdptrs(vcpu);
3801                 break;
3802         default:
3803                 break;
3804         }
3805 }
3806
3807 static __init int cpu_has_kvm_support(void)
3808 {
3809         return cpu_has_vmx();
3810 }
3811
3812 static __init int vmx_disabled_by_bios(void)
3813 {
3814         u64 msr;
3815
3816         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3817         if (msr & FEATURE_CONTROL_LOCKED) {
3818                 /* launched w/ TXT and VMX disabled */
3819                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3820                         && tboot_enabled())
3821                         return 1;
3822                 /* launched w/o TXT and VMX only enabled w/ TXT */
3823                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3824                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3825                         && !tboot_enabled()) {
3826                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3827                                 "activate TXT before enabling KVM\n");
3828                         return 1;
3829                 }
3830                 /* launched w/o TXT and VMX disabled */
3831                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3832                         && !tboot_enabled())
3833                         return 1;
3834         }
3835
3836         return 0;
3837 }
3838
3839 static void kvm_cpu_vmxon(u64 addr)
3840 {
3841         cr4_set_bits(X86_CR4_VMXE);
3842         intel_pt_handle_vmx(1);
3843
3844         asm volatile (ASM_VMX_VMXON_RAX
3845                         : : "a"(&addr), "m"(addr)
3846                         : "memory", "cc");
3847 }
3848
3849 static int hardware_enable(void)
3850 {
3851         int cpu = raw_smp_processor_id();
3852         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3853         u64 old, test_bits;
3854
3855         if (cr4_read_shadow() & X86_CR4_VMXE)
3856                 return -EBUSY;
3857
3858         /*
3859          * This can happen if we hot-added a CPU but failed to allocate
3860          * VP assist page for it.
3861          */
3862         if (static_branch_unlikely(&enable_evmcs) &&
3863             !hv_get_vp_assist_page(cpu))
3864                 return -EFAULT;
3865
3866         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3867         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3868         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3869
3870         /*
3871          * Now we can enable the vmclear operation in kdump
3872          * since the loaded_vmcss_on_cpu list on this cpu
3873          * has been initialized.
3874          *
3875          * Though the cpu is not in VMX operation now, there
3876          * is no problem to enable the vmclear operation
3877          * for the loaded_vmcss_on_cpu list is empty!
3878          */
3879         crash_enable_local_vmclear(cpu);
3880
3881         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3882
3883         test_bits = FEATURE_CONTROL_LOCKED;
3884         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3885         if (tboot_enabled())
3886                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3887
3888         if ((old & test_bits) != test_bits) {
3889                 /* enable and lock */
3890                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3891         }
3892         kvm_cpu_vmxon(phys_addr);
3893         if (enable_ept)
3894                 ept_sync_global();
3895
3896         return 0;
3897 }
3898
3899 static void vmclear_local_loaded_vmcss(void)
3900 {
3901         int cpu = raw_smp_processor_id();
3902         struct loaded_vmcs *v, *n;
3903
3904         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3905                                  loaded_vmcss_on_cpu_link)
3906                 __loaded_vmcs_clear(v);
3907 }
3908
3909
3910 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3911  * tricks.
3912  */
3913 static void kvm_cpu_vmxoff(void)
3914 {
3915         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3916
3917         intel_pt_handle_vmx(0);
3918         cr4_clear_bits(X86_CR4_VMXE);
3919 }
3920
3921 static void hardware_disable(void)
3922 {
3923         vmclear_local_loaded_vmcss();
3924         kvm_cpu_vmxoff();
3925 }
3926
3927 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3928                                       u32 msr, u32 *result)
3929 {
3930         u32 vmx_msr_low, vmx_msr_high;
3931         u32 ctl = ctl_min | ctl_opt;
3932
3933         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3934
3935         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3936         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3937
3938         /* Ensure minimum (required) set of control bits are supported. */
3939         if (ctl_min & ~ctl)
3940                 return -EIO;
3941
3942         *result = ctl;
3943         return 0;
3944 }
3945
3946 static __init bool allow_1_setting(u32 msr, u32 ctl)
3947 {
3948         u32 vmx_msr_low, vmx_msr_high;
3949
3950         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3951         return vmx_msr_high & ctl;
3952 }
3953
3954 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3955 {
3956         u32 vmx_msr_low, vmx_msr_high;
3957         u32 min, opt, min2, opt2;
3958         u32 _pin_based_exec_control = 0;
3959         u32 _cpu_based_exec_control = 0;
3960         u32 _cpu_based_2nd_exec_control = 0;
3961         u32 _vmexit_control = 0;
3962         u32 _vmentry_control = 0;
3963
3964         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
3965         min = CPU_BASED_HLT_EXITING |
3966 #ifdef CONFIG_X86_64
3967               CPU_BASED_CR8_LOAD_EXITING |
3968               CPU_BASED_CR8_STORE_EXITING |
3969 #endif
3970               CPU_BASED_CR3_LOAD_EXITING |
3971               CPU_BASED_CR3_STORE_EXITING |
3972               CPU_BASED_UNCOND_IO_EXITING |
3973               CPU_BASED_MOV_DR_EXITING |
3974               CPU_BASED_USE_TSC_OFFSETING |
3975               CPU_BASED_MWAIT_EXITING |
3976               CPU_BASED_MONITOR_EXITING |
3977               CPU_BASED_INVLPG_EXITING |
3978               CPU_BASED_RDPMC_EXITING;
3979
3980         opt = CPU_BASED_TPR_SHADOW |
3981               CPU_BASED_USE_MSR_BITMAPS |
3982               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3983         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3984                                 &_cpu_based_exec_control) < 0)
3985                 return -EIO;
3986 #ifdef CONFIG_X86_64
3987         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3988                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3989                                            ~CPU_BASED_CR8_STORE_EXITING;
3990 #endif
3991         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3992                 min2 = 0;
3993                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3994                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3995                         SECONDARY_EXEC_WBINVD_EXITING |
3996                         SECONDARY_EXEC_ENABLE_VPID |
3997                         SECONDARY_EXEC_ENABLE_EPT |
3998                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3999                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
4000                         SECONDARY_EXEC_DESC |
4001                         SECONDARY_EXEC_RDTSCP |
4002                         SECONDARY_EXEC_ENABLE_INVPCID |
4003                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4004                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4005                         SECONDARY_EXEC_SHADOW_VMCS |
4006                         SECONDARY_EXEC_XSAVES |
4007                         SECONDARY_EXEC_RDSEED_EXITING |
4008                         SECONDARY_EXEC_RDRAND_EXITING |
4009                         SECONDARY_EXEC_ENABLE_PML |
4010                         SECONDARY_EXEC_TSC_SCALING |
4011                         SECONDARY_EXEC_ENABLE_VMFUNC;
4012                 if (adjust_vmx_controls(min2, opt2,
4013                                         MSR_IA32_VMX_PROCBASED_CTLS2,
4014                                         &_cpu_based_2nd_exec_control) < 0)
4015                         return -EIO;
4016         }
4017 #ifndef CONFIG_X86_64
4018         if (!(_cpu_based_2nd_exec_control &
4019                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
4020                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
4021 #endif
4022
4023         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4024                 _cpu_based_2nd_exec_control &= ~(
4025                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4026                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4027                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4028
4029         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
4030                 &vmx_capability.ept, &vmx_capability.vpid);
4031
4032         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
4033                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4034                    enabled */
4035                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
4036                                              CPU_BASED_CR3_STORE_EXITING |
4037                                              CPU_BASED_INVLPG_EXITING);
4038         } else if (vmx_capability.ept) {
4039                 vmx_capability.ept = 0;
4040                 pr_warn_once("EPT CAP should not exist if not support "
4041                                 "1-setting enable EPT VM-execution control\n");
4042         }
4043         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
4044                 vmx_capability.vpid) {
4045                 vmx_capability.vpid = 0;
4046                 pr_warn_once("VPID CAP should not exist if not support "
4047                                 "1-setting enable VPID VM-execution control\n");
4048         }
4049
4050         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4051 #ifdef CONFIG_X86_64
4052         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4053 #endif
4054         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4055                 VM_EXIT_CLEAR_BNDCFGS;
4056         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4057                                 &_vmexit_control) < 0)
4058                 return -EIO;
4059
4060         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4061         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4062                  PIN_BASED_VMX_PREEMPTION_TIMER;
4063         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4064                                 &_pin_based_exec_control) < 0)
4065                 return -EIO;
4066
4067         if (cpu_has_broken_vmx_preemption_timer())
4068                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4069         if (!(_cpu_based_2nd_exec_control &
4070                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4071                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4072
4073         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4074         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4075         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4076                                 &_vmentry_control) < 0)
4077                 return -EIO;
4078
4079         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4080
4081         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4082         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4083                 return -EIO;
4084
4085 #ifdef CONFIG_X86_64
4086         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4087         if (vmx_msr_high & (1u<<16))
4088                 return -EIO;
4089 #endif
4090
4091         /* Require Write-Back (WB) memory type for VMCS accesses. */
4092         if (((vmx_msr_high >> 18) & 15) != 6)
4093                 return -EIO;
4094
4095         vmcs_conf->size = vmx_msr_high & 0x1fff;
4096         vmcs_conf->order = get_order(vmcs_conf->size);
4097         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4098
4099         /* KVM supports Enlightened VMCS v1 only */
4100         if (static_branch_unlikely(&enable_evmcs))
4101                 vmcs_conf->revision_id = KVM_EVMCS_VERSION;
4102         else
4103                 vmcs_conf->revision_id = vmx_msr_low;
4104
4105         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4106         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4107         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4108         vmcs_conf->vmexit_ctrl         = _vmexit_control;
4109         vmcs_conf->vmentry_ctrl        = _vmentry_control;
4110
4111         if (static_branch_unlikely(&enable_evmcs))
4112                 evmcs_sanitize_exec_ctrls(vmcs_conf);
4113
4114         cpu_has_load_ia32_efer =
4115                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4116                                 VM_ENTRY_LOAD_IA32_EFER)
4117                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4118                                    VM_EXIT_LOAD_IA32_EFER);
4119
4120         cpu_has_load_perf_global_ctrl =
4121                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4122                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4123                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4124                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4125
4126         /*
4127          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4128          * but due to errata below it can't be used. Workaround is to use
4129          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4130          *
4131          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4132          *
4133          * AAK155             (model 26)
4134          * AAP115             (model 30)
4135          * AAT100             (model 37)
4136          * BC86,AAY89,BD102   (model 44)
4137          * BA97               (model 46)
4138          *
4139          */
4140         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4141                 switch (boot_cpu_data.x86_model) {
4142                 case 26:
4143                 case 30:
4144                 case 37:
4145                 case 44:
4146                 case 46:
4147                         cpu_has_load_perf_global_ctrl = false;
4148                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4149                                         "does not work properly. Using workaround\n");
4150                         break;
4151                 default:
4152                         break;
4153                 }
4154         }
4155
4156         if (boot_cpu_has(X86_FEATURE_XSAVES))
4157                 rdmsrl(MSR_IA32_XSS, host_xss);
4158
4159         return 0;
4160 }
4161
4162 static struct vmcs *alloc_vmcs_cpu(int cpu)
4163 {
4164         int node = cpu_to_node(cpu);
4165         struct page *pages;
4166         struct vmcs *vmcs;
4167
4168         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4169         if (!pages)
4170                 return NULL;
4171         vmcs = page_address(pages);
4172         memset(vmcs, 0, vmcs_config.size);
4173         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
4174         return vmcs;
4175 }
4176
4177 static void free_vmcs(struct vmcs *vmcs)
4178 {
4179         free_pages((unsigned long)vmcs, vmcs_config.order);
4180 }
4181
4182 /*
4183  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4184  */
4185 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4186 {
4187         if (!loaded_vmcs->vmcs)
4188                 return;
4189         loaded_vmcs_clear(loaded_vmcs);
4190         free_vmcs(loaded_vmcs->vmcs);
4191         loaded_vmcs->vmcs = NULL;
4192         if (loaded_vmcs->msr_bitmap)
4193                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4194         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4195 }
4196
4197 static struct vmcs *alloc_vmcs(void)
4198 {
4199         return alloc_vmcs_cpu(raw_smp_processor_id());
4200 }
4201
4202 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4203 {
4204         loaded_vmcs->vmcs = alloc_vmcs();
4205         if (!loaded_vmcs->vmcs)
4206                 return -ENOMEM;
4207
4208         loaded_vmcs->shadow_vmcs = NULL;
4209         loaded_vmcs_init(loaded_vmcs);
4210
4211         if (cpu_has_vmx_msr_bitmap()) {
4212                 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4213                 if (!loaded_vmcs->msr_bitmap)
4214                         goto out_vmcs;
4215                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4216         }
4217         return 0;
4218
4219 out_vmcs:
4220         free_loaded_vmcs(loaded_vmcs);
4221         return -ENOMEM;
4222 }
4223
4224 static void free_kvm_area(void)
4225 {
4226         int cpu;
4227
4228         for_each_possible_cpu(cpu) {
4229                 free_vmcs(per_cpu(vmxarea, cpu));
4230                 per_cpu(vmxarea, cpu) = NULL;
4231         }
4232 }
4233
4234 enum vmcs_field_width {
4235         VMCS_FIELD_WIDTH_U16 = 0,
4236         VMCS_FIELD_WIDTH_U64 = 1,
4237         VMCS_FIELD_WIDTH_U32 = 2,
4238         VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
4239 };
4240
4241 static inline int vmcs_field_width(unsigned long field)
4242 {
4243         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
4244                 return VMCS_FIELD_WIDTH_U32;
4245         return (field >> 13) & 0x3 ;
4246 }
4247
4248 static inline int vmcs_field_readonly(unsigned long field)
4249 {
4250         return (((field >> 10) & 0x3) == 1);
4251 }
4252
4253 static void init_vmcs_shadow_fields(void)
4254 {
4255         int i, j;
4256
4257         for (i = j = 0; i < max_shadow_read_only_fields; i++) {
4258                 u16 field = shadow_read_only_fields[i];
4259                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4260                     (i + 1 == max_shadow_read_only_fields ||
4261                      shadow_read_only_fields[i + 1] != field + 1))
4262                         pr_err("Missing field from shadow_read_only_field %x\n",
4263                                field + 1);
4264
4265                 clear_bit(field, vmx_vmread_bitmap);
4266 #ifdef CONFIG_X86_64
4267                 if (field & 1)
4268                         continue;
4269 #endif
4270                 if (j < i)
4271                         shadow_read_only_fields[j] = field;
4272                 j++;
4273         }
4274         max_shadow_read_only_fields = j;
4275
4276         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4277                 u16 field = shadow_read_write_fields[i];
4278                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4279                     (i + 1 == max_shadow_read_write_fields ||
4280                      shadow_read_write_fields[i + 1] != field + 1))
4281                         pr_err("Missing field from shadow_read_write_field %x\n",
4282                                field + 1);
4283
4284                 /*
4285                  * PML and the preemption timer can be emulated, but the
4286                  * processor cannot vmwrite to fields that don't exist
4287                  * on bare metal.
4288                  */
4289                 switch (field) {
4290                 case GUEST_PML_INDEX:
4291                         if (!cpu_has_vmx_pml())
4292                                 continue;
4293                         break;
4294                 case VMX_PREEMPTION_TIMER_VALUE:
4295                         if (!cpu_has_vmx_preemption_timer())
4296                                 continue;
4297                         break;
4298                 case GUEST_INTR_STATUS:
4299                         if (!cpu_has_vmx_apicv())
4300                                 continue;
4301                         break;
4302                 default:
4303                         break;
4304                 }
4305
4306                 clear_bit(field, vmx_vmwrite_bitmap);
4307                 clear_bit(field, vmx_vmread_bitmap);
4308 #ifdef CONFIG_X86_64
4309                 if (field & 1)
4310                         continue;
4311 #endif
4312                 if (j < i)
4313                         shadow_read_write_fields[j] = field;
4314                 j++;
4315         }
4316         max_shadow_read_write_fields = j;
4317 }
4318
4319 static __init int alloc_kvm_area(void)
4320 {
4321         int cpu;
4322
4323         for_each_possible_cpu(cpu) {
4324                 struct vmcs *vmcs;
4325
4326                 vmcs = alloc_vmcs_cpu(cpu);
4327                 if (!vmcs) {
4328                         free_kvm_area();
4329                         return -ENOMEM;
4330                 }
4331
4332                 per_cpu(vmxarea, cpu) = vmcs;
4333         }
4334         return 0;
4335 }
4336
4337 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4338                 struct kvm_segment *save)
4339 {
4340         if (!emulate_invalid_guest_state) {
4341                 /*
4342                  * CS and SS RPL should be equal during guest entry according
4343                  * to VMX spec, but in reality it is not always so. Since vcpu
4344                  * is in the middle of the transition from real mode to
4345                  * protected mode it is safe to assume that RPL 0 is a good
4346                  * default value.
4347                  */
4348                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4349                         save->selector &= ~SEGMENT_RPL_MASK;
4350                 save->dpl = save->selector & SEGMENT_RPL_MASK;
4351                 save->s = 1;
4352         }
4353         vmx_set_segment(vcpu, save, seg);
4354 }
4355
4356 static void enter_pmode(struct kvm_vcpu *vcpu)
4357 {
4358         unsigned long flags;
4359         struct vcpu_vmx *vmx = to_vmx(vcpu);
4360
4361         /*
4362          * Update real mode segment cache. It may be not up-to-date if sement
4363          * register was written while vcpu was in a guest mode.
4364          */
4365         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4366         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4367         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4368         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4369         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4370         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4371
4372         vmx->rmode.vm86_active = 0;
4373
4374         vmx_segment_cache_clear(vmx);
4375
4376         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4377
4378         flags = vmcs_readl(GUEST_RFLAGS);
4379         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4380         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4381         vmcs_writel(GUEST_RFLAGS, flags);
4382
4383         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4384                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4385
4386         update_exception_bitmap(vcpu);
4387
4388         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4389         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4390         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4391         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4392         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4393         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4394 }
4395
4396 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4397 {
4398         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4399         struct kvm_segment var = *save;
4400
4401         var.dpl = 0x3;
4402         if (seg == VCPU_SREG_CS)
4403                 var.type = 0x3;
4404
4405         if (!emulate_invalid_guest_state) {
4406                 var.selector = var.base >> 4;
4407                 var.base = var.base & 0xffff0;
4408                 var.limit = 0xffff;
4409                 var.g = 0;
4410                 var.db = 0;
4411                 var.present = 1;
4412                 var.s = 1;
4413                 var.l = 0;
4414                 var.unusable = 0;
4415                 var.type = 0x3;
4416                 var.avl = 0;
4417                 if (save->base & 0xf)
4418                         printk_once(KERN_WARNING "kvm: segment base is not "
4419                                         "paragraph aligned when entering "
4420                                         "protected mode (seg=%d)", seg);
4421         }
4422
4423         vmcs_write16(sf->selector, var.selector);
4424         vmcs_writel(sf->base, var.base);
4425         vmcs_write32(sf->limit, var.limit);
4426         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4427 }
4428
4429 static void enter_rmode(struct kvm_vcpu *vcpu)
4430 {
4431         unsigned long flags;
4432         struct vcpu_vmx *vmx = to_vmx(vcpu);
4433         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
4434
4435         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4436         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4437         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4438         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4439         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4440         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4441         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4442
4443         vmx->rmode.vm86_active = 1;
4444
4445         /*
4446          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4447          * vcpu. Warn the user that an update is overdue.
4448          */
4449         if (!kvm_vmx->tss_addr)
4450                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4451                              "called before entering vcpu\n");
4452
4453         vmx_segment_cache_clear(vmx);
4454
4455         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
4456         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4457         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4458
4459         flags = vmcs_readl(GUEST_RFLAGS);
4460         vmx->rmode.save_rflags = flags;
4461
4462         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4463
4464         vmcs_writel(GUEST_RFLAGS, flags);
4465         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4466         update_exception_bitmap(vcpu);
4467
4468         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4469         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4470         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4471         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4472         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4473         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4474
4475         kvm_mmu_reset_context(vcpu);
4476 }
4477
4478 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4479 {
4480         struct vcpu_vmx *vmx = to_vmx(vcpu);
4481         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4482
4483         if (!msr)
4484                 return;
4485
4486         /*
4487          * Force kernel_gs_base reloading before EFER changes, as control
4488          * of this msr depends on is_long_mode().
4489          */
4490         vmx_load_host_state(to_vmx(vcpu));
4491         vcpu->arch.efer = efer;
4492         if (efer & EFER_LMA) {
4493                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4494                 msr->data = efer;
4495         } else {
4496                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4497
4498                 msr->data = efer & ~EFER_LME;
4499         }
4500         setup_msrs(vmx);
4501 }
4502
4503 #ifdef CONFIG_X86_64
4504
4505 static void enter_lmode(struct kvm_vcpu *vcpu)
4506 {
4507         u32 guest_tr_ar;
4508
4509         vmx_segment_cache_clear(to_vmx(vcpu));
4510
4511         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4512         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4513                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4514                                      __func__);
4515                 vmcs_write32(GUEST_TR_AR_BYTES,
4516                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4517                              | VMX_AR_TYPE_BUSY_64_TSS);
4518         }
4519         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4520 }
4521
4522 static void exit_lmode(struct kvm_vcpu *vcpu)
4523 {
4524         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4525         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4526 }
4527
4528 #endif
4529
4530 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
4531                                 bool invalidate_gpa)
4532 {
4533         if (enable_ept && (invalidate_gpa || !enable_vpid)) {
4534                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4535                         return;
4536                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4537         } else {
4538                 vpid_sync_context(vpid);
4539         }
4540 }
4541
4542 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
4543 {
4544         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
4545 }
4546
4547 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4548 {
4549         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4550
4551         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4552         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4553 }
4554
4555 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4556 {
4557         if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
4558                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4559         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4560 }
4561
4562 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4563 {
4564         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4565
4566         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4567         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4568 }
4569
4570 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4571 {
4572         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4573
4574         if (!test_bit(VCPU_EXREG_PDPTR,
4575                       (unsigned long *)&vcpu->arch.regs_dirty))
4576                 return;
4577
4578         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4579                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4580                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4581                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4582                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4583         }
4584 }
4585
4586 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4587 {
4588         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4589
4590         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4591                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4592                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4593                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4594                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4595         }
4596
4597         __set_bit(VCPU_EXREG_PDPTR,
4598                   (unsigned long *)&vcpu->arch.regs_avail);
4599         __set_bit(VCPU_EXREG_PDPTR,
4600                   (unsigned long *)&vcpu->arch.regs_dirty);
4601 }
4602
4603 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4604 {
4605         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4606         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4607         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4608
4609         if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
4610                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4611             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4612                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4613
4614         return fixed_bits_valid(val, fixed0, fixed1);
4615 }
4616
4617 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4618 {
4619         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4620         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4621
4622         return fixed_bits_valid(val, fixed0, fixed1);
4623 }
4624
4625 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4626 {
4627         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
4628         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
4629
4630         return fixed_bits_valid(val, fixed0, fixed1);
4631 }
4632
4633 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4634 #define nested_guest_cr4_valid  nested_cr4_valid
4635 #define nested_host_cr4_valid   nested_cr4_valid
4636
4637 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4638
4639 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4640                                         unsigned long cr0,
4641                                         struct kvm_vcpu *vcpu)
4642 {
4643         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4644                 vmx_decache_cr3(vcpu);
4645         if (!(cr0 & X86_CR0_PG)) {
4646                 /* From paging/starting to nonpaging */
4647                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4648                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4649                              (CPU_BASED_CR3_LOAD_EXITING |
4650                               CPU_BASED_CR3_STORE_EXITING));
4651                 vcpu->arch.cr0 = cr0;
4652                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4653         } else if (!is_paging(vcpu)) {
4654                 /* From nonpaging to paging */
4655                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4656                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4657                              ~(CPU_BASED_CR3_LOAD_EXITING |
4658                                CPU_BASED_CR3_STORE_EXITING));
4659                 vcpu->arch.cr0 = cr0;
4660                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4661         }
4662
4663         if (!(cr0 & X86_CR0_WP))
4664                 *hw_cr0 &= ~X86_CR0_WP;
4665 }
4666
4667 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4668 {
4669         struct vcpu_vmx *vmx = to_vmx(vcpu);
4670         unsigned long hw_cr0;
4671
4672         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4673         if (enable_unrestricted_guest)
4674                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4675         else {
4676                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4677
4678                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4679                         enter_pmode(vcpu);
4680
4681                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4682                         enter_rmode(vcpu);
4683         }
4684
4685 #ifdef CONFIG_X86_64
4686         if (vcpu->arch.efer & EFER_LME) {
4687                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4688                         enter_lmode(vcpu);
4689                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4690                         exit_lmode(vcpu);
4691         }
4692 #endif
4693
4694         if (enable_ept && !enable_unrestricted_guest)
4695                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4696
4697         vmcs_writel(CR0_READ_SHADOW, cr0);
4698         vmcs_writel(GUEST_CR0, hw_cr0);
4699         vcpu->arch.cr0 = cr0;
4700
4701         /* depends on vcpu->arch.cr0 to be set to a new value */
4702         vmx->emulation_required = emulation_required(vcpu);
4703 }
4704
4705 static int get_ept_level(struct kvm_vcpu *vcpu)
4706 {
4707         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4708                 return 5;
4709         return 4;
4710 }
4711
4712 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4713 {
4714         u64 eptp = VMX_EPTP_MT_WB;
4715
4716         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4717
4718         if (enable_ept_ad_bits &&
4719             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4720                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4721         eptp |= (root_hpa & PAGE_MASK);
4722
4723         return eptp;
4724 }
4725
4726 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4727 {
4728         unsigned long guest_cr3;
4729         u64 eptp;
4730
4731         guest_cr3 = cr3;
4732         if (enable_ept) {
4733                 eptp = construct_eptp(vcpu, cr3);
4734                 vmcs_write64(EPT_POINTER, eptp);
4735                 if (enable_unrestricted_guest || is_paging(vcpu) ||
4736                     is_guest_mode(vcpu))
4737                         guest_cr3 = kvm_read_cr3(vcpu);
4738                 else
4739                         guest_cr3 = to_kvm_vmx(vcpu->kvm)->ept_identity_map_addr;
4740                 ept_load_pdptrs(vcpu);
4741         }
4742
4743         vmx_flush_tlb(vcpu, true);
4744         vmcs_writel(GUEST_CR3, guest_cr3);
4745 }
4746
4747 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4748 {
4749         /*
4750          * Pass through host's Machine Check Enable value to hw_cr4, which
4751          * is in force while we are in guest mode.  Do not let guests control
4752          * this bit, even if host CR4.MCE == 0.
4753          */
4754         unsigned long hw_cr4;
4755
4756         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
4757         if (enable_unrestricted_guest)
4758                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
4759         else if (to_vmx(vcpu)->rmode.vm86_active)
4760                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
4761         else
4762                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
4763
4764         if ((cr4 & X86_CR4_UMIP) && !boot_cpu_has(X86_FEATURE_UMIP)) {
4765                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4766                               SECONDARY_EXEC_DESC);
4767                 hw_cr4 &= ~X86_CR4_UMIP;
4768         } else if (!is_guest_mode(vcpu) ||
4769                    !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
4770                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4771                                 SECONDARY_EXEC_DESC);
4772
4773         if (cr4 & X86_CR4_VMXE) {
4774                 /*
4775                  * To use VMXON (and later other VMX instructions), a guest
4776                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4777                  * So basically the check on whether to allow nested VMX
4778                  * is here.
4779                  */
4780                 if (!nested_vmx_allowed(vcpu))
4781                         return 1;
4782         }
4783
4784         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4785                 return 1;
4786
4787         vcpu->arch.cr4 = cr4;
4788
4789         if (!enable_unrestricted_guest) {
4790                 if (enable_ept) {
4791                         if (!is_paging(vcpu)) {
4792                                 hw_cr4 &= ~X86_CR4_PAE;
4793                                 hw_cr4 |= X86_CR4_PSE;
4794                         } else if (!(cr4 & X86_CR4_PAE)) {
4795                                 hw_cr4 &= ~X86_CR4_PAE;
4796                         }
4797                 }
4798
4799                 /*
4800                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4801                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4802                  * to be manually disabled when guest switches to non-paging
4803                  * mode.
4804                  *
4805                  * If !enable_unrestricted_guest, the CPU is always running
4806                  * with CR0.PG=1 and CR4 needs to be modified.
4807                  * If enable_unrestricted_guest, the CPU automatically
4808                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4809                  */
4810                 if (!is_paging(vcpu))
4811                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4812         }
4813
4814         vmcs_writel(CR4_READ_SHADOW, cr4);
4815         vmcs_writel(GUEST_CR4, hw_cr4);
4816         return 0;
4817 }
4818
4819 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4820                             struct kvm_segment *var, int seg)
4821 {
4822         struct vcpu_vmx *vmx = to_vmx(vcpu);
4823         u32 ar;
4824
4825         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4826                 *var = vmx->rmode.segs[seg];
4827                 if (seg == VCPU_SREG_TR
4828                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4829                         return;
4830                 var->base = vmx_read_guest_seg_base(vmx, seg);
4831                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4832                 return;
4833         }
4834         var->base = vmx_read_guest_seg_base(vmx, seg);
4835         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4836         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4837         ar = vmx_read_guest_seg_ar(vmx, seg);
4838         var->unusable = (ar >> 16) & 1;
4839         var->type = ar & 15;
4840         var->s = (ar >> 4) & 1;
4841         var->dpl = (ar >> 5) & 3;
4842         /*
4843          * Some userspaces do not preserve unusable property. Since usable
4844          * segment has to be present according to VMX spec we can use present
4845          * property to amend userspace bug by making unusable segment always
4846          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4847          * segment as unusable.
4848          */
4849         var->present = !var->unusable;
4850         var->avl = (ar >> 12) & 1;
4851         var->l = (ar >> 13) & 1;
4852         var->db = (ar >> 14) & 1;
4853         var->g = (ar >> 15) & 1;
4854 }
4855
4856 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4857 {
4858         struct kvm_segment s;
4859
4860         if (to_vmx(vcpu)->rmode.vm86_active) {
4861                 vmx_get_segment(vcpu, &s, seg);
4862                 return s.base;
4863         }
4864         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4865 }
4866
4867 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4868 {
4869         struct vcpu_vmx *vmx = to_vmx(vcpu);
4870
4871         if (unlikely(vmx->rmode.vm86_active))
4872                 return 0;
4873         else {
4874                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4875                 return VMX_AR_DPL(ar);
4876         }
4877 }
4878
4879 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4880 {
4881         u32 ar;
4882
4883         if (var->unusable || !var->present)
4884                 ar = 1 << 16;
4885         else {
4886                 ar = var->type & 15;
4887                 ar |= (var->s & 1) << 4;
4888                 ar |= (var->dpl & 3) << 5;
4889                 ar |= (var->present & 1) << 7;
4890                 ar |= (var->avl & 1) << 12;
4891                 ar |= (var->l & 1) << 13;
4892                 ar |= (var->db & 1) << 14;
4893                 ar |= (var->g & 1) << 15;
4894         }
4895
4896         return ar;
4897 }
4898
4899 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4900                             struct kvm_segment *var, int seg)
4901 {
4902         struct vcpu_vmx *vmx = to_vmx(vcpu);
4903         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4904
4905         vmx_segment_cache_clear(vmx);
4906
4907         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4908                 vmx->rmode.segs[seg] = *var;
4909                 if (seg == VCPU_SREG_TR)
4910                         vmcs_write16(sf->selector, var->selector);
4911                 else if (var->s)
4912                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4913                 goto out;
4914         }
4915
4916         vmcs_writel(sf->base, var->base);
4917         vmcs_write32(sf->limit, var->limit);
4918         vmcs_write16(sf->selector, var->selector);
4919
4920         /*
4921          *   Fix the "Accessed" bit in AR field of segment registers for older
4922          * qemu binaries.
4923          *   IA32 arch specifies that at the time of processor reset the
4924          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4925          * is setting it to 0 in the userland code. This causes invalid guest
4926          * state vmexit when "unrestricted guest" mode is turned on.
4927          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4928          * tree. Newer qemu binaries with that qemu fix would not need this
4929          * kvm hack.
4930          */
4931         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4932                 var->type |= 0x1; /* Accessed */
4933
4934         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4935
4936 out:
4937         vmx->emulation_required = emulation_required(vcpu);
4938 }
4939
4940 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4941 {
4942         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4943
4944         *db = (ar >> 14) & 1;
4945         *l = (ar >> 13) & 1;
4946 }
4947
4948 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4949 {
4950         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4951         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4952 }
4953
4954 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4955 {
4956         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4957         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4958 }
4959
4960 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4961 {
4962         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4963         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4964 }
4965
4966 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4967 {
4968         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4969         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4970 }
4971
4972 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4973 {
4974         struct kvm_segment var;
4975         u32 ar;
4976
4977         vmx_get_segment(vcpu, &var, seg);
4978         var.dpl = 0x3;
4979         if (seg == VCPU_SREG_CS)
4980                 var.type = 0x3;
4981         ar = vmx_segment_access_rights(&var);
4982
4983         if (var.base != (var.selector << 4))
4984                 return false;
4985         if (var.limit != 0xffff)
4986                 return false;
4987         if (ar != 0xf3)
4988                 return false;
4989
4990         return true;
4991 }
4992
4993 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4994 {
4995         struct kvm_segment cs;
4996         unsigned int cs_rpl;
4997
4998         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4999         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
5000
5001         if (cs.unusable)
5002                 return false;
5003         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
5004                 return false;
5005         if (!cs.s)
5006                 return false;
5007         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
5008                 if (cs.dpl > cs_rpl)
5009                         return false;
5010         } else {
5011                 if (cs.dpl != cs_rpl)
5012                         return false;
5013         }
5014         if (!cs.present)
5015                 return false;
5016
5017         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5018         return true;
5019 }
5020
5021 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
5022 {
5023         struct kvm_segment ss;
5024         unsigned int ss_rpl;
5025
5026         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5027         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
5028
5029         if (ss.unusable)
5030                 return true;
5031         if (ss.type != 3 && ss.type != 7)
5032                 return false;
5033         if (!ss.s)
5034                 return false;
5035         if (ss.dpl != ss_rpl) /* DPL != RPL */
5036                 return false;
5037         if (!ss.present)
5038                 return false;
5039
5040         return true;
5041 }
5042
5043 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
5044 {
5045         struct kvm_segment var;
5046         unsigned int rpl;
5047
5048         vmx_get_segment(vcpu, &var, seg);
5049         rpl = var.selector & SEGMENT_RPL_MASK;
5050
5051         if (var.unusable)
5052                 return true;
5053         if (!var.s)
5054                 return false;
5055         if (!var.present)
5056                 return false;
5057         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
5058                 if (var.dpl < rpl) /* DPL < RPL */
5059                         return false;
5060         }
5061
5062         /* TODO: Add other members to kvm_segment_field to allow checking for other access
5063          * rights flags
5064          */
5065         return true;
5066 }
5067
5068 static bool tr_valid(struct kvm_vcpu *vcpu)
5069 {
5070         struct kvm_segment tr;
5071
5072         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
5073
5074         if (tr.unusable)
5075                 return false;
5076         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
5077                 return false;
5078         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
5079                 return false;
5080         if (!tr.present)
5081                 return false;
5082
5083         return true;
5084 }
5085
5086 static bool ldtr_valid(struct kvm_vcpu *vcpu)
5087 {
5088         struct kvm_segment ldtr;
5089
5090         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
5091
5092         if (ldtr.unusable)
5093                 return true;
5094         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
5095                 return false;
5096         if (ldtr.type != 2)
5097                 return false;
5098         if (!ldtr.present)
5099                 return false;
5100
5101         return true;
5102 }
5103
5104 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5105 {
5106         struct kvm_segment cs, ss;
5107
5108         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5109         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5110
5111         return ((cs.selector & SEGMENT_RPL_MASK) ==
5112                  (ss.selector & SEGMENT_RPL_MASK));
5113 }
5114
5115 /*
5116  * Check if guest state is valid. Returns true if valid, false if
5117  * not.
5118  * We assume that registers are always usable
5119  */
5120 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5121 {
5122         if (enable_unrestricted_guest)
5123                 return true;
5124
5125         /* real mode guest state checks */
5126         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5127                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5128                         return false;
5129                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5130                         return false;
5131                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5132                         return false;
5133                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5134                         return false;
5135                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5136                         return false;
5137                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5138                         return false;
5139         } else {
5140         /* protected mode guest state checks */
5141                 if (!cs_ss_rpl_check(vcpu))
5142                         return false;
5143                 if (!code_segment_valid(vcpu))
5144                         return false;
5145                 if (!stack_segment_valid(vcpu))
5146                         return false;
5147                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5148                         return false;
5149                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5150                         return false;
5151                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5152                         return false;
5153                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5154                         return false;
5155                 if (!tr_valid(vcpu))
5156                         return false;
5157                 if (!ldtr_valid(vcpu))
5158                         return false;
5159         }
5160         /* TODO:
5161          * - Add checks on RIP
5162          * - Add checks on RFLAGS
5163          */
5164
5165         return true;
5166 }
5167
5168 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5169 {
5170         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5171 }
5172
5173 static int init_rmode_tss(struct kvm *kvm)
5174 {
5175         gfn_t fn;
5176         u16 data = 0;
5177         int idx, r;
5178
5179         idx = srcu_read_lock(&kvm->srcu);
5180         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
5181         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5182         if (r < 0)
5183                 goto out;
5184         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5185         r = kvm_write_guest_page(kvm, fn++, &data,
5186                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
5187         if (r < 0)
5188                 goto out;
5189         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5190         if (r < 0)
5191                 goto out;
5192         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5193         if (r < 0)
5194                 goto out;
5195         data = ~0;
5196         r = kvm_write_guest_page(kvm, fn, &data,
5197                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5198                                  sizeof(u8));
5199 out:
5200         srcu_read_unlock(&kvm->srcu, idx);
5201         return r;
5202 }
5203
5204 static int init_rmode_identity_map(struct kvm *kvm)
5205 {
5206         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
5207         int i, idx, r = 0;
5208         kvm_pfn_t identity_map_pfn;
5209         u32 tmp;
5210
5211         /* Protect kvm_vmx->ept_identity_pagetable_done. */
5212         mutex_lock(&kvm->slots_lock);
5213
5214         if (likely(kvm_vmx->ept_identity_pagetable_done))
5215                 goto out2;
5216
5217         if (!kvm_vmx->ept_identity_map_addr)
5218                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5219         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
5220
5221         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5222                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
5223         if (r < 0)
5224                 goto out2;
5225
5226         idx = srcu_read_lock(&kvm->srcu);
5227         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5228         if (r < 0)
5229                 goto out;
5230         /* Set up identity-mapping pagetable for EPT in real mode */
5231         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5232                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5233                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5234                 r = kvm_write_guest_page(kvm, identity_map_pfn,
5235                                 &tmp, i * sizeof(tmp), sizeof(tmp));
5236                 if (r < 0)
5237                         goto out;
5238         }
5239         kvm_vmx->ept_identity_pagetable_done = true;
5240
5241 out:
5242         srcu_read_unlock(&kvm->srcu, idx);
5243
5244 out2:
5245         mutex_unlock(&kvm->slots_lock);
5246         return r;
5247 }
5248
5249 static void seg_setup(int seg)
5250 {
5251         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5252         unsigned int ar;
5253
5254         vmcs_write16(sf->selector, 0);
5255         vmcs_writel(sf->base, 0);
5256         vmcs_write32(sf->limit, 0xffff);
5257         ar = 0x93;
5258         if (seg == VCPU_SREG_CS)
5259                 ar |= 0x08; /* code segment */
5260
5261         vmcs_write32(sf->ar_bytes, ar);
5262 }
5263
5264 static int alloc_apic_access_page(struct kvm *kvm)
5265 {
5266         struct page *page;
5267         int r = 0;
5268
5269         mutex_lock(&kvm->slots_lock);
5270         if (kvm->arch.apic_access_page_done)
5271                 goto out;
5272         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5273                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5274         if (r)
5275                 goto out;
5276
5277         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5278         if (is_error_page(page)) {
5279                 r = -EFAULT;
5280                 goto out;
5281         }
5282
5283         /*
5284          * Do not pin the page in memory, so that memory hot-unplug
5285          * is able to migrate it.
5286          */
5287         put_page(page);
5288         kvm->arch.apic_access_page_done = true;
5289 out:
5290         mutex_unlock(&kvm->slots_lock);
5291         return r;
5292 }
5293
5294 static int allocate_vpid(void)
5295 {
5296         int vpid;
5297
5298         if (!enable_vpid)
5299                 return 0;
5300         spin_lock(&vmx_vpid_lock);
5301         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5302         if (vpid < VMX_NR_VPIDS)
5303                 __set_bit(vpid, vmx_vpid_bitmap);
5304         else
5305                 vpid = 0;
5306         spin_unlock(&vmx_vpid_lock);
5307         return vpid;
5308 }
5309
5310 static void free_vpid(int vpid)
5311 {
5312         if (!enable_vpid || vpid == 0)
5313                 return;
5314         spin_lock(&vmx_vpid_lock);
5315         __clear_bit(vpid, vmx_vpid_bitmap);
5316         spin_unlock(&vmx_vpid_lock);
5317 }
5318
5319 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5320                                                           u32 msr, int type)
5321 {
5322         int f = sizeof(unsigned long);
5323
5324         if (!cpu_has_vmx_msr_bitmap())
5325                 return;
5326
5327         /*
5328          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5329          * have the write-low and read-high bitmap offsets the wrong way round.
5330          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5331          */
5332         if (msr <= 0x1fff) {
5333                 if (type & MSR_TYPE_R)
5334                         /* read-low */
5335                         __clear_bit(msr, msr_bitmap + 0x000 / f);
5336
5337                 if (type & MSR_TYPE_W)
5338                         /* write-low */
5339                         __clear_bit(msr, msr_bitmap + 0x800 / f);
5340
5341         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5342                 msr &= 0x1fff;
5343                 if (type & MSR_TYPE_R)
5344                         /* read-high */
5345                         __clear_bit(msr, msr_bitmap + 0x400 / f);
5346
5347                 if (type & MSR_TYPE_W)
5348                         /* write-high */
5349                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
5350
5351         }
5352 }
5353
5354 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5355                                                          u32 msr, int type)
5356 {
5357         int f = sizeof(unsigned long);
5358
5359         if (!cpu_has_vmx_msr_bitmap())
5360                 return;
5361
5362         /*
5363          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5364          * have the write-low and read-high bitmap offsets the wrong way round.
5365          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5366          */
5367         if (msr <= 0x1fff) {
5368                 if (type & MSR_TYPE_R)
5369                         /* read-low */
5370                         __set_bit(msr, msr_bitmap + 0x000 / f);
5371
5372                 if (type & MSR_TYPE_W)
5373                         /* write-low */
5374                         __set_bit(msr, msr_bitmap + 0x800 / f);
5375
5376         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5377                 msr &= 0x1fff;
5378                 if (type & MSR_TYPE_R)
5379                         /* read-high */
5380                         __set_bit(msr, msr_bitmap + 0x400 / f);
5381
5382                 if (type & MSR_TYPE_W)
5383                         /* write-high */
5384                         __set_bit(msr, msr_bitmap + 0xc00 / f);
5385
5386         }
5387 }
5388
5389 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5390                                                       u32 msr, int type, bool value)
5391 {
5392         if (value)
5393                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
5394         else
5395                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
5396 }
5397
5398 /*
5399  * If a msr is allowed by L0, we should check whether it is allowed by L1.
5400  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5401  */
5402 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
5403                                                unsigned long *msr_bitmap_nested,
5404                                                u32 msr, int type)
5405 {
5406         int f = sizeof(unsigned long);
5407
5408         /*
5409          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5410          * have the write-low and read-high bitmap offsets the wrong way round.
5411          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5412          */
5413         if (msr <= 0x1fff) {
5414                 if (type & MSR_TYPE_R &&
5415                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
5416                         /* read-low */
5417                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
5418
5419                 if (type & MSR_TYPE_W &&
5420                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
5421                         /* write-low */
5422                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
5423
5424         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5425                 msr &= 0x1fff;
5426                 if (type & MSR_TYPE_R &&
5427                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
5428                         /* read-high */
5429                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
5430
5431                 if (type & MSR_TYPE_W &&
5432                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
5433                         /* write-high */
5434                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
5435
5436         }
5437 }
5438
5439 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5440 {
5441         u8 mode = 0;
5442
5443         if (cpu_has_secondary_exec_ctrls() &&
5444             (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5445              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5446                 mode |= MSR_BITMAP_MODE_X2APIC;
5447                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5448                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5449         }
5450
5451         if (is_long_mode(vcpu))
5452                 mode |= MSR_BITMAP_MODE_LM;
5453
5454         return mode;
5455 }
5456
5457 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5458
5459 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5460                                          u8 mode)
5461 {
5462         int msr;
5463
5464         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5465                 unsigned word = msr / BITS_PER_LONG;
5466                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5467                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5468         }
5469
5470         if (mode & MSR_BITMAP_MODE_X2APIC) {
5471                 /*
5472                  * TPR reads and writes can be virtualized even if virtual interrupt
5473                  * delivery is not in use.
5474                  */
5475                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5476                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5477                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5478                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5479                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5480                 }
5481         }
5482 }
5483
5484 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
5485 {
5486         struct vcpu_vmx *vmx = to_vmx(vcpu);
5487         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5488         u8 mode = vmx_msr_bitmap_mode(vcpu);
5489         u8 changed = mode ^ vmx->msr_bitmap_mode;
5490
5491         if (!changed)
5492                 return;
5493
5494         vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5495                                   !(mode & MSR_BITMAP_MODE_LM));
5496
5497         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5498                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5499
5500         vmx->msr_bitmap_mode = mode;
5501 }
5502
5503 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5504 {
5505         return enable_apicv;
5506 }
5507
5508 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5509 {
5510         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5511         gfn_t gfn;
5512
5513         /*
5514          * Don't need to mark the APIC access page dirty; it is never
5515          * written to by the CPU during APIC virtualization.
5516          */
5517
5518         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5519                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5520                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5521         }
5522
5523         if (nested_cpu_has_posted_intr(vmcs12)) {
5524                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5525                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5526         }
5527 }
5528
5529
5530 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5531 {
5532         struct vcpu_vmx *vmx = to_vmx(vcpu);
5533         int max_irr;
5534         void *vapic_page;
5535         u16 status;
5536
5537         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5538                 return;
5539
5540         vmx->nested.pi_pending = false;
5541         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5542                 return;
5543
5544         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5545         if (max_irr != 256) {
5546                 vapic_page = kmap(vmx->nested.virtual_apic_page);
5547                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
5548                         vapic_page, &max_irr);
5549                 kunmap(vmx->nested.virtual_apic_page);
5550
5551                 status = vmcs_read16(GUEST_INTR_STATUS);
5552                 if ((u8)max_irr > ((u8)status & 0xff)) {
5553                         status &= ~0xff;
5554                         status |= (u8)max_irr;
5555                         vmcs_write16(GUEST_INTR_STATUS, status);
5556                 }
5557         }
5558
5559         nested_mark_vmcs12_pages_dirty(vcpu);
5560 }
5561
5562 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5563                                                      bool nested)
5564 {
5565 #ifdef CONFIG_SMP
5566         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5567
5568         if (vcpu->mode == IN_GUEST_MODE) {
5569                 /*
5570                  * The vector of interrupt to be delivered to vcpu had
5571                  * been set in PIR before this function.
5572                  *
5573                  * Following cases will be reached in this block, and
5574                  * we always send a notification event in all cases as
5575                  * explained below.
5576                  *
5577                  * Case 1: vcpu keeps in non-root mode. Sending a
5578                  * notification event posts the interrupt to vcpu.
5579                  *
5580                  * Case 2: vcpu exits to root mode and is still
5581                  * runnable. PIR will be synced to vIRR before the
5582                  * next vcpu entry. Sending a notification event in
5583                  * this case has no effect, as vcpu is not in root
5584                  * mode.
5585                  *
5586                  * Case 3: vcpu exits to root mode and is blocked.
5587                  * vcpu_block() has already synced PIR to vIRR and
5588                  * never blocks vcpu if vIRR is not cleared. Therefore,
5589                  * a blocked vcpu here does not wait for any requested
5590                  * interrupts in PIR, and sending a notification event
5591                  * which has no effect is safe here.
5592                  */
5593
5594                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5595                 return true;
5596         }
5597 #endif
5598         return false;
5599 }
5600
5601 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5602                                                 int vector)
5603 {
5604         struct vcpu_vmx *vmx = to_vmx(vcpu);
5605
5606         if (is_guest_mode(vcpu) &&
5607             vector == vmx->nested.posted_intr_nv) {
5608                 /*
5609                  * If a posted intr is not recognized by hardware,
5610                  * we will accomplish it in the next vmentry.
5611                  */
5612                 vmx->nested.pi_pending = true;
5613                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5614                 /* the PIR and ON have been set by L1. */
5615                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
5616                         kvm_vcpu_kick(vcpu);
5617                 return 0;
5618         }
5619         return -1;
5620 }
5621 /*
5622  * Send interrupt to vcpu via posted interrupt way.
5623  * 1. If target vcpu is running(non-root mode), send posted interrupt
5624  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5625  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5626  * interrupt from PIR in next vmentry.
5627  */
5628 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5629 {
5630         struct vcpu_vmx *vmx = to_vmx(vcpu);
5631         int r;
5632
5633         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5634         if (!r)
5635                 return;
5636
5637         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5638                 return;
5639
5640         /* If a previous notification has sent the IPI, nothing to do.  */
5641         if (pi_test_and_set_on(&vmx->pi_desc))
5642                 return;
5643
5644         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5645                 kvm_vcpu_kick(vcpu);
5646 }
5647
5648 /*
5649  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5650  * will not change in the lifetime of the guest.
5651  * Note that host-state that does change is set elsewhere. E.g., host-state
5652  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5653  */
5654 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5655 {
5656         u32 low32, high32;
5657         unsigned long tmpl;
5658         struct desc_ptr dt;
5659         unsigned long cr0, cr3, cr4;
5660
5661         cr0 = read_cr0();
5662         WARN_ON(cr0 & X86_CR0_TS);
5663         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5664
5665         /*
5666          * Save the most likely value for this task's CR3 in the VMCS.
5667          * We can't use __get_current_cr3_fast() because we're not atomic.
5668          */
5669         cr3 = __read_cr3();
5670         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5671         vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5672
5673         /* Save the most likely value for this task's CR4 in the VMCS. */
5674         cr4 = cr4_read_shadow();
5675         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5676         vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5677
5678         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5679 #ifdef CONFIG_X86_64
5680         /*
5681          * Load null selectors, so we can avoid reloading them in
5682          * __vmx_load_host_state(), in case userspace uses the null selectors
5683          * too (the expected case).
5684          */
5685         vmcs_write16(HOST_DS_SELECTOR, 0);
5686         vmcs_write16(HOST_ES_SELECTOR, 0);
5687 #else
5688         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5689         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5690 #endif
5691         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5692         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5693
5694         store_idt(&dt);
5695         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5696         vmx->host_idt_base = dt.address;
5697
5698         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5699
5700         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5701         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5702         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5703         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5704
5705         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5706                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5707                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5708         }
5709 }
5710
5711 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5712 {
5713         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5714         if (enable_ept)
5715                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5716         if (is_guest_mode(&vmx->vcpu))
5717                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5718                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5719         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5720 }
5721
5722 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5723 {
5724         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5725
5726         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5727                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5728
5729         if (!enable_vnmi)
5730                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
5731
5732         /* Enable the preemption timer dynamically */
5733         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5734         return pin_based_exec_ctrl;
5735 }
5736
5737 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5738 {
5739         struct vcpu_vmx *vmx = to_vmx(vcpu);
5740
5741         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5742         if (cpu_has_secondary_exec_ctrls()) {
5743                 if (kvm_vcpu_apicv_active(vcpu))
5744                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5745                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5746                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5747                 else
5748                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5749                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5750                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5751         }
5752
5753         if (cpu_has_vmx_msr_bitmap())
5754                 vmx_update_msr_bitmap(vcpu);
5755 }
5756
5757 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5758 {
5759         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5760
5761         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5762                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5763
5764         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5765                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5766 #ifdef CONFIG_X86_64
5767                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5768                                 CPU_BASED_CR8_LOAD_EXITING;
5769 #endif
5770         }
5771         if (!enable_ept)
5772                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5773                                 CPU_BASED_CR3_LOAD_EXITING  |
5774                                 CPU_BASED_INVLPG_EXITING;
5775         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
5776                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
5777                                 CPU_BASED_MONITOR_EXITING);
5778         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
5779                 exec_control &= ~CPU_BASED_HLT_EXITING;
5780         return exec_control;
5781 }
5782
5783 static bool vmx_rdrand_supported(void)
5784 {
5785         return vmcs_config.cpu_based_2nd_exec_ctrl &
5786                 SECONDARY_EXEC_RDRAND_EXITING;
5787 }
5788
5789 static bool vmx_rdseed_supported(void)
5790 {
5791         return vmcs_config.cpu_based_2nd_exec_ctrl &
5792                 SECONDARY_EXEC_RDSEED_EXITING;
5793 }
5794
5795 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
5796 {
5797         struct kvm_vcpu *vcpu = &vmx->vcpu;
5798
5799         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5800
5801         if (!cpu_need_virtualize_apic_accesses(vcpu))
5802                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5803         if (vmx->vpid == 0)
5804                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5805         if (!enable_ept) {
5806                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5807                 enable_unrestricted_guest = 0;
5808                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5809                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5810         }
5811         if (!enable_unrestricted_guest)
5812                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5813         if (kvm_pause_in_guest(vmx->vcpu.kvm))
5814                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5815         if (!kvm_vcpu_apicv_active(vcpu))
5816                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5817                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5818         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5819
5820         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
5821          * in vmx_set_cr4.  */
5822         exec_control &= ~SECONDARY_EXEC_DESC;
5823
5824         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5825            (handle_vmptrld).
5826            We can NOT enable shadow_vmcs here because we don't have yet
5827            a current VMCS12
5828         */
5829         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5830
5831         if (!enable_pml)
5832                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5833
5834         if (vmx_xsaves_supported()) {
5835                 /* Exposing XSAVES only when XSAVE is exposed */
5836                 bool xsaves_enabled =
5837                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
5838                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
5839
5840                 if (!xsaves_enabled)
5841                         exec_control &= ~SECONDARY_EXEC_XSAVES;
5842
5843                 if (nested) {
5844                         if (xsaves_enabled)
5845                                 vmx->nested.msrs.secondary_ctls_high |=
5846                                         SECONDARY_EXEC_XSAVES;
5847                         else
5848                                 vmx->nested.msrs.secondary_ctls_high &=
5849                                         ~SECONDARY_EXEC_XSAVES;
5850                 }
5851         }
5852
5853         if (vmx_rdtscp_supported()) {
5854                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
5855                 if (!rdtscp_enabled)
5856                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
5857
5858                 if (nested) {
5859                         if (rdtscp_enabled)
5860                                 vmx->nested.msrs.secondary_ctls_high |=
5861                                         SECONDARY_EXEC_RDTSCP;
5862                         else
5863                                 vmx->nested.msrs.secondary_ctls_high &=
5864                                         ~SECONDARY_EXEC_RDTSCP;
5865                 }
5866         }
5867
5868         if (vmx_invpcid_supported()) {
5869                 /* Exposing INVPCID only when PCID is exposed */
5870                 bool invpcid_enabled =
5871                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
5872                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
5873
5874                 if (!invpcid_enabled) {
5875                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5876                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
5877                 }
5878
5879                 if (nested) {
5880                         if (invpcid_enabled)
5881                                 vmx->nested.msrs.secondary_ctls_high |=
5882                                         SECONDARY_EXEC_ENABLE_INVPCID;
5883                         else
5884                                 vmx->nested.msrs.secondary_ctls_high &=
5885                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
5886                 }
5887         }
5888
5889         if (vmx_rdrand_supported()) {
5890                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
5891                 if (rdrand_enabled)
5892                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
5893
5894                 if (nested) {
5895                         if (rdrand_enabled)
5896                                 vmx->nested.msrs.secondary_ctls_high |=
5897                                         SECONDARY_EXEC_RDRAND_EXITING;
5898                         else
5899                                 vmx->nested.msrs.secondary_ctls_high &=
5900                                         ~SECONDARY_EXEC_RDRAND_EXITING;
5901                 }
5902         }
5903
5904         if (vmx_rdseed_supported()) {
5905                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
5906                 if (rdseed_enabled)
5907                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
5908
5909                 if (nested) {
5910                         if (rdseed_enabled)
5911                                 vmx->nested.msrs.secondary_ctls_high |=
5912                                         SECONDARY_EXEC_RDSEED_EXITING;
5913                         else
5914                                 vmx->nested.msrs.secondary_ctls_high &=
5915                                         ~SECONDARY_EXEC_RDSEED_EXITING;
5916                 }
5917         }
5918
5919         vmx->secondary_exec_control = exec_control;
5920 }
5921
5922 static void ept_set_mmio_spte_mask(void)
5923 {
5924         /*
5925          * EPT Misconfigurations can be generated if the value of bits 2:0
5926          * of an EPT paging-structure entry is 110b (write/execute).
5927          */
5928         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5929                                    VMX_EPT_MISCONFIG_WX_VALUE);
5930 }
5931
5932 #define VMX_XSS_EXIT_BITMAP 0
5933 /*
5934  * Sets up the vmcs for emulated real mode.
5935  */
5936 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
5937 {
5938 #ifdef CONFIG_X86_64
5939         unsigned long a;
5940 #endif
5941         int i;
5942
5943         if (enable_shadow_vmcs) {
5944                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5945                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5946         }
5947         if (cpu_has_vmx_msr_bitmap())
5948                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
5949
5950         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5951
5952         /* Control */
5953         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5954         vmx->hv_deadline_tsc = -1;
5955
5956         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5957
5958         if (cpu_has_secondary_exec_ctrls()) {
5959                 vmx_compute_secondary_exec_control(vmx);
5960                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5961                              vmx->secondary_exec_control);
5962         }
5963
5964         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5965                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5966                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5967                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5968                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5969
5970                 vmcs_write16(GUEST_INTR_STATUS, 0);
5971
5972                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5973                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5974         }
5975
5976         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
5977                 vmcs_write32(PLE_GAP, ple_gap);
5978                 vmx->ple_window = ple_window;
5979                 vmx->ple_window_dirty = true;
5980         }
5981
5982         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5983         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5984         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5985
5986         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5987         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5988         vmx_set_constant_host_state(vmx);
5989 #ifdef CONFIG_X86_64
5990         rdmsrl(MSR_FS_BASE, a);
5991         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5992         rdmsrl(MSR_GS_BASE, a);
5993         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5994 #else
5995         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5996         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5997 #endif
5998
5999         if (cpu_has_vmx_vmfunc())
6000                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
6001
6002         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
6003         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
6004         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
6005         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6006         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6007
6008         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6009                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6010
6011         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6012                 u32 index = vmx_msr_index[i];
6013                 u32 data_low, data_high;
6014                 int j = vmx->nmsrs;
6015
6016                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6017                         continue;
6018                 if (wrmsr_safe(index, data_low, data_high) < 0)
6019                         continue;
6020                 vmx->guest_msrs[j].index = i;
6021                 vmx->guest_msrs[j].data = 0;
6022                 vmx->guest_msrs[j].mask = -1ull;
6023                 ++vmx->nmsrs;
6024         }
6025
6026         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
6027                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
6028
6029         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6030
6031         /* 22.2.1, 20.8.1 */
6032         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
6033
6034         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
6035         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
6036
6037         set_cr4_guest_host_mask(vmx);
6038
6039         if (vmx_xsaves_supported())
6040                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
6041
6042         if (enable_pml) {
6043                 ASSERT(vmx->pml_pg);
6044                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
6045                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6046         }
6047 }
6048
6049 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
6050 {
6051         struct vcpu_vmx *vmx = to_vmx(vcpu);
6052         struct msr_data apic_base_msr;
6053         u64 cr0;
6054
6055         vmx->rmode.vm86_active = 0;
6056         vmx->spec_ctrl = 0;
6057
6058         vcpu->arch.microcode_version = 0x100000000ULL;
6059         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
6060         kvm_set_cr8(vcpu, 0);
6061
6062         if (!init_event) {
6063                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6064                                      MSR_IA32_APICBASE_ENABLE;
6065                 if (kvm_vcpu_is_reset_bsp(vcpu))
6066                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6067                 apic_base_msr.host_initiated = true;
6068                 kvm_set_apic_base(vcpu, &apic_base_msr);
6069         }
6070
6071         vmx_segment_cache_clear(vmx);
6072
6073         seg_setup(VCPU_SREG_CS);
6074         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6075         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6076
6077         seg_setup(VCPU_SREG_DS);
6078         seg_setup(VCPU_SREG_ES);
6079         seg_setup(VCPU_SREG_FS);
6080         seg_setup(VCPU_SREG_GS);
6081         seg_setup(VCPU_SREG_SS);
6082
6083         vmcs_write16(GUEST_TR_SELECTOR, 0);
6084         vmcs_writel(GUEST_TR_BASE, 0);
6085         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6086         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6087
6088         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6089         vmcs_writel(GUEST_LDTR_BASE, 0);
6090         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6091         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6092
6093         if (!init_event) {
6094                 vmcs_write32(GUEST_SYSENTER_CS, 0);
6095                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6096                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6097                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6098         }
6099
6100         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6101         kvm_rip_write(vcpu, 0xfff0);
6102
6103         vmcs_writel(GUEST_GDTR_BASE, 0);
6104         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6105
6106         vmcs_writel(GUEST_IDTR_BASE, 0);
6107         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6108
6109         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6110         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6111         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6112         if (kvm_mpx_supported())
6113                 vmcs_write64(GUEST_BNDCFGS, 0);
6114
6115         setup_msrs(vmx);
6116
6117         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
6118
6119         if (cpu_has_vmx_tpr_shadow() && !init_event) {
6120                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6121                 if (cpu_need_tpr_shadow(vcpu))
6122                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6123                                      __pa(vcpu->arch.apic->regs));
6124                 vmcs_write32(TPR_THRESHOLD, 0);
6125         }
6126
6127         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6128
6129         if (vmx->vpid != 0)
6130                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6131
6132         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6133         vmx->vcpu.arch.cr0 = cr0;
6134         vmx_set_cr0(vcpu, cr0); /* enter rmode */
6135         vmx_set_cr4(vcpu, 0);
6136         vmx_set_efer(vcpu, 0);
6137
6138         update_exception_bitmap(vcpu);
6139
6140         vpid_sync_context(vmx->vpid);
6141         if (init_event)
6142                 vmx_clear_hlt(vcpu);
6143 }
6144
6145 /*
6146  * In nested virtualization, check if L1 asked to exit on external interrupts.
6147  * For most existing hypervisors, this will always return true.
6148  */
6149 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6150 {
6151         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6152                 PIN_BASED_EXT_INTR_MASK;
6153 }
6154
6155 /*
6156  * In nested virtualization, check if L1 has set
6157  * VM_EXIT_ACK_INTR_ON_EXIT
6158  */
6159 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6160 {
6161         return get_vmcs12(vcpu)->vm_exit_controls &
6162                 VM_EXIT_ACK_INTR_ON_EXIT;
6163 }
6164
6165 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6166 {
6167         return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
6168 }
6169
6170 static void enable_irq_window(struct kvm_vcpu *vcpu)
6171 {
6172         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6173                       CPU_BASED_VIRTUAL_INTR_PENDING);
6174 }
6175
6176 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6177 {
6178         if (!enable_vnmi ||
6179             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6180                 enable_irq_window(vcpu);
6181                 return;
6182         }
6183
6184         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6185                       CPU_BASED_VIRTUAL_NMI_PENDING);
6186 }
6187
6188 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6189 {
6190         struct vcpu_vmx *vmx = to_vmx(vcpu);
6191         uint32_t intr;
6192         int irq = vcpu->arch.interrupt.nr;
6193
6194         trace_kvm_inj_virq(irq);
6195
6196         ++vcpu->stat.irq_injections;
6197         if (vmx->rmode.vm86_active) {
6198                 int inc_eip = 0;
6199                 if (vcpu->arch.interrupt.soft)
6200                         inc_eip = vcpu->arch.event_exit_inst_len;
6201                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6202                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6203                 return;
6204         }
6205         intr = irq | INTR_INFO_VALID_MASK;
6206         if (vcpu->arch.interrupt.soft) {
6207                 intr |= INTR_TYPE_SOFT_INTR;
6208                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6209                              vmx->vcpu.arch.event_exit_inst_len);
6210         } else
6211                 intr |= INTR_TYPE_EXT_INTR;
6212         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6213
6214         vmx_clear_hlt(vcpu);
6215 }
6216
6217 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6218 {
6219         struct vcpu_vmx *vmx = to_vmx(vcpu);
6220
6221         if (!enable_vnmi) {
6222                 /*
6223                  * Tracking the NMI-blocked state in software is built upon
6224                  * finding the next open IRQ window. This, in turn, depends on
6225                  * well-behaving guests: They have to keep IRQs disabled at
6226                  * least as long as the NMI handler runs. Otherwise we may
6227                  * cause NMI nesting, maybe breaking the guest. But as this is
6228                  * highly unlikely, we can live with the residual risk.
6229                  */
6230                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6231                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6232         }
6233
6234         ++vcpu->stat.nmi_injections;
6235         vmx->loaded_vmcs->nmi_known_unmasked = false;
6236
6237         if (vmx->rmode.vm86_active) {
6238                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6239                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6240                 return;
6241         }
6242
6243         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6244                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6245
6246         vmx_clear_hlt(vcpu);
6247 }
6248
6249 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6250 {
6251         struct vcpu_vmx *vmx = to_vmx(vcpu);
6252         bool masked;
6253
6254         if (!enable_vnmi)
6255                 return vmx->loaded_vmcs->soft_vnmi_blocked;
6256         if (vmx->loaded_vmcs->nmi_known_unmasked)
6257                 return false;
6258         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6259         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6260         return masked;
6261 }
6262
6263 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6264 {
6265         struct vcpu_vmx *vmx = to_vmx(vcpu);
6266
6267         if (!enable_vnmi) {
6268                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6269                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6270                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
6271                 }
6272         } else {
6273                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6274                 if (masked)
6275                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6276                                       GUEST_INTR_STATE_NMI);
6277                 else
6278                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6279                                         GUEST_INTR_STATE_NMI);
6280         }
6281 }
6282
6283 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6284 {
6285         if (to_vmx(vcpu)->nested.nested_run_pending)
6286                 return 0;
6287
6288         if (!enable_vnmi &&
6289             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6290                 return 0;
6291
6292         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6293                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6294                    | GUEST_INTR_STATE_NMI));
6295 }
6296
6297 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6298 {
6299         return (!to_vmx(vcpu)->nested.nested_run_pending &&
6300                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6301                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6302                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6303 }
6304
6305 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6306 {
6307         int ret;
6308
6309         if (enable_unrestricted_guest)
6310                 return 0;
6311
6312         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6313                                     PAGE_SIZE * 3);
6314         if (ret)
6315                 return ret;
6316         to_kvm_vmx(kvm)->tss_addr = addr;
6317         return init_rmode_tss(kvm);
6318 }
6319
6320 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
6321 {
6322         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
6323         return 0;
6324 }
6325
6326 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6327 {
6328         switch (vec) {
6329         case BP_VECTOR:
6330                 /*
6331                  * Update instruction length as we may reinject the exception
6332                  * from user space while in guest debugging mode.
6333                  */
6334                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6335                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6336                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6337                         return false;
6338                 /* fall through */
6339         case DB_VECTOR:
6340                 if (vcpu->guest_debug &
6341                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6342                         return false;
6343                 /* fall through */
6344         case DE_VECTOR:
6345         case OF_VECTOR:
6346         case BR_VECTOR:
6347         case UD_VECTOR:
6348         case DF_VECTOR:
6349         case SS_VECTOR:
6350         case GP_VECTOR:
6351         case MF_VECTOR:
6352                 return true;
6353         break;
6354         }
6355         return false;
6356 }
6357
6358 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6359                                   int vec, u32 err_code)
6360 {
6361         /*
6362          * Instruction with address size override prefix opcode 0x67
6363          * Cause the #SS fault with 0 error code in VM86 mode.
6364          */
6365         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6366                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6367                         if (vcpu->arch.halt_request) {
6368                                 vcpu->arch.halt_request = 0;
6369                                 return kvm_vcpu_halt(vcpu);
6370                         }
6371                         return 1;
6372                 }
6373                 return 0;
6374         }
6375
6376         /*
6377          * Forward all other exceptions that are valid in real mode.
6378          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6379          *        the required debugging infrastructure rework.
6380          */
6381         kvm_queue_exception(vcpu, vec);
6382         return 1;
6383 }
6384
6385 /*
6386  * Trigger machine check on the host. We assume all the MSRs are already set up
6387  * by the CPU and that we still run on the same CPU as the MCE occurred on.
6388  * We pass a fake environment to the machine check handler because we want
6389  * the guest to be always treated like user space, no matter what context
6390  * it used internally.
6391  */
6392 static void kvm_machine_check(void)
6393 {
6394 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6395         struct pt_regs regs = {
6396                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
6397                 .flags = X86_EFLAGS_IF,
6398         };
6399
6400         do_machine_check(&regs, 0);
6401 #endif
6402 }
6403
6404 static int handle_machine_check(struct kvm_vcpu *vcpu)
6405 {
6406         /* already handled by vcpu_run */
6407         return 1;
6408 }
6409
6410 static int handle_exception(struct kvm_vcpu *vcpu)
6411 {
6412         struct vcpu_vmx *vmx = to_vmx(vcpu);
6413         struct kvm_run *kvm_run = vcpu->run;
6414         u32 intr_info, ex_no, error_code;
6415         unsigned long cr2, rip, dr6;
6416         u32 vect_info;
6417         enum emulation_result er;
6418
6419         vect_info = vmx->idt_vectoring_info;
6420         intr_info = vmx->exit_intr_info;
6421
6422         if (is_machine_check(intr_info))
6423                 return handle_machine_check(vcpu);
6424
6425         if (is_nmi(intr_info))
6426                 return 1;  /* already handled by vmx_vcpu_run() */
6427
6428         if (is_invalid_opcode(intr_info))
6429                 return handle_ud(vcpu);
6430
6431         error_code = 0;
6432         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6433                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6434
6435         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
6436                 WARN_ON_ONCE(!enable_vmware_backdoor);
6437                 er = emulate_instruction(vcpu,
6438                         EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
6439                 if (er == EMULATE_USER_EXIT)
6440                         return 0;
6441                 else if (er != EMULATE_DONE)
6442                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
6443                 return 1;
6444         }
6445
6446         /*
6447          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6448          * MMIO, it is better to report an internal error.
6449          * See the comments in vmx_handle_exit.
6450          */
6451         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
6452             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
6453                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6454                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
6455                 vcpu->run->internal.ndata = 3;
6456                 vcpu->run->internal.data[0] = vect_info;
6457                 vcpu->run->internal.data[1] = intr_info;
6458                 vcpu->run->internal.data[2] = error_code;
6459                 return 0;
6460         }
6461
6462         if (is_page_fault(intr_info)) {
6463                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
6464                 /* EPT won't cause page fault directly */
6465                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
6466                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6467         }
6468
6469         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
6470
6471         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
6472                 return handle_rmode_exception(vcpu, ex_no, error_code);
6473
6474         switch (ex_no) {
6475         case AC_VECTOR:
6476                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
6477                 return 1;
6478         case DB_VECTOR:
6479                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
6480                 if (!(vcpu->guest_debug &
6481                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
6482                         vcpu->arch.dr6 &= ~15;
6483                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
6484                         if (is_icebp(intr_info))
6485                                 skip_emulated_instruction(vcpu);
6486
6487                         kvm_queue_exception(vcpu, DB_VECTOR);
6488                         return 1;
6489                 }
6490                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
6491                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
6492                 /* fall through */
6493         case BP_VECTOR:
6494                 /*
6495                  * Update instruction length as we may reinject #BP from
6496                  * user space while in guest debugging mode. Reading it for
6497                  * #DB as well causes no harm, it is not used in that case.
6498                  */
6499                 vmx->vcpu.arch.event_exit_inst_len =
6500                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6501                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6502                 rip = kvm_rip_read(vcpu);
6503                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
6504                 kvm_run->debug.arch.exception = ex_no;
6505                 break;
6506         default:
6507                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6508                 kvm_run->ex.exception = ex_no;
6509                 kvm_run->ex.error_code = error_code;
6510                 break;
6511         }
6512         return 0;
6513 }
6514
6515 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6516 {
6517         ++vcpu->stat.irq_exits;
6518         return 1;
6519 }
6520
6521 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6522 {
6523         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6524         vcpu->mmio_needed = 0;
6525         return 0;
6526 }
6527
6528 static int handle_io(struct kvm_vcpu *vcpu)
6529 {
6530         unsigned long exit_qualification;
6531         int size, in, string;
6532         unsigned port;
6533
6534         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6535         string = (exit_qualification & 16) != 0;
6536
6537         ++vcpu->stat.io_exits;
6538
6539         if (string)
6540                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6541
6542         port = exit_qualification >> 16;
6543         size = (exit_qualification & 7) + 1;
6544         in = (exit_qualification & 8) != 0;
6545
6546         return kvm_fast_pio(vcpu, size, port, in);
6547 }
6548
6549 static void
6550 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6551 {
6552         /*
6553          * Patch in the VMCALL instruction:
6554          */
6555         hypercall[0] = 0x0f;
6556         hypercall[1] = 0x01;
6557         hypercall[2] = 0xc1;
6558 }
6559
6560 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6561 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6562 {
6563         if (is_guest_mode(vcpu)) {
6564                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6565                 unsigned long orig_val = val;
6566
6567                 /*
6568                  * We get here when L2 changed cr0 in a way that did not change
6569                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6570                  * but did change L0 shadowed bits. So we first calculate the
6571                  * effective cr0 value that L1 would like to write into the
6572                  * hardware. It consists of the L2-owned bits from the new
6573                  * value combined with the L1-owned bits from L1's guest_cr0.
6574                  */
6575                 val = (val & ~vmcs12->cr0_guest_host_mask) |
6576                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6577
6578                 if (!nested_guest_cr0_valid(vcpu, val))
6579                         return 1;
6580
6581                 if (kvm_set_cr0(vcpu, val))
6582                         return 1;
6583                 vmcs_writel(CR0_READ_SHADOW, orig_val);
6584                 return 0;
6585         } else {
6586                 if (to_vmx(vcpu)->nested.vmxon &&
6587                     !nested_host_cr0_valid(vcpu, val))
6588                         return 1;
6589
6590                 return kvm_set_cr0(vcpu, val);
6591         }
6592 }
6593
6594 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6595 {
6596         if (is_guest_mode(vcpu)) {
6597                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6598                 unsigned long orig_val = val;
6599
6600                 /* analogously to handle_set_cr0 */
6601                 val = (val & ~vmcs12->cr4_guest_host_mask) |
6602                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6603                 if (kvm_set_cr4(vcpu, val))
6604                         return 1;
6605                 vmcs_writel(CR4_READ_SHADOW, orig_val);
6606                 return 0;
6607         } else
6608                 return kvm_set_cr4(vcpu, val);
6609 }
6610
6611 static int handle_desc(struct kvm_vcpu *vcpu)
6612 {
6613         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
6614         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6615 }
6616
6617 static int handle_cr(struct kvm_vcpu *vcpu)
6618 {
6619         unsigned long exit_qualification, val;
6620         int cr;
6621         int reg;
6622         int err;
6623         int ret;
6624
6625         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6626         cr = exit_qualification & 15;
6627         reg = (exit_qualification >> 8) & 15;
6628         switch ((exit_qualification >> 4) & 3) {
6629         case 0: /* mov to cr */
6630                 val = kvm_register_readl(vcpu, reg);
6631                 trace_kvm_cr_write(cr, val);
6632                 switch (cr) {
6633                 case 0:
6634                         err = handle_set_cr0(vcpu, val);
6635                         return kvm_complete_insn_gp(vcpu, err);
6636                 case 3:
6637                         WARN_ON_ONCE(enable_unrestricted_guest);
6638                         err = kvm_set_cr3(vcpu, val);
6639                         return kvm_complete_insn_gp(vcpu, err);
6640                 case 4:
6641                         err = handle_set_cr4(vcpu, val);
6642                         return kvm_complete_insn_gp(vcpu, err);
6643                 case 8: {
6644                                 u8 cr8_prev = kvm_get_cr8(vcpu);
6645                                 u8 cr8 = (u8)val;
6646                                 err = kvm_set_cr8(vcpu, cr8);
6647                                 ret = kvm_complete_insn_gp(vcpu, err);
6648                                 if (lapic_in_kernel(vcpu))
6649                                         return ret;
6650                                 if (cr8_prev <= cr8)
6651                                         return ret;
6652                                 /*
6653                                  * TODO: we might be squashing a
6654                                  * KVM_GUESTDBG_SINGLESTEP-triggered
6655                                  * KVM_EXIT_DEBUG here.
6656                                  */
6657                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6658                                 return 0;
6659                         }
6660                 }
6661                 break;
6662         case 2: /* clts */
6663                 WARN_ONCE(1, "Guest should always own CR0.TS");
6664                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6665                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6666                 return kvm_skip_emulated_instruction(vcpu);
6667         case 1: /*mov from cr*/
6668                 switch (cr) {
6669                 case 3:
6670                         WARN_ON_ONCE(enable_unrestricted_guest);
6671                         val = kvm_read_cr3(vcpu);
6672                         kvm_register_write(vcpu, reg, val);
6673                         trace_kvm_cr_read(cr, val);
6674                         return kvm_skip_emulated_instruction(vcpu);
6675                 case 8:
6676                         val = kvm_get_cr8(vcpu);
6677                         kvm_register_write(vcpu, reg, val);
6678                         trace_kvm_cr_read(cr, val);
6679                         return kvm_skip_emulated_instruction(vcpu);
6680                 }
6681                 break;
6682         case 3: /* lmsw */
6683                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6684                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6685                 kvm_lmsw(vcpu, val);
6686
6687                 return kvm_skip_emulated_instruction(vcpu);
6688         default:
6689                 break;
6690         }
6691         vcpu->run->exit_reason = 0;
6692         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6693                (int)(exit_qualification >> 4) & 3, cr);
6694         return 0;
6695 }
6696
6697 static int handle_dr(struct kvm_vcpu *vcpu)
6698 {
6699         unsigned long exit_qualification;
6700         int dr, dr7, reg;
6701
6702         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6703         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6704
6705         /* First, if DR does not exist, trigger UD */
6706         if (!kvm_require_dr(vcpu, dr))
6707                 return 1;
6708
6709         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6710         if (!kvm_require_cpl(vcpu, 0))
6711                 return 1;
6712         dr7 = vmcs_readl(GUEST_DR7);
6713         if (dr7 & DR7_GD) {
6714                 /*
6715                  * As the vm-exit takes precedence over the debug trap, we
6716                  * need to emulate the latter, either for the host or the
6717                  * guest debugging itself.
6718                  */
6719                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6720                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6721                         vcpu->run->debug.arch.dr7 = dr7;
6722                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6723                         vcpu->run->debug.arch.exception = DB_VECTOR;
6724                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6725                         return 0;
6726                 } else {
6727                         vcpu->arch.dr6 &= ~15;
6728                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6729                         kvm_queue_exception(vcpu, DB_VECTOR);
6730                         return 1;
6731                 }
6732         }
6733
6734         if (vcpu->guest_debug == 0) {
6735                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6736                                 CPU_BASED_MOV_DR_EXITING);
6737
6738                 /*
6739                  * No more DR vmexits; force a reload of the debug registers
6740                  * and reenter on this instruction.  The next vmexit will
6741                  * retrieve the full state of the debug registers.
6742                  */
6743                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6744                 return 1;
6745         }
6746
6747         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6748         if (exit_qualification & TYPE_MOV_FROM_DR) {
6749                 unsigned long val;
6750
6751                 if (kvm_get_dr(vcpu, dr, &val))
6752                         return 1;
6753                 kvm_register_write(vcpu, reg, val);
6754         } else
6755                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6756                         return 1;
6757
6758         return kvm_skip_emulated_instruction(vcpu);
6759 }
6760
6761 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6762 {
6763         return vcpu->arch.dr6;
6764 }
6765
6766 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6767 {
6768 }
6769
6770 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6771 {
6772         get_debugreg(vcpu->arch.db[0], 0);
6773         get_debugreg(vcpu->arch.db[1], 1);
6774         get_debugreg(vcpu->arch.db[2], 2);
6775         get_debugreg(vcpu->arch.db[3], 3);
6776         get_debugreg(vcpu->arch.dr6, 6);
6777         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6778
6779         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6780         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6781 }
6782
6783 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6784 {
6785         vmcs_writel(GUEST_DR7, val);
6786 }
6787
6788 static int handle_cpuid(struct kvm_vcpu *vcpu)
6789 {
6790         return kvm_emulate_cpuid(vcpu);
6791 }
6792
6793 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6794 {
6795         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6796         struct msr_data msr_info;
6797
6798         msr_info.index = ecx;
6799         msr_info.host_initiated = false;
6800         if (vmx_get_msr(vcpu, &msr_info)) {
6801                 trace_kvm_msr_read_ex(ecx);
6802                 kvm_inject_gp(vcpu, 0);
6803                 return 1;
6804         }
6805
6806         trace_kvm_msr_read(ecx, msr_info.data);
6807
6808         /* FIXME: handling of bits 32:63 of rax, rdx */
6809         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6810         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6811         return kvm_skip_emulated_instruction(vcpu);
6812 }
6813
6814 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6815 {
6816         struct msr_data msr;
6817         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6818         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6819                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6820
6821         msr.data = data;
6822         msr.index = ecx;
6823         msr.host_initiated = false;
6824         if (kvm_set_msr(vcpu, &msr) != 0) {
6825                 trace_kvm_msr_write_ex(ecx, data);
6826                 kvm_inject_gp(vcpu, 0);
6827                 return 1;
6828         }
6829
6830         trace_kvm_msr_write(ecx, data);
6831         return kvm_skip_emulated_instruction(vcpu);
6832 }
6833
6834 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6835 {
6836         kvm_apic_update_ppr(vcpu);
6837         return 1;
6838 }
6839
6840 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6841 {
6842         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6843                         CPU_BASED_VIRTUAL_INTR_PENDING);
6844
6845         kvm_make_request(KVM_REQ_EVENT, vcpu);
6846
6847         ++vcpu->stat.irq_window_exits;
6848         return 1;
6849 }
6850
6851 static int handle_halt(struct kvm_vcpu *vcpu)
6852 {
6853         return kvm_emulate_halt(vcpu);
6854 }
6855
6856 static int handle_vmcall(struct kvm_vcpu *vcpu)
6857 {
6858         return kvm_emulate_hypercall(vcpu);
6859 }
6860
6861 static int handle_invd(struct kvm_vcpu *vcpu)
6862 {
6863         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6864 }
6865
6866 static int handle_invlpg(struct kvm_vcpu *vcpu)
6867 {
6868         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6869
6870         kvm_mmu_invlpg(vcpu, exit_qualification);
6871         return kvm_skip_emulated_instruction(vcpu);
6872 }
6873
6874 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6875 {
6876         int err;
6877
6878         err = kvm_rdpmc(vcpu);
6879         return kvm_complete_insn_gp(vcpu, err);
6880 }
6881
6882 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6883 {
6884         return kvm_emulate_wbinvd(vcpu);
6885 }
6886
6887 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6888 {
6889         u64 new_bv = kvm_read_edx_eax(vcpu);
6890         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6891
6892         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6893                 return kvm_skip_emulated_instruction(vcpu);
6894         return 1;
6895 }
6896
6897 static int handle_xsaves(struct kvm_vcpu *vcpu)
6898 {
6899         kvm_skip_emulated_instruction(vcpu);
6900         WARN(1, "this should never happen\n");
6901         return 1;
6902 }
6903
6904 static int handle_xrstors(struct kvm_vcpu *vcpu)
6905 {
6906         kvm_skip_emulated_instruction(vcpu);
6907         WARN(1, "this should never happen\n");
6908         return 1;
6909 }
6910
6911 static int handle_apic_access(struct kvm_vcpu *vcpu)
6912 {
6913         if (likely(fasteoi)) {
6914                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6915                 int access_type, offset;
6916
6917                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6918                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6919                 /*
6920                  * Sane guest uses MOV to write EOI, with written value
6921                  * not cared. So make a short-circuit here by avoiding
6922                  * heavy instruction emulation.
6923                  */
6924                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6925                     (offset == APIC_EOI)) {
6926                         kvm_lapic_set_eoi(vcpu);
6927                         return kvm_skip_emulated_instruction(vcpu);
6928                 }
6929         }
6930         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6931 }
6932
6933 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6934 {
6935         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6936         int vector = exit_qualification & 0xff;
6937
6938         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6939         kvm_apic_set_eoi_accelerated(vcpu, vector);
6940         return 1;
6941 }
6942
6943 static int handle_apic_write(struct kvm_vcpu *vcpu)
6944 {
6945         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6946         u32 offset = exit_qualification & 0xfff;
6947
6948         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6949         kvm_apic_write_nodecode(vcpu, offset);
6950         return 1;
6951 }
6952
6953 static int handle_task_switch(struct kvm_vcpu *vcpu)
6954 {
6955         struct vcpu_vmx *vmx = to_vmx(vcpu);
6956         unsigned long exit_qualification;
6957         bool has_error_code = false;
6958         u32 error_code = 0;
6959         u16 tss_selector;
6960         int reason, type, idt_v, idt_index;
6961
6962         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6963         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6964         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6965
6966         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6967
6968         reason = (u32)exit_qualification >> 30;
6969         if (reason == TASK_SWITCH_GATE && idt_v) {
6970                 switch (type) {
6971                 case INTR_TYPE_NMI_INTR:
6972                         vcpu->arch.nmi_injected = false;
6973                         vmx_set_nmi_mask(vcpu, true);
6974                         break;
6975                 case INTR_TYPE_EXT_INTR:
6976                 case INTR_TYPE_SOFT_INTR:
6977                         kvm_clear_interrupt_queue(vcpu);
6978                         break;
6979                 case INTR_TYPE_HARD_EXCEPTION:
6980                         if (vmx->idt_vectoring_info &
6981                             VECTORING_INFO_DELIVER_CODE_MASK) {
6982                                 has_error_code = true;
6983                                 error_code =
6984                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6985                         }
6986                         /* fall through */
6987                 case INTR_TYPE_SOFT_EXCEPTION:
6988                         kvm_clear_exception_queue(vcpu);
6989                         break;
6990                 default:
6991                         break;
6992                 }
6993         }
6994         tss_selector = exit_qualification;
6995
6996         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6997                        type != INTR_TYPE_EXT_INTR &&
6998                        type != INTR_TYPE_NMI_INTR))
6999                 skip_emulated_instruction(vcpu);
7000
7001         if (kvm_task_switch(vcpu, tss_selector,
7002                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
7003                             has_error_code, error_code) == EMULATE_FAIL) {
7004                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7005                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7006                 vcpu->run->internal.ndata = 0;
7007                 return 0;
7008         }
7009
7010         /*
7011          * TODO: What about debug traps on tss switch?
7012          *       Are we supposed to inject them and update dr6?
7013          */
7014
7015         return 1;
7016 }
7017
7018 static int handle_ept_violation(struct kvm_vcpu *vcpu)
7019 {
7020         unsigned long exit_qualification;
7021         gpa_t gpa;
7022         u64 error_code;
7023
7024         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7025
7026         /*
7027          * EPT violation happened while executing iret from NMI,
7028          * "blocked by NMI" bit has to be set before next VM entry.
7029          * There are errata that may cause this bit to not be set:
7030          * AAK134, BY25.
7031          */
7032         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7033                         enable_vnmi &&
7034                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7035                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
7036
7037         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7038         trace_kvm_page_fault(gpa, exit_qualification);
7039
7040         /* Is it a read fault? */
7041         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
7042                      ? PFERR_USER_MASK : 0;
7043         /* Is it a write fault? */
7044         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
7045                       ? PFERR_WRITE_MASK : 0;
7046         /* Is it a fetch fault? */
7047         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
7048                       ? PFERR_FETCH_MASK : 0;
7049         /* ept page table entry is present? */
7050         error_code |= (exit_qualification &
7051                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
7052                         EPT_VIOLATION_EXECUTABLE))
7053                       ? PFERR_PRESENT_MASK : 0;
7054
7055         error_code |= (exit_qualification & 0x100) != 0 ?
7056                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
7057
7058         vcpu->arch.exit_qualification = exit_qualification;
7059         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
7060 }
7061
7062 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
7063 {
7064         gpa_t gpa;
7065
7066         /*
7067          * A nested guest cannot optimize MMIO vmexits, because we have an
7068          * nGPA here instead of the required GPA.
7069          */
7070         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7071         if (!is_guest_mode(vcpu) &&
7072             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
7073                 trace_kvm_fast_mmio(gpa);
7074                 /*
7075                  * Doing kvm_skip_emulated_instruction() depends on undefined
7076                  * behavior: Intel's manual doesn't mandate
7077                  * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7078                  * occurs and while on real hardware it was observed to be set,
7079                  * other hypervisors (namely Hyper-V) don't set it, we end up
7080                  * advancing IP with some random value. Disable fast mmio when
7081                  * running nested and keep it for real hardware in hope that
7082                  * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7083                  */
7084                 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7085                         return kvm_skip_emulated_instruction(vcpu);
7086                 else
7087                         return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP,
7088                                                        NULL, 0) == EMULATE_DONE;
7089         }
7090
7091         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7092 }
7093
7094 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7095 {
7096         WARN_ON_ONCE(!enable_vnmi);
7097         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7098                         CPU_BASED_VIRTUAL_NMI_PENDING);
7099         ++vcpu->stat.nmi_window_exits;
7100         kvm_make_request(KVM_REQ_EVENT, vcpu);
7101
7102         return 1;
7103 }
7104
7105 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7106 {
7107         struct vcpu_vmx *vmx = to_vmx(vcpu);
7108         enum emulation_result err = EMULATE_DONE;
7109         int ret = 1;
7110         u32 cpu_exec_ctrl;
7111         bool intr_window_requested;
7112         unsigned count = 130;
7113
7114         /*
7115          * We should never reach the point where we are emulating L2
7116          * due to invalid guest state as that means we incorrectly
7117          * allowed a nested VMEntry with an invalid vmcs12.
7118          */
7119         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
7120
7121         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7122         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7123
7124         while (vmx->emulation_required && count-- != 0) {
7125                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7126                         return handle_interrupt_window(&vmx->vcpu);
7127
7128                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7129                         return 1;
7130
7131                 err = emulate_instruction(vcpu, 0);
7132
7133                 if (err == EMULATE_USER_EXIT) {
7134                         ++vcpu->stat.mmio_exits;
7135                         ret = 0;
7136                         goto out;
7137                 }
7138
7139                 if (err != EMULATE_DONE)
7140                         goto emulation_error;
7141
7142                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7143                     vcpu->arch.exception.pending)
7144                         goto emulation_error;
7145
7146                 if (vcpu->arch.halt_request) {
7147                         vcpu->arch.halt_request = 0;
7148                         ret = kvm_vcpu_halt(vcpu);
7149                         goto out;
7150                 }
7151
7152                 if (signal_pending(current))
7153                         goto out;
7154                 if (need_resched())
7155                         schedule();
7156         }
7157
7158 out:
7159         return ret;
7160
7161 emulation_error:
7162         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7163         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7164         vcpu->run->internal.ndata = 0;
7165         return 0;
7166 }
7167
7168 static void grow_ple_window(struct kvm_vcpu *vcpu)
7169 {
7170         struct vcpu_vmx *vmx = to_vmx(vcpu);
7171         int old = vmx->ple_window;
7172
7173         vmx->ple_window = __grow_ple_window(old, ple_window,
7174                                             ple_window_grow,
7175                                             ple_window_max);
7176
7177         if (vmx->ple_window != old)
7178                 vmx->ple_window_dirty = true;
7179
7180         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7181 }
7182
7183 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7184 {
7185         struct vcpu_vmx *vmx = to_vmx(vcpu);
7186         int old = vmx->ple_window;
7187
7188         vmx->ple_window = __shrink_ple_window(old, ple_window,
7189                                               ple_window_shrink,
7190                                               ple_window);
7191
7192         if (vmx->ple_window != old)
7193                 vmx->ple_window_dirty = true;
7194
7195         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7196 }
7197
7198 /*
7199  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7200  */
7201 static void wakeup_handler(void)
7202 {
7203         struct kvm_vcpu *vcpu;
7204         int cpu = smp_processor_id();
7205
7206         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7207         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7208                         blocked_vcpu_list) {
7209                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7210
7211                 if (pi_test_on(pi_desc) == 1)
7212                         kvm_vcpu_kick(vcpu);
7213         }
7214         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7215 }
7216
7217 static void vmx_enable_tdp(void)
7218 {
7219         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7220                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7221                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7222                 0ull, VMX_EPT_EXECUTABLE_MASK,
7223                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7224                 VMX_EPT_RWX_MASK, 0ull);
7225
7226         ept_set_mmio_spte_mask();
7227         kvm_enable_tdp();
7228 }
7229
7230 static __init int hardware_setup(void)
7231 {
7232         int r = -ENOMEM, i;
7233
7234         rdmsrl_safe(MSR_EFER, &host_efer);
7235
7236         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7237                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7238
7239         for (i = 0; i < VMX_BITMAP_NR; i++) {
7240                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7241                 if (!vmx_bitmap[i])
7242                         goto out;
7243         }
7244
7245         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7246         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7247
7248         if (setup_vmcs_config(&vmcs_config) < 0) {
7249                 r = -EIO;
7250                 goto out;
7251         }
7252
7253         if (boot_cpu_has(X86_FEATURE_NX))
7254                 kvm_enable_efer_bits(EFER_NX);
7255
7256         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7257                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7258                 enable_vpid = 0;
7259
7260         if (!cpu_has_vmx_ept() ||
7261             !cpu_has_vmx_ept_4levels() ||
7262             !cpu_has_vmx_ept_mt_wb() ||
7263             !cpu_has_vmx_invept_global())
7264                 enable_ept = 0;
7265
7266         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7267                 enable_ept_ad_bits = 0;
7268
7269         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7270                 enable_unrestricted_guest = 0;
7271
7272         if (!cpu_has_vmx_flexpriority())
7273                 flexpriority_enabled = 0;
7274
7275         if (!cpu_has_virtual_nmis())
7276                 enable_vnmi = 0;
7277
7278         /*
7279          * set_apic_access_page_addr() is used to reload apic access
7280          * page upon invalidation.  No need to do anything if not
7281          * using the APIC_ACCESS_ADDR VMCS field.
7282          */
7283         if (!flexpriority_enabled)
7284                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7285
7286         if (!cpu_has_vmx_tpr_shadow())
7287                 kvm_x86_ops->update_cr8_intercept = NULL;
7288
7289         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7290                 kvm_disable_largepages();
7291
7292         if (!cpu_has_vmx_ple()) {
7293                 ple_gap = 0;
7294                 ple_window = 0;
7295                 ple_window_grow = 0;
7296                 ple_window_max = 0;
7297                 ple_window_shrink = 0;
7298         }
7299
7300         if (!cpu_has_vmx_apicv()) {
7301                 enable_apicv = 0;
7302                 kvm_x86_ops->sync_pir_to_irr = NULL;
7303         }
7304
7305         if (cpu_has_vmx_tsc_scaling()) {
7306                 kvm_has_tsc_control = true;
7307                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7308                 kvm_tsc_scaling_ratio_frac_bits = 48;
7309         }
7310
7311         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7312
7313         if (enable_ept)
7314                 vmx_enable_tdp();
7315         else
7316                 kvm_disable_tdp();
7317
7318         /*
7319          * Only enable PML when hardware supports PML feature, and both EPT
7320          * and EPT A/D bit features are enabled -- PML depends on them to work.
7321          */
7322         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7323                 enable_pml = 0;
7324
7325         if (!enable_pml) {
7326                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7327                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7328                 kvm_x86_ops->flush_log_dirty = NULL;
7329                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7330         }
7331
7332         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7333                 u64 vmx_msr;
7334
7335                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7336                 cpu_preemption_timer_multi =
7337                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7338         } else {
7339                 kvm_x86_ops->set_hv_timer = NULL;
7340                 kvm_x86_ops->cancel_hv_timer = NULL;
7341         }
7342
7343         if (!cpu_has_vmx_shadow_vmcs())
7344                 enable_shadow_vmcs = 0;
7345         if (enable_shadow_vmcs)
7346                 init_vmcs_shadow_fields();
7347
7348         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7349         nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv);
7350
7351         kvm_mce_cap_supported |= MCG_LMCE_P;
7352
7353         return alloc_kvm_area();
7354
7355 out:
7356         for (i = 0; i < VMX_BITMAP_NR; i++)
7357                 free_page((unsigned long)vmx_bitmap[i]);
7358
7359     return r;
7360 }
7361
7362 static __exit void hardware_unsetup(void)
7363 {
7364         int i;
7365
7366         for (i = 0; i < VMX_BITMAP_NR; i++)
7367                 free_page((unsigned long)vmx_bitmap[i]);
7368
7369         free_kvm_area();
7370 }
7371
7372 /*
7373  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7374  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7375  */
7376 static int handle_pause(struct kvm_vcpu *vcpu)
7377 {
7378         if (!kvm_pause_in_guest(vcpu->kvm))
7379                 grow_ple_window(vcpu);
7380
7381         /*
7382          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7383          * VM-execution control is ignored if CPL > 0. OTOH, KVM
7384          * never set PAUSE_EXITING and just set PLE if supported,
7385          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7386          */
7387         kvm_vcpu_on_spin(vcpu, true);
7388         return kvm_skip_emulated_instruction(vcpu);
7389 }
7390
7391 static int handle_nop(struct kvm_vcpu *vcpu)
7392 {
7393         return kvm_skip_emulated_instruction(vcpu);
7394 }
7395
7396 static int handle_mwait(struct kvm_vcpu *vcpu)
7397 {
7398         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
7399         return handle_nop(vcpu);
7400 }
7401
7402 static int handle_invalid_op(struct kvm_vcpu *vcpu)
7403 {
7404         kvm_queue_exception(vcpu, UD_VECTOR);
7405         return 1;
7406 }
7407
7408 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
7409 {
7410         return 1;
7411 }
7412
7413 static int handle_monitor(struct kvm_vcpu *vcpu)
7414 {
7415         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
7416         return handle_nop(vcpu);
7417 }
7418
7419 /*
7420  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7421  * set the success or error code of an emulated VMX instruction, as specified
7422  * by Vol 2B, VMX Instruction Reference, "Conventions".
7423  */
7424 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7425 {
7426         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7427                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7428                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7429 }
7430
7431 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7432 {
7433         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7434                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7435                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7436                         | X86_EFLAGS_CF);
7437 }
7438
7439 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7440                                         u32 vm_instruction_error)
7441 {
7442         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7443                 /*
7444                  * failValid writes the error number to the current VMCS, which
7445                  * can't be done there isn't a current VMCS.
7446                  */
7447                 nested_vmx_failInvalid(vcpu);
7448                 return;
7449         }
7450         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7451                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7452                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7453                         | X86_EFLAGS_ZF);
7454         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7455         /*
7456          * We don't need to force a shadow sync because
7457          * VM_INSTRUCTION_ERROR is not shadowed
7458          */
7459 }
7460
7461 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7462 {
7463         /* TODO: not to reset guest simply here. */
7464         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7465         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7466 }
7467
7468 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7469 {
7470         struct vcpu_vmx *vmx =
7471                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7472
7473         vmx->nested.preemption_timer_expired = true;
7474         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7475         kvm_vcpu_kick(&vmx->vcpu);
7476
7477         return HRTIMER_NORESTART;
7478 }
7479
7480 /*
7481  * Decode the memory-address operand of a vmx instruction, as recorded on an
7482  * exit caused by such an instruction (run by a guest hypervisor).
7483  * On success, returns 0. When the operand is invalid, returns 1 and throws
7484  * #UD or #GP.
7485  */
7486 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7487                                  unsigned long exit_qualification,
7488                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
7489 {
7490         gva_t off;
7491         bool exn;
7492         struct kvm_segment s;
7493
7494         /*
7495          * According to Vol. 3B, "Information for VM Exits Due to Instruction
7496          * Execution", on an exit, vmx_instruction_info holds most of the
7497          * addressing components of the operand. Only the displacement part
7498          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7499          * For how an actual address is calculated from all these components,
7500          * refer to Vol. 1, "Operand Addressing".
7501          */
7502         int  scaling = vmx_instruction_info & 3;
7503         int  addr_size = (vmx_instruction_info >> 7) & 7;
7504         bool is_reg = vmx_instruction_info & (1u << 10);
7505         int  seg_reg = (vmx_instruction_info >> 15) & 7;
7506         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
7507         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7508         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
7509         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
7510
7511         if (is_reg) {
7512                 kvm_queue_exception(vcpu, UD_VECTOR);
7513                 return 1;
7514         }
7515
7516         /* Addr = segment_base + offset */
7517         /* offset = base + [index * scale] + displacement */
7518         off = exit_qualification; /* holds the displacement */
7519         if (base_is_valid)
7520                 off += kvm_register_read(vcpu, base_reg);
7521         if (index_is_valid)
7522                 off += kvm_register_read(vcpu, index_reg)<<scaling;
7523         vmx_get_segment(vcpu, &s, seg_reg);
7524         *ret = s.base + off;
7525
7526         if (addr_size == 1) /* 32 bit */
7527                 *ret &= 0xffffffff;
7528
7529         /* Checks for #GP/#SS exceptions. */
7530         exn = false;
7531         if (is_long_mode(vcpu)) {
7532                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7533                  * non-canonical form. This is the only check on the memory
7534                  * destination for long mode!
7535                  */
7536                 exn = is_noncanonical_address(*ret, vcpu);
7537         } else if (is_protmode(vcpu)) {
7538                 /* Protected mode: apply checks for segment validity in the
7539                  * following order:
7540                  * - segment type check (#GP(0) may be thrown)
7541                  * - usability check (#GP(0)/#SS(0))
7542                  * - limit check (#GP(0)/#SS(0))
7543                  */
7544                 if (wr)
7545                         /* #GP(0) if the destination operand is located in a
7546                          * read-only data segment or any code segment.
7547                          */
7548                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
7549                 else
7550                         /* #GP(0) if the source operand is located in an
7551                          * execute-only code segment
7552                          */
7553                         exn = ((s.type & 0xa) == 8);
7554                 if (exn) {
7555                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7556                         return 1;
7557                 }
7558                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7559                  */
7560                 exn = (s.unusable != 0);
7561                 /* Protected mode: #GP(0)/#SS(0) if the memory
7562                  * operand is outside the segment limit.
7563                  */
7564                 exn = exn || (off + sizeof(u64) > s.limit);
7565         }
7566         if (exn) {
7567                 kvm_queue_exception_e(vcpu,
7568                                       seg_reg == VCPU_SREG_SS ?
7569                                                 SS_VECTOR : GP_VECTOR,
7570                                       0);
7571                 return 1;
7572         }
7573
7574         return 0;
7575 }
7576
7577 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7578 {
7579         gva_t gva;
7580         struct x86_exception e;
7581
7582         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7583                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7584                 return 1;
7585
7586         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7587                                 sizeof(*vmpointer), &e)) {
7588                 kvm_inject_page_fault(vcpu, &e);
7589                 return 1;
7590         }
7591
7592         return 0;
7593 }
7594
7595 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7596 {
7597         struct vcpu_vmx *vmx = to_vmx(vcpu);
7598         struct vmcs *shadow_vmcs;
7599         int r;
7600
7601         r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7602         if (r < 0)
7603                 goto out_vmcs02;
7604
7605         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7606         if (!vmx->nested.cached_vmcs12)
7607                 goto out_cached_vmcs12;
7608
7609         if (enable_shadow_vmcs) {
7610                 shadow_vmcs = alloc_vmcs();
7611                 if (!shadow_vmcs)
7612                         goto out_shadow_vmcs;
7613                 /* mark vmcs as shadow */
7614                 shadow_vmcs->revision_id |= (1u << 31);
7615                 /* init shadow vmcs */
7616                 vmcs_clear(shadow_vmcs);
7617                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7618         }
7619
7620         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7621                      HRTIMER_MODE_REL_PINNED);
7622         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7623
7624         vmx->nested.vmxon = true;
7625         return 0;
7626
7627 out_shadow_vmcs:
7628         kfree(vmx->nested.cached_vmcs12);
7629
7630 out_cached_vmcs12:
7631         free_loaded_vmcs(&vmx->nested.vmcs02);
7632
7633 out_vmcs02:
7634         return -ENOMEM;
7635 }
7636
7637 /*
7638  * Emulate the VMXON instruction.
7639  * Currently, we just remember that VMX is active, and do not save or even
7640  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7641  * do not currently need to store anything in that guest-allocated memory
7642  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7643  * argument is different from the VMXON pointer (which the spec says they do).
7644  */
7645 static int handle_vmon(struct kvm_vcpu *vcpu)
7646 {
7647         int ret;
7648         gpa_t vmptr;
7649         struct page *page;
7650         struct vcpu_vmx *vmx = to_vmx(vcpu);
7651         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7652                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7653
7654         /*
7655          * The Intel VMX Instruction Reference lists a bunch of bits that are
7656          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7657          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7658          * Otherwise, we should fail with #UD.  But most faulting conditions
7659          * have already been checked by hardware, prior to the VM-exit for
7660          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7661          * that bit set to 1 in non-root mode.
7662          */
7663         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7664                 kvm_queue_exception(vcpu, UD_VECTOR);
7665                 return 1;
7666         }
7667
7668         if (vmx->nested.vmxon) {
7669                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7670                 return kvm_skip_emulated_instruction(vcpu);
7671         }
7672
7673         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7674                         != VMXON_NEEDED_FEATURES) {
7675                 kvm_inject_gp(vcpu, 0);
7676                 return 1;
7677         }
7678
7679         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7680                 return 1;
7681
7682         /*
7683          * SDM 3: 24.11.5
7684          * The first 4 bytes of VMXON region contain the supported
7685          * VMCS revision identifier
7686          *
7687          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7688          * which replaces physical address width with 32
7689          */
7690         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7691                 nested_vmx_failInvalid(vcpu);
7692                 return kvm_skip_emulated_instruction(vcpu);
7693         }
7694
7695         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7696         if (is_error_page(page)) {
7697                 nested_vmx_failInvalid(vcpu);
7698                 return kvm_skip_emulated_instruction(vcpu);
7699         }
7700         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7701                 kunmap(page);
7702                 kvm_release_page_clean(page);
7703                 nested_vmx_failInvalid(vcpu);
7704                 return kvm_skip_emulated_instruction(vcpu);
7705         }
7706         kunmap(page);
7707         kvm_release_page_clean(page);
7708
7709         vmx->nested.vmxon_ptr = vmptr;
7710         ret = enter_vmx_operation(vcpu);
7711         if (ret)
7712                 return ret;
7713
7714         nested_vmx_succeed(vcpu);
7715         return kvm_skip_emulated_instruction(vcpu);
7716 }
7717
7718 /*
7719  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7720  * for running VMX instructions (except VMXON, whose prerequisites are
7721  * slightly different). It also specifies what exception to inject otherwise.
7722  * Note that many of these exceptions have priority over VM exits, so they
7723  * don't have to be checked again here.
7724  */
7725 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7726 {
7727         if (!to_vmx(vcpu)->nested.vmxon) {
7728                 kvm_queue_exception(vcpu, UD_VECTOR);
7729                 return 0;
7730         }
7731         return 1;
7732 }
7733
7734 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7735 {
7736         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7737         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7738 }
7739
7740 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7741 {
7742         if (vmx->nested.current_vmptr == -1ull)
7743                 return;
7744
7745         if (enable_shadow_vmcs) {
7746                 /* copy to memory all shadowed fields in case
7747                    they were modified */
7748                 copy_shadow_to_vmcs12(vmx);
7749                 vmx->nested.sync_shadow_vmcs = false;
7750                 vmx_disable_shadow_vmcs(vmx);
7751         }
7752         vmx->nested.posted_intr_nv = -1;
7753
7754         /* Flush VMCS12 to guest memory */
7755         kvm_vcpu_write_guest_page(&vmx->vcpu,
7756                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
7757                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7758
7759         vmx->nested.current_vmptr = -1ull;
7760 }
7761
7762 /*
7763  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7764  * just stops using VMX.
7765  */
7766 static void free_nested(struct vcpu_vmx *vmx)
7767 {
7768         if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
7769                 return;
7770
7771         vmx->nested.vmxon = false;
7772         vmx->nested.smm.vmxon = false;
7773         free_vpid(vmx->nested.vpid02);
7774         vmx->nested.posted_intr_nv = -1;
7775         vmx->nested.current_vmptr = -1ull;
7776         if (enable_shadow_vmcs) {
7777                 vmx_disable_shadow_vmcs(vmx);
7778                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7779                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7780                 vmx->vmcs01.shadow_vmcs = NULL;
7781         }
7782         kfree(vmx->nested.cached_vmcs12);
7783         /* Unpin physical memory we referred to in the vmcs02 */
7784         if (vmx->nested.apic_access_page) {
7785                 kvm_release_page_dirty(vmx->nested.apic_access_page);
7786                 vmx->nested.apic_access_page = NULL;
7787         }
7788         if (vmx->nested.virtual_apic_page) {
7789                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
7790                 vmx->nested.virtual_apic_page = NULL;
7791         }
7792         if (vmx->nested.pi_desc_page) {
7793                 kunmap(vmx->nested.pi_desc_page);
7794                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
7795                 vmx->nested.pi_desc_page = NULL;
7796                 vmx->nested.pi_desc = NULL;
7797         }
7798
7799         free_loaded_vmcs(&vmx->nested.vmcs02);
7800 }
7801
7802 /* Emulate the VMXOFF instruction */
7803 static int handle_vmoff(struct kvm_vcpu *vcpu)
7804 {
7805         if (!nested_vmx_check_permission(vcpu))
7806                 return 1;
7807         free_nested(to_vmx(vcpu));
7808         nested_vmx_succeed(vcpu);
7809         return kvm_skip_emulated_instruction(vcpu);
7810 }
7811
7812 /* Emulate the VMCLEAR instruction */
7813 static int handle_vmclear(struct kvm_vcpu *vcpu)
7814 {
7815         struct vcpu_vmx *vmx = to_vmx(vcpu);
7816         u32 zero = 0;
7817         gpa_t vmptr;
7818
7819         if (!nested_vmx_check_permission(vcpu))
7820                 return 1;
7821
7822         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7823                 return 1;
7824
7825         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7826                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7827                 return kvm_skip_emulated_instruction(vcpu);
7828         }
7829
7830         if (vmptr == vmx->nested.vmxon_ptr) {
7831                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7832                 return kvm_skip_emulated_instruction(vcpu);
7833         }
7834
7835         if (vmptr == vmx->nested.current_vmptr)
7836                 nested_release_vmcs12(vmx);
7837
7838         kvm_vcpu_write_guest(vcpu,
7839                         vmptr + offsetof(struct vmcs12, launch_state),
7840                         &zero, sizeof(zero));
7841
7842         nested_vmx_succeed(vcpu);
7843         return kvm_skip_emulated_instruction(vcpu);
7844 }
7845
7846 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7847
7848 /* Emulate the VMLAUNCH instruction */
7849 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7850 {
7851         return nested_vmx_run(vcpu, true);
7852 }
7853
7854 /* Emulate the VMRESUME instruction */
7855 static int handle_vmresume(struct kvm_vcpu *vcpu)
7856 {
7857
7858         return nested_vmx_run(vcpu, false);
7859 }
7860
7861 /*
7862  * Read a vmcs12 field. Since these can have varying lengths and we return
7863  * one type, we chose the biggest type (u64) and zero-extend the return value
7864  * to that size. Note that the caller, handle_vmread, might need to use only
7865  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7866  * 64-bit fields are to be returned).
7867  */
7868 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7869                                   unsigned long field, u64 *ret)
7870 {
7871         short offset = vmcs_field_to_offset(field);
7872         char *p;
7873
7874         if (offset < 0)
7875                 return offset;
7876
7877         p = ((char *)(get_vmcs12(vcpu))) + offset;
7878
7879         switch (vmcs_field_width(field)) {
7880         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
7881                 *ret = *((natural_width *)p);
7882                 return 0;
7883         case VMCS_FIELD_WIDTH_U16:
7884                 *ret = *((u16 *)p);
7885                 return 0;
7886         case VMCS_FIELD_WIDTH_U32:
7887                 *ret = *((u32 *)p);
7888                 return 0;
7889         case VMCS_FIELD_WIDTH_U64:
7890                 *ret = *((u64 *)p);
7891                 return 0;
7892         default:
7893                 WARN_ON(1);
7894                 return -ENOENT;
7895         }
7896 }
7897
7898
7899 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7900                                    unsigned long field, u64 field_value){
7901         short offset = vmcs_field_to_offset(field);
7902         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7903         if (offset < 0)
7904                 return offset;
7905
7906         switch (vmcs_field_width(field)) {
7907         case VMCS_FIELD_WIDTH_U16:
7908                 *(u16 *)p = field_value;
7909                 return 0;
7910         case VMCS_FIELD_WIDTH_U32:
7911                 *(u32 *)p = field_value;
7912                 return 0;
7913         case VMCS_FIELD_WIDTH_U64:
7914                 *(u64 *)p = field_value;
7915                 return 0;
7916         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
7917                 *(natural_width *)p = field_value;
7918                 return 0;
7919         default:
7920                 WARN_ON(1);
7921                 return -ENOENT;
7922         }
7923
7924 }
7925
7926 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7927 {
7928         int i;
7929         unsigned long field;
7930         u64 field_value;
7931         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7932         const u16 *fields = shadow_read_write_fields;
7933         const int num_fields = max_shadow_read_write_fields;
7934
7935         preempt_disable();
7936
7937         vmcs_load(shadow_vmcs);
7938
7939         for (i = 0; i < num_fields; i++) {
7940                 field = fields[i];
7941                 field_value = __vmcs_readl(field);
7942                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7943         }
7944
7945         vmcs_clear(shadow_vmcs);
7946         vmcs_load(vmx->loaded_vmcs->vmcs);
7947
7948         preempt_enable();
7949 }
7950
7951 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7952 {
7953         const u16 *fields[] = {
7954                 shadow_read_write_fields,
7955                 shadow_read_only_fields
7956         };
7957         const int max_fields[] = {
7958                 max_shadow_read_write_fields,
7959                 max_shadow_read_only_fields
7960         };
7961         int i, q;
7962         unsigned long field;
7963         u64 field_value = 0;
7964         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7965
7966         vmcs_load(shadow_vmcs);
7967
7968         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7969                 for (i = 0; i < max_fields[q]; i++) {
7970                         field = fields[q][i];
7971                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7972                         __vmcs_writel(field, field_value);
7973                 }
7974         }
7975
7976         vmcs_clear(shadow_vmcs);
7977         vmcs_load(vmx->loaded_vmcs->vmcs);
7978 }
7979
7980 /*
7981  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7982  * used before) all generate the same failure when it is missing.
7983  */
7984 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7985 {
7986         struct vcpu_vmx *vmx = to_vmx(vcpu);
7987         if (vmx->nested.current_vmptr == -1ull) {
7988                 nested_vmx_failInvalid(vcpu);
7989                 return 0;
7990         }
7991         return 1;
7992 }
7993
7994 static int handle_vmread(struct kvm_vcpu *vcpu)
7995 {
7996         unsigned long field;
7997         u64 field_value;
7998         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7999         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8000         gva_t gva = 0;
8001
8002         if (!nested_vmx_check_permission(vcpu))
8003                 return 1;
8004
8005         if (!nested_vmx_check_vmcs12(vcpu))
8006                 return kvm_skip_emulated_instruction(vcpu);
8007
8008         /* Decode instruction info and find the field to read */
8009         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8010         /* Read the field, zero-extended to a u64 field_value */
8011         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
8012                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8013                 return kvm_skip_emulated_instruction(vcpu);
8014         }
8015         /*
8016          * Now copy part of this value to register or memory, as requested.
8017          * Note that the number of bits actually copied is 32 or 64 depending
8018          * on the guest's mode (32 or 64 bit), not on the given field's length.
8019          */
8020         if (vmx_instruction_info & (1u << 10)) {
8021                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
8022                         field_value);
8023         } else {
8024                 if (get_vmx_mem_address(vcpu, exit_qualification,
8025                                 vmx_instruction_info, true, &gva))
8026                         return 1;
8027                 /* _system ok, as hardware has verified cpl=0 */
8028                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
8029                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
8030         }
8031
8032         nested_vmx_succeed(vcpu);
8033         return kvm_skip_emulated_instruction(vcpu);
8034 }
8035
8036
8037 static int handle_vmwrite(struct kvm_vcpu *vcpu)
8038 {
8039         unsigned long field;
8040         gva_t gva;
8041         struct vcpu_vmx *vmx = to_vmx(vcpu);
8042         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8043         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8044
8045         /* The value to write might be 32 or 64 bits, depending on L1's long
8046          * mode, and eventually we need to write that into a field of several
8047          * possible lengths. The code below first zero-extends the value to 64
8048          * bit (field_value), and then copies only the appropriate number of
8049          * bits into the vmcs12 field.
8050          */
8051         u64 field_value = 0;
8052         struct x86_exception e;
8053
8054         if (!nested_vmx_check_permission(vcpu))
8055                 return 1;
8056
8057         if (!nested_vmx_check_vmcs12(vcpu))
8058                 return kvm_skip_emulated_instruction(vcpu);
8059
8060         if (vmx_instruction_info & (1u << 10))
8061                 field_value = kvm_register_readl(vcpu,
8062                         (((vmx_instruction_info) >> 3) & 0xf));
8063         else {
8064                 if (get_vmx_mem_address(vcpu, exit_qualification,
8065                                 vmx_instruction_info, false, &gva))
8066                         return 1;
8067                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
8068                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
8069                         kvm_inject_page_fault(vcpu, &e);
8070                         return 1;
8071                 }
8072         }
8073
8074
8075         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8076         if (vmcs_field_readonly(field)) {
8077                 nested_vmx_failValid(vcpu,
8078                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
8079                 return kvm_skip_emulated_instruction(vcpu);
8080         }
8081
8082         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
8083                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8084                 return kvm_skip_emulated_instruction(vcpu);
8085         }
8086
8087         switch (field) {
8088 #define SHADOW_FIELD_RW(x) case x:
8089 #include "vmx_shadow_fields.h"
8090                 /*
8091                  * The fields that can be updated by L1 without a vmexit are
8092                  * always updated in the vmcs02, the others go down the slow
8093                  * path of prepare_vmcs02.
8094                  */
8095                 break;
8096         default:
8097                 vmx->nested.dirty_vmcs12 = true;
8098                 break;
8099         }
8100
8101         nested_vmx_succeed(vcpu);
8102         return kvm_skip_emulated_instruction(vcpu);
8103 }
8104
8105 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
8106 {
8107         vmx->nested.current_vmptr = vmptr;
8108         if (enable_shadow_vmcs) {
8109                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
8110                               SECONDARY_EXEC_SHADOW_VMCS);
8111                 vmcs_write64(VMCS_LINK_POINTER,
8112                              __pa(vmx->vmcs01.shadow_vmcs));
8113                 vmx->nested.sync_shadow_vmcs = true;
8114         }
8115         vmx->nested.dirty_vmcs12 = true;
8116 }
8117
8118 /* Emulate the VMPTRLD instruction */
8119 static int handle_vmptrld(struct kvm_vcpu *vcpu)
8120 {
8121         struct vcpu_vmx *vmx = to_vmx(vcpu);
8122         gpa_t vmptr;
8123
8124         if (!nested_vmx_check_permission(vcpu))
8125                 return 1;
8126
8127         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8128                 return 1;
8129
8130         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8131                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
8132                 return kvm_skip_emulated_instruction(vcpu);
8133         }
8134
8135         if (vmptr == vmx->nested.vmxon_ptr) {
8136                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
8137                 return kvm_skip_emulated_instruction(vcpu);
8138         }
8139
8140         if (vmx->nested.current_vmptr != vmptr) {
8141                 struct vmcs12 *new_vmcs12;
8142                 struct page *page;
8143                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8144                 if (is_error_page(page)) {
8145                         nested_vmx_failInvalid(vcpu);
8146                         return kvm_skip_emulated_instruction(vcpu);
8147                 }
8148                 new_vmcs12 = kmap(page);
8149                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
8150                         kunmap(page);
8151                         kvm_release_page_clean(page);
8152                         nested_vmx_failValid(vcpu,
8153                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
8154                         return kvm_skip_emulated_instruction(vcpu);
8155                 }
8156
8157                 nested_release_vmcs12(vmx);
8158                 /*
8159                  * Load VMCS12 from guest memory since it is not already
8160                  * cached.
8161                  */
8162                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
8163                 kunmap(page);
8164                 kvm_release_page_clean(page);
8165
8166                 set_current_vmptr(vmx, vmptr);
8167         }
8168
8169         nested_vmx_succeed(vcpu);
8170         return kvm_skip_emulated_instruction(vcpu);
8171 }
8172
8173 /* Emulate the VMPTRST instruction */
8174 static int handle_vmptrst(struct kvm_vcpu *vcpu)
8175 {
8176         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8177         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8178         gva_t vmcs_gva;
8179         struct x86_exception e;
8180
8181         if (!nested_vmx_check_permission(vcpu))
8182                 return 1;
8183
8184         if (get_vmx_mem_address(vcpu, exit_qualification,
8185                         vmx_instruction_info, true, &vmcs_gva))
8186                 return 1;
8187         /* ok to use *_system, as hardware has verified cpl=0 */
8188         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
8189                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
8190                                  sizeof(u64), &e)) {
8191                 kvm_inject_page_fault(vcpu, &e);
8192                 return 1;
8193         }
8194         nested_vmx_succeed(vcpu);
8195         return kvm_skip_emulated_instruction(vcpu);
8196 }
8197
8198 /* Emulate the INVEPT instruction */
8199 static int handle_invept(struct kvm_vcpu *vcpu)
8200 {
8201         struct vcpu_vmx *vmx = to_vmx(vcpu);
8202         u32 vmx_instruction_info, types;
8203         unsigned long type;
8204         gva_t gva;
8205         struct x86_exception e;
8206         struct {
8207                 u64 eptp, gpa;
8208         } operand;
8209
8210         if (!(vmx->nested.msrs.secondary_ctls_high &
8211               SECONDARY_EXEC_ENABLE_EPT) ||
8212             !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
8213                 kvm_queue_exception(vcpu, UD_VECTOR);
8214                 return 1;
8215         }
8216
8217         if (!nested_vmx_check_permission(vcpu))
8218                 return 1;
8219
8220         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8221         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8222
8223         types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
8224
8225         if (type >= 32 || !(types & (1 << type))) {
8226                 nested_vmx_failValid(vcpu,
8227                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8228                 return kvm_skip_emulated_instruction(vcpu);
8229         }
8230
8231         /* According to the Intel VMX instruction reference, the memory
8232          * operand is read even if it isn't needed (e.g., for type==global)
8233          */
8234         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8235                         vmx_instruction_info, false, &gva))
8236                 return 1;
8237         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
8238                                 sizeof(operand), &e)) {
8239                 kvm_inject_page_fault(vcpu, &e);
8240                 return 1;
8241         }
8242
8243         switch (type) {
8244         case VMX_EPT_EXTENT_GLOBAL:
8245         /*
8246          * TODO: track mappings and invalidate
8247          * single context requests appropriately
8248          */
8249         case VMX_EPT_EXTENT_CONTEXT:
8250                 kvm_mmu_sync_roots(vcpu);
8251                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
8252                 nested_vmx_succeed(vcpu);
8253                 break;
8254         default:
8255                 BUG_ON(1);
8256                 break;
8257         }
8258
8259         return kvm_skip_emulated_instruction(vcpu);
8260 }
8261
8262 static int handle_invvpid(struct kvm_vcpu *vcpu)
8263 {
8264         struct vcpu_vmx *vmx = to_vmx(vcpu);
8265         u32 vmx_instruction_info;
8266         unsigned long type, types;
8267         gva_t gva;
8268         struct x86_exception e;
8269         struct {
8270                 u64 vpid;
8271                 u64 gla;
8272         } operand;
8273
8274         if (!(vmx->nested.msrs.secondary_ctls_high &
8275               SECONDARY_EXEC_ENABLE_VPID) ||
8276                         !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
8277                 kvm_queue_exception(vcpu, UD_VECTOR);
8278                 return 1;
8279         }
8280
8281         if (!nested_vmx_check_permission(vcpu))
8282                 return 1;
8283
8284         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8285         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8286
8287         types = (vmx->nested.msrs.vpid_caps &
8288                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
8289
8290         if (type >= 32 || !(types & (1 << type))) {
8291                 nested_vmx_failValid(vcpu,
8292                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8293                 return kvm_skip_emulated_instruction(vcpu);
8294         }
8295
8296         /* according to the intel vmx instruction reference, the memory
8297          * operand is read even if it isn't needed (e.g., for type==global)
8298          */
8299         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8300                         vmx_instruction_info, false, &gva))
8301                 return 1;
8302         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
8303                                 sizeof(operand), &e)) {
8304                 kvm_inject_page_fault(vcpu, &e);
8305                 return 1;
8306         }
8307         if (operand.vpid >> 16) {
8308                 nested_vmx_failValid(vcpu,
8309                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8310                 return kvm_skip_emulated_instruction(vcpu);
8311         }
8312
8313         switch (type) {
8314         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
8315                 if (is_noncanonical_address(operand.gla, vcpu)) {
8316                         nested_vmx_failValid(vcpu,
8317                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8318                         return kvm_skip_emulated_instruction(vcpu);
8319                 }
8320                 /* fall through */
8321         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
8322         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
8323                 if (!operand.vpid) {
8324                         nested_vmx_failValid(vcpu,
8325                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8326                         return kvm_skip_emulated_instruction(vcpu);
8327                 }
8328                 break;
8329         case VMX_VPID_EXTENT_ALL_CONTEXT:
8330                 break;
8331         default:
8332                 WARN_ON_ONCE(1);
8333                 return kvm_skip_emulated_instruction(vcpu);
8334         }
8335
8336         __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8337         nested_vmx_succeed(vcpu);
8338
8339         return kvm_skip_emulated_instruction(vcpu);
8340 }
8341
8342 static int handle_pml_full(struct kvm_vcpu *vcpu)
8343 {
8344         unsigned long exit_qualification;
8345
8346         trace_kvm_pml_full(vcpu->vcpu_id);
8347
8348         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8349
8350         /*
8351          * PML buffer FULL happened while executing iret from NMI,
8352          * "blocked by NMI" bit has to be set before next VM entry.
8353          */
8354         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
8355                         enable_vnmi &&
8356                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
8357                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8358                                 GUEST_INTR_STATE_NMI);
8359
8360         /*
8361          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8362          * here.., and there's no userspace involvement needed for PML.
8363          */
8364         return 1;
8365 }
8366
8367 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8368 {
8369         kvm_lapic_expired_hv_timer(vcpu);
8370         return 1;
8371 }
8372
8373 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8374 {
8375         struct vcpu_vmx *vmx = to_vmx(vcpu);
8376         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8377
8378         /* Check for memory type validity */
8379         switch (address & VMX_EPTP_MT_MASK) {
8380         case VMX_EPTP_MT_UC:
8381                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))
8382                         return false;
8383                 break;
8384         case VMX_EPTP_MT_WB:
8385                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))
8386                         return false;
8387                 break;
8388         default:
8389                 return false;
8390         }
8391
8392         /* only 4 levels page-walk length are valid */
8393         if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8394                 return false;
8395
8396         /* Reserved bits should not be set */
8397         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8398                 return false;
8399
8400         /* AD, if set, should be supported */
8401         if (address & VMX_EPTP_AD_ENABLE_BIT) {
8402                 if (!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))
8403                         return false;
8404         }
8405
8406         return true;
8407 }
8408
8409 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8410                                      struct vmcs12 *vmcs12)
8411 {
8412         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8413         u64 address;
8414         bool accessed_dirty;
8415         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8416
8417         if (!nested_cpu_has_eptp_switching(vmcs12) ||
8418             !nested_cpu_has_ept(vmcs12))
8419                 return 1;
8420
8421         if (index >= VMFUNC_EPTP_ENTRIES)
8422                 return 1;
8423
8424
8425         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8426                                      &address, index * 8, 8))
8427                 return 1;
8428
8429         accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8430
8431         /*
8432          * If the (L2) guest does a vmfunc to the currently
8433          * active ept pointer, we don't have to do anything else
8434          */
8435         if (vmcs12->ept_pointer != address) {
8436                 if (!valid_ept_address(vcpu, address))
8437                         return 1;
8438
8439                 kvm_mmu_unload(vcpu);
8440                 mmu->ept_ad = accessed_dirty;
8441                 mmu->base_role.ad_disabled = !accessed_dirty;
8442                 vmcs12->ept_pointer = address;
8443                 /*
8444                  * TODO: Check what's the correct approach in case
8445                  * mmu reload fails. Currently, we just let the next
8446                  * reload potentially fail
8447                  */
8448                 kvm_mmu_reload(vcpu);
8449         }
8450
8451         return 0;
8452 }
8453
8454 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8455 {
8456         struct vcpu_vmx *vmx = to_vmx(vcpu);
8457         struct vmcs12 *vmcs12;
8458         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8459
8460         /*
8461          * VMFUNC is only supported for nested guests, but we always enable the
8462          * secondary control for simplicity; for non-nested mode, fake that we
8463          * didn't by injecting #UD.
8464          */
8465         if (!is_guest_mode(vcpu)) {
8466                 kvm_queue_exception(vcpu, UD_VECTOR);
8467                 return 1;
8468         }
8469
8470         vmcs12 = get_vmcs12(vcpu);
8471         if ((vmcs12->vm_function_control & (1 << function)) == 0)
8472                 goto fail;
8473
8474         switch (function) {
8475         case 0:
8476                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8477                         goto fail;
8478                 break;
8479         default:
8480                 goto fail;
8481         }
8482         return kvm_skip_emulated_instruction(vcpu);
8483
8484 fail:
8485         nested_vmx_vmexit(vcpu, vmx->exit_reason,
8486                           vmcs_read32(VM_EXIT_INTR_INFO),
8487                           vmcs_readl(EXIT_QUALIFICATION));
8488         return 1;
8489 }
8490
8491 /*
8492  * The exit handlers return 1 if the exit was handled fully and guest execution
8493  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
8494  * to be done to userspace and return 0.
8495  */
8496 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8497         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
8498         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
8499         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
8500         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
8501         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
8502         [EXIT_REASON_CR_ACCESS]               = handle_cr,
8503         [EXIT_REASON_DR_ACCESS]               = handle_dr,
8504         [EXIT_REASON_CPUID]                   = handle_cpuid,
8505         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
8506         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
8507         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
8508         [EXIT_REASON_HLT]                     = handle_halt,
8509         [EXIT_REASON_INVD]                    = handle_invd,
8510         [EXIT_REASON_INVLPG]                  = handle_invlpg,
8511         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
8512         [EXIT_REASON_VMCALL]                  = handle_vmcall,
8513         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
8514         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
8515         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
8516         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
8517         [EXIT_REASON_VMREAD]                  = handle_vmread,
8518         [EXIT_REASON_VMRESUME]                = handle_vmresume,
8519         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
8520         [EXIT_REASON_VMOFF]                   = handle_vmoff,
8521         [EXIT_REASON_VMON]                    = handle_vmon,
8522         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
8523         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
8524         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
8525         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
8526         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
8527         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
8528         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
8529         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
8530         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
8531         [EXIT_REASON_LDTR_TR]                 = handle_desc,
8532         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
8533         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
8534         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
8535         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
8536         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
8537         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
8538         [EXIT_REASON_INVEPT]                  = handle_invept,
8539         [EXIT_REASON_INVVPID]                 = handle_invvpid,
8540         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
8541         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
8542         [EXIT_REASON_XSAVES]                  = handle_xsaves,
8543         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
8544         [EXIT_REASON_PML_FULL]                = handle_pml_full,
8545         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
8546         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
8547 };
8548
8549 static const int kvm_vmx_max_exit_handlers =
8550         ARRAY_SIZE(kvm_vmx_exit_handlers);
8551
8552 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8553                                        struct vmcs12 *vmcs12)
8554 {
8555         unsigned long exit_qualification;
8556         gpa_t bitmap, last_bitmap;
8557         unsigned int port;
8558         int size;
8559         u8 b;
8560
8561         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8562                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8563
8564         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8565
8566         port = exit_qualification >> 16;
8567         size = (exit_qualification & 7) + 1;
8568
8569         last_bitmap = (gpa_t)-1;
8570         b = -1;
8571
8572         while (size > 0) {
8573                 if (port < 0x8000)
8574                         bitmap = vmcs12->io_bitmap_a;
8575                 else if (port < 0x10000)
8576                         bitmap = vmcs12->io_bitmap_b;
8577                 else
8578                         return true;
8579                 bitmap += (port & 0x7fff) / 8;
8580
8581                 if (last_bitmap != bitmap)
8582                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8583                                 return true;
8584                 if (b & (1 << (port & 7)))
8585                         return true;
8586
8587                 port++;
8588                 size--;
8589                 last_bitmap = bitmap;
8590         }
8591
8592         return false;
8593 }
8594
8595 /*
8596  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8597  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8598  * disinterest in the current event (read or write a specific MSR) by using an
8599  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8600  */
8601 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8602         struct vmcs12 *vmcs12, u32 exit_reason)
8603 {
8604         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8605         gpa_t bitmap;
8606
8607         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8608                 return true;
8609
8610         /*
8611          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8612          * for the four combinations of read/write and low/high MSR numbers.
8613          * First we need to figure out which of the four to use:
8614          */
8615         bitmap = vmcs12->msr_bitmap;
8616         if (exit_reason == EXIT_REASON_MSR_WRITE)
8617                 bitmap += 2048;
8618         if (msr_index >= 0xc0000000) {
8619                 msr_index -= 0xc0000000;
8620                 bitmap += 1024;
8621         }
8622
8623         /* Then read the msr_index'th bit from this bitmap: */
8624         if (msr_index < 1024*8) {
8625                 unsigned char b;
8626                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8627                         return true;
8628                 return 1 & (b >> (msr_index & 7));
8629         } else
8630                 return true; /* let L1 handle the wrong parameter */
8631 }
8632
8633 /*
8634  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8635  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8636  * intercept (via guest_host_mask etc.) the current event.
8637  */
8638 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8639         struct vmcs12 *vmcs12)
8640 {
8641         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8642         int cr = exit_qualification & 15;
8643         int reg;
8644         unsigned long val;
8645
8646         switch ((exit_qualification >> 4) & 3) {
8647         case 0: /* mov to cr */
8648                 reg = (exit_qualification >> 8) & 15;
8649                 val = kvm_register_readl(vcpu, reg);
8650                 switch (cr) {
8651                 case 0:
8652                         if (vmcs12->cr0_guest_host_mask &
8653                             (val ^ vmcs12->cr0_read_shadow))
8654                                 return true;
8655                         break;
8656                 case 3:
8657                         if ((vmcs12->cr3_target_count >= 1 &&
8658                                         vmcs12->cr3_target_value0 == val) ||
8659                                 (vmcs12->cr3_target_count >= 2 &&
8660                                         vmcs12->cr3_target_value1 == val) ||
8661                                 (vmcs12->cr3_target_count >= 3 &&
8662                                         vmcs12->cr3_target_value2 == val) ||
8663                                 (vmcs12->cr3_target_count >= 4 &&
8664                                         vmcs12->cr3_target_value3 == val))
8665                                 return false;
8666                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8667                                 return true;
8668                         break;
8669                 case 4:
8670                         if (vmcs12->cr4_guest_host_mask &
8671                             (vmcs12->cr4_read_shadow ^ val))
8672                                 return true;
8673                         break;
8674                 case 8:
8675                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8676                                 return true;
8677                         break;
8678                 }
8679                 break;
8680         case 2: /* clts */
8681                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8682                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8683                         return true;
8684                 break;
8685         case 1: /* mov from cr */
8686                 switch (cr) {
8687                 case 3:
8688                         if (vmcs12->cpu_based_vm_exec_control &
8689                             CPU_BASED_CR3_STORE_EXITING)
8690                                 return true;
8691                         break;
8692                 case 8:
8693                         if (vmcs12->cpu_based_vm_exec_control &
8694                             CPU_BASED_CR8_STORE_EXITING)
8695                                 return true;
8696                         break;
8697                 }
8698                 break;
8699         case 3: /* lmsw */
8700                 /*
8701                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8702                  * cr0. Other attempted changes are ignored, with no exit.
8703                  */
8704                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8705                 if (vmcs12->cr0_guest_host_mask & 0xe &
8706                     (val ^ vmcs12->cr0_read_shadow))
8707                         return true;
8708                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8709                     !(vmcs12->cr0_read_shadow & 0x1) &&
8710                     (val & 0x1))
8711                         return true;
8712                 break;
8713         }
8714         return false;
8715 }
8716
8717 /*
8718  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8719  * should handle it ourselves in L0 (and then continue L2). Only call this
8720  * when in is_guest_mode (L2).
8721  */
8722 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8723 {
8724         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8725         struct vcpu_vmx *vmx = to_vmx(vcpu);
8726         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8727
8728         if (vmx->nested.nested_run_pending)
8729                 return false;
8730
8731         if (unlikely(vmx->fail)) {
8732                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8733                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8734                 return true;
8735         }
8736
8737         /*
8738          * The host physical addresses of some pages of guest memory
8739          * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
8740          * Page). The CPU may write to these pages via their host
8741          * physical address while L2 is running, bypassing any
8742          * address-translation-based dirty tracking (e.g. EPT write
8743          * protection).
8744          *
8745          * Mark them dirty on every exit from L2 to prevent them from
8746          * getting out of sync with dirty tracking.
8747          */
8748         nested_mark_vmcs12_pages_dirty(vcpu);
8749
8750         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8751                                 vmcs_readl(EXIT_QUALIFICATION),
8752                                 vmx->idt_vectoring_info,
8753                                 intr_info,
8754                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8755                                 KVM_ISA_VMX);
8756
8757         switch (exit_reason) {
8758         case EXIT_REASON_EXCEPTION_NMI:
8759                 if (is_nmi(intr_info))
8760                         return false;
8761                 else if (is_page_fault(intr_info))
8762                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8763                 else if (is_no_device(intr_info) &&
8764                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8765                         return false;
8766                 else if (is_debug(intr_info) &&
8767                          vcpu->guest_debug &
8768                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8769                         return false;
8770                 else if (is_breakpoint(intr_info) &&
8771                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8772                         return false;
8773                 return vmcs12->exception_bitmap &
8774                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8775         case EXIT_REASON_EXTERNAL_INTERRUPT:
8776                 return false;
8777         case EXIT_REASON_TRIPLE_FAULT:
8778                 return true;
8779         case EXIT_REASON_PENDING_INTERRUPT:
8780                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8781         case EXIT_REASON_NMI_WINDOW:
8782                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8783         case EXIT_REASON_TASK_SWITCH:
8784                 return true;
8785         case EXIT_REASON_CPUID:
8786                 return true;
8787         case EXIT_REASON_HLT:
8788                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8789         case EXIT_REASON_INVD:
8790                 return true;
8791         case EXIT_REASON_INVLPG:
8792                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8793         case EXIT_REASON_RDPMC:
8794                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8795         case EXIT_REASON_RDRAND:
8796                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
8797         case EXIT_REASON_RDSEED:
8798                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
8799         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8800                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8801         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8802         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8803         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8804         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8805         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8806         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8807                 /*
8808                  * VMX instructions trap unconditionally. This allows L1 to
8809                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8810                  */
8811                 return true;
8812         case EXIT_REASON_CR_ACCESS:
8813                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8814         case EXIT_REASON_DR_ACCESS:
8815                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8816         case EXIT_REASON_IO_INSTRUCTION:
8817                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8818         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8819                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8820         case EXIT_REASON_MSR_READ:
8821         case EXIT_REASON_MSR_WRITE:
8822                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8823         case EXIT_REASON_INVALID_STATE:
8824                 return true;
8825         case EXIT_REASON_MWAIT_INSTRUCTION:
8826                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8827         case EXIT_REASON_MONITOR_TRAP_FLAG:
8828                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8829         case EXIT_REASON_MONITOR_INSTRUCTION:
8830                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8831         case EXIT_REASON_PAUSE_INSTRUCTION:
8832                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8833                         nested_cpu_has2(vmcs12,
8834                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8835         case EXIT_REASON_MCE_DURING_VMENTRY:
8836                 return false;
8837         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8838                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8839         case EXIT_REASON_APIC_ACCESS:
8840                 return nested_cpu_has2(vmcs12,
8841                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8842         case EXIT_REASON_APIC_WRITE:
8843         case EXIT_REASON_EOI_INDUCED:
8844                 /* apic_write and eoi_induced should exit unconditionally. */
8845                 return true;
8846         case EXIT_REASON_EPT_VIOLATION:
8847                 /*
8848                  * L0 always deals with the EPT violation. If nested EPT is
8849                  * used, and the nested mmu code discovers that the address is
8850                  * missing in the guest EPT table (EPT12), the EPT violation
8851                  * will be injected with nested_ept_inject_page_fault()
8852                  */
8853                 return false;
8854         case EXIT_REASON_EPT_MISCONFIG:
8855                 /*
8856                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8857                  * table (shadow on EPT) or a merged EPT table that L0 built
8858                  * (EPT on EPT). So any problems with the structure of the
8859                  * table is L0's fault.
8860                  */
8861                 return false;
8862         case EXIT_REASON_INVPCID:
8863                 return
8864                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
8865                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8866         case EXIT_REASON_WBINVD:
8867                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8868         case EXIT_REASON_XSETBV:
8869                 return true;
8870         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8871                 /*
8872                  * This should never happen, since it is not possible to
8873                  * set XSS to a non-zero value---neither in L1 nor in L2.
8874                  * If if it were, XSS would have to be checked against
8875                  * the XSS exit bitmap in vmcs12.
8876                  */
8877                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8878         case EXIT_REASON_PREEMPTION_TIMER:
8879                 return false;
8880         case EXIT_REASON_PML_FULL:
8881                 /* We emulate PML support to L1. */
8882                 return false;
8883         case EXIT_REASON_VMFUNC:
8884                 /* VM functions are emulated through L2->L0 vmexits. */
8885                 return false;
8886         default:
8887                 return true;
8888         }
8889 }
8890
8891 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8892 {
8893         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8894
8895         /*
8896          * At this point, the exit interruption info in exit_intr_info
8897          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
8898          * we need to query the in-kernel LAPIC.
8899          */
8900         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8901         if ((exit_intr_info &
8902              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8903             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8904                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8905                 vmcs12->vm_exit_intr_error_code =
8906                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8907         }
8908
8909         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8910                           vmcs_readl(EXIT_QUALIFICATION));
8911         return 1;
8912 }
8913
8914 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8915 {
8916         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8917         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8918 }
8919
8920 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8921 {
8922         if (vmx->pml_pg) {
8923                 __free_page(vmx->pml_pg);
8924                 vmx->pml_pg = NULL;
8925         }
8926 }
8927
8928 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8929 {
8930         struct vcpu_vmx *vmx = to_vmx(vcpu);
8931         u64 *pml_buf;
8932         u16 pml_idx;
8933
8934         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8935
8936         /* Do nothing if PML buffer is empty */
8937         if (pml_idx == (PML_ENTITY_NUM - 1))
8938                 return;
8939
8940         /* PML index always points to next available PML buffer entity */
8941         if (pml_idx >= PML_ENTITY_NUM)
8942                 pml_idx = 0;
8943         else
8944                 pml_idx++;
8945
8946         pml_buf = page_address(vmx->pml_pg);
8947         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8948                 u64 gpa;
8949
8950                 gpa = pml_buf[pml_idx];
8951                 WARN_ON(gpa & (PAGE_SIZE - 1));
8952                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8953         }
8954
8955         /* reset PML index */
8956         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8957 }
8958
8959 /*
8960  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8961  * Called before reporting dirty_bitmap to userspace.
8962  */
8963 static void kvm_flush_pml_buffers(struct kvm *kvm)
8964 {
8965         int i;
8966         struct kvm_vcpu *vcpu;
8967         /*
8968          * We only need to kick vcpu out of guest mode here, as PML buffer
8969          * is flushed at beginning of all VMEXITs, and it's obvious that only
8970          * vcpus running in guest are possible to have unflushed GPAs in PML
8971          * buffer.
8972          */
8973         kvm_for_each_vcpu(i, vcpu, kvm)
8974                 kvm_vcpu_kick(vcpu);
8975 }
8976
8977 static void vmx_dump_sel(char *name, uint32_t sel)
8978 {
8979         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8980                name, vmcs_read16(sel),
8981                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8982                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8983                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8984 }
8985
8986 static void vmx_dump_dtsel(char *name, uint32_t limit)
8987 {
8988         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8989                name, vmcs_read32(limit),
8990                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8991 }
8992
8993 static void dump_vmcs(void)
8994 {
8995         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8996         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8997         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8998         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8999         u32 secondary_exec_control = 0;
9000         unsigned long cr4 = vmcs_readl(GUEST_CR4);
9001         u64 efer = vmcs_read64(GUEST_IA32_EFER);
9002         int i, n;
9003
9004         if (cpu_has_secondary_exec_ctrls())
9005                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9006
9007         pr_err("*** Guest State ***\n");
9008         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9009                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
9010                vmcs_readl(CR0_GUEST_HOST_MASK));
9011         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9012                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
9013         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
9014         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
9015             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
9016         {
9017                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
9018                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
9019                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
9020                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
9021         }
9022         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
9023                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
9024         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
9025                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
9026         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9027                vmcs_readl(GUEST_SYSENTER_ESP),
9028                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
9029         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
9030         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
9031         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
9032         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
9033         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
9034         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
9035         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
9036         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
9037         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
9038         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
9039         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
9040             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
9041                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
9042                        efer, vmcs_read64(GUEST_IA32_PAT));
9043         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
9044                vmcs_read64(GUEST_IA32_DEBUGCTL),
9045                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
9046         if (cpu_has_load_perf_global_ctrl &&
9047             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
9048                 pr_err("PerfGlobCtl = 0x%016llx\n",
9049                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
9050         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
9051                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
9052         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
9053                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
9054                vmcs_read32(GUEST_ACTIVITY_STATE));
9055         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
9056                 pr_err("InterruptStatus = %04x\n",
9057                        vmcs_read16(GUEST_INTR_STATUS));
9058
9059         pr_err("*** Host State ***\n");
9060         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
9061                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
9062         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9063                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
9064                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
9065                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
9066                vmcs_read16(HOST_TR_SELECTOR));
9067         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9068                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
9069                vmcs_readl(HOST_TR_BASE));
9070         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9071                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
9072         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9073                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
9074                vmcs_readl(HOST_CR4));
9075         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9076                vmcs_readl(HOST_IA32_SYSENTER_ESP),
9077                vmcs_read32(HOST_IA32_SYSENTER_CS),
9078                vmcs_readl(HOST_IA32_SYSENTER_EIP));
9079         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
9080                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
9081                        vmcs_read64(HOST_IA32_EFER),
9082                        vmcs_read64(HOST_IA32_PAT));
9083         if (cpu_has_load_perf_global_ctrl &&
9084             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9085                 pr_err("PerfGlobCtl = 0x%016llx\n",
9086                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
9087
9088         pr_err("*** Control State ***\n");
9089         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
9090                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
9091         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
9092         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
9093                vmcs_read32(EXCEPTION_BITMAP),
9094                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
9095                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
9096         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
9097                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9098                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
9099                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
9100         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
9101                vmcs_read32(VM_EXIT_INTR_INFO),
9102                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9103                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
9104         pr_err("        reason=%08x qualification=%016lx\n",
9105                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
9106         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
9107                vmcs_read32(IDT_VECTORING_INFO_FIELD),
9108                vmcs_read32(IDT_VECTORING_ERROR_CODE));
9109         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
9110         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
9111                 pr_err("TSC Multiplier = 0x%016llx\n",
9112                        vmcs_read64(TSC_MULTIPLIER));
9113         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
9114                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9115         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
9116                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
9117         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
9118                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
9119         n = vmcs_read32(CR3_TARGET_COUNT);
9120         for (i = 0; i + 1 < n; i += 4)
9121                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
9122                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
9123                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
9124         if (i < n)
9125                 pr_err("CR3 target%u=%016lx\n",
9126                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
9127         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
9128                 pr_err("PLE Gap=%08x Window=%08x\n",
9129                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
9130         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
9131                 pr_err("Virtual processor ID = 0x%04x\n",
9132                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
9133 }
9134
9135 /*
9136  * The guest has exited.  See if we can fix it or if we need userspace
9137  * assistance.
9138  */
9139 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
9140 {
9141         struct vcpu_vmx *vmx = to_vmx(vcpu);
9142         u32 exit_reason = vmx->exit_reason;
9143         u32 vectoring_info = vmx->idt_vectoring_info;
9144
9145         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
9146
9147         /*
9148          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
9149          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
9150          * querying dirty_bitmap, we only need to kick all vcpus out of guest
9151          * mode as if vcpus is in root mode, the PML buffer must has been
9152          * flushed already.
9153          */
9154         if (enable_pml)
9155                 vmx_flush_pml_buffer(vcpu);
9156
9157         /* If guest state is invalid, start emulating */
9158         if (vmx->emulation_required)
9159                 return handle_invalid_guest_state(vcpu);
9160
9161         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
9162                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9163
9164         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
9165                 dump_vmcs();
9166                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9167                 vcpu->run->fail_entry.hardware_entry_failure_reason
9168                         = exit_reason;
9169                 return 0;
9170         }
9171
9172         if (unlikely(vmx->fail)) {
9173                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9174                 vcpu->run->fail_entry.hardware_entry_failure_reason
9175                         = vmcs_read32(VM_INSTRUCTION_ERROR);
9176                 return 0;
9177         }
9178
9179         /*
9180          * Note:
9181          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
9182          * delivery event since it indicates guest is accessing MMIO.
9183          * The vm-exit can be triggered again after return to guest that
9184          * will cause infinite loop.
9185          */
9186         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
9187                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
9188                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
9189                         exit_reason != EXIT_REASON_PML_FULL &&
9190                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
9191                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9192                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
9193                 vcpu->run->internal.ndata = 3;
9194                 vcpu->run->internal.data[0] = vectoring_info;
9195                 vcpu->run->internal.data[1] = exit_reason;
9196                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
9197                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
9198                         vcpu->run->internal.ndata++;
9199                         vcpu->run->internal.data[3] =
9200                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9201                 }
9202                 return 0;
9203         }
9204
9205         if (unlikely(!enable_vnmi &&
9206                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
9207                 if (vmx_interrupt_allowed(vcpu)) {
9208                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9209                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
9210                            vcpu->arch.nmi_pending) {
9211                         /*
9212                          * This CPU don't support us in finding the end of an
9213                          * NMI-blocked window if the guest runs with IRQs
9214                          * disabled. So we pull the trigger after 1 s of
9215                          * futile waiting, but inform the user about this.
9216                          */
9217                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
9218                                "state on VCPU %d after 1 s timeout\n",
9219                                __func__, vcpu->vcpu_id);
9220                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9221                 }
9222         }
9223
9224         if (exit_reason < kvm_vmx_max_exit_handlers
9225             && kvm_vmx_exit_handlers[exit_reason])
9226                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
9227         else {
9228                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
9229                                 exit_reason);
9230                 kvm_queue_exception(vcpu, UD_VECTOR);
9231                 return 1;
9232         }
9233 }
9234
9235 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
9236 {
9237         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9238
9239         if (is_guest_mode(vcpu) &&
9240                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9241                 return;
9242
9243         if (irr == -1 || tpr < irr) {
9244                 vmcs_write32(TPR_THRESHOLD, 0);
9245                 return;
9246         }
9247
9248         vmcs_write32(TPR_THRESHOLD, irr);
9249 }
9250
9251 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
9252 {
9253         u32 sec_exec_control;
9254
9255         /* Postpone execution until vmcs01 is the current VMCS. */
9256         if (is_guest_mode(vcpu)) {
9257                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
9258                 return;
9259         }
9260
9261         if (!cpu_has_vmx_virtualize_x2apic_mode())
9262                 return;
9263
9264         if (!cpu_need_tpr_shadow(vcpu))
9265                 return;
9266
9267         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9268
9269         if (set) {
9270                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9271                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9272         } else {
9273                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9274                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9275                 vmx_flush_tlb(vcpu, true);
9276         }
9277         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
9278
9279         vmx_update_msr_bitmap(vcpu);
9280 }
9281
9282 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
9283 {
9284         struct vcpu_vmx *vmx = to_vmx(vcpu);
9285
9286         /*
9287          * Currently we do not handle the nested case where L2 has an
9288          * APIC access page of its own; that page is still pinned.
9289          * Hence, we skip the case where the VCPU is in guest mode _and_
9290          * L1 prepared an APIC access page for L2.
9291          *
9292          * For the case where L1 and L2 share the same APIC access page
9293          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
9294          * in the vmcs12), this function will only update either the vmcs01
9295          * or the vmcs02.  If the former, the vmcs02 will be updated by
9296          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
9297          * the next L2->L1 exit.
9298          */
9299         if (!is_guest_mode(vcpu) ||
9300             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
9301                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9302                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9303                 vmx_flush_tlb(vcpu, true);
9304         }
9305 }
9306
9307 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
9308 {
9309         u16 status;
9310         u8 old;
9311
9312         if (max_isr == -1)
9313                 max_isr = 0;
9314
9315         status = vmcs_read16(GUEST_INTR_STATUS);
9316         old = status >> 8;
9317         if (max_isr != old) {
9318                 status &= 0xff;
9319                 status |= max_isr << 8;
9320                 vmcs_write16(GUEST_INTR_STATUS, status);
9321         }
9322 }
9323
9324 static void vmx_set_rvi(int vector)
9325 {
9326         u16 status;
9327         u8 old;
9328
9329         if (vector == -1)
9330                 vector = 0;
9331
9332         status = vmcs_read16(GUEST_INTR_STATUS);
9333         old = (u8)status & 0xff;
9334         if ((u8)vector != old) {
9335                 status &= ~0xff;
9336                 status |= (u8)vector;
9337                 vmcs_write16(GUEST_INTR_STATUS, status);
9338         }
9339 }
9340
9341 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
9342 {
9343         /*
9344          * When running L2, updating RVI is only relevant when
9345          * vmcs12 virtual-interrupt-delivery enabled.
9346          * However, it can be enabled only when L1 also
9347          * intercepts external-interrupts and in that case
9348          * we should not update vmcs02 RVI but instead intercept
9349          * interrupt. Therefore, do nothing when running L2.
9350          */
9351         if (!is_guest_mode(vcpu))
9352                 vmx_set_rvi(max_irr);
9353 }
9354
9355 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
9356 {
9357         struct vcpu_vmx *vmx = to_vmx(vcpu);
9358         int max_irr;
9359         bool max_irr_updated;
9360
9361         WARN_ON(!vcpu->arch.apicv_active);
9362         if (pi_test_on(&vmx->pi_desc)) {
9363                 pi_clear_on(&vmx->pi_desc);
9364                 /*
9365                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9366                  * But on x86 this is just a compiler barrier anyway.
9367                  */
9368                 smp_mb__after_atomic();
9369                 max_irr_updated =
9370                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
9371
9372                 /*
9373                  * If we are running L2 and L1 has a new pending interrupt
9374                  * which can be injected, we should re-evaluate
9375                  * what should be done with this new L1 interrupt.
9376                  * If L1 intercepts external-interrupts, we should
9377                  * exit from L2 to L1. Otherwise, interrupt should be
9378                  * delivered directly to L2.
9379                  */
9380                 if (is_guest_mode(vcpu) && max_irr_updated) {
9381                         if (nested_exit_on_intr(vcpu))
9382                                 kvm_vcpu_exiting_guest_mode(vcpu);
9383                         else
9384                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9385                 }
9386         } else {
9387                 max_irr = kvm_lapic_find_highest_irr(vcpu);
9388         }
9389         vmx_hwapic_irr_update(vcpu, max_irr);
9390         return max_irr;
9391 }
9392
9393 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
9394 {
9395         if (!kvm_vcpu_apicv_active(vcpu))
9396                 return;
9397
9398         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9399         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9400         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9401         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9402 }
9403
9404 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9405 {
9406         struct vcpu_vmx *vmx = to_vmx(vcpu);
9407
9408         pi_clear_on(&vmx->pi_desc);
9409         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9410 }
9411
9412 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9413 {
9414         u32 exit_intr_info = 0;
9415         u16 basic_exit_reason = (u16)vmx->exit_reason;
9416
9417         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9418               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9419                 return;
9420
9421         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9422                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9423         vmx->exit_intr_info = exit_intr_info;
9424
9425         /* if exit due to PF check for async PF */
9426         if (is_page_fault(exit_intr_info))
9427                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9428
9429         /* Handle machine checks before interrupts are enabled */
9430         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9431             is_machine_check(exit_intr_info))
9432                 kvm_machine_check();
9433
9434         /* We need to handle NMIs before interrupts are enabled */
9435         if (is_nmi(exit_intr_info)) {
9436                 kvm_before_interrupt(&vmx->vcpu);
9437                 asm("int $2");
9438                 kvm_after_interrupt(&vmx->vcpu);
9439         }
9440 }
9441
9442 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9443 {
9444         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9445
9446         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9447                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9448                 unsigned int vector;
9449                 unsigned long entry;
9450                 gate_desc *desc;
9451                 struct vcpu_vmx *vmx = to_vmx(vcpu);
9452 #ifdef CONFIG_X86_64
9453                 unsigned long tmp;
9454 #endif
9455
9456                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
9457                 desc = (gate_desc *)vmx->host_idt_base + vector;
9458                 entry = gate_offset(desc);
9459                 asm volatile(
9460 #ifdef CONFIG_X86_64
9461                         "mov %%" _ASM_SP ", %[sp]\n\t"
9462                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9463                         "push $%c[ss]\n\t"
9464                         "push %[sp]\n\t"
9465 #endif
9466                         "pushf\n\t"
9467                         __ASM_SIZE(push) " $%c[cs]\n\t"
9468                         CALL_NOSPEC
9469                         :
9470 #ifdef CONFIG_X86_64
9471                         [sp]"=&r"(tmp),
9472 #endif
9473                         ASM_CALL_CONSTRAINT
9474                         :
9475                         THUNK_TARGET(entry),
9476                         [ss]"i"(__KERNEL_DS),
9477                         [cs]"i"(__KERNEL_CS)
9478                         );
9479         }
9480 }
9481 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9482
9483 static bool vmx_has_high_real_mode_segbase(void)
9484 {
9485         return enable_unrestricted_guest || emulate_invalid_guest_state;
9486 }
9487
9488 static bool vmx_mpx_supported(void)
9489 {
9490         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9491                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9492 }
9493
9494 static bool vmx_xsaves_supported(void)
9495 {
9496         return vmcs_config.cpu_based_2nd_exec_ctrl &
9497                 SECONDARY_EXEC_XSAVES;
9498 }
9499
9500 static bool vmx_umip_emulated(void)
9501 {
9502         return vmcs_config.cpu_based_2nd_exec_ctrl &
9503                 SECONDARY_EXEC_DESC;
9504 }
9505
9506 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9507 {
9508         u32 exit_intr_info;
9509         bool unblock_nmi;
9510         u8 vector;
9511         bool idtv_info_valid;
9512
9513         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9514
9515         if (enable_vnmi) {
9516                 if (vmx->loaded_vmcs->nmi_known_unmasked)
9517                         return;
9518                 /*
9519                  * Can't use vmx->exit_intr_info since we're not sure what
9520                  * the exit reason is.
9521                  */
9522                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9523                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9524                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9525                 /*
9526                  * SDM 3: 27.7.1.2 (September 2008)
9527                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
9528                  * a guest IRET fault.
9529                  * SDM 3: 23.2.2 (September 2008)
9530                  * Bit 12 is undefined in any of the following cases:
9531                  *  If the VM exit sets the valid bit in the IDT-vectoring
9532                  *   information field.
9533                  *  If the VM exit is due to a double fault.
9534                  */
9535                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9536                     vector != DF_VECTOR && !idtv_info_valid)
9537                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9538                                       GUEST_INTR_STATE_NMI);
9539                 else
9540                         vmx->loaded_vmcs->nmi_known_unmasked =
9541                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9542                                   & GUEST_INTR_STATE_NMI);
9543         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
9544                 vmx->loaded_vmcs->vnmi_blocked_time +=
9545                         ktime_to_ns(ktime_sub(ktime_get(),
9546                                               vmx->loaded_vmcs->entry_time));
9547 }
9548
9549 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9550                                       u32 idt_vectoring_info,
9551                                       int instr_len_field,
9552                                       int error_code_field)
9553 {
9554         u8 vector;
9555         int type;
9556         bool idtv_info_valid;
9557
9558         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9559
9560         vcpu->arch.nmi_injected = false;
9561         kvm_clear_exception_queue(vcpu);
9562         kvm_clear_interrupt_queue(vcpu);
9563
9564         if (!idtv_info_valid)
9565                 return;
9566
9567         kvm_make_request(KVM_REQ_EVENT, vcpu);
9568
9569         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9570         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9571
9572         switch (type) {
9573         case INTR_TYPE_NMI_INTR:
9574                 vcpu->arch.nmi_injected = true;
9575                 /*
9576                  * SDM 3: 27.7.1.2 (September 2008)
9577                  * Clear bit "block by NMI" before VM entry if a NMI
9578                  * delivery faulted.
9579                  */
9580                 vmx_set_nmi_mask(vcpu, false);
9581                 break;
9582         case INTR_TYPE_SOFT_EXCEPTION:
9583                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9584                 /* fall through */
9585         case INTR_TYPE_HARD_EXCEPTION:
9586                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9587                         u32 err = vmcs_read32(error_code_field);
9588                         kvm_requeue_exception_e(vcpu, vector, err);
9589                 } else
9590                         kvm_requeue_exception(vcpu, vector);
9591                 break;
9592         case INTR_TYPE_SOFT_INTR:
9593                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9594                 /* fall through */
9595         case INTR_TYPE_EXT_INTR:
9596                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9597                 break;
9598         default:
9599                 break;
9600         }
9601 }
9602
9603 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9604 {
9605         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9606                                   VM_EXIT_INSTRUCTION_LEN,
9607                                   IDT_VECTORING_ERROR_CODE);
9608 }
9609
9610 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9611 {
9612         __vmx_complete_interrupts(vcpu,
9613                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9614                                   VM_ENTRY_INSTRUCTION_LEN,
9615                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
9616
9617         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9618 }
9619
9620 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9621 {
9622         int i, nr_msrs;
9623         struct perf_guest_switch_msr *msrs;
9624
9625         msrs = perf_guest_get_msrs(&nr_msrs);
9626
9627         if (!msrs)
9628                 return;
9629
9630         for (i = 0; i < nr_msrs; i++)
9631                 if (msrs[i].host == msrs[i].guest)
9632                         clear_atomic_switch_msr(vmx, msrs[i].msr);
9633                 else
9634                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9635                                         msrs[i].host);
9636 }
9637
9638 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9639 {
9640         struct vcpu_vmx *vmx = to_vmx(vcpu);
9641         u64 tscl;
9642         u32 delta_tsc;
9643
9644         if (vmx->hv_deadline_tsc == -1)
9645                 return;
9646
9647         tscl = rdtsc();
9648         if (vmx->hv_deadline_tsc > tscl)
9649                 /* sure to be 32 bit only because checked on set_hv_timer */
9650                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9651                         cpu_preemption_timer_multi);
9652         else
9653                 delta_tsc = 0;
9654
9655         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9656 }
9657
9658 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9659 {
9660         struct vcpu_vmx *vmx = to_vmx(vcpu);
9661         unsigned long cr3, cr4, evmcs_rsp;
9662
9663         /* Record the guest's net vcpu time for enforced NMI injections. */
9664         if (unlikely(!enable_vnmi &&
9665                      vmx->loaded_vmcs->soft_vnmi_blocked))
9666                 vmx->loaded_vmcs->entry_time = ktime_get();
9667
9668         /* Don't enter VMX if guest state is invalid, let the exit handler
9669            start emulation until we arrive back to a valid state */
9670         if (vmx->emulation_required)
9671                 return;
9672
9673         if (vmx->ple_window_dirty) {
9674                 vmx->ple_window_dirty = false;
9675                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9676         }
9677
9678         if (vmx->nested.sync_shadow_vmcs) {
9679                 copy_vmcs12_to_shadow(vmx);
9680                 vmx->nested.sync_shadow_vmcs = false;
9681         }
9682
9683         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9684                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9685         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9686                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9687
9688         cr3 = __get_current_cr3_fast();
9689         if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9690                 vmcs_writel(HOST_CR3, cr3);
9691                 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9692         }
9693
9694         cr4 = cr4_read_shadow();
9695         if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9696                 vmcs_writel(HOST_CR4, cr4);
9697                 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9698         }
9699
9700         /* When single-stepping over STI and MOV SS, we must clear the
9701          * corresponding interruptibility bits in the guest state. Otherwise
9702          * vmentry fails as it then expects bit 14 (BS) in pending debug
9703          * exceptions being set, but that's not correct for the guest debugging
9704          * case. */
9705         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9706                 vmx_set_interrupt_shadow(vcpu, 0);
9707
9708         if (static_cpu_has(X86_FEATURE_PKU) &&
9709             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9710             vcpu->arch.pkru != vmx->host_pkru)
9711                 __write_pkru(vcpu->arch.pkru);
9712
9713         atomic_switch_perf_msrs(vmx);
9714
9715         vmx_arm_hv_timer(vcpu);
9716
9717         /*
9718          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
9719          * it's non-zero. Since vmentry is serialising on affected CPUs, there
9720          * is no need to worry about the conditional branch over the wrmsr
9721          * being speculatively taken.
9722          */
9723         if (vmx->spec_ctrl)
9724                 native_wrmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl);
9725
9726         vmx->__launched = vmx->loaded_vmcs->launched;
9727
9728         evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
9729                 (unsigned long)&current_evmcs->host_rsp : 0;
9730
9731         asm(
9732                 /* Store host registers */
9733                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9734                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9735                 "push %%" _ASM_CX " \n\t"
9736                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9737                 "je 1f \n\t"
9738                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9739                 /* Avoid VMWRITE when Enlightened VMCS is in use */
9740                 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
9741                 "jz 2f \n\t"
9742                 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
9743                 "jmp 1f \n\t"
9744                 "2: \n\t"
9745                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9746                 "1: \n\t"
9747                 /* Reload cr2 if changed */
9748                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9749                 "mov %%cr2, %%" _ASM_DX " \n\t"
9750                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9751                 "je 3f \n\t"
9752                 "mov %%" _ASM_AX", %%cr2 \n\t"
9753                 "3: \n\t"
9754                 /* Check if vmlaunch of vmresume is needed */
9755                 "cmpl $0, %c[launched](%0) \n\t"
9756                 /* Load guest registers.  Don't clobber flags. */
9757                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9758                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9759                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9760                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9761                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9762                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9763 #ifdef CONFIG_X86_64
9764                 "mov %c[r8](%0),  %%r8  \n\t"
9765                 "mov %c[r9](%0),  %%r9  \n\t"
9766                 "mov %c[r10](%0), %%r10 \n\t"
9767                 "mov %c[r11](%0), %%r11 \n\t"
9768                 "mov %c[r12](%0), %%r12 \n\t"
9769                 "mov %c[r13](%0), %%r13 \n\t"
9770                 "mov %c[r14](%0), %%r14 \n\t"
9771                 "mov %c[r15](%0), %%r15 \n\t"
9772 #endif
9773                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9774
9775                 /* Enter guest mode */
9776                 "jne 1f \n\t"
9777                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9778                 "jmp 2f \n\t"
9779                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9780                 "2: "
9781                 /* Save guest registers, load host registers, keep flags */
9782                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9783                 "pop %0 \n\t"
9784                 "setbe %c[fail](%0)\n\t"
9785                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9786                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9787                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9788                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9789                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9790                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9791                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9792 #ifdef CONFIG_X86_64
9793                 "mov %%r8,  %c[r8](%0) \n\t"
9794                 "mov %%r9,  %c[r9](%0) \n\t"
9795                 "mov %%r10, %c[r10](%0) \n\t"
9796                 "mov %%r11, %c[r11](%0) \n\t"
9797                 "mov %%r12, %c[r12](%0) \n\t"
9798                 "mov %%r13, %c[r13](%0) \n\t"
9799                 "mov %%r14, %c[r14](%0) \n\t"
9800                 "mov %%r15, %c[r15](%0) \n\t"
9801                 "xor %%r8d,  %%r8d \n\t"
9802                 "xor %%r9d,  %%r9d \n\t"
9803                 "xor %%r10d, %%r10d \n\t"
9804                 "xor %%r11d, %%r11d \n\t"
9805                 "xor %%r12d, %%r12d \n\t"
9806                 "xor %%r13d, %%r13d \n\t"
9807                 "xor %%r14d, %%r14d \n\t"
9808                 "xor %%r15d, %%r15d \n\t"
9809 #endif
9810                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9811                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9812
9813                 "xor %%eax, %%eax \n\t"
9814                 "xor %%ebx, %%ebx \n\t"
9815                 "xor %%esi, %%esi \n\t"
9816                 "xor %%edi, %%edi \n\t"
9817                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9818                 ".pushsection .rodata \n\t"
9819                 ".global vmx_return \n\t"
9820                 "vmx_return: " _ASM_PTR " 2b \n\t"
9821                 ".popsection"
9822               : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
9823                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9824                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9825                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9826                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9827                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9828                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9829                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9830                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9831                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9832                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9833 #ifdef CONFIG_X86_64
9834                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9835                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9836                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9837                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9838                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9839                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9840                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9841                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9842 #endif
9843                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9844                 [wordsize]"i"(sizeof(ulong))
9845               : "cc", "memory"
9846 #ifdef CONFIG_X86_64
9847                 , "rax", "rbx", "rdi"
9848                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9849 #else
9850                 , "eax", "ebx", "edi"
9851 #endif
9852               );
9853
9854         /*
9855          * We do not use IBRS in the kernel. If this vCPU has used the
9856          * SPEC_CTRL MSR it may have left it on; save the value and
9857          * turn it off. This is much more efficient than blindly adding
9858          * it to the atomic save/restore list. Especially as the former
9859          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
9860          *
9861          * For non-nested case:
9862          * If the L01 MSR bitmap does not intercept the MSR, then we need to
9863          * save it.
9864          *
9865          * For nested case:
9866          * If the L02 MSR bitmap does not intercept the MSR, then we need to
9867          * save it.
9868          */
9869         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
9870                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
9871
9872         if (vmx->spec_ctrl)
9873                 native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
9874
9875         /* Eliminate branch target predictions from guest mode */
9876         vmexit_fill_RSB();
9877
9878         /* All fields are clean at this point */
9879         if (static_branch_unlikely(&enable_evmcs))
9880                 current_evmcs->hv_clean_fields |=
9881                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
9882
9883         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9884         if (vmx->host_debugctlmsr)
9885                 update_debugctlmsr(vmx->host_debugctlmsr);
9886
9887 #ifndef CONFIG_X86_64
9888         /*
9889          * The sysexit path does not restore ds/es, so we must set them to
9890          * a reasonable value ourselves.
9891          *
9892          * We can't defer this to vmx_load_host_state() since that function
9893          * may be executed in interrupt context, which saves and restore segments
9894          * around it, nullifying its effect.
9895          */
9896         loadsegment(ds, __USER_DS);
9897         loadsegment(es, __USER_DS);
9898 #endif
9899
9900         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9901                                   | (1 << VCPU_EXREG_RFLAGS)
9902                                   | (1 << VCPU_EXREG_PDPTR)
9903                                   | (1 << VCPU_EXREG_SEGMENTS)
9904                                   | (1 << VCPU_EXREG_CR3));
9905         vcpu->arch.regs_dirty = 0;
9906
9907         /*
9908          * eager fpu is enabled if PKEY is supported and CR4 is switched
9909          * back on host, so it is safe to read guest PKRU from current
9910          * XSAVE.
9911          */
9912         if (static_cpu_has(X86_FEATURE_PKU) &&
9913             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
9914                 vcpu->arch.pkru = __read_pkru();
9915                 if (vcpu->arch.pkru != vmx->host_pkru)
9916                         __write_pkru(vmx->host_pkru);
9917         }
9918
9919         vmx->nested.nested_run_pending = 0;
9920         vmx->idt_vectoring_info = 0;
9921
9922         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
9923         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9924                 return;
9925
9926         vmx->loaded_vmcs->launched = 1;
9927         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9928
9929         vmx_complete_atomic_exit(vmx);
9930         vmx_recover_nmi_blocking(vmx);
9931         vmx_complete_interrupts(vmx);
9932 }
9933 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9934
9935 static struct kvm *vmx_vm_alloc(void)
9936 {
9937         struct kvm_vmx *kvm_vmx = kzalloc(sizeof(struct kvm_vmx), GFP_KERNEL);
9938         return &kvm_vmx->kvm;
9939 }
9940
9941 static void vmx_vm_free(struct kvm *kvm)
9942 {
9943         kfree(to_kvm_vmx(kvm));
9944 }
9945
9946 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9947 {
9948         struct vcpu_vmx *vmx = to_vmx(vcpu);
9949         int cpu;
9950
9951         if (vmx->loaded_vmcs == vmcs)
9952                 return;
9953
9954         cpu = get_cpu();
9955         vmx->loaded_vmcs = vmcs;
9956         vmx_vcpu_put(vcpu);
9957         vmx_vcpu_load(vcpu, cpu);
9958         put_cpu();
9959 }
9960
9961 /*
9962  * Ensure that the current vmcs of the logical processor is the
9963  * vmcs01 of the vcpu before calling free_nested().
9964  */
9965 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9966 {
9967        struct vcpu_vmx *vmx = to_vmx(vcpu);
9968
9969        vcpu_load(vcpu);
9970        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9971        free_nested(vmx);
9972        vcpu_put(vcpu);
9973 }
9974
9975 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9976 {
9977         struct vcpu_vmx *vmx = to_vmx(vcpu);
9978
9979         if (enable_pml)
9980                 vmx_destroy_pml_buffer(vmx);
9981         free_vpid(vmx->vpid);
9982         leave_guest_mode(vcpu);
9983         vmx_free_vcpu_nested(vcpu);
9984         free_loaded_vmcs(vmx->loaded_vmcs);
9985         kfree(vmx->guest_msrs);
9986         kvm_vcpu_uninit(vcpu);
9987         kmem_cache_free(kvm_vcpu_cache, vmx);
9988 }
9989
9990 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9991 {
9992         int err;
9993         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9994         unsigned long *msr_bitmap;
9995         int cpu;
9996
9997         if (!vmx)
9998                 return ERR_PTR(-ENOMEM);
9999
10000         vmx->vpid = allocate_vpid();
10001
10002         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
10003         if (err)
10004                 goto free_vcpu;
10005
10006         err = -ENOMEM;
10007
10008         /*
10009          * If PML is turned on, failure on enabling PML just results in failure
10010          * of creating the vcpu, therefore we can simplify PML logic (by
10011          * avoiding dealing with cases, such as enabling PML partially on vcpus
10012          * for the guest, etc.
10013          */
10014         if (enable_pml) {
10015                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
10016                 if (!vmx->pml_pg)
10017                         goto uninit_vcpu;
10018         }
10019
10020         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
10021         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
10022                      > PAGE_SIZE);
10023
10024         if (!vmx->guest_msrs)
10025                 goto free_pml;
10026
10027         err = alloc_loaded_vmcs(&vmx->vmcs01);
10028         if (err < 0)
10029                 goto free_msrs;
10030
10031         msr_bitmap = vmx->vmcs01.msr_bitmap;
10032         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
10033         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
10034         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
10035         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
10036         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
10037         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
10038         vmx->msr_bitmap_mode = 0;
10039
10040         vmx->loaded_vmcs = &vmx->vmcs01;
10041         cpu = get_cpu();
10042         vmx_vcpu_load(&vmx->vcpu, cpu);
10043         vmx->vcpu.cpu = cpu;
10044         vmx_vcpu_setup(vmx);
10045         vmx_vcpu_put(&vmx->vcpu);
10046         put_cpu();
10047         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10048                 err = alloc_apic_access_page(kvm);
10049                 if (err)
10050                         goto free_vmcs;
10051         }
10052
10053         if (enable_ept && !enable_unrestricted_guest) {
10054                 err = init_rmode_identity_map(kvm);
10055                 if (err)
10056                         goto free_vmcs;
10057         }
10058
10059         if (nested) {
10060                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
10061                                            kvm_vcpu_apicv_active(&vmx->vcpu));
10062                 vmx->nested.vpid02 = allocate_vpid();
10063         }
10064
10065         vmx->nested.posted_intr_nv = -1;
10066         vmx->nested.current_vmptr = -1ull;
10067
10068         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
10069
10070         /*
10071          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
10072          * or POSTED_INTR_WAKEUP_VECTOR.
10073          */
10074         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
10075         vmx->pi_desc.sn = 1;
10076
10077         return &vmx->vcpu;
10078
10079 free_vmcs:
10080         free_vpid(vmx->nested.vpid02);
10081         free_loaded_vmcs(vmx->loaded_vmcs);
10082 free_msrs:
10083         kfree(vmx->guest_msrs);
10084 free_pml:
10085         vmx_destroy_pml_buffer(vmx);
10086 uninit_vcpu:
10087         kvm_vcpu_uninit(&vmx->vcpu);
10088 free_vcpu:
10089         free_vpid(vmx->vpid);
10090         kmem_cache_free(kvm_vcpu_cache, vmx);
10091         return ERR_PTR(err);
10092 }
10093
10094 static int vmx_vm_init(struct kvm *kvm)
10095 {
10096         if (!ple_gap)
10097                 kvm->arch.pause_in_guest = true;
10098         return 0;
10099 }
10100
10101 static void __init vmx_check_processor_compat(void *rtn)
10102 {
10103         struct vmcs_config vmcs_conf;
10104
10105         *(int *)rtn = 0;
10106         if (setup_vmcs_config(&vmcs_conf) < 0)
10107                 *(int *)rtn = -EIO;
10108         nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, enable_apicv);
10109         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
10110                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
10111                                 smp_processor_id());
10112                 *(int *)rtn = -EIO;
10113         }
10114 }
10115
10116 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
10117 {
10118         u8 cache;
10119         u64 ipat = 0;
10120
10121         /* For VT-d and EPT combination
10122          * 1. MMIO: always map as UC
10123          * 2. EPT with VT-d:
10124          *   a. VT-d without snooping control feature: can't guarantee the
10125          *      result, try to trust guest.
10126          *   b. VT-d with snooping control feature: snooping control feature of
10127          *      VT-d engine can guarantee the cache correctness. Just set it
10128          *      to WB to keep consistent with host. So the same as item 3.
10129          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
10130          *    consistent with host MTRR
10131          */
10132         if (is_mmio) {
10133                 cache = MTRR_TYPE_UNCACHABLE;
10134                 goto exit;
10135         }
10136
10137         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
10138                 ipat = VMX_EPT_IPAT_BIT;
10139                 cache = MTRR_TYPE_WRBACK;
10140                 goto exit;
10141         }
10142
10143         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
10144                 ipat = VMX_EPT_IPAT_BIT;
10145                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
10146                         cache = MTRR_TYPE_WRBACK;
10147                 else
10148                         cache = MTRR_TYPE_UNCACHABLE;
10149                 goto exit;
10150         }
10151
10152         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
10153
10154 exit:
10155         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
10156 }
10157
10158 static int vmx_get_lpage_level(void)
10159 {
10160         if (enable_ept && !cpu_has_vmx_ept_1g_page())
10161                 return PT_DIRECTORY_LEVEL;
10162         else
10163                 /* For shadow and EPT supported 1GB page */
10164                 return PT_PDPE_LEVEL;
10165 }
10166
10167 static void vmcs_set_secondary_exec_control(u32 new_ctl)
10168 {
10169         /*
10170          * These bits in the secondary execution controls field
10171          * are dynamic, the others are mostly based on the hypervisor
10172          * architecture and the guest's CPUID.  Do not touch the
10173          * dynamic bits.
10174          */
10175         u32 mask =
10176                 SECONDARY_EXEC_SHADOW_VMCS |
10177                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
10178                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10179                 SECONDARY_EXEC_DESC;
10180
10181         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
10182
10183         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
10184                      (new_ctl & ~mask) | (cur_ctl & mask));
10185 }
10186
10187 /*
10188  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
10189  * (indicating "allowed-1") if they are supported in the guest's CPUID.
10190  */
10191 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
10192 {
10193         struct vcpu_vmx *vmx = to_vmx(vcpu);
10194         struct kvm_cpuid_entry2 *entry;
10195
10196         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
10197         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
10198
10199 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
10200         if (entry && (entry->_reg & (_cpuid_mask)))                     \
10201                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
10202 } while (0)
10203
10204         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
10205         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
10206         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
10207         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
10208         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
10209         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
10210         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
10211         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
10212         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
10213         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
10214         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
10215         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
10216         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
10217         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
10218         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
10219
10220         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
10221         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
10222         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
10223         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
10224         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
10225         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
10226
10227 #undef cr4_fixed1_update
10228 }
10229
10230 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
10231 {
10232         struct vcpu_vmx *vmx = to_vmx(vcpu);
10233
10234         if (cpu_has_secondary_exec_ctrls()) {
10235                 vmx_compute_secondary_exec_control(vmx);
10236                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
10237         }
10238
10239         if (nested_vmx_allowed(vcpu))
10240                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
10241                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10242         else
10243                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
10244                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10245
10246         if (nested_vmx_allowed(vcpu))
10247                 nested_vmx_cr_fixed1_bits_update(vcpu);
10248 }
10249
10250 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
10251 {
10252         if (func == 1 && nested)
10253                 entry->ecx |= bit(X86_FEATURE_VMX);
10254 }
10255
10256 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
10257                 struct x86_exception *fault)
10258 {
10259         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10260         struct vcpu_vmx *vmx = to_vmx(vcpu);
10261         u32 exit_reason;
10262         unsigned long exit_qualification = vcpu->arch.exit_qualification;
10263
10264         if (vmx->nested.pml_full) {
10265                 exit_reason = EXIT_REASON_PML_FULL;
10266                 vmx->nested.pml_full = false;
10267                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
10268         } else if (fault->error_code & PFERR_RSVD_MASK)
10269                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
10270         else
10271                 exit_reason = EXIT_REASON_EPT_VIOLATION;
10272
10273         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
10274         vmcs12->guest_physical_address = fault->address;
10275 }
10276
10277 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
10278 {
10279         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
10280 }
10281
10282 /* Callbacks for nested_ept_init_mmu_context: */
10283
10284 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
10285 {
10286         /* return the page table to be shadowed - in our case, EPT12 */
10287         return get_vmcs12(vcpu)->ept_pointer;
10288 }
10289
10290 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
10291 {
10292         WARN_ON(mmu_is_nested(vcpu));
10293         if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
10294                 return 1;
10295
10296         kvm_mmu_unload(vcpu);
10297         kvm_init_shadow_ept_mmu(vcpu,
10298                         to_vmx(vcpu)->nested.msrs.ept_caps &
10299                         VMX_EPT_EXECUTE_ONLY_BIT,
10300                         nested_ept_ad_enabled(vcpu));
10301         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
10302         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
10303         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
10304
10305         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
10306         return 0;
10307 }
10308
10309 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
10310 {
10311         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
10312 }
10313
10314 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
10315                                             u16 error_code)
10316 {
10317         bool inequality, bit;
10318
10319         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
10320         inequality =
10321                 (error_code & vmcs12->page_fault_error_code_mask) !=
10322                  vmcs12->page_fault_error_code_match;
10323         return inequality ^ bit;
10324 }
10325
10326 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
10327                 struct x86_exception *fault)
10328 {
10329         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10330
10331         WARN_ON(!is_guest_mode(vcpu));
10332
10333         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
10334                 !to_vmx(vcpu)->nested.nested_run_pending) {
10335                 vmcs12->vm_exit_intr_error_code = fault->error_code;
10336                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10337                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
10338                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
10339                                   fault->address);
10340         } else {
10341                 kvm_inject_page_fault(vcpu, fault);
10342         }
10343 }
10344
10345 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10346                                                  struct vmcs12 *vmcs12);
10347
10348 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
10349                                         struct vmcs12 *vmcs12)
10350 {
10351         struct vcpu_vmx *vmx = to_vmx(vcpu);
10352         struct page *page;
10353         u64 hpa;
10354
10355         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10356                 /*
10357                  * Translate L1 physical address to host physical
10358                  * address for vmcs02. Keep the page pinned, so this
10359                  * physical address remains valid. We keep a reference
10360                  * to it so we can release it later.
10361                  */
10362                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
10363                         kvm_release_page_dirty(vmx->nested.apic_access_page);
10364                         vmx->nested.apic_access_page = NULL;
10365                 }
10366                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
10367                 /*
10368                  * If translation failed, no matter: This feature asks
10369                  * to exit when accessing the given address, and if it
10370                  * can never be accessed, this feature won't do
10371                  * anything anyway.
10372                  */
10373                 if (!is_error_page(page)) {
10374                         vmx->nested.apic_access_page = page;
10375                         hpa = page_to_phys(vmx->nested.apic_access_page);
10376                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
10377                 } else {
10378                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
10379                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10380                 }
10381         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
10382                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10383                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
10384                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10385                 kvm_vcpu_reload_apic_access_page(vcpu);
10386         }
10387
10388         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
10389                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
10390                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
10391                         vmx->nested.virtual_apic_page = NULL;
10392                 }
10393                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
10394
10395                 /*
10396                  * If translation failed, VM entry will fail because
10397                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10398                  * Failing the vm entry is _not_ what the processor
10399                  * does but it's basically the only possibility we
10400                  * have.  We could still enter the guest if CR8 load
10401                  * exits are enabled, CR8 store exits are enabled, and
10402                  * virtualize APIC access is disabled; in this case
10403                  * the processor would never use the TPR shadow and we
10404                  * could simply clear the bit from the execution
10405                  * control.  But such a configuration is useless, so
10406                  * let's keep the code simple.
10407                  */
10408                 if (!is_error_page(page)) {
10409                         vmx->nested.virtual_apic_page = page;
10410                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
10411                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
10412                 }
10413         }
10414
10415         if (nested_cpu_has_posted_intr(vmcs12)) {
10416                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
10417                         kunmap(vmx->nested.pi_desc_page);
10418                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
10419                         vmx->nested.pi_desc_page = NULL;
10420                 }
10421                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
10422                 if (is_error_page(page))
10423                         return;
10424                 vmx->nested.pi_desc_page = page;
10425                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
10426                 vmx->nested.pi_desc =
10427                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
10428                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10429                         (PAGE_SIZE - 1)));
10430                 vmcs_write64(POSTED_INTR_DESC_ADDR,
10431                         page_to_phys(vmx->nested.pi_desc_page) +
10432                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10433                         (PAGE_SIZE - 1)));
10434         }
10435         if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
10436                 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
10437                               CPU_BASED_USE_MSR_BITMAPS);
10438         else
10439                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
10440                                 CPU_BASED_USE_MSR_BITMAPS);
10441 }
10442
10443 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
10444 {
10445         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
10446         struct vcpu_vmx *vmx = to_vmx(vcpu);
10447
10448         if (vcpu->arch.virtual_tsc_khz == 0)
10449                 return;
10450
10451         /* Make sure short timeouts reliably trigger an immediate vmexit.
10452          * hrtimer_start does not guarantee this. */
10453         if (preemption_timeout <= 1) {
10454                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
10455                 return;
10456         }
10457
10458         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10459         preemption_timeout *= 1000000;
10460         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
10461         hrtimer_start(&vmx->nested.preemption_timer,
10462                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
10463 }
10464
10465 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
10466                                                struct vmcs12 *vmcs12)
10467 {
10468         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
10469                 return 0;
10470
10471         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
10472             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
10473                 return -EINVAL;
10474
10475         return 0;
10476 }
10477
10478 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
10479                                                 struct vmcs12 *vmcs12)
10480 {
10481         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10482                 return 0;
10483
10484         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10485                 return -EINVAL;
10486
10487         return 0;
10488 }
10489
10490 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10491                                                 struct vmcs12 *vmcs12)
10492 {
10493         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10494                 return 0;
10495
10496         if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10497                 return -EINVAL;
10498
10499         return 0;
10500 }
10501
10502 /*
10503  * Merge L0's and L1's MSR bitmap, return false to indicate that
10504  * we do not use the hardware.
10505  */
10506 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10507                                                  struct vmcs12 *vmcs12)
10508 {
10509         int msr;
10510         struct page *page;
10511         unsigned long *msr_bitmap_l1;
10512         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
10513         /*
10514          * pred_cmd & spec_ctrl are trying to verify two things:
10515          *
10516          * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10517          *    ensures that we do not accidentally generate an L02 MSR bitmap
10518          *    from the L12 MSR bitmap that is too permissive.
10519          * 2. That L1 or L2s have actually used the MSR. This avoids
10520          *    unnecessarily merging of the bitmap if the MSR is unused. This
10521          *    works properly because we only update the L01 MSR bitmap lazily.
10522          *    So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10523          *    updated to reflect this when L1 (or its L2s) actually write to
10524          *    the MSR.
10525          */
10526         bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
10527         bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
10528
10529         /* Nothing to do if the MSR bitmap is not in use.  */
10530         if (!cpu_has_vmx_msr_bitmap() ||
10531             !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10532                 return false;
10533
10534         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10535             !pred_cmd && !spec_ctrl)
10536                 return false;
10537
10538         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10539         if (is_error_page(page))
10540                 return false;
10541
10542         msr_bitmap_l1 = (unsigned long *)kmap(page);
10543         if (nested_cpu_has_apic_reg_virt(vmcs12)) {
10544                 /*
10545                  * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
10546                  * just lets the processor take the value from the virtual-APIC page;
10547                  * take those 256 bits directly from the L1 bitmap.
10548                  */
10549                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10550                         unsigned word = msr / BITS_PER_LONG;
10551                         msr_bitmap_l0[word] = msr_bitmap_l1[word];
10552                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10553                 }
10554         } else {
10555                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10556                         unsigned word = msr / BITS_PER_LONG;
10557                         msr_bitmap_l0[word] = ~0;
10558                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10559                 }
10560         }
10561
10562         nested_vmx_disable_intercept_for_msr(
10563                 msr_bitmap_l1, msr_bitmap_l0,
10564                 X2APIC_MSR(APIC_TASKPRI),
10565                 MSR_TYPE_W);
10566
10567         if (nested_cpu_has_vid(vmcs12)) {
10568                 nested_vmx_disable_intercept_for_msr(
10569                         msr_bitmap_l1, msr_bitmap_l0,
10570                         X2APIC_MSR(APIC_EOI),
10571                         MSR_TYPE_W);
10572                 nested_vmx_disable_intercept_for_msr(
10573                         msr_bitmap_l1, msr_bitmap_l0,
10574                         X2APIC_MSR(APIC_SELF_IPI),
10575                         MSR_TYPE_W);
10576         }
10577
10578         if (spec_ctrl)
10579                 nested_vmx_disable_intercept_for_msr(
10580                                         msr_bitmap_l1, msr_bitmap_l0,
10581                                         MSR_IA32_SPEC_CTRL,
10582                                         MSR_TYPE_R | MSR_TYPE_W);
10583
10584         if (pred_cmd)
10585                 nested_vmx_disable_intercept_for_msr(
10586                                         msr_bitmap_l1, msr_bitmap_l0,
10587                                         MSR_IA32_PRED_CMD,
10588                                         MSR_TYPE_W);
10589
10590         kunmap(page);
10591         kvm_release_page_clean(page);
10592
10593         return true;
10594 }
10595
10596 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
10597                                           struct vmcs12 *vmcs12)
10598 {
10599         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
10600             !page_address_valid(vcpu, vmcs12->apic_access_addr))
10601                 return -EINVAL;
10602         else
10603                 return 0;
10604 }
10605
10606 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10607                                            struct vmcs12 *vmcs12)
10608 {
10609         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10610             !nested_cpu_has_apic_reg_virt(vmcs12) &&
10611             !nested_cpu_has_vid(vmcs12) &&
10612             !nested_cpu_has_posted_intr(vmcs12))
10613                 return 0;
10614
10615         /*
10616          * If virtualize x2apic mode is enabled,
10617          * virtualize apic access must be disabled.
10618          */
10619         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10620             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10621                 return -EINVAL;
10622
10623         /*
10624          * If virtual interrupt delivery is enabled,
10625          * we must exit on external interrupts.
10626          */
10627         if (nested_cpu_has_vid(vmcs12) &&
10628            !nested_exit_on_intr(vcpu))
10629                 return -EINVAL;
10630
10631         /*
10632          * bits 15:8 should be zero in posted_intr_nv,
10633          * the descriptor address has been already checked
10634          * in nested_get_vmcs12_pages.
10635          */
10636         if (nested_cpu_has_posted_intr(vmcs12) &&
10637            (!nested_cpu_has_vid(vmcs12) ||
10638             !nested_exit_intr_ack_set(vcpu) ||
10639             vmcs12->posted_intr_nv & 0xff00))
10640                 return -EINVAL;
10641
10642         /* tpr shadow is needed by all apicv features. */
10643         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10644                 return -EINVAL;
10645
10646         return 0;
10647 }
10648
10649 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10650                                        unsigned long count_field,
10651                                        unsigned long addr_field)
10652 {
10653         int maxphyaddr;
10654         u64 count, addr;
10655
10656         if (vmcs12_read_any(vcpu, count_field, &count) ||
10657             vmcs12_read_any(vcpu, addr_field, &addr)) {
10658                 WARN_ON(1);
10659                 return -EINVAL;
10660         }
10661         if (count == 0)
10662                 return 0;
10663         maxphyaddr = cpuid_maxphyaddr(vcpu);
10664         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10665             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10666                 pr_debug_ratelimited(
10667                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10668                         addr_field, maxphyaddr, count, addr);
10669                 return -EINVAL;
10670         }
10671         return 0;
10672 }
10673
10674 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10675                                                 struct vmcs12 *vmcs12)
10676 {
10677         if (vmcs12->vm_exit_msr_load_count == 0 &&
10678             vmcs12->vm_exit_msr_store_count == 0 &&
10679             vmcs12->vm_entry_msr_load_count == 0)
10680                 return 0; /* Fast path */
10681         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10682                                         VM_EXIT_MSR_LOAD_ADDR) ||
10683             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10684                                         VM_EXIT_MSR_STORE_ADDR) ||
10685             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10686                                         VM_ENTRY_MSR_LOAD_ADDR))
10687                 return -EINVAL;
10688         return 0;
10689 }
10690
10691 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10692                                          struct vmcs12 *vmcs12)
10693 {
10694         u64 address = vmcs12->pml_address;
10695         int maxphyaddr = cpuid_maxphyaddr(vcpu);
10696
10697         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10698                 if (!nested_cpu_has_ept(vmcs12) ||
10699                     !IS_ALIGNED(address, 4096)  ||
10700                     address >> maxphyaddr)
10701                         return -EINVAL;
10702         }
10703
10704         return 0;
10705 }
10706
10707 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10708                                        struct vmx_msr_entry *e)
10709 {
10710         /* x2APIC MSR accesses are not allowed */
10711         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10712                 return -EINVAL;
10713         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10714             e->index == MSR_IA32_UCODE_REV)
10715                 return -EINVAL;
10716         if (e->reserved != 0)
10717                 return -EINVAL;
10718         return 0;
10719 }
10720
10721 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10722                                      struct vmx_msr_entry *e)
10723 {
10724         if (e->index == MSR_FS_BASE ||
10725             e->index == MSR_GS_BASE ||
10726             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10727             nested_vmx_msr_check_common(vcpu, e))
10728                 return -EINVAL;
10729         return 0;
10730 }
10731
10732 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10733                                       struct vmx_msr_entry *e)
10734 {
10735         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
10736             nested_vmx_msr_check_common(vcpu, e))
10737                 return -EINVAL;
10738         return 0;
10739 }
10740
10741 /*
10742  * Load guest's/host's msr at nested entry/exit.
10743  * return 0 for success, entry index for failure.
10744  */
10745 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10746 {
10747         u32 i;
10748         struct vmx_msr_entry e;
10749         struct msr_data msr;
10750
10751         msr.host_initiated = false;
10752         for (i = 0; i < count; i++) {
10753                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
10754                                         &e, sizeof(e))) {
10755                         pr_debug_ratelimited(
10756                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10757                                 __func__, i, gpa + i * sizeof(e));
10758                         goto fail;
10759                 }
10760                 if (nested_vmx_load_msr_check(vcpu, &e)) {
10761                         pr_debug_ratelimited(
10762                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10763                                 __func__, i, e.index, e.reserved);
10764                         goto fail;
10765                 }
10766                 msr.index = e.index;
10767                 msr.data = e.value;
10768                 if (kvm_set_msr(vcpu, &msr)) {
10769                         pr_debug_ratelimited(
10770                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10771                                 __func__, i, e.index, e.value);
10772                         goto fail;
10773                 }
10774         }
10775         return 0;
10776 fail:
10777         return i + 1;
10778 }
10779
10780 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10781 {
10782         u32 i;
10783         struct vmx_msr_entry e;
10784
10785         for (i = 0; i < count; i++) {
10786                 struct msr_data msr_info;
10787                 if (kvm_vcpu_read_guest(vcpu,
10788                                         gpa + i * sizeof(e),
10789                                         &e, 2 * sizeof(u32))) {
10790                         pr_debug_ratelimited(
10791                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10792                                 __func__, i, gpa + i * sizeof(e));
10793                         return -EINVAL;
10794                 }
10795                 if (nested_vmx_store_msr_check(vcpu, &e)) {
10796                         pr_debug_ratelimited(
10797                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10798                                 __func__, i, e.index, e.reserved);
10799                         return -EINVAL;
10800                 }
10801                 msr_info.host_initiated = false;
10802                 msr_info.index = e.index;
10803                 if (kvm_get_msr(vcpu, &msr_info)) {
10804                         pr_debug_ratelimited(
10805                                 "%s cannot read MSR (%u, 0x%x)\n",
10806                                 __func__, i, e.index);
10807                         return -EINVAL;
10808                 }
10809                 if (kvm_vcpu_write_guest(vcpu,
10810                                          gpa + i * sizeof(e) +
10811                                              offsetof(struct vmx_msr_entry, value),
10812                                          &msr_info.data, sizeof(msr_info.data))) {
10813                         pr_debug_ratelimited(
10814                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10815                                 __func__, i, e.index, msr_info.data);
10816                         return -EINVAL;
10817                 }
10818         }
10819         return 0;
10820 }
10821
10822 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10823 {
10824         unsigned long invalid_mask;
10825
10826         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10827         return (val & invalid_mask) == 0;
10828 }
10829
10830 /*
10831  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10832  * emulating VM entry into a guest with EPT enabled.
10833  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10834  * is assigned to entry_failure_code on failure.
10835  */
10836 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10837                                u32 *entry_failure_code)
10838 {
10839         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10840                 if (!nested_cr3_valid(vcpu, cr3)) {
10841                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10842                         return 1;
10843                 }
10844
10845                 /*
10846                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10847                  * must not be dereferenced.
10848                  */
10849                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10850                     !nested_ept) {
10851                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10852                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
10853                                 return 1;
10854                         }
10855                 }
10856
10857                 vcpu->arch.cr3 = cr3;
10858                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10859         }
10860
10861         kvm_mmu_reset_context(vcpu);
10862         return 0;
10863 }
10864
10865 static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10866                                bool from_vmentry)
10867 {
10868         struct vcpu_vmx *vmx = to_vmx(vcpu);
10869
10870         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10871         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10872         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10873         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10874         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10875         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10876         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10877         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10878         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10879         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10880         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10881         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10882         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10883         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10884         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10885         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10886         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10887         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10888         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10889         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10890         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10891         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10892         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10893         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10894         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10895         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10896         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10897         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10898         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10899         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10900         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10901
10902         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10903         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10904                 vmcs12->guest_pending_dbg_exceptions);
10905         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10906         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10907
10908         if (nested_cpu_has_xsaves(vmcs12))
10909                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10910         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10911
10912         if (cpu_has_vmx_posted_intr())
10913                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10914
10915         /*
10916          * Whether page-faults are trapped is determined by a combination of
10917          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10918          * If enable_ept, L0 doesn't care about page faults and we should
10919          * set all of these to L1's desires. However, if !enable_ept, L0 does
10920          * care about (at least some) page faults, and because it is not easy
10921          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10922          * to exit on each and every L2 page fault. This is done by setting
10923          * MASK=MATCH=0 and (see below) EB.PF=1.
10924          * Note that below we don't need special code to set EB.PF beyond the
10925          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10926          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10927          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10928          */
10929         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10930                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10931         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10932                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10933
10934         /* All VMFUNCs are currently emulated through L0 vmexits.  */
10935         if (cpu_has_vmx_vmfunc())
10936                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
10937
10938         if (cpu_has_vmx_apicv()) {
10939                 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
10940                 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
10941                 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
10942                 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
10943         }
10944
10945         /*
10946          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10947          * Some constant fields are set here by vmx_set_constant_host_state().
10948          * Other fields are different per CPU, and will be set later when
10949          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10950          */
10951         vmx_set_constant_host_state(vmx);
10952
10953         /*
10954          * Set the MSR load/store lists to match L0's settings.
10955          */
10956         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10957         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10958         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10959         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10960         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10961
10962         set_cr4_guest_host_mask(vmx);
10963
10964         if (vmx_mpx_supported())
10965                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10966
10967         if (enable_vpid) {
10968                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
10969                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10970                 else
10971                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10972         }
10973
10974         /*
10975          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10976          */
10977         if (enable_ept) {
10978                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10979                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10980                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10981                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10982         }
10983
10984         if (cpu_has_vmx_msr_bitmap())
10985                 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
10986 }
10987
10988 /*
10989  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10990  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10991  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10992  * guest in a way that will both be appropriate to L1's requests, and our
10993  * needs. In addition to modifying the active vmcs (which is vmcs02), this
10994  * function also has additional necessary side-effects, like setting various
10995  * vcpu->arch fields.
10996  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10997  * is assigned to entry_failure_code on failure.
10998  */
10999 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11000                           bool from_vmentry, u32 *entry_failure_code)
11001 {
11002         struct vcpu_vmx *vmx = to_vmx(vcpu);
11003         u32 exec_control, vmcs12_exec_ctrl;
11004
11005         if (vmx->nested.dirty_vmcs12) {
11006                 prepare_vmcs02_full(vcpu, vmcs12, from_vmentry);
11007                 vmx->nested.dirty_vmcs12 = false;
11008         }
11009
11010         /*
11011          * First, the fields that are shadowed.  This must be kept in sync
11012          * with vmx_shadow_fields.h.
11013          */
11014
11015         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
11016         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
11017         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
11018         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
11019         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
11020
11021         /*
11022          * Not in vmcs02: GUEST_PML_INDEX, HOST_FS_SELECTOR, HOST_GS_SELECTOR,
11023          * HOST_FS_BASE, HOST_GS_BASE.
11024          */
11025
11026         if (from_vmentry &&
11027             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
11028                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
11029                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
11030         } else {
11031                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
11032                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
11033         }
11034         if (from_vmentry) {
11035                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
11036                              vmcs12->vm_entry_intr_info_field);
11037                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
11038                              vmcs12->vm_entry_exception_error_code);
11039                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
11040                              vmcs12->vm_entry_instruction_len);
11041                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
11042                              vmcs12->guest_interruptibility_info);
11043                 vmx->loaded_vmcs->nmi_known_unmasked =
11044                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
11045         } else {
11046                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
11047         }
11048         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
11049
11050         exec_control = vmcs12->pin_based_vm_exec_control;
11051
11052         /* Preemption timer setting is only taken from vmcs01.  */
11053         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11054         exec_control |= vmcs_config.pin_based_exec_ctrl;
11055         if (vmx->hv_deadline_tsc == -1)
11056                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11057
11058         /* Posted interrupts setting is only taken from vmcs12.  */
11059         if (nested_cpu_has_posted_intr(vmcs12)) {
11060                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
11061                 vmx->nested.pi_pending = false;
11062         } else {
11063                 exec_control &= ~PIN_BASED_POSTED_INTR;
11064         }
11065
11066         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
11067
11068         vmx->nested.preemption_timer_expired = false;
11069         if (nested_cpu_has_preemption_timer(vmcs12))
11070                 vmx_start_preemption_timer(vcpu);
11071
11072         if (cpu_has_secondary_exec_ctrls()) {
11073                 exec_control = vmx->secondary_exec_control;
11074
11075                 /* Take the following fields only from vmcs12 */
11076                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
11077                                   SECONDARY_EXEC_ENABLE_INVPCID |
11078                                   SECONDARY_EXEC_RDTSCP |
11079                                   SECONDARY_EXEC_XSAVES |
11080                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
11081                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
11082                                   SECONDARY_EXEC_ENABLE_VMFUNC);
11083                 if (nested_cpu_has(vmcs12,
11084                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
11085                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
11086                                 ~SECONDARY_EXEC_ENABLE_PML;
11087                         exec_control |= vmcs12_exec_ctrl;
11088                 }
11089
11090                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
11091                         vmcs_write16(GUEST_INTR_STATUS,
11092                                 vmcs12->guest_intr_status);
11093
11094                 /*
11095                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
11096                  * nested_get_vmcs12_pages will either fix it up or
11097                  * remove the VM execution control.
11098                  */
11099                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
11100                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
11101
11102                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
11103         }
11104
11105         /*
11106          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
11107          * entry, but only if the current (host) sp changed from the value
11108          * we wrote last (vmx->host_rsp). This cache is no longer relevant
11109          * if we switch vmcs, and rather than hold a separate cache per vmcs,
11110          * here we just force the write to happen on entry.
11111          */
11112         vmx->host_rsp = 0;
11113
11114         exec_control = vmx_exec_control(vmx); /* L0's desires */
11115         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
11116         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
11117         exec_control &= ~CPU_BASED_TPR_SHADOW;
11118         exec_control |= vmcs12->cpu_based_vm_exec_control;
11119
11120         /*
11121          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
11122          * nested_get_vmcs12_pages can't fix it up, the illegal value
11123          * will result in a VM entry failure.
11124          */
11125         if (exec_control & CPU_BASED_TPR_SHADOW) {
11126                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
11127                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
11128         } else {
11129 #ifdef CONFIG_X86_64
11130                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
11131                                 CPU_BASED_CR8_STORE_EXITING;
11132 #endif
11133         }
11134
11135         /*
11136          * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
11137          * for I/O port accesses.
11138          */
11139         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
11140         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
11141
11142         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
11143
11144         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
11145          * bitwise-or of what L1 wants to trap for L2, and what we want to
11146          * trap. Note that CR0.TS also needs updating - we do this later.
11147          */
11148         update_exception_bitmap(vcpu);
11149         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
11150         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
11151
11152         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
11153          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
11154          * bits are further modified by vmx_set_efer() below.
11155          */
11156         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
11157
11158         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
11159          * emulated by vmx_set_efer(), below.
11160          */
11161         vm_entry_controls_init(vmx,
11162                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
11163                         ~VM_ENTRY_IA32E_MODE) |
11164                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
11165
11166         if (from_vmentry &&
11167             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
11168                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
11169                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
11170         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
11171                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
11172         }
11173
11174         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11175
11176         if (kvm_has_tsc_control)
11177                 decache_tsc_multiplier(vmx);
11178
11179         if (enable_vpid) {
11180                 /*
11181                  * There is no direct mapping between vpid02 and vpid12, the
11182                  * vpid02 is per-vCPU for L0 and reused while the value of
11183                  * vpid12 is changed w/ one invvpid during nested vmentry.
11184                  * The vpid12 is allocated by L1 for L2, so it will not
11185                  * influence global bitmap(for vpid01 and vpid02 allocation)
11186                  * even if spawn a lot of nested vCPUs.
11187                  */
11188                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
11189                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
11190                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
11191                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02, true);
11192                         }
11193                 } else {
11194                         vmx_flush_tlb(vcpu, true);
11195                 }
11196         }
11197
11198         if (enable_pml) {
11199                 /*
11200                  * Conceptually we want to copy the PML address and index from
11201                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
11202                  * since we always flush the log on each vmexit, this happens
11203                  * to be equivalent to simply resetting the fields in vmcs02.
11204                  */
11205                 ASSERT(vmx->pml_pg);
11206                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
11207                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
11208         }
11209
11210         if (nested_cpu_has_ept(vmcs12)) {
11211                 if (nested_ept_init_mmu_context(vcpu)) {
11212                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
11213                         return 1;
11214                 }
11215         } else if (nested_cpu_has2(vmcs12,
11216                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11217                 vmx_flush_tlb(vcpu, true);
11218         }
11219
11220         /*
11221          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
11222          * bits which we consider mandatory enabled.
11223          * The CR0_READ_SHADOW is what L2 should have expected to read given
11224          * the specifications by L1; It's not enough to take
11225          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
11226          * have more bits than L1 expected.
11227          */
11228         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
11229         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
11230
11231         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
11232         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
11233
11234         if (from_vmentry &&
11235             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
11236                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
11237         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
11238                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11239         else
11240                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11241         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
11242         vmx_set_efer(vcpu, vcpu->arch.efer);
11243
11244         /*
11245          * Guest state is invalid and unrestricted guest is disabled,
11246          * which means L1 attempted VMEntry to L2 with invalid state.
11247          * Fail the VMEntry.
11248          */
11249         if (vmx->emulation_required) {
11250                 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11251                 return 1;
11252         }
11253
11254         /* Shadow page tables on either EPT or shadow page tables. */
11255         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
11256                                 entry_failure_code))
11257                 return 1;
11258
11259         if (!enable_ept)
11260                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
11261
11262         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
11263         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
11264         return 0;
11265 }
11266
11267 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
11268 {
11269         if (!nested_cpu_has_nmi_exiting(vmcs12) &&
11270             nested_cpu_has_virtual_nmis(vmcs12))
11271                 return -EINVAL;
11272
11273         if (!nested_cpu_has_virtual_nmis(vmcs12) &&
11274             nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING))
11275                 return -EINVAL;
11276
11277         return 0;
11278 }
11279
11280 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11281 {
11282         struct vcpu_vmx *vmx = to_vmx(vcpu);
11283
11284         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
11285             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
11286                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11287
11288         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
11289                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11290
11291         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
11292                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11293
11294         if (nested_vmx_check_apic_access_controls(vcpu, vmcs12))
11295                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11296
11297         if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
11298                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11299
11300         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
11301                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11302
11303         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
11304                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11305
11306         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
11307                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11308
11309         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
11310                                 vmx->nested.msrs.procbased_ctls_low,
11311                                 vmx->nested.msrs.procbased_ctls_high) ||
11312             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
11313              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
11314                                  vmx->nested.msrs.secondary_ctls_low,
11315                                  vmx->nested.msrs.secondary_ctls_high)) ||
11316             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
11317                                 vmx->nested.msrs.pinbased_ctls_low,
11318                                 vmx->nested.msrs.pinbased_ctls_high) ||
11319             !vmx_control_verify(vmcs12->vm_exit_controls,
11320                                 vmx->nested.msrs.exit_ctls_low,
11321                                 vmx->nested.msrs.exit_ctls_high) ||
11322             !vmx_control_verify(vmcs12->vm_entry_controls,
11323                                 vmx->nested.msrs.entry_ctls_low,
11324                                 vmx->nested.msrs.entry_ctls_high))
11325                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11326
11327         if (nested_vmx_check_nmi_controls(vmcs12))
11328                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11329
11330         if (nested_cpu_has_vmfunc(vmcs12)) {
11331                 if (vmcs12->vm_function_control &
11332                     ~vmx->nested.msrs.vmfunc_controls)
11333                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11334
11335                 if (nested_cpu_has_eptp_switching(vmcs12)) {
11336                         if (!nested_cpu_has_ept(vmcs12) ||
11337                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
11338                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11339                 }
11340         }
11341
11342         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
11343                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11344
11345         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
11346             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
11347             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
11348                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
11349
11350         return 0;
11351 }
11352
11353 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11354                                   u32 *exit_qual)
11355 {
11356         bool ia32e;
11357
11358         *exit_qual = ENTRY_FAIL_DEFAULT;
11359
11360         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
11361             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
11362                 return 1;
11363
11364         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
11365             vmcs12->vmcs_link_pointer != -1ull) {
11366                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
11367                 return 1;
11368         }
11369
11370         /*
11371          * If the load IA32_EFER VM-entry control is 1, the following checks
11372          * are performed on the field for the IA32_EFER MSR:
11373          * - Bits reserved in the IA32_EFER MSR must be 0.
11374          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11375          *   the IA-32e mode guest VM-exit control. It must also be identical
11376          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11377          *   CR0.PG) is 1.
11378          */
11379         if (to_vmx(vcpu)->nested.nested_run_pending &&
11380             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
11381                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
11382                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
11383                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
11384                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
11385                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
11386                         return 1;
11387         }
11388
11389         /*
11390          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11391          * IA32_EFER MSR must be 0 in the field for that register. In addition,
11392          * the values of the LMA and LME bits in the field must each be that of
11393          * the host address-space size VM-exit control.
11394          */
11395         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
11396                 ia32e = (vmcs12->vm_exit_controls &
11397                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
11398                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
11399                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
11400                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
11401                         return 1;
11402         }
11403
11404         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
11405                 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
11406                 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
11407                         return 1;
11408
11409         return 0;
11410 }
11411
11412 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
11413 {
11414         struct vcpu_vmx *vmx = to_vmx(vcpu);
11415         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11416         u32 msr_entry_idx;
11417         u32 exit_qual;
11418         int r;
11419
11420         enter_guest_mode(vcpu);
11421
11422         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
11423                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11424
11425         vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
11426         vmx_segment_cache_clear(vmx);
11427
11428         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11429                 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
11430
11431         r = EXIT_REASON_INVALID_STATE;
11432         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual))
11433                 goto fail;
11434
11435         nested_get_vmcs12_pages(vcpu, vmcs12);
11436
11437         r = EXIT_REASON_MSR_LOAD_FAIL;
11438         msr_entry_idx = nested_vmx_load_msr(vcpu,
11439                                             vmcs12->vm_entry_msr_load_addr,
11440                                             vmcs12->vm_entry_msr_load_count);
11441         if (msr_entry_idx)
11442                 goto fail;
11443
11444         /*
11445          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11446          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11447          * returned as far as L1 is concerned. It will only return (and set
11448          * the success flag) when L2 exits (see nested_vmx_vmexit()).
11449          */
11450         return 0;
11451
11452 fail:
11453         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11454                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
11455         leave_guest_mode(vcpu);
11456         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11457         nested_vmx_entry_failure(vcpu, vmcs12, r, exit_qual);
11458         return 1;
11459 }
11460
11461 /*
11462  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11463  * for running an L2 nested guest.
11464  */
11465 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
11466 {
11467         struct vmcs12 *vmcs12;
11468         struct vcpu_vmx *vmx = to_vmx(vcpu);
11469         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
11470         u32 exit_qual;
11471         int ret;
11472
11473         if (!nested_vmx_check_permission(vcpu))
11474                 return 1;
11475
11476         if (!nested_vmx_check_vmcs12(vcpu))
11477                 goto out;
11478
11479         vmcs12 = get_vmcs12(vcpu);
11480
11481         if (enable_shadow_vmcs)
11482                 copy_shadow_to_vmcs12(vmx);
11483
11484         /*
11485          * The nested entry process starts with enforcing various prerequisites
11486          * on vmcs12 as required by the Intel SDM, and act appropriately when
11487          * they fail: As the SDM explains, some conditions should cause the
11488          * instruction to fail, while others will cause the instruction to seem
11489          * to succeed, but return an EXIT_REASON_INVALID_STATE.
11490          * To speed up the normal (success) code path, we should avoid checking
11491          * for misconfigurations which will anyway be caught by the processor
11492          * when using the merged vmcs02.
11493          */
11494         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
11495                 nested_vmx_failValid(vcpu,
11496                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
11497                 goto out;
11498         }
11499
11500         if (vmcs12->launch_state == launch) {
11501                 nested_vmx_failValid(vcpu,
11502                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11503                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
11504                 goto out;
11505         }
11506
11507         ret = check_vmentry_prereqs(vcpu, vmcs12);
11508         if (ret) {
11509                 nested_vmx_failValid(vcpu, ret);
11510                 goto out;
11511         }
11512
11513         /*
11514          * After this point, the trap flag no longer triggers a singlestep trap
11515          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11516          * This is not 100% correct; for performance reasons, we delegate most
11517          * of the checks on host state to the processor.  If those fail,
11518          * the singlestep trap is missed.
11519          */
11520         skip_emulated_instruction(vcpu);
11521
11522         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
11523         if (ret) {
11524                 nested_vmx_entry_failure(vcpu, vmcs12,
11525                                          EXIT_REASON_INVALID_STATE, exit_qual);
11526                 return 1;
11527         }
11528
11529         /*
11530          * We're finally done with prerequisite checking, and can start with
11531          * the nested entry.
11532          */
11533
11534         ret = enter_vmx_non_root_mode(vcpu, true);
11535         if (ret)
11536                 return ret;
11537
11538         /*
11539          * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
11540          * by event injection, halt vcpu.
11541          */
11542         if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
11543             !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK))
11544                 return kvm_vcpu_halt(vcpu);
11545
11546         vmx->nested.nested_run_pending = 1;
11547
11548         return 1;
11549
11550 out:
11551         return kvm_skip_emulated_instruction(vcpu);
11552 }
11553
11554 /*
11555  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11556  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11557  * This function returns the new value we should put in vmcs12.guest_cr0.
11558  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11559  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11560  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11561  *     didn't trap the bit, because if L1 did, so would L0).
11562  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11563  *     been modified by L2, and L1 knows it. So just leave the old value of
11564  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11565  *     isn't relevant, because if L0 traps this bit it can set it to anything.
11566  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11567  *     changed these bits, and therefore they need to be updated, but L0
11568  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11569  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11570  */
11571 static inline unsigned long
11572 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11573 {
11574         return
11575         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
11576         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
11577         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
11578                         vcpu->arch.cr0_guest_owned_bits));
11579 }
11580
11581 static inline unsigned long
11582 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11583 {
11584         return
11585         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
11586         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
11587         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
11588                         vcpu->arch.cr4_guest_owned_bits));
11589 }
11590
11591 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
11592                                        struct vmcs12 *vmcs12)
11593 {
11594         u32 idt_vectoring;
11595         unsigned int nr;
11596
11597         if (vcpu->arch.exception.injected) {
11598                 nr = vcpu->arch.exception.nr;
11599                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11600
11601                 if (kvm_exception_is_soft(nr)) {
11602                         vmcs12->vm_exit_instruction_len =
11603                                 vcpu->arch.event_exit_inst_len;
11604                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11605                 } else
11606                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11607
11608                 if (vcpu->arch.exception.has_error_code) {
11609                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11610                         vmcs12->idt_vectoring_error_code =
11611                                 vcpu->arch.exception.error_code;
11612                 }
11613
11614                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11615         } else if (vcpu->arch.nmi_injected) {
11616                 vmcs12->idt_vectoring_info_field =
11617                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11618         } else if (vcpu->arch.interrupt.injected) {
11619                 nr = vcpu->arch.interrupt.nr;
11620                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11621
11622                 if (vcpu->arch.interrupt.soft) {
11623                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
11624                         vmcs12->vm_entry_instruction_len =
11625                                 vcpu->arch.event_exit_inst_len;
11626                 } else
11627                         idt_vectoring |= INTR_TYPE_EXT_INTR;
11628
11629                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11630         }
11631 }
11632
11633 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
11634 {
11635         struct vcpu_vmx *vmx = to_vmx(vcpu);
11636         unsigned long exit_qual;
11637         bool block_nested_events =
11638             vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
11639
11640         if (vcpu->arch.exception.pending &&
11641                 nested_vmx_check_exception(vcpu, &exit_qual)) {
11642                 if (block_nested_events)
11643                         return -EBUSY;
11644                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11645                 return 0;
11646         }
11647
11648         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11649             vmx->nested.preemption_timer_expired) {
11650                 if (block_nested_events)
11651                         return -EBUSY;
11652                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11653                 return 0;
11654         }
11655
11656         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11657                 if (block_nested_events)
11658                         return -EBUSY;
11659                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11660                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
11661                                   INTR_INFO_VALID_MASK, 0);
11662                 /*
11663                  * The NMI-triggered VM exit counts as injection:
11664                  * clear this one and block further NMIs.
11665                  */
11666                 vcpu->arch.nmi_pending = 0;
11667                 vmx_set_nmi_mask(vcpu, true);
11668                 return 0;
11669         }
11670
11671         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
11672             nested_exit_on_intr(vcpu)) {
11673                 if (block_nested_events)
11674                         return -EBUSY;
11675                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
11676                 return 0;
11677         }
11678
11679         vmx_complete_nested_posted_interrupt(vcpu);
11680         return 0;
11681 }
11682
11683 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
11684 {
11685         ktime_t remaining =
11686                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
11687         u64 value;
11688
11689         if (ktime_to_ns(remaining) <= 0)
11690                 return 0;
11691
11692         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
11693         do_div(value, 1000000);
11694         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11695 }
11696
11697 /*
11698  * Update the guest state fields of vmcs12 to reflect changes that
11699  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11700  * VM-entry controls is also updated, since this is really a guest
11701  * state bit.)
11702  */
11703 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11704 {
11705         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
11706         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
11707
11708         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
11709         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
11710         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
11711
11712         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
11713         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
11714         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
11715         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
11716         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11717         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11718         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11719         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11720         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11721         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11722         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
11723         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
11724         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
11725         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
11726         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
11727         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
11728         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
11729         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
11730         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
11731         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
11732         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
11733         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
11734         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
11735         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
11736         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
11737         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
11738         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
11739         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
11740         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
11741         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
11742         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
11743         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
11744         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
11745         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
11746         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
11747         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
11748
11749         vmcs12->guest_interruptibility_info =
11750                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
11751         vmcs12->guest_pending_dbg_exceptions =
11752                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
11753         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11754                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
11755         else
11756                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
11757
11758         if (nested_cpu_has_preemption_timer(vmcs12)) {
11759                 if (vmcs12->vm_exit_controls &
11760                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
11761                         vmcs12->vmx_preemption_timer_value =
11762                                 vmx_get_preemption_timer_value(vcpu);
11763                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
11764         }
11765
11766         /*
11767          * In some cases (usually, nested EPT), L2 is allowed to change its
11768          * own CR3 without exiting. If it has changed it, we must keep it.
11769          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11770          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11771          *
11772          * Additionally, restore L2's PDPTR to vmcs12.
11773          */
11774         if (enable_ept) {
11775                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
11776                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
11777                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
11778                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
11779                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
11780         }
11781
11782         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
11783
11784         if (nested_cpu_has_vid(vmcs12))
11785                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
11786
11787         vmcs12->vm_entry_controls =
11788                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
11789                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
11790
11791         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
11792                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
11793                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11794         }
11795
11796         /* TODO: These cannot have changed unless we have MSR bitmaps and
11797          * the relevant bit asks not to trap the change */
11798         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
11799                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
11800         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
11801                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
11802         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
11803         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
11804         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
11805         if (kvm_mpx_supported())
11806                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
11807 }
11808
11809 /*
11810  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11811  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11812  * and this function updates it to reflect the changes to the guest state while
11813  * L2 was running (and perhaps made some exits which were handled directly by L0
11814  * without going back to L1), and to reflect the exit reason.
11815  * Note that we do not have to copy here all VMCS fields, just those that
11816  * could have changed by the L2 guest or the exit - i.e., the guest-state and
11817  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11818  * which already writes to vmcs12 directly.
11819  */
11820 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11821                            u32 exit_reason, u32 exit_intr_info,
11822                            unsigned long exit_qualification)
11823 {
11824         /* update guest state fields: */
11825         sync_vmcs12(vcpu, vmcs12);
11826
11827         /* update exit information fields: */
11828
11829         vmcs12->vm_exit_reason = exit_reason;
11830         vmcs12->exit_qualification = exit_qualification;
11831         vmcs12->vm_exit_intr_info = exit_intr_info;
11832
11833         vmcs12->idt_vectoring_info_field = 0;
11834         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
11835         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
11836
11837         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
11838                 vmcs12->launch_state = 1;
11839
11840                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11841                  * instead of reading the real value. */
11842                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
11843
11844                 /*
11845                  * Transfer the event that L0 or L1 may wanted to inject into
11846                  * L2 to IDT_VECTORING_INFO_FIELD.
11847                  */
11848                 vmcs12_save_pending_event(vcpu, vmcs12);
11849         }
11850
11851         /*
11852          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11853          * preserved above and would only end up incorrectly in L1.
11854          */
11855         vcpu->arch.nmi_injected = false;
11856         kvm_clear_exception_queue(vcpu);
11857         kvm_clear_interrupt_queue(vcpu);
11858 }
11859
11860 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
11861                         struct vmcs12 *vmcs12)
11862 {
11863         u32 entry_failure_code;
11864
11865         nested_ept_uninit_mmu_context(vcpu);
11866
11867         /*
11868          * Only PDPTE load can fail as the value of cr3 was checked on entry and
11869          * couldn't have changed.
11870          */
11871         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
11872                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
11873
11874         if (!enable_ept)
11875                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11876 }
11877
11878 /*
11879  * A part of what we need to when the nested L2 guest exits and we want to
11880  * run its L1 parent, is to reset L1's guest state to the host state specified
11881  * in vmcs12.
11882  * This function is to be called not only on normal nested exit, but also on
11883  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11884  * Failures During or After Loading Guest State").
11885  * This function should be called when the active VMCS is L1's (vmcs01).
11886  */
11887 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
11888                                    struct vmcs12 *vmcs12)
11889 {
11890         struct kvm_segment seg;
11891
11892         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
11893                 vcpu->arch.efer = vmcs12->host_ia32_efer;
11894         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11895                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11896         else
11897                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11898         vmx_set_efer(vcpu, vcpu->arch.efer);
11899
11900         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11901         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
11902         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
11903         /*
11904          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11905          * actually changed, because vmx_set_cr0 refers to efer set above.
11906          *
11907          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11908          * (KVM doesn't change it);
11909          */
11910         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
11911         vmx_set_cr0(vcpu, vmcs12->host_cr0);
11912
11913         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
11914         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
11915         vmx_set_cr4(vcpu, vmcs12->host_cr4);
11916
11917         load_vmcs12_mmu_host_state(vcpu, vmcs12);
11918
11919         if (enable_vpid) {
11920                 /*
11921                  * Trivially support vpid by letting L2s share their parent
11922                  * L1's vpid. TODO: move to a more elaborate solution, giving
11923                  * each L2 its own vpid and exposing the vpid feature to L1.
11924                  */
11925                 vmx_flush_tlb(vcpu, true);
11926         }
11927
11928         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11929         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11930         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11931         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11932         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11933         vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
11934         vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
11935
11936         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
11937         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11938                 vmcs_write64(GUEST_BNDCFGS, 0);
11939
11940         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11941                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11942                 vcpu->arch.pat = vmcs12->host_ia32_pat;
11943         }
11944         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11945                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11946                         vmcs12->host_ia32_perf_global_ctrl);
11947
11948         /* Set L1 segment info according to Intel SDM
11949             27.5.2 Loading Host Segment and Descriptor-Table Registers */
11950         seg = (struct kvm_segment) {
11951                 .base = 0,
11952                 .limit = 0xFFFFFFFF,
11953                 .selector = vmcs12->host_cs_selector,
11954                 .type = 11,
11955                 .present = 1,
11956                 .s = 1,
11957                 .g = 1
11958         };
11959         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11960                 seg.l = 1;
11961         else
11962                 seg.db = 1;
11963         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11964         seg = (struct kvm_segment) {
11965                 .base = 0,
11966                 .limit = 0xFFFFFFFF,
11967                 .type = 3,
11968                 .present = 1,
11969                 .s = 1,
11970                 .db = 1,
11971                 .g = 1
11972         };
11973         seg.selector = vmcs12->host_ds_selector;
11974         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11975         seg.selector = vmcs12->host_es_selector;
11976         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11977         seg.selector = vmcs12->host_ss_selector;
11978         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11979         seg.selector = vmcs12->host_fs_selector;
11980         seg.base = vmcs12->host_fs_base;
11981         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11982         seg.selector = vmcs12->host_gs_selector;
11983         seg.base = vmcs12->host_gs_base;
11984         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11985         seg = (struct kvm_segment) {
11986                 .base = vmcs12->host_tr_base,
11987                 .limit = 0x67,
11988                 .selector = vmcs12->host_tr_selector,
11989                 .type = 11,
11990                 .present = 1
11991         };
11992         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11993
11994         kvm_set_dr(vcpu, 7, 0x400);
11995         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11996
11997         if (cpu_has_vmx_msr_bitmap())
11998                 vmx_update_msr_bitmap(vcpu);
11999
12000         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
12001                                 vmcs12->vm_exit_msr_load_count))
12002                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
12003 }
12004
12005 /*
12006  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
12007  * and modify vmcs12 to make it see what it would expect to see there if
12008  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
12009  */
12010 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
12011                               u32 exit_intr_info,
12012                               unsigned long exit_qualification)
12013 {
12014         struct vcpu_vmx *vmx = to_vmx(vcpu);
12015         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12016
12017         /* trying to cancel vmlaunch/vmresume is a bug */
12018         WARN_ON_ONCE(vmx->nested.nested_run_pending);
12019
12020         /*
12021          * The only expected VM-instruction error is "VM entry with
12022          * invalid control field(s)." Anything else indicates a
12023          * problem with L0.
12024          */
12025         WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
12026                                    VMXERR_ENTRY_INVALID_CONTROL_FIELD));
12027
12028         leave_guest_mode(vcpu);
12029
12030         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12031                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
12032
12033         if (likely(!vmx->fail)) {
12034                 if (exit_reason == -1)
12035                         sync_vmcs12(vcpu, vmcs12);
12036                 else
12037                         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
12038                                        exit_qualification);
12039
12040                 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
12041                                          vmcs12->vm_exit_msr_store_count))
12042                         nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
12043         }
12044
12045         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12046         vm_entry_controls_reset_shadow(vmx);
12047         vm_exit_controls_reset_shadow(vmx);
12048         vmx_segment_cache_clear(vmx);
12049
12050         /* Update any VMCS fields that might have changed while L2 ran */
12051         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
12052         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
12053         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
12054         if (vmx->hv_deadline_tsc == -1)
12055                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12056                                 PIN_BASED_VMX_PREEMPTION_TIMER);
12057         else
12058                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12059                               PIN_BASED_VMX_PREEMPTION_TIMER);
12060         if (kvm_has_tsc_control)
12061                 decache_tsc_multiplier(vmx);
12062
12063         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
12064                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
12065                 vmx_set_virtual_x2apic_mode(vcpu,
12066                                 vcpu->arch.apic_base & X2APIC_ENABLE);
12067         } else if (!nested_cpu_has_ept(vmcs12) &&
12068                    nested_cpu_has2(vmcs12,
12069                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
12070                 vmx_flush_tlb(vcpu, true);
12071         }
12072
12073         /* This is needed for same reason as it was needed in prepare_vmcs02 */
12074         vmx->host_rsp = 0;
12075
12076         /* Unpin physical memory we referred to in vmcs02 */
12077         if (vmx->nested.apic_access_page) {
12078                 kvm_release_page_dirty(vmx->nested.apic_access_page);
12079                 vmx->nested.apic_access_page = NULL;
12080         }
12081         if (vmx->nested.virtual_apic_page) {
12082                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
12083                 vmx->nested.virtual_apic_page = NULL;
12084         }
12085         if (vmx->nested.pi_desc_page) {
12086                 kunmap(vmx->nested.pi_desc_page);
12087                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
12088                 vmx->nested.pi_desc_page = NULL;
12089                 vmx->nested.pi_desc = NULL;
12090         }
12091
12092         /*
12093          * We are now running in L2, mmu_notifier will force to reload the
12094          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
12095          */
12096         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
12097
12098         if (enable_shadow_vmcs && exit_reason != -1)
12099                 vmx->nested.sync_shadow_vmcs = true;
12100
12101         /* in case we halted in L2 */
12102         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12103
12104         if (likely(!vmx->fail)) {
12105                 /*
12106                  * TODO: SDM says that with acknowledge interrupt on
12107                  * exit, bit 31 of the VM-exit interrupt information
12108                  * (valid interrupt) is always set to 1 on
12109                  * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
12110                  * need kvm_cpu_has_interrupt().  See the commit
12111                  * message for details.
12112                  */
12113                 if (nested_exit_intr_ack_set(vcpu) &&
12114                     exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
12115                     kvm_cpu_has_interrupt(vcpu)) {
12116                         int irq = kvm_cpu_get_interrupt(vcpu);
12117                         WARN_ON(irq < 0);
12118                         vmcs12->vm_exit_intr_info = irq |
12119                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
12120                 }
12121
12122                 if (exit_reason != -1)
12123                         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
12124                                                        vmcs12->exit_qualification,
12125                                                        vmcs12->idt_vectoring_info_field,
12126                                                        vmcs12->vm_exit_intr_info,
12127                                                        vmcs12->vm_exit_intr_error_code,
12128                                                        KVM_ISA_VMX);
12129
12130                 load_vmcs12_host_state(vcpu, vmcs12);
12131
12132                 return;
12133         }
12134
12135         /*
12136          * After an early L2 VM-entry failure, we're now back
12137          * in L1 which thinks it just finished a VMLAUNCH or
12138          * VMRESUME instruction, so we need to set the failure
12139          * flag and the VM-instruction error field of the VMCS
12140          * accordingly.
12141          */
12142         nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
12143
12144         load_vmcs12_mmu_host_state(vcpu, vmcs12);
12145
12146         /*
12147          * The emulated instruction was already skipped in
12148          * nested_vmx_run, but the updated RIP was never
12149          * written back to the vmcs01.
12150          */
12151         skip_emulated_instruction(vcpu);
12152         vmx->fail = 0;
12153 }
12154
12155 /*
12156  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
12157  */
12158 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
12159 {
12160         if (is_guest_mode(vcpu)) {
12161                 to_vmx(vcpu)->nested.nested_run_pending = 0;
12162                 nested_vmx_vmexit(vcpu, -1, 0, 0);
12163         }
12164         free_nested(to_vmx(vcpu));
12165 }
12166
12167 /*
12168  * L1's failure to enter L2 is a subset of a normal exit, as explained in
12169  * 23.7 "VM-entry failures during or after loading guest state" (this also
12170  * lists the acceptable exit-reason and exit-qualification parameters).
12171  * It should only be called before L2 actually succeeded to run, and when
12172  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
12173  */
12174 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
12175                         struct vmcs12 *vmcs12,
12176                         u32 reason, unsigned long qualification)
12177 {
12178         load_vmcs12_host_state(vcpu, vmcs12);
12179         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
12180         vmcs12->exit_qualification = qualification;
12181         nested_vmx_succeed(vcpu);
12182         if (enable_shadow_vmcs)
12183                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
12184 }
12185
12186 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
12187                                struct x86_instruction_info *info,
12188                                enum x86_intercept_stage stage)
12189 {
12190         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12191         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
12192
12193         /*
12194          * RDPID causes #UD if disabled through secondary execution controls.
12195          * Because it is marked as EmulateOnUD, we need to intercept it here.
12196          */
12197         if (info->intercept == x86_intercept_rdtscp &&
12198             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
12199                 ctxt->exception.vector = UD_VECTOR;
12200                 ctxt->exception.error_code_valid = false;
12201                 return X86EMUL_PROPAGATE_FAULT;
12202         }
12203
12204         /* TODO: check more intercepts... */
12205         return X86EMUL_CONTINUE;
12206 }
12207
12208 #ifdef CONFIG_X86_64
12209 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
12210 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
12211                                   u64 divisor, u64 *result)
12212 {
12213         u64 low = a << shift, high = a >> (64 - shift);
12214
12215         /* To avoid the overflow on divq */
12216         if (high >= divisor)
12217                 return 1;
12218
12219         /* Low hold the result, high hold rem which is discarded */
12220         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
12221             "rm" (divisor), "0" (low), "1" (high));
12222         *result = low;
12223
12224         return 0;
12225 }
12226
12227 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
12228 {
12229         struct vcpu_vmx *vmx;
12230         u64 tscl, guest_tscl, delta_tsc;
12231
12232         if (kvm_mwait_in_guest(vcpu->kvm))
12233                 return -EOPNOTSUPP;
12234
12235         vmx = to_vmx(vcpu);
12236         tscl = rdtsc();
12237         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
12238         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
12239
12240         /* Convert to host delta tsc if tsc scaling is enabled */
12241         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
12242                         u64_shl_div_u64(delta_tsc,
12243                                 kvm_tsc_scaling_ratio_frac_bits,
12244                                 vcpu->arch.tsc_scaling_ratio,
12245                                 &delta_tsc))
12246                 return -ERANGE;
12247
12248         /*
12249          * If the delta tsc can't fit in the 32 bit after the multi shift,
12250          * we can't use the preemption timer.
12251          * It's possible that it fits on later vmentries, but checking
12252          * on every vmentry is costly so we just use an hrtimer.
12253          */
12254         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
12255                 return -ERANGE;
12256
12257         vmx->hv_deadline_tsc = tscl + delta_tsc;
12258         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12259                         PIN_BASED_VMX_PREEMPTION_TIMER);
12260
12261         return delta_tsc == 0;
12262 }
12263
12264 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
12265 {
12266         struct vcpu_vmx *vmx = to_vmx(vcpu);
12267         vmx->hv_deadline_tsc = -1;
12268         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12269                         PIN_BASED_VMX_PREEMPTION_TIMER);
12270 }
12271 #endif
12272
12273 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
12274 {
12275         if (!kvm_pause_in_guest(vcpu->kvm))
12276                 shrink_ple_window(vcpu);
12277 }
12278
12279 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
12280                                      struct kvm_memory_slot *slot)
12281 {
12282         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
12283         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
12284 }
12285
12286 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
12287                                        struct kvm_memory_slot *slot)
12288 {
12289         kvm_mmu_slot_set_dirty(kvm, slot);
12290 }
12291
12292 static void vmx_flush_log_dirty(struct kvm *kvm)
12293 {
12294         kvm_flush_pml_buffers(kvm);
12295 }
12296
12297 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
12298 {
12299         struct vmcs12 *vmcs12;
12300         struct vcpu_vmx *vmx = to_vmx(vcpu);
12301         gpa_t gpa;
12302         struct page *page = NULL;
12303         u64 *pml_address;
12304
12305         if (is_guest_mode(vcpu)) {
12306                 WARN_ON_ONCE(vmx->nested.pml_full);
12307
12308                 /*
12309                  * Check if PML is enabled for the nested guest.
12310                  * Whether eptp bit 6 is set is already checked
12311                  * as part of A/D emulation.
12312                  */
12313                 vmcs12 = get_vmcs12(vcpu);
12314                 if (!nested_cpu_has_pml(vmcs12))
12315                         return 0;
12316
12317                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
12318                         vmx->nested.pml_full = true;
12319                         return 1;
12320                 }
12321
12322                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
12323
12324                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
12325                 if (is_error_page(page))
12326                         return 0;
12327
12328                 pml_address = kmap(page);
12329                 pml_address[vmcs12->guest_pml_index--] = gpa;
12330                 kunmap(page);
12331                 kvm_release_page_clean(page);
12332         }
12333
12334         return 0;
12335 }
12336
12337 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
12338                                            struct kvm_memory_slot *memslot,
12339                                            gfn_t offset, unsigned long mask)
12340 {
12341         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
12342 }
12343
12344 static void __pi_post_block(struct kvm_vcpu *vcpu)
12345 {
12346         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12347         struct pi_desc old, new;
12348         unsigned int dest;
12349
12350         do {
12351                 old.control = new.control = pi_desc->control;
12352                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
12353                      "Wakeup handler not enabled while the VCPU is blocked\n");
12354
12355                 dest = cpu_physical_id(vcpu->cpu);
12356
12357                 if (x2apic_enabled())
12358                         new.ndst = dest;
12359                 else
12360                         new.ndst = (dest << 8) & 0xFF00;
12361
12362                 /* set 'NV' to 'notification vector' */
12363                 new.nv = POSTED_INTR_VECTOR;
12364         } while (cmpxchg64(&pi_desc->control, old.control,
12365                            new.control) != old.control);
12366
12367         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
12368                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12369                 list_del(&vcpu->blocked_vcpu_list);
12370                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12371                 vcpu->pre_pcpu = -1;
12372         }
12373 }
12374
12375 /*
12376  * This routine does the following things for vCPU which is going
12377  * to be blocked if VT-d PI is enabled.
12378  * - Store the vCPU to the wakeup list, so when interrupts happen
12379  *   we can find the right vCPU to wake up.
12380  * - Change the Posted-interrupt descriptor as below:
12381  *      'NDST' <-- vcpu->pre_pcpu
12382  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12383  * - If 'ON' is set during this process, which means at least one
12384  *   interrupt is posted for this vCPU, we cannot block it, in
12385  *   this case, return 1, otherwise, return 0.
12386  *
12387  */
12388 static int pi_pre_block(struct kvm_vcpu *vcpu)
12389 {
12390         unsigned int dest;
12391         struct pi_desc old, new;
12392         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12393
12394         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
12395                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
12396                 !kvm_vcpu_apicv_active(vcpu))
12397                 return 0;
12398
12399         WARN_ON(irqs_disabled());
12400         local_irq_disable();
12401         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
12402                 vcpu->pre_pcpu = vcpu->cpu;
12403                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12404                 list_add_tail(&vcpu->blocked_vcpu_list,
12405                               &per_cpu(blocked_vcpu_on_cpu,
12406                                        vcpu->pre_pcpu));
12407                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12408         }
12409
12410         do {
12411                 old.control = new.control = pi_desc->control;
12412
12413                 WARN((pi_desc->sn == 1),
12414                      "Warning: SN field of posted-interrupts "
12415                      "is set before blocking\n");
12416
12417                 /*
12418                  * Since vCPU can be preempted during this process,
12419                  * vcpu->cpu could be different with pre_pcpu, we
12420                  * need to set pre_pcpu as the destination of wakeup
12421                  * notification event, then we can find the right vCPU
12422                  * to wakeup in wakeup handler if interrupts happen
12423                  * when the vCPU is in blocked state.
12424                  */
12425                 dest = cpu_physical_id(vcpu->pre_pcpu);
12426
12427                 if (x2apic_enabled())
12428                         new.ndst = dest;
12429                 else
12430                         new.ndst = (dest << 8) & 0xFF00;
12431
12432                 /* set 'NV' to 'wakeup vector' */
12433                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
12434         } while (cmpxchg64(&pi_desc->control, old.control,
12435                            new.control) != old.control);
12436
12437         /* We should not block the vCPU if an interrupt is posted for it.  */
12438         if (pi_test_on(pi_desc) == 1)
12439                 __pi_post_block(vcpu);
12440
12441         local_irq_enable();
12442         return (vcpu->pre_pcpu == -1);
12443 }
12444
12445 static int vmx_pre_block(struct kvm_vcpu *vcpu)
12446 {
12447         if (pi_pre_block(vcpu))
12448                 return 1;
12449
12450         if (kvm_lapic_hv_timer_in_use(vcpu))
12451                 kvm_lapic_switch_to_sw_timer(vcpu);
12452
12453         return 0;
12454 }
12455
12456 static void pi_post_block(struct kvm_vcpu *vcpu)
12457 {
12458         if (vcpu->pre_pcpu == -1)
12459                 return;
12460
12461         WARN_ON(irqs_disabled());
12462         local_irq_disable();
12463         __pi_post_block(vcpu);
12464         local_irq_enable();
12465 }
12466
12467 static void vmx_post_block(struct kvm_vcpu *vcpu)
12468 {
12469         if (kvm_x86_ops->set_hv_timer)
12470                 kvm_lapic_switch_to_hv_timer(vcpu);
12471
12472         pi_post_block(vcpu);
12473 }
12474
12475 /*
12476  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12477  *
12478  * @kvm: kvm
12479  * @host_irq: host irq of the interrupt
12480  * @guest_irq: gsi of the interrupt
12481  * @set: set or unset PI
12482  * returns 0 on success, < 0 on failure
12483  */
12484 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
12485                               uint32_t guest_irq, bool set)
12486 {
12487         struct kvm_kernel_irq_routing_entry *e;
12488         struct kvm_irq_routing_table *irq_rt;
12489         struct kvm_lapic_irq irq;
12490         struct kvm_vcpu *vcpu;
12491         struct vcpu_data vcpu_info;
12492         int idx, ret = 0;
12493
12494         if (!kvm_arch_has_assigned_device(kvm) ||
12495                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12496                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
12497                 return 0;
12498
12499         idx = srcu_read_lock(&kvm->irq_srcu);
12500         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
12501         if (guest_irq >= irq_rt->nr_rt_entries ||
12502             hlist_empty(&irq_rt->map[guest_irq])) {
12503                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12504                              guest_irq, irq_rt->nr_rt_entries);
12505                 goto out;
12506         }
12507
12508         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
12509                 if (e->type != KVM_IRQ_ROUTING_MSI)
12510                         continue;
12511                 /*
12512                  * VT-d PI cannot support posting multicast/broadcast
12513                  * interrupts to a vCPU, we still use interrupt remapping
12514                  * for these kind of interrupts.
12515                  *
12516                  * For lowest-priority interrupts, we only support
12517                  * those with single CPU as the destination, e.g. user
12518                  * configures the interrupts via /proc/irq or uses
12519                  * irqbalance to make the interrupts single-CPU.
12520                  *
12521                  * We will support full lowest-priority interrupt later.
12522                  */
12523
12524                 kvm_set_msi_irq(kvm, e, &irq);
12525                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
12526                         /*
12527                          * Make sure the IRTE is in remapped mode if
12528                          * we don't handle it in posted mode.
12529                          */
12530                         ret = irq_set_vcpu_affinity(host_irq, NULL);
12531                         if (ret < 0) {
12532                                 printk(KERN_INFO
12533                                    "failed to back to remapped mode, irq: %u\n",
12534                                    host_irq);
12535                                 goto out;
12536                         }
12537
12538                         continue;
12539                 }
12540
12541                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
12542                 vcpu_info.vector = irq.vector;
12543
12544                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
12545                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
12546
12547                 if (set)
12548                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
12549                 else
12550                         ret = irq_set_vcpu_affinity(host_irq, NULL);
12551
12552                 if (ret < 0) {
12553                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
12554                                         __func__);
12555                         goto out;
12556                 }
12557         }
12558
12559         ret = 0;
12560 out:
12561         srcu_read_unlock(&kvm->irq_srcu, idx);
12562         return ret;
12563 }
12564
12565 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
12566 {
12567         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
12568                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
12569                         FEATURE_CONTROL_LMCE;
12570         else
12571                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
12572                         ~FEATURE_CONTROL_LMCE;
12573 }
12574
12575 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
12576 {
12577         /* we need a nested vmexit to enter SMM, postpone if run is pending */
12578         if (to_vmx(vcpu)->nested.nested_run_pending)
12579                 return 0;
12580         return 1;
12581 }
12582
12583 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
12584 {
12585         struct vcpu_vmx *vmx = to_vmx(vcpu);
12586
12587         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
12588         if (vmx->nested.smm.guest_mode)
12589                 nested_vmx_vmexit(vcpu, -1, 0, 0);
12590
12591         vmx->nested.smm.vmxon = vmx->nested.vmxon;
12592         vmx->nested.vmxon = false;
12593         vmx_clear_hlt(vcpu);
12594         return 0;
12595 }
12596
12597 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
12598 {
12599         struct vcpu_vmx *vmx = to_vmx(vcpu);
12600         int ret;
12601
12602         if (vmx->nested.smm.vmxon) {
12603                 vmx->nested.vmxon = true;
12604                 vmx->nested.smm.vmxon = false;
12605         }
12606
12607         if (vmx->nested.smm.guest_mode) {
12608                 vcpu->arch.hflags &= ~HF_SMM_MASK;
12609                 ret = enter_vmx_non_root_mode(vcpu, false);
12610                 vcpu->arch.hflags |= HF_SMM_MASK;
12611                 if (ret)
12612                         return ret;
12613
12614                 vmx->nested.smm.guest_mode = false;
12615         }
12616         return 0;
12617 }
12618
12619 static int enable_smi_window(struct kvm_vcpu *vcpu)
12620 {
12621         return 0;
12622 }
12623
12624 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
12625         .cpu_has_kvm_support = cpu_has_kvm_support,
12626         .disabled_by_bios = vmx_disabled_by_bios,
12627         .hardware_setup = hardware_setup,
12628         .hardware_unsetup = hardware_unsetup,
12629         .check_processor_compatibility = vmx_check_processor_compat,
12630         .hardware_enable = hardware_enable,
12631         .hardware_disable = hardware_disable,
12632         .cpu_has_accelerated_tpr = report_flexpriority,
12633         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
12634
12635         .vm_init = vmx_vm_init,
12636         .vm_alloc = vmx_vm_alloc,
12637         .vm_free = vmx_vm_free,
12638
12639         .vcpu_create = vmx_create_vcpu,
12640         .vcpu_free = vmx_free_vcpu,
12641         .vcpu_reset = vmx_vcpu_reset,
12642
12643         .prepare_guest_switch = vmx_save_host_state,
12644         .vcpu_load = vmx_vcpu_load,
12645         .vcpu_put = vmx_vcpu_put,
12646
12647         .update_bp_intercept = update_exception_bitmap,
12648         .get_msr_feature = vmx_get_msr_feature,
12649         .get_msr = vmx_get_msr,
12650         .set_msr = vmx_set_msr,
12651         .get_segment_base = vmx_get_segment_base,
12652         .get_segment = vmx_get_segment,
12653         .set_segment = vmx_set_segment,
12654         .get_cpl = vmx_get_cpl,
12655         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
12656         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
12657         .decache_cr3 = vmx_decache_cr3,
12658         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
12659         .set_cr0 = vmx_set_cr0,
12660         .set_cr3 = vmx_set_cr3,
12661         .set_cr4 = vmx_set_cr4,
12662         .set_efer = vmx_set_efer,
12663         .get_idt = vmx_get_idt,
12664         .set_idt = vmx_set_idt,
12665         .get_gdt = vmx_get_gdt,
12666         .set_gdt = vmx_set_gdt,
12667         .get_dr6 = vmx_get_dr6,
12668         .set_dr6 = vmx_set_dr6,
12669         .set_dr7 = vmx_set_dr7,
12670         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
12671         .cache_reg = vmx_cache_reg,
12672         .get_rflags = vmx_get_rflags,
12673         .set_rflags = vmx_set_rflags,
12674
12675         .tlb_flush = vmx_flush_tlb,
12676
12677         .run = vmx_vcpu_run,
12678         .handle_exit = vmx_handle_exit,
12679         .skip_emulated_instruction = skip_emulated_instruction,
12680         .set_interrupt_shadow = vmx_set_interrupt_shadow,
12681         .get_interrupt_shadow = vmx_get_interrupt_shadow,
12682         .patch_hypercall = vmx_patch_hypercall,
12683         .set_irq = vmx_inject_irq,
12684         .set_nmi = vmx_inject_nmi,
12685         .queue_exception = vmx_queue_exception,
12686         .cancel_injection = vmx_cancel_injection,
12687         .interrupt_allowed = vmx_interrupt_allowed,
12688         .nmi_allowed = vmx_nmi_allowed,
12689         .get_nmi_mask = vmx_get_nmi_mask,
12690         .set_nmi_mask = vmx_set_nmi_mask,
12691         .enable_nmi_window = enable_nmi_window,
12692         .enable_irq_window = enable_irq_window,
12693         .update_cr8_intercept = update_cr8_intercept,
12694         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
12695         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
12696         .get_enable_apicv = vmx_get_enable_apicv,
12697         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
12698         .load_eoi_exitmap = vmx_load_eoi_exitmap,
12699         .apicv_post_state_restore = vmx_apicv_post_state_restore,
12700         .hwapic_irr_update = vmx_hwapic_irr_update,
12701         .hwapic_isr_update = vmx_hwapic_isr_update,
12702         .sync_pir_to_irr = vmx_sync_pir_to_irr,
12703         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
12704
12705         .set_tss_addr = vmx_set_tss_addr,
12706         .set_identity_map_addr = vmx_set_identity_map_addr,
12707         .get_tdp_level = get_ept_level,
12708         .get_mt_mask = vmx_get_mt_mask,
12709
12710         .get_exit_info = vmx_get_exit_info,
12711
12712         .get_lpage_level = vmx_get_lpage_level,
12713
12714         .cpuid_update = vmx_cpuid_update,
12715
12716         .rdtscp_supported = vmx_rdtscp_supported,
12717         .invpcid_supported = vmx_invpcid_supported,
12718
12719         .set_supported_cpuid = vmx_set_supported_cpuid,
12720
12721         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
12722
12723         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
12724         .write_tsc_offset = vmx_write_tsc_offset,
12725
12726         .set_tdp_cr3 = vmx_set_cr3,
12727
12728         .check_intercept = vmx_check_intercept,
12729         .handle_external_intr = vmx_handle_external_intr,
12730         .mpx_supported = vmx_mpx_supported,
12731         .xsaves_supported = vmx_xsaves_supported,
12732         .umip_emulated = vmx_umip_emulated,
12733
12734         .check_nested_events = vmx_check_nested_events,
12735
12736         .sched_in = vmx_sched_in,
12737
12738         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
12739         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
12740         .flush_log_dirty = vmx_flush_log_dirty,
12741         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
12742         .write_log_dirty = vmx_write_pml_buffer,
12743
12744         .pre_block = vmx_pre_block,
12745         .post_block = vmx_post_block,
12746
12747         .pmu_ops = &intel_pmu_ops,
12748
12749         .update_pi_irte = vmx_update_pi_irte,
12750
12751 #ifdef CONFIG_X86_64
12752         .set_hv_timer = vmx_set_hv_timer,
12753         .cancel_hv_timer = vmx_cancel_hv_timer,
12754 #endif
12755
12756         .setup_mce = vmx_setup_mce,
12757
12758         .smi_allowed = vmx_smi_allowed,
12759         .pre_enter_smm = vmx_pre_enter_smm,
12760         .pre_leave_smm = vmx_pre_leave_smm,
12761         .enable_smi_window = enable_smi_window,
12762 };
12763
12764 static int __init vmx_init(void)
12765 {
12766         int r;
12767
12768 #if IS_ENABLED(CONFIG_HYPERV)
12769         /*
12770          * Enlightened VMCS usage should be recommended and the host needs
12771          * to support eVMCS v1 or above. We can also disable eVMCS support
12772          * with module parameter.
12773          */
12774         if (enlightened_vmcs &&
12775             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
12776             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
12777             KVM_EVMCS_VERSION) {
12778                 int cpu;
12779
12780                 /* Check that we have assist pages on all online CPUs */
12781                 for_each_online_cpu(cpu) {
12782                         if (!hv_get_vp_assist_page(cpu)) {
12783                                 enlightened_vmcs = false;
12784                                 break;
12785                         }
12786                 }
12787
12788                 if (enlightened_vmcs) {
12789                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
12790                         static_branch_enable(&enable_evmcs);
12791                 }
12792         } else {
12793                 enlightened_vmcs = false;
12794         }
12795 #endif
12796
12797         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
12798                      __alignof__(struct vcpu_vmx), THIS_MODULE);
12799         if (r)
12800                 return r;
12801
12802 #ifdef CONFIG_KEXEC_CORE
12803         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
12804                            crash_vmclear_local_loaded_vmcss);
12805 #endif
12806
12807         return 0;
12808 }
12809
12810 static void __exit vmx_exit(void)
12811 {
12812 #ifdef CONFIG_KEXEC_CORE
12813         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
12814         synchronize_rcu();
12815 #endif
12816
12817         kvm_exit();
12818
12819 #if IS_ENABLED(CONFIG_HYPERV)
12820         if (static_branch_unlikely(&enable_evmcs)) {
12821                 int cpu;
12822                 struct hv_vp_assist_page *vp_ap;
12823                 /*
12824                  * Reset everything to support using non-enlightened VMCS
12825                  * access later (e.g. when we reload the module with
12826                  * enlightened_vmcs=0)
12827                  */
12828                 for_each_online_cpu(cpu) {
12829                         vp_ap = hv_get_vp_assist_page(cpu);
12830
12831                         if (!vp_ap)
12832                                 continue;
12833
12834                         vp_ap->current_nested_vmcs = 0;
12835                         vp_ap->enlighten_vmentry = 0;
12836                 }
12837
12838                 static_branch_disable(&enable_evmcs);
12839         }
12840 #endif
12841 }
12842
12843 module_init(vmx_init)
12844 module_exit(vmx_exit)