2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX),
66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
68 static bool __read_mostly enable_vpid = 1;
69 module_param_named(vpid, enable_vpid, bool, 0444);
71 static bool __read_mostly flexpriority_enabled = 1;
72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
74 static bool __read_mostly enable_ept = 1;
75 module_param_named(ept, enable_ept, bool, S_IRUGO);
77 static bool __read_mostly enable_unrestricted_guest = 1;
78 module_param_named(unrestricted_guest,
79 enable_unrestricted_guest, bool, S_IRUGO);
81 static bool __read_mostly enable_ept_ad_bits = 1;
82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
84 static bool __read_mostly emulate_invalid_guest_state = true;
85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
87 static bool __read_mostly vmm_exclusive = 1;
88 module_param(vmm_exclusive, bool, S_IRUGO);
90 static bool __read_mostly fasteoi = 1;
91 module_param(fasteoi, bool, S_IRUGO);
93 static bool __read_mostly enable_apicv = 1;
94 module_param(enable_apicv, bool, S_IRUGO);
96 static bool __read_mostly enable_shadow_vmcs = 1;
97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested = 0;
104 module_param(nested, bool, S_IRUGO);
106 static u64 __read_mostly host_xss;
108 static bool __read_mostly enable_pml = 1;
109 module_param_named(pml, enable_pml, bool, S_IRUGO);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
114 static int __read_mostly cpu_preemption_timer_multi;
115 static bool __read_mostly enable_preemption_timer = 1;
117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
122 #define KVM_VM_CR0_ALWAYS_ON \
123 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
124 #define KVM_CR4_GUEST_OWNED_BITS \
125 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
126 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
136 * Hyper-V requires all of these, so mark them as supported even though
137 * they are just treated the same as all-context.
139 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
140 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
141 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
143 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
146 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
147 * ple_gap: upper bound on the amount of time between two successive
148 * executions of PAUSE in a loop. Also indicate if ple enabled.
149 * According to test, this time is usually smaller than 128 cycles.
150 * ple_window: upper bound on the amount of time a guest is allowed to execute
151 * in a PAUSE loop. Tests indicate that most spinlocks are held for
152 * less than 2^12 cycles
153 * Time is measured based on a counter that runs at the same rate as the TSC,
154 * refer SDM volume 3b section 21.6.13 & 22.1.3.
156 #define KVM_VMX_DEFAULT_PLE_GAP 128
157 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
161 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
163 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
164 module_param(ple_gap, int, S_IRUGO);
166 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167 module_param(ple_window, int, S_IRUGO);
169 /* Default doubles per-vcpu window every exit. */
170 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
171 module_param(ple_window_grow, int, S_IRUGO);
173 /* Default resets per-vcpu window every exit to ple_window. */
174 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
175 module_param(ple_window_shrink, int, S_IRUGO);
177 /* Default is to compute the maximum so we can never overflow. */
178 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
180 module_param(ple_window_max, int, S_IRUGO);
182 extern const ulong vmx_return;
184 #define NR_AUTOLOAD_MSRS 8
185 #define VMCS02_POOL_SIZE 1
194 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
195 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
196 * loaded on this CPU (so we can clear them if the CPU goes down).
200 struct vmcs *shadow_vmcs;
203 struct list_head loaded_vmcss_on_cpu_link;
206 struct shared_msr_entry {
213 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
214 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
215 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
216 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
217 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
218 * More than one of these structures may exist, if L1 runs multiple L2 guests.
219 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
220 * underlying hardware which will be used to run L2.
221 * This structure is packed to ensure that its layout is identical across
222 * machines (necessary for live migration).
223 * If there are changes in this struct, VMCS12_REVISION must be changed.
225 typedef u64 natural_width;
226 struct __packed vmcs12 {
227 /* According to the Intel spec, a VMCS region must start with the
228 * following two fields. Then follow implementation-specific data.
233 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
234 u32 padding[7]; /* room for future expansion */
239 u64 vm_exit_msr_store_addr;
240 u64 vm_exit_msr_load_addr;
241 u64 vm_entry_msr_load_addr;
243 u64 virtual_apic_page_addr;
244 u64 apic_access_addr;
245 u64 posted_intr_desc_addr;
247 u64 eoi_exit_bitmap0;
248 u64 eoi_exit_bitmap1;
249 u64 eoi_exit_bitmap2;
250 u64 eoi_exit_bitmap3;
252 u64 guest_physical_address;
253 u64 vmcs_link_pointer;
254 u64 guest_ia32_debugctl;
257 u64 guest_ia32_perf_global_ctrl;
265 u64 host_ia32_perf_global_ctrl;
266 u64 padding64[8]; /* room for future expansion */
268 * To allow migration of L1 (complete with its L2 guests) between
269 * machines of different natural widths (32 or 64 bit), we cannot have
270 * unsigned long fields with no explict size. We use u64 (aliased
271 * natural_width) instead. Luckily, x86 is little-endian.
273 natural_width cr0_guest_host_mask;
274 natural_width cr4_guest_host_mask;
275 natural_width cr0_read_shadow;
276 natural_width cr4_read_shadow;
277 natural_width cr3_target_value0;
278 natural_width cr3_target_value1;
279 natural_width cr3_target_value2;
280 natural_width cr3_target_value3;
281 natural_width exit_qualification;
282 natural_width guest_linear_address;
283 natural_width guest_cr0;
284 natural_width guest_cr3;
285 natural_width guest_cr4;
286 natural_width guest_es_base;
287 natural_width guest_cs_base;
288 natural_width guest_ss_base;
289 natural_width guest_ds_base;
290 natural_width guest_fs_base;
291 natural_width guest_gs_base;
292 natural_width guest_ldtr_base;
293 natural_width guest_tr_base;
294 natural_width guest_gdtr_base;
295 natural_width guest_idtr_base;
296 natural_width guest_dr7;
297 natural_width guest_rsp;
298 natural_width guest_rip;
299 natural_width guest_rflags;
300 natural_width guest_pending_dbg_exceptions;
301 natural_width guest_sysenter_esp;
302 natural_width guest_sysenter_eip;
303 natural_width host_cr0;
304 natural_width host_cr3;
305 natural_width host_cr4;
306 natural_width host_fs_base;
307 natural_width host_gs_base;
308 natural_width host_tr_base;
309 natural_width host_gdtr_base;
310 natural_width host_idtr_base;
311 natural_width host_ia32_sysenter_esp;
312 natural_width host_ia32_sysenter_eip;
313 natural_width host_rsp;
314 natural_width host_rip;
315 natural_width paddingl[8]; /* room for future expansion */
316 u32 pin_based_vm_exec_control;
317 u32 cpu_based_vm_exec_control;
318 u32 exception_bitmap;
319 u32 page_fault_error_code_mask;
320 u32 page_fault_error_code_match;
321 u32 cr3_target_count;
322 u32 vm_exit_controls;
323 u32 vm_exit_msr_store_count;
324 u32 vm_exit_msr_load_count;
325 u32 vm_entry_controls;
326 u32 vm_entry_msr_load_count;
327 u32 vm_entry_intr_info_field;
328 u32 vm_entry_exception_error_code;
329 u32 vm_entry_instruction_len;
331 u32 secondary_vm_exec_control;
332 u32 vm_instruction_error;
334 u32 vm_exit_intr_info;
335 u32 vm_exit_intr_error_code;
336 u32 idt_vectoring_info_field;
337 u32 idt_vectoring_error_code;
338 u32 vm_exit_instruction_len;
339 u32 vmx_instruction_info;
346 u32 guest_ldtr_limit;
348 u32 guest_gdtr_limit;
349 u32 guest_idtr_limit;
350 u32 guest_es_ar_bytes;
351 u32 guest_cs_ar_bytes;
352 u32 guest_ss_ar_bytes;
353 u32 guest_ds_ar_bytes;
354 u32 guest_fs_ar_bytes;
355 u32 guest_gs_ar_bytes;
356 u32 guest_ldtr_ar_bytes;
357 u32 guest_tr_ar_bytes;
358 u32 guest_interruptibility_info;
359 u32 guest_activity_state;
360 u32 guest_sysenter_cs;
361 u32 host_ia32_sysenter_cs;
362 u32 vmx_preemption_timer_value;
363 u32 padding32[7]; /* room for future expansion */
364 u16 virtual_processor_id;
366 u16 guest_es_selector;
367 u16 guest_cs_selector;
368 u16 guest_ss_selector;
369 u16 guest_ds_selector;
370 u16 guest_fs_selector;
371 u16 guest_gs_selector;
372 u16 guest_ldtr_selector;
373 u16 guest_tr_selector;
374 u16 guest_intr_status;
375 u16 host_es_selector;
376 u16 host_cs_selector;
377 u16 host_ss_selector;
378 u16 host_ds_selector;
379 u16 host_fs_selector;
380 u16 host_gs_selector;
381 u16 host_tr_selector;
385 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
386 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
387 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
389 #define VMCS12_REVISION 0x11e57ed0
392 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
393 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
394 * current implementation, 4K are reserved to avoid future complications.
396 #define VMCS12_SIZE 0x1000
398 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
400 struct list_head list;
402 struct loaded_vmcs vmcs02;
406 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
407 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
410 /* Has the level1 guest done vmxon? */
414 /* The guest-physical address of the current VMCS L1 keeps for L2 */
416 /* The host-usable pointer to the above */
417 struct page *current_vmcs12_page;
418 struct vmcs12 *current_vmcs12;
420 * Cache of the guest's VMCS, existing outside of guest memory.
421 * Loaded from guest memory during VMPTRLD. Flushed to guest
422 * memory during VMXOFF, VMCLEAR, VMPTRLD.
424 struct vmcs12 *cached_vmcs12;
426 * Indicates if the shadow vmcs must be updated with the
427 * data hold by vmcs12
429 bool sync_shadow_vmcs;
431 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
432 struct list_head vmcs02_pool;
434 bool change_vmcs01_virtual_x2apic_mode;
435 /* L2 must run next, and mustn't decide to exit to L1. */
436 bool nested_run_pending;
438 * Guest pages referred to in vmcs02 with host-physical pointers, so
439 * we must keep them pinned while L2 runs.
441 struct page *apic_access_page;
442 struct page *virtual_apic_page;
443 struct page *pi_desc_page;
444 struct pi_desc *pi_desc;
448 unsigned long *msr_bitmap;
450 struct hrtimer preemption_timer;
451 bool preemption_timer_expired;
453 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
460 * We only store the "true" versions of the VMX capability MSRs. We
461 * generate the "non-true" versions by setting the must-be-1 bits
462 * according to the SDM.
464 u32 nested_vmx_procbased_ctls_low;
465 u32 nested_vmx_procbased_ctls_high;
466 u32 nested_vmx_secondary_ctls_low;
467 u32 nested_vmx_secondary_ctls_high;
468 u32 nested_vmx_pinbased_ctls_low;
469 u32 nested_vmx_pinbased_ctls_high;
470 u32 nested_vmx_exit_ctls_low;
471 u32 nested_vmx_exit_ctls_high;
472 u32 nested_vmx_entry_ctls_low;
473 u32 nested_vmx_entry_ctls_high;
474 u32 nested_vmx_misc_low;
475 u32 nested_vmx_misc_high;
476 u32 nested_vmx_ept_caps;
477 u32 nested_vmx_vpid_caps;
478 u64 nested_vmx_basic;
479 u64 nested_vmx_cr0_fixed0;
480 u64 nested_vmx_cr0_fixed1;
481 u64 nested_vmx_cr4_fixed0;
482 u64 nested_vmx_cr4_fixed1;
483 u64 nested_vmx_vmcs_enum;
486 #define POSTED_INTR_ON 0
487 #define POSTED_INTR_SN 1
489 /* Posted-Interrupt Descriptor */
491 u32 pir[8]; /* Posted interrupt requested */
494 /* bit 256 - Outstanding Notification */
496 /* bit 257 - Suppress Notification */
498 /* bit 271:258 - Reserved */
500 /* bit 279:272 - Notification Vector */
502 /* bit 287:280 - Reserved */
504 /* bit 319:288 - Notification Destination */
512 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
514 return test_and_set_bit(POSTED_INTR_ON,
515 (unsigned long *)&pi_desc->control);
518 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
520 return test_and_clear_bit(POSTED_INTR_ON,
521 (unsigned long *)&pi_desc->control);
524 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
526 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
529 static inline void pi_clear_sn(struct pi_desc *pi_desc)
531 return clear_bit(POSTED_INTR_SN,
532 (unsigned long *)&pi_desc->control);
535 static inline void pi_set_sn(struct pi_desc *pi_desc)
537 return set_bit(POSTED_INTR_SN,
538 (unsigned long *)&pi_desc->control);
541 static inline void pi_clear_on(struct pi_desc *pi_desc)
543 clear_bit(POSTED_INTR_ON,
544 (unsigned long *)&pi_desc->control);
547 static inline int pi_test_on(struct pi_desc *pi_desc)
549 return test_bit(POSTED_INTR_ON,
550 (unsigned long *)&pi_desc->control);
553 static inline int pi_test_sn(struct pi_desc *pi_desc)
555 return test_bit(POSTED_INTR_SN,
556 (unsigned long *)&pi_desc->control);
560 struct kvm_vcpu vcpu;
561 unsigned long host_rsp;
563 bool nmi_known_unmasked;
565 u32 idt_vectoring_info;
567 struct shared_msr_entry *guest_msrs;
570 unsigned long host_idt_base;
572 u64 msr_host_kernel_gs_base;
573 u64 msr_guest_kernel_gs_base;
575 u32 vm_entry_controls_shadow;
576 u32 vm_exit_controls_shadow;
578 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
579 * non-nested (L1) guest, it always points to vmcs01. For a nested
580 * guest (L2), it points to a different VMCS.
582 struct loaded_vmcs vmcs01;
583 struct loaded_vmcs *loaded_vmcs;
584 bool __launched; /* temporary, used in vmx_vcpu_run */
585 struct msr_autoload {
587 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
588 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
592 u16 fs_sel, gs_sel, ldt_sel;
596 int gs_ldt_reload_needed;
597 int fs_reload_needed;
598 u64 msr_host_bndcfgs;
599 unsigned long vmcs_host_cr4; /* May not match real cr4 */
604 struct kvm_segment segs[8];
607 u32 bitmask; /* 4 bits per segment (1 bit per field) */
608 struct kvm_save_segment {
616 bool emulation_required;
618 /* Support for vnmi-less CPUs */
619 int soft_vnmi_blocked;
621 s64 vnmi_blocked_time;
624 /* Posted interrupt descriptor */
625 struct pi_desc pi_desc;
627 /* Support for a guest hypervisor (nested VMX) */
628 struct nested_vmx nested;
630 /* Dynamic PLE window. */
632 bool ple_window_dirty;
634 /* Support for PML */
635 #define PML_ENTITY_NUM 512
638 /* apic deadline value in host tsc */
641 u64 current_tsc_ratio;
643 bool guest_pkru_valid;
648 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
649 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
650 * in msr_ia32_feature_control_valid_bits.
652 u64 msr_ia32_feature_control;
653 u64 msr_ia32_feature_control_valid_bits;
656 enum segment_cache_field {
665 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
667 return container_of(vcpu, struct vcpu_vmx, vcpu);
670 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
672 return &(to_vmx(vcpu)->pi_desc);
675 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
676 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
677 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
678 [number##_HIGH] = VMCS12_OFFSET(name)+4
681 static unsigned long shadow_read_only_fields[] = {
683 * We do NOT shadow fields that are modified when L0
684 * traps and emulates any vmx instruction (e.g. VMPTRLD,
685 * VMXON...) executed by L1.
686 * For example, VM_INSTRUCTION_ERROR is read
687 * by L1 if a vmx instruction fails (part of the error path).
688 * Note the code assumes this logic. If for some reason
689 * we start shadowing these fields then we need to
690 * force a shadow sync when L0 emulates vmx instructions
691 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
692 * by nested_vmx_failValid)
696 VM_EXIT_INSTRUCTION_LEN,
697 IDT_VECTORING_INFO_FIELD,
698 IDT_VECTORING_ERROR_CODE,
699 VM_EXIT_INTR_ERROR_CODE,
701 GUEST_LINEAR_ADDRESS,
702 GUEST_PHYSICAL_ADDRESS
704 static int max_shadow_read_only_fields =
705 ARRAY_SIZE(shadow_read_only_fields);
707 static unsigned long shadow_read_write_fields[] = {
714 GUEST_INTERRUPTIBILITY_INFO,
727 CPU_BASED_VM_EXEC_CONTROL,
728 VM_ENTRY_EXCEPTION_ERROR_CODE,
729 VM_ENTRY_INTR_INFO_FIELD,
730 VM_ENTRY_INSTRUCTION_LEN,
731 VM_ENTRY_EXCEPTION_ERROR_CODE,
737 static int max_shadow_read_write_fields =
738 ARRAY_SIZE(shadow_read_write_fields);
740 static const unsigned short vmcs_field_to_offset_table[] = {
741 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
742 FIELD(POSTED_INTR_NV, posted_intr_nv),
743 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
744 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
745 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
746 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
747 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
748 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
749 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
750 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
751 FIELD(GUEST_INTR_STATUS, guest_intr_status),
752 FIELD(HOST_ES_SELECTOR, host_es_selector),
753 FIELD(HOST_CS_SELECTOR, host_cs_selector),
754 FIELD(HOST_SS_SELECTOR, host_ss_selector),
755 FIELD(HOST_DS_SELECTOR, host_ds_selector),
756 FIELD(HOST_FS_SELECTOR, host_fs_selector),
757 FIELD(HOST_GS_SELECTOR, host_gs_selector),
758 FIELD(HOST_TR_SELECTOR, host_tr_selector),
759 FIELD64(IO_BITMAP_A, io_bitmap_a),
760 FIELD64(IO_BITMAP_B, io_bitmap_b),
761 FIELD64(MSR_BITMAP, msr_bitmap),
762 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
763 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
764 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
765 FIELD64(TSC_OFFSET, tsc_offset),
766 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
767 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
768 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
769 FIELD64(EPT_POINTER, ept_pointer),
770 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
771 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
772 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
773 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
774 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
775 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
776 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
777 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
778 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
779 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
780 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
781 FIELD64(GUEST_PDPTR0, guest_pdptr0),
782 FIELD64(GUEST_PDPTR1, guest_pdptr1),
783 FIELD64(GUEST_PDPTR2, guest_pdptr2),
784 FIELD64(GUEST_PDPTR3, guest_pdptr3),
785 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
786 FIELD64(HOST_IA32_PAT, host_ia32_pat),
787 FIELD64(HOST_IA32_EFER, host_ia32_efer),
788 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
789 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
790 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
791 FIELD(EXCEPTION_BITMAP, exception_bitmap),
792 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
793 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
794 FIELD(CR3_TARGET_COUNT, cr3_target_count),
795 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
796 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
797 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
798 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
799 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
800 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
801 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
802 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
803 FIELD(TPR_THRESHOLD, tpr_threshold),
804 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
805 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
806 FIELD(VM_EXIT_REASON, vm_exit_reason),
807 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
808 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
809 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
810 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
811 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
812 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
813 FIELD(GUEST_ES_LIMIT, guest_es_limit),
814 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
815 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
816 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
817 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
818 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
819 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
820 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
821 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
822 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
823 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
824 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
825 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
826 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
827 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
828 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
829 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
830 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
831 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
832 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
833 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
834 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
835 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
836 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
837 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
838 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
839 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
840 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
841 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
842 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
843 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
844 FIELD(EXIT_QUALIFICATION, exit_qualification),
845 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
846 FIELD(GUEST_CR0, guest_cr0),
847 FIELD(GUEST_CR3, guest_cr3),
848 FIELD(GUEST_CR4, guest_cr4),
849 FIELD(GUEST_ES_BASE, guest_es_base),
850 FIELD(GUEST_CS_BASE, guest_cs_base),
851 FIELD(GUEST_SS_BASE, guest_ss_base),
852 FIELD(GUEST_DS_BASE, guest_ds_base),
853 FIELD(GUEST_FS_BASE, guest_fs_base),
854 FIELD(GUEST_GS_BASE, guest_gs_base),
855 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
856 FIELD(GUEST_TR_BASE, guest_tr_base),
857 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
858 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
859 FIELD(GUEST_DR7, guest_dr7),
860 FIELD(GUEST_RSP, guest_rsp),
861 FIELD(GUEST_RIP, guest_rip),
862 FIELD(GUEST_RFLAGS, guest_rflags),
863 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
864 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
865 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
866 FIELD(HOST_CR0, host_cr0),
867 FIELD(HOST_CR3, host_cr3),
868 FIELD(HOST_CR4, host_cr4),
869 FIELD(HOST_FS_BASE, host_fs_base),
870 FIELD(HOST_GS_BASE, host_gs_base),
871 FIELD(HOST_TR_BASE, host_tr_base),
872 FIELD(HOST_GDTR_BASE, host_gdtr_base),
873 FIELD(HOST_IDTR_BASE, host_idtr_base),
874 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
875 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
876 FIELD(HOST_RSP, host_rsp),
877 FIELD(HOST_RIP, host_rip),
880 static inline short vmcs_field_to_offset(unsigned long field)
882 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
884 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
885 vmcs_field_to_offset_table[field] == 0)
888 return vmcs_field_to_offset_table[field];
891 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
893 return to_vmx(vcpu)->nested.cached_vmcs12;
896 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
898 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
899 if (is_error_page(page))
905 static void nested_release_page(struct page *page)
907 kvm_release_page_dirty(page);
910 static void nested_release_page_clean(struct page *page)
912 kvm_release_page_clean(page);
915 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
916 static u64 construct_eptp(unsigned long root_hpa);
917 static void kvm_cpu_vmxon(u64 addr);
918 static void kvm_cpu_vmxoff(void);
919 static bool vmx_xsaves_supported(void);
920 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
921 static void vmx_set_segment(struct kvm_vcpu *vcpu,
922 struct kvm_segment *var, int seg);
923 static void vmx_get_segment(struct kvm_vcpu *vcpu,
924 struct kvm_segment *var, int seg);
925 static bool guest_state_valid(struct kvm_vcpu *vcpu);
926 static u32 vmx_segment_access_rights(struct kvm_segment *var);
927 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
928 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
929 static int alloc_identity_pagetable(struct kvm *kvm);
931 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
932 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
934 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
935 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
937 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
938 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
941 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
942 * can find which vCPU should be waken up.
944 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
945 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
950 VMX_MSR_BITMAP_LEGACY,
951 VMX_MSR_BITMAP_LONGMODE,
952 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
953 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
954 VMX_MSR_BITMAP_LEGACY_X2APIC,
955 VMX_MSR_BITMAP_LONGMODE_X2APIC,
961 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
963 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
964 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
965 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
966 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
967 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
968 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
969 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
970 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
971 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
972 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
974 static bool cpu_has_load_ia32_efer;
975 static bool cpu_has_load_perf_global_ctrl;
977 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
978 static DEFINE_SPINLOCK(vmx_vpid_lock);
980 static struct vmcs_config {
985 u32 pin_based_exec_ctrl;
986 u32 cpu_based_exec_ctrl;
987 u32 cpu_based_2nd_exec_ctrl;
992 static struct vmx_capability {
997 #define VMX_SEGMENT_FIELD(seg) \
998 [VCPU_SREG_##seg] = { \
999 .selector = GUEST_##seg##_SELECTOR, \
1000 .base = GUEST_##seg##_BASE, \
1001 .limit = GUEST_##seg##_LIMIT, \
1002 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1005 static const struct kvm_vmx_segment_field {
1010 } kvm_vmx_segment_fields[] = {
1011 VMX_SEGMENT_FIELD(CS),
1012 VMX_SEGMENT_FIELD(DS),
1013 VMX_SEGMENT_FIELD(ES),
1014 VMX_SEGMENT_FIELD(FS),
1015 VMX_SEGMENT_FIELD(GS),
1016 VMX_SEGMENT_FIELD(SS),
1017 VMX_SEGMENT_FIELD(TR),
1018 VMX_SEGMENT_FIELD(LDTR),
1021 static u64 host_efer;
1023 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1026 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1027 * away by decrementing the array size.
1029 static const u32 vmx_msr_index[] = {
1030 #ifdef CONFIG_X86_64
1031 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1033 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1036 static inline bool is_exception_n(u32 intr_info, u8 vector)
1038 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1039 INTR_INFO_VALID_MASK)) ==
1040 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1043 static inline bool is_debug(u32 intr_info)
1045 return is_exception_n(intr_info, DB_VECTOR);
1048 static inline bool is_breakpoint(u32 intr_info)
1050 return is_exception_n(intr_info, BP_VECTOR);
1053 static inline bool is_page_fault(u32 intr_info)
1055 return is_exception_n(intr_info, PF_VECTOR);
1058 static inline bool is_no_device(u32 intr_info)
1060 return is_exception_n(intr_info, NM_VECTOR);
1063 static inline bool is_invalid_opcode(u32 intr_info)
1065 return is_exception_n(intr_info, UD_VECTOR);
1068 static inline bool is_external_interrupt(u32 intr_info)
1070 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1071 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1074 static inline bool is_machine_check(u32 intr_info)
1076 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1077 INTR_INFO_VALID_MASK)) ==
1078 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1083 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1088 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1093 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1098 return vmcs_config.cpu_based_exec_ctrl &
1099 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1104 return vmcs_config.cpu_based_2nd_exec_ctrl &
1105 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1110 return vmcs_config.cpu_based_2nd_exec_ctrl &
1111 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1116 return vmcs_config.cpu_based_2nd_exec_ctrl &
1117 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1122 return vmcs_config.cpu_based_2nd_exec_ctrl &
1123 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1127 * Comment's format: document - errata name - stepping - processor name.
1129 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1131 static u32 vmx_preemption_cpu_tfms[] = {
1132 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1134 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1138 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1140 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1143 * 320767.pdf - AAP86 - B1 -
1144 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1153 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1161 u32 eax = cpuid_eax(0x00000001), i;
1163 /* Clear the reserved bits */
1164 eax &= ~(0x3U << 14 | 0xfU << 28);
1165 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1166 if (eax == vmx_preemption_cpu_tfms[i])
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1174 return vmcs_config.pin_based_exec_ctrl &
1175 PIN_BASED_VMX_PREEMPTION_TIMER;
1178 static inline bool cpu_has_vmx_posted_intr(void)
1180 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1181 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1184 static inline bool cpu_has_vmx_apicv(void)
1186 return cpu_has_vmx_apic_register_virt() &&
1187 cpu_has_vmx_virtual_intr_delivery() &&
1188 cpu_has_vmx_posted_intr();
1191 static inline bool cpu_has_vmx_flexpriority(void)
1193 return cpu_has_vmx_tpr_shadow() &&
1194 cpu_has_vmx_virtualize_apic_accesses();
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1199 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1204 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1209 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1214 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1217 static inline bool cpu_has_vmx_ept_ad_bits(void)
1219 return vmx_capability.ept & VMX_EPT_AD_BIT;
1222 static inline bool cpu_has_vmx_invept_context(void)
1224 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1227 static inline bool cpu_has_vmx_invept_global(void)
1229 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1232 static inline bool cpu_has_vmx_invvpid_single(void)
1234 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1237 static inline bool cpu_has_vmx_invvpid_global(void)
1239 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1242 static inline bool cpu_has_vmx_ept(void)
1244 return vmcs_config.cpu_based_2nd_exec_ctrl &
1245 SECONDARY_EXEC_ENABLE_EPT;
1248 static inline bool cpu_has_vmx_unrestricted_guest(void)
1250 return vmcs_config.cpu_based_2nd_exec_ctrl &
1251 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1254 static inline bool cpu_has_vmx_ple(void)
1256 return vmcs_config.cpu_based_2nd_exec_ctrl &
1257 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1260 static inline bool cpu_has_vmx_basic_inout(void)
1262 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1265 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1267 return flexpriority_enabled && lapic_in_kernel(vcpu);
1270 static inline bool cpu_has_vmx_vpid(void)
1272 return vmcs_config.cpu_based_2nd_exec_ctrl &
1273 SECONDARY_EXEC_ENABLE_VPID;
1276 static inline bool cpu_has_vmx_rdtscp(void)
1278 return vmcs_config.cpu_based_2nd_exec_ctrl &
1279 SECONDARY_EXEC_RDTSCP;
1282 static inline bool cpu_has_vmx_invpcid(void)
1284 return vmcs_config.cpu_based_2nd_exec_ctrl &
1285 SECONDARY_EXEC_ENABLE_INVPCID;
1288 static inline bool cpu_has_virtual_nmis(void)
1290 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1293 static inline bool cpu_has_vmx_wbinvd_exit(void)
1295 return vmcs_config.cpu_based_2nd_exec_ctrl &
1296 SECONDARY_EXEC_WBINVD_EXITING;
1299 static inline bool cpu_has_vmx_shadow_vmcs(void)
1302 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1303 /* check if the cpu supports writing r/o exit information fields */
1304 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1307 return vmcs_config.cpu_based_2nd_exec_ctrl &
1308 SECONDARY_EXEC_SHADOW_VMCS;
1311 static inline bool cpu_has_vmx_pml(void)
1313 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1316 static inline bool cpu_has_vmx_tsc_scaling(void)
1318 return vmcs_config.cpu_based_2nd_exec_ctrl &
1319 SECONDARY_EXEC_TSC_SCALING;
1322 static inline bool report_flexpriority(void)
1324 return flexpriority_enabled;
1327 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1329 return vmcs12->cpu_based_vm_exec_control & bit;
1332 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1334 return (vmcs12->cpu_based_vm_exec_control &
1335 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1336 (vmcs12->secondary_vm_exec_control & bit);
1339 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1341 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1344 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1346 return vmcs12->pin_based_vm_exec_control &
1347 PIN_BASED_VMX_PREEMPTION_TIMER;
1350 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1352 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1355 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1357 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1358 vmx_xsaves_supported();
1361 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1363 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1366 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1368 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1371 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1373 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1376 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1378 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1381 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1383 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1386 static inline bool is_nmi(u32 intr_info)
1388 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1389 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1392 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1394 unsigned long exit_qualification);
1395 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1396 struct vmcs12 *vmcs12,
1397 u32 reason, unsigned long qualification);
1399 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1403 for (i = 0; i < vmx->nmsrs; ++i)
1404 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1409 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1415 } operand = { vpid, 0, gva };
1417 asm volatile (__ex(ASM_VMX_INVVPID)
1418 /* CF==1 or ZF==1 --> rc = -1 */
1419 "; ja 1f ; ud2 ; 1:"
1420 : : "a"(&operand), "c"(ext) : "cc", "memory");
1423 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1427 } operand = {eptp, gpa};
1429 asm volatile (__ex(ASM_VMX_INVEPT)
1430 /* CF==1 or ZF==1 --> rc = -1 */
1431 "; ja 1f ; ud2 ; 1:\n"
1432 : : "a" (&operand), "c" (ext) : "cc", "memory");
1435 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1439 i = __find_msr_index(vmx, msr);
1441 return &vmx->guest_msrs[i];
1445 static void vmcs_clear(struct vmcs *vmcs)
1447 u64 phys_addr = __pa(vmcs);
1450 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1451 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1454 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1458 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1460 vmcs_clear(loaded_vmcs->vmcs);
1461 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1462 vmcs_clear(loaded_vmcs->shadow_vmcs);
1463 loaded_vmcs->cpu = -1;
1464 loaded_vmcs->launched = 0;
1467 static void vmcs_load(struct vmcs *vmcs)
1469 u64 phys_addr = __pa(vmcs);
1472 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1473 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1476 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1480 #ifdef CONFIG_KEXEC_CORE
1482 * This bitmap is used to indicate whether the vmclear
1483 * operation is enabled on all cpus. All disabled by
1486 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1488 static inline void crash_enable_local_vmclear(int cpu)
1490 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1493 static inline void crash_disable_local_vmclear(int cpu)
1495 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1498 static inline int crash_local_vmclear_enabled(int cpu)
1500 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1503 static void crash_vmclear_local_loaded_vmcss(void)
1505 int cpu = raw_smp_processor_id();
1506 struct loaded_vmcs *v;
1508 if (!crash_local_vmclear_enabled(cpu))
1511 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1512 loaded_vmcss_on_cpu_link)
1513 vmcs_clear(v->vmcs);
1516 static inline void crash_enable_local_vmclear(int cpu) { }
1517 static inline void crash_disable_local_vmclear(int cpu) { }
1518 #endif /* CONFIG_KEXEC_CORE */
1520 static void __loaded_vmcs_clear(void *arg)
1522 struct loaded_vmcs *loaded_vmcs = arg;
1523 int cpu = raw_smp_processor_id();
1525 if (loaded_vmcs->cpu != cpu)
1526 return; /* vcpu migration can race with cpu offline */
1527 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1528 per_cpu(current_vmcs, cpu) = NULL;
1529 crash_disable_local_vmclear(cpu);
1530 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1533 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1534 * is before setting loaded_vmcs->vcpu to -1 which is done in
1535 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1536 * then adds the vmcs into percpu list before it is deleted.
1540 loaded_vmcs_init(loaded_vmcs);
1541 crash_enable_local_vmclear(cpu);
1544 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1546 int cpu = loaded_vmcs->cpu;
1549 smp_call_function_single(cpu,
1550 __loaded_vmcs_clear, loaded_vmcs, 1);
1553 static inline void vpid_sync_vcpu_single(int vpid)
1558 if (cpu_has_vmx_invvpid_single())
1559 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1562 static inline void vpid_sync_vcpu_global(void)
1564 if (cpu_has_vmx_invvpid_global())
1565 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1568 static inline void vpid_sync_context(int vpid)
1570 if (cpu_has_vmx_invvpid_single())
1571 vpid_sync_vcpu_single(vpid);
1573 vpid_sync_vcpu_global();
1576 static inline void ept_sync_global(void)
1578 if (cpu_has_vmx_invept_global())
1579 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1582 static inline void ept_sync_context(u64 eptp)
1585 if (cpu_has_vmx_invept_context())
1586 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1592 static __always_inline void vmcs_check16(unsigned long field)
1594 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1595 "16-bit accessor invalid for 64-bit field");
1596 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1597 "16-bit accessor invalid for 64-bit high field");
1598 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1599 "16-bit accessor invalid for 32-bit high field");
1600 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1601 "16-bit accessor invalid for natural width field");
1604 static __always_inline void vmcs_check32(unsigned long field)
1606 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1607 "32-bit accessor invalid for 16-bit field");
1608 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1609 "32-bit accessor invalid for natural width field");
1612 static __always_inline void vmcs_check64(unsigned long field)
1614 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1615 "64-bit accessor invalid for 16-bit field");
1616 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1617 "64-bit accessor invalid for 64-bit high field");
1618 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1619 "64-bit accessor invalid for 32-bit field");
1620 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1621 "64-bit accessor invalid for natural width field");
1624 static __always_inline void vmcs_checkl(unsigned long field)
1626 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1627 "Natural width accessor invalid for 16-bit field");
1628 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1629 "Natural width accessor invalid for 64-bit field");
1630 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1631 "Natural width accessor invalid for 64-bit high field");
1632 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1633 "Natural width accessor invalid for 32-bit field");
1636 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1638 unsigned long value;
1640 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1641 : "=a"(value) : "d"(field) : "cc");
1645 static __always_inline u16 vmcs_read16(unsigned long field)
1647 vmcs_check16(field);
1648 return __vmcs_readl(field);
1651 static __always_inline u32 vmcs_read32(unsigned long field)
1653 vmcs_check32(field);
1654 return __vmcs_readl(field);
1657 static __always_inline u64 vmcs_read64(unsigned long field)
1659 vmcs_check64(field);
1660 #ifdef CONFIG_X86_64
1661 return __vmcs_readl(field);
1663 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1667 static __always_inline unsigned long vmcs_readl(unsigned long field)
1670 return __vmcs_readl(field);
1673 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1675 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1676 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1680 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1684 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1685 : "=q"(error) : "a"(value), "d"(field) : "cc");
1686 if (unlikely(error))
1687 vmwrite_error(field, value);
1690 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1692 vmcs_check16(field);
1693 __vmcs_writel(field, value);
1696 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1698 vmcs_check32(field);
1699 __vmcs_writel(field, value);
1702 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1704 vmcs_check64(field);
1705 __vmcs_writel(field, value);
1706 #ifndef CONFIG_X86_64
1708 __vmcs_writel(field+1, value >> 32);
1712 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1715 __vmcs_writel(field, value);
1718 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1720 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1721 "vmcs_clear_bits does not support 64-bit fields");
1722 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1725 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1727 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1728 "vmcs_set_bits does not support 64-bit fields");
1729 __vmcs_writel(field, __vmcs_readl(field) | mask);
1732 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1734 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1737 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1739 vmcs_write32(VM_ENTRY_CONTROLS, val);
1740 vmx->vm_entry_controls_shadow = val;
1743 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1745 if (vmx->vm_entry_controls_shadow != val)
1746 vm_entry_controls_init(vmx, val);
1749 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1751 return vmx->vm_entry_controls_shadow;
1755 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1757 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1760 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1762 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1765 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1767 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1770 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1772 vmcs_write32(VM_EXIT_CONTROLS, val);
1773 vmx->vm_exit_controls_shadow = val;
1776 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1778 if (vmx->vm_exit_controls_shadow != val)
1779 vm_exit_controls_init(vmx, val);
1782 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1784 return vmx->vm_exit_controls_shadow;
1788 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1790 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1793 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1795 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1798 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1800 vmx->segment_cache.bitmask = 0;
1803 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1807 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1809 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1810 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1811 vmx->segment_cache.bitmask = 0;
1813 ret = vmx->segment_cache.bitmask & mask;
1814 vmx->segment_cache.bitmask |= mask;
1818 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1820 u16 *p = &vmx->segment_cache.seg[seg].selector;
1822 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1823 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1827 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1829 ulong *p = &vmx->segment_cache.seg[seg].base;
1831 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1832 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1836 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1838 u32 *p = &vmx->segment_cache.seg[seg].limit;
1840 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1841 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1845 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1847 u32 *p = &vmx->segment_cache.seg[seg].ar;
1849 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1850 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1854 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1858 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1859 (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1860 if ((vcpu->guest_debug &
1861 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1862 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1863 eb |= 1u << BP_VECTOR;
1864 if (to_vmx(vcpu)->rmode.vm86_active)
1867 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1868 if (vcpu->fpu_active)
1869 eb &= ~(1u << NM_VECTOR);
1871 /* When we are running a nested L2 guest and L1 specified for it a
1872 * certain exception bitmap, we must trap the same exceptions and pass
1873 * them to L1. When running L2, we will only handle the exceptions
1874 * specified above if L1 did not want them.
1876 if (is_guest_mode(vcpu))
1877 eb |= get_vmcs12(vcpu)->exception_bitmap;
1879 vmcs_write32(EXCEPTION_BITMAP, eb);
1882 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1883 unsigned long entry, unsigned long exit)
1885 vm_entry_controls_clearbit(vmx, entry);
1886 vm_exit_controls_clearbit(vmx, exit);
1889 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1892 struct msr_autoload *m = &vmx->msr_autoload;
1896 if (cpu_has_load_ia32_efer) {
1897 clear_atomic_switch_msr_special(vmx,
1898 VM_ENTRY_LOAD_IA32_EFER,
1899 VM_EXIT_LOAD_IA32_EFER);
1903 case MSR_CORE_PERF_GLOBAL_CTRL:
1904 if (cpu_has_load_perf_global_ctrl) {
1905 clear_atomic_switch_msr_special(vmx,
1906 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1907 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1913 for (i = 0; i < m->nr; ++i)
1914 if (m->guest[i].index == msr)
1920 m->guest[i] = m->guest[m->nr];
1921 m->host[i] = m->host[m->nr];
1922 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1923 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1926 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1927 unsigned long entry, unsigned long exit,
1928 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1929 u64 guest_val, u64 host_val)
1931 vmcs_write64(guest_val_vmcs, guest_val);
1932 vmcs_write64(host_val_vmcs, host_val);
1933 vm_entry_controls_setbit(vmx, entry);
1934 vm_exit_controls_setbit(vmx, exit);
1937 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1938 u64 guest_val, u64 host_val)
1941 struct msr_autoload *m = &vmx->msr_autoload;
1945 if (cpu_has_load_ia32_efer) {
1946 add_atomic_switch_msr_special(vmx,
1947 VM_ENTRY_LOAD_IA32_EFER,
1948 VM_EXIT_LOAD_IA32_EFER,
1951 guest_val, host_val);
1955 case MSR_CORE_PERF_GLOBAL_CTRL:
1956 if (cpu_has_load_perf_global_ctrl) {
1957 add_atomic_switch_msr_special(vmx,
1958 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1959 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1960 GUEST_IA32_PERF_GLOBAL_CTRL,
1961 HOST_IA32_PERF_GLOBAL_CTRL,
1962 guest_val, host_val);
1966 case MSR_IA32_PEBS_ENABLE:
1967 /* PEBS needs a quiescent period after being disabled (to write
1968 * a record). Disabling PEBS through VMX MSR swapping doesn't
1969 * provide that period, so a CPU could write host's record into
1972 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1975 for (i = 0; i < m->nr; ++i)
1976 if (m->guest[i].index == msr)
1979 if (i == NR_AUTOLOAD_MSRS) {
1980 printk_once(KERN_WARNING "Not enough msr switch entries. "
1981 "Can't add msr %x\n", msr);
1983 } else if (i == m->nr) {
1985 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1986 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1989 m->guest[i].index = msr;
1990 m->guest[i].value = guest_val;
1991 m->host[i].index = msr;
1992 m->host[i].value = host_val;
1995 static void reload_tss(void)
1998 * VT restores TR but not its size. Useless.
2000 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2001 struct desc_struct *descs;
2003 descs = (void *)gdt->address;
2004 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
2008 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2010 u64 guest_efer = vmx->vcpu.arch.efer;
2011 u64 ignore_bits = 0;
2015 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2016 * host CPUID is more efficient than testing guest CPUID
2017 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2019 if (boot_cpu_has(X86_FEATURE_SMEP))
2020 guest_efer |= EFER_NX;
2021 else if (!(guest_efer & EFER_NX))
2022 ignore_bits |= EFER_NX;
2026 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2028 ignore_bits |= EFER_SCE;
2029 #ifdef CONFIG_X86_64
2030 ignore_bits |= EFER_LMA | EFER_LME;
2031 /* SCE is meaningful only in long mode on Intel */
2032 if (guest_efer & EFER_LMA)
2033 ignore_bits &= ~(u64)EFER_SCE;
2036 clear_atomic_switch_msr(vmx, MSR_EFER);
2039 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2040 * On CPUs that support "load IA32_EFER", always switch EFER
2041 * atomically, since it's faster than switching it manually.
2043 if (cpu_has_load_ia32_efer ||
2044 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2045 if (!(guest_efer & EFER_LMA))
2046 guest_efer &= ~EFER_LME;
2047 if (guest_efer != host_efer)
2048 add_atomic_switch_msr(vmx, MSR_EFER,
2049 guest_efer, host_efer);
2052 guest_efer &= ~ignore_bits;
2053 guest_efer |= host_efer & ignore_bits;
2055 vmx->guest_msrs[efer_offset].data = guest_efer;
2056 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2062 static unsigned long segment_base(u16 selector)
2064 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2065 struct desc_struct *d;
2066 unsigned long table_base;
2069 if (!(selector & ~3))
2072 table_base = gdt->address;
2074 if (selector & 4) { /* from ldt */
2075 u16 ldt_selector = kvm_read_ldt();
2077 if (!(ldt_selector & ~3))
2080 table_base = segment_base(ldt_selector);
2082 d = (struct desc_struct *)(table_base + (selector & ~7));
2083 v = get_desc_base(d);
2084 #ifdef CONFIG_X86_64
2085 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2086 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2091 static inline unsigned long kvm_read_tr_base(void)
2094 asm("str %0" : "=g"(tr));
2095 return segment_base(tr);
2098 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2100 struct vcpu_vmx *vmx = to_vmx(vcpu);
2103 if (vmx->host_state.loaded)
2106 vmx->host_state.loaded = 1;
2108 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2109 * allow segment selectors with cpl > 0 or ti == 1.
2111 vmx->host_state.ldt_sel = kvm_read_ldt();
2112 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2113 savesegment(fs, vmx->host_state.fs_sel);
2114 if (!(vmx->host_state.fs_sel & 7)) {
2115 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2116 vmx->host_state.fs_reload_needed = 0;
2118 vmcs_write16(HOST_FS_SELECTOR, 0);
2119 vmx->host_state.fs_reload_needed = 1;
2121 savesegment(gs, vmx->host_state.gs_sel);
2122 if (!(vmx->host_state.gs_sel & 7))
2123 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2125 vmcs_write16(HOST_GS_SELECTOR, 0);
2126 vmx->host_state.gs_ldt_reload_needed = 1;
2129 #ifdef CONFIG_X86_64
2130 savesegment(ds, vmx->host_state.ds_sel);
2131 savesegment(es, vmx->host_state.es_sel);
2134 #ifdef CONFIG_X86_64
2135 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2136 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2138 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2139 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2142 #ifdef CONFIG_X86_64
2143 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2144 if (is_long_mode(&vmx->vcpu))
2145 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2147 if (boot_cpu_has(X86_FEATURE_MPX))
2148 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2149 for (i = 0; i < vmx->save_nmsrs; ++i)
2150 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2151 vmx->guest_msrs[i].data,
2152 vmx->guest_msrs[i].mask);
2155 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2157 if (!vmx->host_state.loaded)
2160 ++vmx->vcpu.stat.host_state_reload;
2161 vmx->host_state.loaded = 0;
2162 #ifdef CONFIG_X86_64
2163 if (is_long_mode(&vmx->vcpu))
2164 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2166 if (vmx->host_state.gs_ldt_reload_needed) {
2167 kvm_load_ldt(vmx->host_state.ldt_sel);
2168 #ifdef CONFIG_X86_64
2169 load_gs_index(vmx->host_state.gs_sel);
2171 loadsegment(gs, vmx->host_state.gs_sel);
2174 if (vmx->host_state.fs_reload_needed)
2175 loadsegment(fs, vmx->host_state.fs_sel);
2176 #ifdef CONFIG_X86_64
2177 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2178 loadsegment(ds, vmx->host_state.ds_sel);
2179 loadsegment(es, vmx->host_state.es_sel);
2183 #ifdef CONFIG_X86_64
2184 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2186 if (vmx->host_state.msr_host_bndcfgs)
2187 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2188 load_gdt(this_cpu_ptr(&host_gdt));
2191 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2194 __vmx_load_host_state(vmx);
2198 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2200 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2201 struct pi_desc old, new;
2204 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2205 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2206 !kvm_vcpu_apicv_active(vcpu))
2210 old.control = new.control = pi_desc->control;
2213 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2214 * are two possible cases:
2215 * 1. After running 'pre_block', context switch
2216 * happened. For this case, 'sn' was set in
2217 * vmx_vcpu_put(), so we need to clear it here.
2218 * 2. After running 'pre_block', we were blocked,
2219 * and woken up by some other guy. For this case,
2220 * we don't need to do anything, 'pi_post_block'
2221 * will do everything for us. However, we cannot
2222 * check whether it is case #1 or case #2 here
2223 * (maybe, not needed), so we also clear sn here,
2224 * I think it is not a big deal.
2226 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2227 if (vcpu->cpu != cpu) {
2228 dest = cpu_physical_id(cpu);
2230 if (x2apic_enabled())
2233 new.ndst = (dest << 8) & 0xFF00;
2236 /* set 'NV' to 'notification vector' */
2237 new.nv = POSTED_INTR_VECTOR;
2240 /* Allow posting non-urgent interrupts */
2242 } while (cmpxchg(&pi_desc->control, old.control,
2243 new.control) != old.control);
2246 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2248 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2249 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2253 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2254 * vcpu mutex is already taken.
2256 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2258 struct vcpu_vmx *vmx = to_vmx(vcpu);
2259 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2260 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2263 kvm_cpu_vmxon(phys_addr);
2264 else if (!already_loaded)
2265 loaded_vmcs_clear(vmx->loaded_vmcs);
2267 if (!already_loaded) {
2268 local_irq_disable();
2269 crash_disable_local_vmclear(cpu);
2272 * Read loaded_vmcs->cpu should be before fetching
2273 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2274 * See the comments in __loaded_vmcs_clear().
2278 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2279 &per_cpu(loaded_vmcss_on_cpu, cpu));
2280 crash_enable_local_vmclear(cpu);
2284 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2285 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2286 vmcs_load(vmx->loaded_vmcs->vmcs);
2289 if (!already_loaded) {
2290 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2291 unsigned long sysenter_esp;
2293 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2296 * Linux uses per-cpu TSS and GDT, so set these when switching
2299 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2300 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
2302 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2303 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2305 vmx->loaded_vmcs->cpu = cpu;
2308 /* Setup TSC multiplier */
2309 if (kvm_has_tsc_control &&
2310 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2311 decache_tsc_multiplier(vmx);
2313 vmx_vcpu_pi_load(vcpu, cpu);
2314 vmx->host_pkru = read_pkru();
2317 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2319 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2321 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2322 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2323 !kvm_vcpu_apicv_active(vcpu))
2326 /* Set SN when the vCPU is preempted */
2327 if (vcpu->preempted)
2331 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2333 vmx_vcpu_pi_put(vcpu);
2335 __vmx_load_host_state(to_vmx(vcpu));
2336 if (!vmm_exclusive) {
2337 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2343 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2347 if (vcpu->fpu_active)
2349 vcpu->fpu_active = 1;
2350 cr0 = vmcs_readl(GUEST_CR0);
2351 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2352 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2353 vmcs_writel(GUEST_CR0, cr0);
2354 update_exception_bitmap(vcpu);
2355 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2356 if (is_guest_mode(vcpu))
2357 vcpu->arch.cr0_guest_owned_bits &=
2358 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2359 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2362 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2365 * Return the cr0 value that a nested guest would read. This is a combination
2366 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2367 * its hypervisor (cr0_read_shadow).
2369 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2371 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2372 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2374 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2376 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2377 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2380 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2382 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2383 * set this *before* calling this function.
2385 vmx_decache_cr0_guest_bits(vcpu);
2386 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2387 update_exception_bitmap(vcpu);
2388 vcpu->arch.cr0_guest_owned_bits = 0;
2389 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2390 if (is_guest_mode(vcpu)) {
2392 * L1's specified read shadow might not contain the TS bit,
2393 * so now that we turned on shadowing of this bit, we need to
2394 * set this bit of the shadow. Like in nested_vmx_run we need
2395 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2396 * up-to-date here because we just decached cr0.TS (and we'll
2397 * only update vmcs12->guest_cr0 on nested exit).
2399 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2400 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2401 (vcpu->arch.cr0 & X86_CR0_TS);
2402 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2404 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2407 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2409 unsigned long rflags, save_rflags;
2411 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2412 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2413 rflags = vmcs_readl(GUEST_RFLAGS);
2414 if (to_vmx(vcpu)->rmode.vm86_active) {
2415 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2416 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2417 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2419 to_vmx(vcpu)->rflags = rflags;
2421 return to_vmx(vcpu)->rflags;
2424 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2426 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2427 to_vmx(vcpu)->rflags = rflags;
2428 if (to_vmx(vcpu)->rmode.vm86_active) {
2429 to_vmx(vcpu)->rmode.save_rflags = rflags;
2430 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2432 vmcs_writel(GUEST_RFLAGS, rflags);
2435 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2437 return to_vmx(vcpu)->guest_pkru;
2440 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2442 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2445 if (interruptibility & GUEST_INTR_STATE_STI)
2446 ret |= KVM_X86_SHADOW_INT_STI;
2447 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2448 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2453 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2455 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2456 u32 interruptibility = interruptibility_old;
2458 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2460 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2461 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2462 else if (mask & KVM_X86_SHADOW_INT_STI)
2463 interruptibility |= GUEST_INTR_STATE_STI;
2465 if ((interruptibility != interruptibility_old))
2466 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2469 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2473 rip = kvm_rip_read(vcpu);
2474 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2475 kvm_rip_write(vcpu, rip);
2477 /* skipping an emulated instruction also counts */
2478 vmx_set_interrupt_shadow(vcpu, 0);
2482 * KVM wants to inject page-faults which it got to the guest. This function
2483 * checks whether in a nested guest, we need to inject them to L1 or L2.
2485 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2487 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2489 if (!(vmcs12->exception_bitmap & (1u << nr)))
2492 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2493 vmcs_read32(VM_EXIT_INTR_INFO),
2494 vmcs_readl(EXIT_QUALIFICATION));
2498 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2499 bool has_error_code, u32 error_code,
2502 struct vcpu_vmx *vmx = to_vmx(vcpu);
2503 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2505 if (!reinject && is_guest_mode(vcpu) &&
2506 nested_vmx_check_exception(vcpu, nr))
2509 if (has_error_code) {
2510 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2511 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2514 if (vmx->rmode.vm86_active) {
2516 if (kvm_exception_is_soft(nr))
2517 inc_eip = vcpu->arch.event_exit_inst_len;
2518 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2519 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2523 if (kvm_exception_is_soft(nr)) {
2524 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2525 vmx->vcpu.arch.event_exit_inst_len);
2526 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2528 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2530 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2533 static bool vmx_rdtscp_supported(void)
2535 return cpu_has_vmx_rdtscp();
2538 static bool vmx_invpcid_supported(void)
2540 return cpu_has_vmx_invpcid() && enable_ept;
2544 * Swap MSR entry in host/guest MSR entry array.
2546 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2548 struct shared_msr_entry tmp;
2550 tmp = vmx->guest_msrs[to];
2551 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2552 vmx->guest_msrs[from] = tmp;
2555 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2557 unsigned long *msr_bitmap;
2559 if (is_guest_mode(vcpu))
2560 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2561 else if (cpu_has_secondary_exec_ctrls() &&
2562 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2563 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2564 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2565 if (is_long_mode(vcpu))
2566 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2568 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2570 if (is_long_mode(vcpu))
2571 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2573 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2576 if (is_long_mode(vcpu))
2577 msr_bitmap = vmx_msr_bitmap_longmode;
2579 msr_bitmap = vmx_msr_bitmap_legacy;
2582 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2586 * Set up the vmcs to automatically save and restore system
2587 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2588 * mode, as fiddling with msrs is very expensive.
2590 static void setup_msrs(struct vcpu_vmx *vmx)
2592 int save_nmsrs, index;
2595 #ifdef CONFIG_X86_64
2596 if (is_long_mode(&vmx->vcpu)) {
2597 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2599 move_msr_up(vmx, index, save_nmsrs++);
2600 index = __find_msr_index(vmx, MSR_LSTAR);
2602 move_msr_up(vmx, index, save_nmsrs++);
2603 index = __find_msr_index(vmx, MSR_CSTAR);
2605 move_msr_up(vmx, index, save_nmsrs++);
2606 index = __find_msr_index(vmx, MSR_TSC_AUX);
2607 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2608 move_msr_up(vmx, index, save_nmsrs++);
2610 * MSR_STAR is only needed on long mode guests, and only
2611 * if efer.sce is enabled.
2613 index = __find_msr_index(vmx, MSR_STAR);
2614 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2615 move_msr_up(vmx, index, save_nmsrs++);
2618 index = __find_msr_index(vmx, MSR_EFER);
2619 if (index >= 0 && update_transition_efer(vmx, index))
2620 move_msr_up(vmx, index, save_nmsrs++);
2622 vmx->save_nmsrs = save_nmsrs;
2624 if (cpu_has_vmx_msr_bitmap())
2625 vmx_set_msr_bitmap(&vmx->vcpu);
2629 * reads and returns guest's timestamp counter "register"
2630 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2631 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2633 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2635 u64 host_tsc, tsc_offset;
2638 tsc_offset = vmcs_read64(TSC_OFFSET);
2639 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2643 * writes 'offset' into guest's timestamp counter offset register
2645 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2647 if (is_guest_mode(vcpu)) {
2649 * We're here if L1 chose not to trap WRMSR to TSC. According
2650 * to the spec, this should set L1's TSC; The offset that L1
2651 * set for L2 remains unchanged, and still needs to be added
2652 * to the newly set TSC to get L2's TSC.
2654 struct vmcs12 *vmcs12;
2655 /* recalculate vmcs02.TSC_OFFSET: */
2656 vmcs12 = get_vmcs12(vcpu);
2657 vmcs_write64(TSC_OFFSET, offset +
2658 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2659 vmcs12->tsc_offset : 0));
2661 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2662 vmcs_read64(TSC_OFFSET), offset);
2663 vmcs_write64(TSC_OFFSET, offset);
2667 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2669 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2670 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2674 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2675 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2676 * all guests if the "nested" module option is off, and can also be disabled
2677 * for a single guest by disabling its VMX cpuid bit.
2679 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2681 return nested && guest_cpuid_has_vmx(vcpu);
2685 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2686 * returned for the various VMX controls MSRs when nested VMX is enabled.
2687 * The same values should also be used to verify that vmcs12 control fields are
2688 * valid during nested entry from L1 to L2.
2689 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2690 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2691 * bit in the high half is on if the corresponding bit in the control field
2692 * may be on. See also vmx_control_verify().
2694 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2697 * Note that as a general rule, the high half of the MSRs (bits in
2698 * the control fields which may be 1) should be initialized by the
2699 * intersection of the underlying hardware's MSR (i.e., features which
2700 * can be supported) and the list of features we want to expose -
2701 * because they are known to be properly supported in our code.
2702 * Also, usually, the low half of the MSRs (bits which must be 1) can
2703 * be set to 0, meaning that L1 may turn off any of these bits. The
2704 * reason is that if one of these bits is necessary, it will appear
2705 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2706 * fields of vmcs01 and vmcs02, will turn these bits off - and
2707 * nested_vmx_exit_handled() will not pass related exits to L1.
2708 * These rules have exceptions below.
2711 /* pin-based controls */
2712 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2713 vmx->nested.nested_vmx_pinbased_ctls_low,
2714 vmx->nested.nested_vmx_pinbased_ctls_high);
2715 vmx->nested.nested_vmx_pinbased_ctls_low |=
2716 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2717 vmx->nested.nested_vmx_pinbased_ctls_high &=
2718 PIN_BASED_EXT_INTR_MASK |
2719 PIN_BASED_NMI_EXITING |
2720 PIN_BASED_VIRTUAL_NMIS;
2721 vmx->nested.nested_vmx_pinbased_ctls_high |=
2722 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2723 PIN_BASED_VMX_PREEMPTION_TIMER;
2724 if (kvm_vcpu_apicv_active(&vmx->vcpu))
2725 vmx->nested.nested_vmx_pinbased_ctls_high |=
2726 PIN_BASED_POSTED_INTR;
2729 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2730 vmx->nested.nested_vmx_exit_ctls_low,
2731 vmx->nested.nested_vmx_exit_ctls_high);
2732 vmx->nested.nested_vmx_exit_ctls_low =
2733 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2735 vmx->nested.nested_vmx_exit_ctls_high &=
2736 #ifdef CONFIG_X86_64
2737 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2739 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2740 vmx->nested.nested_vmx_exit_ctls_high |=
2741 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2742 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2743 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2745 if (kvm_mpx_supported())
2746 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2748 /* We support free control of debug control saving. */
2749 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2751 /* entry controls */
2752 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2753 vmx->nested.nested_vmx_entry_ctls_low,
2754 vmx->nested.nested_vmx_entry_ctls_high);
2755 vmx->nested.nested_vmx_entry_ctls_low =
2756 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2757 vmx->nested.nested_vmx_entry_ctls_high &=
2758 #ifdef CONFIG_X86_64
2759 VM_ENTRY_IA32E_MODE |
2761 VM_ENTRY_LOAD_IA32_PAT;
2762 vmx->nested.nested_vmx_entry_ctls_high |=
2763 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2764 if (kvm_mpx_supported())
2765 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2767 /* We support free control of debug control loading. */
2768 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2770 /* cpu-based controls */
2771 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2772 vmx->nested.nested_vmx_procbased_ctls_low,
2773 vmx->nested.nested_vmx_procbased_ctls_high);
2774 vmx->nested.nested_vmx_procbased_ctls_low =
2775 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2776 vmx->nested.nested_vmx_procbased_ctls_high &=
2777 CPU_BASED_VIRTUAL_INTR_PENDING |
2778 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2779 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2780 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2781 CPU_BASED_CR3_STORE_EXITING |
2782 #ifdef CONFIG_X86_64
2783 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2785 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2786 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2787 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2788 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2789 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2791 * We can allow some features even when not supported by the
2792 * hardware. For example, L1 can specify an MSR bitmap - and we
2793 * can use it to avoid exits to L1 - even when L0 runs L2
2794 * without MSR bitmaps.
2796 vmx->nested.nested_vmx_procbased_ctls_high |=
2797 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2798 CPU_BASED_USE_MSR_BITMAPS;
2800 /* We support free control of CR3 access interception. */
2801 vmx->nested.nested_vmx_procbased_ctls_low &=
2802 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2804 /* secondary cpu-based controls */
2805 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2806 vmx->nested.nested_vmx_secondary_ctls_low,
2807 vmx->nested.nested_vmx_secondary_ctls_high);
2808 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2809 vmx->nested.nested_vmx_secondary_ctls_high &=
2810 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2811 SECONDARY_EXEC_RDTSCP |
2812 SECONDARY_EXEC_DESC |
2813 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2814 SECONDARY_EXEC_ENABLE_VPID |
2815 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2816 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2817 SECONDARY_EXEC_WBINVD_EXITING |
2818 SECONDARY_EXEC_XSAVES;
2821 /* nested EPT: emulate EPT also to L1 */
2822 vmx->nested.nested_vmx_secondary_ctls_high |=
2823 SECONDARY_EXEC_ENABLE_EPT;
2824 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2825 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2827 if (cpu_has_vmx_ept_execute_only())
2828 vmx->nested.nested_vmx_ept_caps |=
2829 VMX_EPT_EXECUTE_ONLY_BIT;
2830 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2831 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2832 VMX_EPT_EXTENT_CONTEXT_BIT;
2834 vmx->nested.nested_vmx_ept_caps = 0;
2837 * Old versions of KVM use the single-context version without
2838 * checking for support, so declare that it is supported even
2839 * though it is treated as global context. The alternative is
2840 * not failing the single-context invvpid, and it is worse.
2843 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2844 VMX_VPID_EXTENT_SUPPORTED_MASK;
2846 vmx->nested.nested_vmx_vpid_caps = 0;
2848 if (enable_unrestricted_guest)
2849 vmx->nested.nested_vmx_secondary_ctls_high |=
2850 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2852 /* miscellaneous data */
2853 rdmsr(MSR_IA32_VMX_MISC,
2854 vmx->nested.nested_vmx_misc_low,
2855 vmx->nested.nested_vmx_misc_high);
2856 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2857 vmx->nested.nested_vmx_misc_low |=
2858 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2859 VMX_MISC_ACTIVITY_HLT;
2860 vmx->nested.nested_vmx_misc_high = 0;
2863 * This MSR reports some information about VMX support. We
2864 * should return information about the VMX we emulate for the
2865 * guest, and the VMCS structure we give it - not about the
2866 * VMX support of the underlying hardware.
2868 vmx->nested.nested_vmx_basic =
2870 VMX_BASIC_TRUE_CTLS |
2871 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2872 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2874 if (cpu_has_vmx_basic_inout())
2875 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2878 * These MSRs specify bits which the guest must keep fixed on
2879 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2880 * We picked the standard core2 setting.
2882 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2883 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2884 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2885 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2887 /* These MSRs specify bits which the guest must keep fixed off. */
2888 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2889 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2891 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2892 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2896 * if fixed0[i] == 1: val[i] must be 1
2897 * if fixed1[i] == 0: val[i] must be 0
2899 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2901 return ((val & fixed1) | fixed0) == val;
2904 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2906 return fixed_bits_valid(control, low, high);
2909 static inline u64 vmx_control_msr(u32 low, u32 high)
2911 return low | ((u64)high << 32);
2914 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2919 return (superset | subset) == superset;
2922 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2924 const u64 feature_and_reserved =
2925 /* feature (except bit 48; see below) */
2926 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2928 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2929 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2931 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2935 * KVM does not emulate a version of VMX that constrains physical
2936 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2938 if (data & BIT_ULL(48))
2941 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2942 vmx_basic_vmcs_revision_id(data))
2945 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2948 vmx->nested.nested_vmx_basic = data;
2953 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2958 switch (msr_index) {
2959 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2960 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2961 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2963 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2964 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2965 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2967 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2968 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2969 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2971 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2972 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2973 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2975 case MSR_IA32_VMX_PROCBASED_CTLS2:
2976 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2977 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2983 supported = vmx_control_msr(*lowp, *highp);
2985 /* Check must-be-1 bits are still 1. */
2986 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2989 /* Check must-be-0 bits are still 0. */
2990 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2994 *highp = data >> 32;
2998 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3000 const u64 feature_and_reserved_bits =
3002 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3003 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3005 GENMASK_ULL(13, 9) | BIT_ULL(31);
3008 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3009 vmx->nested.nested_vmx_misc_high);
3011 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3014 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3015 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3016 vmx_misc_preemption_timer_rate(data) !=
3017 vmx_misc_preemption_timer_rate(vmx_misc))
3020 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3023 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3026 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3029 vmx->nested.nested_vmx_misc_low = data;
3030 vmx->nested.nested_vmx_misc_high = data >> 32;
3034 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3036 u64 vmx_ept_vpid_cap;
3038 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3039 vmx->nested.nested_vmx_vpid_caps);
3041 /* Every bit is either reserved or a feature bit. */
3042 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3045 vmx->nested.nested_vmx_ept_caps = data;
3046 vmx->nested.nested_vmx_vpid_caps = data >> 32;
3050 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3054 switch (msr_index) {
3055 case MSR_IA32_VMX_CR0_FIXED0:
3056 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3058 case MSR_IA32_VMX_CR4_FIXED0:
3059 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3066 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3067 * must be 1 in the restored value.
3069 if (!is_bitwise_subset(data, *msr, -1ULL))
3077 * Called when userspace is restoring VMX MSRs.
3079 * Returns 0 on success, non-0 otherwise.
3081 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3083 struct vcpu_vmx *vmx = to_vmx(vcpu);
3085 switch (msr_index) {
3086 case MSR_IA32_VMX_BASIC:
3087 return vmx_restore_vmx_basic(vmx, data);
3088 case MSR_IA32_VMX_PINBASED_CTLS:
3089 case MSR_IA32_VMX_PROCBASED_CTLS:
3090 case MSR_IA32_VMX_EXIT_CTLS:
3091 case MSR_IA32_VMX_ENTRY_CTLS:
3093 * The "non-true" VMX capability MSRs are generated from the
3094 * "true" MSRs, so we do not support restoring them directly.
3096 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3097 * should restore the "true" MSRs with the must-be-1 bits
3098 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3099 * DEFAULT SETTINGS".
3102 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3103 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3104 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3105 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3106 case MSR_IA32_VMX_PROCBASED_CTLS2:
3107 return vmx_restore_control_msr(vmx, msr_index, data);
3108 case MSR_IA32_VMX_MISC:
3109 return vmx_restore_vmx_misc(vmx, data);
3110 case MSR_IA32_VMX_CR0_FIXED0:
3111 case MSR_IA32_VMX_CR4_FIXED0:
3112 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3113 case MSR_IA32_VMX_CR0_FIXED1:
3114 case MSR_IA32_VMX_CR4_FIXED1:
3116 * These MSRs are generated based on the vCPU's CPUID, so we
3117 * do not support restoring them directly.
3120 case MSR_IA32_VMX_EPT_VPID_CAP:
3121 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3122 case MSR_IA32_VMX_VMCS_ENUM:
3123 vmx->nested.nested_vmx_vmcs_enum = data;
3127 * The rest of the VMX capability MSRs do not support restore.
3133 /* Returns 0 on success, non-0 otherwise. */
3134 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3136 struct vcpu_vmx *vmx = to_vmx(vcpu);
3138 switch (msr_index) {
3139 case MSR_IA32_VMX_BASIC:
3140 *pdata = vmx->nested.nested_vmx_basic;
3142 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3143 case MSR_IA32_VMX_PINBASED_CTLS:
3144 *pdata = vmx_control_msr(
3145 vmx->nested.nested_vmx_pinbased_ctls_low,
3146 vmx->nested.nested_vmx_pinbased_ctls_high);
3147 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3148 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3150 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3151 case MSR_IA32_VMX_PROCBASED_CTLS:
3152 *pdata = vmx_control_msr(
3153 vmx->nested.nested_vmx_procbased_ctls_low,
3154 vmx->nested.nested_vmx_procbased_ctls_high);
3155 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3156 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3158 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3159 case MSR_IA32_VMX_EXIT_CTLS:
3160 *pdata = vmx_control_msr(
3161 vmx->nested.nested_vmx_exit_ctls_low,
3162 vmx->nested.nested_vmx_exit_ctls_high);
3163 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3164 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3166 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3167 case MSR_IA32_VMX_ENTRY_CTLS:
3168 *pdata = vmx_control_msr(
3169 vmx->nested.nested_vmx_entry_ctls_low,
3170 vmx->nested.nested_vmx_entry_ctls_high);
3171 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3172 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3174 case MSR_IA32_VMX_MISC:
3175 *pdata = vmx_control_msr(
3176 vmx->nested.nested_vmx_misc_low,
3177 vmx->nested.nested_vmx_misc_high);
3179 case MSR_IA32_VMX_CR0_FIXED0:
3180 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3182 case MSR_IA32_VMX_CR0_FIXED1:
3183 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3185 case MSR_IA32_VMX_CR4_FIXED0:
3186 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3188 case MSR_IA32_VMX_CR4_FIXED1:
3189 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3191 case MSR_IA32_VMX_VMCS_ENUM:
3192 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3194 case MSR_IA32_VMX_PROCBASED_CTLS2:
3195 *pdata = vmx_control_msr(
3196 vmx->nested.nested_vmx_secondary_ctls_low,
3197 vmx->nested.nested_vmx_secondary_ctls_high);
3199 case MSR_IA32_VMX_EPT_VPID_CAP:
3200 *pdata = vmx->nested.nested_vmx_ept_caps |
3201 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3210 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3213 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3215 return !(val & ~valid_bits);
3219 * Reads an msr value (of 'msr_index') into 'pdata'.
3220 * Returns 0 on success, non-0 otherwise.
3221 * Assumes vcpu_load() was already called.
3223 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3225 struct shared_msr_entry *msr;
3227 switch (msr_info->index) {
3228 #ifdef CONFIG_X86_64
3230 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3233 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3235 case MSR_KERNEL_GS_BASE:
3236 vmx_load_host_state(to_vmx(vcpu));
3237 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3241 return kvm_get_msr_common(vcpu, msr_info);
3243 msr_info->data = guest_read_tsc(vcpu);
3245 case MSR_IA32_SYSENTER_CS:
3246 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3248 case MSR_IA32_SYSENTER_EIP:
3249 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3251 case MSR_IA32_SYSENTER_ESP:
3252 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3254 case MSR_IA32_BNDCFGS:
3255 if (!kvm_mpx_supported())
3257 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3259 case MSR_IA32_MCG_EXT_CTL:
3260 if (!msr_info->host_initiated &&
3261 !(to_vmx(vcpu)->msr_ia32_feature_control &
3262 FEATURE_CONTROL_LMCE))
3264 msr_info->data = vcpu->arch.mcg_ext_ctl;
3266 case MSR_IA32_FEATURE_CONTROL:
3267 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3269 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3270 if (!nested_vmx_allowed(vcpu))
3272 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3274 if (!vmx_xsaves_supported())
3276 msr_info->data = vcpu->arch.ia32_xss;
3279 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3281 /* Otherwise falls through */
3283 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3285 msr_info->data = msr->data;
3288 return kvm_get_msr_common(vcpu, msr_info);
3294 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3297 * Writes msr value into into the appropriate "register".
3298 * Returns 0 on success, non-0 otherwise.
3299 * Assumes vcpu_load() was already called.
3301 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3303 struct vcpu_vmx *vmx = to_vmx(vcpu);
3304 struct shared_msr_entry *msr;
3306 u32 msr_index = msr_info->index;
3307 u64 data = msr_info->data;
3309 switch (msr_index) {
3311 ret = kvm_set_msr_common(vcpu, msr_info);
3313 #ifdef CONFIG_X86_64
3315 vmx_segment_cache_clear(vmx);
3316 vmcs_writel(GUEST_FS_BASE, data);
3319 vmx_segment_cache_clear(vmx);
3320 vmcs_writel(GUEST_GS_BASE, data);
3322 case MSR_KERNEL_GS_BASE:
3323 vmx_load_host_state(vmx);
3324 vmx->msr_guest_kernel_gs_base = data;
3327 case MSR_IA32_SYSENTER_CS:
3328 vmcs_write32(GUEST_SYSENTER_CS, data);
3330 case MSR_IA32_SYSENTER_EIP:
3331 vmcs_writel(GUEST_SYSENTER_EIP, data);
3333 case MSR_IA32_SYSENTER_ESP:
3334 vmcs_writel(GUEST_SYSENTER_ESP, data);
3336 case MSR_IA32_BNDCFGS:
3337 if (!kvm_mpx_supported())
3339 vmcs_write64(GUEST_BNDCFGS, data);
3342 kvm_write_tsc(vcpu, msr_info);
3344 case MSR_IA32_CR_PAT:
3345 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3346 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3348 vmcs_write64(GUEST_IA32_PAT, data);
3349 vcpu->arch.pat = data;
3352 ret = kvm_set_msr_common(vcpu, msr_info);
3354 case MSR_IA32_TSC_ADJUST:
3355 ret = kvm_set_msr_common(vcpu, msr_info);
3357 case MSR_IA32_MCG_EXT_CTL:
3358 if ((!msr_info->host_initiated &&
3359 !(to_vmx(vcpu)->msr_ia32_feature_control &
3360 FEATURE_CONTROL_LMCE)) ||
3361 (data & ~MCG_EXT_CTL_LMCE_EN))
3363 vcpu->arch.mcg_ext_ctl = data;
3365 case MSR_IA32_FEATURE_CONTROL:
3366 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3367 (to_vmx(vcpu)->msr_ia32_feature_control &
3368 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3370 vmx->msr_ia32_feature_control = data;
3371 if (msr_info->host_initiated && data == 0)
3372 vmx_leave_nested(vcpu);
3374 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3375 if (!msr_info->host_initiated)
3376 return 1; /* they are read-only */
3377 if (!nested_vmx_allowed(vcpu))
3379 return vmx_set_vmx_msr(vcpu, msr_index, data);
3381 if (!vmx_xsaves_supported())
3384 * The only supported bit as of Skylake is bit 8, but
3385 * it is not supported on KVM.
3389 vcpu->arch.ia32_xss = data;
3390 if (vcpu->arch.ia32_xss != host_xss)
3391 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3392 vcpu->arch.ia32_xss, host_xss);
3394 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3397 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3399 /* Check reserved bit, higher 32 bits should be zero */
3400 if ((data >> 32) != 0)
3402 /* Otherwise falls through */
3404 msr = find_msr_entry(vmx, msr_index);
3406 u64 old_msr_data = msr->data;
3408 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3410 ret = kvm_set_shared_msr(msr->index, msr->data,
3414 msr->data = old_msr_data;
3418 ret = kvm_set_msr_common(vcpu, msr_info);
3424 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3426 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3429 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3432 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3434 case VCPU_EXREG_PDPTR:
3436 ept_save_pdptrs(vcpu);
3443 static __init int cpu_has_kvm_support(void)
3445 return cpu_has_vmx();
3448 static __init int vmx_disabled_by_bios(void)
3452 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3453 if (msr & FEATURE_CONTROL_LOCKED) {
3454 /* launched w/ TXT and VMX disabled */
3455 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3458 /* launched w/o TXT and VMX only enabled w/ TXT */
3459 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3460 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3461 && !tboot_enabled()) {
3462 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3463 "activate TXT before enabling KVM\n");
3466 /* launched w/o TXT and VMX disabled */
3467 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3468 && !tboot_enabled())
3475 static void kvm_cpu_vmxon(u64 addr)
3477 intel_pt_handle_vmx(1);
3479 asm volatile (ASM_VMX_VMXON_RAX
3480 : : "a"(&addr), "m"(addr)
3484 static int hardware_enable(void)
3486 int cpu = raw_smp_processor_id();
3487 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3490 if (cr4_read_shadow() & X86_CR4_VMXE)
3493 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3494 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3495 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3498 * Now we can enable the vmclear operation in kdump
3499 * since the loaded_vmcss_on_cpu list on this cpu
3500 * has been initialized.
3502 * Though the cpu is not in VMX operation now, there
3503 * is no problem to enable the vmclear operation
3504 * for the loaded_vmcss_on_cpu list is empty!
3506 crash_enable_local_vmclear(cpu);
3508 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3510 test_bits = FEATURE_CONTROL_LOCKED;
3511 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3512 if (tboot_enabled())
3513 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3515 if ((old & test_bits) != test_bits) {
3516 /* enable and lock */
3517 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3519 cr4_set_bits(X86_CR4_VMXE);
3521 if (vmm_exclusive) {
3522 kvm_cpu_vmxon(phys_addr);
3526 native_store_gdt(this_cpu_ptr(&host_gdt));
3531 static void vmclear_local_loaded_vmcss(void)
3533 int cpu = raw_smp_processor_id();
3534 struct loaded_vmcs *v, *n;
3536 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3537 loaded_vmcss_on_cpu_link)
3538 __loaded_vmcs_clear(v);
3542 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3545 static void kvm_cpu_vmxoff(void)
3547 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3549 intel_pt_handle_vmx(0);
3552 static void hardware_disable(void)
3554 if (vmm_exclusive) {
3555 vmclear_local_loaded_vmcss();
3558 cr4_clear_bits(X86_CR4_VMXE);
3561 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3562 u32 msr, u32 *result)
3564 u32 vmx_msr_low, vmx_msr_high;
3565 u32 ctl = ctl_min | ctl_opt;
3567 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3569 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3570 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3572 /* Ensure minimum (required) set of control bits are supported. */
3580 static __init bool allow_1_setting(u32 msr, u32 ctl)
3582 u32 vmx_msr_low, vmx_msr_high;
3584 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3585 return vmx_msr_high & ctl;
3588 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3590 u32 vmx_msr_low, vmx_msr_high;
3591 u32 min, opt, min2, opt2;
3592 u32 _pin_based_exec_control = 0;
3593 u32 _cpu_based_exec_control = 0;
3594 u32 _cpu_based_2nd_exec_control = 0;
3595 u32 _vmexit_control = 0;
3596 u32 _vmentry_control = 0;
3598 min = CPU_BASED_HLT_EXITING |
3599 #ifdef CONFIG_X86_64
3600 CPU_BASED_CR8_LOAD_EXITING |
3601 CPU_BASED_CR8_STORE_EXITING |
3603 CPU_BASED_CR3_LOAD_EXITING |
3604 CPU_BASED_CR3_STORE_EXITING |
3605 CPU_BASED_USE_IO_BITMAPS |
3606 CPU_BASED_MOV_DR_EXITING |
3607 CPU_BASED_USE_TSC_OFFSETING |
3608 CPU_BASED_MWAIT_EXITING |
3609 CPU_BASED_MONITOR_EXITING |
3610 CPU_BASED_INVLPG_EXITING |
3611 CPU_BASED_RDPMC_EXITING;
3613 opt = CPU_BASED_TPR_SHADOW |
3614 CPU_BASED_USE_MSR_BITMAPS |
3615 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3616 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3617 &_cpu_based_exec_control) < 0)
3619 #ifdef CONFIG_X86_64
3620 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3621 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3622 ~CPU_BASED_CR8_STORE_EXITING;
3624 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3626 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3627 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3628 SECONDARY_EXEC_WBINVD_EXITING |
3629 SECONDARY_EXEC_ENABLE_VPID |
3630 SECONDARY_EXEC_ENABLE_EPT |
3631 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3632 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3633 SECONDARY_EXEC_RDTSCP |
3634 SECONDARY_EXEC_ENABLE_INVPCID |
3635 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3636 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3637 SECONDARY_EXEC_SHADOW_VMCS |
3638 SECONDARY_EXEC_XSAVES |
3639 SECONDARY_EXEC_ENABLE_PML |
3640 SECONDARY_EXEC_TSC_SCALING;
3641 if (adjust_vmx_controls(min2, opt2,
3642 MSR_IA32_VMX_PROCBASED_CTLS2,
3643 &_cpu_based_2nd_exec_control) < 0)
3646 #ifndef CONFIG_X86_64
3647 if (!(_cpu_based_2nd_exec_control &
3648 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3649 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3652 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3653 _cpu_based_2nd_exec_control &= ~(
3654 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3655 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3656 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3658 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3659 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3661 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3662 CPU_BASED_CR3_STORE_EXITING |
3663 CPU_BASED_INVLPG_EXITING);
3664 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3665 vmx_capability.ept, vmx_capability.vpid);
3668 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3669 #ifdef CONFIG_X86_64
3670 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3672 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3673 VM_EXIT_CLEAR_BNDCFGS;
3674 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3675 &_vmexit_control) < 0)
3678 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3679 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3680 PIN_BASED_VMX_PREEMPTION_TIMER;
3681 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3682 &_pin_based_exec_control) < 0)
3685 if (cpu_has_broken_vmx_preemption_timer())
3686 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3687 if (!(_cpu_based_2nd_exec_control &
3688 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3689 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3691 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3692 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3693 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3694 &_vmentry_control) < 0)
3697 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3699 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3700 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3703 #ifdef CONFIG_X86_64
3704 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3705 if (vmx_msr_high & (1u<<16))
3709 /* Require Write-Back (WB) memory type for VMCS accesses. */
3710 if (((vmx_msr_high >> 18) & 15) != 6)
3713 vmcs_conf->size = vmx_msr_high & 0x1fff;
3714 vmcs_conf->order = get_order(vmcs_conf->size);
3715 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3716 vmcs_conf->revision_id = vmx_msr_low;
3718 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3719 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3720 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3721 vmcs_conf->vmexit_ctrl = _vmexit_control;
3722 vmcs_conf->vmentry_ctrl = _vmentry_control;
3724 cpu_has_load_ia32_efer =
3725 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3726 VM_ENTRY_LOAD_IA32_EFER)
3727 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3728 VM_EXIT_LOAD_IA32_EFER);
3730 cpu_has_load_perf_global_ctrl =
3731 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3732 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3733 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3734 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3737 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3738 * but due to errata below it can't be used. Workaround is to use
3739 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3741 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3746 * BC86,AAY89,BD102 (model 44)
3750 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3751 switch (boot_cpu_data.x86_model) {
3757 cpu_has_load_perf_global_ctrl = false;
3758 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3759 "does not work properly. Using workaround\n");
3766 if (boot_cpu_has(X86_FEATURE_XSAVES))
3767 rdmsrl(MSR_IA32_XSS, host_xss);
3772 static struct vmcs *alloc_vmcs_cpu(int cpu)
3774 int node = cpu_to_node(cpu);
3778 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3781 vmcs = page_address(pages);
3782 memset(vmcs, 0, vmcs_config.size);
3783 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3787 static struct vmcs *alloc_vmcs(void)
3789 return alloc_vmcs_cpu(raw_smp_processor_id());
3792 static void free_vmcs(struct vmcs *vmcs)
3794 free_pages((unsigned long)vmcs, vmcs_config.order);
3798 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3800 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3802 if (!loaded_vmcs->vmcs)
3804 loaded_vmcs_clear(loaded_vmcs);
3805 free_vmcs(loaded_vmcs->vmcs);
3806 loaded_vmcs->vmcs = NULL;
3807 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3810 static void free_kvm_area(void)
3814 for_each_possible_cpu(cpu) {
3815 free_vmcs(per_cpu(vmxarea, cpu));
3816 per_cpu(vmxarea, cpu) = NULL;
3820 static void init_vmcs_shadow_fields(void)
3824 /* No checks for read only fields yet */
3826 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3827 switch (shadow_read_write_fields[i]) {
3829 if (!kvm_mpx_supported())
3837 shadow_read_write_fields[j] =
3838 shadow_read_write_fields[i];
3841 max_shadow_read_write_fields = j;
3843 /* shadowed fields guest access without vmexit */
3844 for (i = 0; i < max_shadow_read_write_fields; i++) {
3845 clear_bit(shadow_read_write_fields[i],
3846 vmx_vmwrite_bitmap);
3847 clear_bit(shadow_read_write_fields[i],
3850 for (i = 0; i < max_shadow_read_only_fields; i++)
3851 clear_bit(shadow_read_only_fields[i],
3855 static __init int alloc_kvm_area(void)
3859 for_each_possible_cpu(cpu) {
3862 vmcs = alloc_vmcs_cpu(cpu);
3868 per_cpu(vmxarea, cpu) = vmcs;
3873 static bool emulation_required(struct kvm_vcpu *vcpu)
3875 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3878 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3879 struct kvm_segment *save)
3881 if (!emulate_invalid_guest_state) {
3883 * CS and SS RPL should be equal during guest entry according
3884 * to VMX spec, but in reality it is not always so. Since vcpu
3885 * is in the middle of the transition from real mode to
3886 * protected mode it is safe to assume that RPL 0 is a good
3889 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3890 save->selector &= ~SEGMENT_RPL_MASK;
3891 save->dpl = save->selector & SEGMENT_RPL_MASK;
3894 vmx_set_segment(vcpu, save, seg);
3897 static void enter_pmode(struct kvm_vcpu *vcpu)
3899 unsigned long flags;
3900 struct vcpu_vmx *vmx = to_vmx(vcpu);
3903 * Update real mode segment cache. It may be not up-to-date if sement
3904 * register was written while vcpu was in a guest mode.
3906 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3907 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3908 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3909 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3910 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3911 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3913 vmx->rmode.vm86_active = 0;
3915 vmx_segment_cache_clear(vmx);
3917 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3919 flags = vmcs_readl(GUEST_RFLAGS);
3920 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3921 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3922 vmcs_writel(GUEST_RFLAGS, flags);
3924 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3925 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3927 update_exception_bitmap(vcpu);
3929 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3930 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3931 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3932 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3933 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3934 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3937 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3939 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3940 struct kvm_segment var = *save;
3943 if (seg == VCPU_SREG_CS)
3946 if (!emulate_invalid_guest_state) {
3947 var.selector = var.base >> 4;
3948 var.base = var.base & 0xffff0;
3958 if (save->base & 0xf)
3959 printk_once(KERN_WARNING "kvm: segment base is not "
3960 "paragraph aligned when entering "
3961 "protected mode (seg=%d)", seg);
3964 vmcs_write16(sf->selector, var.selector);
3965 vmcs_write32(sf->base, var.base);
3966 vmcs_write32(sf->limit, var.limit);
3967 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3970 static void enter_rmode(struct kvm_vcpu *vcpu)
3972 unsigned long flags;
3973 struct vcpu_vmx *vmx = to_vmx(vcpu);
3975 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3976 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3977 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3978 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3979 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3980 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3981 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3983 vmx->rmode.vm86_active = 1;
3986 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3987 * vcpu. Warn the user that an update is overdue.
3989 if (!vcpu->kvm->arch.tss_addr)
3990 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3991 "called before entering vcpu\n");
3993 vmx_segment_cache_clear(vmx);
3995 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3996 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3997 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3999 flags = vmcs_readl(GUEST_RFLAGS);
4000 vmx->rmode.save_rflags = flags;
4002 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4004 vmcs_writel(GUEST_RFLAGS, flags);
4005 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4006 update_exception_bitmap(vcpu);
4008 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4009 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4010 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4011 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4012 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4013 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4015 kvm_mmu_reset_context(vcpu);
4018 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4020 struct vcpu_vmx *vmx = to_vmx(vcpu);
4021 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4027 * Force kernel_gs_base reloading before EFER changes, as control
4028 * of this msr depends on is_long_mode().
4030 vmx_load_host_state(to_vmx(vcpu));
4031 vcpu->arch.efer = efer;
4032 if (efer & EFER_LMA) {
4033 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4036 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4038 msr->data = efer & ~EFER_LME;
4043 #ifdef CONFIG_X86_64
4045 static void enter_lmode(struct kvm_vcpu *vcpu)
4049 vmx_segment_cache_clear(to_vmx(vcpu));
4051 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4052 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4053 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4055 vmcs_write32(GUEST_TR_AR_BYTES,
4056 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4057 | VMX_AR_TYPE_BUSY_64_TSS);
4059 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4062 static void exit_lmode(struct kvm_vcpu *vcpu)
4064 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4065 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4070 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4072 vpid_sync_context(vpid);
4074 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4076 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
4080 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4082 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4085 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4087 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4089 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4090 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4093 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4095 if (enable_ept && is_paging(vcpu))
4096 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4097 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4100 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4102 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4104 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4105 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4108 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4110 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4112 if (!test_bit(VCPU_EXREG_PDPTR,
4113 (unsigned long *)&vcpu->arch.regs_dirty))
4116 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4117 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4118 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4119 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4120 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4124 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4126 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4128 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4129 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4130 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4131 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4132 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4135 __set_bit(VCPU_EXREG_PDPTR,
4136 (unsigned long *)&vcpu->arch.regs_avail);
4137 __set_bit(VCPU_EXREG_PDPTR,
4138 (unsigned long *)&vcpu->arch.regs_dirty);
4141 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4143 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4144 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4145 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4147 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4148 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4149 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4150 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4152 return fixed_bits_valid(val, fixed0, fixed1);
4155 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4157 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4158 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4160 return fixed_bits_valid(val, fixed0, fixed1);
4163 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4165 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4166 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4168 return fixed_bits_valid(val, fixed0, fixed1);
4171 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4172 #define nested_guest_cr4_valid nested_cr4_valid
4173 #define nested_host_cr4_valid nested_cr4_valid
4175 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4177 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4179 struct kvm_vcpu *vcpu)
4181 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4182 vmx_decache_cr3(vcpu);
4183 if (!(cr0 & X86_CR0_PG)) {
4184 /* From paging/starting to nonpaging */
4185 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4186 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4187 (CPU_BASED_CR3_LOAD_EXITING |
4188 CPU_BASED_CR3_STORE_EXITING));
4189 vcpu->arch.cr0 = cr0;
4190 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4191 } else if (!is_paging(vcpu)) {
4192 /* From nonpaging to paging */
4193 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4194 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4195 ~(CPU_BASED_CR3_LOAD_EXITING |
4196 CPU_BASED_CR3_STORE_EXITING));
4197 vcpu->arch.cr0 = cr0;
4198 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4201 if (!(cr0 & X86_CR0_WP))
4202 *hw_cr0 &= ~X86_CR0_WP;
4205 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4207 struct vcpu_vmx *vmx = to_vmx(vcpu);
4208 unsigned long hw_cr0;
4210 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4211 if (enable_unrestricted_guest)
4212 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4214 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4216 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4219 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4223 #ifdef CONFIG_X86_64
4224 if (vcpu->arch.efer & EFER_LME) {
4225 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4227 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4233 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4235 if (!vcpu->fpu_active)
4236 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
4238 vmcs_writel(CR0_READ_SHADOW, cr0);
4239 vmcs_writel(GUEST_CR0, hw_cr0);
4240 vcpu->arch.cr0 = cr0;
4242 /* depends on vcpu->arch.cr0 to be set to a new value */
4243 vmx->emulation_required = emulation_required(vcpu);
4246 static u64 construct_eptp(unsigned long root_hpa)
4250 /* TODO write the value reading from MSR */
4251 eptp = VMX_EPT_DEFAULT_MT |
4252 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4253 if (enable_ept_ad_bits)
4254 eptp |= VMX_EPT_AD_ENABLE_BIT;
4255 eptp |= (root_hpa & PAGE_MASK);
4260 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4262 unsigned long guest_cr3;
4267 eptp = construct_eptp(cr3);
4268 vmcs_write64(EPT_POINTER, eptp);
4269 if (is_paging(vcpu) || is_guest_mode(vcpu))
4270 guest_cr3 = kvm_read_cr3(vcpu);
4272 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4273 ept_load_pdptrs(vcpu);
4276 vmx_flush_tlb(vcpu);
4277 vmcs_writel(GUEST_CR3, guest_cr3);
4280 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4283 * Pass through host's Machine Check Enable value to hw_cr4, which
4284 * is in force while we are in guest mode. Do not let guests control
4285 * this bit, even if host CR4.MCE == 0.
4287 unsigned long hw_cr4 =
4288 (cr4_read_shadow() & X86_CR4_MCE) |
4289 (cr4 & ~X86_CR4_MCE) |
4290 (to_vmx(vcpu)->rmode.vm86_active ?
4291 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4293 if (cr4 & X86_CR4_VMXE) {
4295 * To use VMXON (and later other VMX instructions), a guest
4296 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4297 * So basically the check on whether to allow nested VMX
4300 if (!nested_vmx_allowed(vcpu))
4304 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4307 vcpu->arch.cr4 = cr4;
4309 if (!is_paging(vcpu)) {
4310 hw_cr4 &= ~X86_CR4_PAE;
4311 hw_cr4 |= X86_CR4_PSE;
4312 } else if (!(cr4 & X86_CR4_PAE)) {
4313 hw_cr4 &= ~X86_CR4_PAE;
4317 if (!enable_unrestricted_guest && !is_paging(vcpu))
4319 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4320 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4321 * to be manually disabled when guest switches to non-paging
4324 * If !enable_unrestricted_guest, the CPU is always running
4325 * with CR0.PG=1 and CR4 needs to be modified.
4326 * If enable_unrestricted_guest, the CPU automatically
4327 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4329 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4331 vmcs_writel(CR4_READ_SHADOW, cr4);
4332 vmcs_writel(GUEST_CR4, hw_cr4);
4336 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4337 struct kvm_segment *var, int seg)
4339 struct vcpu_vmx *vmx = to_vmx(vcpu);
4342 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4343 *var = vmx->rmode.segs[seg];
4344 if (seg == VCPU_SREG_TR
4345 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4347 var->base = vmx_read_guest_seg_base(vmx, seg);
4348 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4351 var->base = vmx_read_guest_seg_base(vmx, seg);
4352 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4353 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4354 ar = vmx_read_guest_seg_ar(vmx, seg);
4355 var->unusable = (ar >> 16) & 1;
4356 var->type = ar & 15;
4357 var->s = (ar >> 4) & 1;
4358 var->dpl = (ar >> 5) & 3;
4360 * Some userspaces do not preserve unusable property. Since usable
4361 * segment has to be present according to VMX spec we can use present
4362 * property to amend userspace bug by making unusable segment always
4363 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4364 * segment as unusable.
4366 var->present = !var->unusable;
4367 var->avl = (ar >> 12) & 1;
4368 var->l = (ar >> 13) & 1;
4369 var->db = (ar >> 14) & 1;
4370 var->g = (ar >> 15) & 1;
4373 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4375 struct kvm_segment s;
4377 if (to_vmx(vcpu)->rmode.vm86_active) {
4378 vmx_get_segment(vcpu, &s, seg);
4381 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4384 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4386 struct vcpu_vmx *vmx = to_vmx(vcpu);
4388 if (unlikely(vmx->rmode.vm86_active))
4391 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4392 return VMX_AR_DPL(ar);
4396 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4400 if (var->unusable || !var->present)
4403 ar = var->type & 15;
4404 ar |= (var->s & 1) << 4;
4405 ar |= (var->dpl & 3) << 5;
4406 ar |= (var->present & 1) << 7;
4407 ar |= (var->avl & 1) << 12;
4408 ar |= (var->l & 1) << 13;
4409 ar |= (var->db & 1) << 14;
4410 ar |= (var->g & 1) << 15;
4416 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4417 struct kvm_segment *var, int seg)
4419 struct vcpu_vmx *vmx = to_vmx(vcpu);
4420 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4422 vmx_segment_cache_clear(vmx);
4424 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4425 vmx->rmode.segs[seg] = *var;
4426 if (seg == VCPU_SREG_TR)
4427 vmcs_write16(sf->selector, var->selector);
4429 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4433 vmcs_writel(sf->base, var->base);
4434 vmcs_write32(sf->limit, var->limit);
4435 vmcs_write16(sf->selector, var->selector);
4438 * Fix the "Accessed" bit in AR field of segment registers for older
4440 * IA32 arch specifies that at the time of processor reset the
4441 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4442 * is setting it to 0 in the userland code. This causes invalid guest
4443 * state vmexit when "unrestricted guest" mode is turned on.
4444 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4445 * tree. Newer qemu binaries with that qemu fix would not need this
4448 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4449 var->type |= 0x1; /* Accessed */
4451 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4454 vmx->emulation_required = emulation_required(vcpu);
4457 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4459 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4461 *db = (ar >> 14) & 1;
4462 *l = (ar >> 13) & 1;
4465 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4467 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4468 dt->address = vmcs_readl(GUEST_IDTR_BASE);
4471 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4473 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4474 vmcs_writel(GUEST_IDTR_BASE, dt->address);
4477 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4479 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4480 dt->address = vmcs_readl(GUEST_GDTR_BASE);
4483 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4485 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4486 vmcs_writel(GUEST_GDTR_BASE, dt->address);
4489 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4491 struct kvm_segment var;
4494 vmx_get_segment(vcpu, &var, seg);
4496 if (seg == VCPU_SREG_CS)
4498 ar = vmx_segment_access_rights(&var);
4500 if (var.base != (var.selector << 4))
4502 if (var.limit != 0xffff)
4510 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4512 struct kvm_segment cs;
4513 unsigned int cs_rpl;
4515 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4516 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4520 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4524 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4525 if (cs.dpl > cs_rpl)
4528 if (cs.dpl != cs_rpl)
4534 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4538 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4540 struct kvm_segment ss;
4541 unsigned int ss_rpl;
4543 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4544 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4548 if (ss.type != 3 && ss.type != 7)
4552 if (ss.dpl != ss_rpl) /* DPL != RPL */
4560 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4562 struct kvm_segment var;
4565 vmx_get_segment(vcpu, &var, seg);
4566 rpl = var.selector & SEGMENT_RPL_MASK;
4574 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4575 if (var.dpl < rpl) /* DPL < RPL */
4579 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4585 static bool tr_valid(struct kvm_vcpu *vcpu)
4587 struct kvm_segment tr;
4589 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4593 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4595 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4603 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4605 struct kvm_segment ldtr;
4607 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4611 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4621 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4623 struct kvm_segment cs, ss;
4625 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4626 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4628 return ((cs.selector & SEGMENT_RPL_MASK) ==
4629 (ss.selector & SEGMENT_RPL_MASK));
4633 * Check if guest state is valid. Returns true if valid, false if
4635 * We assume that registers are always usable
4637 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4639 if (enable_unrestricted_guest)
4642 /* real mode guest state checks */
4643 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4644 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4646 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4648 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4650 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4652 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4654 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4657 /* protected mode guest state checks */
4658 if (!cs_ss_rpl_check(vcpu))
4660 if (!code_segment_valid(vcpu))
4662 if (!stack_segment_valid(vcpu))
4664 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4666 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4668 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4670 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4672 if (!tr_valid(vcpu))
4674 if (!ldtr_valid(vcpu))
4678 * - Add checks on RIP
4679 * - Add checks on RFLAGS
4685 static int init_rmode_tss(struct kvm *kvm)
4691 idx = srcu_read_lock(&kvm->srcu);
4692 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4693 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4696 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4697 r = kvm_write_guest_page(kvm, fn++, &data,
4698 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4701 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4704 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4708 r = kvm_write_guest_page(kvm, fn, &data,
4709 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4712 srcu_read_unlock(&kvm->srcu, idx);
4716 static int init_rmode_identity_map(struct kvm *kvm)
4719 kvm_pfn_t identity_map_pfn;
4725 /* Protect kvm->arch.ept_identity_pagetable_done. */
4726 mutex_lock(&kvm->slots_lock);
4728 if (likely(kvm->arch.ept_identity_pagetable_done))
4731 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4733 r = alloc_identity_pagetable(kvm);
4737 idx = srcu_read_lock(&kvm->srcu);
4738 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4741 /* Set up identity-mapping pagetable for EPT in real mode */
4742 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4743 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4744 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4745 r = kvm_write_guest_page(kvm, identity_map_pfn,
4746 &tmp, i * sizeof(tmp), sizeof(tmp));
4750 kvm->arch.ept_identity_pagetable_done = true;
4753 srcu_read_unlock(&kvm->srcu, idx);
4756 mutex_unlock(&kvm->slots_lock);
4760 static void seg_setup(int seg)
4762 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4765 vmcs_write16(sf->selector, 0);
4766 vmcs_writel(sf->base, 0);
4767 vmcs_write32(sf->limit, 0xffff);
4769 if (seg == VCPU_SREG_CS)
4770 ar |= 0x08; /* code segment */
4772 vmcs_write32(sf->ar_bytes, ar);
4775 static int alloc_apic_access_page(struct kvm *kvm)
4780 mutex_lock(&kvm->slots_lock);
4781 if (kvm->arch.apic_access_page_done)
4783 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4784 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4788 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4789 if (is_error_page(page)) {
4795 * Do not pin the page in memory, so that memory hot-unplug
4796 * is able to migrate it.
4799 kvm->arch.apic_access_page_done = true;
4801 mutex_unlock(&kvm->slots_lock);
4805 static int alloc_identity_pagetable(struct kvm *kvm)
4807 /* Called with kvm->slots_lock held. */
4811 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4813 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4814 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4819 static int allocate_vpid(void)
4825 spin_lock(&vmx_vpid_lock);
4826 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4827 if (vpid < VMX_NR_VPIDS)
4828 __set_bit(vpid, vmx_vpid_bitmap);
4831 spin_unlock(&vmx_vpid_lock);
4835 static void free_vpid(int vpid)
4837 if (!enable_vpid || vpid == 0)
4839 spin_lock(&vmx_vpid_lock);
4840 __clear_bit(vpid, vmx_vpid_bitmap);
4841 spin_unlock(&vmx_vpid_lock);
4844 #define MSR_TYPE_R 1
4845 #define MSR_TYPE_W 2
4846 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4849 int f = sizeof(unsigned long);
4851 if (!cpu_has_vmx_msr_bitmap())
4855 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4856 * have the write-low and read-high bitmap offsets the wrong way round.
4857 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4859 if (msr <= 0x1fff) {
4860 if (type & MSR_TYPE_R)
4862 __clear_bit(msr, msr_bitmap + 0x000 / f);
4864 if (type & MSR_TYPE_W)
4866 __clear_bit(msr, msr_bitmap + 0x800 / f);
4868 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4870 if (type & MSR_TYPE_R)
4872 __clear_bit(msr, msr_bitmap + 0x400 / f);
4874 if (type & MSR_TYPE_W)
4876 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4882 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4883 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4885 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4886 unsigned long *msr_bitmap_nested,
4889 int f = sizeof(unsigned long);
4891 if (!cpu_has_vmx_msr_bitmap()) {
4897 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4898 * have the write-low and read-high bitmap offsets the wrong way round.
4899 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4901 if (msr <= 0x1fff) {
4902 if (type & MSR_TYPE_R &&
4903 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4905 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4907 if (type & MSR_TYPE_W &&
4908 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4910 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4912 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4914 if (type & MSR_TYPE_R &&
4915 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4917 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4919 if (type & MSR_TYPE_W &&
4920 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4922 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4927 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4930 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4931 msr, MSR_TYPE_R | MSR_TYPE_W);
4932 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4933 msr, MSR_TYPE_R | MSR_TYPE_W);
4936 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4939 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4941 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4944 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4946 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4951 static bool vmx_get_enable_apicv(void)
4953 return enable_apicv;
4956 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4958 struct vcpu_vmx *vmx = to_vmx(vcpu);
4963 if (vmx->nested.pi_desc &&
4964 vmx->nested.pi_pending) {
4965 vmx->nested.pi_pending = false;
4966 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4969 max_irr = find_last_bit(
4970 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4975 vapic_page = kmap(vmx->nested.virtual_apic_page);
4976 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4977 kunmap(vmx->nested.virtual_apic_page);
4979 status = vmcs_read16(GUEST_INTR_STATUS);
4980 if ((u8)max_irr > ((u8)status & 0xff)) {
4982 status |= (u8)max_irr;
4983 vmcs_write16(GUEST_INTR_STATUS, status);
4988 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4991 if (vcpu->mode == IN_GUEST_MODE) {
4992 struct vcpu_vmx *vmx = to_vmx(vcpu);
4995 * Currently, we don't support urgent interrupt,
4996 * all interrupts are recognized as non-urgent
4997 * interrupt, so we cannot post interrupts when
5000 * If the vcpu is in guest mode, it means it is
5001 * running instead of being scheduled out and
5002 * waiting in the run queue, and that's the only
5003 * case when 'SN' is set currently, warning if
5006 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
5008 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
5009 POSTED_INTR_VECTOR);
5016 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5019 struct vcpu_vmx *vmx = to_vmx(vcpu);
5021 if (is_guest_mode(vcpu) &&
5022 vector == vmx->nested.posted_intr_nv) {
5023 /* the PIR and ON have been set by L1. */
5024 kvm_vcpu_trigger_posted_interrupt(vcpu);
5026 * If a posted intr is not recognized by hardware,
5027 * we will accomplish it in the next vmentry.
5029 vmx->nested.pi_pending = true;
5030 kvm_make_request(KVM_REQ_EVENT, vcpu);
5036 * Send interrupt to vcpu via posted interrupt way.
5037 * 1. If target vcpu is running(non-root mode), send posted interrupt
5038 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5039 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5040 * interrupt from PIR in next vmentry.
5042 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5044 struct vcpu_vmx *vmx = to_vmx(vcpu);
5047 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5051 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5054 /* If a previous notification has sent the IPI, nothing to do. */
5055 if (pi_test_and_set_on(&vmx->pi_desc))
5058 if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5059 kvm_vcpu_kick(vcpu);
5063 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5064 * will not change in the lifetime of the guest.
5065 * Note that host-state that does change is set elsewhere. E.g., host-state
5066 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5068 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5073 unsigned long cr0, cr4;
5076 WARN_ON(cr0 & X86_CR0_TS);
5077 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
5078 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
5080 /* Save the most likely value for this task's CR4 in the VMCS. */
5081 cr4 = cr4_read_shadow();
5082 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5083 vmx->host_state.vmcs_host_cr4 = cr4;
5085 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
5086 #ifdef CONFIG_X86_64
5088 * Load null selectors, so we can avoid reloading them in
5089 * __vmx_load_host_state(), in case userspace uses the null selectors
5090 * too (the expected case).
5092 vmcs_write16(HOST_DS_SELECTOR, 0);
5093 vmcs_write16(HOST_ES_SELECTOR, 0);
5095 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5096 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5098 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5099 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5101 native_store_idt(&dt);
5102 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
5103 vmx->host_idt_base = dt.address;
5105 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5107 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5108 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5109 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5110 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5112 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5113 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5114 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5118 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5120 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5122 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5123 if (is_guest_mode(&vmx->vcpu))
5124 vmx->vcpu.arch.cr4_guest_owned_bits &=
5125 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5126 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5129 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5131 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5133 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5134 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5135 /* Enable the preemption timer dynamically */
5136 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5137 return pin_based_exec_ctrl;
5140 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5142 struct vcpu_vmx *vmx = to_vmx(vcpu);
5144 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5145 if (cpu_has_secondary_exec_ctrls()) {
5146 if (kvm_vcpu_apicv_active(vcpu))
5147 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5148 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5149 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5151 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5152 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5153 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5156 if (cpu_has_vmx_msr_bitmap())
5157 vmx_set_msr_bitmap(vcpu);
5160 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5162 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5164 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5165 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5167 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5168 exec_control &= ~CPU_BASED_TPR_SHADOW;
5169 #ifdef CONFIG_X86_64
5170 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5171 CPU_BASED_CR8_LOAD_EXITING;
5175 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5176 CPU_BASED_CR3_LOAD_EXITING |
5177 CPU_BASED_INVLPG_EXITING;
5178 return exec_control;
5181 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5183 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5184 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5185 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5187 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5189 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5190 enable_unrestricted_guest = 0;
5191 /* Enable INVPCID for non-ept guests may cause performance regression. */
5192 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5194 if (!enable_unrestricted_guest)
5195 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5197 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5198 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5199 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5200 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5201 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5202 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5204 We can NOT enable shadow_vmcs here because we don't have yet
5207 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5210 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5212 return exec_control;
5215 static void ept_set_mmio_spte_mask(void)
5218 * EPT Misconfigurations can be generated if the value of bits 2:0
5219 * of an EPT paging-structure entry is 110b (write/execute).
5221 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5224 #define VMX_XSS_EXIT_BITMAP 0
5226 * Sets up the vmcs for emulated real mode.
5228 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5230 #ifdef CONFIG_X86_64
5236 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5237 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5239 if (enable_shadow_vmcs) {
5240 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5241 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5243 if (cpu_has_vmx_msr_bitmap())
5244 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5246 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5249 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5250 vmx->hv_deadline_tsc = -1;
5252 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5254 if (cpu_has_secondary_exec_ctrls()) {
5255 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5256 vmx_secondary_exec_control(vmx));
5259 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5260 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5261 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5262 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5263 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5265 vmcs_write16(GUEST_INTR_STATUS, 0);
5267 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5268 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5272 vmcs_write32(PLE_GAP, ple_gap);
5273 vmx->ple_window = ple_window;
5274 vmx->ple_window_dirty = true;
5277 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5278 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5279 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5281 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5282 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
5283 vmx_set_constant_host_state(vmx);
5284 #ifdef CONFIG_X86_64
5285 rdmsrl(MSR_FS_BASE, a);
5286 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5287 rdmsrl(MSR_GS_BASE, a);
5288 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5290 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5291 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5294 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5295 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5296 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5297 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5298 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5300 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5301 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5303 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5304 u32 index = vmx_msr_index[i];
5305 u32 data_low, data_high;
5308 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5310 if (wrmsr_safe(index, data_low, data_high) < 0)
5312 vmx->guest_msrs[j].index = i;
5313 vmx->guest_msrs[j].data = 0;
5314 vmx->guest_msrs[j].mask = -1ull;
5319 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5321 /* 22.2.1, 20.8.1 */
5322 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5324 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
5325 set_cr4_guest_host_mask(vmx);
5327 if (vmx_xsaves_supported())
5328 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5331 ASSERT(vmx->pml_pg);
5332 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5333 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5339 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5341 struct vcpu_vmx *vmx = to_vmx(vcpu);
5342 struct msr_data apic_base_msr;
5345 vmx->rmode.vm86_active = 0;
5347 vmx->soft_vnmi_blocked = 0;
5349 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5350 kvm_set_cr8(vcpu, 0);
5353 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5354 MSR_IA32_APICBASE_ENABLE;
5355 if (kvm_vcpu_is_reset_bsp(vcpu))
5356 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5357 apic_base_msr.host_initiated = true;
5358 kvm_set_apic_base(vcpu, &apic_base_msr);
5361 vmx_segment_cache_clear(vmx);
5363 seg_setup(VCPU_SREG_CS);
5364 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5365 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5367 seg_setup(VCPU_SREG_DS);
5368 seg_setup(VCPU_SREG_ES);
5369 seg_setup(VCPU_SREG_FS);
5370 seg_setup(VCPU_SREG_GS);
5371 seg_setup(VCPU_SREG_SS);
5373 vmcs_write16(GUEST_TR_SELECTOR, 0);
5374 vmcs_writel(GUEST_TR_BASE, 0);
5375 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5376 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5378 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5379 vmcs_writel(GUEST_LDTR_BASE, 0);
5380 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5381 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5384 vmcs_write32(GUEST_SYSENTER_CS, 0);
5385 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5386 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5387 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5390 vmcs_writel(GUEST_RFLAGS, 0x02);
5391 kvm_rip_write(vcpu, 0xfff0);
5393 vmcs_writel(GUEST_GDTR_BASE, 0);
5394 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5396 vmcs_writel(GUEST_IDTR_BASE, 0);
5397 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5399 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5400 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5401 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5405 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5407 if (cpu_has_vmx_tpr_shadow() && !init_event) {
5408 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5409 if (cpu_need_tpr_shadow(vcpu))
5410 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5411 __pa(vcpu->arch.apic->regs));
5412 vmcs_write32(TPR_THRESHOLD, 0);
5415 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5417 if (kvm_vcpu_apicv_active(vcpu))
5418 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5421 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5423 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5424 vmx->vcpu.arch.cr0 = cr0;
5425 vmx_set_cr0(vcpu, cr0); /* enter rmode */
5426 vmx_set_cr4(vcpu, 0);
5427 vmx_set_efer(vcpu, 0);
5428 vmx_fpu_activate(vcpu);
5429 update_exception_bitmap(vcpu);
5431 vpid_sync_context(vmx->vpid);
5435 * In nested virtualization, check if L1 asked to exit on external interrupts.
5436 * For most existing hypervisors, this will always return true.
5438 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5440 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5441 PIN_BASED_EXT_INTR_MASK;
5445 * In nested virtualization, check if L1 has set
5446 * VM_EXIT_ACK_INTR_ON_EXIT
5448 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5450 return get_vmcs12(vcpu)->vm_exit_controls &
5451 VM_EXIT_ACK_INTR_ON_EXIT;
5454 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5456 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5457 PIN_BASED_NMI_EXITING;
5460 static void enable_irq_window(struct kvm_vcpu *vcpu)
5462 u32 cpu_based_vm_exec_control;
5464 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5465 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5466 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5469 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5471 u32 cpu_based_vm_exec_control;
5473 if (!cpu_has_virtual_nmis() ||
5474 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5475 enable_irq_window(vcpu);
5479 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5480 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5481 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5484 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5486 struct vcpu_vmx *vmx = to_vmx(vcpu);
5488 int irq = vcpu->arch.interrupt.nr;
5490 trace_kvm_inj_virq(irq);
5492 ++vcpu->stat.irq_injections;
5493 if (vmx->rmode.vm86_active) {
5495 if (vcpu->arch.interrupt.soft)
5496 inc_eip = vcpu->arch.event_exit_inst_len;
5497 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5498 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5501 intr = irq | INTR_INFO_VALID_MASK;
5502 if (vcpu->arch.interrupt.soft) {
5503 intr |= INTR_TYPE_SOFT_INTR;
5504 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5505 vmx->vcpu.arch.event_exit_inst_len);
5507 intr |= INTR_TYPE_EXT_INTR;
5508 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5511 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5513 struct vcpu_vmx *vmx = to_vmx(vcpu);
5515 if (!is_guest_mode(vcpu)) {
5516 if (!cpu_has_virtual_nmis()) {
5518 * Tracking the NMI-blocked state in software is built upon
5519 * finding the next open IRQ window. This, in turn, depends on
5520 * well-behaving guests: They have to keep IRQs disabled at
5521 * least as long as the NMI handler runs. Otherwise we may
5522 * cause NMI nesting, maybe breaking the guest. But as this is
5523 * highly unlikely, we can live with the residual risk.
5525 vmx->soft_vnmi_blocked = 1;
5526 vmx->vnmi_blocked_time = 0;
5529 ++vcpu->stat.nmi_injections;
5530 vmx->nmi_known_unmasked = false;
5533 if (vmx->rmode.vm86_active) {
5534 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5535 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5539 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5540 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5543 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5545 if (!cpu_has_virtual_nmis())
5546 return to_vmx(vcpu)->soft_vnmi_blocked;
5547 if (to_vmx(vcpu)->nmi_known_unmasked)
5549 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5552 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5554 struct vcpu_vmx *vmx = to_vmx(vcpu);
5556 if (!cpu_has_virtual_nmis()) {
5557 if (vmx->soft_vnmi_blocked != masked) {
5558 vmx->soft_vnmi_blocked = masked;
5559 vmx->vnmi_blocked_time = 0;
5562 vmx->nmi_known_unmasked = !masked;
5564 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5565 GUEST_INTR_STATE_NMI);
5567 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5568 GUEST_INTR_STATE_NMI);
5572 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5574 if (to_vmx(vcpu)->nested.nested_run_pending)
5577 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5580 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5581 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5582 | GUEST_INTR_STATE_NMI));
5585 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5587 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5588 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5589 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5590 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5593 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5597 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5601 kvm->arch.tss_addr = addr;
5602 return init_rmode_tss(kvm);
5605 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5610 * Update instruction length as we may reinject the exception
5611 * from user space while in guest debugging mode.
5613 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5614 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5615 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5619 if (vcpu->guest_debug &
5620 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5637 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5638 int vec, u32 err_code)
5641 * Instruction with address size override prefix opcode 0x67
5642 * Cause the #SS fault with 0 error code in VM86 mode.
5644 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5645 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5646 if (vcpu->arch.halt_request) {
5647 vcpu->arch.halt_request = 0;
5648 return kvm_vcpu_halt(vcpu);
5656 * Forward all other exceptions that are valid in real mode.
5657 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5658 * the required debugging infrastructure rework.
5660 kvm_queue_exception(vcpu, vec);
5665 * Trigger machine check on the host. We assume all the MSRs are already set up
5666 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5667 * We pass a fake environment to the machine check handler because we want
5668 * the guest to be always treated like user space, no matter what context
5669 * it used internally.
5671 static void kvm_machine_check(void)
5673 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5674 struct pt_regs regs = {
5675 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5676 .flags = X86_EFLAGS_IF,
5679 do_machine_check(®s, 0);
5683 static int handle_machine_check(struct kvm_vcpu *vcpu)
5685 /* already handled by vcpu_run */
5689 static int handle_exception(struct kvm_vcpu *vcpu)
5691 struct vcpu_vmx *vmx = to_vmx(vcpu);
5692 struct kvm_run *kvm_run = vcpu->run;
5693 u32 intr_info, ex_no, error_code;
5694 unsigned long cr2, rip, dr6;
5696 enum emulation_result er;
5698 vect_info = vmx->idt_vectoring_info;
5699 intr_info = vmx->exit_intr_info;
5701 if (is_machine_check(intr_info))
5702 return handle_machine_check(vcpu);
5704 if (is_nmi(intr_info))
5705 return 1; /* already handled by vmx_vcpu_run() */
5707 if (is_no_device(intr_info)) {
5708 vmx_fpu_activate(vcpu);
5712 if (is_invalid_opcode(intr_info)) {
5713 if (is_guest_mode(vcpu)) {
5714 kvm_queue_exception(vcpu, UD_VECTOR);
5717 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5718 if (er != EMULATE_DONE)
5719 kvm_queue_exception(vcpu, UD_VECTOR);
5724 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5725 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5728 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5729 * MMIO, it is better to report an internal error.
5730 * See the comments in vmx_handle_exit.
5732 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5733 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5734 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5735 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5736 vcpu->run->internal.ndata = 3;
5737 vcpu->run->internal.data[0] = vect_info;
5738 vcpu->run->internal.data[1] = intr_info;
5739 vcpu->run->internal.data[2] = error_code;
5743 if (is_page_fault(intr_info)) {
5744 /* EPT won't cause page fault directly */
5746 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5747 trace_kvm_page_fault(cr2, error_code);
5749 if (kvm_event_needs_reinjection(vcpu))
5750 kvm_mmu_unprotect_page_virt(vcpu, cr2);
5751 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5754 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5756 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5757 return handle_rmode_exception(vcpu, ex_no, error_code);
5761 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5764 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5765 if (!(vcpu->guest_debug &
5766 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5767 vcpu->arch.dr6 &= ~15;
5768 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5769 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5770 skip_emulated_instruction(vcpu);
5772 kvm_queue_exception(vcpu, DB_VECTOR);
5775 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5776 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5780 * Update instruction length as we may reinject #BP from
5781 * user space while in guest debugging mode. Reading it for
5782 * #DB as well causes no harm, it is not used in that case.
5784 vmx->vcpu.arch.event_exit_inst_len =
5785 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5786 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5787 rip = kvm_rip_read(vcpu);
5788 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5789 kvm_run->debug.arch.exception = ex_no;
5792 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5793 kvm_run->ex.exception = ex_no;
5794 kvm_run->ex.error_code = error_code;
5800 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5802 ++vcpu->stat.irq_exits;
5806 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5808 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5812 static int handle_io(struct kvm_vcpu *vcpu)
5814 unsigned long exit_qualification;
5815 int size, in, string, ret;
5818 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5819 string = (exit_qualification & 16) != 0;
5820 in = (exit_qualification & 8) != 0;
5822 ++vcpu->stat.io_exits;
5825 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5827 port = exit_qualification >> 16;
5828 size = (exit_qualification & 7) + 1;
5830 ret = kvm_skip_emulated_instruction(vcpu);
5833 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5834 * KVM_EXIT_DEBUG here.
5836 return kvm_fast_pio_out(vcpu, size, port) && ret;
5840 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5843 * Patch in the VMCALL instruction:
5845 hypercall[0] = 0x0f;
5846 hypercall[1] = 0x01;
5847 hypercall[2] = 0xc1;
5850 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5851 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5853 if (is_guest_mode(vcpu)) {
5854 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5855 unsigned long orig_val = val;
5858 * We get here when L2 changed cr0 in a way that did not change
5859 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5860 * but did change L0 shadowed bits. So we first calculate the
5861 * effective cr0 value that L1 would like to write into the
5862 * hardware. It consists of the L2-owned bits from the new
5863 * value combined with the L1-owned bits from L1's guest_cr0.
5865 val = (val & ~vmcs12->cr0_guest_host_mask) |
5866 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5868 if (!nested_guest_cr0_valid(vcpu, val))
5871 if (kvm_set_cr0(vcpu, val))
5873 vmcs_writel(CR0_READ_SHADOW, orig_val);
5876 if (to_vmx(vcpu)->nested.vmxon &&
5877 !nested_host_cr0_valid(vcpu, val))
5880 return kvm_set_cr0(vcpu, val);
5884 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5886 if (is_guest_mode(vcpu)) {
5887 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5888 unsigned long orig_val = val;
5890 /* analogously to handle_set_cr0 */
5891 val = (val & ~vmcs12->cr4_guest_host_mask) |
5892 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5893 if (kvm_set_cr4(vcpu, val))
5895 vmcs_writel(CR4_READ_SHADOW, orig_val);
5898 return kvm_set_cr4(vcpu, val);
5901 /* called to set cr0 as appropriate for clts instruction exit. */
5902 static void handle_clts(struct kvm_vcpu *vcpu)
5904 if (is_guest_mode(vcpu)) {
5906 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5907 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5908 * just pretend it's off (also in arch.cr0 for fpu_activate).
5910 vmcs_writel(CR0_READ_SHADOW,
5911 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5912 vcpu->arch.cr0 &= ~X86_CR0_TS;
5914 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5917 static int handle_cr(struct kvm_vcpu *vcpu)
5919 unsigned long exit_qualification, val;
5925 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5926 cr = exit_qualification & 15;
5927 reg = (exit_qualification >> 8) & 15;
5928 switch ((exit_qualification >> 4) & 3) {
5929 case 0: /* mov to cr */
5930 val = kvm_register_readl(vcpu, reg);
5931 trace_kvm_cr_write(cr, val);
5934 err = handle_set_cr0(vcpu, val);
5935 return kvm_complete_insn_gp(vcpu, err);
5937 err = kvm_set_cr3(vcpu, val);
5938 return kvm_complete_insn_gp(vcpu, err);
5940 err = handle_set_cr4(vcpu, val);
5941 return kvm_complete_insn_gp(vcpu, err);
5943 u8 cr8_prev = kvm_get_cr8(vcpu);
5945 err = kvm_set_cr8(vcpu, cr8);
5946 ret = kvm_complete_insn_gp(vcpu, err);
5947 if (lapic_in_kernel(vcpu))
5949 if (cr8_prev <= cr8)
5952 * TODO: we might be squashing a
5953 * KVM_GUESTDBG_SINGLESTEP-triggered
5954 * KVM_EXIT_DEBUG here.
5956 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5963 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5964 vmx_fpu_activate(vcpu);
5965 return kvm_skip_emulated_instruction(vcpu);
5966 case 1: /*mov from cr*/
5969 val = kvm_read_cr3(vcpu);
5970 kvm_register_write(vcpu, reg, val);
5971 trace_kvm_cr_read(cr, val);
5972 return kvm_skip_emulated_instruction(vcpu);
5974 val = kvm_get_cr8(vcpu);
5975 kvm_register_write(vcpu, reg, val);
5976 trace_kvm_cr_read(cr, val);
5977 return kvm_skip_emulated_instruction(vcpu);
5981 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5982 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5983 kvm_lmsw(vcpu, val);
5985 return kvm_skip_emulated_instruction(vcpu);
5989 vcpu->run->exit_reason = 0;
5990 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5991 (int)(exit_qualification >> 4) & 3, cr);
5995 static int handle_dr(struct kvm_vcpu *vcpu)
5997 unsigned long exit_qualification;
6000 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6001 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6003 /* First, if DR does not exist, trigger UD */
6004 if (!kvm_require_dr(vcpu, dr))
6007 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6008 if (!kvm_require_cpl(vcpu, 0))
6010 dr7 = vmcs_readl(GUEST_DR7);
6013 * As the vm-exit takes precedence over the debug trap, we
6014 * need to emulate the latter, either for the host or the
6015 * guest debugging itself.
6017 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6018 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6019 vcpu->run->debug.arch.dr7 = dr7;
6020 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6021 vcpu->run->debug.arch.exception = DB_VECTOR;
6022 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6025 vcpu->arch.dr6 &= ~15;
6026 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6027 kvm_queue_exception(vcpu, DB_VECTOR);
6032 if (vcpu->guest_debug == 0) {
6033 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6034 CPU_BASED_MOV_DR_EXITING);
6037 * No more DR vmexits; force a reload of the debug registers
6038 * and reenter on this instruction. The next vmexit will
6039 * retrieve the full state of the debug registers.
6041 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6045 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6046 if (exit_qualification & TYPE_MOV_FROM_DR) {
6049 if (kvm_get_dr(vcpu, dr, &val))
6051 kvm_register_write(vcpu, reg, val);
6053 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6056 return kvm_skip_emulated_instruction(vcpu);
6059 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6061 return vcpu->arch.dr6;
6064 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6068 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6070 get_debugreg(vcpu->arch.db[0], 0);
6071 get_debugreg(vcpu->arch.db[1], 1);
6072 get_debugreg(vcpu->arch.db[2], 2);
6073 get_debugreg(vcpu->arch.db[3], 3);
6074 get_debugreg(vcpu->arch.dr6, 6);
6075 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6077 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6078 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6081 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6083 vmcs_writel(GUEST_DR7, val);
6086 static int handle_cpuid(struct kvm_vcpu *vcpu)
6088 return kvm_emulate_cpuid(vcpu);
6091 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6093 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6094 struct msr_data msr_info;
6096 msr_info.index = ecx;
6097 msr_info.host_initiated = false;
6098 if (vmx_get_msr(vcpu, &msr_info)) {
6099 trace_kvm_msr_read_ex(ecx);
6100 kvm_inject_gp(vcpu, 0);
6104 trace_kvm_msr_read(ecx, msr_info.data);
6106 /* FIXME: handling of bits 32:63 of rax, rdx */
6107 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6108 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6109 return kvm_skip_emulated_instruction(vcpu);
6112 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6114 struct msr_data msr;
6115 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6116 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6117 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6121 msr.host_initiated = false;
6122 if (kvm_set_msr(vcpu, &msr) != 0) {
6123 trace_kvm_msr_write_ex(ecx, data);
6124 kvm_inject_gp(vcpu, 0);
6128 trace_kvm_msr_write(ecx, data);
6129 return kvm_skip_emulated_instruction(vcpu);
6132 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6134 kvm_apic_update_ppr(vcpu);
6138 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6140 u32 cpu_based_vm_exec_control;
6142 /* clear pending irq */
6143 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6144 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6145 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6147 kvm_make_request(KVM_REQ_EVENT, vcpu);
6149 ++vcpu->stat.irq_window_exits;
6153 static int handle_halt(struct kvm_vcpu *vcpu)
6155 return kvm_emulate_halt(vcpu);
6158 static int handle_vmcall(struct kvm_vcpu *vcpu)
6160 return kvm_emulate_hypercall(vcpu);
6163 static int handle_invd(struct kvm_vcpu *vcpu)
6165 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6168 static int handle_invlpg(struct kvm_vcpu *vcpu)
6170 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6172 kvm_mmu_invlpg(vcpu, exit_qualification);
6173 return kvm_skip_emulated_instruction(vcpu);
6176 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6180 err = kvm_rdpmc(vcpu);
6181 return kvm_complete_insn_gp(vcpu, err);
6184 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6186 return kvm_emulate_wbinvd(vcpu);
6189 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6191 u64 new_bv = kvm_read_edx_eax(vcpu);
6192 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6194 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6195 return kvm_skip_emulated_instruction(vcpu);
6199 static int handle_xsaves(struct kvm_vcpu *vcpu)
6201 kvm_skip_emulated_instruction(vcpu);
6202 WARN(1, "this should never happen\n");
6206 static int handle_xrstors(struct kvm_vcpu *vcpu)
6208 kvm_skip_emulated_instruction(vcpu);
6209 WARN(1, "this should never happen\n");
6213 static int handle_apic_access(struct kvm_vcpu *vcpu)
6215 if (likely(fasteoi)) {
6216 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6217 int access_type, offset;
6219 access_type = exit_qualification & APIC_ACCESS_TYPE;
6220 offset = exit_qualification & APIC_ACCESS_OFFSET;
6222 * Sane guest uses MOV to write EOI, with written value
6223 * not cared. So make a short-circuit here by avoiding
6224 * heavy instruction emulation.
6226 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6227 (offset == APIC_EOI)) {
6228 kvm_lapic_set_eoi(vcpu);
6229 return kvm_skip_emulated_instruction(vcpu);
6232 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6235 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6237 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6238 int vector = exit_qualification & 0xff;
6240 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6241 kvm_apic_set_eoi_accelerated(vcpu, vector);
6245 static int handle_apic_write(struct kvm_vcpu *vcpu)
6247 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6248 u32 offset = exit_qualification & 0xfff;
6250 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6251 kvm_apic_write_nodecode(vcpu, offset);
6255 static int handle_task_switch(struct kvm_vcpu *vcpu)
6257 struct vcpu_vmx *vmx = to_vmx(vcpu);
6258 unsigned long exit_qualification;
6259 bool has_error_code = false;
6262 int reason, type, idt_v, idt_index;
6264 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6265 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6266 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6268 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6270 reason = (u32)exit_qualification >> 30;
6271 if (reason == TASK_SWITCH_GATE && idt_v) {
6273 case INTR_TYPE_NMI_INTR:
6274 vcpu->arch.nmi_injected = false;
6275 vmx_set_nmi_mask(vcpu, true);
6277 case INTR_TYPE_EXT_INTR:
6278 case INTR_TYPE_SOFT_INTR:
6279 kvm_clear_interrupt_queue(vcpu);
6281 case INTR_TYPE_HARD_EXCEPTION:
6282 if (vmx->idt_vectoring_info &
6283 VECTORING_INFO_DELIVER_CODE_MASK) {
6284 has_error_code = true;
6286 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6289 case INTR_TYPE_SOFT_EXCEPTION:
6290 kvm_clear_exception_queue(vcpu);
6296 tss_selector = exit_qualification;
6298 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6299 type != INTR_TYPE_EXT_INTR &&
6300 type != INTR_TYPE_NMI_INTR))
6301 skip_emulated_instruction(vcpu);
6303 if (kvm_task_switch(vcpu, tss_selector,
6304 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6305 has_error_code, error_code) == EMULATE_FAIL) {
6306 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6307 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6308 vcpu->run->internal.ndata = 0;
6313 * TODO: What about debug traps on tss switch?
6314 * Are we supposed to inject them and update dr6?
6320 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6322 unsigned long exit_qualification;
6327 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6329 gla_validity = (exit_qualification >> 7) & 0x3;
6330 if (gla_validity == 0x2) {
6331 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6332 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6333 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6334 vmcs_readl(GUEST_LINEAR_ADDRESS));
6335 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6336 (long unsigned int)exit_qualification);
6337 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6338 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6343 * EPT violation happened while executing iret from NMI,
6344 * "blocked by NMI" bit has to be set before next VM entry.
6345 * There are errata that may cause this bit to not be set:
6348 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6349 cpu_has_virtual_nmis() &&
6350 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6351 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6353 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6354 trace_kvm_page_fault(gpa, exit_qualification);
6356 /* Is it a read fault? */
6357 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6358 ? PFERR_USER_MASK : 0;
6359 /* Is it a write fault? */
6360 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6361 ? PFERR_WRITE_MASK : 0;
6362 /* Is it a fetch fault? */
6363 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6364 ? PFERR_FETCH_MASK : 0;
6365 /* ept page table entry is present? */
6366 error_code |= (exit_qualification &
6367 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6368 EPT_VIOLATION_EXECUTABLE))
6369 ? PFERR_PRESENT_MASK : 0;
6371 vcpu->arch.gpa_available = true;
6372 vcpu->arch.exit_qualification = exit_qualification;
6374 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6377 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6382 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6383 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6384 trace_kvm_fast_mmio(gpa);
6385 return kvm_skip_emulated_instruction(vcpu);
6388 ret = handle_mmio_page_fault(vcpu, gpa, true);
6389 vcpu->arch.gpa_available = true;
6390 if (likely(ret == RET_MMIO_PF_EMULATE))
6391 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6394 if (unlikely(ret == RET_MMIO_PF_INVALID))
6395 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6397 if (unlikely(ret == RET_MMIO_PF_RETRY))
6400 /* It is the real ept misconfig */
6403 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6404 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6409 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6411 u32 cpu_based_vm_exec_control;
6413 /* clear pending NMI */
6414 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6415 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6416 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6417 ++vcpu->stat.nmi_window_exits;
6418 kvm_make_request(KVM_REQ_EVENT, vcpu);
6423 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6425 struct vcpu_vmx *vmx = to_vmx(vcpu);
6426 enum emulation_result err = EMULATE_DONE;
6429 bool intr_window_requested;
6430 unsigned count = 130;
6432 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6433 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6435 while (vmx->emulation_required && count-- != 0) {
6436 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6437 return handle_interrupt_window(&vmx->vcpu);
6439 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6442 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6444 if (err == EMULATE_USER_EXIT) {
6445 ++vcpu->stat.mmio_exits;
6450 if (err != EMULATE_DONE) {
6451 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6452 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6453 vcpu->run->internal.ndata = 0;
6457 if (vcpu->arch.halt_request) {
6458 vcpu->arch.halt_request = 0;
6459 ret = kvm_vcpu_halt(vcpu);
6463 if (signal_pending(current))
6473 static int __grow_ple_window(int val)
6475 if (ple_window_grow < 1)
6478 val = min(val, ple_window_actual_max);
6480 if (ple_window_grow < ple_window)
6481 val *= ple_window_grow;
6483 val += ple_window_grow;
6488 static int __shrink_ple_window(int val, int modifier, int minimum)
6493 if (modifier < ple_window)
6498 return max(val, minimum);
6501 static void grow_ple_window(struct kvm_vcpu *vcpu)
6503 struct vcpu_vmx *vmx = to_vmx(vcpu);
6504 int old = vmx->ple_window;
6506 vmx->ple_window = __grow_ple_window(old);
6508 if (vmx->ple_window != old)
6509 vmx->ple_window_dirty = true;
6511 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6514 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6516 struct vcpu_vmx *vmx = to_vmx(vcpu);
6517 int old = vmx->ple_window;
6519 vmx->ple_window = __shrink_ple_window(old,
6520 ple_window_shrink, ple_window);
6522 if (vmx->ple_window != old)
6523 vmx->ple_window_dirty = true;
6525 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6529 * ple_window_actual_max is computed to be one grow_ple_window() below
6530 * ple_window_max. (See __grow_ple_window for the reason.)
6531 * This prevents overflows, because ple_window_max is int.
6532 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6534 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6536 static void update_ple_window_actual_max(void)
6538 ple_window_actual_max =
6539 __shrink_ple_window(max(ple_window_max, ple_window),
6540 ple_window_grow, INT_MIN);
6544 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6546 static void wakeup_handler(void)
6548 struct kvm_vcpu *vcpu;
6549 int cpu = smp_processor_id();
6551 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6552 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6553 blocked_vcpu_list) {
6554 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6556 if (pi_test_on(pi_desc) == 1)
6557 kvm_vcpu_kick(vcpu);
6559 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6562 void vmx_enable_tdp(void)
6564 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6565 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6566 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6567 0ull, VMX_EPT_EXECUTABLE_MASK,
6568 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6569 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6571 ept_set_mmio_spte_mask();
6575 static __init int hardware_setup(void)
6577 int r = -ENOMEM, i, msr;
6579 rdmsrl_safe(MSR_EFER, &host_efer);
6581 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6582 kvm_define_shared_msr(i, vmx_msr_index[i]);
6584 for (i = 0; i < VMX_BITMAP_NR; i++) {
6585 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6590 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6591 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6592 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6595 * Allow direct access to the PC debug port (it is often used for I/O
6596 * delays, but the vmexits simply slow things down).
6598 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6599 clear_bit(0x80, vmx_io_bitmap_a);
6601 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6603 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6604 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6606 if (setup_vmcs_config(&vmcs_config) < 0) {
6611 if (boot_cpu_has(X86_FEATURE_NX))
6612 kvm_enable_efer_bits(EFER_NX);
6614 if (!cpu_has_vmx_vpid())
6616 if (!cpu_has_vmx_shadow_vmcs())
6617 enable_shadow_vmcs = 0;
6618 if (enable_shadow_vmcs)
6619 init_vmcs_shadow_fields();
6621 if (!cpu_has_vmx_ept() ||
6622 !cpu_has_vmx_ept_4levels()) {
6624 enable_unrestricted_guest = 0;
6625 enable_ept_ad_bits = 0;
6628 if (!cpu_has_vmx_ept_ad_bits())
6629 enable_ept_ad_bits = 0;
6631 if (!cpu_has_vmx_unrestricted_guest())
6632 enable_unrestricted_guest = 0;
6634 if (!cpu_has_vmx_flexpriority())
6635 flexpriority_enabled = 0;
6638 * set_apic_access_page_addr() is used to reload apic access
6639 * page upon invalidation. No need to do anything if not
6640 * using the APIC_ACCESS_ADDR VMCS field.
6642 if (!flexpriority_enabled)
6643 kvm_x86_ops->set_apic_access_page_addr = NULL;
6645 if (!cpu_has_vmx_tpr_shadow())
6646 kvm_x86_ops->update_cr8_intercept = NULL;
6648 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6649 kvm_disable_largepages();
6651 if (!cpu_has_vmx_ple())
6654 if (!cpu_has_vmx_apicv()) {
6656 kvm_x86_ops->sync_pir_to_irr = NULL;
6659 if (cpu_has_vmx_tsc_scaling()) {
6660 kvm_has_tsc_control = true;
6661 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6662 kvm_tsc_scaling_ratio_frac_bits = 48;
6665 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6666 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6667 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6668 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6669 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6670 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6671 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6673 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6674 vmx_msr_bitmap_legacy, PAGE_SIZE);
6675 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6676 vmx_msr_bitmap_longmode, PAGE_SIZE);
6677 memcpy(vmx_msr_bitmap_legacy_x2apic,
6678 vmx_msr_bitmap_legacy, PAGE_SIZE);
6679 memcpy(vmx_msr_bitmap_longmode_x2apic,
6680 vmx_msr_bitmap_longmode, PAGE_SIZE);
6682 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6684 for (msr = 0x800; msr <= 0x8ff; msr++) {
6685 if (msr == 0x839 /* TMCCT */)
6687 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6691 * TPR reads and writes can be virtualized even if virtual interrupt
6692 * delivery is not in use.
6694 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6695 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6698 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6700 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6707 update_ple_window_actual_max();
6710 * Only enable PML when hardware supports PML feature, and both EPT
6711 * and EPT A/D bit features are enabled -- PML depends on them to work.
6713 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6717 kvm_x86_ops->slot_enable_log_dirty = NULL;
6718 kvm_x86_ops->slot_disable_log_dirty = NULL;
6719 kvm_x86_ops->flush_log_dirty = NULL;
6720 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6723 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6726 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6727 cpu_preemption_timer_multi =
6728 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6730 kvm_x86_ops->set_hv_timer = NULL;
6731 kvm_x86_ops->cancel_hv_timer = NULL;
6734 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6736 kvm_mce_cap_supported |= MCG_LMCE_P;
6738 return alloc_kvm_area();
6741 for (i = 0; i < VMX_BITMAP_NR; i++)
6742 free_page((unsigned long)vmx_bitmap[i]);
6747 static __exit void hardware_unsetup(void)
6751 for (i = 0; i < VMX_BITMAP_NR; i++)
6752 free_page((unsigned long)vmx_bitmap[i]);
6758 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6759 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6761 static int handle_pause(struct kvm_vcpu *vcpu)
6764 grow_ple_window(vcpu);
6766 kvm_vcpu_on_spin(vcpu);
6767 return kvm_skip_emulated_instruction(vcpu);
6770 static int handle_nop(struct kvm_vcpu *vcpu)
6772 return kvm_skip_emulated_instruction(vcpu);
6775 static int handle_mwait(struct kvm_vcpu *vcpu)
6777 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6778 return handle_nop(vcpu);
6781 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6786 static int handle_monitor(struct kvm_vcpu *vcpu)
6788 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6789 return handle_nop(vcpu);
6793 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6794 * We could reuse a single VMCS for all the L2 guests, but we also want the
6795 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6796 * allows keeping them loaded on the processor, and in the future will allow
6797 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6798 * every entry if they never change.
6799 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6800 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6802 * The following functions allocate and free a vmcs02 in this pool.
6805 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6806 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6808 struct vmcs02_list *item;
6809 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6810 if (item->vmptr == vmx->nested.current_vmptr) {
6811 list_move(&item->list, &vmx->nested.vmcs02_pool);
6812 return &item->vmcs02;
6815 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6816 /* Recycle the least recently used VMCS. */
6817 item = list_last_entry(&vmx->nested.vmcs02_pool,
6818 struct vmcs02_list, list);
6819 item->vmptr = vmx->nested.current_vmptr;
6820 list_move(&item->list, &vmx->nested.vmcs02_pool);
6821 return &item->vmcs02;
6824 /* Create a new VMCS */
6825 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6828 item->vmcs02.vmcs = alloc_vmcs();
6829 item->vmcs02.shadow_vmcs = NULL;
6830 if (!item->vmcs02.vmcs) {
6834 loaded_vmcs_init(&item->vmcs02);
6835 item->vmptr = vmx->nested.current_vmptr;
6836 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6837 vmx->nested.vmcs02_num++;
6838 return &item->vmcs02;
6841 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6842 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6844 struct vmcs02_list *item;
6845 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6846 if (item->vmptr == vmptr) {
6847 free_loaded_vmcs(&item->vmcs02);
6848 list_del(&item->list);
6850 vmx->nested.vmcs02_num--;
6856 * Free all VMCSs saved for this vcpu, except the one pointed by
6857 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6858 * must be &vmx->vmcs01.
6860 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6862 struct vmcs02_list *item, *n;
6864 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6865 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6867 * Something will leak if the above WARN triggers. Better than
6870 if (vmx->loaded_vmcs == &item->vmcs02)
6873 free_loaded_vmcs(&item->vmcs02);
6874 list_del(&item->list);
6876 vmx->nested.vmcs02_num--;
6881 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6882 * set the success or error code of an emulated VMX instruction, as specified
6883 * by Vol 2B, VMX Instruction Reference, "Conventions".
6885 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6887 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6888 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6889 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6892 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6894 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6895 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6896 X86_EFLAGS_SF | X86_EFLAGS_OF))
6900 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6901 u32 vm_instruction_error)
6903 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6905 * failValid writes the error number to the current VMCS, which
6906 * can't be done there isn't a current VMCS.
6908 nested_vmx_failInvalid(vcpu);
6911 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6912 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6913 X86_EFLAGS_SF | X86_EFLAGS_OF))
6915 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6917 * We don't need to force a shadow sync because
6918 * VM_INSTRUCTION_ERROR is not shadowed
6922 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6924 /* TODO: not to reset guest simply here. */
6925 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6926 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6929 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6931 struct vcpu_vmx *vmx =
6932 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6934 vmx->nested.preemption_timer_expired = true;
6935 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6936 kvm_vcpu_kick(&vmx->vcpu);
6938 return HRTIMER_NORESTART;
6942 * Decode the memory-address operand of a vmx instruction, as recorded on an
6943 * exit caused by such an instruction (run by a guest hypervisor).
6944 * On success, returns 0. When the operand is invalid, returns 1 and throws
6947 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6948 unsigned long exit_qualification,
6949 u32 vmx_instruction_info, bool wr, gva_t *ret)
6953 struct kvm_segment s;
6956 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6957 * Execution", on an exit, vmx_instruction_info holds most of the
6958 * addressing components of the operand. Only the displacement part
6959 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6960 * For how an actual address is calculated from all these components,
6961 * refer to Vol. 1, "Operand Addressing".
6963 int scaling = vmx_instruction_info & 3;
6964 int addr_size = (vmx_instruction_info >> 7) & 7;
6965 bool is_reg = vmx_instruction_info & (1u << 10);
6966 int seg_reg = (vmx_instruction_info >> 15) & 7;
6967 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6968 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6969 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6970 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6973 kvm_queue_exception(vcpu, UD_VECTOR);
6977 /* Addr = segment_base + offset */
6978 /* offset = base + [index * scale] + displacement */
6979 off = exit_qualification; /* holds the displacement */
6981 off += kvm_register_read(vcpu, base_reg);
6983 off += kvm_register_read(vcpu, index_reg)<<scaling;
6984 vmx_get_segment(vcpu, &s, seg_reg);
6985 *ret = s.base + off;
6987 if (addr_size == 1) /* 32 bit */
6990 /* Checks for #GP/#SS exceptions. */
6992 if (is_long_mode(vcpu)) {
6993 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6994 * non-canonical form. This is the only check on the memory
6995 * destination for long mode!
6997 exn = is_noncanonical_address(*ret);
6998 } else if (is_protmode(vcpu)) {
6999 /* Protected mode: apply checks for segment validity in the
7001 * - segment type check (#GP(0) may be thrown)
7002 * - usability check (#GP(0)/#SS(0))
7003 * - limit check (#GP(0)/#SS(0))
7006 /* #GP(0) if the destination operand is located in a
7007 * read-only data segment or any code segment.
7009 exn = ((s.type & 0xa) == 0 || (s.type & 8));
7011 /* #GP(0) if the source operand is located in an
7012 * execute-only code segment
7014 exn = ((s.type & 0xa) == 8);
7016 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7019 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7021 exn = (s.unusable != 0);
7022 /* Protected mode: #GP(0)/#SS(0) if the memory
7023 * operand is outside the segment limit.
7025 exn = exn || (off + sizeof(u64) > s.limit);
7028 kvm_queue_exception_e(vcpu,
7029 seg_reg == VCPU_SREG_SS ?
7030 SS_VECTOR : GP_VECTOR,
7039 * This function performs the various checks including
7040 * - if it's 4KB aligned
7041 * - No bits beyond the physical address width are set
7042 * - Returns 0 on success or else 1
7043 * (Intel SDM Section 30.3)
7045 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
7050 struct x86_exception e;
7052 struct vcpu_vmx *vmx = to_vmx(vcpu);
7053 int maxphyaddr = cpuid_maxphyaddr(vcpu);
7055 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7056 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7059 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
7060 sizeof(vmptr), &e)) {
7061 kvm_inject_page_fault(vcpu, &e);
7065 switch (exit_reason) {
7066 case EXIT_REASON_VMON:
7069 * The first 4 bytes of VMXON region contain the supported
7070 * VMCS revision identifier
7072 * Note - IA32_VMX_BASIC[48] will never be 1
7073 * for the nested case;
7074 * which replaces physical address width with 32
7077 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7078 nested_vmx_failInvalid(vcpu);
7079 return kvm_skip_emulated_instruction(vcpu);
7082 page = nested_get_page(vcpu, vmptr);
7084 *(u32 *)kmap(page) != VMCS12_REVISION) {
7085 nested_vmx_failInvalid(vcpu);
7087 return kvm_skip_emulated_instruction(vcpu);
7090 vmx->nested.vmxon_ptr = vmptr;
7092 case EXIT_REASON_VMCLEAR:
7093 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7094 nested_vmx_failValid(vcpu,
7095 VMXERR_VMCLEAR_INVALID_ADDRESS);
7096 return kvm_skip_emulated_instruction(vcpu);
7099 if (vmptr == vmx->nested.vmxon_ptr) {
7100 nested_vmx_failValid(vcpu,
7101 VMXERR_VMCLEAR_VMXON_POINTER);
7102 return kvm_skip_emulated_instruction(vcpu);
7105 case EXIT_REASON_VMPTRLD:
7106 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7107 nested_vmx_failValid(vcpu,
7108 VMXERR_VMPTRLD_INVALID_ADDRESS);
7109 return kvm_skip_emulated_instruction(vcpu);
7112 if (vmptr == vmx->nested.vmxon_ptr) {
7113 nested_vmx_failValid(vcpu,
7114 VMXERR_VMPTRLD_VMXON_POINTER);
7115 return kvm_skip_emulated_instruction(vcpu);
7119 return 1; /* shouldn't happen */
7128 * Emulate the VMXON instruction.
7129 * Currently, we just remember that VMX is active, and do not save or even
7130 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7131 * do not currently need to store anything in that guest-allocated memory
7132 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7133 * argument is different from the VMXON pointer (which the spec says they do).
7135 static int handle_vmon(struct kvm_vcpu *vcpu)
7137 struct kvm_segment cs;
7138 struct vcpu_vmx *vmx = to_vmx(vcpu);
7139 struct vmcs *shadow_vmcs;
7140 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7141 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7143 /* The Intel VMX Instruction Reference lists a bunch of bits that
7144 * are prerequisite to running VMXON, most notably cr4.VMXE must be
7145 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7146 * Otherwise, we should fail with #UD. We test these now:
7148 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7149 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7150 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7151 kvm_queue_exception(vcpu, UD_VECTOR);
7155 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7156 if (is_long_mode(vcpu) && !cs.l) {
7157 kvm_queue_exception(vcpu, UD_VECTOR);
7161 if (vmx_get_cpl(vcpu)) {
7162 kvm_inject_gp(vcpu, 0);
7166 if (vmx->nested.vmxon) {
7167 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7168 return kvm_skip_emulated_instruction(vcpu);
7171 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7172 != VMXON_NEEDED_FEATURES) {
7173 kvm_inject_gp(vcpu, 0);
7177 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7180 if (cpu_has_vmx_msr_bitmap()) {
7181 vmx->nested.msr_bitmap =
7182 (unsigned long *)__get_free_page(GFP_KERNEL);
7183 if (!vmx->nested.msr_bitmap)
7184 goto out_msr_bitmap;
7187 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7188 if (!vmx->nested.cached_vmcs12)
7189 goto out_cached_vmcs12;
7191 if (enable_shadow_vmcs) {
7192 shadow_vmcs = alloc_vmcs();
7194 goto out_shadow_vmcs;
7195 /* mark vmcs as shadow */
7196 shadow_vmcs->revision_id |= (1u << 31);
7197 /* init shadow vmcs */
7198 vmcs_clear(shadow_vmcs);
7199 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7202 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7203 vmx->nested.vmcs02_num = 0;
7205 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7206 HRTIMER_MODE_REL_PINNED);
7207 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7209 vmx->nested.vmxon = true;
7211 nested_vmx_succeed(vcpu);
7212 return kvm_skip_emulated_instruction(vcpu);
7215 kfree(vmx->nested.cached_vmcs12);
7218 free_page((unsigned long)vmx->nested.msr_bitmap);
7225 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7226 * for running VMX instructions (except VMXON, whose prerequisites are
7227 * slightly different). It also specifies what exception to inject otherwise.
7229 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7231 struct kvm_segment cs;
7232 struct vcpu_vmx *vmx = to_vmx(vcpu);
7234 if (!vmx->nested.vmxon) {
7235 kvm_queue_exception(vcpu, UD_VECTOR);
7239 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7240 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7241 (is_long_mode(vcpu) && !cs.l)) {
7242 kvm_queue_exception(vcpu, UD_VECTOR);
7246 if (vmx_get_cpl(vcpu)) {
7247 kvm_inject_gp(vcpu, 0);
7254 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7256 if (vmx->nested.current_vmptr == -1ull)
7259 /* current_vmptr and current_vmcs12 are always set/reset together */
7260 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7263 if (enable_shadow_vmcs) {
7264 /* copy to memory all shadowed fields in case
7265 they were modified */
7266 copy_shadow_to_vmcs12(vmx);
7267 vmx->nested.sync_shadow_vmcs = false;
7268 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7269 SECONDARY_EXEC_SHADOW_VMCS);
7270 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7272 vmx->nested.posted_intr_nv = -1;
7274 /* Flush VMCS12 to guest memory */
7275 memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7278 kunmap(vmx->nested.current_vmcs12_page);
7279 nested_release_page(vmx->nested.current_vmcs12_page);
7280 vmx->nested.current_vmptr = -1ull;
7281 vmx->nested.current_vmcs12 = NULL;
7285 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7286 * just stops using VMX.
7288 static void free_nested(struct vcpu_vmx *vmx)
7290 if (!vmx->nested.vmxon)
7293 vmx->nested.vmxon = false;
7294 free_vpid(vmx->nested.vpid02);
7295 nested_release_vmcs12(vmx);
7296 if (vmx->nested.msr_bitmap) {
7297 free_page((unsigned long)vmx->nested.msr_bitmap);
7298 vmx->nested.msr_bitmap = NULL;
7300 if (enable_shadow_vmcs) {
7301 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7302 free_vmcs(vmx->vmcs01.shadow_vmcs);
7303 vmx->vmcs01.shadow_vmcs = NULL;
7305 kfree(vmx->nested.cached_vmcs12);
7306 /* Unpin physical memory we referred to in current vmcs02 */
7307 if (vmx->nested.apic_access_page) {
7308 nested_release_page(vmx->nested.apic_access_page);
7309 vmx->nested.apic_access_page = NULL;
7311 if (vmx->nested.virtual_apic_page) {
7312 nested_release_page(vmx->nested.virtual_apic_page);
7313 vmx->nested.virtual_apic_page = NULL;
7315 if (vmx->nested.pi_desc_page) {
7316 kunmap(vmx->nested.pi_desc_page);
7317 nested_release_page(vmx->nested.pi_desc_page);
7318 vmx->nested.pi_desc_page = NULL;
7319 vmx->nested.pi_desc = NULL;
7322 nested_free_all_saved_vmcss(vmx);
7325 /* Emulate the VMXOFF instruction */
7326 static int handle_vmoff(struct kvm_vcpu *vcpu)
7328 if (!nested_vmx_check_permission(vcpu))
7330 free_nested(to_vmx(vcpu));
7331 nested_vmx_succeed(vcpu);
7332 return kvm_skip_emulated_instruction(vcpu);
7335 /* Emulate the VMCLEAR instruction */
7336 static int handle_vmclear(struct kvm_vcpu *vcpu)
7338 struct vcpu_vmx *vmx = to_vmx(vcpu);
7340 struct vmcs12 *vmcs12;
7343 if (!nested_vmx_check_permission(vcpu))
7346 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7349 if (vmptr == vmx->nested.current_vmptr)
7350 nested_release_vmcs12(vmx);
7352 page = nested_get_page(vcpu, vmptr);
7355 * For accurate processor emulation, VMCLEAR beyond available
7356 * physical memory should do nothing at all. However, it is
7357 * possible that a nested vmx bug, not a guest hypervisor bug,
7358 * resulted in this case, so let's shut down before doing any
7361 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7364 vmcs12 = kmap(page);
7365 vmcs12->launch_state = 0;
7367 nested_release_page(page);
7369 nested_free_vmcs02(vmx, vmptr);
7371 nested_vmx_succeed(vcpu);
7372 return kvm_skip_emulated_instruction(vcpu);
7375 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7377 /* Emulate the VMLAUNCH instruction */
7378 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7380 return nested_vmx_run(vcpu, true);
7383 /* Emulate the VMRESUME instruction */
7384 static int handle_vmresume(struct kvm_vcpu *vcpu)
7387 return nested_vmx_run(vcpu, false);
7390 enum vmcs_field_type {
7391 VMCS_FIELD_TYPE_U16 = 0,
7392 VMCS_FIELD_TYPE_U64 = 1,
7393 VMCS_FIELD_TYPE_U32 = 2,
7394 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7397 static inline int vmcs_field_type(unsigned long field)
7399 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
7400 return VMCS_FIELD_TYPE_U32;
7401 return (field >> 13) & 0x3 ;
7404 static inline int vmcs_field_readonly(unsigned long field)
7406 return (((field >> 10) & 0x3) == 1);
7410 * Read a vmcs12 field. Since these can have varying lengths and we return
7411 * one type, we chose the biggest type (u64) and zero-extend the return value
7412 * to that size. Note that the caller, handle_vmread, might need to use only
7413 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7414 * 64-bit fields are to be returned).
7416 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7417 unsigned long field, u64 *ret)
7419 short offset = vmcs_field_to_offset(field);
7425 p = ((char *)(get_vmcs12(vcpu))) + offset;
7427 switch (vmcs_field_type(field)) {
7428 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7429 *ret = *((natural_width *)p);
7431 case VMCS_FIELD_TYPE_U16:
7434 case VMCS_FIELD_TYPE_U32:
7437 case VMCS_FIELD_TYPE_U64:
7447 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7448 unsigned long field, u64 field_value){
7449 short offset = vmcs_field_to_offset(field);
7450 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7454 switch (vmcs_field_type(field)) {
7455 case VMCS_FIELD_TYPE_U16:
7456 *(u16 *)p = field_value;
7458 case VMCS_FIELD_TYPE_U32:
7459 *(u32 *)p = field_value;
7461 case VMCS_FIELD_TYPE_U64:
7462 *(u64 *)p = field_value;
7464 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7465 *(natural_width *)p = field_value;
7474 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7477 unsigned long field;
7479 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7480 const unsigned long *fields = shadow_read_write_fields;
7481 const int num_fields = max_shadow_read_write_fields;
7485 vmcs_load(shadow_vmcs);
7487 for (i = 0; i < num_fields; i++) {
7489 switch (vmcs_field_type(field)) {
7490 case VMCS_FIELD_TYPE_U16:
7491 field_value = vmcs_read16(field);
7493 case VMCS_FIELD_TYPE_U32:
7494 field_value = vmcs_read32(field);
7496 case VMCS_FIELD_TYPE_U64:
7497 field_value = vmcs_read64(field);
7499 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7500 field_value = vmcs_readl(field);
7506 vmcs12_write_any(&vmx->vcpu, field, field_value);
7509 vmcs_clear(shadow_vmcs);
7510 vmcs_load(vmx->loaded_vmcs->vmcs);
7515 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7517 const unsigned long *fields[] = {
7518 shadow_read_write_fields,
7519 shadow_read_only_fields
7521 const int max_fields[] = {
7522 max_shadow_read_write_fields,
7523 max_shadow_read_only_fields
7526 unsigned long field;
7527 u64 field_value = 0;
7528 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7530 vmcs_load(shadow_vmcs);
7532 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7533 for (i = 0; i < max_fields[q]; i++) {
7534 field = fields[q][i];
7535 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7537 switch (vmcs_field_type(field)) {
7538 case VMCS_FIELD_TYPE_U16:
7539 vmcs_write16(field, (u16)field_value);
7541 case VMCS_FIELD_TYPE_U32:
7542 vmcs_write32(field, (u32)field_value);
7544 case VMCS_FIELD_TYPE_U64:
7545 vmcs_write64(field, (u64)field_value);
7547 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7548 vmcs_writel(field, (long)field_value);
7557 vmcs_clear(shadow_vmcs);
7558 vmcs_load(vmx->loaded_vmcs->vmcs);
7562 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7563 * used before) all generate the same failure when it is missing.
7565 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7567 struct vcpu_vmx *vmx = to_vmx(vcpu);
7568 if (vmx->nested.current_vmptr == -1ull) {
7569 nested_vmx_failInvalid(vcpu);
7575 static int handle_vmread(struct kvm_vcpu *vcpu)
7577 unsigned long field;
7579 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7580 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7583 if (!nested_vmx_check_permission(vcpu))
7586 if (!nested_vmx_check_vmcs12(vcpu))
7587 return kvm_skip_emulated_instruction(vcpu);
7589 /* Decode instruction info and find the field to read */
7590 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7591 /* Read the field, zero-extended to a u64 field_value */
7592 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7593 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7594 return kvm_skip_emulated_instruction(vcpu);
7597 * Now copy part of this value to register or memory, as requested.
7598 * Note that the number of bits actually copied is 32 or 64 depending
7599 * on the guest's mode (32 or 64 bit), not on the given field's length.
7601 if (vmx_instruction_info & (1u << 10)) {
7602 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7605 if (get_vmx_mem_address(vcpu, exit_qualification,
7606 vmx_instruction_info, true, &gva))
7608 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7609 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7610 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7613 nested_vmx_succeed(vcpu);
7614 return kvm_skip_emulated_instruction(vcpu);
7618 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7620 unsigned long field;
7622 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7623 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7624 /* The value to write might be 32 or 64 bits, depending on L1's long
7625 * mode, and eventually we need to write that into a field of several
7626 * possible lengths. The code below first zero-extends the value to 64
7627 * bit (field_value), and then copies only the appropriate number of
7628 * bits into the vmcs12 field.
7630 u64 field_value = 0;
7631 struct x86_exception e;
7633 if (!nested_vmx_check_permission(vcpu))
7636 if (!nested_vmx_check_vmcs12(vcpu))
7637 return kvm_skip_emulated_instruction(vcpu);
7639 if (vmx_instruction_info & (1u << 10))
7640 field_value = kvm_register_readl(vcpu,
7641 (((vmx_instruction_info) >> 3) & 0xf));
7643 if (get_vmx_mem_address(vcpu, exit_qualification,
7644 vmx_instruction_info, false, &gva))
7646 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7647 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7648 kvm_inject_page_fault(vcpu, &e);
7654 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7655 if (vmcs_field_readonly(field)) {
7656 nested_vmx_failValid(vcpu,
7657 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7658 return kvm_skip_emulated_instruction(vcpu);
7661 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7662 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7663 return kvm_skip_emulated_instruction(vcpu);
7666 nested_vmx_succeed(vcpu);
7667 return kvm_skip_emulated_instruction(vcpu);
7670 /* Emulate the VMPTRLD instruction */
7671 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7673 struct vcpu_vmx *vmx = to_vmx(vcpu);
7676 if (!nested_vmx_check_permission(vcpu))
7679 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7682 if (vmx->nested.current_vmptr != vmptr) {
7683 struct vmcs12 *new_vmcs12;
7685 page = nested_get_page(vcpu, vmptr);
7687 nested_vmx_failInvalid(vcpu);
7688 return kvm_skip_emulated_instruction(vcpu);
7690 new_vmcs12 = kmap(page);
7691 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7693 nested_release_page_clean(page);
7694 nested_vmx_failValid(vcpu,
7695 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7696 return kvm_skip_emulated_instruction(vcpu);
7699 nested_release_vmcs12(vmx);
7700 vmx->nested.current_vmptr = vmptr;
7701 vmx->nested.current_vmcs12 = new_vmcs12;
7702 vmx->nested.current_vmcs12_page = page;
7704 * Load VMCS12 from guest memory since it is not already
7707 memcpy(vmx->nested.cached_vmcs12,
7708 vmx->nested.current_vmcs12, VMCS12_SIZE);
7710 if (enable_shadow_vmcs) {
7711 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7712 SECONDARY_EXEC_SHADOW_VMCS);
7713 vmcs_write64(VMCS_LINK_POINTER,
7714 __pa(vmx->vmcs01.shadow_vmcs));
7715 vmx->nested.sync_shadow_vmcs = true;
7719 nested_vmx_succeed(vcpu);
7720 return kvm_skip_emulated_instruction(vcpu);
7723 /* Emulate the VMPTRST instruction */
7724 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7726 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7727 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7729 struct x86_exception e;
7731 if (!nested_vmx_check_permission(vcpu))
7734 if (get_vmx_mem_address(vcpu, exit_qualification,
7735 vmx_instruction_info, true, &vmcs_gva))
7737 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7738 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7739 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7741 kvm_inject_page_fault(vcpu, &e);
7744 nested_vmx_succeed(vcpu);
7745 return kvm_skip_emulated_instruction(vcpu);
7748 /* Emulate the INVEPT instruction */
7749 static int handle_invept(struct kvm_vcpu *vcpu)
7751 struct vcpu_vmx *vmx = to_vmx(vcpu);
7752 u32 vmx_instruction_info, types;
7755 struct x86_exception e;
7760 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7761 SECONDARY_EXEC_ENABLE_EPT) ||
7762 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7763 kvm_queue_exception(vcpu, UD_VECTOR);
7767 if (!nested_vmx_check_permission(vcpu))
7770 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7771 kvm_queue_exception(vcpu, UD_VECTOR);
7775 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7776 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7778 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7780 if (type >= 32 || !(types & (1 << type))) {
7781 nested_vmx_failValid(vcpu,
7782 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7783 return kvm_skip_emulated_instruction(vcpu);
7786 /* According to the Intel VMX instruction reference, the memory
7787 * operand is read even if it isn't needed (e.g., for type==global)
7789 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7790 vmx_instruction_info, false, &gva))
7792 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7793 sizeof(operand), &e)) {
7794 kvm_inject_page_fault(vcpu, &e);
7799 case VMX_EPT_EXTENT_GLOBAL:
7801 * TODO: track mappings and invalidate
7802 * single context requests appropriately
7804 case VMX_EPT_EXTENT_CONTEXT:
7805 kvm_mmu_sync_roots(vcpu);
7806 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7807 nested_vmx_succeed(vcpu);
7814 return kvm_skip_emulated_instruction(vcpu);
7817 static int handle_invvpid(struct kvm_vcpu *vcpu)
7819 struct vcpu_vmx *vmx = to_vmx(vcpu);
7820 u32 vmx_instruction_info;
7821 unsigned long type, types;
7823 struct x86_exception e;
7826 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7827 SECONDARY_EXEC_ENABLE_VPID) ||
7828 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7829 kvm_queue_exception(vcpu, UD_VECTOR);
7833 if (!nested_vmx_check_permission(vcpu))
7836 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7837 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7839 types = (vmx->nested.nested_vmx_vpid_caps &
7840 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7842 if (type >= 32 || !(types & (1 << type))) {
7843 nested_vmx_failValid(vcpu,
7844 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7845 return kvm_skip_emulated_instruction(vcpu);
7848 /* according to the intel vmx instruction reference, the memory
7849 * operand is read even if it isn't needed (e.g., for type==global)
7851 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7852 vmx_instruction_info, false, &gva))
7854 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7856 kvm_inject_page_fault(vcpu, &e);
7861 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7862 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7863 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7865 nested_vmx_failValid(vcpu,
7866 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7867 return kvm_skip_emulated_instruction(vcpu);
7870 case VMX_VPID_EXTENT_ALL_CONTEXT:
7874 return kvm_skip_emulated_instruction(vcpu);
7877 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7878 nested_vmx_succeed(vcpu);
7880 return kvm_skip_emulated_instruction(vcpu);
7883 static int handle_pml_full(struct kvm_vcpu *vcpu)
7885 unsigned long exit_qualification;
7887 trace_kvm_pml_full(vcpu->vcpu_id);
7889 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7892 * PML buffer FULL happened while executing iret from NMI,
7893 * "blocked by NMI" bit has to be set before next VM entry.
7895 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7896 cpu_has_virtual_nmis() &&
7897 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7898 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7899 GUEST_INTR_STATE_NMI);
7902 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7903 * here.., and there's no userspace involvement needed for PML.
7908 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7910 kvm_lapic_expired_hv_timer(vcpu);
7915 * The exit handlers return 1 if the exit was handled fully and guest execution
7916 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7917 * to be done to userspace and return 0.
7919 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7920 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7921 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7922 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7923 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7924 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7925 [EXIT_REASON_CR_ACCESS] = handle_cr,
7926 [EXIT_REASON_DR_ACCESS] = handle_dr,
7927 [EXIT_REASON_CPUID] = handle_cpuid,
7928 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7929 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7930 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7931 [EXIT_REASON_HLT] = handle_halt,
7932 [EXIT_REASON_INVD] = handle_invd,
7933 [EXIT_REASON_INVLPG] = handle_invlpg,
7934 [EXIT_REASON_RDPMC] = handle_rdpmc,
7935 [EXIT_REASON_VMCALL] = handle_vmcall,
7936 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7937 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7938 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7939 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7940 [EXIT_REASON_VMREAD] = handle_vmread,
7941 [EXIT_REASON_VMRESUME] = handle_vmresume,
7942 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7943 [EXIT_REASON_VMOFF] = handle_vmoff,
7944 [EXIT_REASON_VMON] = handle_vmon,
7945 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7946 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7947 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7948 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7949 [EXIT_REASON_WBINVD] = handle_wbinvd,
7950 [EXIT_REASON_XSETBV] = handle_xsetbv,
7951 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7952 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7953 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7954 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7955 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7956 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7957 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
7958 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7959 [EXIT_REASON_INVEPT] = handle_invept,
7960 [EXIT_REASON_INVVPID] = handle_invvpid,
7961 [EXIT_REASON_XSAVES] = handle_xsaves,
7962 [EXIT_REASON_XRSTORS] = handle_xrstors,
7963 [EXIT_REASON_PML_FULL] = handle_pml_full,
7964 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
7967 static const int kvm_vmx_max_exit_handlers =
7968 ARRAY_SIZE(kvm_vmx_exit_handlers);
7970 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7971 struct vmcs12 *vmcs12)
7973 unsigned long exit_qualification;
7974 gpa_t bitmap, last_bitmap;
7979 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7980 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7982 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7984 port = exit_qualification >> 16;
7985 size = (exit_qualification & 7) + 1;
7987 last_bitmap = (gpa_t)-1;
7992 bitmap = vmcs12->io_bitmap_a;
7993 else if (port < 0x10000)
7994 bitmap = vmcs12->io_bitmap_b;
7997 bitmap += (port & 0x7fff) / 8;
7999 if (last_bitmap != bitmap)
8000 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8002 if (b & (1 << (port & 7)))
8007 last_bitmap = bitmap;
8014 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8015 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8016 * disinterest in the current event (read or write a specific MSR) by using an
8017 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8019 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8020 struct vmcs12 *vmcs12, u32 exit_reason)
8022 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8025 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8029 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8030 * for the four combinations of read/write and low/high MSR numbers.
8031 * First we need to figure out which of the four to use:
8033 bitmap = vmcs12->msr_bitmap;
8034 if (exit_reason == EXIT_REASON_MSR_WRITE)
8036 if (msr_index >= 0xc0000000) {
8037 msr_index -= 0xc0000000;
8041 /* Then read the msr_index'th bit from this bitmap: */
8042 if (msr_index < 1024*8) {
8044 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8046 return 1 & (b >> (msr_index & 7));
8048 return true; /* let L1 handle the wrong parameter */
8052 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8053 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8054 * intercept (via guest_host_mask etc.) the current event.
8056 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8057 struct vmcs12 *vmcs12)
8059 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8060 int cr = exit_qualification & 15;
8061 int reg = (exit_qualification >> 8) & 15;
8062 unsigned long val = kvm_register_readl(vcpu, reg);
8064 switch ((exit_qualification >> 4) & 3) {
8065 case 0: /* mov to cr */
8068 if (vmcs12->cr0_guest_host_mask &
8069 (val ^ vmcs12->cr0_read_shadow))
8073 if ((vmcs12->cr3_target_count >= 1 &&
8074 vmcs12->cr3_target_value0 == val) ||
8075 (vmcs12->cr3_target_count >= 2 &&
8076 vmcs12->cr3_target_value1 == val) ||
8077 (vmcs12->cr3_target_count >= 3 &&
8078 vmcs12->cr3_target_value2 == val) ||
8079 (vmcs12->cr3_target_count >= 4 &&
8080 vmcs12->cr3_target_value3 == val))
8082 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8086 if (vmcs12->cr4_guest_host_mask &
8087 (vmcs12->cr4_read_shadow ^ val))
8091 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8097 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8098 (vmcs12->cr0_read_shadow & X86_CR0_TS))
8101 case 1: /* mov from cr */
8104 if (vmcs12->cpu_based_vm_exec_control &
8105 CPU_BASED_CR3_STORE_EXITING)
8109 if (vmcs12->cpu_based_vm_exec_control &
8110 CPU_BASED_CR8_STORE_EXITING)
8117 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8118 * cr0. Other attempted changes are ignored, with no exit.
8120 if (vmcs12->cr0_guest_host_mask & 0xe &
8121 (val ^ vmcs12->cr0_read_shadow))
8123 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8124 !(vmcs12->cr0_read_shadow & 0x1) &&
8133 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8134 * should handle it ourselves in L0 (and then continue L2). Only call this
8135 * when in is_guest_mode (L2).
8137 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8139 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8140 struct vcpu_vmx *vmx = to_vmx(vcpu);
8141 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8142 u32 exit_reason = vmx->exit_reason;
8144 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8145 vmcs_readl(EXIT_QUALIFICATION),
8146 vmx->idt_vectoring_info,
8148 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8151 if (vmx->nested.nested_run_pending)
8154 if (unlikely(vmx->fail)) {
8155 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8156 vmcs_read32(VM_INSTRUCTION_ERROR));
8160 switch (exit_reason) {
8161 case EXIT_REASON_EXCEPTION_NMI:
8162 if (is_nmi(intr_info))
8164 else if (is_page_fault(intr_info))
8166 else if (is_no_device(intr_info) &&
8167 !(vmcs12->guest_cr0 & X86_CR0_TS))
8169 else if (is_debug(intr_info) &&
8171 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8173 else if (is_breakpoint(intr_info) &&
8174 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8176 return vmcs12->exception_bitmap &
8177 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8178 case EXIT_REASON_EXTERNAL_INTERRUPT:
8180 case EXIT_REASON_TRIPLE_FAULT:
8182 case EXIT_REASON_PENDING_INTERRUPT:
8183 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8184 case EXIT_REASON_NMI_WINDOW:
8185 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8186 case EXIT_REASON_TASK_SWITCH:
8188 case EXIT_REASON_CPUID:
8190 case EXIT_REASON_HLT:
8191 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8192 case EXIT_REASON_INVD:
8194 case EXIT_REASON_INVLPG:
8195 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8196 case EXIT_REASON_RDPMC:
8197 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8198 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8199 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8200 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8201 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8202 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8203 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8204 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8205 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8207 * VMX instructions trap unconditionally. This allows L1 to
8208 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8211 case EXIT_REASON_CR_ACCESS:
8212 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8213 case EXIT_REASON_DR_ACCESS:
8214 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8215 case EXIT_REASON_IO_INSTRUCTION:
8216 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8217 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8218 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8219 case EXIT_REASON_MSR_READ:
8220 case EXIT_REASON_MSR_WRITE:
8221 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8222 case EXIT_REASON_INVALID_STATE:
8224 case EXIT_REASON_MWAIT_INSTRUCTION:
8225 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8226 case EXIT_REASON_MONITOR_TRAP_FLAG:
8227 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8228 case EXIT_REASON_MONITOR_INSTRUCTION:
8229 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8230 case EXIT_REASON_PAUSE_INSTRUCTION:
8231 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8232 nested_cpu_has2(vmcs12,
8233 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8234 case EXIT_REASON_MCE_DURING_VMENTRY:
8236 case EXIT_REASON_TPR_BELOW_THRESHOLD:
8237 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8238 case EXIT_REASON_APIC_ACCESS:
8239 return nested_cpu_has2(vmcs12,
8240 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8241 case EXIT_REASON_APIC_WRITE:
8242 case EXIT_REASON_EOI_INDUCED:
8243 /* apic_write and eoi_induced should exit unconditionally. */
8245 case EXIT_REASON_EPT_VIOLATION:
8247 * L0 always deals with the EPT violation. If nested EPT is
8248 * used, and the nested mmu code discovers that the address is
8249 * missing in the guest EPT table (EPT12), the EPT violation
8250 * will be injected with nested_ept_inject_page_fault()
8253 case EXIT_REASON_EPT_MISCONFIG:
8255 * L2 never uses directly L1's EPT, but rather L0's own EPT
8256 * table (shadow on EPT) or a merged EPT table that L0 built
8257 * (EPT on EPT). So any problems with the structure of the
8258 * table is L0's fault.
8261 case EXIT_REASON_WBINVD:
8262 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8263 case EXIT_REASON_XSETBV:
8265 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8267 * This should never happen, since it is not possible to
8268 * set XSS to a non-zero value---neither in L1 nor in L2.
8269 * If if it were, XSS would have to be checked against
8270 * the XSS exit bitmap in vmcs12.
8272 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8273 case EXIT_REASON_PREEMPTION_TIMER:
8280 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8282 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8283 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8286 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8289 __free_page(vmx->pml_pg);
8294 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8296 struct vcpu_vmx *vmx = to_vmx(vcpu);
8300 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8302 /* Do nothing if PML buffer is empty */
8303 if (pml_idx == (PML_ENTITY_NUM - 1))
8306 /* PML index always points to next available PML buffer entity */
8307 if (pml_idx >= PML_ENTITY_NUM)
8312 pml_buf = page_address(vmx->pml_pg);
8313 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8316 gpa = pml_buf[pml_idx];
8317 WARN_ON(gpa & (PAGE_SIZE - 1));
8318 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8321 /* reset PML index */
8322 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8326 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8327 * Called before reporting dirty_bitmap to userspace.
8329 static void kvm_flush_pml_buffers(struct kvm *kvm)
8332 struct kvm_vcpu *vcpu;
8334 * We only need to kick vcpu out of guest mode here, as PML buffer
8335 * is flushed at beginning of all VMEXITs, and it's obvious that only
8336 * vcpus running in guest are possible to have unflushed GPAs in PML
8339 kvm_for_each_vcpu(i, vcpu, kvm)
8340 kvm_vcpu_kick(vcpu);
8343 static void vmx_dump_sel(char *name, uint32_t sel)
8345 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8346 name, vmcs_read32(sel),
8347 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8348 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8349 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8352 static void vmx_dump_dtsel(char *name, uint32_t limit)
8354 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8355 name, vmcs_read32(limit),
8356 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8359 static void dump_vmcs(void)
8361 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8362 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8363 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8364 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8365 u32 secondary_exec_control = 0;
8366 unsigned long cr4 = vmcs_readl(GUEST_CR4);
8367 u64 efer = vmcs_read64(GUEST_IA32_EFER);
8370 if (cpu_has_secondary_exec_ctrls())
8371 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8373 pr_err("*** Guest State ***\n");
8374 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8375 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8376 vmcs_readl(CR0_GUEST_HOST_MASK));
8377 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8378 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8379 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8380 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8381 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8383 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8384 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8385 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8386 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8388 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8389 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8390 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8391 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8392 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8393 vmcs_readl(GUEST_SYSENTER_ESP),
8394 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8395 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8396 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8397 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8398 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8399 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8400 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8401 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8402 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8403 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8404 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8405 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8406 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8407 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8408 efer, vmcs_read64(GUEST_IA32_PAT));
8409 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8410 vmcs_read64(GUEST_IA32_DEBUGCTL),
8411 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8412 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8413 pr_err("PerfGlobCtl = 0x%016llx\n",
8414 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8415 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8416 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8417 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8418 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8419 vmcs_read32(GUEST_ACTIVITY_STATE));
8420 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8421 pr_err("InterruptStatus = %04x\n",
8422 vmcs_read16(GUEST_INTR_STATUS));
8424 pr_err("*** Host State ***\n");
8425 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8426 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8427 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8428 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8429 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8430 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8431 vmcs_read16(HOST_TR_SELECTOR));
8432 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8433 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8434 vmcs_readl(HOST_TR_BASE));
8435 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8436 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8437 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8438 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8439 vmcs_readl(HOST_CR4));
8440 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8441 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8442 vmcs_read32(HOST_IA32_SYSENTER_CS),
8443 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8444 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8445 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8446 vmcs_read64(HOST_IA32_EFER),
8447 vmcs_read64(HOST_IA32_PAT));
8448 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8449 pr_err("PerfGlobCtl = 0x%016llx\n",
8450 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8452 pr_err("*** Control State ***\n");
8453 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8454 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8455 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8456 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8457 vmcs_read32(EXCEPTION_BITMAP),
8458 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8459 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8460 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8461 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8462 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8463 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8464 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8465 vmcs_read32(VM_EXIT_INTR_INFO),
8466 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8467 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8468 pr_err(" reason=%08x qualification=%016lx\n",
8469 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8470 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8471 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8472 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8473 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8474 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8475 pr_err("TSC Multiplier = 0x%016llx\n",
8476 vmcs_read64(TSC_MULTIPLIER));
8477 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8478 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8479 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8480 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8481 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8482 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8483 n = vmcs_read32(CR3_TARGET_COUNT);
8484 for (i = 0; i + 1 < n; i += 4)
8485 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8486 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8487 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8489 pr_err("CR3 target%u=%016lx\n",
8490 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8491 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8492 pr_err("PLE Gap=%08x Window=%08x\n",
8493 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8494 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8495 pr_err("Virtual processor ID = 0x%04x\n",
8496 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8500 * The guest has exited. See if we can fix it or if we need userspace
8503 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8505 struct vcpu_vmx *vmx = to_vmx(vcpu);
8506 u32 exit_reason = vmx->exit_reason;
8507 u32 vectoring_info = vmx->idt_vectoring_info;
8509 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8510 vcpu->arch.gpa_available = false;
8513 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8514 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8515 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8516 * mode as if vcpus is in root mode, the PML buffer must has been
8520 vmx_flush_pml_buffer(vcpu);
8522 /* If guest state is invalid, start emulating */
8523 if (vmx->emulation_required)
8524 return handle_invalid_guest_state(vcpu);
8526 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8527 nested_vmx_vmexit(vcpu, exit_reason,
8528 vmcs_read32(VM_EXIT_INTR_INFO),
8529 vmcs_readl(EXIT_QUALIFICATION));
8533 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8535 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8536 vcpu->run->fail_entry.hardware_entry_failure_reason
8541 if (unlikely(vmx->fail)) {
8542 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8543 vcpu->run->fail_entry.hardware_entry_failure_reason
8544 = vmcs_read32(VM_INSTRUCTION_ERROR);
8550 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8551 * delivery event since it indicates guest is accessing MMIO.
8552 * The vm-exit can be triggered again after return to guest that
8553 * will cause infinite loop.
8555 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8556 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8557 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8558 exit_reason != EXIT_REASON_PML_FULL &&
8559 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8560 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8561 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8562 vcpu->run->internal.ndata = 2;
8563 vcpu->run->internal.data[0] = vectoring_info;
8564 vcpu->run->internal.data[1] = exit_reason;
8568 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8569 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8570 get_vmcs12(vcpu))))) {
8571 if (vmx_interrupt_allowed(vcpu)) {
8572 vmx->soft_vnmi_blocked = 0;
8573 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8574 vcpu->arch.nmi_pending) {
8576 * This CPU don't support us in finding the end of an
8577 * NMI-blocked window if the guest runs with IRQs
8578 * disabled. So we pull the trigger after 1 s of
8579 * futile waiting, but inform the user about this.
8581 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8582 "state on VCPU %d after 1 s timeout\n",
8583 __func__, vcpu->vcpu_id);
8584 vmx->soft_vnmi_blocked = 0;
8588 if (exit_reason < kvm_vmx_max_exit_handlers
8589 && kvm_vmx_exit_handlers[exit_reason])
8590 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8592 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8593 kvm_queue_exception(vcpu, UD_VECTOR);
8598 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8600 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8602 if (is_guest_mode(vcpu) &&
8603 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8606 if (irr == -1 || tpr < irr) {
8607 vmcs_write32(TPR_THRESHOLD, 0);
8611 vmcs_write32(TPR_THRESHOLD, irr);
8614 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8616 u32 sec_exec_control;
8618 /* Postpone execution until vmcs01 is the current VMCS. */
8619 if (is_guest_mode(vcpu)) {
8620 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8624 if (!cpu_has_vmx_virtualize_x2apic_mode())
8627 if (!cpu_need_tpr_shadow(vcpu))
8630 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8633 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8634 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8636 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8637 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8639 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8641 vmx_set_msr_bitmap(vcpu);
8644 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8646 struct vcpu_vmx *vmx = to_vmx(vcpu);
8649 * Currently we do not handle the nested case where L2 has an
8650 * APIC access page of its own; that page is still pinned.
8651 * Hence, we skip the case where the VCPU is in guest mode _and_
8652 * L1 prepared an APIC access page for L2.
8654 * For the case where L1 and L2 share the same APIC access page
8655 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8656 * in the vmcs12), this function will only update either the vmcs01
8657 * or the vmcs02. If the former, the vmcs02 will be updated by
8658 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8659 * the next L2->L1 exit.
8661 if (!is_guest_mode(vcpu) ||
8662 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8663 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8664 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8667 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8675 status = vmcs_read16(GUEST_INTR_STATUS);
8677 if (max_isr != old) {
8679 status |= max_isr << 8;
8680 vmcs_write16(GUEST_INTR_STATUS, status);
8684 static void vmx_set_rvi(int vector)
8692 status = vmcs_read16(GUEST_INTR_STATUS);
8693 old = (u8)status & 0xff;
8694 if ((u8)vector != old) {
8696 status |= (u8)vector;
8697 vmcs_write16(GUEST_INTR_STATUS, status);
8701 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8703 if (!is_guest_mode(vcpu)) {
8704 vmx_set_rvi(max_irr);
8712 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8715 if (nested_exit_on_intr(vcpu))
8719 * Else, fall back to pre-APICv interrupt injection since L2
8720 * is run without virtual interrupt delivery.
8722 if (!kvm_event_needs_reinjection(vcpu) &&
8723 vmx_interrupt_allowed(vcpu)) {
8724 kvm_queue_interrupt(vcpu, max_irr, false);
8725 vmx_inject_irq(vcpu);
8729 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8731 struct vcpu_vmx *vmx = to_vmx(vcpu);
8734 WARN_ON(!vcpu->arch.apicv_active);
8735 if (pi_test_on(&vmx->pi_desc)) {
8736 pi_clear_on(&vmx->pi_desc);
8738 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8739 * But on x86 this is just a compiler barrier anyway.
8741 smp_mb__after_atomic();
8742 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8744 max_irr = kvm_lapic_find_highest_irr(vcpu);
8746 vmx_hwapic_irr_update(vcpu, max_irr);
8750 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8752 if (!kvm_vcpu_apicv_active(vcpu))
8755 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8756 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8757 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8758 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8761 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8763 struct vcpu_vmx *vmx = to_vmx(vcpu);
8765 pi_clear_on(&vmx->pi_desc);
8766 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8769 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8773 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8774 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8777 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8778 exit_intr_info = vmx->exit_intr_info;
8780 /* Handle machine checks before interrupts are enabled */
8781 if (is_machine_check(exit_intr_info))
8782 kvm_machine_check();
8784 /* We need to handle NMIs before interrupts are enabled */
8785 if (is_nmi(exit_intr_info)) {
8786 kvm_before_handle_nmi(&vmx->vcpu);
8788 kvm_after_handle_nmi(&vmx->vcpu);
8792 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8794 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8795 register void *__sp asm(_ASM_SP);
8797 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8798 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8799 unsigned int vector;
8800 unsigned long entry;
8802 struct vcpu_vmx *vmx = to_vmx(vcpu);
8803 #ifdef CONFIG_X86_64
8807 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8808 desc = (gate_desc *)vmx->host_idt_base + vector;
8809 entry = gate_offset(*desc);
8811 #ifdef CONFIG_X86_64
8812 "mov %%" _ASM_SP ", %[sp]\n\t"
8813 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8818 __ASM_SIZE(push) " $%c[cs]\n\t"
8819 "call *%[entry]\n\t"
8821 #ifdef CONFIG_X86_64
8827 [ss]"i"(__KERNEL_DS),
8828 [cs]"i"(__KERNEL_CS)
8833 static bool vmx_has_high_real_mode_segbase(void)
8835 return enable_unrestricted_guest || emulate_invalid_guest_state;
8838 static bool vmx_mpx_supported(void)
8840 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8841 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8844 static bool vmx_xsaves_supported(void)
8846 return vmcs_config.cpu_based_2nd_exec_ctrl &
8847 SECONDARY_EXEC_XSAVES;
8850 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8855 bool idtv_info_valid;
8857 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8859 if (cpu_has_virtual_nmis()) {
8860 if (vmx->nmi_known_unmasked)
8863 * Can't use vmx->exit_intr_info since we're not sure what
8864 * the exit reason is.
8866 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8867 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8868 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8870 * SDM 3: 27.7.1.2 (September 2008)
8871 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8872 * a guest IRET fault.
8873 * SDM 3: 23.2.2 (September 2008)
8874 * Bit 12 is undefined in any of the following cases:
8875 * If the VM exit sets the valid bit in the IDT-vectoring
8876 * information field.
8877 * If the VM exit is due to a double fault.
8879 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8880 vector != DF_VECTOR && !idtv_info_valid)
8881 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8882 GUEST_INTR_STATE_NMI);
8884 vmx->nmi_known_unmasked =
8885 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8886 & GUEST_INTR_STATE_NMI);
8887 } else if (unlikely(vmx->soft_vnmi_blocked))
8888 vmx->vnmi_blocked_time +=
8889 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8892 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8893 u32 idt_vectoring_info,
8894 int instr_len_field,
8895 int error_code_field)
8899 bool idtv_info_valid;
8901 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8903 vcpu->arch.nmi_injected = false;
8904 kvm_clear_exception_queue(vcpu);
8905 kvm_clear_interrupt_queue(vcpu);
8907 if (!idtv_info_valid)
8910 kvm_make_request(KVM_REQ_EVENT, vcpu);
8912 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8913 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8916 case INTR_TYPE_NMI_INTR:
8917 vcpu->arch.nmi_injected = true;
8919 * SDM 3: 27.7.1.2 (September 2008)
8920 * Clear bit "block by NMI" before VM entry if a NMI
8923 vmx_set_nmi_mask(vcpu, false);
8925 case INTR_TYPE_SOFT_EXCEPTION:
8926 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8928 case INTR_TYPE_HARD_EXCEPTION:
8929 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8930 u32 err = vmcs_read32(error_code_field);
8931 kvm_requeue_exception_e(vcpu, vector, err);
8933 kvm_requeue_exception(vcpu, vector);
8935 case INTR_TYPE_SOFT_INTR:
8936 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8938 case INTR_TYPE_EXT_INTR:
8939 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8946 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8948 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8949 VM_EXIT_INSTRUCTION_LEN,
8950 IDT_VECTORING_ERROR_CODE);
8953 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8955 __vmx_complete_interrupts(vcpu,
8956 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8957 VM_ENTRY_INSTRUCTION_LEN,
8958 VM_ENTRY_EXCEPTION_ERROR_CODE);
8960 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8963 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8966 struct perf_guest_switch_msr *msrs;
8968 msrs = perf_guest_get_msrs(&nr_msrs);
8973 for (i = 0; i < nr_msrs; i++)
8974 if (msrs[i].host == msrs[i].guest)
8975 clear_atomic_switch_msr(vmx, msrs[i].msr);
8977 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8981 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8983 struct vcpu_vmx *vmx = to_vmx(vcpu);
8987 if (vmx->hv_deadline_tsc == -1)
8991 if (vmx->hv_deadline_tsc > tscl)
8992 /* sure to be 32 bit only because checked on set_hv_timer */
8993 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8994 cpu_preemption_timer_multi);
8998 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9001 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9003 struct vcpu_vmx *vmx = to_vmx(vcpu);
9004 unsigned long debugctlmsr, cr4;
9006 /* Record the guest's net vcpu time for enforced NMI injections. */
9007 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
9008 vmx->entry_time = ktime_get();
9010 /* Don't enter VMX if guest state is invalid, let the exit handler
9011 start emulation until we arrive back to a valid state */
9012 if (vmx->emulation_required)
9015 if (vmx->ple_window_dirty) {
9016 vmx->ple_window_dirty = false;
9017 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9020 if (vmx->nested.sync_shadow_vmcs) {
9021 copy_vmcs12_to_shadow(vmx);
9022 vmx->nested.sync_shadow_vmcs = false;
9025 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9026 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9027 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9028 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9030 cr4 = cr4_read_shadow();
9031 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
9032 vmcs_writel(HOST_CR4, cr4);
9033 vmx->host_state.vmcs_host_cr4 = cr4;
9036 /* When single-stepping over STI and MOV SS, we must clear the
9037 * corresponding interruptibility bits in the guest state. Otherwise
9038 * vmentry fails as it then expects bit 14 (BS) in pending debug
9039 * exceptions being set, but that's not correct for the guest debugging
9041 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9042 vmx_set_interrupt_shadow(vcpu, 0);
9044 if (vmx->guest_pkru_valid)
9045 __write_pkru(vmx->guest_pkru);
9047 atomic_switch_perf_msrs(vmx);
9048 debugctlmsr = get_debugctlmsr();
9050 vmx_arm_hv_timer(vcpu);
9052 vmx->__launched = vmx->loaded_vmcs->launched;
9054 /* Store host registers */
9055 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9056 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9057 "push %%" _ASM_CX " \n\t"
9058 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9060 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9061 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9063 /* Reload cr2 if changed */
9064 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9065 "mov %%cr2, %%" _ASM_DX " \n\t"
9066 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9068 "mov %%" _ASM_AX", %%cr2 \n\t"
9070 /* Check if vmlaunch of vmresume is needed */
9071 "cmpl $0, %c[launched](%0) \n\t"
9072 /* Load guest registers. Don't clobber flags. */
9073 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9074 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9075 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9076 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9077 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9078 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9079 #ifdef CONFIG_X86_64
9080 "mov %c[r8](%0), %%r8 \n\t"
9081 "mov %c[r9](%0), %%r9 \n\t"
9082 "mov %c[r10](%0), %%r10 \n\t"
9083 "mov %c[r11](%0), %%r11 \n\t"
9084 "mov %c[r12](%0), %%r12 \n\t"
9085 "mov %c[r13](%0), %%r13 \n\t"
9086 "mov %c[r14](%0), %%r14 \n\t"
9087 "mov %c[r15](%0), %%r15 \n\t"
9089 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9091 /* Enter guest mode */
9093 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9095 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9097 /* Save guest registers, load host registers, keep flags */
9098 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9100 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9101 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9102 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9103 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9104 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9105 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9106 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9107 #ifdef CONFIG_X86_64
9108 "mov %%r8, %c[r8](%0) \n\t"
9109 "mov %%r9, %c[r9](%0) \n\t"
9110 "mov %%r10, %c[r10](%0) \n\t"
9111 "mov %%r11, %c[r11](%0) \n\t"
9112 "mov %%r12, %c[r12](%0) \n\t"
9113 "mov %%r13, %c[r13](%0) \n\t"
9114 "mov %%r14, %c[r14](%0) \n\t"
9115 "mov %%r15, %c[r15](%0) \n\t"
9117 "mov %%cr2, %%" _ASM_AX " \n\t"
9118 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9120 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
9121 "setbe %c[fail](%0) \n\t"
9122 ".pushsection .rodata \n\t"
9123 ".global vmx_return \n\t"
9124 "vmx_return: " _ASM_PTR " 2b \n\t"
9126 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9127 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9128 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9129 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9130 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9131 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9132 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9133 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9134 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9135 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9136 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9137 #ifdef CONFIG_X86_64
9138 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9139 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9140 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9141 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9142 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9143 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9144 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9145 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9147 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9148 [wordsize]"i"(sizeof(ulong))
9150 #ifdef CONFIG_X86_64
9151 , "rax", "rbx", "rdi", "rsi"
9152 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9154 , "eax", "ebx", "edi", "esi"
9158 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9160 update_debugctlmsr(debugctlmsr);
9162 #ifndef CONFIG_X86_64
9164 * The sysexit path does not restore ds/es, so we must set them to
9165 * a reasonable value ourselves.
9167 * We can't defer this to vmx_load_host_state() since that function
9168 * may be executed in interrupt context, which saves and restore segments
9169 * around it, nullifying its effect.
9171 loadsegment(ds, __USER_DS);
9172 loadsegment(es, __USER_DS);
9175 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9176 | (1 << VCPU_EXREG_RFLAGS)
9177 | (1 << VCPU_EXREG_PDPTR)
9178 | (1 << VCPU_EXREG_SEGMENTS)
9179 | (1 << VCPU_EXREG_CR3));
9180 vcpu->arch.regs_dirty = 0;
9182 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9184 vmx->loaded_vmcs->launched = 1;
9186 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9189 * eager fpu is enabled if PKEY is supported and CR4 is switched
9190 * back on host, so it is safe to read guest PKRU from current
9193 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9194 vmx->guest_pkru = __read_pkru();
9195 if (vmx->guest_pkru != vmx->host_pkru) {
9196 vmx->guest_pkru_valid = true;
9197 __write_pkru(vmx->host_pkru);
9199 vmx->guest_pkru_valid = false;
9203 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9204 * we did not inject a still-pending event to L1 now because of
9205 * nested_run_pending, we need to re-enable this bit.
9207 if (vmx->nested.nested_run_pending)
9208 kvm_make_request(KVM_REQ_EVENT, vcpu);
9210 vmx->nested.nested_run_pending = 0;
9212 vmx_complete_atomic_exit(vmx);
9213 vmx_recover_nmi_blocking(vmx);
9214 vmx_complete_interrupts(vmx);
9217 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9219 struct vcpu_vmx *vmx = to_vmx(vcpu);
9222 if (vmx->loaded_vmcs == &vmx->vmcs01)
9226 vmx->loaded_vmcs = &vmx->vmcs01;
9228 vmx_vcpu_load(vcpu, cpu);
9234 * Ensure that the current vmcs of the logical processor is the
9235 * vmcs01 of the vcpu before calling free_nested().
9237 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9239 struct vcpu_vmx *vmx = to_vmx(vcpu);
9242 r = vcpu_load(vcpu);
9244 vmx_load_vmcs01(vcpu);
9249 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9251 struct vcpu_vmx *vmx = to_vmx(vcpu);
9254 vmx_destroy_pml_buffer(vmx);
9255 free_vpid(vmx->vpid);
9256 leave_guest_mode(vcpu);
9257 vmx_free_vcpu_nested(vcpu);
9258 free_loaded_vmcs(vmx->loaded_vmcs);
9259 kfree(vmx->guest_msrs);
9260 kvm_vcpu_uninit(vcpu);
9261 kmem_cache_free(kvm_vcpu_cache, vmx);
9264 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9267 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9271 return ERR_PTR(-ENOMEM);
9273 vmx->vpid = allocate_vpid();
9275 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9282 * If PML is turned on, failure on enabling PML just results in failure
9283 * of creating the vcpu, therefore we can simplify PML logic (by
9284 * avoiding dealing with cases, such as enabling PML partially on vcpus
9285 * for the guest, etc.
9288 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9293 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9294 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9297 if (!vmx->guest_msrs)
9300 vmx->loaded_vmcs = &vmx->vmcs01;
9301 vmx->loaded_vmcs->vmcs = alloc_vmcs();
9302 vmx->loaded_vmcs->shadow_vmcs = NULL;
9303 if (!vmx->loaded_vmcs->vmcs)
9306 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9307 loaded_vmcs_init(vmx->loaded_vmcs);
9312 vmx_vcpu_load(&vmx->vcpu, cpu);
9313 vmx->vcpu.cpu = cpu;
9314 err = vmx_vcpu_setup(vmx);
9315 vmx_vcpu_put(&vmx->vcpu);
9319 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9320 err = alloc_apic_access_page(kvm);
9326 if (!kvm->arch.ept_identity_map_addr)
9327 kvm->arch.ept_identity_map_addr =
9328 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9329 err = init_rmode_identity_map(kvm);
9335 nested_vmx_setup_ctls_msrs(vmx);
9336 vmx->nested.vpid02 = allocate_vpid();
9339 vmx->nested.posted_intr_nv = -1;
9340 vmx->nested.current_vmptr = -1ull;
9341 vmx->nested.current_vmcs12 = NULL;
9343 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9348 free_vpid(vmx->nested.vpid02);
9349 free_loaded_vmcs(vmx->loaded_vmcs);
9351 kfree(vmx->guest_msrs);
9353 vmx_destroy_pml_buffer(vmx);
9355 kvm_vcpu_uninit(&vmx->vcpu);
9357 free_vpid(vmx->vpid);
9358 kmem_cache_free(kvm_vcpu_cache, vmx);
9359 return ERR_PTR(err);
9362 static void __init vmx_check_processor_compat(void *rtn)
9364 struct vmcs_config vmcs_conf;
9367 if (setup_vmcs_config(&vmcs_conf) < 0)
9369 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9370 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9371 smp_processor_id());
9376 static int get_ept_level(void)
9378 return VMX_EPT_DEFAULT_GAW + 1;
9381 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9386 /* For VT-d and EPT combination
9387 * 1. MMIO: always map as UC
9389 * a. VT-d without snooping control feature: can't guarantee the
9390 * result, try to trust guest.
9391 * b. VT-d with snooping control feature: snooping control feature of
9392 * VT-d engine can guarantee the cache correctness. Just set it
9393 * to WB to keep consistent with host. So the same as item 3.
9394 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9395 * consistent with host MTRR
9398 cache = MTRR_TYPE_UNCACHABLE;
9402 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9403 ipat = VMX_EPT_IPAT_BIT;
9404 cache = MTRR_TYPE_WRBACK;
9408 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9409 ipat = VMX_EPT_IPAT_BIT;
9410 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9411 cache = MTRR_TYPE_WRBACK;
9413 cache = MTRR_TYPE_UNCACHABLE;
9417 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9420 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9423 static int vmx_get_lpage_level(void)
9425 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9426 return PT_DIRECTORY_LEVEL;
9428 /* For shadow and EPT supported 1GB page */
9429 return PT_PDPE_LEVEL;
9432 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9435 * These bits in the secondary execution controls field
9436 * are dynamic, the others are mostly based on the hypervisor
9437 * architecture and the guest's CPUID. Do not touch the
9441 SECONDARY_EXEC_SHADOW_VMCS |
9442 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9443 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9445 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9447 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9448 (new_ctl & ~mask) | (cur_ctl & mask));
9452 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9453 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9455 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9457 struct vcpu_vmx *vmx = to_vmx(vcpu);
9458 struct kvm_cpuid_entry2 *entry;
9460 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9461 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9463 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9464 if (entry && (entry->_reg & (_cpuid_mask))) \
9465 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9468 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9469 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9470 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9471 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9472 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9473 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9474 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9475 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9476 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9477 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9478 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9479 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9480 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9481 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9482 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9484 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9485 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9486 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9487 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9488 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9489 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9490 cr4_fixed1_update(bit(11), ecx, bit(2));
9492 #undef cr4_fixed1_update
9495 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9497 struct kvm_cpuid_entry2 *best;
9498 struct vcpu_vmx *vmx = to_vmx(vcpu);
9499 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9501 if (vmx_rdtscp_supported()) {
9502 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9503 if (!rdtscp_enabled)
9504 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9508 vmx->nested.nested_vmx_secondary_ctls_high |=
9509 SECONDARY_EXEC_RDTSCP;
9511 vmx->nested.nested_vmx_secondary_ctls_high &=
9512 ~SECONDARY_EXEC_RDTSCP;
9516 /* Exposing INVPCID only when PCID is exposed */
9517 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9518 if (vmx_invpcid_supported() &&
9519 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9520 !guest_cpuid_has_pcid(vcpu))) {
9521 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9524 best->ebx &= ~bit(X86_FEATURE_INVPCID);
9527 if (cpu_has_secondary_exec_ctrls())
9528 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9530 if (nested_vmx_allowed(vcpu))
9531 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9532 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9534 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9535 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9537 if (nested_vmx_allowed(vcpu))
9538 nested_vmx_cr_fixed1_bits_update(vcpu);
9541 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9543 if (func == 1 && nested)
9544 entry->ecx |= bit(X86_FEATURE_VMX);
9547 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9548 struct x86_exception *fault)
9550 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9553 if (fault->error_code & PFERR_RSVD_MASK)
9554 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9556 exit_reason = EXIT_REASON_EPT_VIOLATION;
9557 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9558 vmcs12->guest_physical_address = fault->address;
9561 /* Callbacks for nested_ept_init_mmu_context: */
9563 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9565 /* return the page table to be shadowed - in our case, EPT12 */
9566 return get_vmcs12(vcpu)->ept_pointer;
9569 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9571 WARN_ON(mmu_is_nested(vcpu));
9572 kvm_init_shadow_ept_mmu(vcpu,
9573 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9574 VMX_EPT_EXECUTE_ONLY_BIT);
9575 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9576 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9577 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9579 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
9582 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9584 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9587 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9590 bool inequality, bit;
9592 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9594 (error_code & vmcs12->page_fault_error_code_mask) !=
9595 vmcs12->page_fault_error_code_match;
9596 return inequality ^ bit;
9599 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9600 struct x86_exception *fault)
9602 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9604 WARN_ON(!is_guest_mode(vcpu));
9606 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9607 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9608 vmcs_read32(VM_EXIT_INTR_INFO),
9609 vmcs_readl(EXIT_QUALIFICATION));
9611 kvm_inject_page_fault(vcpu, fault);
9614 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9615 struct vmcs12 *vmcs12)
9617 struct vcpu_vmx *vmx = to_vmx(vcpu);
9618 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9620 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9621 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9622 vmcs12->apic_access_addr >> maxphyaddr)
9626 * Translate L1 physical address to host physical
9627 * address for vmcs02. Keep the page pinned, so this
9628 * physical address remains valid. We keep a reference
9629 * to it so we can release it later.
9631 if (vmx->nested.apic_access_page) /* shouldn't happen */
9632 nested_release_page(vmx->nested.apic_access_page);
9633 vmx->nested.apic_access_page =
9634 nested_get_page(vcpu, vmcs12->apic_access_addr);
9637 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9638 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9639 vmcs12->virtual_apic_page_addr >> maxphyaddr)
9642 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9643 nested_release_page(vmx->nested.virtual_apic_page);
9644 vmx->nested.virtual_apic_page =
9645 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9648 * Failing the vm entry is _not_ what the processor does
9649 * but it's basically the only possibility we have.
9650 * We could still enter the guest if CR8 load exits are
9651 * enabled, CR8 store exits are enabled, and virtualize APIC
9652 * access is disabled; in this case the processor would never
9653 * use the TPR shadow and we could simply clear the bit from
9654 * the execution control. But such a configuration is useless,
9655 * so let's keep the code simple.
9657 if (!vmx->nested.virtual_apic_page)
9661 if (nested_cpu_has_posted_intr(vmcs12)) {
9662 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9663 vmcs12->posted_intr_desc_addr >> maxphyaddr)
9666 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9667 kunmap(vmx->nested.pi_desc_page);
9668 nested_release_page(vmx->nested.pi_desc_page);
9670 vmx->nested.pi_desc_page =
9671 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9672 if (!vmx->nested.pi_desc_page)
9675 vmx->nested.pi_desc =
9676 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9677 if (!vmx->nested.pi_desc) {
9678 nested_release_page_clean(vmx->nested.pi_desc_page);
9681 vmx->nested.pi_desc =
9682 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9683 (unsigned long)(vmcs12->posted_intr_desc_addr &
9690 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9692 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9693 struct vcpu_vmx *vmx = to_vmx(vcpu);
9695 if (vcpu->arch.virtual_tsc_khz == 0)
9698 /* Make sure short timeouts reliably trigger an immediate vmexit.
9699 * hrtimer_start does not guarantee this. */
9700 if (preemption_timeout <= 1) {
9701 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9705 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9706 preemption_timeout *= 1000000;
9707 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9708 hrtimer_start(&vmx->nested.preemption_timer,
9709 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9712 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9713 struct vmcs12 *vmcs12)
9718 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9721 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9725 maxphyaddr = cpuid_maxphyaddr(vcpu);
9727 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9728 ((addr + PAGE_SIZE) >> maxphyaddr))
9735 * Merge L0's and L1's MSR bitmap, return false to indicate that
9736 * we do not use the hardware.
9738 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9739 struct vmcs12 *vmcs12)
9743 unsigned long *msr_bitmap_l1;
9744 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9746 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9747 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9750 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9755 msr_bitmap_l1 = (unsigned long *)kmap(page);
9757 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9759 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9760 if (nested_cpu_has_apic_reg_virt(vmcs12))
9761 for (msr = 0x800; msr <= 0x8ff; msr++)
9762 nested_vmx_disable_intercept_for_msr(
9763 msr_bitmap_l1, msr_bitmap_l0,
9766 nested_vmx_disable_intercept_for_msr(
9767 msr_bitmap_l1, msr_bitmap_l0,
9768 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9769 MSR_TYPE_R | MSR_TYPE_W);
9771 if (nested_cpu_has_vid(vmcs12)) {
9772 nested_vmx_disable_intercept_for_msr(
9773 msr_bitmap_l1, msr_bitmap_l0,
9774 APIC_BASE_MSR + (APIC_EOI >> 4),
9776 nested_vmx_disable_intercept_for_msr(
9777 msr_bitmap_l1, msr_bitmap_l0,
9778 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9783 nested_release_page_clean(page);
9788 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9789 struct vmcs12 *vmcs12)
9791 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9792 !nested_cpu_has_apic_reg_virt(vmcs12) &&
9793 !nested_cpu_has_vid(vmcs12) &&
9794 !nested_cpu_has_posted_intr(vmcs12))
9798 * If virtualize x2apic mode is enabled,
9799 * virtualize apic access must be disabled.
9801 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9802 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9806 * If virtual interrupt delivery is enabled,
9807 * we must exit on external interrupts.
9809 if (nested_cpu_has_vid(vmcs12) &&
9810 !nested_exit_on_intr(vcpu))
9814 * bits 15:8 should be zero in posted_intr_nv,
9815 * the descriptor address has been already checked
9816 * in nested_get_vmcs12_pages.
9818 if (nested_cpu_has_posted_intr(vmcs12) &&
9819 (!nested_cpu_has_vid(vmcs12) ||
9820 !nested_exit_intr_ack_set(vcpu) ||
9821 vmcs12->posted_intr_nv & 0xff00))
9824 /* tpr shadow is needed by all apicv features. */
9825 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9831 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9832 unsigned long count_field,
9833 unsigned long addr_field)
9838 if (vmcs12_read_any(vcpu, count_field, &count) ||
9839 vmcs12_read_any(vcpu, addr_field, &addr)) {
9845 maxphyaddr = cpuid_maxphyaddr(vcpu);
9846 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9847 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9848 pr_debug_ratelimited(
9849 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9850 addr_field, maxphyaddr, count, addr);
9856 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9857 struct vmcs12 *vmcs12)
9859 if (vmcs12->vm_exit_msr_load_count == 0 &&
9860 vmcs12->vm_exit_msr_store_count == 0 &&
9861 vmcs12->vm_entry_msr_load_count == 0)
9862 return 0; /* Fast path */
9863 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9864 VM_EXIT_MSR_LOAD_ADDR) ||
9865 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9866 VM_EXIT_MSR_STORE_ADDR) ||
9867 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9868 VM_ENTRY_MSR_LOAD_ADDR))
9873 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9874 struct vmx_msr_entry *e)
9876 /* x2APIC MSR accesses are not allowed */
9877 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9879 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9880 e->index == MSR_IA32_UCODE_REV)
9882 if (e->reserved != 0)
9887 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9888 struct vmx_msr_entry *e)
9890 if (e->index == MSR_FS_BASE ||
9891 e->index == MSR_GS_BASE ||
9892 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9893 nested_vmx_msr_check_common(vcpu, e))
9898 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9899 struct vmx_msr_entry *e)
9901 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9902 nested_vmx_msr_check_common(vcpu, e))
9908 * Load guest's/host's msr at nested entry/exit.
9909 * return 0 for success, entry index for failure.
9911 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9914 struct vmx_msr_entry e;
9915 struct msr_data msr;
9917 msr.host_initiated = false;
9918 for (i = 0; i < count; i++) {
9919 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9921 pr_debug_ratelimited(
9922 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9923 __func__, i, gpa + i * sizeof(e));
9926 if (nested_vmx_load_msr_check(vcpu, &e)) {
9927 pr_debug_ratelimited(
9928 "%s check failed (%u, 0x%x, 0x%x)\n",
9929 __func__, i, e.index, e.reserved);
9932 msr.index = e.index;
9934 if (kvm_set_msr(vcpu, &msr)) {
9935 pr_debug_ratelimited(
9936 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9937 __func__, i, e.index, e.value);
9946 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9949 struct vmx_msr_entry e;
9951 for (i = 0; i < count; i++) {
9952 struct msr_data msr_info;
9953 if (kvm_vcpu_read_guest(vcpu,
9954 gpa + i * sizeof(e),
9955 &e, 2 * sizeof(u32))) {
9956 pr_debug_ratelimited(
9957 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9958 __func__, i, gpa + i * sizeof(e));
9961 if (nested_vmx_store_msr_check(vcpu, &e)) {
9962 pr_debug_ratelimited(
9963 "%s check failed (%u, 0x%x, 0x%x)\n",
9964 __func__, i, e.index, e.reserved);
9967 msr_info.host_initiated = false;
9968 msr_info.index = e.index;
9969 if (kvm_get_msr(vcpu, &msr_info)) {
9970 pr_debug_ratelimited(
9971 "%s cannot read MSR (%u, 0x%x)\n",
9972 __func__, i, e.index);
9975 if (kvm_vcpu_write_guest(vcpu,
9976 gpa + i * sizeof(e) +
9977 offsetof(struct vmx_msr_entry, value),
9978 &msr_info.data, sizeof(msr_info.data))) {
9979 pr_debug_ratelimited(
9980 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9981 __func__, i, e.index, msr_info.data);
9988 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9990 unsigned long invalid_mask;
9992 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9993 return (val & invalid_mask) == 0;
9997 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9998 * emulating VM entry into a guest with EPT enabled.
9999 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10000 * is assigned to entry_failure_code on failure.
10002 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10003 unsigned long *entry_failure_code)
10005 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10006 if (!nested_cr3_valid(vcpu, cr3)) {
10007 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10012 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10013 * must not be dereferenced.
10015 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10017 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10018 *entry_failure_code = ENTRY_FAIL_PDPTE;
10023 vcpu->arch.cr3 = cr3;
10024 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10027 kvm_mmu_reset_context(vcpu);
10032 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10033 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10034 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10035 * guest in a way that will both be appropriate to L1's requests, and our
10036 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10037 * function also has additional necessary side-effects, like setting various
10038 * vcpu->arch fields.
10039 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10040 * is assigned to entry_failure_code on failure.
10042 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10043 unsigned long *entry_failure_code)
10045 struct vcpu_vmx *vmx = to_vmx(vcpu);
10047 bool nested_ept_enabled = false;
10049 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10050 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10051 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10052 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10053 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10054 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10055 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10056 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10057 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10058 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10059 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10060 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10061 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10062 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10063 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10064 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10065 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10066 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10067 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10068 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10069 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10070 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10071 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10072 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10073 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10074 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10075 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10076 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10077 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10078 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10079 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10080 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10081 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10082 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10083 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10084 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10086 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
10087 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10088 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10090 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10091 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10093 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10094 vmcs12->vm_entry_intr_info_field);
10095 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10096 vmcs12->vm_entry_exception_error_code);
10097 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10098 vmcs12->vm_entry_instruction_len);
10099 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10100 vmcs12->guest_interruptibility_info);
10101 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10102 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10103 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10104 vmcs12->guest_pending_dbg_exceptions);
10105 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10106 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10108 if (nested_cpu_has_xsaves(vmcs12))
10109 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10110 vmcs_write64(VMCS_LINK_POINTER, -1ull);
10112 exec_control = vmcs12->pin_based_vm_exec_control;
10114 /* Preemption timer setting is only taken from vmcs01. */
10115 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10116 exec_control |= vmcs_config.pin_based_exec_ctrl;
10117 if (vmx->hv_deadline_tsc == -1)
10118 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10120 /* Posted interrupts setting is only taken from vmcs12. */
10121 if (nested_cpu_has_posted_intr(vmcs12)) {
10123 * Note that we use L0's vector here and in
10124 * vmx_deliver_nested_posted_interrupt.
10126 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10127 vmx->nested.pi_pending = false;
10128 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10129 vmcs_write64(POSTED_INTR_DESC_ADDR,
10130 page_to_phys(vmx->nested.pi_desc_page) +
10131 (unsigned long)(vmcs12->posted_intr_desc_addr &
10134 exec_control &= ~PIN_BASED_POSTED_INTR;
10136 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10138 vmx->nested.preemption_timer_expired = false;
10139 if (nested_cpu_has_preemption_timer(vmcs12))
10140 vmx_start_preemption_timer(vcpu);
10143 * Whether page-faults are trapped is determined by a combination of
10144 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10145 * If enable_ept, L0 doesn't care about page faults and we should
10146 * set all of these to L1's desires. However, if !enable_ept, L0 does
10147 * care about (at least some) page faults, and because it is not easy
10148 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10149 * to exit on each and every L2 page fault. This is done by setting
10150 * MASK=MATCH=0 and (see below) EB.PF=1.
10151 * Note that below we don't need special code to set EB.PF beyond the
10152 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10153 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10154 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10156 * A problem with this approach (when !enable_ept) is that L1 may be
10157 * injected with more page faults than it asked for. This could have
10158 * caused problems, but in practice existing hypervisors don't care.
10159 * To fix this, we will need to emulate the PFEC checking (on the L1
10160 * page tables), using walk_addr(), when injecting PFs to L1.
10162 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10163 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10164 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10165 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10167 if (cpu_has_secondary_exec_ctrls()) {
10168 exec_control = vmx_secondary_exec_control(vmx);
10170 /* Take the following fields only from vmcs12 */
10171 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10172 SECONDARY_EXEC_RDTSCP |
10173 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10174 SECONDARY_EXEC_APIC_REGISTER_VIRT);
10175 if (nested_cpu_has(vmcs12,
10176 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10177 exec_control |= vmcs12->secondary_vm_exec_control;
10179 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
10181 * If translation failed, no matter: This feature asks
10182 * to exit when accessing the given address, and if it
10183 * can never be accessed, this feature won't do
10186 if (!vmx->nested.apic_access_page)
10188 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
10190 vmcs_write64(APIC_ACCESS_ADDR,
10191 page_to_phys(vmx->nested.apic_access_page));
10192 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
10193 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10195 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
10196 kvm_vcpu_reload_apic_access_page(vcpu);
10199 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10200 vmcs_write64(EOI_EXIT_BITMAP0,
10201 vmcs12->eoi_exit_bitmap0);
10202 vmcs_write64(EOI_EXIT_BITMAP1,
10203 vmcs12->eoi_exit_bitmap1);
10204 vmcs_write64(EOI_EXIT_BITMAP2,
10205 vmcs12->eoi_exit_bitmap2);
10206 vmcs_write64(EOI_EXIT_BITMAP3,
10207 vmcs12->eoi_exit_bitmap3);
10208 vmcs_write16(GUEST_INTR_STATUS,
10209 vmcs12->guest_intr_status);
10212 nested_ept_enabled = (exec_control & SECONDARY_EXEC_ENABLE_EPT) != 0;
10213 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10218 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10219 * Some constant fields are set here by vmx_set_constant_host_state().
10220 * Other fields are different per CPU, and will be set later when
10221 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10223 vmx_set_constant_host_state(vmx);
10226 * Set the MSR load/store lists to match L0's settings.
10228 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10229 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10230 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10231 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10232 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10235 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10236 * entry, but only if the current (host) sp changed from the value
10237 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10238 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10239 * here we just force the write to happen on entry.
10243 exec_control = vmx_exec_control(vmx); /* L0's desires */
10244 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10245 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10246 exec_control &= ~CPU_BASED_TPR_SHADOW;
10247 exec_control |= vmcs12->cpu_based_vm_exec_control;
10249 if (exec_control & CPU_BASED_TPR_SHADOW) {
10250 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
10251 page_to_phys(vmx->nested.virtual_apic_page));
10252 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10255 if (cpu_has_vmx_msr_bitmap() &&
10256 exec_control & CPU_BASED_USE_MSR_BITMAPS &&
10257 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
10258 ; /* MSR_BITMAP will be set by following vmx_set_efer. */
10260 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
10263 * Merging of IO bitmap not currently supported.
10264 * Rather, exit every time.
10266 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10267 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10269 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10271 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10272 * bitwise-or of what L1 wants to trap for L2, and what we want to
10273 * trap. Note that CR0.TS also needs updating - we do this later.
10275 update_exception_bitmap(vcpu);
10276 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10277 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10279 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10280 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10281 * bits are further modified by vmx_set_efer() below.
10283 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10285 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10286 * emulated by vmx_set_efer(), below.
10288 vm_entry_controls_init(vmx,
10289 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10290 ~VM_ENTRY_IA32E_MODE) |
10291 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10293 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
10294 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10295 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10296 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
10297 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10300 set_cr4_guest_host_mask(vmx);
10302 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10303 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10305 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10306 vmcs_write64(TSC_OFFSET,
10307 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10309 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10310 if (kvm_has_tsc_control)
10311 decache_tsc_multiplier(vmx);
10315 * There is no direct mapping between vpid02 and vpid12, the
10316 * vpid02 is per-vCPU for L0 and reused while the value of
10317 * vpid12 is changed w/ one invvpid during nested vmentry.
10318 * The vpid12 is allocated by L1 for L2, so it will not
10319 * influence global bitmap(for vpid01 and vpid02 allocation)
10320 * even if spawn a lot of nested vCPUs.
10322 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10323 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10324 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10325 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10326 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10329 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10330 vmx_flush_tlb(vcpu);
10335 if (nested_cpu_has_ept(vmcs12)) {
10336 kvm_mmu_unload(vcpu);
10337 nested_ept_init_mmu_context(vcpu);
10341 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10342 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10343 * The CR0_READ_SHADOW is what L2 should have expected to read given
10344 * the specifications by L1; It's not enough to take
10345 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10346 * have more bits than L1 expected.
10348 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10349 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10351 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10352 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10354 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
10355 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10356 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10357 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10359 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10360 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10361 vmx_set_efer(vcpu, vcpu->arch.efer);
10363 /* Shadow page tables on either EPT or shadow page tables. */
10364 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_ept_enabled,
10365 entry_failure_code))
10368 kvm_mmu_reset_context(vcpu);
10371 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10374 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10377 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10378 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10379 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10380 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10383 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10384 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10389 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10390 * for running an L2 nested guest.
10392 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10394 struct vmcs12 *vmcs12;
10395 struct vcpu_vmx *vmx = to_vmx(vcpu);
10397 struct loaded_vmcs *vmcs02;
10400 unsigned long exit_qualification;
10402 if (!nested_vmx_check_permission(vcpu))
10405 if (!nested_vmx_check_vmcs12(vcpu))
10408 vmcs12 = get_vmcs12(vcpu);
10410 if (enable_shadow_vmcs)
10411 copy_shadow_to_vmcs12(vmx);
10414 * The nested entry process starts with enforcing various prerequisites
10415 * on vmcs12 as required by the Intel SDM, and act appropriately when
10416 * they fail: As the SDM explains, some conditions should cause the
10417 * instruction to fail, while others will cause the instruction to seem
10418 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10419 * To speed up the normal (success) code path, we should avoid checking
10420 * for misconfigurations which will anyway be caught by the processor
10421 * when using the merged vmcs02.
10423 if (vmcs12->launch_state == launch) {
10424 nested_vmx_failValid(vcpu,
10425 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10426 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10430 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10431 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
10432 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10436 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
10437 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10441 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
10442 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10446 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
10447 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10451 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
10452 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10456 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10457 vmx->nested.nested_vmx_procbased_ctls_low,
10458 vmx->nested.nested_vmx_procbased_ctls_high) ||
10459 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10460 vmx->nested.nested_vmx_secondary_ctls_low,
10461 vmx->nested.nested_vmx_secondary_ctls_high) ||
10462 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10463 vmx->nested.nested_vmx_pinbased_ctls_low,
10464 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10465 !vmx_control_verify(vmcs12->vm_exit_controls,
10466 vmx->nested.nested_vmx_exit_ctls_low,
10467 vmx->nested.nested_vmx_exit_ctls_high) ||
10468 !vmx_control_verify(vmcs12->vm_entry_controls,
10469 vmx->nested.nested_vmx_entry_ctls_low,
10470 vmx->nested.nested_vmx_entry_ctls_high))
10472 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10476 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10477 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10478 !nested_cr3_valid(vcpu, vmcs12->host_cr3)) {
10479 nested_vmx_failValid(vcpu,
10480 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
10484 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10485 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)) {
10486 nested_vmx_entry_failure(vcpu, vmcs12,
10487 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10490 if (vmcs12->vmcs_link_pointer != -1ull) {
10491 nested_vmx_entry_failure(vcpu, vmcs12,
10492 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
10497 * If the load IA32_EFER VM-entry control is 1, the following checks
10498 * are performed on the field for the IA32_EFER MSR:
10499 * - Bits reserved in the IA32_EFER MSR must be 0.
10500 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10501 * the IA-32e mode guest VM-exit control. It must also be identical
10502 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10505 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10506 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10507 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10508 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10509 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10510 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10511 nested_vmx_entry_failure(vcpu, vmcs12,
10512 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10518 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10519 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10520 * the values of the LMA and LME bits in the field must each be that of
10521 * the host address-space size VM-exit control.
10523 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10524 ia32e = (vmcs12->vm_exit_controls &
10525 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10526 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10527 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10528 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10529 nested_vmx_entry_failure(vcpu, vmcs12,
10530 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10536 * We're finally done with prerequisite checking, and can start with
10537 * the nested entry.
10540 vmcs02 = nested_get_current_vmcs02(vmx);
10545 * After this point, the trap flag no longer triggers a singlestep trap
10546 * on the vm entry instructions. Don't call
10547 * kvm_skip_emulated_instruction.
10549 skip_emulated_instruction(vcpu);
10550 enter_guest_mode(vcpu);
10552 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10553 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10556 vmx->loaded_vmcs = vmcs02;
10557 vmx_vcpu_put(vcpu);
10558 vmx_vcpu_load(vcpu, cpu);
10562 vmx_segment_cache_clear(vmx);
10564 if (prepare_vmcs02(vcpu, vmcs12, &exit_qualification)) {
10565 leave_guest_mode(vcpu);
10566 vmx_load_vmcs01(vcpu);
10567 nested_vmx_entry_failure(vcpu, vmcs12,
10568 EXIT_REASON_INVALID_STATE, exit_qualification);
10572 msr_entry_idx = nested_vmx_load_msr(vcpu,
10573 vmcs12->vm_entry_msr_load_addr,
10574 vmcs12->vm_entry_msr_load_count);
10575 if (msr_entry_idx) {
10576 leave_guest_mode(vcpu);
10577 vmx_load_vmcs01(vcpu);
10578 nested_vmx_entry_failure(vcpu, vmcs12,
10579 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10583 vmcs12->launch_state = 1;
10585 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10586 return kvm_vcpu_halt(vcpu);
10588 vmx->nested.nested_run_pending = 1;
10591 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10592 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10593 * returned as far as L1 is concerned. It will only return (and set
10594 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10599 return kvm_skip_emulated_instruction(vcpu);
10603 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10604 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10605 * This function returns the new value we should put in vmcs12.guest_cr0.
10606 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10607 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10608 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10609 * didn't trap the bit, because if L1 did, so would L0).
10610 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10611 * been modified by L2, and L1 knows it. So just leave the old value of
10612 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10613 * isn't relevant, because if L0 traps this bit it can set it to anything.
10614 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10615 * changed these bits, and therefore they need to be updated, but L0
10616 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10617 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10619 static inline unsigned long
10620 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10623 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10624 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10625 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10626 vcpu->arch.cr0_guest_owned_bits));
10629 static inline unsigned long
10630 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10633 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10634 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10635 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10636 vcpu->arch.cr4_guest_owned_bits));
10639 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10640 struct vmcs12 *vmcs12)
10645 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10646 nr = vcpu->arch.exception.nr;
10647 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10649 if (kvm_exception_is_soft(nr)) {
10650 vmcs12->vm_exit_instruction_len =
10651 vcpu->arch.event_exit_inst_len;
10652 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10654 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10656 if (vcpu->arch.exception.has_error_code) {
10657 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10658 vmcs12->idt_vectoring_error_code =
10659 vcpu->arch.exception.error_code;
10662 vmcs12->idt_vectoring_info_field = idt_vectoring;
10663 } else if (vcpu->arch.nmi_injected) {
10664 vmcs12->idt_vectoring_info_field =
10665 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10666 } else if (vcpu->arch.interrupt.pending) {
10667 nr = vcpu->arch.interrupt.nr;
10668 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10670 if (vcpu->arch.interrupt.soft) {
10671 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10672 vmcs12->vm_entry_instruction_len =
10673 vcpu->arch.event_exit_inst_len;
10675 idt_vectoring |= INTR_TYPE_EXT_INTR;
10677 vmcs12->idt_vectoring_info_field = idt_vectoring;
10681 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10683 struct vcpu_vmx *vmx = to_vmx(vcpu);
10685 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10686 vmx->nested.preemption_timer_expired) {
10687 if (vmx->nested.nested_run_pending)
10689 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10693 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10694 if (vmx->nested.nested_run_pending ||
10695 vcpu->arch.interrupt.pending)
10697 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10698 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10699 INTR_INFO_VALID_MASK, 0);
10701 * The NMI-triggered VM exit counts as injection:
10702 * clear this one and block further NMIs.
10704 vcpu->arch.nmi_pending = 0;
10705 vmx_set_nmi_mask(vcpu, true);
10709 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10710 nested_exit_on_intr(vcpu)) {
10711 if (vmx->nested.nested_run_pending)
10713 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10717 vmx_complete_nested_posted_interrupt(vcpu);
10721 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10723 ktime_t remaining =
10724 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10727 if (ktime_to_ns(remaining) <= 0)
10730 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10731 do_div(value, 1000000);
10732 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10736 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10737 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10738 * and this function updates it to reflect the changes to the guest state while
10739 * L2 was running (and perhaps made some exits which were handled directly by L0
10740 * without going back to L1), and to reflect the exit reason.
10741 * Note that we do not have to copy here all VMCS fields, just those that
10742 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10743 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10744 * which already writes to vmcs12 directly.
10746 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10747 u32 exit_reason, u32 exit_intr_info,
10748 unsigned long exit_qualification)
10750 /* update guest state fields: */
10751 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10752 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10754 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10755 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10756 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10758 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10759 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10760 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10761 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10762 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10763 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10764 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10765 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10766 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10767 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10768 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10769 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10770 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10771 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10772 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10773 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10774 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10775 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10776 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10777 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10778 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10779 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10780 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10781 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10782 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10783 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10784 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10785 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10786 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10787 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10788 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10789 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10790 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10791 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10792 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10793 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10795 vmcs12->guest_interruptibility_info =
10796 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10797 vmcs12->guest_pending_dbg_exceptions =
10798 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10799 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10800 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10802 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10804 if (nested_cpu_has_preemption_timer(vmcs12)) {
10805 if (vmcs12->vm_exit_controls &
10806 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10807 vmcs12->vmx_preemption_timer_value =
10808 vmx_get_preemption_timer_value(vcpu);
10809 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10813 * In some cases (usually, nested EPT), L2 is allowed to change its
10814 * own CR3 without exiting. If it has changed it, we must keep it.
10815 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10816 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10818 * Additionally, restore L2's PDPTR to vmcs12.
10821 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10822 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10823 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10824 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10825 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10828 if (nested_cpu_has_ept(vmcs12))
10829 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10831 if (nested_cpu_has_vid(vmcs12))
10832 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10834 vmcs12->vm_entry_controls =
10835 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10836 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10838 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10839 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10840 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10843 /* TODO: These cannot have changed unless we have MSR bitmaps and
10844 * the relevant bit asks not to trap the change */
10845 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10846 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10847 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10848 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10849 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10850 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10851 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10852 if (kvm_mpx_supported())
10853 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10854 if (nested_cpu_has_xsaves(vmcs12))
10855 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10857 /* update exit information fields: */
10859 vmcs12->vm_exit_reason = exit_reason;
10860 vmcs12->exit_qualification = exit_qualification;
10862 vmcs12->vm_exit_intr_info = exit_intr_info;
10863 if ((vmcs12->vm_exit_intr_info &
10864 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10865 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10866 vmcs12->vm_exit_intr_error_code =
10867 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10868 vmcs12->idt_vectoring_info_field = 0;
10869 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10870 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10872 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10873 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10874 * instead of reading the real value. */
10875 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10878 * Transfer the event that L0 or L1 may wanted to inject into
10879 * L2 to IDT_VECTORING_INFO_FIELD.
10881 vmcs12_save_pending_event(vcpu, vmcs12);
10885 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10886 * preserved above and would only end up incorrectly in L1.
10888 vcpu->arch.nmi_injected = false;
10889 kvm_clear_exception_queue(vcpu);
10890 kvm_clear_interrupt_queue(vcpu);
10894 * A part of what we need to when the nested L2 guest exits and we want to
10895 * run its L1 parent, is to reset L1's guest state to the host state specified
10897 * This function is to be called not only on normal nested exit, but also on
10898 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10899 * Failures During or After Loading Guest State").
10900 * This function should be called when the active VMCS is L1's (vmcs01).
10902 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10903 struct vmcs12 *vmcs12)
10905 struct kvm_segment seg;
10906 unsigned long entry_failure_code;
10908 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10909 vcpu->arch.efer = vmcs12->host_ia32_efer;
10910 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10911 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10913 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10914 vmx_set_efer(vcpu, vcpu->arch.efer);
10916 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10917 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10918 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10920 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10921 * actually changed, because it depends on the current state of
10922 * fpu_active (which may have changed).
10923 * Note that vmx_set_cr0 refers to efer set above.
10925 vmx_set_cr0(vcpu, vmcs12->host_cr0);
10927 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10928 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10929 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10931 update_exception_bitmap(vcpu);
10932 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10933 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10936 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10937 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10939 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10940 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10942 nested_ept_uninit_mmu_context(vcpu);
10945 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10946 * couldn't have changed.
10948 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10949 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10952 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10956 * Trivially support vpid by letting L2s share their parent
10957 * L1's vpid. TODO: move to a more elaborate solution, giving
10958 * each L2 its own vpid and exposing the vpid feature to L1.
10960 vmx_flush_tlb(vcpu);
10964 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10965 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10966 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10967 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10968 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10970 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10971 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10972 vmcs_write64(GUEST_BNDCFGS, 0);
10974 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10975 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10976 vcpu->arch.pat = vmcs12->host_ia32_pat;
10978 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10979 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10980 vmcs12->host_ia32_perf_global_ctrl);
10982 /* Set L1 segment info according to Intel SDM
10983 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10984 seg = (struct kvm_segment) {
10986 .limit = 0xFFFFFFFF,
10987 .selector = vmcs12->host_cs_selector,
10993 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10997 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10998 seg = (struct kvm_segment) {
11000 .limit = 0xFFFFFFFF,
11007 seg.selector = vmcs12->host_ds_selector;
11008 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11009 seg.selector = vmcs12->host_es_selector;
11010 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11011 seg.selector = vmcs12->host_ss_selector;
11012 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11013 seg.selector = vmcs12->host_fs_selector;
11014 seg.base = vmcs12->host_fs_base;
11015 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11016 seg.selector = vmcs12->host_gs_selector;
11017 seg.base = vmcs12->host_gs_base;
11018 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11019 seg = (struct kvm_segment) {
11020 .base = vmcs12->host_tr_base,
11022 .selector = vmcs12->host_tr_selector,
11026 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11028 kvm_set_dr(vcpu, 7, 0x400);
11029 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11031 if (cpu_has_vmx_msr_bitmap())
11032 vmx_set_msr_bitmap(vcpu);
11034 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11035 vmcs12->vm_exit_msr_load_count))
11036 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11040 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11041 * and modify vmcs12 to make it see what it would expect to see there if
11042 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11044 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11045 u32 exit_intr_info,
11046 unsigned long exit_qualification)
11048 struct vcpu_vmx *vmx = to_vmx(vcpu);
11049 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11050 u32 vm_inst_error = 0;
11052 /* trying to cancel vmlaunch/vmresume is a bug */
11053 WARN_ON_ONCE(vmx->nested.nested_run_pending);
11055 leave_guest_mode(vcpu);
11056 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11057 exit_qualification);
11059 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11060 vmcs12->vm_exit_msr_store_count))
11061 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11063 if (unlikely(vmx->fail))
11064 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11066 vmx_load_vmcs01(vcpu);
11068 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11069 && nested_exit_intr_ack_set(vcpu)) {
11070 int irq = kvm_cpu_get_interrupt(vcpu);
11072 vmcs12->vm_exit_intr_info = irq |
11073 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11076 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11077 vmcs12->exit_qualification,
11078 vmcs12->idt_vectoring_info_field,
11079 vmcs12->vm_exit_intr_info,
11080 vmcs12->vm_exit_intr_error_code,
11083 vm_entry_controls_reset_shadow(vmx);
11084 vm_exit_controls_reset_shadow(vmx);
11085 vmx_segment_cache_clear(vmx);
11087 /* if no vmcs02 cache requested, remove the one we used */
11088 if (VMCS02_POOL_SIZE == 0)
11089 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11091 load_vmcs12_host_state(vcpu, vmcs12);
11093 /* Update any VMCS fields that might have changed while L2 ran */
11094 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11095 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11096 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11097 if (vmx->hv_deadline_tsc == -1)
11098 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11099 PIN_BASED_VMX_PREEMPTION_TIMER);
11101 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11102 PIN_BASED_VMX_PREEMPTION_TIMER);
11103 if (kvm_has_tsc_control)
11104 decache_tsc_multiplier(vmx);
11106 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11107 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11108 vmx_set_virtual_x2apic_mode(vcpu,
11109 vcpu->arch.apic_base & X2APIC_ENABLE);
11112 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11115 /* Unpin physical memory we referred to in vmcs02 */
11116 if (vmx->nested.apic_access_page) {
11117 nested_release_page(vmx->nested.apic_access_page);
11118 vmx->nested.apic_access_page = NULL;
11120 if (vmx->nested.virtual_apic_page) {
11121 nested_release_page(vmx->nested.virtual_apic_page);
11122 vmx->nested.virtual_apic_page = NULL;
11124 if (vmx->nested.pi_desc_page) {
11125 kunmap(vmx->nested.pi_desc_page);
11126 nested_release_page(vmx->nested.pi_desc_page);
11127 vmx->nested.pi_desc_page = NULL;
11128 vmx->nested.pi_desc = NULL;
11132 * We are now running in L2, mmu_notifier will force to reload the
11133 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11135 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11138 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11139 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11140 * success or failure flag accordingly.
11142 if (unlikely(vmx->fail)) {
11144 nested_vmx_failValid(vcpu, vm_inst_error);
11146 nested_vmx_succeed(vcpu);
11147 if (enable_shadow_vmcs)
11148 vmx->nested.sync_shadow_vmcs = true;
11150 /* in case we halted in L2 */
11151 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11155 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11157 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11159 if (is_guest_mode(vcpu))
11160 nested_vmx_vmexit(vcpu, -1, 0, 0);
11161 free_nested(to_vmx(vcpu));
11165 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11166 * 23.7 "VM-entry failures during or after loading guest state" (this also
11167 * lists the acceptable exit-reason and exit-qualification parameters).
11168 * It should only be called before L2 actually succeeded to run, and when
11169 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11171 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11172 struct vmcs12 *vmcs12,
11173 u32 reason, unsigned long qualification)
11175 load_vmcs12_host_state(vcpu, vmcs12);
11176 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11177 vmcs12->exit_qualification = qualification;
11178 nested_vmx_succeed(vcpu);
11179 if (enable_shadow_vmcs)
11180 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11183 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11184 struct x86_instruction_info *info,
11185 enum x86_intercept_stage stage)
11187 return X86EMUL_CONTINUE;
11190 #ifdef CONFIG_X86_64
11191 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11192 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11193 u64 divisor, u64 *result)
11195 u64 low = a << shift, high = a >> (64 - shift);
11197 /* To avoid the overflow on divq */
11198 if (high >= divisor)
11201 /* Low hold the result, high hold rem which is discarded */
11202 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11203 "rm" (divisor), "0" (low), "1" (high));
11209 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11211 struct vcpu_vmx *vmx = to_vmx(vcpu);
11212 u64 tscl = rdtsc();
11213 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11214 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11216 /* Convert to host delta tsc if tsc scaling is enabled */
11217 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11218 u64_shl_div_u64(delta_tsc,
11219 kvm_tsc_scaling_ratio_frac_bits,
11220 vcpu->arch.tsc_scaling_ratio,
11225 * If the delta tsc can't fit in the 32 bit after the multi shift,
11226 * we can't use the preemption timer.
11227 * It's possible that it fits on later vmentries, but checking
11228 * on every vmentry is costly so we just use an hrtimer.
11230 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11233 vmx->hv_deadline_tsc = tscl + delta_tsc;
11234 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11235 PIN_BASED_VMX_PREEMPTION_TIMER);
11239 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11241 struct vcpu_vmx *vmx = to_vmx(vcpu);
11242 vmx->hv_deadline_tsc = -1;
11243 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11244 PIN_BASED_VMX_PREEMPTION_TIMER);
11248 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11251 shrink_ple_window(vcpu);
11254 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11255 struct kvm_memory_slot *slot)
11257 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11258 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11261 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11262 struct kvm_memory_slot *slot)
11264 kvm_mmu_slot_set_dirty(kvm, slot);
11267 static void vmx_flush_log_dirty(struct kvm *kvm)
11269 kvm_flush_pml_buffers(kvm);
11272 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11273 struct kvm_memory_slot *memslot,
11274 gfn_t offset, unsigned long mask)
11276 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11280 * This routine does the following things for vCPU which is going
11281 * to be blocked if VT-d PI is enabled.
11282 * - Store the vCPU to the wakeup list, so when interrupts happen
11283 * we can find the right vCPU to wake up.
11284 * - Change the Posted-interrupt descriptor as below:
11285 * 'NDST' <-- vcpu->pre_pcpu
11286 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11287 * - If 'ON' is set during this process, which means at least one
11288 * interrupt is posted for this vCPU, we cannot block it, in
11289 * this case, return 1, otherwise, return 0.
11292 static int pi_pre_block(struct kvm_vcpu *vcpu)
11294 unsigned long flags;
11296 struct pi_desc old, new;
11297 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11299 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11300 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11301 !kvm_vcpu_apicv_active(vcpu))
11304 vcpu->pre_pcpu = vcpu->cpu;
11305 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11306 vcpu->pre_pcpu), flags);
11307 list_add_tail(&vcpu->blocked_vcpu_list,
11308 &per_cpu(blocked_vcpu_on_cpu,
11310 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11311 vcpu->pre_pcpu), flags);
11314 old.control = new.control = pi_desc->control;
11317 * We should not block the vCPU if
11318 * an interrupt is posted for it.
11320 if (pi_test_on(pi_desc) == 1) {
11321 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11322 vcpu->pre_pcpu), flags);
11323 list_del(&vcpu->blocked_vcpu_list);
11324 spin_unlock_irqrestore(
11325 &per_cpu(blocked_vcpu_on_cpu_lock,
11326 vcpu->pre_pcpu), flags);
11327 vcpu->pre_pcpu = -1;
11332 WARN((pi_desc->sn == 1),
11333 "Warning: SN field of posted-interrupts "
11334 "is set before blocking\n");
11337 * Since vCPU can be preempted during this process,
11338 * vcpu->cpu could be different with pre_pcpu, we
11339 * need to set pre_pcpu as the destination of wakeup
11340 * notification event, then we can find the right vCPU
11341 * to wakeup in wakeup handler if interrupts happen
11342 * when the vCPU is in blocked state.
11344 dest = cpu_physical_id(vcpu->pre_pcpu);
11346 if (x2apic_enabled())
11349 new.ndst = (dest << 8) & 0xFF00;
11351 /* set 'NV' to 'wakeup vector' */
11352 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11353 } while (cmpxchg(&pi_desc->control, old.control,
11354 new.control) != old.control);
11359 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11361 if (pi_pre_block(vcpu))
11364 if (kvm_lapic_hv_timer_in_use(vcpu))
11365 kvm_lapic_switch_to_sw_timer(vcpu);
11370 static void pi_post_block(struct kvm_vcpu *vcpu)
11372 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11373 struct pi_desc old, new;
11375 unsigned long flags;
11377 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11378 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11379 !kvm_vcpu_apicv_active(vcpu))
11383 old.control = new.control = pi_desc->control;
11385 dest = cpu_physical_id(vcpu->cpu);
11387 if (x2apic_enabled())
11390 new.ndst = (dest << 8) & 0xFF00;
11392 /* Allow posting non-urgent interrupts */
11395 /* set 'NV' to 'notification vector' */
11396 new.nv = POSTED_INTR_VECTOR;
11397 } while (cmpxchg(&pi_desc->control, old.control,
11398 new.control) != old.control);
11400 if(vcpu->pre_pcpu != -1) {
11402 &per_cpu(blocked_vcpu_on_cpu_lock,
11403 vcpu->pre_pcpu), flags);
11404 list_del(&vcpu->blocked_vcpu_list);
11405 spin_unlock_irqrestore(
11406 &per_cpu(blocked_vcpu_on_cpu_lock,
11407 vcpu->pre_pcpu), flags);
11408 vcpu->pre_pcpu = -1;
11412 static void vmx_post_block(struct kvm_vcpu *vcpu)
11414 if (kvm_x86_ops->set_hv_timer)
11415 kvm_lapic_switch_to_hv_timer(vcpu);
11417 pi_post_block(vcpu);
11421 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11424 * @host_irq: host irq of the interrupt
11425 * @guest_irq: gsi of the interrupt
11426 * @set: set or unset PI
11427 * returns 0 on success, < 0 on failure
11429 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11430 uint32_t guest_irq, bool set)
11432 struct kvm_kernel_irq_routing_entry *e;
11433 struct kvm_irq_routing_table *irq_rt;
11434 struct kvm_lapic_irq irq;
11435 struct kvm_vcpu *vcpu;
11436 struct vcpu_data vcpu_info;
11437 int idx, ret = -EINVAL;
11439 if (!kvm_arch_has_assigned_device(kvm) ||
11440 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11441 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11444 idx = srcu_read_lock(&kvm->irq_srcu);
11445 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11446 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11448 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11449 if (e->type != KVM_IRQ_ROUTING_MSI)
11452 * VT-d PI cannot support posting multicast/broadcast
11453 * interrupts to a vCPU, we still use interrupt remapping
11454 * for these kind of interrupts.
11456 * For lowest-priority interrupts, we only support
11457 * those with single CPU as the destination, e.g. user
11458 * configures the interrupts via /proc/irq or uses
11459 * irqbalance to make the interrupts single-CPU.
11461 * We will support full lowest-priority interrupt later.
11464 kvm_set_msi_irq(kvm, e, &irq);
11465 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11467 * Make sure the IRTE is in remapped mode if
11468 * we don't handle it in posted mode.
11470 ret = irq_set_vcpu_affinity(host_irq, NULL);
11473 "failed to back to remapped mode, irq: %u\n",
11481 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11482 vcpu_info.vector = irq.vector;
11484 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11485 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11488 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11490 /* suppress notification event before unposting */
11491 pi_set_sn(vcpu_to_pi_desc(vcpu));
11492 ret = irq_set_vcpu_affinity(host_irq, NULL);
11493 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11497 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11505 srcu_read_unlock(&kvm->irq_srcu, idx);
11509 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11511 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11512 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11513 FEATURE_CONTROL_LMCE;
11515 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11516 ~FEATURE_CONTROL_LMCE;
11519 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11520 .cpu_has_kvm_support = cpu_has_kvm_support,
11521 .disabled_by_bios = vmx_disabled_by_bios,
11522 .hardware_setup = hardware_setup,
11523 .hardware_unsetup = hardware_unsetup,
11524 .check_processor_compatibility = vmx_check_processor_compat,
11525 .hardware_enable = hardware_enable,
11526 .hardware_disable = hardware_disable,
11527 .cpu_has_accelerated_tpr = report_flexpriority,
11528 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11530 .vcpu_create = vmx_create_vcpu,
11531 .vcpu_free = vmx_free_vcpu,
11532 .vcpu_reset = vmx_vcpu_reset,
11534 .prepare_guest_switch = vmx_save_host_state,
11535 .vcpu_load = vmx_vcpu_load,
11536 .vcpu_put = vmx_vcpu_put,
11538 .update_bp_intercept = update_exception_bitmap,
11539 .get_msr = vmx_get_msr,
11540 .set_msr = vmx_set_msr,
11541 .get_segment_base = vmx_get_segment_base,
11542 .get_segment = vmx_get_segment,
11543 .set_segment = vmx_set_segment,
11544 .get_cpl = vmx_get_cpl,
11545 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11546 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11547 .decache_cr3 = vmx_decache_cr3,
11548 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11549 .set_cr0 = vmx_set_cr0,
11550 .set_cr3 = vmx_set_cr3,
11551 .set_cr4 = vmx_set_cr4,
11552 .set_efer = vmx_set_efer,
11553 .get_idt = vmx_get_idt,
11554 .set_idt = vmx_set_idt,
11555 .get_gdt = vmx_get_gdt,
11556 .set_gdt = vmx_set_gdt,
11557 .get_dr6 = vmx_get_dr6,
11558 .set_dr6 = vmx_set_dr6,
11559 .set_dr7 = vmx_set_dr7,
11560 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11561 .cache_reg = vmx_cache_reg,
11562 .get_rflags = vmx_get_rflags,
11563 .set_rflags = vmx_set_rflags,
11565 .get_pkru = vmx_get_pkru,
11567 .fpu_activate = vmx_fpu_activate,
11568 .fpu_deactivate = vmx_fpu_deactivate,
11570 .tlb_flush = vmx_flush_tlb,
11572 .run = vmx_vcpu_run,
11573 .handle_exit = vmx_handle_exit,
11574 .skip_emulated_instruction = skip_emulated_instruction,
11575 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11576 .get_interrupt_shadow = vmx_get_interrupt_shadow,
11577 .patch_hypercall = vmx_patch_hypercall,
11578 .set_irq = vmx_inject_irq,
11579 .set_nmi = vmx_inject_nmi,
11580 .queue_exception = vmx_queue_exception,
11581 .cancel_injection = vmx_cancel_injection,
11582 .interrupt_allowed = vmx_interrupt_allowed,
11583 .nmi_allowed = vmx_nmi_allowed,
11584 .get_nmi_mask = vmx_get_nmi_mask,
11585 .set_nmi_mask = vmx_set_nmi_mask,
11586 .enable_nmi_window = enable_nmi_window,
11587 .enable_irq_window = enable_irq_window,
11588 .update_cr8_intercept = update_cr8_intercept,
11589 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11590 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11591 .get_enable_apicv = vmx_get_enable_apicv,
11592 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11593 .load_eoi_exitmap = vmx_load_eoi_exitmap,
11594 .apicv_post_state_restore = vmx_apicv_post_state_restore,
11595 .hwapic_irr_update = vmx_hwapic_irr_update,
11596 .hwapic_isr_update = vmx_hwapic_isr_update,
11597 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11598 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11600 .set_tss_addr = vmx_set_tss_addr,
11601 .get_tdp_level = get_ept_level,
11602 .get_mt_mask = vmx_get_mt_mask,
11604 .get_exit_info = vmx_get_exit_info,
11606 .get_lpage_level = vmx_get_lpage_level,
11608 .cpuid_update = vmx_cpuid_update,
11610 .rdtscp_supported = vmx_rdtscp_supported,
11611 .invpcid_supported = vmx_invpcid_supported,
11613 .set_supported_cpuid = vmx_set_supported_cpuid,
11615 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11617 .write_tsc_offset = vmx_write_tsc_offset,
11619 .set_tdp_cr3 = vmx_set_cr3,
11621 .check_intercept = vmx_check_intercept,
11622 .handle_external_intr = vmx_handle_external_intr,
11623 .mpx_supported = vmx_mpx_supported,
11624 .xsaves_supported = vmx_xsaves_supported,
11626 .check_nested_events = vmx_check_nested_events,
11628 .sched_in = vmx_sched_in,
11630 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11631 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11632 .flush_log_dirty = vmx_flush_log_dirty,
11633 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11635 .pre_block = vmx_pre_block,
11636 .post_block = vmx_post_block,
11638 .pmu_ops = &intel_pmu_ops,
11640 .update_pi_irte = vmx_update_pi_irte,
11642 #ifdef CONFIG_X86_64
11643 .set_hv_timer = vmx_set_hv_timer,
11644 .cancel_hv_timer = vmx_cancel_hv_timer,
11647 .setup_mce = vmx_setup_mce,
11650 static int __init vmx_init(void)
11652 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11653 __alignof__(struct vcpu_vmx), THIS_MODULE);
11657 #ifdef CONFIG_KEXEC_CORE
11658 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11659 crash_vmclear_local_loaded_vmcss);
11665 static void __exit vmx_exit(void)
11667 #ifdef CONFIG_KEXEC_CORE
11668 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11675 module_init(vmx_init)
11676 module_exit(vmx_exit)