2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
34 #include <asm/virtext.h>
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
41 static int bypass_guest_pf = 1;
42 module_param(bypass_guest_pf, bool, 0);
44 static int enable_vpid = 1;
45 module_param(enable_vpid, bool, 0);
47 static int flexpriority_enabled = 1;
48 module_param(flexpriority_enabled, bool, 0);
50 static int enable_ept = 1;
51 module_param(enable_ept, bool, 0);
53 static int emulate_invalid_guest_state = 0;
54 module_param(emulate_invalid_guest_state, bool, 0);
64 struct list_head local_vcpus_link;
65 unsigned long host_rsp;
68 u32 idt_vectoring_info;
69 struct kvm_msr_entry *guest_msrs;
70 struct kvm_msr_entry *host_msrs;
75 int msr_offset_kernel_gs_base;
80 u16 fs_sel, gs_sel, ldt_sel;
81 int gs_ldt_reload_needed;
83 int guest_efer_loaded;
93 bool emulation_required;
95 /* Support for vnmi-less CPUs */
96 int soft_vnmi_blocked;
98 s64 vnmi_blocked_time;
101 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
103 return container_of(vcpu, struct vcpu_vmx, vcpu);
106 static int init_rmode(struct kvm *kvm);
107 static u64 construct_eptp(unsigned long root_hpa);
109 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
110 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
111 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
113 static struct page *vmx_io_bitmap_a;
114 static struct page *vmx_io_bitmap_b;
115 static struct page *vmx_msr_bitmap;
117 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
118 static DEFINE_SPINLOCK(vmx_vpid_lock);
120 static struct vmcs_config {
124 u32 pin_based_exec_ctrl;
125 u32 cpu_based_exec_ctrl;
126 u32 cpu_based_2nd_exec_ctrl;
131 static struct vmx_capability {
136 #define VMX_SEGMENT_FIELD(seg) \
137 [VCPU_SREG_##seg] = { \
138 .selector = GUEST_##seg##_SELECTOR, \
139 .base = GUEST_##seg##_BASE, \
140 .limit = GUEST_##seg##_LIMIT, \
141 .ar_bytes = GUEST_##seg##_AR_BYTES, \
144 static struct kvm_vmx_segment_field {
149 } kvm_vmx_segment_fields[] = {
150 VMX_SEGMENT_FIELD(CS),
151 VMX_SEGMENT_FIELD(DS),
152 VMX_SEGMENT_FIELD(ES),
153 VMX_SEGMENT_FIELD(FS),
154 VMX_SEGMENT_FIELD(GS),
155 VMX_SEGMENT_FIELD(SS),
156 VMX_SEGMENT_FIELD(TR),
157 VMX_SEGMENT_FIELD(LDTR),
161 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
162 * away by decrementing the array size.
164 static const u32 vmx_msr_index[] = {
166 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
168 MSR_EFER, MSR_K6_STAR,
170 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
172 static void load_msrs(struct kvm_msr_entry *e, int n)
176 for (i = 0; i < n; ++i)
177 wrmsrl(e[i].index, e[i].data);
180 static void save_msrs(struct kvm_msr_entry *e, int n)
184 for (i = 0; i < n; ++i)
185 rdmsrl(e[i].index, e[i].data);
188 static inline int is_page_fault(u32 intr_info)
190 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
191 INTR_INFO_VALID_MASK)) ==
192 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
195 static inline int is_no_device(u32 intr_info)
197 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
198 INTR_INFO_VALID_MASK)) ==
199 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
202 static inline int is_invalid_opcode(u32 intr_info)
204 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
205 INTR_INFO_VALID_MASK)) ==
206 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
209 static inline int is_external_interrupt(u32 intr_info)
211 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
212 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
215 static inline int cpu_has_vmx_msr_bitmap(void)
217 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
220 static inline int cpu_has_vmx_tpr_shadow(void)
222 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
225 static inline int vm_need_tpr_shadow(struct kvm *kvm)
227 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
230 static inline int cpu_has_secondary_exec_ctrls(void)
232 return (vmcs_config.cpu_based_exec_ctrl &
233 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
236 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
238 return flexpriority_enabled
239 && (vmcs_config.cpu_based_2nd_exec_ctrl &
240 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
243 static inline int cpu_has_vmx_invept_individual_addr(void)
245 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
248 static inline int cpu_has_vmx_invept_context(void)
250 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
253 static inline int cpu_has_vmx_invept_global(void)
255 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
258 static inline int cpu_has_vmx_ept(void)
260 return (vmcs_config.cpu_based_2nd_exec_ctrl &
261 SECONDARY_EXEC_ENABLE_EPT);
264 static inline int vm_need_ept(void)
266 return (cpu_has_vmx_ept() && enable_ept);
269 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
271 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
272 (irqchip_in_kernel(kvm)));
275 static inline int cpu_has_vmx_vpid(void)
277 return (vmcs_config.cpu_based_2nd_exec_ctrl &
278 SECONDARY_EXEC_ENABLE_VPID);
281 static inline int cpu_has_virtual_nmis(void)
283 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
286 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
290 for (i = 0; i < vmx->nmsrs; ++i)
291 if (vmx->guest_msrs[i].index == msr)
296 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
302 } operand = { vpid, 0, gva };
304 asm volatile (__ex(ASM_VMX_INVVPID)
305 /* CF==1 or ZF==1 --> rc = -1 */
307 : : "a"(&operand), "c"(ext) : "cc", "memory");
310 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
314 } operand = {eptp, gpa};
316 asm volatile (__ex(ASM_VMX_INVEPT)
317 /* CF==1 or ZF==1 --> rc = -1 */
318 "; ja 1f ; ud2 ; 1:\n"
319 : : "a" (&operand), "c" (ext) : "cc", "memory");
322 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
326 i = __find_msr_index(vmx, msr);
328 return &vmx->guest_msrs[i];
332 static void vmcs_clear(struct vmcs *vmcs)
334 u64 phys_addr = __pa(vmcs);
337 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
338 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
341 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
345 static void __vcpu_clear(void *arg)
347 struct vcpu_vmx *vmx = arg;
348 int cpu = raw_smp_processor_id();
350 if (vmx->vcpu.cpu == cpu)
351 vmcs_clear(vmx->vmcs);
352 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
353 per_cpu(current_vmcs, cpu) = NULL;
354 rdtscll(vmx->vcpu.arch.host_tsc);
355 list_del(&vmx->local_vcpus_link);
360 static void vcpu_clear(struct vcpu_vmx *vmx)
362 if (vmx->vcpu.cpu == -1)
364 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
367 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
372 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
375 static inline void ept_sync_global(void)
377 if (cpu_has_vmx_invept_global())
378 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
381 static inline void ept_sync_context(u64 eptp)
384 if (cpu_has_vmx_invept_context())
385 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
391 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
394 if (cpu_has_vmx_invept_individual_addr())
395 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
398 ept_sync_context(eptp);
402 static unsigned long vmcs_readl(unsigned long field)
406 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
407 : "=a"(value) : "d"(field) : "cc");
411 static u16 vmcs_read16(unsigned long field)
413 return vmcs_readl(field);
416 static u32 vmcs_read32(unsigned long field)
418 return vmcs_readl(field);
421 static u64 vmcs_read64(unsigned long field)
424 return vmcs_readl(field);
426 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
430 static noinline void vmwrite_error(unsigned long field, unsigned long value)
432 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
433 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
437 static void vmcs_writel(unsigned long field, unsigned long value)
441 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
442 : "=q"(error) : "a"(value), "d"(field) : "cc");
444 vmwrite_error(field, value);
447 static void vmcs_write16(unsigned long field, u16 value)
449 vmcs_writel(field, value);
452 static void vmcs_write32(unsigned long field, u32 value)
454 vmcs_writel(field, value);
457 static void vmcs_write64(unsigned long field, u64 value)
459 vmcs_writel(field, value);
460 #ifndef CONFIG_X86_64
462 vmcs_writel(field+1, value >> 32);
466 static void vmcs_clear_bits(unsigned long field, u32 mask)
468 vmcs_writel(field, vmcs_readl(field) & ~mask);
471 static void vmcs_set_bits(unsigned long field, u32 mask)
473 vmcs_writel(field, vmcs_readl(field) | mask);
476 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
480 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
481 if (!vcpu->fpu_active)
482 eb |= 1u << NM_VECTOR;
483 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
484 if (vcpu->guest_debug &
485 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
486 eb |= 1u << DB_VECTOR;
487 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
488 eb |= 1u << BP_VECTOR;
490 if (vcpu->arch.rmode.active)
493 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
494 vmcs_write32(EXCEPTION_BITMAP, eb);
497 static void reload_tss(void)
500 * VT restores TR but not its size. Useless.
502 struct descriptor_table gdt;
503 struct desc_struct *descs;
506 descs = (void *)gdt.base;
507 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
511 static void load_transition_efer(struct vcpu_vmx *vmx)
513 int efer_offset = vmx->msr_offset_efer;
514 u64 host_efer = vmx->host_msrs[efer_offset].data;
515 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
521 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
524 ignore_bits = EFER_NX | EFER_SCE;
526 ignore_bits |= EFER_LMA | EFER_LME;
527 /* SCE is meaningful only in long mode on Intel */
528 if (guest_efer & EFER_LMA)
529 ignore_bits &= ~(u64)EFER_SCE;
531 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
534 vmx->host_state.guest_efer_loaded = 1;
535 guest_efer &= ~ignore_bits;
536 guest_efer |= host_efer & ignore_bits;
537 wrmsrl(MSR_EFER, guest_efer);
538 vmx->vcpu.stat.efer_reload++;
541 static void reload_host_efer(struct vcpu_vmx *vmx)
543 if (vmx->host_state.guest_efer_loaded) {
544 vmx->host_state.guest_efer_loaded = 0;
545 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
549 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
551 struct vcpu_vmx *vmx = to_vmx(vcpu);
553 if (vmx->host_state.loaded)
556 vmx->host_state.loaded = 1;
558 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
559 * allow segment selectors with cpl > 0 or ti == 1.
561 vmx->host_state.ldt_sel = kvm_read_ldt();
562 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
563 vmx->host_state.fs_sel = kvm_read_fs();
564 if (!(vmx->host_state.fs_sel & 7)) {
565 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
566 vmx->host_state.fs_reload_needed = 0;
568 vmcs_write16(HOST_FS_SELECTOR, 0);
569 vmx->host_state.fs_reload_needed = 1;
571 vmx->host_state.gs_sel = kvm_read_gs();
572 if (!(vmx->host_state.gs_sel & 7))
573 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
575 vmcs_write16(HOST_GS_SELECTOR, 0);
576 vmx->host_state.gs_ldt_reload_needed = 1;
580 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
581 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
583 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
584 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
588 if (is_long_mode(&vmx->vcpu))
589 save_msrs(vmx->host_msrs +
590 vmx->msr_offset_kernel_gs_base, 1);
593 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
594 load_transition_efer(vmx);
597 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
601 if (!vmx->host_state.loaded)
604 ++vmx->vcpu.stat.host_state_reload;
605 vmx->host_state.loaded = 0;
606 if (vmx->host_state.fs_reload_needed)
607 kvm_load_fs(vmx->host_state.fs_sel);
608 if (vmx->host_state.gs_ldt_reload_needed) {
609 kvm_load_ldt(vmx->host_state.ldt_sel);
611 * If we have to reload gs, we must take care to
612 * preserve our gs base.
614 local_irq_save(flags);
615 kvm_load_gs(vmx->host_state.gs_sel);
617 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
619 local_irq_restore(flags);
622 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
623 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
624 reload_host_efer(vmx);
627 static void vmx_load_host_state(struct vcpu_vmx *vmx)
630 __vmx_load_host_state(vmx);
635 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
636 * vcpu mutex is already taken.
638 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
640 struct vcpu_vmx *vmx = to_vmx(vcpu);
641 u64 phys_addr = __pa(vmx->vmcs);
642 u64 tsc_this, delta, new_offset;
644 if (vcpu->cpu != cpu) {
646 kvm_migrate_timers(vcpu);
647 vpid_sync_vcpu_all(vmx);
649 list_add(&vmx->local_vcpus_link,
650 &per_cpu(vcpus_on_cpu, cpu));
654 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
657 per_cpu(current_vmcs, cpu) = vmx->vmcs;
658 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
659 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
662 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
663 vmx->vmcs, phys_addr);
666 if (vcpu->cpu != cpu) {
667 struct descriptor_table dt;
668 unsigned long sysenter_esp;
672 * Linux uses per-cpu TSS and GDT, so set these when switching
675 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
677 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
679 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
680 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
683 * Make sure the time stamp counter is monotonous.
686 if (tsc_this < vcpu->arch.host_tsc) {
687 delta = vcpu->arch.host_tsc - tsc_this;
688 new_offset = vmcs_read64(TSC_OFFSET) + delta;
689 vmcs_write64(TSC_OFFSET, new_offset);
694 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
696 __vmx_load_host_state(to_vmx(vcpu));
699 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
701 if (vcpu->fpu_active)
703 vcpu->fpu_active = 1;
704 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
705 if (vcpu->arch.cr0 & X86_CR0_TS)
706 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
707 update_exception_bitmap(vcpu);
710 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
712 if (!vcpu->fpu_active)
714 vcpu->fpu_active = 0;
715 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
716 update_exception_bitmap(vcpu);
719 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
721 return vmcs_readl(GUEST_RFLAGS);
724 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
726 if (vcpu->arch.rmode.active)
727 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
728 vmcs_writel(GUEST_RFLAGS, rflags);
731 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
734 u32 interruptibility;
736 rip = kvm_rip_read(vcpu);
737 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
738 kvm_rip_write(vcpu, rip);
741 * We emulated an instruction, so temporary interrupt blocking
742 * should be removed, if set.
744 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
745 if (interruptibility & 3)
746 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
747 interruptibility & ~3);
748 vcpu->arch.interrupt_window_open = 1;
751 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
752 bool has_error_code, u32 error_code)
754 struct vcpu_vmx *vmx = to_vmx(vcpu);
755 u32 intr_info = nr | INTR_INFO_VALID_MASK;
757 if (has_error_code) {
758 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
759 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
762 if (vcpu->arch.rmode.active) {
763 vmx->rmode.irq.pending = true;
764 vmx->rmode.irq.vector = nr;
765 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
766 if (nr == BP_VECTOR || nr == OF_VECTOR)
767 vmx->rmode.irq.rip++;
768 intr_info |= INTR_TYPE_SOFT_INTR;
769 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
770 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
771 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
775 if (nr == BP_VECTOR || nr == OF_VECTOR) {
776 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
777 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
779 intr_info |= INTR_TYPE_HARD_EXCEPTION;
781 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
784 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
790 * Swap MSR entry in host/guest MSR entry array.
793 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
795 struct kvm_msr_entry tmp;
797 tmp = vmx->guest_msrs[to];
798 vmx->guest_msrs[to] = vmx->guest_msrs[from];
799 vmx->guest_msrs[from] = tmp;
800 tmp = vmx->host_msrs[to];
801 vmx->host_msrs[to] = vmx->host_msrs[from];
802 vmx->host_msrs[from] = tmp;
807 * Set up the vmcs to automatically save and restore system
808 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
809 * mode, as fiddling with msrs is very expensive.
811 static void setup_msrs(struct vcpu_vmx *vmx)
815 vmx_load_host_state(vmx);
818 if (is_long_mode(&vmx->vcpu)) {
821 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
823 move_msr_up(vmx, index, save_nmsrs++);
824 index = __find_msr_index(vmx, MSR_LSTAR);
826 move_msr_up(vmx, index, save_nmsrs++);
827 index = __find_msr_index(vmx, MSR_CSTAR);
829 move_msr_up(vmx, index, save_nmsrs++);
830 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
832 move_msr_up(vmx, index, save_nmsrs++);
834 * MSR_K6_STAR is only needed on long mode guests, and only
835 * if efer.sce is enabled.
837 index = __find_msr_index(vmx, MSR_K6_STAR);
838 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
839 move_msr_up(vmx, index, save_nmsrs++);
842 vmx->save_nmsrs = save_nmsrs;
845 vmx->msr_offset_kernel_gs_base =
846 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
848 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
852 * reads and returns guest's timestamp counter "register"
853 * guest_tsc = host_tsc + tsc_offset -- 21.3
855 static u64 guest_read_tsc(void)
857 u64 host_tsc, tsc_offset;
860 tsc_offset = vmcs_read64(TSC_OFFSET);
861 return host_tsc + tsc_offset;
865 * writes 'guest_tsc' into guest's timestamp counter "register"
866 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
868 static void guest_write_tsc(u64 guest_tsc)
873 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
877 * Reads an msr value (of 'msr_index') into 'pdata'.
878 * Returns 0 on success, non-0 otherwise.
879 * Assumes vcpu_load() was already called.
881 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
884 struct kvm_msr_entry *msr;
887 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
894 data = vmcs_readl(GUEST_FS_BASE);
897 data = vmcs_readl(GUEST_GS_BASE);
900 return kvm_get_msr_common(vcpu, msr_index, pdata);
902 case MSR_IA32_TIME_STAMP_COUNTER:
903 data = guest_read_tsc();
905 case MSR_IA32_SYSENTER_CS:
906 data = vmcs_read32(GUEST_SYSENTER_CS);
908 case MSR_IA32_SYSENTER_EIP:
909 data = vmcs_readl(GUEST_SYSENTER_EIP);
911 case MSR_IA32_SYSENTER_ESP:
912 data = vmcs_readl(GUEST_SYSENTER_ESP);
915 vmx_load_host_state(to_vmx(vcpu));
916 msr = find_msr_entry(to_vmx(vcpu), msr_index);
921 return kvm_get_msr_common(vcpu, msr_index, pdata);
929 * Writes msr value into into the appropriate "register".
930 * Returns 0 on success, non-0 otherwise.
931 * Assumes vcpu_load() was already called.
933 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
935 struct vcpu_vmx *vmx = to_vmx(vcpu);
936 struct kvm_msr_entry *msr;
942 vmx_load_host_state(vmx);
943 ret = kvm_set_msr_common(vcpu, msr_index, data);
946 vmcs_writel(GUEST_FS_BASE, data);
949 vmcs_writel(GUEST_GS_BASE, data);
952 case MSR_IA32_SYSENTER_CS:
953 vmcs_write32(GUEST_SYSENTER_CS, data);
955 case MSR_IA32_SYSENTER_EIP:
956 vmcs_writel(GUEST_SYSENTER_EIP, data);
958 case MSR_IA32_SYSENTER_ESP:
959 vmcs_writel(GUEST_SYSENTER_ESP, data);
961 case MSR_IA32_TIME_STAMP_COUNTER:
962 guest_write_tsc(data);
964 case MSR_P6_PERFCTR0:
965 case MSR_P6_PERFCTR1:
966 case MSR_P6_EVNTSEL0:
967 case MSR_P6_EVNTSEL1:
969 * Just discard all writes to the performance counters; this
970 * should keep both older linux and windows 64-bit guests
973 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
976 case MSR_IA32_CR_PAT:
977 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
978 vmcs_write64(GUEST_IA32_PAT, data);
979 vcpu->arch.pat = data;
982 /* Otherwise falls through to kvm_set_msr_common */
984 vmx_load_host_state(vmx);
985 msr = find_msr_entry(vmx, msr_index);
990 ret = kvm_set_msr_common(vcpu, msr_index, data);
996 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
998 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1001 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1004 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1011 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1013 int old_debug = vcpu->guest_debug;
1014 unsigned long flags;
1016 vcpu->guest_debug = dbg->control;
1017 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1018 vcpu->guest_debug = 0;
1020 flags = vmcs_readl(GUEST_RFLAGS);
1021 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1022 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1023 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1024 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1025 vmcs_writel(GUEST_RFLAGS, flags);
1027 update_exception_bitmap(vcpu);
1032 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1034 if (!vcpu->arch.interrupt.pending)
1036 return vcpu->arch.interrupt.nr;
1039 static __init int cpu_has_kvm_support(void)
1041 return cpu_has_vmx();
1044 static __init int vmx_disabled_by_bios(void)
1048 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1049 return (msr & (FEATURE_CONTROL_LOCKED |
1050 FEATURE_CONTROL_VMXON_ENABLED))
1051 == FEATURE_CONTROL_LOCKED;
1052 /* locked but not enabled */
1055 static void hardware_enable(void *garbage)
1057 int cpu = raw_smp_processor_id();
1058 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1061 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1062 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1063 if ((old & (FEATURE_CONTROL_LOCKED |
1064 FEATURE_CONTROL_VMXON_ENABLED))
1065 != (FEATURE_CONTROL_LOCKED |
1066 FEATURE_CONTROL_VMXON_ENABLED))
1067 /* enable and lock */
1068 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1069 FEATURE_CONTROL_LOCKED |
1070 FEATURE_CONTROL_VMXON_ENABLED);
1071 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1072 asm volatile (ASM_VMX_VMXON_RAX
1073 : : "a"(&phys_addr), "m"(phys_addr)
1077 static void vmclear_local_vcpus(void)
1079 int cpu = raw_smp_processor_id();
1080 struct vcpu_vmx *vmx, *n;
1082 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1088 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1091 static void kvm_cpu_vmxoff(void)
1093 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1094 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1097 static void hardware_disable(void *garbage)
1099 vmclear_local_vcpus();
1103 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1104 u32 msr, u32 *result)
1106 u32 vmx_msr_low, vmx_msr_high;
1107 u32 ctl = ctl_min | ctl_opt;
1109 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1111 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1112 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1114 /* Ensure minimum (required) set of control bits are supported. */
1122 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1124 u32 vmx_msr_low, vmx_msr_high;
1125 u32 min, opt, min2, opt2;
1126 u32 _pin_based_exec_control = 0;
1127 u32 _cpu_based_exec_control = 0;
1128 u32 _cpu_based_2nd_exec_control = 0;
1129 u32 _vmexit_control = 0;
1130 u32 _vmentry_control = 0;
1132 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1133 opt = PIN_BASED_VIRTUAL_NMIS;
1134 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1135 &_pin_based_exec_control) < 0)
1138 min = CPU_BASED_HLT_EXITING |
1139 #ifdef CONFIG_X86_64
1140 CPU_BASED_CR8_LOAD_EXITING |
1141 CPU_BASED_CR8_STORE_EXITING |
1143 CPU_BASED_CR3_LOAD_EXITING |
1144 CPU_BASED_CR3_STORE_EXITING |
1145 CPU_BASED_USE_IO_BITMAPS |
1146 CPU_BASED_MOV_DR_EXITING |
1147 CPU_BASED_USE_TSC_OFFSETING |
1148 CPU_BASED_INVLPG_EXITING;
1149 opt = CPU_BASED_TPR_SHADOW |
1150 CPU_BASED_USE_MSR_BITMAPS |
1151 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1152 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1153 &_cpu_based_exec_control) < 0)
1155 #ifdef CONFIG_X86_64
1156 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1157 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1158 ~CPU_BASED_CR8_STORE_EXITING;
1160 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1162 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1163 SECONDARY_EXEC_WBINVD_EXITING |
1164 SECONDARY_EXEC_ENABLE_VPID |
1165 SECONDARY_EXEC_ENABLE_EPT;
1166 if (adjust_vmx_controls(min2, opt2,
1167 MSR_IA32_VMX_PROCBASED_CTLS2,
1168 &_cpu_based_2nd_exec_control) < 0)
1171 #ifndef CONFIG_X86_64
1172 if (!(_cpu_based_2nd_exec_control &
1173 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1174 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1176 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1177 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1179 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1180 CPU_BASED_CR3_STORE_EXITING |
1181 CPU_BASED_INVLPG_EXITING);
1182 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1183 &_cpu_based_exec_control) < 0)
1185 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1186 vmx_capability.ept, vmx_capability.vpid);
1190 #ifdef CONFIG_X86_64
1191 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1193 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1194 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1195 &_vmexit_control) < 0)
1199 opt = VM_ENTRY_LOAD_IA32_PAT;
1200 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1201 &_vmentry_control) < 0)
1204 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1206 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1207 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1210 #ifdef CONFIG_X86_64
1211 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1212 if (vmx_msr_high & (1u<<16))
1216 /* Require Write-Back (WB) memory type for VMCS accesses. */
1217 if (((vmx_msr_high >> 18) & 15) != 6)
1220 vmcs_conf->size = vmx_msr_high & 0x1fff;
1221 vmcs_conf->order = get_order(vmcs_config.size);
1222 vmcs_conf->revision_id = vmx_msr_low;
1224 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1225 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1226 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1227 vmcs_conf->vmexit_ctrl = _vmexit_control;
1228 vmcs_conf->vmentry_ctrl = _vmentry_control;
1233 static struct vmcs *alloc_vmcs_cpu(int cpu)
1235 int node = cpu_to_node(cpu);
1239 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1242 vmcs = page_address(pages);
1243 memset(vmcs, 0, vmcs_config.size);
1244 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1248 static struct vmcs *alloc_vmcs(void)
1250 return alloc_vmcs_cpu(raw_smp_processor_id());
1253 static void free_vmcs(struct vmcs *vmcs)
1255 free_pages((unsigned long)vmcs, vmcs_config.order);
1258 static void free_kvm_area(void)
1262 for_each_online_cpu(cpu)
1263 free_vmcs(per_cpu(vmxarea, cpu));
1266 static __init int alloc_kvm_area(void)
1270 for_each_online_cpu(cpu) {
1273 vmcs = alloc_vmcs_cpu(cpu);
1279 per_cpu(vmxarea, cpu) = vmcs;
1284 static __init int hardware_setup(void)
1286 if (setup_vmcs_config(&vmcs_config) < 0)
1289 if (boot_cpu_has(X86_FEATURE_NX))
1290 kvm_enable_efer_bits(EFER_NX);
1292 return alloc_kvm_area();
1295 static __exit void hardware_unsetup(void)
1300 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1302 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1304 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1305 vmcs_write16(sf->selector, save->selector);
1306 vmcs_writel(sf->base, save->base);
1307 vmcs_write32(sf->limit, save->limit);
1308 vmcs_write32(sf->ar_bytes, save->ar);
1310 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1312 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1316 static void enter_pmode(struct kvm_vcpu *vcpu)
1318 unsigned long flags;
1319 struct vcpu_vmx *vmx = to_vmx(vcpu);
1321 vmx->emulation_required = 1;
1322 vcpu->arch.rmode.active = 0;
1324 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1325 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1326 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1328 flags = vmcs_readl(GUEST_RFLAGS);
1329 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1330 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1331 vmcs_writel(GUEST_RFLAGS, flags);
1333 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1334 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1336 update_exception_bitmap(vcpu);
1338 if (emulate_invalid_guest_state)
1341 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1342 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1343 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1344 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1346 vmcs_write16(GUEST_SS_SELECTOR, 0);
1347 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1349 vmcs_write16(GUEST_CS_SELECTOR,
1350 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1351 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1354 static gva_t rmode_tss_base(struct kvm *kvm)
1356 if (!kvm->arch.tss_addr) {
1357 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1358 kvm->memslots[0].npages - 3;
1359 return base_gfn << PAGE_SHIFT;
1361 return kvm->arch.tss_addr;
1364 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1366 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1368 save->selector = vmcs_read16(sf->selector);
1369 save->base = vmcs_readl(sf->base);
1370 save->limit = vmcs_read32(sf->limit);
1371 save->ar = vmcs_read32(sf->ar_bytes);
1372 vmcs_write16(sf->selector, save->base >> 4);
1373 vmcs_write32(sf->base, save->base & 0xfffff);
1374 vmcs_write32(sf->limit, 0xffff);
1375 vmcs_write32(sf->ar_bytes, 0xf3);
1378 static void enter_rmode(struct kvm_vcpu *vcpu)
1380 unsigned long flags;
1381 struct vcpu_vmx *vmx = to_vmx(vcpu);
1383 vmx->emulation_required = 1;
1384 vcpu->arch.rmode.active = 1;
1386 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1387 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1389 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1390 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1392 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1393 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1395 flags = vmcs_readl(GUEST_RFLAGS);
1396 vcpu->arch.rmode.save_iopl
1397 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1399 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1401 vmcs_writel(GUEST_RFLAGS, flags);
1402 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1403 update_exception_bitmap(vcpu);
1405 if (emulate_invalid_guest_state)
1406 goto continue_rmode;
1408 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1409 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1410 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1412 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1413 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1414 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1415 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1416 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1418 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1419 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1420 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1421 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1424 kvm_mmu_reset_context(vcpu);
1425 init_rmode(vcpu->kvm);
1428 #ifdef CONFIG_X86_64
1430 static void enter_lmode(struct kvm_vcpu *vcpu)
1434 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1435 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1436 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1438 vmcs_write32(GUEST_TR_AR_BYTES,
1439 (guest_tr_ar & ~AR_TYPE_MASK)
1440 | AR_TYPE_BUSY_64_TSS);
1443 vcpu->arch.shadow_efer |= EFER_LMA;
1445 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1446 vmcs_write32(VM_ENTRY_CONTROLS,
1447 vmcs_read32(VM_ENTRY_CONTROLS)
1448 | VM_ENTRY_IA32E_MODE);
1451 static void exit_lmode(struct kvm_vcpu *vcpu)
1453 vcpu->arch.shadow_efer &= ~EFER_LMA;
1455 vmcs_write32(VM_ENTRY_CONTROLS,
1456 vmcs_read32(VM_ENTRY_CONTROLS)
1457 & ~VM_ENTRY_IA32E_MODE);
1462 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1464 vpid_sync_vcpu_all(to_vmx(vcpu));
1466 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1469 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1471 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1472 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1475 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1477 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1478 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1479 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1482 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1483 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1484 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1485 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1489 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1491 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1493 struct kvm_vcpu *vcpu)
1495 if (!(cr0 & X86_CR0_PG)) {
1496 /* From paging/starting to nonpaging */
1497 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1498 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1499 (CPU_BASED_CR3_LOAD_EXITING |
1500 CPU_BASED_CR3_STORE_EXITING));
1501 vcpu->arch.cr0 = cr0;
1502 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1503 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1504 *hw_cr0 &= ~X86_CR0_WP;
1505 } else if (!is_paging(vcpu)) {
1506 /* From nonpaging to paging */
1507 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1508 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1509 ~(CPU_BASED_CR3_LOAD_EXITING |
1510 CPU_BASED_CR3_STORE_EXITING));
1511 vcpu->arch.cr0 = cr0;
1512 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1513 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1514 *hw_cr0 &= ~X86_CR0_WP;
1518 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1519 struct kvm_vcpu *vcpu)
1521 if (!is_paging(vcpu)) {
1522 *hw_cr4 &= ~X86_CR4_PAE;
1523 *hw_cr4 |= X86_CR4_PSE;
1524 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1525 *hw_cr4 &= ~X86_CR4_PAE;
1528 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1530 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1531 KVM_VM_CR0_ALWAYS_ON;
1533 vmx_fpu_deactivate(vcpu);
1535 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1538 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1541 #ifdef CONFIG_X86_64
1542 if (vcpu->arch.shadow_efer & EFER_LME) {
1543 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1545 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1551 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1553 vmcs_writel(CR0_READ_SHADOW, cr0);
1554 vmcs_writel(GUEST_CR0, hw_cr0);
1555 vcpu->arch.cr0 = cr0;
1557 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1558 vmx_fpu_activate(vcpu);
1561 static u64 construct_eptp(unsigned long root_hpa)
1565 /* TODO write the value reading from MSR */
1566 eptp = VMX_EPT_DEFAULT_MT |
1567 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1568 eptp |= (root_hpa & PAGE_MASK);
1573 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1575 unsigned long guest_cr3;
1579 if (vm_need_ept()) {
1580 eptp = construct_eptp(cr3);
1581 vmcs_write64(EPT_POINTER, eptp);
1582 ept_sync_context(eptp);
1583 ept_load_pdptrs(vcpu);
1584 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1585 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1588 vmx_flush_tlb(vcpu);
1589 vmcs_writel(GUEST_CR3, guest_cr3);
1590 if (vcpu->arch.cr0 & X86_CR0_PE)
1591 vmx_fpu_deactivate(vcpu);
1594 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1596 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1597 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1599 vcpu->arch.cr4 = cr4;
1601 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1603 vmcs_writel(CR4_READ_SHADOW, cr4);
1604 vmcs_writel(GUEST_CR4, hw_cr4);
1607 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1609 struct vcpu_vmx *vmx = to_vmx(vcpu);
1610 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1612 vcpu->arch.shadow_efer = efer;
1615 if (efer & EFER_LMA) {
1616 vmcs_write32(VM_ENTRY_CONTROLS,
1617 vmcs_read32(VM_ENTRY_CONTROLS) |
1618 VM_ENTRY_IA32E_MODE);
1622 vmcs_write32(VM_ENTRY_CONTROLS,
1623 vmcs_read32(VM_ENTRY_CONTROLS) &
1624 ~VM_ENTRY_IA32E_MODE);
1626 msr->data = efer & ~EFER_LME;
1631 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1633 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1635 return vmcs_readl(sf->base);
1638 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1639 struct kvm_segment *var, int seg)
1641 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1644 var->base = vmcs_readl(sf->base);
1645 var->limit = vmcs_read32(sf->limit);
1646 var->selector = vmcs_read16(sf->selector);
1647 ar = vmcs_read32(sf->ar_bytes);
1648 if (ar & AR_UNUSABLE_MASK)
1650 var->type = ar & 15;
1651 var->s = (ar >> 4) & 1;
1652 var->dpl = (ar >> 5) & 3;
1653 var->present = (ar >> 7) & 1;
1654 var->avl = (ar >> 12) & 1;
1655 var->l = (ar >> 13) & 1;
1656 var->db = (ar >> 14) & 1;
1657 var->g = (ar >> 15) & 1;
1658 var->unusable = (ar >> 16) & 1;
1661 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1663 struct kvm_segment kvm_seg;
1665 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1668 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1671 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1672 return kvm_seg.selector & 3;
1675 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1682 ar = var->type & 15;
1683 ar |= (var->s & 1) << 4;
1684 ar |= (var->dpl & 3) << 5;
1685 ar |= (var->present & 1) << 7;
1686 ar |= (var->avl & 1) << 12;
1687 ar |= (var->l & 1) << 13;
1688 ar |= (var->db & 1) << 14;
1689 ar |= (var->g & 1) << 15;
1691 if (ar == 0) /* a 0 value means unusable */
1692 ar = AR_UNUSABLE_MASK;
1697 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1698 struct kvm_segment *var, int seg)
1700 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1703 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1704 vcpu->arch.rmode.tr.selector = var->selector;
1705 vcpu->arch.rmode.tr.base = var->base;
1706 vcpu->arch.rmode.tr.limit = var->limit;
1707 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1710 vmcs_writel(sf->base, var->base);
1711 vmcs_write32(sf->limit, var->limit);
1712 vmcs_write16(sf->selector, var->selector);
1713 if (vcpu->arch.rmode.active && var->s) {
1715 * Hack real-mode segments into vm86 compatibility.
1717 if (var->base == 0xffff0000 && var->selector == 0xf000)
1718 vmcs_writel(sf->base, 0xf0000);
1721 ar = vmx_segment_access_rights(var);
1722 vmcs_write32(sf->ar_bytes, ar);
1725 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1727 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1729 *db = (ar >> 14) & 1;
1730 *l = (ar >> 13) & 1;
1733 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1735 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1736 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1739 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1741 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1742 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1745 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1747 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1748 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1751 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1753 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1754 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1757 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1759 struct kvm_segment var;
1762 vmx_get_segment(vcpu, &var, seg);
1763 ar = vmx_segment_access_rights(&var);
1765 if (var.base != (var.selector << 4))
1767 if (var.limit != 0xffff)
1775 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1777 struct kvm_segment cs;
1778 unsigned int cs_rpl;
1780 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1781 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1783 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1787 if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) {
1788 if (cs.dpl > cs_rpl)
1790 } else if (cs.type & AR_TYPE_CODE_MASK) {
1791 if (cs.dpl != cs_rpl)
1797 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1801 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1803 struct kvm_segment ss;
1804 unsigned int ss_rpl;
1806 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1807 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1809 if ((ss.type != 3) || (ss.type != 7))
1813 if (ss.dpl != ss_rpl) /* DPL != RPL */
1821 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1823 struct kvm_segment var;
1826 vmx_get_segment(vcpu, &var, seg);
1827 rpl = var.selector & SELECTOR_RPL_MASK;
1833 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1834 if (var.dpl < rpl) /* DPL < RPL */
1838 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1844 static bool tr_valid(struct kvm_vcpu *vcpu)
1846 struct kvm_segment tr;
1848 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1850 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1852 if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */
1860 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1862 struct kvm_segment ldtr;
1864 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1866 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1876 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1878 struct kvm_segment cs, ss;
1880 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1881 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1883 return ((cs.selector & SELECTOR_RPL_MASK) ==
1884 (ss.selector & SELECTOR_RPL_MASK));
1888 * Check if guest state is valid. Returns true if valid, false if
1890 * We assume that registers are always usable
1892 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1894 /* real mode guest state checks */
1895 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1896 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1898 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1900 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1902 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1904 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1906 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1909 /* protected mode guest state checks */
1910 if (!cs_ss_rpl_check(vcpu))
1912 if (!code_segment_valid(vcpu))
1914 if (!stack_segment_valid(vcpu))
1916 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1918 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1920 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1922 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1924 if (!tr_valid(vcpu))
1926 if (!ldtr_valid(vcpu))
1930 * - Add checks on RIP
1931 * - Add checks on RFLAGS
1937 static int init_rmode_tss(struct kvm *kvm)
1939 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1944 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1947 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1948 r = kvm_write_guest_page(kvm, fn++, &data,
1949 TSS_IOPB_BASE_OFFSET, sizeof(u16));
1952 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1955 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1959 r = kvm_write_guest_page(kvm, fn, &data,
1960 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1970 static int init_rmode_identity_map(struct kvm *kvm)
1973 pfn_t identity_map_pfn;
1978 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1979 printk(KERN_ERR "EPT: identity-mapping pagetable "
1980 "haven't been allocated!\n");
1983 if (likely(kvm->arch.ept_identity_pagetable_done))
1986 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1987 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1990 /* Set up identity-mapping pagetable for EPT in real mode */
1991 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1992 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1993 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1994 r = kvm_write_guest_page(kvm, identity_map_pfn,
1995 &tmp, i * sizeof(tmp), sizeof(tmp));
1999 kvm->arch.ept_identity_pagetable_done = true;
2005 static void seg_setup(int seg)
2007 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2009 vmcs_write16(sf->selector, 0);
2010 vmcs_writel(sf->base, 0);
2011 vmcs_write32(sf->limit, 0xffff);
2012 vmcs_write32(sf->ar_bytes, 0xf3);
2015 static int alloc_apic_access_page(struct kvm *kvm)
2017 struct kvm_userspace_memory_region kvm_userspace_mem;
2020 down_write(&kvm->slots_lock);
2021 if (kvm->arch.apic_access_page)
2023 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2024 kvm_userspace_mem.flags = 0;
2025 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2026 kvm_userspace_mem.memory_size = PAGE_SIZE;
2027 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2031 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2033 up_write(&kvm->slots_lock);
2037 static int alloc_identity_pagetable(struct kvm *kvm)
2039 struct kvm_userspace_memory_region kvm_userspace_mem;
2042 down_write(&kvm->slots_lock);
2043 if (kvm->arch.ept_identity_pagetable)
2045 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2046 kvm_userspace_mem.flags = 0;
2047 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2048 kvm_userspace_mem.memory_size = PAGE_SIZE;
2049 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2053 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2054 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2056 up_write(&kvm->slots_lock);
2060 static void allocate_vpid(struct vcpu_vmx *vmx)
2065 if (!enable_vpid || !cpu_has_vmx_vpid())
2067 spin_lock(&vmx_vpid_lock);
2068 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2069 if (vpid < VMX_NR_VPIDS) {
2071 __set_bit(vpid, vmx_vpid_bitmap);
2073 spin_unlock(&vmx_vpid_lock);
2076 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
2080 if (!cpu_has_vmx_msr_bitmap())
2084 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2085 * have the write-low and read-high bitmap offsets the wrong way round.
2086 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2088 va = kmap(msr_bitmap);
2089 if (msr <= 0x1fff) {
2090 __clear_bit(msr, va + 0x000); /* read-low */
2091 __clear_bit(msr, va + 0x800); /* write-low */
2092 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2094 __clear_bit(msr, va + 0x400); /* read-high */
2095 __clear_bit(msr, va + 0xc00); /* write-high */
2101 * Sets up the vmcs for emulated real mode.
2103 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2105 u32 host_sysenter_cs, msr_low, msr_high;
2109 struct descriptor_table dt;
2111 unsigned long kvm_vmx_return;
2115 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2116 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
2118 if (cpu_has_vmx_msr_bitmap())
2119 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2121 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2124 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2125 vmcs_config.pin_based_exec_ctrl);
2127 exec_control = vmcs_config.cpu_based_exec_ctrl;
2128 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2129 exec_control &= ~CPU_BASED_TPR_SHADOW;
2130 #ifdef CONFIG_X86_64
2131 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2132 CPU_BASED_CR8_LOAD_EXITING;
2136 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2137 CPU_BASED_CR3_LOAD_EXITING |
2138 CPU_BASED_INVLPG_EXITING;
2139 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2141 if (cpu_has_secondary_exec_ctrls()) {
2142 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2143 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2145 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2147 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2149 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2150 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2153 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2154 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2155 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2157 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2158 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2159 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2161 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2162 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2163 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2164 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2165 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2166 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2167 #ifdef CONFIG_X86_64
2168 rdmsrl(MSR_FS_BASE, a);
2169 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2170 rdmsrl(MSR_GS_BASE, a);
2171 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2173 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2174 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2177 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2180 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2182 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2183 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2184 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2185 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2186 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2188 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2189 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2190 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2191 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2192 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2193 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2195 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2196 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2197 host_pat = msr_low | ((u64) msr_high << 32);
2198 vmcs_write64(HOST_IA32_PAT, host_pat);
2200 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2201 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2202 host_pat = msr_low | ((u64) msr_high << 32);
2203 /* Write the default value follow host pat */
2204 vmcs_write64(GUEST_IA32_PAT, host_pat);
2205 /* Keep arch.pat sync with GUEST_IA32_PAT */
2206 vmx->vcpu.arch.pat = host_pat;
2209 for (i = 0; i < NR_VMX_MSR; ++i) {
2210 u32 index = vmx_msr_index[i];
2211 u32 data_low, data_high;
2215 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2217 if (wrmsr_safe(index, data_low, data_high) < 0)
2219 data = data_low | ((u64)data_high << 32);
2220 vmx->host_msrs[j].index = index;
2221 vmx->host_msrs[j].reserved = 0;
2222 vmx->host_msrs[j].data = data;
2223 vmx->guest_msrs[j] = vmx->host_msrs[j];
2227 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2229 /* 22.2.1, 20.8.1 */
2230 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2232 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2233 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2239 static int init_rmode(struct kvm *kvm)
2241 if (!init_rmode_tss(kvm))
2243 if (!init_rmode_identity_map(kvm))
2248 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2250 struct vcpu_vmx *vmx = to_vmx(vcpu);
2254 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2255 down_read(&vcpu->kvm->slots_lock);
2256 if (!init_rmode(vmx->vcpu.kvm)) {
2261 vmx->vcpu.arch.rmode.active = 0;
2263 vmx->soft_vnmi_blocked = 0;
2265 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2266 kvm_set_cr8(&vmx->vcpu, 0);
2267 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2268 if (vmx->vcpu.vcpu_id == 0)
2269 msr |= MSR_IA32_APICBASE_BSP;
2270 kvm_set_apic_base(&vmx->vcpu, msr);
2272 fx_init(&vmx->vcpu);
2274 seg_setup(VCPU_SREG_CS);
2276 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2277 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2279 if (vmx->vcpu.vcpu_id == 0) {
2280 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2281 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2283 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2284 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2287 seg_setup(VCPU_SREG_DS);
2288 seg_setup(VCPU_SREG_ES);
2289 seg_setup(VCPU_SREG_FS);
2290 seg_setup(VCPU_SREG_GS);
2291 seg_setup(VCPU_SREG_SS);
2293 vmcs_write16(GUEST_TR_SELECTOR, 0);
2294 vmcs_writel(GUEST_TR_BASE, 0);
2295 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2296 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2298 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2299 vmcs_writel(GUEST_LDTR_BASE, 0);
2300 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2301 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2303 vmcs_write32(GUEST_SYSENTER_CS, 0);
2304 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2305 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2307 vmcs_writel(GUEST_RFLAGS, 0x02);
2308 if (vmx->vcpu.vcpu_id == 0)
2309 kvm_rip_write(vcpu, 0xfff0);
2311 kvm_rip_write(vcpu, 0);
2312 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2314 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2315 vmcs_writel(GUEST_DR7, 0x400);
2317 vmcs_writel(GUEST_GDTR_BASE, 0);
2318 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2320 vmcs_writel(GUEST_IDTR_BASE, 0);
2321 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2323 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2324 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2325 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2329 /* Special registers */
2330 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2334 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2336 if (cpu_has_vmx_tpr_shadow()) {
2337 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2338 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2339 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2340 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2341 vmcs_write32(TPR_THRESHOLD, 0);
2344 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2345 vmcs_write64(APIC_ACCESS_ADDR,
2346 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2349 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2351 vmx->vcpu.arch.cr0 = 0x60000010;
2352 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2353 vmx_set_cr4(&vmx->vcpu, 0);
2354 vmx_set_efer(&vmx->vcpu, 0);
2355 vmx_fpu_activate(&vmx->vcpu);
2356 update_exception_bitmap(&vmx->vcpu);
2358 vpid_sync_vcpu_all(vmx);
2362 /* HACK: Don't enable emulation on guest boot/reset */
2363 vmx->emulation_required = 0;
2366 up_read(&vcpu->kvm->slots_lock);
2370 static void enable_irq_window(struct kvm_vcpu *vcpu)
2372 u32 cpu_based_vm_exec_control;
2374 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2375 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2376 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2379 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2381 u32 cpu_based_vm_exec_control;
2383 if (!cpu_has_virtual_nmis()) {
2384 enable_irq_window(vcpu);
2388 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2389 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2390 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2393 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2395 struct vcpu_vmx *vmx = to_vmx(vcpu);
2397 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2399 ++vcpu->stat.irq_injections;
2400 if (vcpu->arch.rmode.active) {
2401 vmx->rmode.irq.pending = true;
2402 vmx->rmode.irq.vector = irq;
2403 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2404 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2405 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2406 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2407 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2410 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2411 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2414 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2416 struct vcpu_vmx *vmx = to_vmx(vcpu);
2418 if (!cpu_has_virtual_nmis()) {
2420 * Tracking the NMI-blocked state in software is built upon
2421 * finding the next open IRQ window. This, in turn, depends on
2422 * well-behaving guests: They have to keep IRQs disabled at
2423 * least as long as the NMI handler runs. Otherwise we may
2424 * cause NMI nesting, maybe breaking the guest. But as this is
2425 * highly unlikely, we can live with the residual risk.
2427 vmx->soft_vnmi_blocked = 1;
2428 vmx->vnmi_blocked_time = 0;
2431 ++vcpu->stat.nmi_injections;
2432 if (vcpu->arch.rmode.active) {
2433 vmx->rmode.irq.pending = true;
2434 vmx->rmode.irq.vector = NMI_VECTOR;
2435 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2436 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2437 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2438 INTR_INFO_VALID_MASK);
2439 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2440 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2443 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2444 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2447 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2449 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2451 vcpu->arch.nmi_window_open =
2452 !(guest_intr & (GUEST_INTR_STATE_STI |
2453 GUEST_INTR_STATE_MOV_SS |
2454 GUEST_INTR_STATE_NMI));
2455 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2456 vcpu->arch.nmi_window_open = 0;
2458 vcpu->arch.interrupt_window_open =
2459 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2460 !(guest_intr & (GUEST_INTR_STATE_STI |
2461 GUEST_INTR_STATE_MOV_SS)));
2464 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2466 int word_index = __ffs(vcpu->arch.irq_summary);
2467 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2468 int irq = word_index * BITS_PER_LONG + bit_index;
2470 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2471 if (!vcpu->arch.irq_pending[word_index])
2472 clear_bit(word_index, &vcpu->arch.irq_summary);
2473 kvm_queue_interrupt(vcpu, irq);
2476 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2477 struct kvm_run *kvm_run)
2479 vmx_update_window_states(vcpu);
2481 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2482 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2483 GUEST_INTR_STATE_STI |
2484 GUEST_INTR_STATE_MOV_SS);
2486 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2487 if (vcpu->arch.interrupt.pending) {
2488 enable_nmi_window(vcpu);
2489 } else if (vcpu->arch.nmi_window_open) {
2490 vcpu->arch.nmi_pending = false;
2491 vcpu->arch.nmi_injected = true;
2493 enable_nmi_window(vcpu);
2497 if (vcpu->arch.nmi_injected) {
2498 vmx_inject_nmi(vcpu);
2499 if (vcpu->arch.nmi_pending)
2500 enable_nmi_window(vcpu);
2501 else if (vcpu->arch.irq_summary
2502 || kvm_run->request_interrupt_window)
2503 enable_irq_window(vcpu);
2507 if (vcpu->arch.interrupt_window_open) {
2508 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2509 kvm_do_inject_irq(vcpu);
2511 if (vcpu->arch.interrupt.pending)
2512 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2514 if (!vcpu->arch.interrupt_window_open &&
2515 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2516 enable_irq_window(vcpu);
2519 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2522 struct kvm_userspace_memory_region tss_mem = {
2523 .slot = TSS_PRIVATE_MEMSLOT,
2524 .guest_phys_addr = addr,
2525 .memory_size = PAGE_SIZE * 3,
2529 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2532 kvm->arch.tss_addr = addr;
2536 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2537 int vec, u32 err_code)
2540 * Instruction with address size override prefix opcode 0x67
2541 * Cause the #SS fault with 0 error code in VM86 mode.
2543 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2544 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2547 * Forward all other exceptions that are valid in real mode.
2548 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2549 * the required debugging infrastructure rework.
2553 if (vcpu->guest_debug &
2554 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2556 kvm_queue_exception(vcpu, vec);
2559 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2570 kvm_queue_exception(vcpu, vec);
2576 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2578 struct vcpu_vmx *vmx = to_vmx(vcpu);
2579 u32 intr_info, ex_no, error_code;
2580 unsigned long cr2, rip;
2582 enum emulation_result er;
2584 vect_info = vmx->idt_vectoring_info;
2585 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2587 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2588 !is_page_fault(intr_info))
2589 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2590 "intr info 0x%x\n", __func__, vect_info, intr_info);
2592 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2593 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2594 set_bit(irq, vcpu->arch.irq_pending);
2595 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2598 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2599 return 1; /* already handled by vmx_vcpu_run() */
2601 if (is_no_device(intr_info)) {
2602 vmx_fpu_activate(vcpu);
2606 if (is_invalid_opcode(intr_info)) {
2607 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2608 if (er != EMULATE_DONE)
2609 kvm_queue_exception(vcpu, UD_VECTOR);
2614 rip = kvm_rip_read(vcpu);
2615 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2616 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2617 if (is_page_fault(intr_info)) {
2618 /* EPT won't cause page fault directly */
2621 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2622 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2623 (u32)((u64)cr2 >> 32), handler);
2624 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2625 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2626 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2629 if (vcpu->arch.rmode.active &&
2630 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2632 if (vcpu->arch.halt_request) {
2633 vcpu->arch.halt_request = 0;
2634 return kvm_emulate_halt(vcpu);
2639 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2640 if (ex_no == DB_VECTOR || ex_no == BP_VECTOR) {
2641 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2642 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2643 kvm_run->debug.arch.exception = ex_no;
2645 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2646 kvm_run->ex.exception = ex_no;
2647 kvm_run->ex.error_code = error_code;
2652 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2653 struct kvm_run *kvm_run)
2655 ++vcpu->stat.irq_exits;
2656 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2660 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2662 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2666 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2668 unsigned long exit_qualification;
2669 int size, down, in, string, rep;
2672 ++vcpu->stat.io_exits;
2673 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2674 string = (exit_qualification & 16) != 0;
2677 if (emulate_instruction(vcpu,
2678 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2683 size = (exit_qualification & 7) + 1;
2684 in = (exit_qualification & 8) != 0;
2685 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2686 rep = (exit_qualification & 32) != 0;
2687 port = exit_qualification >> 16;
2689 skip_emulated_instruction(vcpu);
2690 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2694 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2697 * Patch in the VMCALL instruction:
2699 hypercall[0] = 0x0f;
2700 hypercall[1] = 0x01;
2701 hypercall[2] = 0xc1;
2704 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2706 unsigned long exit_qualification;
2710 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2711 cr = exit_qualification & 15;
2712 reg = (exit_qualification >> 8) & 15;
2713 switch ((exit_qualification >> 4) & 3) {
2714 case 0: /* mov to cr */
2715 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2716 (u32)kvm_register_read(vcpu, reg),
2717 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2721 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2722 skip_emulated_instruction(vcpu);
2725 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2726 skip_emulated_instruction(vcpu);
2729 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2730 skip_emulated_instruction(vcpu);
2733 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2734 skip_emulated_instruction(vcpu);
2735 if (irqchip_in_kernel(vcpu->kvm))
2737 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2742 vmx_fpu_deactivate(vcpu);
2743 vcpu->arch.cr0 &= ~X86_CR0_TS;
2744 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2745 vmx_fpu_activate(vcpu);
2746 KVMTRACE_0D(CLTS, vcpu, handler);
2747 skip_emulated_instruction(vcpu);
2749 case 1: /*mov from cr*/
2752 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2753 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2754 (u32)kvm_register_read(vcpu, reg),
2755 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2757 skip_emulated_instruction(vcpu);
2760 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2761 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2762 (u32)kvm_register_read(vcpu, reg), handler);
2763 skip_emulated_instruction(vcpu);
2768 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2770 skip_emulated_instruction(vcpu);
2775 kvm_run->exit_reason = 0;
2776 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2777 (int)(exit_qualification >> 4) & 3, cr);
2781 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2783 unsigned long exit_qualification;
2788 * FIXME: this code assumes the host is debugging the guest.
2789 * need to deal with guest debugging itself too.
2791 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2792 dr = exit_qualification & 7;
2793 reg = (exit_qualification >> 8) & 15;
2794 if (exit_qualification & 16) {
2806 kvm_register_write(vcpu, reg, val);
2807 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2811 skip_emulated_instruction(vcpu);
2815 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2817 kvm_emulate_cpuid(vcpu);
2821 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2823 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2826 if (vmx_get_msr(vcpu, ecx, &data)) {
2827 kvm_inject_gp(vcpu, 0);
2831 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2834 /* FIXME: handling of bits 32:63 of rax, rdx */
2835 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2836 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2837 skip_emulated_instruction(vcpu);
2841 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2843 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2844 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2845 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2847 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2850 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2851 kvm_inject_gp(vcpu, 0);
2855 skip_emulated_instruction(vcpu);
2859 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2860 struct kvm_run *kvm_run)
2865 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2866 struct kvm_run *kvm_run)
2868 u32 cpu_based_vm_exec_control;
2870 /* clear pending irq */
2871 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2872 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2873 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2875 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2876 ++vcpu->stat.irq_window_exits;
2879 * If the user space waits to inject interrupts, exit as soon as
2882 if (kvm_run->request_interrupt_window &&
2883 !vcpu->arch.irq_summary) {
2884 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2890 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2892 skip_emulated_instruction(vcpu);
2893 return kvm_emulate_halt(vcpu);
2896 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2898 skip_emulated_instruction(vcpu);
2899 kvm_emulate_hypercall(vcpu);
2903 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2905 u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2907 kvm_mmu_invlpg(vcpu, exit_qualification);
2908 skip_emulated_instruction(vcpu);
2912 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2914 skip_emulated_instruction(vcpu);
2915 /* TODO: Add support for VT-d/pass-through device */
2919 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2921 u64 exit_qualification;
2922 enum emulation_result er;
2923 unsigned long offset;
2925 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2926 offset = exit_qualification & 0xffful;
2928 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2930 if (er != EMULATE_DONE) {
2932 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2939 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2941 struct vcpu_vmx *vmx = to_vmx(vcpu);
2942 unsigned long exit_qualification;
2946 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2948 reason = (u32)exit_qualification >> 30;
2949 if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
2950 (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
2951 (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
2952 == INTR_TYPE_NMI_INTR) {
2953 vcpu->arch.nmi_injected = false;
2954 if (cpu_has_virtual_nmis())
2955 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2956 GUEST_INTR_STATE_NMI);
2958 tss_selector = exit_qualification;
2960 return kvm_task_switch(vcpu, tss_selector, reason);
2963 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2965 u64 exit_qualification;
2966 enum emulation_result er;
2972 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2974 if (exit_qualification & (1 << 6)) {
2975 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2979 gla_validity = (exit_qualification >> 7) & 0x3;
2980 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2981 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2982 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2983 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2984 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2985 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2986 (long unsigned int)exit_qualification);
2987 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2988 kvm_run->hw.hardware_exit_reason = 0;
2992 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2993 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2994 if (!kvm_is_error_hva(hva)) {
2995 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2997 printk(KERN_ERR "EPT: Not enough memory!\n");
3003 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3005 if (er == EMULATE_FAIL) {
3007 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
3009 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3010 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3011 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3012 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3013 (long unsigned int)exit_qualification);
3015 } else if (er == EMULATE_DO_MMIO)
3021 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3023 u32 cpu_based_vm_exec_control;
3025 /* clear pending NMI */
3026 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3027 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3028 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3029 ++vcpu->stat.nmi_window_exits;
3034 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3035 struct kvm_run *kvm_run)
3037 struct vcpu_vmx *vmx = to_vmx(vcpu);
3043 while (!guest_state_valid(vcpu)) {
3044 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3046 if (err == EMULATE_DO_MMIO)
3049 if (err != EMULATE_DONE) {
3050 kvm_report_emulation_failure(vcpu, "emulation failure");
3054 if (signal_pending(current))
3060 local_irq_disable();
3063 /* Guest state should be valid now except if we need to
3064 * emulate an MMIO */
3065 if (guest_state_valid(vcpu))
3066 vmx->emulation_required = 0;
3070 * The exit handlers return 1 if the exit was handled fully and guest execution
3071 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3072 * to be done to userspace and return 0.
3074 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3075 struct kvm_run *kvm_run) = {
3076 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3077 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3078 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3079 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3080 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3081 [EXIT_REASON_CR_ACCESS] = handle_cr,
3082 [EXIT_REASON_DR_ACCESS] = handle_dr,
3083 [EXIT_REASON_CPUID] = handle_cpuid,
3084 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3085 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3086 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3087 [EXIT_REASON_HLT] = handle_halt,
3088 [EXIT_REASON_INVLPG] = handle_invlpg,
3089 [EXIT_REASON_VMCALL] = handle_vmcall,
3090 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3091 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3092 [EXIT_REASON_WBINVD] = handle_wbinvd,
3093 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3094 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3097 static const int kvm_vmx_max_exit_handlers =
3098 ARRAY_SIZE(kvm_vmx_exit_handlers);
3101 * The guest has exited. See if we can fix it or if we need userspace
3104 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3106 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
3107 struct vcpu_vmx *vmx = to_vmx(vcpu);
3108 u32 vectoring_info = vmx->idt_vectoring_info;
3110 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3111 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3113 /* If we need to emulate an MMIO from handle_invalid_guest_state
3114 * we just return 0 */
3115 if (vmx->emulation_required && emulate_invalid_guest_state)
3118 /* Access CR3 don't cause VMExit in paging mode, so we need
3119 * to sync with guest real CR3. */
3120 if (vm_need_ept() && is_paging(vcpu)) {
3121 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3122 ept_load_pdptrs(vcpu);
3125 if (unlikely(vmx->fail)) {
3126 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3127 kvm_run->fail_entry.hardware_entry_failure_reason
3128 = vmcs_read32(VM_INSTRUCTION_ERROR);
3132 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3133 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3134 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3135 exit_reason != EXIT_REASON_TASK_SWITCH))
3136 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3137 "(0x%x) and exit reason is 0x%x\n",
3138 __func__, vectoring_info, exit_reason);
3140 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3141 if (vcpu->arch.interrupt_window_open) {
3142 vmx->soft_vnmi_blocked = 0;
3143 vcpu->arch.nmi_window_open = 1;
3144 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3145 vcpu->arch.nmi_pending) {
3147 * This CPU don't support us in finding the end of an
3148 * NMI-blocked window if the guest runs with IRQs
3149 * disabled. So we pull the trigger after 1 s of
3150 * futile waiting, but inform the user about this.
3152 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3153 "state on VCPU %d after 1 s timeout\n",
3154 __func__, vcpu->vcpu_id);
3155 vmx->soft_vnmi_blocked = 0;
3156 vmx->vcpu.arch.nmi_window_open = 1;
3160 if (exit_reason < kvm_vmx_max_exit_handlers
3161 && kvm_vmx_exit_handlers[exit_reason])
3162 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3164 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3165 kvm_run->hw.hardware_exit_reason = exit_reason;
3170 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3174 if (!vm_need_tpr_shadow(vcpu->kvm))
3177 if (!kvm_lapic_enabled(vcpu) ||
3178 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3179 vmcs_write32(TPR_THRESHOLD, 0);
3183 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3184 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3187 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3190 u32 idt_vectoring_info;
3194 bool idtv_info_valid;
3197 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3198 if (cpu_has_virtual_nmis()) {
3199 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3200 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3203 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3204 * a guest IRET fault.
3206 if (unblock_nmi && vector != DF_VECTOR)
3207 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3208 GUEST_INTR_STATE_NMI);
3209 } else if (unlikely(vmx->soft_vnmi_blocked))
3210 vmx->vnmi_blocked_time +=
3211 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3213 idt_vectoring_info = vmx->idt_vectoring_info;
3214 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3215 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3216 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3217 if (vmx->vcpu.arch.nmi_injected) {
3220 * Clear bit "block by NMI" before VM entry if a NMI delivery
3223 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3224 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3225 GUEST_INTR_STATE_NMI);
3227 vmx->vcpu.arch.nmi_injected = false;
3229 kvm_clear_exception_queue(&vmx->vcpu);
3230 if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3231 type == INTR_TYPE_SOFT_EXCEPTION)) {
3232 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3233 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3234 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3236 kvm_queue_exception(&vmx->vcpu, vector);
3237 vmx->idt_vectoring_info = 0;
3239 kvm_clear_interrupt_queue(&vmx->vcpu);
3240 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3241 kvm_queue_interrupt(&vmx->vcpu, vector);
3242 vmx->idt_vectoring_info = 0;
3246 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3248 update_tpr_threshold(vcpu);
3250 vmx_update_window_states(vcpu);
3252 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3253 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3254 GUEST_INTR_STATE_STI |
3255 GUEST_INTR_STATE_MOV_SS);
3257 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3258 if (vcpu->arch.interrupt.pending) {
3259 enable_nmi_window(vcpu);
3260 } else if (vcpu->arch.nmi_window_open) {
3261 vcpu->arch.nmi_pending = false;
3262 vcpu->arch.nmi_injected = true;
3264 enable_nmi_window(vcpu);
3268 if (vcpu->arch.nmi_injected) {
3269 vmx_inject_nmi(vcpu);
3270 if (vcpu->arch.nmi_pending)
3271 enable_nmi_window(vcpu);
3272 else if (kvm_cpu_has_interrupt(vcpu))
3273 enable_irq_window(vcpu);
3276 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3277 if (vcpu->arch.interrupt_window_open)
3278 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3280 enable_irq_window(vcpu);
3282 if (vcpu->arch.interrupt.pending) {
3283 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3284 if (kvm_cpu_has_interrupt(vcpu))
3285 enable_irq_window(vcpu);
3290 * Failure to inject an interrupt should give us the information
3291 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3292 * when fetching the interrupt redirection bitmap in the real-mode
3293 * tss, this doesn't happen. So we do it ourselves.
3295 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3297 vmx->rmode.irq.pending = 0;
3298 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3300 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3301 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3302 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3303 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3306 vmx->idt_vectoring_info =
3307 VECTORING_INFO_VALID_MASK
3308 | INTR_TYPE_EXT_INTR
3309 | vmx->rmode.irq.vector;
3312 #ifdef CONFIG_X86_64
3320 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3322 struct vcpu_vmx *vmx = to_vmx(vcpu);
3325 /* Record the guest's net vcpu time for enforced NMI injections. */
3326 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3327 vmx->entry_time = ktime_get();
3329 /* Handle invalid guest state instead of entering VMX */
3330 if (vmx->emulation_required && emulate_invalid_guest_state) {
3331 handle_invalid_guest_state(vcpu, kvm_run);
3335 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3336 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3337 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3338 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3341 * Loading guest fpu may have cleared host cr0.ts
3343 vmcs_writel(HOST_CR0, read_cr0());
3346 /* Store host registers */
3347 "push %%"R"dx; push %%"R"bp;"
3349 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3351 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3352 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3354 /* Check if vmlaunch of vmresume is needed */
3355 "cmpl $0, %c[launched](%0) \n\t"
3356 /* Load guest registers. Don't clobber flags. */
3357 "mov %c[cr2](%0), %%"R"ax \n\t"
3358 "mov %%"R"ax, %%cr2 \n\t"
3359 "mov %c[rax](%0), %%"R"ax \n\t"
3360 "mov %c[rbx](%0), %%"R"bx \n\t"
3361 "mov %c[rdx](%0), %%"R"dx \n\t"
3362 "mov %c[rsi](%0), %%"R"si \n\t"
3363 "mov %c[rdi](%0), %%"R"di \n\t"
3364 "mov %c[rbp](%0), %%"R"bp \n\t"
3365 #ifdef CONFIG_X86_64
3366 "mov %c[r8](%0), %%r8 \n\t"
3367 "mov %c[r9](%0), %%r9 \n\t"
3368 "mov %c[r10](%0), %%r10 \n\t"
3369 "mov %c[r11](%0), %%r11 \n\t"
3370 "mov %c[r12](%0), %%r12 \n\t"
3371 "mov %c[r13](%0), %%r13 \n\t"
3372 "mov %c[r14](%0), %%r14 \n\t"
3373 "mov %c[r15](%0), %%r15 \n\t"
3375 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3377 /* Enter guest mode */
3378 "jne .Llaunched \n\t"
3379 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3380 "jmp .Lkvm_vmx_return \n\t"
3381 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3382 ".Lkvm_vmx_return: "
3383 /* Save guest registers, load host registers, keep flags */
3384 "xchg %0, (%%"R"sp) \n\t"
3385 "mov %%"R"ax, %c[rax](%0) \n\t"
3386 "mov %%"R"bx, %c[rbx](%0) \n\t"
3387 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3388 "mov %%"R"dx, %c[rdx](%0) \n\t"
3389 "mov %%"R"si, %c[rsi](%0) \n\t"
3390 "mov %%"R"di, %c[rdi](%0) \n\t"
3391 "mov %%"R"bp, %c[rbp](%0) \n\t"
3392 #ifdef CONFIG_X86_64
3393 "mov %%r8, %c[r8](%0) \n\t"
3394 "mov %%r9, %c[r9](%0) \n\t"
3395 "mov %%r10, %c[r10](%0) \n\t"
3396 "mov %%r11, %c[r11](%0) \n\t"
3397 "mov %%r12, %c[r12](%0) \n\t"
3398 "mov %%r13, %c[r13](%0) \n\t"
3399 "mov %%r14, %c[r14](%0) \n\t"
3400 "mov %%r15, %c[r15](%0) \n\t"
3402 "mov %%cr2, %%"R"ax \n\t"
3403 "mov %%"R"ax, %c[cr2](%0) \n\t"
3405 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3406 "setbe %c[fail](%0) \n\t"
3407 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3408 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3409 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3410 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3411 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3412 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3413 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3414 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3415 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3416 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3417 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3418 #ifdef CONFIG_X86_64
3419 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3420 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3421 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3422 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3423 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3424 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3425 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3426 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3428 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3430 , R"bx", R"di", R"si"
3431 #ifdef CONFIG_X86_64
3432 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3436 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3437 vcpu->arch.regs_dirty = 0;
3439 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3440 if (vmx->rmode.irq.pending)
3441 fixup_rmode_irq(vmx);
3443 vmx_update_window_states(vcpu);
3445 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3448 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3450 /* We need to handle NMIs before interrupts are enabled */
3451 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3452 (intr_info & INTR_INFO_VALID_MASK)) {
3453 KVMTRACE_0D(NMI, vcpu, handler);
3457 vmx_complete_interrupts(vmx);
3463 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3465 struct vcpu_vmx *vmx = to_vmx(vcpu);
3469 free_vmcs(vmx->vmcs);
3474 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3476 struct vcpu_vmx *vmx = to_vmx(vcpu);
3478 spin_lock(&vmx_vpid_lock);
3480 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3481 spin_unlock(&vmx_vpid_lock);
3482 vmx_free_vmcs(vcpu);
3483 kfree(vmx->host_msrs);
3484 kfree(vmx->guest_msrs);
3485 kvm_vcpu_uninit(vcpu);
3486 kmem_cache_free(kvm_vcpu_cache, vmx);
3489 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3492 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3496 return ERR_PTR(-ENOMEM);
3500 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3504 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3505 if (!vmx->guest_msrs) {
3510 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3511 if (!vmx->host_msrs)
3512 goto free_guest_msrs;
3514 vmx->vmcs = alloc_vmcs();
3518 vmcs_clear(vmx->vmcs);
3521 vmx_vcpu_load(&vmx->vcpu, cpu);
3522 err = vmx_vcpu_setup(vmx);
3523 vmx_vcpu_put(&vmx->vcpu);
3527 if (vm_need_virtualize_apic_accesses(kvm))
3528 if (alloc_apic_access_page(kvm) != 0)
3532 if (alloc_identity_pagetable(kvm) != 0)
3538 free_vmcs(vmx->vmcs);
3540 kfree(vmx->host_msrs);
3542 kfree(vmx->guest_msrs);
3544 kvm_vcpu_uninit(&vmx->vcpu);
3546 kmem_cache_free(kvm_vcpu_cache, vmx);
3547 return ERR_PTR(err);
3550 static void __init vmx_check_processor_compat(void *rtn)
3552 struct vmcs_config vmcs_conf;
3555 if (setup_vmcs_config(&vmcs_conf) < 0)
3557 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3558 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3559 smp_processor_id());
3564 static int get_ept_level(void)
3566 return VMX_EPT_DEFAULT_GAW + 1;
3569 static int vmx_get_mt_mask_shift(void)
3571 return VMX_EPT_MT_EPTE_SHIFT;
3574 static struct kvm_x86_ops vmx_x86_ops = {
3575 .cpu_has_kvm_support = cpu_has_kvm_support,
3576 .disabled_by_bios = vmx_disabled_by_bios,
3577 .hardware_setup = hardware_setup,
3578 .hardware_unsetup = hardware_unsetup,
3579 .check_processor_compatibility = vmx_check_processor_compat,
3580 .hardware_enable = hardware_enable,
3581 .hardware_disable = hardware_disable,
3582 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3584 .vcpu_create = vmx_create_vcpu,
3585 .vcpu_free = vmx_free_vcpu,
3586 .vcpu_reset = vmx_vcpu_reset,
3588 .prepare_guest_switch = vmx_save_host_state,
3589 .vcpu_load = vmx_vcpu_load,
3590 .vcpu_put = vmx_vcpu_put,
3592 .set_guest_debug = set_guest_debug,
3593 .get_msr = vmx_get_msr,
3594 .set_msr = vmx_set_msr,
3595 .get_segment_base = vmx_get_segment_base,
3596 .get_segment = vmx_get_segment,
3597 .set_segment = vmx_set_segment,
3598 .get_cpl = vmx_get_cpl,
3599 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3600 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3601 .set_cr0 = vmx_set_cr0,
3602 .set_cr3 = vmx_set_cr3,
3603 .set_cr4 = vmx_set_cr4,
3604 .set_efer = vmx_set_efer,
3605 .get_idt = vmx_get_idt,
3606 .set_idt = vmx_set_idt,
3607 .get_gdt = vmx_get_gdt,
3608 .set_gdt = vmx_set_gdt,
3609 .cache_reg = vmx_cache_reg,
3610 .get_rflags = vmx_get_rflags,
3611 .set_rflags = vmx_set_rflags,
3613 .tlb_flush = vmx_flush_tlb,
3615 .run = vmx_vcpu_run,
3616 .handle_exit = kvm_handle_exit,
3617 .skip_emulated_instruction = skip_emulated_instruction,
3618 .patch_hypercall = vmx_patch_hypercall,
3619 .get_irq = vmx_get_irq,
3620 .set_irq = vmx_inject_irq,
3621 .queue_exception = vmx_queue_exception,
3622 .exception_injected = vmx_exception_injected,
3623 .inject_pending_irq = vmx_intr_assist,
3624 .inject_pending_vectors = do_interrupt_requests,
3626 .set_tss_addr = vmx_set_tss_addr,
3627 .get_tdp_level = get_ept_level,
3628 .get_mt_mask_shift = vmx_get_mt_mask_shift,
3631 static int __init vmx_init(void)
3636 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3637 if (!vmx_io_bitmap_a)
3640 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3641 if (!vmx_io_bitmap_b) {
3646 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3647 if (!vmx_msr_bitmap) {
3653 * Allow direct access to the PC debug port (it is often used for I/O
3654 * delays, but the vmexits simply slow things down).
3656 va = kmap(vmx_io_bitmap_a);
3657 memset(va, 0xff, PAGE_SIZE);
3658 clear_bit(0x80, va);
3659 kunmap(vmx_io_bitmap_a);
3661 va = kmap(vmx_io_bitmap_b);
3662 memset(va, 0xff, PAGE_SIZE);
3663 kunmap(vmx_io_bitmap_b);
3665 va = kmap(vmx_msr_bitmap);
3666 memset(va, 0xff, PAGE_SIZE);
3667 kunmap(vmx_msr_bitmap);
3669 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3671 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3675 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3676 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3677 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3678 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3679 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3681 if (vm_need_ept()) {
3682 bypass_guest_pf = 0;
3683 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3684 VMX_EPT_WRITABLE_MASK);
3685 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3686 VMX_EPT_EXECUTABLE_MASK,
3687 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3692 if (bypass_guest_pf)
3693 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3700 __free_page(vmx_msr_bitmap);
3702 __free_page(vmx_io_bitmap_b);
3704 __free_page(vmx_io_bitmap_a);
3708 static void __exit vmx_exit(void)
3710 __free_page(vmx_msr_bitmap);
3711 __free_page(vmx_io_bitmap_b);
3712 __free_page(vmx_io_bitmap_a);
3717 module_init(vmx_init)
3718 module_exit(vmx_exit)