arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 137  * ple_gap:    upper bound on the amount of time between two successive
 138  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 139  *             According to test, this time is usually smaller than 128 cycles.
 140  * ple_window: upper bound on the amount of time a guest is allowed to execute
 141  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 142  *             less than 2^12 cycles
 143  * Time is measured based on a counter that runs at the same rate as the TSC,
 144  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 145  */
 146 #define KVM_VMX_DEFAULT_PLE_GAP           128
 147 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 148 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 149 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 150 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 151                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 152
 153 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 154 module_param(ple_gap, int, S_IRUGO);
 155
 156 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 157 module_param(ple_window, int, S_IRUGO);
 158
 159 /* Default doubles per-vcpu window every exit. */
 160 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 161 module_param(ple_window_grow, int, S_IRUGO);
 162
 163 /* Default resets per-vcpu window every exit to ple_window. */
 164 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 165 module_param(ple_window_shrink, int, S_IRUGO);
 166
 167 /* Default is to compute the maximum so we can never overflow. */
 168 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 169 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 170 module_param(ple_window_max, int, S_IRUGO);
 171
 172 extern const ulong vmx_return;
 173
 174 #define NR_AUTOLOAD_MSRS 8
 175 #define VMCS02_POOL_SIZE 1
 176
 177 struct vmcs {
 178         u32 revision_id;
 179         u32 abort;
 180         char data[0];
 181 };
 182
 183 /*
 184  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 185  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 186  * loaded on this CPU (so we can clear them if the CPU goes down).
 187  */
 188 struct loaded_vmcs {
 189         struct vmcs *vmcs;
 190         int cpu;
 191         int launched;
 192         struct list_head loaded_vmcss_on_cpu_link;
 193 };
 194
 195 struct shared_msr_entry {
 196         unsigned index;
 197         u64 data;
 198         u64 mask;
 199 };
 200
 201 /*
 202  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 203  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 204  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 205  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 206  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 207  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 208  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 209  * underlying hardware which will be used to run L2.
 210  * This structure is packed to ensure that its layout is identical across
 211  * machines (necessary for live migration).
 212  * If there are changes in this struct, VMCS12_REVISION must be changed.
 213  */
 214 typedef u64 natural_width;
 215 struct __packed vmcs12 {
 216         /* According to the Intel spec, a VMCS region must start with the
 217          * following two fields. Then follow implementation-specific data.
 218          */
 219         u32 revision_id;
 220         u32 abort;
 221
 222         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 223         u32 padding[7]; /* room for future expansion */
 224
 225         u64 io_bitmap_a;
 226         u64 io_bitmap_b;
 227         u64 msr_bitmap;
 228         u64 vm_exit_msr_store_addr;
 229         u64 vm_exit_msr_load_addr;
 230         u64 vm_entry_msr_load_addr;
 231         u64 tsc_offset;
 232         u64 virtual_apic_page_addr;
 233         u64 apic_access_addr;
 234         u64 posted_intr_desc_addr;
 235         u64 ept_pointer;
 236         u64 eoi_exit_bitmap0;
 237         u64 eoi_exit_bitmap1;
 238         u64 eoi_exit_bitmap2;
 239         u64 eoi_exit_bitmap3;
 240         u64 xss_exit_bitmap;
 241         u64 guest_physical_address;
 242         u64 vmcs_link_pointer;
 243         u64 guest_ia32_debugctl;
 244         u64 guest_ia32_pat;
 245         u64 guest_ia32_efer;
 246         u64 guest_ia32_perf_global_ctrl;
 247         u64 guest_pdptr0;
 248         u64 guest_pdptr1;
 249         u64 guest_pdptr2;
 250         u64 guest_pdptr3;
 251         u64 guest_bndcfgs;
 252         u64 host_ia32_pat;
 253         u64 host_ia32_efer;
 254         u64 host_ia32_perf_global_ctrl;
 255         u64 padding64[8]; /* room for future expansion */
 256         /*
 257          * To allow migration of L1 (complete with its L2 guests) between
 258          * machines of different natural widths (32 or 64 bit), we cannot have
 259          * unsigned long fields with no explict size. We use u64 (aliased
 260          * natural_width) instead. Luckily, x86 is little-endian.
 261          */
 262         natural_width cr0_guest_host_mask;
 263         natural_width cr4_guest_host_mask;
 264         natural_width cr0_read_shadow;
 265         natural_width cr4_read_shadow;
 266         natural_width cr3_target_value0;
 267         natural_width cr3_target_value1;
 268         natural_width cr3_target_value2;
 269         natural_width cr3_target_value3;
 270         natural_width exit_qualification;
 271         natural_width guest_linear_address;
 272         natural_width guest_cr0;
 273         natural_width guest_cr3;
 274         natural_width guest_cr4;
 275         natural_width guest_es_base;
 276         natural_width guest_cs_base;
 277         natural_width guest_ss_base;
 278         natural_width guest_ds_base;
 279         natural_width guest_fs_base;
 280         natural_width guest_gs_base;
 281         natural_width guest_ldtr_base;
 282         natural_width guest_tr_base;
 283         natural_width guest_gdtr_base;
 284         natural_width guest_idtr_base;
 285         natural_width guest_dr7;
 286         natural_width guest_rsp;
 287         natural_width guest_rip;
 288         natural_width guest_rflags;
 289         natural_width guest_pending_dbg_exceptions;
 290         natural_width guest_sysenter_esp;
 291         natural_width guest_sysenter_eip;
 292         natural_width host_cr0;
 293         natural_width host_cr3;
 294         natural_width host_cr4;
 295         natural_width host_fs_base;
 296         natural_width host_gs_base;
 297         natural_width host_tr_base;
 298         natural_width host_gdtr_base;
 299         natural_width host_idtr_base;
 300         natural_width host_ia32_sysenter_esp;
 301         natural_width host_ia32_sysenter_eip;
 302         natural_width host_rsp;
 303         natural_width host_rip;
 304         natural_width paddingl[8]; /* room for future expansion */
 305         u32 pin_based_vm_exec_control;
 306         u32 cpu_based_vm_exec_control;
 307         u32 exception_bitmap;
 308         u32 page_fault_error_code_mask;
 309         u32 page_fault_error_code_match;
 310         u32 cr3_target_count;
 311         u32 vm_exit_controls;
 312         u32 vm_exit_msr_store_count;
 313         u32 vm_exit_msr_load_count;
 314         u32 vm_entry_controls;
 315         u32 vm_entry_msr_load_count;
 316         u32 vm_entry_intr_info_field;
 317         u32 vm_entry_exception_error_code;
 318         u32 vm_entry_instruction_len;
 319         u32 tpr_threshold;
 320         u32 secondary_vm_exec_control;
 321         u32 vm_instruction_error;
 322         u32 vm_exit_reason;
 323         u32 vm_exit_intr_info;
 324         u32 vm_exit_intr_error_code;
 325         u32 idt_vectoring_info_field;
 326         u32 idt_vectoring_error_code;
 327         u32 vm_exit_instruction_len;
 328         u32 vmx_instruction_info;
 329         u32 guest_es_limit;
 330         u32 guest_cs_limit;
 331         u32 guest_ss_limit;
 332         u32 guest_ds_limit;
 333         u32 guest_fs_limit;
 334         u32 guest_gs_limit;
 335         u32 guest_ldtr_limit;
 336         u32 guest_tr_limit;
 337         u32 guest_gdtr_limit;
 338         u32 guest_idtr_limit;
 339         u32 guest_es_ar_bytes;
 340         u32 guest_cs_ar_bytes;
 341         u32 guest_ss_ar_bytes;
 342         u32 guest_ds_ar_bytes;
 343         u32 guest_fs_ar_bytes;
 344         u32 guest_gs_ar_bytes;
 345         u32 guest_ldtr_ar_bytes;
 346         u32 guest_tr_ar_bytes;
 347         u32 guest_interruptibility_info;
 348         u32 guest_activity_state;
 349         u32 guest_sysenter_cs;
 350         u32 host_ia32_sysenter_cs;
 351         u32 vmx_preemption_timer_value;
 352         u32 padding32[7]; /* room for future expansion */
 353         u16 virtual_processor_id;
 354         u16 posted_intr_nv;
 355         u16 guest_es_selector;
 356         u16 guest_cs_selector;
 357         u16 guest_ss_selector;
 358         u16 guest_ds_selector;
 359         u16 guest_fs_selector;
 360         u16 guest_gs_selector;
 361         u16 guest_ldtr_selector;
 362         u16 guest_tr_selector;
 363         u16 guest_intr_status;
 364         u16 host_es_selector;
 365         u16 host_cs_selector;
 366         u16 host_ss_selector;
 367         u16 host_ds_selector;
 368         u16 host_fs_selector;
 369         u16 host_gs_selector;
 370         u16 host_tr_selector;
 371 };
 372
 373 /*
 374  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 375  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 376  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 377  */
 378 #define VMCS12_REVISION 0x11e57ed0
 379
 380 /*
 381  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 382  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 383  * current implementation, 4K are reserved to avoid future complications.
 384  */
 385 #define VMCS12_SIZE 0x1000
 386
 387 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 388 struct vmcs02_list {
 389         struct list_head list;
 390         gpa_t vmptr;
 391         struct loaded_vmcs vmcs02;
 392 };
 393
 394 /*
 395  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 396  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 397  */
 398 struct nested_vmx {
 399         /* Has the level1 guest done vmxon? */
 400         bool vmxon;
 401         gpa_t vmxon_ptr;
 402
 403         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 404         gpa_t current_vmptr;
 405         /* The host-usable pointer to the above */
 406         struct page *current_vmcs12_page;
 407         struct vmcs12 *current_vmcs12;
 408         /*
 409          * Cache of the guest's VMCS, existing outside of guest memory.
 410          * Loaded from guest memory during VMPTRLD. Flushed to guest
 411          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 412          */
 413         struct vmcs12 *cached_vmcs12;
 414         struct vmcs *current_shadow_vmcs;
 415         /*
 416          * Indicates if the shadow vmcs must be updated with the
 417          * data hold by vmcs12
 418          */
 419         bool sync_shadow_vmcs;
 420
 421         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 422         struct list_head vmcs02_pool;
 423         int vmcs02_num;
 424         u64 vmcs01_tsc_offset;
 425         /* L2 must run next, and mustn't decide to exit to L1. */
 426         bool nested_run_pending;
 427         /*
 428          * Guest pages referred to in vmcs02 with host-physical pointers, so
 429          * we must keep them pinned while L2 runs.
 430          */
 431         struct page *apic_access_page;
 432         struct page *virtual_apic_page;
 433         struct page *pi_desc_page;
 434         struct pi_desc *pi_desc;
 435         bool pi_pending;
 436         u16 posted_intr_nv;
 437
 438         unsigned long *msr_bitmap;
 439
 440         struct hrtimer preemption_timer;
 441         bool preemption_timer_expired;
 442
 443         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 444         u64 vmcs01_debugctl;
 445
 446         u16 vpid02;
 447         u16 last_vpid;
 448
 449         u32 nested_vmx_procbased_ctls_low;
 450         u32 nested_vmx_procbased_ctls_high;
 451         u32 nested_vmx_true_procbased_ctls_low;
 452         u32 nested_vmx_secondary_ctls_low;
 453         u32 nested_vmx_secondary_ctls_high;
 454         u32 nested_vmx_pinbased_ctls_low;
 455         u32 nested_vmx_pinbased_ctls_high;
 456         u32 nested_vmx_exit_ctls_low;
 457         u32 nested_vmx_exit_ctls_high;
 458         u32 nested_vmx_true_exit_ctls_low;
 459         u32 nested_vmx_entry_ctls_low;
 460         u32 nested_vmx_entry_ctls_high;
 461         u32 nested_vmx_true_entry_ctls_low;
 462         u32 nested_vmx_misc_low;
 463         u32 nested_vmx_misc_high;
 464         u32 nested_vmx_ept_caps;
 465         u32 nested_vmx_vpid_caps;
 466 };
 467
 468 #define POSTED_INTR_ON  0
 469 #define POSTED_INTR_SN  1
 470
 471 /* Posted-Interrupt Descriptor */
 472 struct pi_desc {
 473         u32 pir[8];     /* Posted interrupt requested */
 474         union {
 475                 struct {
 476                                 /* bit 256 - Outstanding Notification */
 477                         u16     on      : 1,
 478                                 /* bit 257 - Suppress Notification */
 479                                 sn      : 1,
 480                                 /* bit 271:258 - Reserved */
 481                                 rsvd_1  : 14;
 482                                 /* bit 279:272 - Notification Vector */
 483                         u8      nv;
 484                                 /* bit 287:280 - Reserved */
 485                         u8      rsvd_2;
 486                                 /* bit 319:288 - Notification Destination */
 487                         u32     ndst;
 488                 };
 489                 u64 control;
 490         };
 491         u32 rsvd[6];
 492 } __aligned(64);
 493
 494 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 495 {
 496         return test_and_set_bit(POSTED_INTR_ON,
 497                         (unsigned long *)&pi_desc->control);
 498 }
 499
 500 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 501 {
 502         return test_and_clear_bit(POSTED_INTR_ON,
 503                         (unsigned long *)&pi_desc->control);
 504 }
 505
 506 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 507 {
 508         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 509 }
 510
 511 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 512 {
 513         return clear_bit(POSTED_INTR_SN,
 514                         (unsigned long *)&pi_desc->control);
 515 }
 516
 517 static inline void pi_set_sn(struct pi_desc *pi_desc)
 518 {
 519         return set_bit(POSTED_INTR_SN,
 520                         (unsigned long *)&pi_desc->control);
 521 }
 522
 523 static inline int pi_test_on(struct pi_desc *pi_desc)
 524 {
 525         return test_bit(POSTED_INTR_ON,
 526                         (unsigned long *)&pi_desc->control);
 527 }
 528
 529 static inline int pi_test_sn(struct pi_desc *pi_desc)
 530 {
 531         return test_bit(POSTED_INTR_SN,
 532                         (unsigned long *)&pi_desc->control);
 533 }
 534
 535 struct vcpu_vmx {
 536         struct kvm_vcpu       vcpu;
 537         unsigned long         host_rsp;
 538         u8                    fail;
 539         bool                  nmi_known_unmasked;
 540         u32                   exit_intr_info;
 541         u32                   idt_vectoring_info;
 542         ulong                 rflags;
 543         struct shared_msr_entry *guest_msrs;
 544         int                   nmsrs;
 545         int                   save_nmsrs;
 546         unsigned long         host_idt_base;
 547 #ifdef CONFIG_X86_64
 548         u64                   msr_host_kernel_gs_base;
 549         u64                   msr_guest_kernel_gs_base;
 550 #endif
 551         u32 vm_entry_controls_shadow;
 552         u32 vm_exit_controls_shadow;
 553         /*
 554          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 555          * non-nested (L1) guest, it always points to vmcs01. For a nested
 556          * guest (L2), it points to a different VMCS.
 557          */
 558         struct loaded_vmcs    vmcs01;
 559         struct loaded_vmcs   *loaded_vmcs;
 560         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 561         struct msr_autoload {
 562                 unsigned nr;
 563                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 564                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 565         } msr_autoload;
 566         struct {
 567                 int           loaded;
 568                 u16           fs_sel, gs_sel, ldt_sel;
 569 #ifdef CONFIG_X86_64
 570                 u16           ds_sel, es_sel;
 571 #endif
 572                 int           gs_ldt_reload_needed;
 573                 int           fs_reload_needed;
 574                 u64           msr_host_bndcfgs;
 575                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 576         } host_state;
 577         struct {
 578                 int vm86_active;
 579                 ulong save_rflags;
 580                 struct kvm_segment segs[8];
 581         } rmode;
 582         struct {
 583                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 584                 struct kvm_save_segment {
 585                         u16 selector;
 586                         unsigned long base;
 587                         u32 limit;
 588                         u32 ar;
 589                 } seg[8];
 590         } segment_cache;
 591         int vpid;
 592         bool emulation_required;
 593
 594         /* Support for vnmi-less CPUs */
 595         int soft_vnmi_blocked;
 596         ktime_t entry_time;
 597         s64 vnmi_blocked_time;
 598         u32 exit_reason;
 599
 600         /* Posted interrupt descriptor */
 601         struct pi_desc pi_desc;
 602
 603         /* Support for a guest hypervisor (nested VMX) */
 604         struct nested_vmx nested;
 605
 606         /* Dynamic PLE window. */
 607         int ple_window;
 608         bool ple_window_dirty;
 609
 610         /* Support for PML */
 611 #define PML_ENTITY_NUM          512
 612         struct page *pml_pg;
 613
 614         /* apic deadline value in host tsc */
 615         u64 hv_deadline_tsc;
 616
 617         u64 current_tsc_ratio;
 618
 619         bool guest_pkru_valid;
 620         u32 guest_pkru;
 621         u32 host_pkru;
 622
 623         /*
 624          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 625          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 626          * in msr_ia32_feature_control_valid_bits.
 627          */
 628         u64 msr_ia32_feature_control;
 629         u64 msr_ia32_feature_control_valid_bits;
 630 };
 631
 632 enum segment_cache_field {
 633         SEG_FIELD_SEL = 0,
 634         SEG_FIELD_BASE = 1,
 635         SEG_FIELD_LIMIT = 2,
 636         SEG_FIELD_AR = 3,
 637
 638         SEG_FIELD_NR = 4
 639 };
 640
 641 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 642 {
 643         return container_of(vcpu, struct vcpu_vmx, vcpu);
 644 }
 645
 646 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 647 {
 648         return &(to_vmx(vcpu)->pi_desc);
 649 }
 650
 651 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 652 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 653 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 654                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 655
 656
 657 static unsigned long shadow_read_only_fields[] = {
 658         /*
 659          * We do NOT shadow fields that are modified when L0
 660          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 661          * VMXON...) executed by L1.
 662          * For example, VM_INSTRUCTION_ERROR is read
 663          * by L1 if a vmx instruction fails (part of the error path).
 664          * Note the code assumes this logic. If for some reason
 665          * we start shadowing these fields then we need to
 666          * force a shadow sync when L0 emulates vmx instructions
 667          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 668          * by nested_vmx_failValid)
 669          */
 670         VM_EXIT_REASON,
 671         VM_EXIT_INTR_INFO,
 672         VM_EXIT_INSTRUCTION_LEN,
 673         IDT_VECTORING_INFO_FIELD,
 674         IDT_VECTORING_ERROR_CODE,
 675         VM_EXIT_INTR_ERROR_CODE,
 676         EXIT_QUALIFICATION,
 677         GUEST_LINEAR_ADDRESS,
 678         GUEST_PHYSICAL_ADDRESS
 679 };
 680 static int max_shadow_read_only_fields =
 681         ARRAY_SIZE(shadow_read_only_fields);
 682
 683 static unsigned long shadow_read_write_fields[] = {
 684         TPR_THRESHOLD,
 685         GUEST_RIP,
 686         GUEST_RSP,
 687         GUEST_CR0,
 688         GUEST_CR3,
 689         GUEST_CR4,
 690         GUEST_INTERRUPTIBILITY_INFO,
 691         GUEST_RFLAGS,
 692         GUEST_CS_SELECTOR,
 693         GUEST_CS_AR_BYTES,
 694         GUEST_CS_LIMIT,
 695         GUEST_CS_BASE,
 696         GUEST_ES_BASE,
 697         GUEST_BNDCFGS,
 698         CR0_GUEST_HOST_MASK,
 699         CR0_READ_SHADOW,
 700         CR4_READ_SHADOW,
 701         TSC_OFFSET,
 702         EXCEPTION_BITMAP,
 703         CPU_BASED_VM_EXEC_CONTROL,
 704         VM_ENTRY_EXCEPTION_ERROR_CODE,
 705         VM_ENTRY_INTR_INFO_FIELD,
 706         VM_ENTRY_INSTRUCTION_LEN,
 707         VM_ENTRY_EXCEPTION_ERROR_CODE,
 708         HOST_FS_BASE,
 709         HOST_GS_BASE,
 710         HOST_FS_SELECTOR,
 711         HOST_GS_SELECTOR
 712 };
 713 static int max_shadow_read_write_fields =
 714         ARRAY_SIZE(shadow_read_write_fields);
 715
 716 static const unsigned short vmcs_field_to_offset_table[] = {
 717         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 718         FIELD(POSTED_INTR_NV, posted_intr_nv),
 719         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 720         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 721         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 722         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 723         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 724         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 725         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 726         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 727         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 728         FIELD(HOST_ES_SELECTOR, host_es_selector),
 729         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 730         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 731         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 732         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 733         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 734         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 735         FIELD64(IO_BITMAP_A, io_bitmap_a),
 736         FIELD64(IO_BITMAP_B, io_bitmap_b),
 737         FIELD64(MSR_BITMAP, msr_bitmap),
 738         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 739         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 740         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 741         FIELD64(TSC_OFFSET, tsc_offset),
 742         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 743         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 744         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 745         FIELD64(EPT_POINTER, ept_pointer),
 746         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 747         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 748         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 749         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 750         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 751         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 752         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 753         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 754         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 755         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 756         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 757         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 758         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 759         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 760         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 761         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 762         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 763         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 764         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 765         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 766         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 767         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 768         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 769         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 770         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 771         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 772         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 773         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 774         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 775         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 776         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 777         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 778         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 779         FIELD(TPR_THRESHOLD, tpr_threshold),
 780         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 781         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 782         FIELD(VM_EXIT_REASON, vm_exit_reason),
 783         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 784         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 785         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 786         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 787         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 788         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 789         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 790         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 791         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 792         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 793         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 794         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 795         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 796         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 797         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 798         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 799         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 800         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 801         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 802         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 803         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 804         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 805         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 806         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 807         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 808         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 809         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 810         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 811         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 812         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 813         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 814         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 815         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 816         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 817         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 818         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 819         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 820         FIELD(EXIT_QUALIFICATION, exit_qualification),
 821         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 822         FIELD(GUEST_CR0, guest_cr0),
 823         FIELD(GUEST_CR3, guest_cr3),
 824         FIELD(GUEST_CR4, guest_cr4),
 825         FIELD(GUEST_ES_BASE, guest_es_base),
 826         FIELD(GUEST_CS_BASE, guest_cs_base),
 827         FIELD(GUEST_SS_BASE, guest_ss_base),
 828         FIELD(GUEST_DS_BASE, guest_ds_base),
 829         FIELD(GUEST_FS_BASE, guest_fs_base),
 830         FIELD(GUEST_GS_BASE, guest_gs_base),
 831         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 832         FIELD(GUEST_TR_BASE, guest_tr_base),
 833         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 834         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 835         FIELD(GUEST_DR7, guest_dr7),
 836         FIELD(GUEST_RSP, guest_rsp),
 837         FIELD(GUEST_RIP, guest_rip),
 838         FIELD(GUEST_RFLAGS, guest_rflags),
 839         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 840         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 841         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 842         FIELD(HOST_CR0, host_cr0),
 843         FIELD(HOST_CR3, host_cr3),
 844         FIELD(HOST_CR4, host_cr4),
 845         FIELD(HOST_FS_BASE, host_fs_base),
 846         FIELD(HOST_GS_BASE, host_gs_base),
 847         FIELD(HOST_TR_BASE, host_tr_base),
 848         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 849         FIELD(HOST_IDTR_BASE, host_idtr_base),
 850         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 851         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 852         FIELD(HOST_RSP, host_rsp),
 853         FIELD(HOST_RIP, host_rip),
 854 };
 855
 856 static inline short vmcs_field_to_offset(unsigned long field)
 857 {
 858         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 859
 860         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 861             vmcs_field_to_offset_table[field] == 0)
 862                 return -ENOENT;
 863
 864         return vmcs_field_to_offset_table[field];
 865 }
 866
 867 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 868 {
 869         return to_vmx(vcpu)->nested.cached_vmcs12;
 870 }
 871
 872 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 873 {
 874         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 875         if (is_error_page(page))
 876                 return NULL;
 877
 878         return page;
 879 }
 880
 881 static void nested_release_page(struct page *page)
 882 {
 883         kvm_release_page_dirty(page);
 884 }
 885
 886 static void nested_release_page_clean(struct page *page)
 887 {
 888         kvm_release_page_clean(page);
 889 }
 890
 891 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 892 static u64 construct_eptp(unsigned long root_hpa);
 893 static void kvm_cpu_vmxon(u64 addr);
 894 static void kvm_cpu_vmxoff(void);
 895 static bool vmx_xsaves_supported(void);
 896 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 897 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 898                             struct kvm_segment *var, int seg);
 899 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 900                             struct kvm_segment *var, int seg);
 901 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 902 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 903 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 904 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 905 static int alloc_identity_pagetable(struct kvm *kvm);
 906
 907 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 908 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 909 /*
 910  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 911  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 912  */
 913 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 914 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 915
 916 /*
 917  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 918  * can find which vCPU should be waken up.
 919  */
 920 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 921 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 922
 923 static unsigned long *vmx_io_bitmap_a;
 924 static unsigned long *vmx_io_bitmap_b;
 925 static unsigned long *vmx_msr_bitmap_legacy;
 926 static unsigned long *vmx_msr_bitmap_longmode;
 927 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 928 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 929 static unsigned long *vmx_vmread_bitmap;
 930 static unsigned long *vmx_vmwrite_bitmap;
 931
 932 static bool cpu_has_load_ia32_efer;
 933 static bool cpu_has_load_perf_global_ctrl;
 934
 935 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 936 static DEFINE_SPINLOCK(vmx_vpid_lock);
 937
 938 static struct vmcs_config {
 939         int size;
 940         int order;
 941         u32 revision_id;
 942         u32 pin_based_exec_ctrl;
 943         u32 cpu_based_exec_ctrl;
 944         u32 cpu_based_2nd_exec_ctrl;
 945         u32 vmexit_ctrl;
 946         u32 vmentry_ctrl;
 947 } vmcs_config;
 948
 949 static struct vmx_capability {
 950         u32 ept;
 951         u32 vpid;
 952 } vmx_capability;
 953
 954 #define VMX_SEGMENT_FIELD(seg)                                  \
 955         [VCPU_SREG_##seg] = {                                   \
 956                 .selector = GUEST_##seg##_SELECTOR,             \
 957                 .base = GUEST_##seg##_BASE,                     \
 958                 .limit = GUEST_##seg##_LIMIT,                   \
 959                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 960         }
 961
 962 static const struct kvm_vmx_segment_field {
 963         unsigned selector;
 964         unsigned base;
 965         unsigned limit;
 966         unsigned ar_bytes;
 967 } kvm_vmx_segment_fields[] = {
 968         VMX_SEGMENT_FIELD(CS),
 969         VMX_SEGMENT_FIELD(DS),
 970         VMX_SEGMENT_FIELD(ES),
 971         VMX_SEGMENT_FIELD(FS),
 972         VMX_SEGMENT_FIELD(GS),
 973         VMX_SEGMENT_FIELD(SS),
 974         VMX_SEGMENT_FIELD(TR),
 975         VMX_SEGMENT_FIELD(LDTR),
 976 };
 977
 978 static u64 host_efer;
 979
 980 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 981
 982 /*
 983  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 984  * away by decrementing the array size.
 985  */
 986 static const u32 vmx_msr_index[] = {
 987 #ifdef CONFIG_X86_64
 988         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 989 #endif
 990         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 991 };
 992
 993 static inline bool is_exception_n(u32 intr_info, u8 vector)
 994 {
 995         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 996                              INTR_INFO_VALID_MASK)) ==
 997                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
 998 }
 999
1000 static inline bool is_debug(u32 intr_info)
1001 {
1002         return is_exception_n(intr_info, DB_VECTOR);
1003 }
1004
1005 static inline bool is_breakpoint(u32 intr_info)
1006 {
1007         return is_exception_n(intr_info, BP_VECTOR);
1008 }
1009
1010 static inline bool is_page_fault(u32 intr_info)
1011 {
1012         return is_exception_n(intr_info, PF_VECTOR);
1013 }
1014
1015 static inline bool is_no_device(u32 intr_info)
1016 {
1017         return is_exception_n(intr_info, NM_VECTOR);
1018 }
1019
1020 static inline bool is_invalid_opcode(u32 intr_info)
1021 {
1022         return is_exception_n(intr_info, UD_VECTOR);
1023 }
1024
1025 static inline bool is_external_interrupt(u32 intr_info)
1026 {
1027         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1028                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1029 }
1030
1031 static inline bool is_machine_check(u32 intr_info)
1032 {
1033         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1034                              INTR_INFO_VALID_MASK)) ==
1035                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1036 }
1037
1038 static inline bool cpu_has_vmx_msr_bitmap(void)
1039 {
1040         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1041 }
1042
1043 static inline bool cpu_has_vmx_tpr_shadow(void)
1044 {
1045         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1046 }
1047
1048 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1049 {
1050         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1051 }
1052
1053 static inline bool cpu_has_secondary_exec_ctrls(void)
1054 {
1055         return vmcs_config.cpu_based_exec_ctrl &
1056                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1057 }
1058
1059 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1060 {
1061         return vmcs_config.cpu_based_2nd_exec_ctrl &
1062                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1063 }
1064
1065 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1066 {
1067         return vmcs_config.cpu_based_2nd_exec_ctrl &
1068                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1069 }
1070
1071 static inline bool cpu_has_vmx_apic_register_virt(void)
1072 {
1073         return vmcs_config.cpu_based_2nd_exec_ctrl &
1074                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1075 }
1076
1077 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1078 {
1079         return vmcs_config.cpu_based_2nd_exec_ctrl &
1080                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1081 }
1082
1083 /*
1084  * Comment's format: document - errata name - stepping - processor name.
1085  * Refer from
1086  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1087  */
1088 static u32 vmx_preemption_cpu_tfms[] = {
1089 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1090 0x000206E6,
1091 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1092 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1093 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1094 0x00020652,
1095 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1096 0x00020655,
1097 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1098 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1099 /*
1100  * 320767.pdf - AAP86  - B1 -
1101  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1102  */
1103 0x000106E5,
1104 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1105 0x000106A0,
1106 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1107 0x000106A1,
1108 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1109 0x000106A4,
1110  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1111  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1112  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1113 0x000106A5,
1114 };
1115
1116 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1117 {
1118         u32 eax = cpuid_eax(0x00000001), i;
1119
1120         /* Clear the reserved bits */
1121         eax &= ~(0x3U << 14 | 0xfU << 28);
1122         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1123                 if (eax == vmx_preemption_cpu_tfms[i])
1124                         return true;
1125
1126         return false;
1127 }
1128
1129 static inline bool cpu_has_vmx_preemption_timer(void)
1130 {
1131         return vmcs_config.pin_based_exec_ctrl &
1132                 PIN_BASED_VMX_PREEMPTION_TIMER;
1133 }
1134
1135 static inline bool cpu_has_vmx_posted_intr(void)
1136 {
1137         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1138                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1139 }
1140
1141 static inline bool cpu_has_vmx_apicv(void)
1142 {
1143         return cpu_has_vmx_apic_register_virt() &&
1144                 cpu_has_vmx_virtual_intr_delivery() &&
1145                 cpu_has_vmx_posted_intr();
1146 }
1147
1148 static inline bool cpu_has_vmx_flexpriority(void)
1149 {
1150         return cpu_has_vmx_tpr_shadow() &&
1151                 cpu_has_vmx_virtualize_apic_accesses();
1152 }
1153
1154 static inline bool cpu_has_vmx_ept_execute_only(void)
1155 {
1156         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1157 }
1158
1159 static inline bool cpu_has_vmx_ept_2m_page(void)
1160 {
1161         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1162 }
1163
1164 static inline bool cpu_has_vmx_ept_1g_page(void)
1165 {
1166         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1167 }
1168
1169 static inline bool cpu_has_vmx_ept_4levels(void)
1170 {
1171         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1172 }
1173
1174 static inline bool cpu_has_vmx_ept_ad_bits(void)
1175 {
1176         return vmx_capability.ept & VMX_EPT_AD_BIT;
1177 }
1178
1179 static inline bool cpu_has_vmx_invept_context(void)
1180 {
1181         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1182 }
1183
1184 static inline bool cpu_has_vmx_invept_global(void)
1185 {
1186         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1187 }
1188
1189 static inline bool cpu_has_vmx_invvpid_single(void)
1190 {
1191         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1192 }
1193
1194 static inline bool cpu_has_vmx_invvpid_global(void)
1195 {
1196         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1197 }
1198
1199 static inline bool cpu_has_vmx_ept(void)
1200 {
1201         return vmcs_config.cpu_based_2nd_exec_ctrl &
1202                 SECONDARY_EXEC_ENABLE_EPT;
1203 }
1204
1205 static inline bool cpu_has_vmx_unrestricted_guest(void)
1206 {
1207         return vmcs_config.cpu_based_2nd_exec_ctrl &
1208                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1209 }
1210
1211 static inline bool cpu_has_vmx_ple(void)
1212 {
1213         return vmcs_config.cpu_based_2nd_exec_ctrl &
1214                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1215 }
1216
1217 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1218 {
1219         return flexpriority_enabled && lapic_in_kernel(vcpu);
1220 }
1221
1222 static inline bool cpu_has_vmx_vpid(void)
1223 {
1224         return vmcs_config.cpu_based_2nd_exec_ctrl &
1225                 SECONDARY_EXEC_ENABLE_VPID;
1226 }
1227
1228 static inline bool cpu_has_vmx_rdtscp(void)
1229 {
1230         return vmcs_config.cpu_based_2nd_exec_ctrl &
1231                 SECONDARY_EXEC_RDTSCP;
1232 }
1233
1234 static inline bool cpu_has_vmx_invpcid(void)
1235 {
1236         return vmcs_config.cpu_based_2nd_exec_ctrl &
1237                 SECONDARY_EXEC_ENABLE_INVPCID;
1238 }
1239
1240 static inline bool cpu_has_virtual_nmis(void)
1241 {
1242         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1243 }
1244
1245 static inline bool cpu_has_vmx_wbinvd_exit(void)
1246 {
1247         return vmcs_config.cpu_based_2nd_exec_ctrl &
1248                 SECONDARY_EXEC_WBINVD_EXITING;
1249 }
1250
1251 static inline bool cpu_has_vmx_shadow_vmcs(void)
1252 {
1253         u64 vmx_msr;
1254         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1255         /* check if the cpu supports writing r/o exit information fields */
1256         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1257                 return false;
1258
1259         return vmcs_config.cpu_based_2nd_exec_ctrl &
1260                 SECONDARY_EXEC_SHADOW_VMCS;
1261 }
1262
1263 static inline bool cpu_has_vmx_pml(void)
1264 {
1265         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1266 }
1267
1268 static inline bool cpu_has_vmx_tsc_scaling(void)
1269 {
1270         return vmcs_config.cpu_based_2nd_exec_ctrl &
1271                 SECONDARY_EXEC_TSC_SCALING;
1272 }
1273
1274 static inline bool report_flexpriority(void)
1275 {
1276         return flexpriority_enabled;
1277 }
1278
1279 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1280 {
1281         return vmcs12->cpu_based_vm_exec_control & bit;
1282 }
1283
1284 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1285 {
1286         return (vmcs12->cpu_based_vm_exec_control &
1287                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1288                 (vmcs12->secondary_vm_exec_control & bit);
1289 }
1290
1291 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1292 {
1293         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1294 }
1295
1296 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1297 {
1298         return vmcs12->pin_based_vm_exec_control &
1299                 PIN_BASED_VMX_PREEMPTION_TIMER;
1300 }
1301
1302 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1303 {
1304         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1305 }
1306
1307 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1308 {
1309         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1310                 vmx_xsaves_supported();
1311 }
1312
1313 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1314 {
1315         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1316 }
1317
1318 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1319 {
1320         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1321 }
1322
1323 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1324 {
1325         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1326 }
1327
1328 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1329 {
1330         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1331 }
1332
1333 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1334 {
1335         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1336 }
1337
1338 static inline bool is_exception(u32 intr_info)
1339 {
1340         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1341                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1342 }
1343
1344 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1345                               u32 exit_intr_info,
1346                               unsigned long exit_qualification);
1347 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1348                         struct vmcs12 *vmcs12,
1349                         u32 reason, unsigned long qualification);
1350
1351 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1352 {
1353         int i;
1354
1355         for (i = 0; i < vmx->nmsrs; ++i)
1356                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1357                         return i;
1358         return -1;
1359 }
1360
1361 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1362 {
1363     struct {
1364         u64 vpid : 16;
1365         u64 rsvd : 48;
1366         u64 gva;
1367     } operand = { vpid, 0, gva };
1368
1369     asm volatile (__ex(ASM_VMX_INVVPID)
1370                   /* CF==1 or ZF==1 --> rc = -1 */
1371                   "; ja 1f ; ud2 ; 1:"
1372                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1373 }
1374
1375 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1376 {
1377         struct {
1378                 u64 eptp, gpa;
1379         } operand = {eptp, gpa};
1380
1381         asm volatile (__ex(ASM_VMX_INVEPT)
1382                         /* CF==1 or ZF==1 --> rc = -1 */
1383                         "; ja 1f ; ud2 ; 1:\n"
1384                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1385 }
1386
1387 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1388 {
1389         int i;
1390
1391         i = __find_msr_index(vmx, msr);
1392         if (i >= 0)
1393                 return &vmx->guest_msrs[i];
1394         return NULL;
1395 }
1396
1397 static void vmcs_clear(struct vmcs *vmcs)
1398 {
1399         u64 phys_addr = __pa(vmcs);
1400         u8 error;
1401
1402         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1403                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1404                       : "cc", "memory");
1405         if (error)
1406                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1407                        vmcs, phys_addr);
1408 }
1409
1410 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1411 {
1412         vmcs_clear(loaded_vmcs->vmcs);
1413         loaded_vmcs->cpu = -1;
1414         loaded_vmcs->launched = 0;
1415 }
1416
1417 static void vmcs_load(struct vmcs *vmcs)
1418 {
1419         u64 phys_addr = __pa(vmcs);
1420         u8 error;
1421
1422         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1423                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1424                         : "cc", "memory");
1425         if (error)
1426                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1427                        vmcs, phys_addr);
1428 }
1429
1430 #ifdef CONFIG_KEXEC_CORE
1431 /*
1432  * This bitmap is used to indicate whether the vmclear
1433  * operation is enabled on all cpus. All disabled by
1434  * default.
1435  */
1436 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1437
1438 static inline void crash_enable_local_vmclear(int cpu)
1439 {
1440         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1441 }
1442
1443 static inline void crash_disable_local_vmclear(int cpu)
1444 {
1445         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1446 }
1447
1448 static inline int crash_local_vmclear_enabled(int cpu)
1449 {
1450         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1451 }
1452
1453 static void crash_vmclear_local_loaded_vmcss(void)
1454 {
1455         int cpu = raw_smp_processor_id();
1456         struct loaded_vmcs *v;
1457
1458         if (!crash_local_vmclear_enabled(cpu))
1459                 return;
1460
1461         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1462                             loaded_vmcss_on_cpu_link)
1463                 vmcs_clear(v->vmcs);
1464 }
1465 #else
1466 static inline void crash_enable_local_vmclear(int cpu) { }
1467 static inline void crash_disable_local_vmclear(int cpu) { }
1468 #endif /* CONFIG_KEXEC_CORE */
1469
1470 static void __loaded_vmcs_clear(void *arg)
1471 {
1472         struct loaded_vmcs *loaded_vmcs = arg;
1473         int cpu = raw_smp_processor_id();
1474
1475         if (loaded_vmcs->cpu != cpu)
1476                 return; /* vcpu migration can race with cpu offline */
1477         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1478                 per_cpu(current_vmcs, cpu) = NULL;
1479         crash_disable_local_vmclear(cpu);
1480         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1481
1482         /*
1483          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1484          * is before setting loaded_vmcs->vcpu to -1 which is done in
1485          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1486          * then adds the vmcs into percpu list before it is deleted.
1487          */
1488         smp_wmb();
1489
1490         loaded_vmcs_init(loaded_vmcs);
1491         crash_enable_local_vmclear(cpu);
1492 }
1493
1494 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1495 {
1496         int cpu = loaded_vmcs->cpu;
1497
1498         if (cpu != -1)
1499                 smp_call_function_single(cpu,
1500                          __loaded_vmcs_clear, loaded_vmcs, 1);
1501 }
1502
1503 static inline void vpid_sync_vcpu_single(int vpid)
1504 {
1505         if (vpid == 0)
1506                 return;
1507
1508         if (cpu_has_vmx_invvpid_single())
1509                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1510 }
1511
1512 static inline void vpid_sync_vcpu_global(void)
1513 {
1514         if (cpu_has_vmx_invvpid_global())
1515                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1516 }
1517
1518 static inline void vpid_sync_context(int vpid)
1519 {
1520         if (cpu_has_vmx_invvpid_single())
1521                 vpid_sync_vcpu_single(vpid);
1522         else
1523                 vpid_sync_vcpu_global();
1524 }
1525
1526 static inline void ept_sync_global(void)
1527 {
1528         if (cpu_has_vmx_invept_global())
1529                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1530 }
1531
1532 static inline void ept_sync_context(u64 eptp)
1533 {
1534         if (enable_ept) {
1535                 if (cpu_has_vmx_invept_context())
1536                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1537                 else
1538                         ept_sync_global();
1539         }
1540 }
1541
1542 static __always_inline void vmcs_check16(unsigned long field)
1543 {
1544         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1545                          "16-bit accessor invalid for 64-bit field");
1546         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1547                          "16-bit accessor invalid for 64-bit high field");
1548         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1549                          "16-bit accessor invalid for 32-bit high field");
1550         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1551                          "16-bit accessor invalid for natural width field");
1552 }
1553
1554 static __always_inline void vmcs_check32(unsigned long field)
1555 {
1556         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1557                          "32-bit accessor invalid for 16-bit field");
1558         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1559                          "32-bit accessor invalid for natural width field");
1560 }
1561
1562 static __always_inline void vmcs_check64(unsigned long field)
1563 {
1564         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1565                          "64-bit accessor invalid for 16-bit field");
1566         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1567                          "64-bit accessor invalid for 64-bit high field");
1568         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1569                          "64-bit accessor invalid for 32-bit field");
1570         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1571                          "64-bit accessor invalid for natural width field");
1572 }
1573
1574 static __always_inline void vmcs_checkl(unsigned long field)
1575 {
1576         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1577                          "Natural width accessor invalid for 16-bit field");
1578         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1579                          "Natural width accessor invalid for 64-bit field");
1580         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1581                          "Natural width accessor invalid for 64-bit high field");
1582         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1583                          "Natural width accessor invalid for 32-bit field");
1584 }
1585
1586 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1587 {
1588         unsigned long value;
1589
1590         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1591                       : "=a"(value) : "d"(field) : "cc");
1592         return value;
1593 }
1594
1595 static __always_inline u16 vmcs_read16(unsigned long field)
1596 {
1597         vmcs_check16(field);
1598         return __vmcs_readl(field);
1599 }
1600
1601 static __always_inline u32 vmcs_read32(unsigned long field)
1602 {
1603         vmcs_check32(field);
1604         return __vmcs_readl(field);
1605 }
1606
1607 static __always_inline u64 vmcs_read64(unsigned long field)
1608 {
1609         vmcs_check64(field);
1610 #ifdef CONFIG_X86_64
1611         return __vmcs_readl(field);
1612 #else
1613         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1614 #endif
1615 }
1616
1617 static __always_inline unsigned long vmcs_readl(unsigned long field)
1618 {
1619         vmcs_checkl(field);
1620         return __vmcs_readl(field);
1621 }
1622
1623 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1624 {
1625         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1626                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1627         dump_stack();
1628 }
1629
1630 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1631 {
1632         u8 error;
1633
1634         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1635                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1636         if (unlikely(error))
1637                 vmwrite_error(field, value);
1638 }
1639
1640 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1641 {
1642         vmcs_check16(field);
1643         __vmcs_writel(field, value);
1644 }
1645
1646 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1647 {
1648         vmcs_check32(field);
1649         __vmcs_writel(field, value);
1650 }
1651
1652 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1653 {
1654         vmcs_check64(field);
1655         __vmcs_writel(field, value);
1656 #ifndef CONFIG_X86_64
1657         asm volatile ("");
1658         __vmcs_writel(field+1, value >> 32);
1659 #endif
1660 }
1661
1662 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1663 {
1664         vmcs_checkl(field);
1665         __vmcs_writel(field, value);
1666 }
1667
1668 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1669 {
1670         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1671                          "vmcs_clear_bits does not support 64-bit fields");
1672         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1673 }
1674
1675 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1676 {
1677         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1678                          "vmcs_set_bits does not support 64-bit fields");
1679         __vmcs_writel(field, __vmcs_readl(field) | mask);
1680 }
1681
1682 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1683 {
1684         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1685 }
1686
1687 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1688 {
1689         vmcs_write32(VM_ENTRY_CONTROLS, val);
1690         vmx->vm_entry_controls_shadow = val;
1691 }
1692
1693 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1694 {
1695         if (vmx->vm_entry_controls_shadow != val)
1696                 vm_entry_controls_init(vmx, val);
1697 }
1698
1699 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1700 {
1701         return vmx->vm_entry_controls_shadow;
1702 }
1703
1704
1705 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1706 {
1707         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1708 }
1709
1710 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1711 {
1712         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1713 }
1714
1715 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1716 {
1717         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1718 }
1719
1720 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1721 {
1722         vmcs_write32(VM_EXIT_CONTROLS, val);
1723         vmx->vm_exit_controls_shadow = val;
1724 }
1725
1726 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1727 {
1728         if (vmx->vm_exit_controls_shadow != val)
1729                 vm_exit_controls_init(vmx, val);
1730 }
1731
1732 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1733 {
1734         return vmx->vm_exit_controls_shadow;
1735 }
1736
1737
1738 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1739 {
1740         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1741 }
1742
1743 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1744 {
1745         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1746 }
1747
1748 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1749 {
1750         vmx->segment_cache.bitmask = 0;
1751 }
1752
1753 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1754                                        unsigned field)
1755 {
1756         bool ret;
1757         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1758
1759         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1760                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1761                 vmx->segment_cache.bitmask = 0;
1762         }
1763         ret = vmx->segment_cache.bitmask & mask;
1764         vmx->segment_cache.bitmask |= mask;
1765         return ret;
1766 }
1767
1768 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1769 {
1770         u16 *p = &vmx->segment_cache.seg[seg].selector;
1771
1772         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1773                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1774         return *p;
1775 }
1776
1777 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1778 {
1779         ulong *p = &vmx->segment_cache.seg[seg].base;
1780
1781         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1782                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1783         return *p;
1784 }
1785
1786 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1787 {
1788         u32 *p = &vmx->segment_cache.seg[seg].limit;
1789
1790         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1791                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1792         return *p;
1793 }
1794
1795 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1796 {
1797         u32 *p = &vmx->segment_cache.seg[seg].ar;
1798
1799         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1800                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1801         return *p;
1802 }
1803
1804 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1805 {
1806         u32 eb;
1807
1808         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1809              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1810         if ((vcpu->guest_debug &
1811              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1812             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1813                 eb |= 1u << BP_VECTOR;
1814         if (to_vmx(vcpu)->rmode.vm86_active)
1815                 eb = ~0;
1816         if (enable_ept)
1817                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1818         if (vcpu->fpu_active)
1819                 eb &= ~(1u << NM_VECTOR);
1820
1821         /* When we are running a nested L2 guest and L1 specified for it a
1822          * certain exception bitmap, we must trap the same exceptions and pass
1823          * them to L1. When running L2, we will only handle the exceptions
1824          * specified above if L1 did not want them.
1825          */
1826         if (is_guest_mode(vcpu))
1827                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1828
1829         vmcs_write32(EXCEPTION_BITMAP, eb);
1830 }
1831
1832 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1833                 unsigned long entry, unsigned long exit)
1834 {
1835         vm_entry_controls_clearbit(vmx, entry);
1836         vm_exit_controls_clearbit(vmx, exit);
1837 }
1838
1839 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1840 {
1841         unsigned i;
1842         struct msr_autoload *m = &vmx->msr_autoload;
1843
1844         switch (msr) {
1845         case MSR_EFER:
1846                 if (cpu_has_load_ia32_efer) {
1847                         clear_atomic_switch_msr_special(vmx,
1848                                         VM_ENTRY_LOAD_IA32_EFER,
1849                                         VM_EXIT_LOAD_IA32_EFER);
1850                         return;
1851                 }
1852                 break;
1853         case MSR_CORE_PERF_GLOBAL_CTRL:
1854                 if (cpu_has_load_perf_global_ctrl) {
1855                         clear_atomic_switch_msr_special(vmx,
1856                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1857                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1858                         return;
1859                 }
1860                 break;
1861         }
1862
1863         for (i = 0; i < m->nr; ++i)
1864                 if (m->guest[i].index == msr)
1865                         break;
1866
1867         if (i == m->nr)
1868                 return;
1869         --m->nr;
1870         m->guest[i] = m->guest[m->nr];
1871         m->host[i] = m->host[m->nr];
1872         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1873         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1874 }
1875
1876 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1877                 unsigned long entry, unsigned long exit,
1878                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1879                 u64 guest_val, u64 host_val)
1880 {
1881         vmcs_write64(guest_val_vmcs, guest_val);
1882         vmcs_write64(host_val_vmcs, host_val);
1883         vm_entry_controls_setbit(vmx, entry);
1884         vm_exit_controls_setbit(vmx, exit);
1885 }
1886
1887 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1888                                   u64 guest_val, u64 host_val)
1889 {
1890         unsigned i;
1891         struct msr_autoload *m = &vmx->msr_autoload;
1892
1893         switch (msr) {
1894         case MSR_EFER:
1895                 if (cpu_has_load_ia32_efer) {
1896                         add_atomic_switch_msr_special(vmx,
1897                                         VM_ENTRY_LOAD_IA32_EFER,
1898                                         VM_EXIT_LOAD_IA32_EFER,
1899                                         GUEST_IA32_EFER,
1900                                         HOST_IA32_EFER,
1901                                         guest_val, host_val);
1902                         return;
1903                 }
1904                 break;
1905         case MSR_CORE_PERF_GLOBAL_CTRL:
1906                 if (cpu_has_load_perf_global_ctrl) {
1907                         add_atomic_switch_msr_special(vmx,
1908                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1909                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1910                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1911                                         HOST_IA32_PERF_GLOBAL_CTRL,
1912                                         guest_val, host_val);
1913                         return;
1914                 }
1915                 break;
1916         case MSR_IA32_PEBS_ENABLE:
1917                 /* PEBS needs a quiescent period after being disabled (to write
1918                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1919                  * provide that period, so a CPU could write host's record into
1920                  * guest's memory.
1921                  */
1922                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1923         }
1924
1925         for (i = 0; i < m->nr; ++i)
1926                 if (m->guest[i].index == msr)
1927                         break;
1928
1929         if (i == NR_AUTOLOAD_MSRS) {
1930                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1931                                 "Can't add msr %x\n", msr);
1932                 return;
1933         } else if (i == m->nr) {
1934                 ++m->nr;
1935                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1936                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1937         }
1938
1939         m->guest[i].index = msr;
1940         m->guest[i].value = guest_val;
1941         m->host[i].index = msr;
1942         m->host[i].value = host_val;
1943 }
1944
1945 static void reload_tss(void)
1946 {
1947         /*
1948          * VT restores TR but not its size.  Useless.
1949          */
1950         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1951         struct desc_struct *descs;
1952
1953         descs = (void *)gdt->address;
1954         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1955         load_TR_desc();
1956 }
1957
1958 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1959 {
1960         u64 guest_efer = vmx->vcpu.arch.efer;
1961         u64 ignore_bits = 0;
1962
1963         if (!enable_ept) {
1964                 /*
1965                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1966                  * host CPUID is more efficient than testing guest CPUID
1967                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1968                  */
1969                 if (boot_cpu_has(X86_FEATURE_SMEP))
1970                         guest_efer |= EFER_NX;
1971                 else if (!(guest_efer & EFER_NX))
1972                         ignore_bits |= EFER_NX;
1973         }
1974
1975         /*
1976          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1977          */
1978         ignore_bits |= EFER_SCE;
1979 #ifdef CONFIG_X86_64
1980         ignore_bits |= EFER_LMA | EFER_LME;
1981         /* SCE is meaningful only in long mode on Intel */
1982         if (guest_efer & EFER_LMA)
1983                 ignore_bits &= ~(u64)EFER_SCE;
1984 #endif
1985
1986         clear_atomic_switch_msr(vmx, MSR_EFER);
1987
1988         /*
1989          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1990          * On CPUs that support "load IA32_EFER", always switch EFER
1991          * atomically, since it's faster than switching it manually.
1992          */
1993         if (cpu_has_load_ia32_efer ||
1994             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1995                 if (!(guest_efer & EFER_LMA))
1996                         guest_efer &= ~EFER_LME;
1997                 if (guest_efer != host_efer)
1998                         add_atomic_switch_msr(vmx, MSR_EFER,
1999                                               guest_efer, host_efer);
2000                 return false;
2001         } else {
2002                 guest_efer &= ~ignore_bits;
2003                 guest_efer |= host_efer & ignore_bits;
2004
2005                 vmx->guest_msrs[efer_offset].data = guest_efer;
2006                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2007
2008                 return true;
2009         }
2010 }
2011
2012 static unsigned long segment_base(u16 selector)
2013 {
2014         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2015         struct desc_struct *d;
2016         unsigned long table_base;
2017         unsigned long v;
2018
2019         if (!(selector & ~3))
2020                 return 0;
2021
2022         table_base = gdt->address;
2023
2024         if (selector & 4) {           /* from ldt */
2025                 u16 ldt_selector = kvm_read_ldt();
2026
2027                 if (!(ldt_selector & ~3))
2028                         return 0;
2029
2030                 table_base = segment_base(ldt_selector);
2031         }
2032         d = (struct desc_struct *)(table_base + (selector & ~7));
2033         v = get_desc_base(d);
2034 #ifdef CONFIG_X86_64
2035        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2036                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2037 #endif
2038         return v;
2039 }
2040
2041 static inline unsigned long kvm_read_tr_base(void)
2042 {
2043         u16 tr;
2044         asm("str %0" : "=g"(tr));
2045         return segment_base(tr);
2046 }
2047
2048 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2049 {
2050         struct vcpu_vmx *vmx = to_vmx(vcpu);
2051         int i;
2052
2053         if (vmx->host_state.loaded)
2054                 return;
2055
2056         vmx->host_state.loaded = 1;
2057         /*
2058          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2059          * allow segment selectors with cpl > 0 or ti == 1.
2060          */
2061         vmx->host_state.ldt_sel = kvm_read_ldt();
2062         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2063         savesegment(fs, vmx->host_state.fs_sel);
2064         if (!(vmx->host_state.fs_sel & 7)) {
2065                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2066                 vmx->host_state.fs_reload_needed = 0;
2067         } else {
2068                 vmcs_write16(HOST_FS_SELECTOR, 0);
2069                 vmx->host_state.fs_reload_needed = 1;
2070         }
2071         savesegment(gs, vmx->host_state.gs_sel);
2072         if (!(vmx->host_state.gs_sel & 7))
2073                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2074         else {
2075                 vmcs_write16(HOST_GS_SELECTOR, 0);
2076                 vmx->host_state.gs_ldt_reload_needed = 1;
2077         }
2078
2079 #ifdef CONFIG_X86_64
2080         savesegment(ds, vmx->host_state.ds_sel);
2081         savesegment(es, vmx->host_state.es_sel);
2082 #endif
2083
2084 #ifdef CONFIG_X86_64
2085         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2086         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2087 #else
2088         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2089         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2090 #endif
2091
2092 #ifdef CONFIG_X86_64
2093         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2094         if (is_long_mode(&vmx->vcpu))
2095                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2096 #endif
2097         if (boot_cpu_has(X86_FEATURE_MPX))
2098                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2099         for (i = 0; i < vmx->save_nmsrs; ++i)
2100                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2101                                    vmx->guest_msrs[i].data,
2102                                    vmx->guest_msrs[i].mask);
2103 }
2104
2105 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2106 {
2107         if (!vmx->host_state.loaded)
2108                 return;
2109
2110         ++vmx->vcpu.stat.host_state_reload;
2111         vmx->host_state.loaded = 0;
2112 #ifdef CONFIG_X86_64
2113         if (is_long_mode(&vmx->vcpu))
2114                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2115 #endif
2116         if (vmx->host_state.gs_ldt_reload_needed) {
2117                 kvm_load_ldt(vmx->host_state.ldt_sel);
2118 #ifdef CONFIG_X86_64
2119                 load_gs_index(vmx->host_state.gs_sel);
2120 #else
2121                 loadsegment(gs, vmx->host_state.gs_sel);
2122 #endif
2123         }
2124         if (vmx->host_state.fs_reload_needed)
2125                 loadsegment(fs, vmx->host_state.fs_sel);
2126 #ifdef CONFIG_X86_64
2127         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2128                 loadsegment(ds, vmx->host_state.ds_sel);
2129                 loadsegment(es, vmx->host_state.es_sel);
2130         }
2131 #endif
2132         reload_tss();
2133 #ifdef CONFIG_X86_64
2134         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2135 #endif
2136         if (vmx->host_state.msr_host_bndcfgs)
2137                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2138         /*
2139          * If the FPU is not active (through the host task or
2140          * the guest vcpu), then restore the cr0.TS bit.
2141          */
2142         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2143                 stts();
2144         load_gdt(this_cpu_ptr(&host_gdt));
2145 }
2146
2147 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2148 {
2149         preempt_disable();
2150         __vmx_load_host_state(vmx);
2151         preempt_enable();
2152 }
2153
2154 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2155 {
2156         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2157         struct pi_desc old, new;
2158         unsigned int dest;
2159
2160         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2161                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2162                 !kvm_vcpu_apicv_active(vcpu))
2163                 return;
2164
2165         do {
2166                 old.control = new.control = pi_desc->control;
2167
2168                 /*
2169                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2170                  * are two possible cases:
2171                  * 1. After running 'pre_block', context switch
2172                  *    happened. For this case, 'sn' was set in
2173                  *    vmx_vcpu_put(), so we need to clear it here.
2174                  * 2. After running 'pre_block', we were blocked,
2175                  *    and woken up by some other guy. For this case,
2176                  *    we don't need to do anything, 'pi_post_block'
2177                  *    will do everything for us. However, we cannot
2178                  *    check whether it is case #1 or case #2 here
2179                  *    (maybe, not needed), so we also clear sn here,
2180                  *    I think it is not a big deal.
2181                  */
2182                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2183                         if (vcpu->cpu != cpu) {
2184                                 dest = cpu_physical_id(cpu);
2185
2186                                 if (x2apic_enabled())
2187                                         new.ndst = dest;
2188                                 else
2189                                         new.ndst = (dest << 8) & 0xFF00;
2190                         }
2191
2192                         /* set 'NV' to 'notification vector' */
2193                         new.nv = POSTED_INTR_VECTOR;
2194                 }
2195
2196                 /* Allow posting non-urgent interrupts */
2197                 new.sn = 0;
2198         } while (cmpxchg(&pi_desc->control, old.control,
2199                         new.control) != old.control);
2200 }
2201
2202 /*
2203  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2204  * vcpu mutex is already taken.
2205  */
2206 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2207 {
2208         struct vcpu_vmx *vmx = to_vmx(vcpu);
2209         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2210         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2211
2212         if (!vmm_exclusive)
2213                 kvm_cpu_vmxon(phys_addr);
2214         else if (!already_loaded)
2215                 loaded_vmcs_clear(vmx->loaded_vmcs);
2216
2217         if (!already_loaded) {
2218                 local_irq_disable();
2219                 crash_disable_local_vmclear(cpu);
2220
2221                 /*
2222                  * Read loaded_vmcs->cpu should be before fetching
2223                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2224                  * See the comments in __loaded_vmcs_clear().
2225                  */
2226                 smp_rmb();
2227
2228                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2229                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2230                 crash_enable_local_vmclear(cpu);
2231                 local_irq_enable();
2232         }
2233
2234         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2235                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2236                 vmcs_load(vmx->loaded_vmcs->vmcs);
2237         }
2238
2239         if (!already_loaded) {
2240                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2241                 unsigned long sysenter_esp;
2242
2243                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2244
2245                 /*
2246                  * Linux uses per-cpu TSS and GDT, so set these when switching
2247                  * processors.
2248                  */
2249                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2250                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2251
2252                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2253                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2254
2255                 vmx->loaded_vmcs->cpu = cpu;
2256         }
2257
2258         /* Setup TSC multiplier */
2259         if (kvm_has_tsc_control &&
2260             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2261                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2262                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2263         }
2264
2265         vmx_vcpu_pi_load(vcpu, cpu);
2266         vmx->host_pkru = read_pkru();
2267 }
2268
2269 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2270 {
2271         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2272
2273         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2274                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2275                 !kvm_vcpu_apicv_active(vcpu))
2276                 return;
2277
2278         /* Set SN when the vCPU is preempted */
2279         if (vcpu->preempted)
2280                 pi_set_sn(pi_desc);
2281 }
2282
2283 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2284 {
2285         vmx_vcpu_pi_put(vcpu);
2286
2287         __vmx_load_host_state(to_vmx(vcpu));
2288         if (!vmm_exclusive) {
2289                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2290                 vcpu->cpu = -1;
2291                 kvm_cpu_vmxoff();
2292         }
2293 }
2294
2295 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2296 {
2297         ulong cr0;
2298
2299         if (vcpu->fpu_active)
2300                 return;
2301         vcpu->fpu_active = 1;
2302         cr0 = vmcs_readl(GUEST_CR0);
2303         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2304         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2305         vmcs_writel(GUEST_CR0, cr0);
2306         update_exception_bitmap(vcpu);
2307         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2308         if (is_guest_mode(vcpu))
2309                 vcpu->arch.cr0_guest_owned_bits &=
2310                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2311         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2312 }
2313
2314 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2315
2316 /*
2317  * Return the cr0 value that a nested guest would read. This is a combination
2318  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2319  * its hypervisor (cr0_read_shadow).
2320  */
2321 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2322 {
2323         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2324                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2325 }
2326 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2327 {
2328         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2329                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2330 }
2331
2332 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2333 {
2334         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2335          * set this *before* calling this function.
2336          */
2337         vmx_decache_cr0_guest_bits(vcpu);
2338         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2339         update_exception_bitmap(vcpu);
2340         vcpu->arch.cr0_guest_owned_bits = 0;
2341         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2342         if (is_guest_mode(vcpu)) {
2343                 /*
2344                  * L1's specified read shadow might not contain the TS bit,
2345                  * so now that we turned on shadowing of this bit, we need to
2346                  * set this bit of the shadow. Like in nested_vmx_run we need
2347                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2348                  * up-to-date here because we just decached cr0.TS (and we'll
2349                  * only update vmcs12->guest_cr0 on nested exit).
2350                  */
2351                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2352                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2353                         (vcpu->arch.cr0 & X86_CR0_TS);
2354                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2355         } else
2356                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2357 }
2358
2359 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2360 {
2361         unsigned long rflags, save_rflags;
2362
2363         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2364                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2365                 rflags = vmcs_readl(GUEST_RFLAGS);
2366                 if (to_vmx(vcpu)->rmode.vm86_active) {
2367                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2368                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2369                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2370                 }
2371                 to_vmx(vcpu)->rflags = rflags;
2372         }
2373         return to_vmx(vcpu)->rflags;
2374 }
2375
2376 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2377 {
2378         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2379         to_vmx(vcpu)->rflags = rflags;
2380         if (to_vmx(vcpu)->rmode.vm86_active) {
2381                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2382                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2383         }
2384         vmcs_writel(GUEST_RFLAGS, rflags);
2385 }
2386
2387 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2388 {
2389         return to_vmx(vcpu)->guest_pkru;
2390 }
2391
2392 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2393 {
2394         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2395         int ret = 0;
2396
2397         if (interruptibility & GUEST_INTR_STATE_STI)
2398                 ret |= KVM_X86_SHADOW_INT_STI;
2399         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2400                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2401
2402         return ret;
2403 }
2404
2405 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2406 {
2407         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2408         u32 interruptibility = interruptibility_old;
2409
2410         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2411
2412         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2413                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2414         else if (mask & KVM_X86_SHADOW_INT_STI)
2415                 interruptibility |= GUEST_INTR_STATE_STI;
2416
2417         if ((interruptibility != interruptibility_old))
2418                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2419 }
2420
2421 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2422 {
2423         unsigned long rip;
2424
2425         rip = kvm_rip_read(vcpu);
2426         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2427         kvm_rip_write(vcpu, rip);
2428
2429         /* skipping an emulated instruction also counts */
2430         vmx_set_interrupt_shadow(vcpu, 0);
2431 }
2432
2433 /*
2434  * KVM wants to inject page-faults which it got to the guest. This function
2435  * checks whether in a nested guest, we need to inject them to L1 or L2.
2436  */
2437 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2438 {
2439         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2440
2441         if (!(vmcs12->exception_bitmap & (1u << nr)))
2442                 return 0;
2443
2444         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2445                           vmcs_read32(VM_EXIT_INTR_INFO),
2446                           vmcs_readl(EXIT_QUALIFICATION));
2447         return 1;
2448 }
2449
2450 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2451                                 bool has_error_code, u32 error_code,
2452                                 bool reinject)
2453 {
2454         struct vcpu_vmx *vmx = to_vmx(vcpu);
2455         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2456
2457         if (!reinject && is_guest_mode(vcpu) &&
2458             nested_vmx_check_exception(vcpu, nr))
2459                 return;
2460
2461         if (has_error_code) {
2462                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2463                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2464         }
2465
2466         if (vmx->rmode.vm86_active) {
2467                 int inc_eip = 0;
2468                 if (kvm_exception_is_soft(nr))
2469                         inc_eip = vcpu->arch.event_exit_inst_len;
2470                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2471                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2472                 return;
2473         }
2474
2475         if (kvm_exception_is_soft(nr)) {
2476                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2477                              vmx->vcpu.arch.event_exit_inst_len);
2478                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2479         } else
2480                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2481
2482         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2483 }
2484
2485 static bool vmx_rdtscp_supported(void)
2486 {
2487         return cpu_has_vmx_rdtscp();
2488 }
2489
2490 static bool vmx_invpcid_supported(void)
2491 {
2492         return cpu_has_vmx_invpcid() && enable_ept;
2493 }
2494
2495 /*
2496  * Swap MSR entry in host/guest MSR entry array.
2497  */
2498 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2499 {
2500         struct shared_msr_entry tmp;
2501
2502         tmp = vmx->guest_msrs[to];
2503         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2504         vmx->guest_msrs[from] = tmp;
2505 }
2506
2507 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2508 {
2509         unsigned long *msr_bitmap;
2510
2511         if (is_guest_mode(vcpu))
2512                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2513         else if (cpu_has_secondary_exec_ctrls() &&
2514                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2515                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2516                 if (is_long_mode(vcpu))
2517                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2518                 else
2519                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2520         } else {
2521                 if (is_long_mode(vcpu))
2522                         msr_bitmap = vmx_msr_bitmap_longmode;
2523                 else
2524                         msr_bitmap = vmx_msr_bitmap_legacy;
2525         }
2526
2527         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2528 }
2529
2530 /*
2531  * Set up the vmcs to automatically save and restore system
2532  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2533  * mode, as fiddling with msrs is very expensive.
2534  */
2535 static void setup_msrs(struct vcpu_vmx *vmx)
2536 {
2537         int save_nmsrs, index;
2538
2539         save_nmsrs = 0;
2540 #ifdef CONFIG_X86_64
2541         if (is_long_mode(&vmx->vcpu)) {
2542                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2543                 if (index >= 0)
2544                         move_msr_up(vmx, index, save_nmsrs++);
2545                 index = __find_msr_index(vmx, MSR_LSTAR);
2546                 if (index >= 0)
2547                         move_msr_up(vmx, index, save_nmsrs++);
2548                 index = __find_msr_index(vmx, MSR_CSTAR);
2549                 if (index >= 0)
2550                         move_msr_up(vmx, index, save_nmsrs++);
2551                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2552                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2553                         move_msr_up(vmx, index, save_nmsrs++);
2554                 /*
2555                  * MSR_STAR is only needed on long mode guests, and only
2556                  * if efer.sce is enabled.
2557                  */
2558                 index = __find_msr_index(vmx, MSR_STAR);
2559                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2560                         move_msr_up(vmx, index, save_nmsrs++);
2561         }
2562 #endif
2563         index = __find_msr_index(vmx, MSR_EFER);
2564         if (index >= 0 && update_transition_efer(vmx, index))
2565                 move_msr_up(vmx, index, save_nmsrs++);
2566
2567         vmx->save_nmsrs = save_nmsrs;
2568
2569         if (cpu_has_vmx_msr_bitmap())
2570                 vmx_set_msr_bitmap(&vmx->vcpu);
2571 }
2572
2573 /*
2574  * reads and returns guest's timestamp counter "register"
2575  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2576  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2577  */
2578 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2579 {
2580         u64 host_tsc, tsc_offset;
2581
2582         host_tsc = rdtsc();
2583         tsc_offset = vmcs_read64(TSC_OFFSET);
2584         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2585 }
2586
2587 /*
2588  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2589  * counter, even if a nested guest (L2) is currently running.
2590  */
2591 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2592 {
2593         u64 tsc_offset;
2594
2595         tsc_offset = is_guest_mode(vcpu) ?
2596                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2597                 vmcs_read64(TSC_OFFSET);
2598         return host_tsc + tsc_offset;
2599 }
2600
2601 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2602 {
2603         return vmcs_read64(TSC_OFFSET);
2604 }
2605
2606 /*
2607  * writes 'offset' into guest's timestamp counter offset register
2608  */
2609 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2610 {
2611         if (is_guest_mode(vcpu)) {
2612                 /*
2613                  * We're here if L1 chose not to trap WRMSR to TSC. According
2614                  * to the spec, this should set L1's TSC; The offset that L1
2615                  * set for L2 remains unchanged, and still needs to be added
2616                  * to the newly set TSC to get L2's TSC.
2617                  */
2618                 struct vmcs12 *vmcs12;
2619                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2620                 /* recalculate vmcs02.TSC_OFFSET: */
2621                 vmcs12 = get_vmcs12(vcpu);
2622                 vmcs_write64(TSC_OFFSET, offset +
2623                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2624                          vmcs12->tsc_offset : 0));
2625         } else {
2626                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2627                                            vmcs_read64(TSC_OFFSET), offset);
2628                 vmcs_write64(TSC_OFFSET, offset);
2629         }
2630 }
2631
2632 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2633 {
2634         u64 offset = vmcs_read64(TSC_OFFSET);
2635
2636         vmcs_write64(TSC_OFFSET, offset + adjustment);
2637         if (is_guest_mode(vcpu)) {
2638                 /* Even when running L2, the adjustment needs to apply to L1 */
2639                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2640         } else
2641                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2642                                            offset + adjustment);
2643 }
2644
2645 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2646 {
2647         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2648         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2649 }
2650
2651 /*
2652  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2653  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2654  * all guests if the "nested" module option is off, and can also be disabled
2655  * for a single guest by disabling its VMX cpuid bit.
2656  */
2657 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2658 {
2659         return nested && guest_cpuid_has_vmx(vcpu);
2660 }
2661
2662 /*
2663  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2664  * returned for the various VMX controls MSRs when nested VMX is enabled.
2665  * The same values should also be used to verify that vmcs12 control fields are
2666  * valid during nested entry from L1 to L2.
2667  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2668  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2669  * bit in the high half is on if the corresponding bit in the control field
2670  * may be on. See also vmx_control_verify().
2671  */
2672 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2673 {
2674         /*
2675          * Note that as a general rule, the high half of the MSRs (bits in
2676          * the control fields which may be 1) should be initialized by the
2677          * intersection of the underlying hardware's MSR (i.e., features which
2678          * can be supported) and the list of features we want to expose -
2679          * because they are known to be properly supported in our code.
2680          * Also, usually, the low half of the MSRs (bits which must be 1) can
2681          * be set to 0, meaning that L1 may turn off any of these bits. The
2682          * reason is that if one of these bits is necessary, it will appear
2683          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2684          * fields of vmcs01 and vmcs02, will turn these bits off - and
2685          * nested_vmx_exit_handled() will not pass related exits to L1.
2686          * These rules have exceptions below.
2687          */
2688
2689         /* pin-based controls */
2690         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2691                 vmx->nested.nested_vmx_pinbased_ctls_low,
2692                 vmx->nested.nested_vmx_pinbased_ctls_high);
2693         vmx->nested.nested_vmx_pinbased_ctls_low |=
2694                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2695         vmx->nested.nested_vmx_pinbased_ctls_high &=
2696                 PIN_BASED_EXT_INTR_MASK |
2697                 PIN_BASED_NMI_EXITING |
2698                 PIN_BASED_VIRTUAL_NMIS;
2699         vmx->nested.nested_vmx_pinbased_ctls_high |=
2700                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2701                 PIN_BASED_VMX_PREEMPTION_TIMER;
2702         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2703                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2704                         PIN_BASED_POSTED_INTR;
2705
2706         /* exit controls */
2707         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2708                 vmx->nested.nested_vmx_exit_ctls_low,
2709                 vmx->nested.nested_vmx_exit_ctls_high);
2710         vmx->nested.nested_vmx_exit_ctls_low =
2711                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2712
2713         vmx->nested.nested_vmx_exit_ctls_high &=
2714 #ifdef CONFIG_X86_64
2715                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2716 #endif
2717                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2718         vmx->nested.nested_vmx_exit_ctls_high |=
2719                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2720                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2721                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2722
2723         if (kvm_mpx_supported())
2724                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2725
2726         /* We support free control of debug control saving. */
2727         vmx->nested.nested_vmx_true_exit_ctls_low =
2728                 vmx->nested.nested_vmx_exit_ctls_low &
2729                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2730
2731         /* entry controls */
2732         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2733                 vmx->nested.nested_vmx_entry_ctls_low,
2734                 vmx->nested.nested_vmx_entry_ctls_high);
2735         vmx->nested.nested_vmx_entry_ctls_low =
2736                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2737         vmx->nested.nested_vmx_entry_ctls_high &=
2738 #ifdef CONFIG_X86_64
2739                 VM_ENTRY_IA32E_MODE |
2740 #endif
2741                 VM_ENTRY_LOAD_IA32_PAT;
2742         vmx->nested.nested_vmx_entry_ctls_high |=
2743                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2744         if (kvm_mpx_supported())
2745                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2746
2747         /* We support free control of debug control loading. */
2748         vmx->nested.nested_vmx_true_entry_ctls_low =
2749                 vmx->nested.nested_vmx_entry_ctls_low &
2750                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2751
2752         /* cpu-based controls */
2753         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2754                 vmx->nested.nested_vmx_procbased_ctls_low,
2755                 vmx->nested.nested_vmx_procbased_ctls_high);
2756         vmx->nested.nested_vmx_procbased_ctls_low =
2757                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2758         vmx->nested.nested_vmx_procbased_ctls_high &=
2759                 CPU_BASED_VIRTUAL_INTR_PENDING |
2760                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2761                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2762                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2763                 CPU_BASED_CR3_STORE_EXITING |
2764 #ifdef CONFIG_X86_64
2765                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2766 #endif
2767                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2768                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2769                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2770                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2771                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2772         /*
2773          * We can allow some features even when not supported by the
2774          * hardware. For example, L1 can specify an MSR bitmap - and we
2775          * can use it to avoid exits to L1 - even when L0 runs L2
2776          * without MSR bitmaps.
2777          */
2778         vmx->nested.nested_vmx_procbased_ctls_high |=
2779                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2780                 CPU_BASED_USE_MSR_BITMAPS;
2781
2782         /* We support free control of CR3 access interception. */
2783         vmx->nested.nested_vmx_true_procbased_ctls_low =
2784                 vmx->nested.nested_vmx_procbased_ctls_low &
2785                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2786
2787         /* secondary cpu-based controls */
2788         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2789                 vmx->nested.nested_vmx_secondary_ctls_low,
2790                 vmx->nested.nested_vmx_secondary_ctls_high);
2791         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2792         vmx->nested.nested_vmx_secondary_ctls_high &=
2793                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2794                 SECONDARY_EXEC_RDTSCP |
2795                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2796                 SECONDARY_EXEC_ENABLE_VPID |
2797                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2798                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2799                 SECONDARY_EXEC_WBINVD_EXITING |
2800                 SECONDARY_EXEC_XSAVES;
2801
2802         if (enable_ept) {
2803                 /* nested EPT: emulate EPT also to L1 */
2804                 vmx->nested.nested_vmx_secondary_ctls_high |=
2805                         SECONDARY_EXEC_ENABLE_EPT;
2806                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2807                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2808                          VMX_EPT_INVEPT_BIT;
2809                 if (cpu_has_vmx_ept_execute_only())
2810                         vmx->nested.nested_vmx_ept_caps |=
2811                                 VMX_EPT_EXECUTE_ONLY_BIT;
2812                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2813                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2814                         VMX_EPT_EXTENT_CONTEXT_BIT;
2815         } else
2816                 vmx->nested.nested_vmx_ept_caps = 0;
2817
2818         /*
2819          * Old versions of KVM use the single-context version without
2820          * checking for support, so declare that it is supported even
2821          * though it is treated as global context.  The alternative is
2822          * not failing the single-context invvpid, and it is worse.
2823          */
2824         if (enable_vpid)
2825                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2826                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2827                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2828         else
2829                 vmx->nested.nested_vmx_vpid_caps = 0;
2830
2831         if (enable_unrestricted_guest)
2832                 vmx->nested.nested_vmx_secondary_ctls_high |=
2833                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2834
2835         /* miscellaneous data */
2836         rdmsr(MSR_IA32_VMX_MISC,
2837                 vmx->nested.nested_vmx_misc_low,
2838                 vmx->nested.nested_vmx_misc_high);
2839         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2840         vmx->nested.nested_vmx_misc_low |=
2841                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2842                 VMX_MISC_ACTIVITY_HLT;
2843         vmx->nested.nested_vmx_misc_high = 0;
2844 }
2845
2846 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2847 {
2848         /*
2849          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2850          */
2851         return ((control & high) | low) == control;
2852 }
2853
2854 static inline u64 vmx_control_msr(u32 low, u32 high)
2855 {
2856         return low | ((u64)high << 32);
2857 }
2858
2859 /* Returns 0 on success, non-0 otherwise. */
2860 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2861 {
2862         struct vcpu_vmx *vmx = to_vmx(vcpu);
2863
2864         switch (msr_index) {
2865         case MSR_IA32_VMX_BASIC:
2866                 /*
2867                  * This MSR reports some information about VMX support. We
2868                  * should return information about the VMX we emulate for the
2869                  * guest, and the VMCS structure we give it - not about the
2870                  * VMX support of the underlying hardware.
2871                  */
2872                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2873                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2874                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2875                 break;
2876         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2877         case MSR_IA32_VMX_PINBASED_CTLS:
2878                 *pdata = vmx_control_msr(
2879                         vmx->nested.nested_vmx_pinbased_ctls_low,
2880                         vmx->nested.nested_vmx_pinbased_ctls_high);
2881                 break;
2882         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2883                 *pdata = vmx_control_msr(
2884                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2885                         vmx->nested.nested_vmx_procbased_ctls_high);
2886                 break;
2887         case MSR_IA32_VMX_PROCBASED_CTLS:
2888                 *pdata = vmx_control_msr(
2889                         vmx->nested.nested_vmx_procbased_ctls_low,
2890                         vmx->nested.nested_vmx_procbased_ctls_high);
2891                 break;
2892         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2893                 *pdata = vmx_control_msr(
2894                         vmx->nested.nested_vmx_true_exit_ctls_low,
2895                         vmx->nested.nested_vmx_exit_ctls_high);
2896                 break;
2897         case MSR_IA32_VMX_EXIT_CTLS:
2898                 *pdata = vmx_control_msr(
2899                         vmx->nested.nested_vmx_exit_ctls_low,
2900                         vmx->nested.nested_vmx_exit_ctls_high);
2901                 break;
2902         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2903                 *pdata = vmx_control_msr(
2904                         vmx->nested.nested_vmx_true_entry_ctls_low,
2905                         vmx->nested.nested_vmx_entry_ctls_high);
2906                 break;
2907         case MSR_IA32_VMX_ENTRY_CTLS:
2908                 *pdata = vmx_control_msr(
2909                         vmx->nested.nested_vmx_entry_ctls_low,
2910                         vmx->nested.nested_vmx_entry_ctls_high);
2911                 break;
2912         case MSR_IA32_VMX_MISC:
2913                 *pdata = vmx_control_msr(
2914                         vmx->nested.nested_vmx_misc_low,
2915                         vmx->nested.nested_vmx_misc_high);
2916                 break;
2917         /*
2918          * These MSRs specify bits which the guest must keep fixed (on or off)
2919          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2920          * We picked the standard core2 setting.
2921          */
2922 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2923 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2924         case MSR_IA32_VMX_CR0_FIXED0:
2925                 *pdata = VMXON_CR0_ALWAYSON;
2926                 break;
2927         case MSR_IA32_VMX_CR0_FIXED1:
2928                 *pdata = -1ULL;
2929                 break;
2930         case MSR_IA32_VMX_CR4_FIXED0:
2931                 *pdata = VMXON_CR4_ALWAYSON;
2932                 break;
2933         case MSR_IA32_VMX_CR4_FIXED1:
2934                 *pdata = -1ULL;
2935                 break;
2936         case MSR_IA32_VMX_VMCS_ENUM:
2937                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2938                 break;
2939         case MSR_IA32_VMX_PROCBASED_CTLS2:
2940                 *pdata = vmx_control_msr(
2941                         vmx->nested.nested_vmx_secondary_ctls_low,
2942                         vmx->nested.nested_vmx_secondary_ctls_high);
2943                 break;
2944         case MSR_IA32_VMX_EPT_VPID_CAP:
2945                 *pdata = vmx->nested.nested_vmx_ept_caps |
2946                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2947                 break;
2948         default:
2949                 return 1;
2950         }
2951
2952         return 0;
2953 }
2954
2955 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
2956                                                  uint64_t val)
2957 {
2958         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
2959
2960         return !(val & ~valid_bits);
2961 }
2962
2963 /*
2964  * Reads an msr value (of 'msr_index') into 'pdata'.
2965  * Returns 0 on success, non-0 otherwise.
2966  * Assumes vcpu_load() was already called.
2967  */
2968 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2969 {
2970         struct shared_msr_entry *msr;
2971
2972         switch (msr_info->index) {
2973 #ifdef CONFIG_X86_64
2974         case MSR_FS_BASE:
2975                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2976                 break;
2977         case MSR_GS_BASE:
2978                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2979                 break;
2980         case MSR_KERNEL_GS_BASE:
2981                 vmx_load_host_state(to_vmx(vcpu));
2982                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2983                 break;
2984 #endif
2985         case MSR_EFER:
2986                 return kvm_get_msr_common(vcpu, msr_info);
2987         case MSR_IA32_TSC:
2988                 msr_info->data = guest_read_tsc(vcpu);
2989                 break;
2990         case MSR_IA32_SYSENTER_CS:
2991                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2992                 break;
2993         case MSR_IA32_SYSENTER_EIP:
2994                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2995                 break;
2996         case MSR_IA32_SYSENTER_ESP:
2997                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2998                 break;
2999         case MSR_IA32_BNDCFGS:
3000                 if (!kvm_mpx_supported())
3001                         return 1;
3002                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3003                 break;
3004         case MSR_IA32_MCG_EXT_CTL:
3005                 if (!msr_info->host_initiated &&
3006                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3007                       FEATURE_CONTROL_LMCE))
3008                         return 1;
3009                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3010                 break;
3011         case MSR_IA32_FEATURE_CONTROL:
3012                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3013                 break;
3014         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3015                 if (!nested_vmx_allowed(vcpu))
3016                         return 1;
3017                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3018         case MSR_IA32_XSS:
3019                 if (!vmx_xsaves_supported())
3020                         return 1;
3021                 msr_info->data = vcpu->arch.ia32_xss;
3022                 break;
3023         case MSR_TSC_AUX:
3024                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3025                         return 1;
3026                 /* Otherwise falls through */
3027         default:
3028                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3029                 if (msr) {
3030                         msr_info->data = msr->data;
3031                         break;
3032                 }
3033                 return kvm_get_msr_common(vcpu, msr_info);
3034         }
3035
3036         return 0;
3037 }
3038
3039 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3040
3041 /*
3042  * Writes msr value into into the appropriate "register".
3043  * Returns 0 on success, non-0 otherwise.
3044  * Assumes vcpu_load() was already called.
3045  */
3046 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3047 {
3048         struct vcpu_vmx *vmx = to_vmx(vcpu);
3049         struct shared_msr_entry *msr;
3050         int ret = 0;
3051         u32 msr_index = msr_info->index;
3052         u64 data = msr_info->data;
3053
3054         switch (msr_index) {
3055         case MSR_EFER:
3056                 ret = kvm_set_msr_common(vcpu, msr_info);
3057                 break;
3058 #ifdef CONFIG_X86_64
3059         case MSR_FS_BASE:
3060                 vmx_segment_cache_clear(vmx);
3061                 vmcs_writel(GUEST_FS_BASE, data);
3062                 break;
3063         case MSR_GS_BASE:
3064                 vmx_segment_cache_clear(vmx);
3065                 vmcs_writel(GUEST_GS_BASE, data);
3066                 break;
3067         case MSR_KERNEL_GS_BASE:
3068                 vmx_load_host_state(vmx);
3069                 vmx->msr_guest_kernel_gs_base = data;
3070                 break;
3071 #endif
3072         case MSR_IA32_SYSENTER_CS:
3073                 vmcs_write32(GUEST_SYSENTER_CS, data);
3074                 break;
3075         case MSR_IA32_SYSENTER_EIP:
3076                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3077                 break;
3078         case MSR_IA32_SYSENTER_ESP:
3079                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3080                 break;
3081         case MSR_IA32_BNDCFGS:
3082                 if (!kvm_mpx_supported())
3083                         return 1;
3084                 vmcs_write64(GUEST_BNDCFGS, data);
3085                 break;
3086         case MSR_IA32_TSC:
3087                 kvm_write_tsc(vcpu, msr_info);
3088                 break;
3089         case MSR_IA32_CR_PAT:
3090                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3091                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3092                                 return 1;
3093                         vmcs_write64(GUEST_IA32_PAT, data);
3094                         vcpu->arch.pat = data;
3095                         break;
3096                 }
3097                 ret = kvm_set_msr_common(vcpu, msr_info);
3098                 break;
3099         case MSR_IA32_TSC_ADJUST:
3100                 ret = kvm_set_msr_common(vcpu, msr_info);
3101                 break;
3102         case MSR_IA32_MCG_EXT_CTL:
3103                 if ((!msr_info->host_initiated &&
3104                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3105                        FEATURE_CONTROL_LMCE)) ||
3106                     (data & ~MCG_EXT_CTL_LMCE_EN))
3107                         return 1;
3108                 vcpu->arch.mcg_ext_ctl = data;
3109                 break;
3110         case MSR_IA32_FEATURE_CONTROL:
3111                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3112                     (to_vmx(vcpu)->msr_ia32_feature_control &
3113                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3114                         return 1;
3115                 vmx->msr_ia32_feature_control = data;
3116                 if (msr_info->host_initiated && data == 0)
3117                         vmx_leave_nested(vcpu);
3118                 break;
3119         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3120                 return 1; /* they are read-only */
3121         case MSR_IA32_XSS:
3122                 if (!vmx_xsaves_supported())
3123                         return 1;
3124                 /*
3125                  * The only supported bit as of Skylake is bit 8, but
3126                  * it is not supported on KVM.
3127                  */
3128                 if (data != 0)
3129                         return 1;
3130                 vcpu->arch.ia32_xss = data;
3131                 if (vcpu->arch.ia32_xss != host_xss)
3132                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3133                                 vcpu->arch.ia32_xss, host_xss);
3134                 else
3135                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3136                 break;
3137         case MSR_TSC_AUX:
3138                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3139                         return 1;
3140                 /* Check reserved bit, higher 32 bits should be zero */
3141                 if ((data >> 32) != 0)
3142                         return 1;
3143                 /* Otherwise falls through */
3144         default:
3145                 msr = find_msr_entry(vmx, msr_index);
3146                 if (msr) {
3147                         u64 old_msr_data = msr->data;
3148                         msr->data = data;
3149                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3150                                 preempt_disable();
3151                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3152                                                          msr->mask);
3153                                 preempt_enable();
3154                                 if (ret)
3155                                         msr->data = old_msr_data;
3156                         }
3157                         break;
3158                 }
3159                 ret = kvm_set_msr_common(vcpu, msr_info);
3160         }
3161
3162         return ret;
3163 }
3164
3165 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3166 {
3167         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3168         switch (reg) {
3169         case VCPU_REGS_RSP:
3170                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3171                 break;
3172         case VCPU_REGS_RIP:
3173                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3174                 break;
3175         case VCPU_EXREG_PDPTR:
3176                 if (enable_ept)
3177                         ept_save_pdptrs(vcpu);
3178                 break;
3179         default:
3180                 break;
3181         }
3182 }
3183
3184 static __init int cpu_has_kvm_support(void)
3185 {
3186         return cpu_has_vmx();
3187 }
3188
3189 static __init int vmx_disabled_by_bios(void)
3190 {
3191         u64 msr;
3192
3193         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3194         if (msr & FEATURE_CONTROL_LOCKED) {
3195                 /* launched w/ TXT and VMX disabled */
3196                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3197                         && tboot_enabled())
3198                         return 1;
3199                 /* launched w/o TXT and VMX only enabled w/ TXT */
3200                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3201                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3202                         && !tboot_enabled()) {
3203                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3204                                 "activate TXT before enabling KVM\n");
3205                         return 1;
3206                 }
3207                 /* launched w/o TXT and VMX disabled */
3208                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3209                         && !tboot_enabled())
3210                         return 1;
3211         }
3212
3213         return 0;
3214 }
3215
3216 static void kvm_cpu_vmxon(u64 addr)
3217 {
3218         intel_pt_handle_vmx(1);
3219
3220         asm volatile (ASM_VMX_VMXON_RAX
3221                         : : "a"(&addr), "m"(addr)
3222                         : "memory", "cc");
3223 }
3224
3225 static int hardware_enable(void)
3226 {
3227         int cpu = raw_smp_processor_id();
3228         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3229         u64 old, test_bits;
3230
3231         if (cr4_read_shadow() & X86_CR4_VMXE)
3232                 return -EBUSY;
3233
3234         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3235         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3236         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3237
3238         /*
3239          * Now we can enable the vmclear operation in kdump
3240          * since the loaded_vmcss_on_cpu list on this cpu
3241          * has been initialized.
3242          *
3243          * Though the cpu is not in VMX operation now, there
3244          * is no problem to enable the vmclear operation
3245          * for the loaded_vmcss_on_cpu list is empty!
3246          */
3247         crash_enable_local_vmclear(cpu);
3248
3249         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3250
3251         test_bits = FEATURE_CONTROL_LOCKED;
3252         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3253         if (tboot_enabled())
3254                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3255
3256         if ((old & test_bits) != test_bits) {
3257                 /* enable and lock */
3258                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3259         }
3260         cr4_set_bits(X86_CR4_VMXE);
3261
3262         if (vmm_exclusive) {
3263                 kvm_cpu_vmxon(phys_addr);
3264                 ept_sync_global();
3265         }
3266
3267         native_store_gdt(this_cpu_ptr(&host_gdt));
3268
3269         return 0;
3270 }
3271
3272 static void vmclear_local_loaded_vmcss(void)
3273 {
3274         int cpu = raw_smp_processor_id();
3275         struct loaded_vmcs *v, *n;
3276
3277         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3278                                  loaded_vmcss_on_cpu_link)
3279                 __loaded_vmcs_clear(v);
3280 }
3281
3282
3283 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3284  * tricks.
3285  */
3286 static void kvm_cpu_vmxoff(void)
3287 {
3288         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3289
3290         intel_pt_handle_vmx(0);
3291 }
3292
3293 static void hardware_disable(void)
3294 {
3295         if (vmm_exclusive) {
3296                 vmclear_local_loaded_vmcss();
3297                 kvm_cpu_vmxoff();
3298         }
3299         cr4_clear_bits(X86_CR4_VMXE);
3300 }
3301
3302 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3303                                       u32 msr, u32 *result)
3304 {
3305         u32 vmx_msr_low, vmx_msr_high;
3306         u32 ctl = ctl_min | ctl_opt;
3307
3308         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3309
3310         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3311         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3312
3313         /* Ensure minimum (required) set of control bits are supported. */
3314         if (ctl_min & ~ctl)
3315                 return -EIO;
3316
3317         *result = ctl;
3318         return 0;
3319 }
3320
3321 static __init bool allow_1_setting(u32 msr, u32 ctl)
3322 {
3323         u32 vmx_msr_low, vmx_msr_high;
3324
3325         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3326         return vmx_msr_high & ctl;
3327 }
3328
3329 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3330 {
3331         u32 vmx_msr_low, vmx_msr_high;
3332         u32 min, opt, min2, opt2;
3333         u32 _pin_based_exec_control = 0;
3334         u32 _cpu_based_exec_control = 0;
3335         u32 _cpu_based_2nd_exec_control = 0;
3336         u32 _vmexit_control = 0;
3337         u32 _vmentry_control = 0;
3338
3339         min = CPU_BASED_HLT_EXITING |
3340 #ifdef CONFIG_X86_64
3341               CPU_BASED_CR8_LOAD_EXITING |
3342               CPU_BASED_CR8_STORE_EXITING |
3343 #endif
3344               CPU_BASED_CR3_LOAD_EXITING |
3345               CPU_BASED_CR3_STORE_EXITING |
3346               CPU_BASED_USE_IO_BITMAPS |
3347               CPU_BASED_MOV_DR_EXITING |
3348               CPU_BASED_USE_TSC_OFFSETING |
3349               CPU_BASED_MWAIT_EXITING |
3350               CPU_BASED_MONITOR_EXITING |
3351               CPU_BASED_INVLPG_EXITING |
3352               CPU_BASED_RDPMC_EXITING;
3353
3354         opt = CPU_BASED_TPR_SHADOW |
3355               CPU_BASED_USE_MSR_BITMAPS |
3356               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3357         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3358                                 &_cpu_based_exec_control) < 0)
3359                 return -EIO;
3360 #ifdef CONFIG_X86_64
3361         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3362                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3363                                            ~CPU_BASED_CR8_STORE_EXITING;
3364 #endif
3365         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3366                 min2 = 0;
3367                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3368                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3369                         SECONDARY_EXEC_WBINVD_EXITING |
3370                         SECONDARY_EXEC_ENABLE_VPID |
3371                         SECONDARY_EXEC_ENABLE_EPT |
3372                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3373                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3374                         SECONDARY_EXEC_RDTSCP |
3375                         SECONDARY_EXEC_ENABLE_INVPCID |
3376                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3377                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3378                         SECONDARY_EXEC_SHADOW_VMCS |
3379                         SECONDARY_EXEC_XSAVES |
3380                         SECONDARY_EXEC_ENABLE_PML |
3381                         SECONDARY_EXEC_TSC_SCALING;
3382                 if (adjust_vmx_controls(min2, opt2,
3383                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3384                                         &_cpu_based_2nd_exec_control) < 0)
3385                         return -EIO;
3386         }
3387 #ifndef CONFIG_X86_64
3388         if (!(_cpu_based_2nd_exec_control &
3389                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3390                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3391 #endif
3392
3393         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3394                 _cpu_based_2nd_exec_control &= ~(
3395                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3396                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3397                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3398
3399         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3400                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3401                    enabled */
3402                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3403                                              CPU_BASED_CR3_STORE_EXITING |
3404                                              CPU_BASED_INVLPG_EXITING);
3405                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3406                       vmx_capability.ept, vmx_capability.vpid);
3407         }
3408
3409         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3410 #ifdef CONFIG_X86_64
3411         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3412 #endif
3413         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3414                 VM_EXIT_CLEAR_BNDCFGS;
3415         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3416                                 &_vmexit_control) < 0)
3417                 return -EIO;
3418
3419         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3420         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3421                  PIN_BASED_VMX_PREEMPTION_TIMER;
3422         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3423                                 &_pin_based_exec_control) < 0)
3424                 return -EIO;
3425
3426         if (cpu_has_broken_vmx_preemption_timer())
3427                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3428         if (!(_cpu_based_2nd_exec_control &
3429                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3430                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3431
3432         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3433         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3434         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3435                                 &_vmentry_control) < 0)
3436                 return -EIO;
3437
3438         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3439
3440         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3441         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3442                 return -EIO;
3443
3444 #ifdef CONFIG_X86_64
3445         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3446         if (vmx_msr_high & (1u<<16))
3447                 return -EIO;
3448 #endif
3449
3450         /* Require Write-Back (WB) memory type for VMCS accesses. */
3451         if (((vmx_msr_high >> 18) & 15) != 6)
3452                 return -EIO;
3453
3454         vmcs_conf->size = vmx_msr_high & 0x1fff;
3455         vmcs_conf->order = get_order(vmcs_config.size);
3456         vmcs_conf->revision_id = vmx_msr_low;
3457
3458         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3459         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3460         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3461         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3462         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3463
3464         cpu_has_load_ia32_efer =
3465                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3466                                 VM_ENTRY_LOAD_IA32_EFER)
3467                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3468                                    VM_EXIT_LOAD_IA32_EFER);
3469
3470         cpu_has_load_perf_global_ctrl =
3471                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3472                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3473                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3474                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3475
3476         /*
3477          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3478          * but due to errata below it can't be used. Workaround is to use
3479          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3480          *
3481          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3482          *
3483          * AAK155             (model 26)
3484          * AAP115             (model 30)
3485          * AAT100             (model 37)
3486          * BC86,AAY89,BD102   (model 44)
3487          * BA97               (model 46)
3488          *
3489          */
3490         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3491                 switch (boot_cpu_data.x86_model) {
3492                 case 26:
3493                 case 30:
3494                 case 37:
3495                 case 44:
3496                 case 46:
3497                         cpu_has_load_perf_global_ctrl = false;
3498                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3499                                         "does not work properly. Using workaround\n");
3500                         break;
3501                 default:
3502                         break;
3503                 }
3504         }
3505
3506         if (boot_cpu_has(X86_FEATURE_XSAVES))
3507                 rdmsrl(MSR_IA32_XSS, host_xss);
3508
3509         return 0;
3510 }
3511
3512 static struct vmcs *alloc_vmcs_cpu(int cpu)
3513 {
3514         int node = cpu_to_node(cpu);
3515         struct page *pages;
3516         struct vmcs *vmcs;
3517
3518         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3519         if (!pages)
3520                 return NULL;
3521         vmcs = page_address(pages);
3522         memset(vmcs, 0, vmcs_config.size);
3523         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3524         return vmcs;
3525 }
3526
3527 static struct vmcs *alloc_vmcs(void)
3528 {
3529         return alloc_vmcs_cpu(raw_smp_processor_id());
3530 }
3531
3532 static void free_vmcs(struct vmcs *vmcs)
3533 {
3534         free_pages((unsigned long)vmcs, vmcs_config.order);
3535 }
3536
3537 /*
3538  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3539  */
3540 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3541 {
3542         if (!loaded_vmcs->vmcs)
3543                 return;
3544         loaded_vmcs_clear(loaded_vmcs);
3545         free_vmcs(loaded_vmcs->vmcs);
3546         loaded_vmcs->vmcs = NULL;
3547 }
3548
3549 static void free_kvm_area(void)
3550 {
3551         int cpu;
3552
3553         for_each_possible_cpu(cpu) {
3554                 free_vmcs(per_cpu(vmxarea, cpu));
3555                 per_cpu(vmxarea, cpu) = NULL;
3556         }
3557 }
3558
3559 static void init_vmcs_shadow_fields(void)
3560 {
3561         int i, j;
3562
3563         /* No checks for read only fields yet */
3564
3565         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3566                 switch (shadow_read_write_fields[i]) {
3567                 case GUEST_BNDCFGS:
3568                         if (!kvm_mpx_supported())
3569                                 continue;
3570                         break;
3571                 default:
3572                         break;
3573                 }
3574
3575                 if (j < i)
3576                         shadow_read_write_fields[j] =
3577                                 shadow_read_write_fields[i];
3578                 j++;
3579         }
3580         max_shadow_read_write_fields = j;
3581
3582         /* shadowed fields guest access without vmexit */
3583         for (i = 0; i < max_shadow_read_write_fields; i++) {
3584                 clear_bit(shadow_read_write_fields[i],
3585                           vmx_vmwrite_bitmap);
3586                 clear_bit(shadow_read_write_fields[i],
3587                           vmx_vmread_bitmap);
3588         }
3589         for (i = 0; i < max_shadow_read_only_fields; i++)
3590                 clear_bit(shadow_read_only_fields[i],
3591                           vmx_vmread_bitmap);
3592 }
3593
3594 static __init int alloc_kvm_area(void)
3595 {
3596         int cpu;
3597
3598         for_each_possible_cpu(cpu) {
3599                 struct vmcs *vmcs;
3600
3601                 vmcs = alloc_vmcs_cpu(cpu);
3602                 if (!vmcs) {
3603                         free_kvm_area();
3604                         return -ENOMEM;
3605                 }
3606
3607                 per_cpu(vmxarea, cpu) = vmcs;
3608         }
3609         return 0;
3610 }
3611
3612 static bool emulation_required(struct kvm_vcpu *vcpu)
3613 {
3614         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3615 }
3616
3617 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3618                 struct kvm_segment *save)
3619 {
3620         if (!emulate_invalid_guest_state) {
3621                 /*
3622                  * CS and SS RPL should be equal during guest entry according
3623                  * to VMX spec, but in reality it is not always so. Since vcpu
3624                  * is in the middle of the transition from real mode to
3625                  * protected mode it is safe to assume that RPL 0 is a good
3626                  * default value.
3627                  */
3628                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3629                         save->selector &= ~SEGMENT_RPL_MASK;
3630                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3631                 save->s = 1;
3632         }
3633         vmx_set_segment(vcpu, save, seg);
3634 }
3635
3636 static void enter_pmode(struct kvm_vcpu *vcpu)
3637 {
3638         unsigned long flags;
3639         struct vcpu_vmx *vmx = to_vmx(vcpu);
3640
3641         /*
3642          * Update real mode segment cache. It may be not up-to-date if sement
3643          * register was written while vcpu was in a guest mode.
3644          */
3645         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3646         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3647         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3648         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3649         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3650         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3651
3652         vmx->rmode.vm86_active = 0;
3653
3654         vmx_segment_cache_clear(vmx);
3655
3656         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3657
3658         flags = vmcs_readl(GUEST_RFLAGS);
3659         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3660         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3661         vmcs_writel(GUEST_RFLAGS, flags);
3662
3663         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3664                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3665
3666         update_exception_bitmap(vcpu);
3667
3668         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3669         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3670         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3671         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3672         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3673         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3674 }
3675
3676 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3677 {
3678         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3679         struct kvm_segment var = *save;
3680
3681         var.dpl = 0x3;
3682         if (seg == VCPU_SREG_CS)
3683                 var.type = 0x3;
3684
3685         if (!emulate_invalid_guest_state) {
3686                 var.selector = var.base >> 4;
3687                 var.base = var.base & 0xffff0;
3688                 var.limit = 0xffff;
3689                 var.g = 0;
3690                 var.db = 0;
3691                 var.present = 1;
3692                 var.s = 1;
3693                 var.l = 0;
3694                 var.unusable = 0;
3695                 var.type = 0x3;
3696                 var.avl = 0;
3697                 if (save->base & 0xf)
3698                         printk_once(KERN_WARNING "kvm: segment base is not "
3699                                         "paragraph aligned when entering "
3700                                         "protected mode (seg=%d)", seg);
3701         }
3702
3703         vmcs_write16(sf->selector, var.selector);
3704         vmcs_write32(sf->base, var.base);
3705         vmcs_write32(sf->limit, var.limit);
3706         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3707 }
3708
3709 static void enter_rmode(struct kvm_vcpu *vcpu)
3710 {
3711         unsigned long flags;
3712         struct vcpu_vmx *vmx = to_vmx(vcpu);
3713
3714         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3715         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3716         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3717         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3718         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3719         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3720         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3721
3722         vmx->rmode.vm86_active = 1;
3723
3724         /*
3725          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3726          * vcpu. Warn the user that an update is overdue.
3727          */
3728         if (!vcpu->kvm->arch.tss_addr)
3729                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3730                              "called before entering vcpu\n");
3731
3732         vmx_segment_cache_clear(vmx);
3733
3734         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3735         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3736         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3737
3738         flags = vmcs_readl(GUEST_RFLAGS);
3739         vmx->rmode.save_rflags = flags;
3740
3741         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3742
3743         vmcs_writel(GUEST_RFLAGS, flags);
3744         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3745         update_exception_bitmap(vcpu);
3746
3747         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3748         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3749         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3750         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3751         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3752         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3753
3754         kvm_mmu_reset_context(vcpu);
3755 }
3756
3757 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3758 {
3759         struct vcpu_vmx *vmx = to_vmx(vcpu);
3760         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3761
3762         if (!msr)
3763                 return;
3764
3765         /*
3766          * Force kernel_gs_base reloading before EFER changes, as control
3767          * of this msr depends on is_long_mode().
3768          */
3769         vmx_load_host_state(to_vmx(vcpu));
3770         vcpu->arch.efer = efer;
3771         if (efer & EFER_LMA) {
3772                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3773                 msr->data = efer;
3774         } else {
3775                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3776
3777                 msr->data = efer & ~EFER_LME;
3778         }
3779         setup_msrs(vmx);
3780 }
3781
3782 #ifdef CONFIG_X86_64
3783
3784 static void enter_lmode(struct kvm_vcpu *vcpu)
3785 {
3786         u32 guest_tr_ar;
3787
3788         vmx_segment_cache_clear(to_vmx(vcpu));
3789
3790         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3791         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3792                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3793                                      __func__);
3794                 vmcs_write32(GUEST_TR_AR_BYTES,
3795                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3796                              | VMX_AR_TYPE_BUSY_64_TSS);
3797         }
3798         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3799 }
3800
3801 static void exit_lmode(struct kvm_vcpu *vcpu)
3802 {
3803         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3804         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3805 }
3806
3807 #endif
3808
3809 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3810 {
3811         vpid_sync_context(vpid);
3812         if (enable_ept) {
3813                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3814                         return;
3815                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3816         }
3817 }
3818
3819 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3820 {
3821         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3822 }
3823
3824 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3825 {
3826         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3827
3828         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3829         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3830 }
3831
3832 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3833 {
3834         if (enable_ept && is_paging(vcpu))
3835                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3836         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3837 }
3838
3839 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3840 {
3841         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3842
3843         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3844         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3845 }
3846
3847 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3848 {
3849         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3850
3851         if (!test_bit(VCPU_EXREG_PDPTR,
3852                       (unsigned long *)&vcpu->arch.regs_dirty))
3853                 return;
3854
3855         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3856                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3857                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3858                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3859                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3860         }
3861 }
3862
3863 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3864 {
3865         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3866
3867         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3868                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3869                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3870                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3871                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3872         }
3873
3874         __set_bit(VCPU_EXREG_PDPTR,
3875                   (unsigned long *)&vcpu->arch.regs_avail);
3876         __set_bit(VCPU_EXREG_PDPTR,
3877                   (unsigned long *)&vcpu->arch.regs_dirty);
3878 }
3879
3880 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3881
3882 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3883                                         unsigned long cr0,
3884                                         struct kvm_vcpu *vcpu)
3885 {
3886         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3887                 vmx_decache_cr3(vcpu);
3888         if (!(cr0 & X86_CR0_PG)) {
3889                 /* From paging/starting to nonpaging */
3890                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3891                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3892                              (CPU_BASED_CR3_LOAD_EXITING |
3893                               CPU_BASED_CR3_STORE_EXITING));
3894                 vcpu->arch.cr0 = cr0;
3895                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3896         } else if (!is_paging(vcpu)) {
3897                 /* From nonpaging to paging */
3898                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3899                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3900                              ~(CPU_BASED_CR3_LOAD_EXITING |
3901                                CPU_BASED_CR3_STORE_EXITING));
3902                 vcpu->arch.cr0 = cr0;
3903                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3904         }
3905
3906         if (!(cr0 & X86_CR0_WP))
3907                 *hw_cr0 &= ~X86_CR0_WP;
3908 }
3909
3910 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3911 {
3912         struct vcpu_vmx *vmx = to_vmx(vcpu);
3913         unsigned long hw_cr0;
3914
3915         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3916         if (enable_unrestricted_guest)
3917                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3918         else {
3919                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3920
3921                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3922                         enter_pmode(vcpu);
3923
3924                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3925                         enter_rmode(vcpu);
3926         }
3927
3928 #ifdef CONFIG_X86_64
3929         if (vcpu->arch.efer & EFER_LME) {
3930                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3931                         enter_lmode(vcpu);
3932                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3933                         exit_lmode(vcpu);
3934         }
3935 #endif
3936
3937         if (enable_ept)
3938                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3939
3940         if (!vcpu->fpu_active)
3941                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3942
3943         vmcs_writel(CR0_READ_SHADOW, cr0);
3944         vmcs_writel(GUEST_CR0, hw_cr0);
3945         vcpu->arch.cr0 = cr0;
3946
3947         /* depends on vcpu->arch.cr0 to be set to a new value */
3948         vmx->emulation_required = emulation_required(vcpu);
3949 }
3950
3951 static u64 construct_eptp(unsigned long root_hpa)
3952 {
3953         u64 eptp;
3954
3955         /* TODO write the value reading from MSR */
3956         eptp = VMX_EPT_DEFAULT_MT |
3957                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3958         if (enable_ept_ad_bits)
3959                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3960         eptp |= (root_hpa & PAGE_MASK);
3961
3962         return eptp;
3963 }
3964
3965 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3966 {
3967         unsigned long guest_cr3;
3968         u64 eptp;
3969
3970         guest_cr3 = cr3;
3971         if (enable_ept) {
3972                 eptp = construct_eptp(cr3);
3973                 vmcs_write64(EPT_POINTER, eptp);
3974                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3975                         guest_cr3 = kvm_read_cr3(vcpu);
3976                 else
3977                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3978                 ept_load_pdptrs(vcpu);
3979         }
3980
3981         vmx_flush_tlb(vcpu);
3982         vmcs_writel(GUEST_CR3, guest_cr3);
3983 }
3984
3985 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3986 {
3987         /*
3988          * Pass through host's Machine Check Enable value to hw_cr4, which
3989          * is in force while we are in guest mode.  Do not let guests control
3990          * this bit, even if host CR4.MCE == 0.
3991          */
3992         unsigned long hw_cr4 =
3993                 (cr4_read_shadow() & X86_CR4_MCE) |
3994                 (cr4 & ~X86_CR4_MCE) |
3995                 (to_vmx(vcpu)->rmode.vm86_active ?
3996                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3997
3998         if (cr4 & X86_CR4_VMXE) {
3999                 /*
4000                  * To use VMXON (and later other VMX instructions), a guest
4001                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4002                  * So basically the check on whether to allow nested VMX
4003                  * is here.
4004                  */
4005                 if (!nested_vmx_allowed(vcpu))
4006                         return 1;
4007         }
4008         if (to_vmx(vcpu)->nested.vmxon &&
4009             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
4010                 return 1;
4011
4012         vcpu->arch.cr4 = cr4;
4013         if (enable_ept) {
4014                 if (!is_paging(vcpu)) {
4015                         hw_cr4 &= ~X86_CR4_PAE;
4016                         hw_cr4 |= X86_CR4_PSE;
4017                 } else if (!(cr4 & X86_CR4_PAE)) {
4018                         hw_cr4 &= ~X86_CR4_PAE;
4019                 }
4020         }
4021
4022         if (!enable_unrestricted_guest && !is_paging(vcpu))
4023                 /*
4024                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4025                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4026                  * to be manually disabled when guest switches to non-paging
4027                  * mode.
4028                  *
4029                  * If !enable_unrestricted_guest, the CPU is always running
4030                  * with CR0.PG=1 and CR4 needs to be modified.
4031                  * If enable_unrestricted_guest, the CPU automatically
4032                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4033                  */
4034                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4035
4036         vmcs_writel(CR4_READ_SHADOW, cr4);
4037         vmcs_writel(GUEST_CR4, hw_cr4);
4038         return 0;
4039 }
4040
4041 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4042                             struct kvm_segment *var, int seg)
4043 {
4044         struct vcpu_vmx *vmx = to_vmx(vcpu);
4045         u32 ar;
4046
4047         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4048                 *var = vmx->rmode.segs[seg];
4049                 if (seg == VCPU_SREG_TR
4050                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4051                         return;
4052                 var->base = vmx_read_guest_seg_base(vmx, seg);
4053                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4054                 return;
4055         }
4056         var->base = vmx_read_guest_seg_base(vmx, seg);
4057         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4058         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4059         ar = vmx_read_guest_seg_ar(vmx, seg);
4060         var->unusable = (ar >> 16) & 1;
4061         var->type = ar & 15;
4062         var->s = (ar >> 4) & 1;
4063         var->dpl = (ar >> 5) & 3;
4064         /*
4065          * Some userspaces do not preserve unusable property. Since usable
4066          * segment has to be present according to VMX spec we can use present
4067          * property to amend userspace bug by making unusable segment always
4068          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4069          * segment as unusable.
4070          */
4071         var->present = !var->unusable;
4072         var->avl = (ar >> 12) & 1;
4073         var->l = (ar >> 13) & 1;
4074         var->db = (ar >> 14) & 1;
4075         var->g = (ar >> 15) & 1;
4076 }
4077
4078 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4079 {
4080         struct kvm_segment s;
4081
4082         if (to_vmx(vcpu)->rmode.vm86_active) {
4083                 vmx_get_segment(vcpu, &s, seg);
4084                 return s.base;
4085         }
4086         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4087 }
4088
4089 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4090 {
4091         struct vcpu_vmx *vmx = to_vmx(vcpu);
4092
4093         if (unlikely(vmx->rmode.vm86_active))
4094                 return 0;
4095         else {
4096                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4097                 return VMX_AR_DPL(ar);
4098         }
4099 }
4100
4101 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4102 {
4103         u32 ar;
4104
4105         if (var->unusable || !var->present)
4106                 ar = 1 << 16;
4107         else {
4108                 ar = var->type & 15;
4109                 ar |= (var->s & 1) << 4;
4110                 ar |= (var->dpl & 3) << 5;
4111                 ar |= (var->present & 1) << 7;
4112                 ar |= (var->avl & 1) << 12;
4113                 ar |= (var->l & 1) << 13;
4114                 ar |= (var->db & 1) << 14;
4115                 ar |= (var->g & 1) << 15;
4116         }
4117
4118         return ar;
4119 }
4120
4121 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4122                             struct kvm_segment *var, int seg)
4123 {
4124         struct vcpu_vmx *vmx = to_vmx(vcpu);
4125         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4126
4127         vmx_segment_cache_clear(vmx);
4128
4129         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4130                 vmx->rmode.segs[seg] = *var;
4131                 if (seg == VCPU_SREG_TR)
4132                         vmcs_write16(sf->selector, var->selector);
4133                 else if (var->s)
4134                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4135                 goto out;
4136         }
4137
4138         vmcs_writel(sf->base, var->base);
4139         vmcs_write32(sf->limit, var->limit);
4140         vmcs_write16(sf->selector, var->selector);
4141
4142         /*
4143          *   Fix the "Accessed" bit in AR field of segment registers for older
4144          * qemu binaries.
4145          *   IA32 arch specifies that at the time of processor reset the
4146          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4147          * is setting it to 0 in the userland code. This causes invalid guest
4148          * state vmexit when "unrestricted guest" mode is turned on.
4149          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4150          * tree. Newer qemu binaries with that qemu fix would not need this
4151          * kvm hack.
4152          */
4153         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4154                 var->type |= 0x1; /* Accessed */
4155
4156         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4157
4158 out:
4159         vmx->emulation_required = emulation_required(vcpu);
4160 }
4161
4162 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4163 {
4164         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4165
4166         *db = (ar >> 14) & 1;
4167         *l = (ar >> 13) & 1;
4168 }
4169
4170 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4171 {
4172         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4173         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4174 }
4175
4176 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4177 {
4178         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4179         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4180 }
4181
4182 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4183 {
4184         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4185         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4186 }
4187
4188 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4189 {
4190         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4191         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4192 }
4193
4194 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4195 {
4196         struct kvm_segment var;
4197         u32 ar;
4198
4199         vmx_get_segment(vcpu, &var, seg);
4200         var.dpl = 0x3;
4201         if (seg == VCPU_SREG_CS)
4202                 var.type = 0x3;
4203         ar = vmx_segment_access_rights(&var);
4204
4205         if (var.base != (var.selector << 4))
4206                 return false;
4207         if (var.limit != 0xffff)
4208                 return false;
4209         if (ar != 0xf3)
4210                 return false;
4211
4212         return true;
4213 }
4214
4215 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4216 {
4217         struct kvm_segment cs;
4218         unsigned int cs_rpl;
4219
4220         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4221         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4222
4223         if (cs.unusable)
4224                 return false;
4225         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4226                 return false;
4227         if (!cs.s)
4228                 return false;
4229         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4230                 if (cs.dpl > cs_rpl)
4231                         return false;
4232         } else {
4233                 if (cs.dpl != cs_rpl)
4234                         return false;
4235         }
4236         if (!cs.present)
4237                 return false;
4238
4239         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4240         return true;
4241 }
4242
4243 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4244 {
4245         struct kvm_segment ss;
4246         unsigned int ss_rpl;
4247
4248         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4249         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4250
4251         if (ss.unusable)
4252                 return true;
4253         if (ss.type != 3 && ss.type != 7)
4254                 return false;
4255         if (!ss.s)
4256                 return false;
4257         if (ss.dpl != ss_rpl) /* DPL != RPL */
4258                 return false;
4259         if (!ss.present)
4260                 return false;
4261
4262         return true;
4263 }
4264
4265 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4266 {
4267         struct kvm_segment var;
4268         unsigned int rpl;
4269
4270         vmx_get_segment(vcpu, &var, seg);
4271         rpl = var.selector & SEGMENT_RPL_MASK;
4272
4273         if (var.unusable)
4274                 return true;
4275         if (!var.s)
4276                 return false;
4277         if (!var.present)
4278                 return false;
4279         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4280                 if (var.dpl < rpl) /* DPL < RPL */
4281                         return false;
4282         }
4283
4284         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4285          * rights flags
4286          */
4287         return true;
4288 }
4289
4290 static bool tr_valid(struct kvm_vcpu *vcpu)
4291 {
4292         struct kvm_segment tr;
4293
4294         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4295
4296         if (tr.unusable)
4297                 return false;
4298         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4299                 return false;
4300         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4301                 return false;
4302         if (!tr.present)
4303                 return false;
4304
4305         return true;
4306 }
4307
4308 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4309 {
4310         struct kvm_segment ldtr;
4311
4312         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4313
4314         if (ldtr.unusable)
4315                 return true;
4316         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4317                 return false;
4318         if (ldtr.type != 2)
4319                 return false;
4320         if (!ldtr.present)
4321                 return false;
4322
4323         return true;
4324 }
4325
4326 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4327 {
4328         struct kvm_segment cs, ss;
4329
4330         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4331         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4332
4333         return ((cs.selector & SEGMENT_RPL_MASK) ==
4334                  (ss.selector & SEGMENT_RPL_MASK));
4335 }
4336
4337 /*
4338  * Check if guest state is valid. Returns true if valid, false if
4339  * not.
4340  * We assume that registers are always usable
4341  */
4342 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4343 {
4344         if (enable_unrestricted_guest)
4345                 return true;
4346
4347         /* real mode guest state checks */
4348         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4349                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4350                         return false;
4351                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4352                         return false;
4353                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4354                         return false;
4355                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4356                         return false;
4357                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4358                         return false;
4359                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4360                         return false;
4361         } else {
4362         /* protected mode guest state checks */
4363                 if (!cs_ss_rpl_check(vcpu))
4364                         return false;
4365                 if (!code_segment_valid(vcpu))
4366                         return false;
4367                 if (!stack_segment_valid(vcpu))
4368                         return false;
4369                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4370                         return false;
4371                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4372                         return false;
4373                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4374                         return false;
4375                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4376                         return false;
4377                 if (!tr_valid(vcpu))
4378                         return false;
4379                 if (!ldtr_valid(vcpu))
4380                         return false;
4381         }
4382         /* TODO:
4383          * - Add checks on RIP
4384          * - Add checks on RFLAGS
4385          */
4386
4387         return true;
4388 }
4389
4390 static int init_rmode_tss(struct kvm *kvm)
4391 {
4392         gfn_t fn;
4393         u16 data = 0;
4394         int idx, r;
4395
4396         idx = srcu_read_lock(&kvm->srcu);
4397         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4398         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4399         if (r < 0)
4400                 goto out;
4401         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4402         r = kvm_write_guest_page(kvm, fn++, &data,
4403                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4404         if (r < 0)
4405                 goto out;
4406         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4407         if (r < 0)
4408                 goto out;
4409         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4410         if (r < 0)
4411                 goto out;
4412         data = ~0;
4413         r = kvm_write_guest_page(kvm, fn, &data,
4414                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4415                                  sizeof(u8));
4416 out:
4417         srcu_read_unlock(&kvm->srcu, idx);
4418         return r;
4419 }
4420
4421 static int init_rmode_identity_map(struct kvm *kvm)
4422 {
4423         int i, idx, r = 0;
4424         kvm_pfn_t identity_map_pfn;
4425         u32 tmp;
4426
4427         if (!enable_ept)
4428                 return 0;
4429
4430         /* Protect kvm->arch.ept_identity_pagetable_done. */
4431         mutex_lock(&kvm->slots_lock);
4432
4433         if (likely(kvm->arch.ept_identity_pagetable_done))
4434                 goto out2;
4435
4436         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4437
4438         r = alloc_identity_pagetable(kvm);
4439         if (r < 0)
4440                 goto out2;
4441
4442         idx = srcu_read_lock(&kvm->srcu);
4443         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4444         if (r < 0)
4445                 goto out;
4446         /* Set up identity-mapping pagetable for EPT in real mode */
4447         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4448                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4449                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4450                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4451                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4452                 if (r < 0)
4453                         goto out;
4454         }
4455         kvm->arch.ept_identity_pagetable_done = true;
4456
4457 out:
4458         srcu_read_unlock(&kvm->srcu, idx);
4459
4460 out2:
4461         mutex_unlock(&kvm->slots_lock);
4462         return r;
4463 }
4464
4465 static void seg_setup(int seg)
4466 {
4467         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4468         unsigned int ar;
4469
4470         vmcs_write16(sf->selector, 0);
4471         vmcs_writel(sf->base, 0);
4472         vmcs_write32(sf->limit, 0xffff);
4473         ar = 0x93;
4474         if (seg == VCPU_SREG_CS)
4475                 ar |= 0x08; /* code segment */
4476
4477         vmcs_write32(sf->ar_bytes, ar);
4478 }
4479
4480 static int alloc_apic_access_page(struct kvm *kvm)
4481 {
4482         struct page *page;
4483         int r = 0;
4484
4485         mutex_lock(&kvm->slots_lock);
4486         if (kvm->arch.apic_access_page_done)
4487                 goto out;
4488         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4489                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4490         if (r)
4491                 goto out;
4492
4493         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4494         if (is_error_page(page)) {
4495                 r = -EFAULT;
4496                 goto out;
4497         }
4498
4499         /*
4500          * Do not pin the page in memory, so that memory hot-unplug
4501          * is able to migrate it.
4502          */
4503         put_page(page);
4504         kvm->arch.apic_access_page_done = true;
4505 out:
4506         mutex_unlock(&kvm->slots_lock);
4507         return r;
4508 }
4509
4510 static int alloc_identity_pagetable(struct kvm *kvm)
4511 {
4512         /* Called with kvm->slots_lock held. */
4513
4514         int r = 0;
4515
4516         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4517
4518         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4519                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4520
4521         return r;
4522 }
4523
4524 static int allocate_vpid(void)
4525 {
4526         int vpid;
4527
4528         if (!enable_vpid)
4529                 return 0;
4530         spin_lock(&vmx_vpid_lock);
4531         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4532         if (vpid < VMX_NR_VPIDS)
4533                 __set_bit(vpid, vmx_vpid_bitmap);
4534         else
4535                 vpid = 0;
4536         spin_unlock(&vmx_vpid_lock);
4537         return vpid;
4538 }
4539
4540 static void free_vpid(int vpid)
4541 {
4542         if (!enable_vpid || vpid == 0)
4543                 return;
4544         spin_lock(&vmx_vpid_lock);
4545         __clear_bit(vpid, vmx_vpid_bitmap);
4546         spin_unlock(&vmx_vpid_lock);
4547 }
4548
4549 #define MSR_TYPE_R      1
4550 #define MSR_TYPE_W      2
4551 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4552                                                 u32 msr, int type)
4553 {
4554         int f = sizeof(unsigned long);
4555
4556         if (!cpu_has_vmx_msr_bitmap())
4557                 return;
4558
4559         /*
4560          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4561          * have the write-low and read-high bitmap offsets the wrong way round.
4562          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4563          */
4564         if (msr <= 0x1fff) {
4565                 if (type & MSR_TYPE_R)
4566                         /* read-low */
4567                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4568
4569                 if (type & MSR_TYPE_W)
4570                         /* write-low */
4571                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4572
4573         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4574                 msr &= 0x1fff;
4575                 if (type & MSR_TYPE_R)
4576                         /* read-high */
4577                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4578
4579                 if (type & MSR_TYPE_W)
4580                         /* write-high */
4581                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4582
4583         }
4584 }
4585
4586 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4587                                                 u32 msr, int type)
4588 {
4589         int f = sizeof(unsigned long);
4590
4591         if (!cpu_has_vmx_msr_bitmap())
4592                 return;
4593
4594         /*
4595          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4596          * have the write-low and read-high bitmap offsets the wrong way round.
4597          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4598          */
4599         if (msr <= 0x1fff) {
4600                 if (type & MSR_TYPE_R)
4601                         /* read-low */
4602                         __set_bit(msr, msr_bitmap + 0x000 / f);
4603
4604                 if (type & MSR_TYPE_W)
4605                         /* write-low */
4606                         __set_bit(msr, msr_bitmap + 0x800 / f);
4607
4608         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4609                 msr &= 0x1fff;
4610                 if (type & MSR_TYPE_R)
4611                         /* read-high */
4612                         __set_bit(msr, msr_bitmap + 0x400 / f);
4613
4614                 if (type & MSR_TYPE_W)
4615                         /* write-high */
4616                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4617
4618         }
4619 }
4620
4621 /*
4622  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4623  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4624  */
4625 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4626                                                unsigned long *msr_bitmap_nested,
4627                                                u32 msr, int type)
4628 {
4629         int f = sizeof(unsigned long);
4630
4631         if (!cpu_has_vmx_msr_bitmap()) {
4632                 WARN_ON(1);
4633                 return;
4634         }
4635
4636         /*
4637          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4638          * have the write-low and read-high bitmap offsets the wrong way round.
4639          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4640          */
4641         if (msr <= 0x1fff) {
4642                 if (type & MSR_TYPE_R &&
4643                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4644                         /* read-low */
4645                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4646
4647                 if (type & MSR_TYPE_W &&
4648                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4649                         /* write-low */
4650                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4651
4652         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4653                 msr &= 0x1fff;
4654                 if (type & MSR_TYPE_R &&
4655                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4656                         /* read-high */
4657                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4658
4659                 if (type & MSR_TYPE_W &&
4660                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4661                         /* write-high */
4662                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4663
4664         }
4665 }
4666
4667 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4668 {
4669         if (!longmode_only)
4670                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4671                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4672         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4673                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4674 }
4675
4676 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4677 {
4678         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4679                         msr, MSR_TYPE_R);
4680         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4681                         msr, MSR_TYPE_R);
4682 }
4683
4684 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4685 {
4686         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4687                         msr, MSR_TYPE_R);
4688         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4689                         msr, MSR_TYPE_R);
4690 }
4691
4692 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4693 {
4694         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4695                         msr, MSR_TYPE_W);
4696         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4697                         msr, MSR_TYPE_W);
4698 }
4699
4700 static bool vmx_get_enable_apicv(void)
4701 {
4702         return enable_apicv;
4703 }
4704
4705 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4706 {
4707         struct vcpu_vmx *vmx = to_vmx(vcpu);
4708         int max_irr;
4709         void *vapic_page;
4710         u16 status;
4711
4712         if (vmx->nested.pi_desc &&
4713             vmx->nested.pi_pending) {
4714                 vmx->nested.pi_pending = false;
4715                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4716                         return 0;
4717
4718                 max_irr = find_last_bit(
4719                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4720
4721                 if (max_irr == 256)
4722                         return 0;
4723
4724                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4725                 if (!vapic_page) {
4726                         WARN_ON(1);
4727                         return -ENOMEM;
4728                 }
4729                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4730                 kunmap(vmx->nested.virtual_apic_page);
4731
4732                 status = vmcs_read16(GUEST_INTR_STATUS);
4733                 if ((u8)max_irr > ((u8)status & 0xff)) {
4734                         status &= ~0xff;
4735                         status |= (u8)max_irr;
4736                         vmcs_write16(GUEST_INTR_STATUS, status);
4737                 }
4738         }
4739         return 0;
4740 }
4741
4742 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4743 {
4744 #ifdef CONFIG_SMP
4745         if (vcpu->mode == IN_GUEST_MODE) {
4746                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4747
4748                 /*
4749                  * Currently, we don't support urgent interrupt,
4750                  * all interrupts are recognized as non-urgent
4751                  * interrupt, so we cannot post interrupts when
4752                  * 'SN' is set.
4753                  *
4754                  * If the vcpu is in guest mode, it means it is
4755                  * running instead of being scheduled out and
4756                  * waiting in the run queue, and that's the only
4757                  * case when 'SN' is set currently, warning if
4758                  * 'SN' is set.
4759                  */
4760                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4761
4762                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4763                                 POSTED_INTR_VECTOR);
4764                 return true;
4765         }
4766 #endif
4767         return false;
4768 }
4769
4770 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4771                                                 int vector)
4772 {
4773         struct vcpu_vmx *vmx = to_vmx(vcpu);
4774
4775         if (is_guest_mode(vcpu) &&
4776             vector == vmx->nested.posted_intr_nv) {
4777                 /* the PIR and ON have been set by L1. */
4778                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4779                 /*
4780                  * If a posted intr is not recognized by hardware,
4781                  * we will accomplish it in the next vmentry.
4782                  */
4783                 vmx->nested.pi_pending = true;
4784                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4785                 return 0;
4786         }
4787         return -1;
4788 }
4789 /*
4790  * Send interrupt to vcpu via posted interrupt way.
4791  * 1. If target vcpu is running(non-root mode), send posted interrupt
4792  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4793  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4794  * interrupt from PIR in next vmentry.
4795  */
4796 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4797 {
4798         struct vcpu_vmx *vmx = to_vmx(vcpu);
4799         int r;
4800
4801         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4802         if (!r)
4803                 return;
4804
4805         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4806                 return;
4807
4808         r = pi_test_and_set_on(&vmx->pi_desc);
4809         kvm_make_request(KVM_REQ_EVENT, vcpu);
4810         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4811                 kvm_vcpu_kick(vcpu);
4812 }
4813
4814 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4815 {
4816         struct vcpu_vmx *vmx = to_vmx(vcpu);
4817
4818         if (!pi_test_and_clear_on(&vmx->pi_desc))
4819                 return;
4820
4821         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4822 }
4823
4824 /*
4825  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4826  * will not change in the lifetime of the guest.
4827  * Note that host-state that does change is set elsewhere. E.g., host-state
4828  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4829  */
4830 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4831 {
4832         u32 low32, high32;
4833         unsigned long tmpl;
4834         struct desc_ptr dt;
4835         unsigned long cr4;
4836
4837         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4838         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4839
4840         /* Save the most likely value for this task's CR4 in the VMCS. */
4841         cr4 = cr4_read_shadow();
4842         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4843         vmx->host_state.vmcs_host_cr4 = cr4;
4844
4845         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4846 #ifdef CONFIG_X86_64
4847         /*
4848          * Load null selectors, so we can avoid reloading them in
4849          * __vmx_load_host_state(), in case userspace uses the null selectors
4850          * too (the expected case).
4851          */
4852         vmcs_write16(HOST_DS_SELECTOR, 0);
4853         vmcs_write16(HOST_ES_SELECTOR, 0);
4854 #else
4855         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4856         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4857 #endif
4858         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4859         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4860
4861         native_store_idt(&dt);
4862         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4863         vmx->host_idt_base = dt.address;
4864
4865         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4866
4867         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4868         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4869         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4870         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4871
4872         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4873                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4874                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4875         }
4876 }
4877
4878 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4879 {
4880         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4881         if (enable_ept)
4882                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4883         if (is_guest_mode(&vmx->vcpu))
4884                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4885                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4886         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4887 }
4888
4889 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4890 {
4891         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4892
4893         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4894                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4895         /* Enable the preemption timer dynamically */
4896         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4897         return pin_based_exec_ctrl;
4898 }
4899
4900 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4901 {
4902         struct vcpu_vmx *vmx = to_vmx(vcpu);
4903
4904         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4905         if (cpu_has_secondary_exec_ctrls()) {
4906                 if (kvm_vcpu_apicv_active(vcpu))
4907                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4908                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4909                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4910                 else
4911                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4912                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4913                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4914         }
4915
4916         if (cpu_has_vmx_msr_bitmap())
4917                 vmx_set_msr_bitmap(vcpu);
4918 }
4919
4920 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4921 {
4922         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4923
4924         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4925                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4926
4927         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4928                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4929 #ifdef CONFIG_X86_64
4930                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4931                                 CPU_BASED_CR8_LOAD_EXITING;
4932 #endif
4933         }
4934         if (!enable_ept)
4935                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4936                                 CPU_BASED_CR3_LOAD_EXITING  |
4937                                 CPU_BASED_INVLPG_EXITING;
4938         return exec_control;
4939 }
4940
4941 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4942 {
4943         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4944         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4945                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4946         if (vmx->vpid == 0)
4947                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4948         if (!enable_ept) {
4949                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4950                 enable_unrestricted_guest = 0;
4951                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4952                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4953         }
4954         if (!enable_unrestricted_guest)
4955                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4956         if (!ple_gap)
4957                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4958         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4959                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4960                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4961         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4962         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4963            (handle_vmptrld).
4964            We can NOT enable shadow_vmcs here because we don't have yet
4965            a current VMCS12
4966         */
4967         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4968
4969         if (!enable_pml)
4970                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4971
4972         return exec_control;
4973 }
4974
4975 static void ept_set_mmio_spte_mask(void)
4976 {
4977         /*
4978          * EPT Misconfigurations can be generated if the value of bits 2:0
4979          * of an EPT paging-structure entry is 110b (write/execute).
4980          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4981          * spte.
4982          */
4983         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4984 }
4985
4986 #define VMX_XSS_EXIT_BITMAP 0
4987 /*
4988  * Sets up the vmcs for emulated real mode.
4989  */
4990 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4991 {
4992 #ifdef CONFIG_X86_64
4993         unsigned long a;
4994 #endif
4995         int i;
4996
4997         /* I/O */
4998         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4999         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5000
5001         if (enable_shadow_vmcs) {
5002                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5003                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5004         }
5005         if (cpu_has_vmx_msr_bitmap())
5006                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5007
5008         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5009
5010         /* Control */
5011         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5012         vmx->hv_deadline_tsc = -1;
5013
5014         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5015
5016         if (cpu_has_secondary_exec_ctrls()) {
5017                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5018                                 vmx_secondary_exec_control(vmx));
5019         }
5020
5021         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5022                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5023                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5024                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5025                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5026
5027                 vmcs_write16(GUEST_INTR_STATUS, 0);
5028
5029                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5030                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5031         }
5032
5033         if (ple_gap) {
5034                 vmcs_write32(PLE_GAP, ple_gap);
5035                 vmx->ple_window = ple_window;
5036                 vmx->ple_window_dirty = true;
5037         }
5038
5039         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5040         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5041         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5042
5043         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5044         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5045         vmx_set_constant_host_state(vmx);
5046 #ifdef CONFIG_X86_64
5047         rdmsrl(MSR_FS_BASE, a);
5048         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5049         rdmsrl(MSR_GS_BASE, a);
5050         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5051 #else
5052         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5053         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5054 #endif
5055
5056         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5057         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5058         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5059         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5060         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5061
5062         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5063                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5064
5065         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5066                 u32 index = vmx_msr_index[i];
5067                 u32 data_low, data_high;
5068                 int j = vmx->nmsrs;
5069
5070                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5071                         continue;
5072                 if (wrmsr_safe(index, data_low, data_high) < 0)
5073                         continue;
5074                 vmx->guest_msrs[j].index = i;
5075                 vmx->guest_msrs[j].data = 0;
5076                 vmx->guest_msrs[j].mask = -1ull;
5077                 ++vmx->nmsrs;
5078         }
5079
5080
5081         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5082
5083         /* 22.2.1, 20.8.1 */
5084         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5085
5086         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
5087         set_cr4_guest_host_mask(vmx);
5088
5089         if (vmx_xsaves_supported())
5090                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5091
5092         if (enable_pml) {
5093                 ASSERT(vmx->pml_pg);
5094                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5095                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5096         }
5097
5098         return 0;
5099 }
5100
5101 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5102 {
5103         struct vcpu_vmx *vmx = to_vmx(vcpu);
5104         struct msr_data apic_base_msr;
5105         u64 cr0;
5106
5107         vmx->rmode.vm86_active = 0;
5108
5109         vmx->soft_vnmi_blocked = 0;
5110
5111         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5112         kvm_set_cr8(vcpu, 0);
5113
5114         if (!init_event) {
5115                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5116                                      MSR_IA32_APICBASE_ENABLE;
5117                 if (kvm_vcpu_is_reset_bsp(vcpu))
5118                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5119                 apic_base_msr.host_initiated = true;
5120                 kvm_set_apic_base(vcpu, &apic_base_msr);
5121         }
5122
5123         vmx_segment_cache_clear(vmx);
5124
5125         seg_setup(VCPU_SREG_CS);
5126         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5127         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5128
5129         seg_setup(VCPU_SREG_DS);
5130         seg_setup(VCPU_SREG_ES);
5131         seg_setup(VCPU_SREG_FS);
5132         seg_setup(VCPU_SREG_GS);
5133         seg_setup(VCPU_SREG_SS);
5134
5135         vmcs_write16(GUEST_TR_SELECTOR, 0);
5136         vmcs_writel(GUEST_TR_BASE, 0);
5137         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5138         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5139
5140         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5141         vmcs_writel(GUEST_LDTR_BASE, 0);
5142         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5143         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5144
5145         if (!init_event) {
5146                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5147                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5148                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5149                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5150         }
5151
5152         vmcs_writel(GUEST_RFLAGS, 0x02);
5153         kvm_rip_write(vcpu, 0xfff0);
5154
5155         vmcs_writel(GUEST_GDTR_BASE, 0);
5156         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5157
5158         vmcs_writel(GUEST_IDTR_BASE, 0);
5159         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5160
5161         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5162         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5163         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5164
5165         setup_msrs(vmx);
5166
5167         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5168
5169         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5170                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5171                 if (cpu_need_tpr_shadow(vcpu))
5172                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5173                                      __pa(vcpu->arch.apic->regs));
5174                 vmcs_write32(TPR_THRESHOLD, 0);
5175         }
5176
5177         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5178
5179         if (kvm_vcpu_apicv_active(vcpu))
5180                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5181
5182         if (vmx->vpid != 0)
5183                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5184
5185         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5186         vmx->vcpu.arch.cr0 = cr0;
5187         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5188         vmx_set_cr4(vcpu, 0);
5189         vmx_set_efer(vcpu, 0);
5190         vmx_fpu_activate(vcpu);
5191         update_exception_bitmap(vcpu);
5192
5193         vpid_sync_context(vmx->vpid);
5194 }
5195
5196 /*
5197  * In nested virtualization, check if L1 asked to exit on external interrupts.
5198  * For most existing hypervisors, this will always return true.
5199  */
5200 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5201 {
5202         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5203                 PIN_BASED_EXT_INTR_MASK;
5204 }
5205
5206 /*
5207  * In nested virtualization, check if L1 has set
5208  * VM_EXIT_ACK_INTR_ON_EXIT
5209  */
5210 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5211 {
5212         return get_vmcs12(vcpu)->vm_exit_controls &
5213                 VM_EXIT_ACK_INTR_ON_EXIT;
5214 }
5215
5216 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5217 {
5218         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5219                 PIN_BASED_NMI_EXITING;
5220 }
5221
5222 static void enable_irq_window(struct kvm_vcpu *vcpu)
5223 {
5224         u32 cpu_based_vm_exec_control;
5225
5226         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5227         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5228         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5229 }
5230
5231 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5232 {
5233         u32 cpu_based_vm_exec_control;
5234
5235         if (!cpu_has_virtual_nmis() ||
5236             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5237                 enable_irq_window(vcpu);
5238                 return;
5239         }
5240
5241         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5242         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5243         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5244 }
5245
5246 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5247 {
5248         struct vcpu_vmx *vmx = to_vmx(vcpu);
5249         uint32_t intr;
5250         int irq = vcpu->arch.interrupt.nr;
5251
5252         trace_kvm_inj_virq(irq);
5253
5254         ++vcpu->stat.irq_injections;
5255         if (vmx->rmode.vm86_active) {
5256                 int inc_eip = 0;
5257                 if (vcpu->arch.interrupt.soft)
5258                         inc_eip = vcpu->arch.event_exit_inst_len;
5259                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5260                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5261                 return;
5262         }
5263         intr = irq | INTR_INFO_VALID_MASK;
5264         if (vcpu->arch.interrupt.soft) {
5265                 intr |= INTR_TYPE_SOFT_INTR;
5266                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5267                              vmx->vcpu.arch.event_exit_inst_len);
5268         } else
5269                 intr |= INTR_TYPE_EXT_INTR;
5270         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5271 }
5272
5273 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5274 {
5275         struct vcpu_vmx *vmx = to_vmx(vcpu);
5276
5277         if (is_guest_mode(vcpu))
5278                 return;
5279
5280         if (!cpu_has_virtual_nmis()) {
5281                 /*
5282                  * Tracking the NMI-blocked state in software is built upon
5283                  * finding the next open IRQ window. This, in turn, depends on
5284                  * well-behaving guests: They have to keep IRQs disabled at
5285                  * least as long as the NMI handler runs. Otherwise we may
5286                  * cause NMI nesting, maybe breaking the guest. But as this is
5287                  * highly unlikely, we can live with the residual risk.
5288                  */
5289                 vmx->soft_vnmi_blocked = 1;
5290                 vmx->vnmi_blocked_time = 0;
5291         }
5292
5293         ++vcpu->stat.nmi_injections;
5294         vmx->nmi_known_unmasked = false;
5295         if (vmx->rmode.vm86_active) {
5296                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5297                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5298                 return;
5299         }
5300         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5301                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5302 }
5303
5304 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5305 {
5306         if (!cpu_has_virtual_nmis())
5307                 return to_vmx(vcpu)->soft_vnmi_blocked;
5308         if (to_vmx(vcpu)->nmi_known_unmasked)
5309                 return false;
5310         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5311 }
5312
5313 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5314 {
5315         struct vcpu_vmx *vmx = to_vmx(vcpu);
5316
5317         if (!cpu_has_virtual_nmis()) {
5318                 if (vmx->soft_vnmi_blocked != masked) {
5319                         vmx->soft_vnmi_blocked = masked;
5320                         vmx->vnmi_blocked_time = 0;
5321                 }
5322         } else {
5323                 vmx->nmi_known_unmasked = !masked;
5324                 if (masked)
5325                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5326                                       GUEST_INTR_STATE_NMI);
5327                 else
5328                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5329                                         GUEST_INTR_STATE_NMI);
5330         }
5331 }
5332
5333 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5334 {
5335         if (to_vmx(vcpu)->nested.nested_run_pending)
5336                 return 0;
5337
5338         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5339                 return 0;
5340
5341         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5342                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5343                    | GUEST_INTR_STATE_NMI));
5344 }
5345
5346 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5347 {
5348         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5349                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5350                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5351                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5352 }
5353
5354 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5355 {
5356         int ret;
5357
5358         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5359                                     PAGE_SIZE * 3);
5360         if (ret)
5361                 return ret;
5362         kvm->arch.tss_addr = addr;
5363         return init_rmode_tss(kvm);
5364 }
5365
5366 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5367 {
5368         switch (vec) {
5369         case BP_VECTOR:
5370                 /*
5371                  * Update instruction length as we may reinject the exception
5372                  * from user space while in guest debugging mode.
5373                  */
5374                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5375                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5376                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5377                         return false;
5378                 /* fall through */
5379         case DB_VECTOR:
5380                 if (vcpu->guest_debug &
5381                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5382                         return false;
5383                 /* fall through */
5384         case DE_VECTOR:
5385         case OF_VECTOR:
5386         case BR_VECTOR:
5387         case UD_VECTOR:
5388         case DF_VECTOR:
5389         case SS_VECTOR:
5390         case GP_VECTOR:
5391         case MF_VECTOR:
5392                 return true;
5393         break;
5394         }
5395         return false;
5396 }
5397
5398 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5399                                   int vec, u32 err_code)
5400 {
5401         /*
5402          * Instruction with address size override prefix opcode 0x67
5403          * Cause the #SS fault with 0 error code in VM86 mode.
5404          */
5405         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5406                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5407                         if (vcpu->arch.halt_request) {
5408                                 vcpu->arch.halt_request = 0;
5409                                 return kvm_vcpu_halt(vcpu);
5410                         }
5411                         return 1;
5412                 }
5413                 return 0;
5414         }
5415
5416         /*
5417          * Forward all other exceptions that are valid in real mode.
5418          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5419          *        the required debugging infrastructure rework.
5420          */
5421         kvm_queue_exception(vcpu, vec);
5422         return 1;
5423 }
5424
5425 /*
5426  * Trigger machine check on the host. We assume all the MSRs are already set up
5427  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5428  * We pass a fake environment to the machine check handler because we want
5429  * the guest to be always treated like user space, no matter what context
5430  * it used internally.
5431  */
5432 static void kvm_machine_check(void)
5433 {
5434 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5435         struct pt_regs regs = {
5436                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5437                 .flags = X86_EFLAGS_IF,
5438         };
5439
5440         do_machine_check(&regs, 0);
5441 #endif
5442 }
5443
5444 static int handle_machine_check(struct kvm_vcpu *vcpu)
5445 {
5446         /* already handled by vcpu_run */
5447         return 1;
5448 }
5449
5450 static int handle_exception(struct kvm_vcpu *vcpu)
5451 {
5452         struct vcpu_vmx *vmx = to_vmx(vcpu);
5453         struct kvm_run *kvm_run = vcpu->run;
5454         u32 intr_info, ex_no, error_code;
5455         unsigned long cr2, rip, dr6;
5456         u32 vect_info;
5457         enum emulation_result er;
5458
5459         vect_info = vmx->idt_vectoring_info;
5460         intr_info = vmx->exit_intr_info;
5461
5462         if (is_machine_check(intr_info))
5463                 return handle_machine_check(vcpu);
5464
5465         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5466                 return 1;  /* already handled by vmx_vcpu_run() */
5467
5468         if (is_no_device(intr_info)) {
5469                 vmx_fpu_activate(vcpu);
5470                 return 1;
5471         }
5472
5473         if (is_invalid_opcode(intr_info)) {
5474                 if (is_guest_mode(vcpu)) {
5475                         kvm_queue_exception(vcpu, UD_VECTOR);
5476                         return 1;
5477                 }
5478                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5479                 if (er != EMULATE_DONE)
5480                         kvm_queue_exception(vcpu, UD_VECTOR);
5481                 return 1;
5482         }
5483
5484         error_code = 0;
5485         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5486                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5487
5488         /*
5489          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5490          * MMIO, it is better to report an internal error.
5491          * See the comments in vmx_handle_exit.
5492          */
5493         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5494             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5495                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5496                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5497                 vcpu->run->internal.ndata = 3;
5498                 vcpu->run->internal.data[0] = vect_info;
5499                 vcpu->run->internal.data[1] = intr_info;
5500                 vcpu->run->internal.data[2] = error_code;
5501                 return 0;
5502         }
5503
5504         if (is_page_fault(intr_info)) {
5505                 /* EPT won't cause page fault directly */
5506                 BUG_ON(enable_ept);
5507                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5508                 trace_kvm_page_fault(cr2, error_code);
5509
5510                 if (kvm_event_needs_reinjection(vcpu))
5511                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5512                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5513         }
5514
5515         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5516
5517         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5518                 return handle_rmode_exception(vcpu, ex_no, error_code);
5519
5520         switch (ex_no) {
5521         case AC_VECTOR:
5522                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5523                 return 1;
5524         case DB_VECTOR:
5525                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5526                 if (!(vcpu->guest_debug &
5527                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5528                         vcpu->arch.dr6 &= ~15;
5529                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5530                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5531                                 skip_emulated_instruction(vcpu);
5532
5533                         kvm_queue_exception(vcpu, DB_VECTOR);
5534                         return 1;
5535                 }
5536                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5537                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5538                 /* fall through */
5539         case BP_VECTOR:
5540                 /*
5541                  * Update instruction length as we may reinject #BP from
5542                  * user space while in guest debugging mode. Reading it for
5543                  * #DB as well causes no harm, it is not used in that case.
5544                  */
5545                 vmx->vcpu.arch.event_exit_inst_len =
5546                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5547                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5548                 rip = kvm_rip_read(vcpu);
5549                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5550                 kvm_run->debug.arch.exception = ex_no;
5551                 break;
5552         default:
5553                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5554                 kvm_run->ex.exception = ex_no;
5555                 kvm_run->ex.error_code = error_code;
5556                 break;
5557         }
5558         return 0;
5559 }
5560
5561 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5562 {
5563         ++vcpu->stat.irq_exits;
5564         return 1;
5565 }
5566
5567 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5568 {
5569         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5570         return 0;
5571 }
5572
5573 static int handle_io(struct kvm_vcpu *vcpu)
5574 {
5575         unsigned long exit_qualification;
5576         int size, in, string;
5577         unsigned port;
5578
5579         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5580         string = (exit_qualification & 16) != 0;
5581         in = (exit_qualification & 8) != 0;
5582
5583         ++vcpu->stat.io_exits;
5584
5585         if (string || in)
5586                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5587
5588         port = exit_qualification >> 16;
5589         size = (exit_qualification & 7) + 1;
5590         skip_emulated_instruction(vcpu);
5591
5592         return kvm_fast_pio_out(vcpu, size, port);
5593 }
5594
5595 static void
5596 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5597 {
5598         /*
5599          * Patch in the VMCALL instruction:
5600          */
5601         hypercall[0] = 0x0f;
5602         hypercall[1] = 0x01;
5603         hypercall[2] = 0xc1;
5604 }
5605
5606 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5607 {
5608         unsigned long always_on = VMXON_CR0_ALWAYSON;
5609         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5610
5611         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5612                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5613             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5614                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5615         return (val & always_on) == always_on;
5616 }
5617
5618 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5619 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5620 {
5621         if (is_guest_mode(vcpu)) {
5622                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5623                 unsigned long orig_val = val;
5624
5625                 /*
5626                  * We get here when L2 changed cr0 in a way that did not change
5627                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5628                  * but did change L0 shadowed bits. So we first calculate the
5629                  * effective cr0 value that L1 would like to write into the
5630                  * hardware. It consists of the L2-owned bits from the new
5631                  * value combined with the L1-owned bits from L1's guest_cr0.
5632                  */
5633                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5634                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5635
5636                 if (!nested_cr0_valid(vcpu, val))
5637                         return 1;
5638
5639                 if (kvm_set_cr0(vcpu, val))
5640                         return 1;
5641                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5642                 return 0;
5643         } else {
5644                 if (to_vmx(vcpu)->nested.vmxon &&
5645                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5646                         return 1;
5647                 return kvm_set_cr0(vcpu, val);
5648         }
5649 }
5650
5651 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5652 {
5653         if (is_guest_mode(vcpu)) {
5654                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5655                 unsigned long orig_val = val;
5656
5657                 /* analogously to handle_set_cr0 */
5658                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5659                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5660                 if (kvm_set_cr4(vcpu, val))
5661                         return 1;
5662                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5663                 return 0;
5664         } else
5665                 return kvm_set_cr4(vcpu, val);
5666 }
5667
5668 /* called to set cr0 as appropriate for clts instruction exit. */
5669 static void handle_clts(struct kvm_vcpu *vcpu)
5670 {
5671         if (is_guest_mode(vcpu)) {
5672                 /*
5673                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5674                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5675                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5676                  */
5677                 vmcs_writel(CR0_READ_SHADOW,
5678                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5679                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5680         } else
5681                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5682 }
5683
5684 static int handle_cr(struct kvm_vcpu *vcpu)
5685 {
5686         unsigned long exit_qualification, val;
5687         int cr;
5688         int reg;
5689         int err;
5690
5691         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5692         cr = exit_qualification & 15;
5693         reg = (exit_qualification >> 8) & 15;
5694         switch ((exit_qualification >> 4) & 3) {
5695         case 0: /* mov to cr */
5696                 val = kvm_register_readl(vcpu, reg);
5697                 trace_kvm_cr_write(cr, val);
5698                 switch (cr) {
5699                 case 0:
5700                         err = handle_set_cr0(vcpu, val);
5701                         kvm_complete_insn_gp(vcpu, err);
5702                         return 1;
5703                 case 3:
5704                         err = kvm_set_cr3(vcpu, val);
5705                         kvm_complete_insn_gp(vcpu, err);
5706                         return 1;
5707                 case 4:
5708                         err = handle_set_cr4(vcpu, val);
5709                         kvm_complete_insn_gp(vcpu, err);
5710                         return 1;
5711                 case 8: {
5712                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5713                                 u8 cr8 = (u8)val;
5714                                 err = kvm_set_cr8(vcpu, cr8);
5715                                 kvm_complete_insn_gp(vcpu, err);
5716                                 if (lapic_in_kernel(vcpu))
5717                                         return 1;
5718                                 if (cr8_prev <= cr8)
5719                                         return 1;
5720                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5721                                 return 0;
5722                         }
5723                 }
5724                 break;
5725         case 2: /* clts */
5726                 handle_clts(vcpu);
5727                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5728                 skip_emulated_instruction(vcpu);
5729                 vmx_fpu_activate(vcpu);
5730                 return 1;
5731         case 1: /*mov from cr*/
5732                 switch (cr) {
5733                 case 3:
5734                         val = kvm_read_cr3(vcpu);
5735                         kvm_register_write(vcpu, reg, val);
5736                         trace_kvm_cr_read(cr, val);
5737                         skip_emulated_instruction(vcpu);
5738                         return 1;
5739                 case 8:
5740                         val = kvm_get_cr8(vcpu);
5741                         kvm_register_write(vcpu, reg, val);
5742                         trace_kvm_cr_read(cr, val);
5743                         skip_emulated_instruction(vcpu);
5744                         return 1;
5745                 }
5746                 break;
5747         case 3: /* lmsw */
5748                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5749                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5750                 kvm_lmsw(vcpu, val);
5751
5752                 skip_emulated_instruction(vcpu);
5753                 return 1;
5754         default:
5755                 break;
5756         }
5757         vcpu->run->exit_reason = 0;
5758         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5759                (int)(exit_qualification >> 4) & 3, cr);
5760         return 0;
5761 }
5762
5763 static int handle_dr(struct kvm_vcpu *vcpu)
5764 {
5765         unsigned long exit_qualification;
5766         int dr, dr7, reg;
5767
5768         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5769         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5770
5771         /* First, if DR does not exist, trigger UD */
5772         if (!kvm_require_dr(vcpu, dr))
5773                 return 1;
5774
5775         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5776         if (!kvm_require_cpl(vcpu, 0))
5777                 return 1;
5778         dr7 = vmcs_readl(GUEST_DR7);
5779         if (dr7 & DR7_GD) {
5780                 /*
5781                  * As the vm-exit takes precedence over the debug trap, we
5782                  * need to emulate the latter, either for the host or the
5783                  * guest debugging itself.
5784                  */
5785                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5786                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5787                         vcpu->run->debug.arch.dr7 = dr7;
5788                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5789                         vcpu->run->debug.arch.exception = DB_VECTOR;
5790                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5791                         return 0;
5792                 } else {
5793                         vcpu->arch.dr6 &= ~15;
5794                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5795                         kvm_queue_exception(vcpu, DB_VECTOR);
5796                         return 1;
5797                 }
5798         }
5799
5800         if (vcpu->guest_debug == 0) {
5801                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5802                                 CPU_BASED_MOV_DR_EXITING);
5803
5804                 /*
5805                  * No more DR vmexits; force a reload of the debug registers
5806                  * and reenter on this instruction.  The next vmexit will
5807                  * retrieve the full state of the debug registers.
5808                  */
5809                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5810                 return 1;
5811         }
5812
5813         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5814         if (exit_qualification & TYPE_MOV_FROM_DR) {
5815                 unsigned long val;
5816
5817                 if (kvm_get_dr(vcpu, dr, &val))
5818                         return 1;
5819                 kvm_register_write(vcpu, reg, val);
5820         } else
5821                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5822                         return 1;
5823
5824         skip_emulated_instruction(vcpu);
5825         return 1;
5826 }
5827
5828 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5829 {
5830         return vcpu->arch.dr6;
5831 }
5832
5833 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5834 {
5835 }
5836
5837 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5838 {
5839         get_debugreg(vcpu->arch.db[0], 0);
5840         get_debugreg(vcpu->arch.db[1], 1);
5841         get_debugreg(vcpu->arch.db[2], 2);
5842         get_debugreg(vcpu->arch.db[3], 3);
5843         get_debugreg(vcpu->arch.dr6, 6);
5844         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5845
5846         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5847         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5848 }
5849
5850 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5851 {
5852         vmcs_writel(GUEST_DR7, val);
5853 }
5854
5855 static int handle_cpuid(struct kvm_vcpu *vcpu)
5856 {
5857         kvm_emulate_cpuid(vcpu);
5858         return 1;
5859 }
5860
5861 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5862 {
5863         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5864         struct msr_data msr_info;
5865
5866         msr_info.index = ecx;
5867         msr_info.host_initiated = false;
5868         if (vmx_get_msr(vcpu, &msr_info)) {
5869                 trace_kvm_msr_read_ex(ecx);
5870                 kvm_inject_gp(vcpu, 0);
5871                 return 1;
5872         }
5873
5874         trace_kvm_msr_read(ecx, msr_info.data);
5875
5876         /* FIXME: handling of bits 32:63 of rax, rdx */
5877         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5878         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5879         skip_emulated_instruction(vcpu);
5880         return 1;
5881 }
5882
5883 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5884 {
5885         struct msr_data msr;
5886         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5887         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5888                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5889
5890         msr.data = data;
5891         msr.index = ecx;
5892         msr.host_initiated = false;
5893         if (kvm_set_msr(vcpu, &msr) != 0) {
5894                 trace_kvm_msr_write_ex(ecx, data);
5895                 kvm_inject_gp(vcpu, 0);
5896                 return 1;
5897         }
5898
5899         trace_kvm_msr_write(ecx, data);
5900         skip_emulated_instruction(vcpu);
5901         return 1;
5902 }
5903
5904 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5905 {
5906         kvm_make_request(KVM_REQ_EVENT, vcpu);
5907         return 1;
5908 }
5909
5910 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5911 {
5912         u32 cpu_based_vm_exec_control;
5913
5914         /* clear pending irq */
5915         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5916         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5917         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5918
5919         kvm_make_request(KVM_REQ_EVENT, vcpu);
5920
5921         ++vcpu->stat.irq_window_exits;
5922         return 1;
5923 }
5924
5925 static int handle_halt(struct kvm_vcpu *vcpu)
5926 {
5927         return kvm_emulate_halt(vcpu);
5928 }
5929
5930 static int handle_vmcall(struct kvm_vcpu *vcpu)
5931 {
5932         return kvm_emulate_hypercall(vcpu);
5933 }
5934
5935 static int handle_invd(struct kvm_vcpu *vcpu)
5936 {
5937         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5938 }
5939
5940 static int handle_invlpg(struct kvm_vcpu *vcpu)
5941 {
5942         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5943
5944         kvm_mmu_invlpg(vcpu, exit_qualification);
5945         skip_emulated_instruction(vcpu);
5946         return 1;
5947 }
5948
5949 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5950 {
5951         int err;
5952
5953         err = kvm_rdpmc(vcpu);
5954         kvm_complete_insn_gp(vcpu, err);
5955
5956         return 1;
5957 }
5958
5959 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5960 {
5961         kvm_emulate_wbinvd(vcpu);
5962         return 1;
5963 }
5964
5965 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5966 {
5967         u64 new_bv = kvm_read_edx_eax(vcpu);
5968         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5969
5970         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5971                 skip_emulated_instruction(vcpu);
5972         return 1;
5973 }
5974
5975 static int handle_xsaves(struct kvm_vcpu *vcpu)
5976 {
5977         skip_emulated_instruction(vcpu);
5978         WARN(1, "this should never happen\n");
5979         return 1;
5980 }
5981
5982 static int handle_xrstors(struct kvm_vcpu *vcpu)
5983 {
5984         skip_emulated_instruction(vcpu);
5985         WARN(1, "this should never happen\n");
5986         return 1;
5987 }
5988
5989 static int handle_apic_access(struct kvm_vcpu *vcpu)
5990 {
5991         if (likely(fasteoi)) {
5992                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5993                 int access_type, offset;
5994
5995                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5996                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5997                 /*
5998                  * Sane guest uses MOV to write EOI, with written value
5999                  * not cared. So make a short-circuit here by avoiding
6000                  * heavy instruction emulation.
6001                  */
6002                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6003                     (offset == APIC_EOI)) {
6004                         kvm_lapic_set_eoi(vcpu);
6005                         skip_emulated_instruction(vcpu);
6006                         return 1;
6007                 }
6008         }
6009         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6010 }
6011
6012 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6013 {
6014         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6015         int vector = exit_qualification & 0xff;
6016
6017         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6018         kvm_apic_set_eoi_accelerated(vcpu, vector);
6019         return 1;
6020 }
6021
6022 static int handle_apic_write(struct kvm_vcpu *vcpu)
6023 {
6024         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6025         u32 offset = exit_qualification & 0xfff;
6026
6027         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6028         kvm_apic_write_nodecode(vcpu, offset);
6029         return 1;
6030 }
6031
6032 static int handle_task_switch(struct kvm_vcpu *vcpu)
6033 {
6034         struct vcpu_vmx *vmx = to_vmx(vcpu);
6035         unsigned long exit_qualification;
6036         bool has_error_code = false;
6037         u32 error_code = 0;
6038         u16 tss_selector;
6039         int reason, type, idt_v, idt_index;
6040
6041         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6042         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6043         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6044
6045         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6046
6047         reason = (u32)exit_qualification >> 30;
6048         if (reason == TASK_SWITCH_GATE && idt_v) {
6049                 switch (type) {
6050                 case INTR_TYPE_NMI_INTR:
6051                         vcpu->arch.nmi_injected = false;
6052                         vmx_set_nmi_mask(vcpu, true);
6053                         break;
6054                 case INTR_TYPE_EXT_INTR:
6055                 case INTR_TYPE_SOFT_INTR:
6056                         kvm_clear_interrupt_queue(vcpu);
6057                         break;
6058                 case INTR_TYPE_HARD_EXCEPTION:
6059                         if (vmx->idt_vectoring_info &
6060                             VECTORING_INFO_DELIVER_CODE_MASK) {
6061                                 has_error_code = true;
6062                                 error_code =
6063                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6064                         }
6065                         /* fall through */
6066                 case INTR_TYPE_SOFT_EXCEPTION:
6067                         kvm_clear_exception_queue(vcpu);
6068                         break;
6069                 default:
6070                         break;
6071                 }
6072         }
6073         tss_selector = exit_qualification;
6074
6075         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6076                        type != INTR_TYPE_EXT_INTR &&
6077                        type != INTR_TYPE_NMI_INTR))
6078                 skip_emulated_instruction(vcpu);
6079
6080         if (kvm_task_switch(vcpu, tss_selector,
6081                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6082                             has_error_code, error_code) == EMULATE_FAIL) {
6083                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6084                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6085                 vcpu->run->internal.ndata = 0;
6086                 return 0;
6087         }
6088
6089         /*
6090          * TODO: What about debug traps on tss switch?
6091          *       Are we supposed to inject them and update dr6?
6092          */
6093
6094         return 1;
6095 }
6096
6097 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6098 {
6099         unsigned long exit_qualification;
6100         gpa_t gpa;
6101         u32 error_code;
6102         int gla_validity;
6103
6104         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6105
6106         gla_validity = (exit_qualification >> 7) & 0x3;
6107         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
6108                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6109                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6110                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6111                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6112                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6113                         (long unsigned int)exit_qualification);
6114                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6115                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6116                 return 0;
6117         }
6118
6119         /*
6120          * EPT violation happened while executing iret from NMI,
6121          * "blocked by NMI" bit has to be set before next VM entry.
6122          * There are errata that may cause this bit to not be set:
6123          * AAK134, BY25.
6124          */
6125         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6126                         cpu_has_virtual_nmis() &&
6127                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6128                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6129
6130         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6131         trace_kvm_page_fault(gpa, exit_qualification);
6132
6133         /* it is a read fault? */
6134         error_code = (exit_qualification << 2) & PFERR_USER_MASK;
6135         /* it is a write fault? */
6136         error_code |= exit_qualification & PFERR_WRITE_MASK;
6137         /* It is a fetch fault? */
6138         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6139         /* ept page table is present? */
6140         error_code |= (exit_qualification & 0x38) != 0;
6141
6142         vcpu->arch.exit_qualification = exit_qualification;
6143
6144         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6145 }
6146
6147 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6148 {
6149         int ret;
6150         gpa_t gpa;
6151
6152         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6153         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6154                 skip_emulated_instruction(vcpu);
6155                 trace_kvm_fast_mmio(gpa);
6156                 return 1;
6157         }
6158
6159         ret = handle_mmio_page_fault(vcpu, gpa, true);
6160         if (likely(ret == RET_MMIO_PF_EMULATE))
6161                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6162                                               EMULATE_DONE;
6163
6164         if (unlikely(ret == RET_MMIO_PF_INVALID))
6165                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6166
6167         if (unlikely(ret == RET_MMIO_PF_RETRY))
6168                 return 1;
6169
6170         /* It is the real ept misconfig */
6171         WARN_ON(1);
6172
6173         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6174         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6175
6176         return 0;
6177 }
6178
6179 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6180 {
6181         u32 cpu_based_vm_exec_control;
6182
6183         /* clear pending NMI */
6184         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6185         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6186         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6187         ++vcpu->stat.nmi_window_exits;
6188         kvm_make_request(KVM_REQ_EVENT, vcpu);
6189
6190         return 1;
6191 }
6192
6193 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6194 {
6195         struct vcpu_vmx *vmx = to_vmx(vcpu);
6196         enum emulation_result err = EMULATE_DONE;
6197         int ret = 1;
6198         u32 cpu_exec_ctrl;
6199         bool intr_window_requested;
6200         unsigned count = 130;
6201
6202         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6203         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6204
6205         while (vmx->emulation_required && count-- != 0) {
6206                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6207                         return handle_interrupt_window(&vmx->vcpu);
6208
6209                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6210                         return 1;
6211
6212                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6213
6214                 if (err == EMULATE_USER_EXIT) {
6215                         ++vcpu->stat.mmio_exits;
6216                         ret = 0;
6217                         goto out;
6218                 }
6219
6220                 if (err != EMULATE_DONE) {
6221                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6222                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6223                         vcpu->run->internal.ndata = 0;
6224                         return 0;
6225                 }
6226
6227                 if (vcpu->arch.halt_request) {
6228                         vcpu->arch.halt_request = 0;
6229                         ret = kvm_vcpu_halt(vcpu);
6230                         goto out;
6231                 }
6232
6233                 if (signal_pending(current))
6234                         goto out;
6235                 if (need_resched())
6236                         schedule();
6237         }
6238
6239 out:
6240         return ret;
6241 }
6242
6243 static int __grow_ple_window(int val)
6244 {
6245         if (ple_window_grow < 1)
6246                 return ple_window;
6247
6248         val = min(val, ple_window_actual_max);
6249
6250         if (ple_window_grow < ple_window)
6251                 val *= ple_window_grow;
6252         else
6253                 val += ple_window_grow;
6254
6255         return val;
6256 }
6257
6258 static int __shrink_ple_window(int val, int modifier, int minimum)
6259 {
6260         if (modifier < 1)
6261                 return ple_window;
6262
6263         if (modifier < ple_window)
6264                 val /= modifier;
6265         else
6266                 val -= modifier;
6267
6268         return max(val, minimum);
6269 }
6270
6271 static void grow_ple_window(struct kvm_vcpu *vcpu)
6272 {
6273         struct vcpu_vmx *vmx = to_vmx(vcpu);
6274         int old = vmx->ple_window;
6275
6276         vmx->ple_window = __grow_ple_window(old);
6277
6278         if (vmx->ple_window != old)
6279                 vmx->ple_window_dirty = true;
6280
6281         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6282 }
6283
6284 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6285 {
6286         struct vcpu_vmx *vmx = to_vmx(vcpu);
6287         int old = vmx->ple_window;
6288
6289         vmx->ple_window = __shrink_ple_window(old,
6290                                               ple_window_shrink, ple_window);
6291
6292         if (vmx->ple_window != old)
6293                 vmx->ple_window_dirty = true;
6294
6295         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6296 }
6297
6298 /*
6299  * ple_window_actual_max is computed to be one grow_ple_window() below
6300  * ple_window_max. (See __grow_ple_window for the reason.)
6301  * This prevents overflows, because ple_window_max is int.
6302  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6303  * this process.
6304  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6305  */
6306 static void update_ple_window_actual_max(void)
6307 {
6308         ple_window_actual_max =
6309                         __shrink_ple_window(max(ple_window_max, ple_window),
6310                                             ple_window_grow, INT_MIN);
6311 }
6312
6313 /*
6314  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6315  */
6316 static void wakeup_handler(void)
6317 {
6318         struct kvm_vcpu *vcpu;
6319         int cpu = smp_processor_id();
6320
6321         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6322         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6323                         blocked_vcpu_list) {
6324                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6325
6326                 if (pi_test_on(pi_desc) == 1)
6327                         kvm_vcpu_kick(vcpu);
6328         }
6329         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6330 }
6331
6332 static __init int hardware_setup(void)
6333 {
6334         int r = -ENOMEM, i, msr;
6335
6336         rdmsrl_safe(MSR_EFER, &host_efer);
6337
6338         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6339                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6340
6341         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6342         if (!vmx_io_bitmap_a)
6343                 return r;
6344
6345         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6346         if (!vmx_io_bitmap_b)
6347                 goto out;
6348
6349         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6350         if (!vmx_msr_bitmap_legacy)
6351                 goto out1;
6352
6353         vmx_msr_bitmap_legacy_x2apic =
6354                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6355         if (!vmx_msr_bitmap_legacy_x2apic)
6356                 goto out2;
6357
6358         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6359         if (!vmx_msr_bitmap_longmode)
6360                 goto out3;
6361
6362         vmx_msr_bitmap_longmode_x2apic =
6363                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6364         if (!vmx_msr_bitmap_longmode_x2apic)
6365                 goto out4;
6366
6367         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6368         if (!vmx_vmread_bitmap)
6369                 goto out6;
6370
6371         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6372         if (!vmx_vmwrite_bitmap)
6373                 goto out7;
6374
6375         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6376         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6377
6378         /*
6379          * Allow direct access to the PC debug port (it is often used for I/O
6380          * delays, but the vmexits simply slow things down).
6381          */
6382         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6383         clear_bit(0x80, vmx_io_bitmap_a);
6384
6385         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6386
6387         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6388         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6389
6390         if (setup_vmcs_config(&vmcs_config) < 0) {
6391                 r = -EIO;
6392                 goto out8;
6393         }
6394
6395         if (boot_cpu_has(X86_FEATURE_NX))
6396                 kvm_enable_efer_bits(EFER_NX);
6397
6398         if (!cpu_has_vmx_vpid())
6399                 enable_vpid = 0;
6400         if (!cpu_has_vmx_shadow_vmcs())
6401                 enable_shadow_vmcs = 0;
6402         if (enable_shadow_vmcs)
6403                 init_vmcs_shadow_fields();
6404
6405         if (!cpu_has_vmx_ept() ||
6406             !cpu_has_vmx_ept_4levels()) {
6407                 enable_ept = 0;
6408                 enable_unrestricted_guest = 0;
6409                 enable_ept_ad_bits = 0;
6410         }
6411
6412         if (!cpu_has_vmx_ept_ad_bits())
6413                 enable_ept_ad_bits = 0;
6414
6415         if (!cpu_has_vmx_unrestricted_guest())
6416                 enable_unrestricted_guest = 0;
6417
6418         if (!cpu_has_vmx_flexpriority())
6419                 flexpriority_enabled = 0;
6420
6421         /*
6422          * set_apic_access_page_addr() is used to reload apic access
6423          * page upon invalidation.  No need to do anything if not
6424          * using the APIC_ACCESS_ADDR VMCS field.
6425          */
6426         if (!flexpriority_enabled)
6427                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6428
6429         if (!cpu_has_vmx_tpr_shadow())
6430                 kvm_x86_ops->update_cr8_intercept = NULL;
6431
6432         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6433                 kvm_disable_largepages();
6434
6435         if (!cpu_has_vmx_ple())
6436                 ple_gap = 0;
6437
6438         if (!cpu_has_vmx_apicv())
6439                 enable_apicv = 0;
6440
6441         if (cpu_has_vmx_tsc_scaling()) {
6442                 kvm_has_tsc_control = true;
6443                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6444                 kvm_tsc_scaling_ratio_frac_bits = 48;
6445         }
6446
6447         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6448         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6449         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6450         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6451         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6452         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6453         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6454
6455         memcpy(vmx_msr_bitmap_legacy_x2apic,
6456                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6457         memcpy(vmx_msr_bitmap_longmode_x2apic,
6458                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6459
6460         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6461
6462         for (msr = 0x800; msr <= 0x8ff; msr++)
6463                 vmx_disable_intercept_msr_read_x2apic(msr);
6464
6465         /* TMCCT */
6466         vmx_enable_intercept_msr_read_x2apic(0x839);
6467         /* TPR */
6468         vmx_disable_intercept_msr_write_x2apic(0x808);
6469         /* EOI */
6470         vmx_disable_intercept_msr_write_x2apic(0x80b);
6471         /* SELF-IPI */
6472         vmx_disable_intercept_msr_write_x2apic(0x83f);
6473
6474         if (enable_ept) {
6475                 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6476                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6477                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6478                         0ull, VMX_EPT_EXECUTABLE_MASK,
6479                         cpu_has_vmx_ept_execute_only() ?
6480                                       0ull : VMX_EPT_READABLE_MASK);
6481                 ept_set_mmio_spte_mask();
6482                 kvm_enable_tdp();
6483         } else
6484                 kvm_disable_tdp();
6485
6486         update_ple_window_actual_max();
6487
6488         /*
6489          * Only enable PML when hardware supports PML feature, and both EPT
6490          * and EPT A/D bit features are enabled -- PML depends on them to work.
6491          */
6492         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6493                 enable_pml = 0;
6494
6495         if (!enable_pml) {
6496                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6497                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6498                 kvm_x86_ops->flush_log_dirty = NULL;
6499                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6500         }
6501
6502         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6503                 u64 vmx_msr;
6504
6505                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6506                 cpu_preemption_timer_multi =
6507                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6508         } else {
6509                 kvm_x86_ops->set_hv_timer = NULL;
6510                 kvm_x86_ops->cancel_hv_timer = NULL;
6511         }
6512
6513         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6514
6515         kvm_mce_cap_supported |= MCG_LMCE_P;
6516
6517         return alloc_kvm_area();
6518
6519 out8:
6520         free_page((unsigned long)vmx_vmwrite_bitmap);
6521 out7:
6522         free_page((unsigned long)vmx_vmread_bitmap);
6523 out6:
6524         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6525 out4:
6526         free_page((unsigned long)vmx_msr_bitmap_longmode);
6527 out3:
6528         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6529 out2:
6530         free_page((unsigned long)vmx_msr_bitmap_legacy);
6531 out1:
6532         free_page((unsigned long)vmx_io_bitmap_b);
6533 out:
6534         free_page((unsigned long)vmx_io_bitmap_a);
6535
6536     return r;
6537 }
6538
6539 static __exit void hardware_unsetup(void)
6540 {
6541         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6542         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6543         free_page((unsigned long)vmx_msr_bitmap_legacy);
6544         free_page((unsigned long)vmx_msr_bitmap_longmode);
6545         free_page((unsigned long)vmx_io_bitmap_b);
6546         free_page((unsigned long)vmx_io_bitmap_a);
6547         free_page((unsigned long)vmx_vmwrite_bitmap);
6548         free_page((unsigned long)vmx_vmread_bitmap);
6549
6550         free_kvm_area();
6551 }
6552
6553 /*
6554  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6555  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6556  */
6557 static int handle_pause(struct kvm_vcpu *vcpu)
6558 {
6559         if (ple_gap)
6560                 grow_ple_window(vcpu);
6561
6562         skip_emulated_instruction(vcpu);
6563         kvm_vcpu_on_spin(vcpu);
6564
6565         return 1;
6566 }
6567
6568 static int handle_nop(struct kvm_vcpu *vcpu)
6569 {
6570         skip_emulated_instruction(vcpu);
6571         return 1;
6572 }
6573
6574 static int handle_mwait(struct kvm_vcpu *vcpu)
6575 {
6576         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6577         return handle_nop(vcpu);
6578 }
6579
6580 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6581 {
6582         return 1;
6583 }
6584
6585 static int handle_monitor(struct kvm_vcpu *vcpu)
6586 {
6587         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6588         return handle_nop(vcpu);
6589 }
6590
6591 /*
6592  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6593  * We could reuse a single VMCS for all the L2 guests, but we also want the
6594  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6595  * allows keeping them loaded on the processor, and in the future will allow
6596  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6597  * every entry if they never change.
6598  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6599  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6600  *
6601  * The following functions allocate and free a vmcs02 in this pool.
6602  */
6603
6604 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6605 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6606 {
6607         struct vmcs02_list *item;
6608         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6609                 if (item->vmptr == vmx->nested.current_vmptr) {
6610                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6611                         return &item->vmcs02;
6612                 }
6613
6614         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6615                 /* Recycle the least recently used VMCS. */
6616                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6617                                        struct vmcs02_list, list);
6618                 item->vmptr = vmx->nested.current_vmptr;
6619                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6620                 return &item->vmcs02;
6621         }
6622
6623         /* Create a new VMCS */
6624         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6625         if (!item)
6626                 return NULL;
6627         item->vmcs02.vmcs = alloc_vmcs();
6628         if (!item->vmcs02.vmcs) {
6629                 kfree(item);
6630                 return NULL;
6631         }
6632         loaded_vmcs_init(&item->vmcs02);
6633         item->vmptr = vmx->nested.current_vmptr;
6634         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6635         vmx->nested.vmcs02_num++;
6636         return &item->vmcs02;
6637 }
6638
6639 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6640 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6641 {
6642         struct vmcs02_list *item;
6643         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6644                 if (item->vmptr == vmptr) {
6645                         free_loaded_vmcs(&item->vmcs02);
6646                         list_del(&item->list);
6647                         kfree(item);
6648                         vmx->nested.vmcs02_num--;
6649                         return;
6650                 }
6651 }
6652
6653 /*
6654  * Free all VMCSs saved for this vcpu, except the one pointed by
6655  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6656  * must be &vmx->vmcs01.
6657  */
6658 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6659 {
6660         struct vmcs02_list *item, *n;
6661
6662         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6663         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6664                 /*
6665                  * Something will leak if the above WARN triggers.  Better than
6666                  * a use-after-free.
6667                  */
6668                 if (vmx->loaded_vmcs == &item->vmcs02)
6669                         continue;
6670
6671                 free_loaded_vmcs(&item->vmcs02);
6672                 list_del(&item->list);
6673                 kfree(item);
6674                 vmx->nested.vmcs02_num--;
6675         }
6676 }
6677
6678 /*
6679  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6680  * set the success or error code of an emulated VMX instruction, as specified
6681  * by Vol 2B, VMX Instruction Reference, "Conventions".
6682  */
6683 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6684 {
6685         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6686                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6687                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6688 }
6689
6690 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6691 {
6692         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6693                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6694                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6695                         | X86_EFLAGS_CF);
6696 }
6697
6698 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6699                                         u32 vm_instruction_error)
6700 {
6701         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6702                 /*
6703                  * failValid writes the error number to the current VMCS, which
6704                  * can't be done there isn't a current VMCS.
6705                  */
6706                 nested_vmx_failInvalid(vcpu);
6707                 return;
6708         }
6709         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6710                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6711                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6712                         | X86_EFLAGS_ZF);
6713         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6714         /*
6715          * We don't need to force a shadow sync because
6716          * VM_INSTRUCTION_ERROR is not shadowed
6717          */
6718 }
6719
6720 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6721 {
6722         /* TODO: not to reset guest simply here. */
6723         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6724         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6725 }
6726
6727 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6728 {
6729         struct vcpu_vmx *vmx =
6730                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6731
6732         vmx->nested.preemption_timer_expired = true;
6733         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6734         kvm_vcpu_kick(&vmx->vcpu);
6735
6736         return HRTIMER_NORESTART;
6737 }
6738
6739 /*
6740  * Decode the memory-address operand of a vmx instruction, as recorded on an
6741  * exit caused by such an instruction (run by a guest hypervisor).
6742  * On success, returns 0. When the operand is invalid, returns 1 and throws
6743  * #UD or #GP.
6744  */
6745 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6746                                  unsigned long exit_qualification,
6747                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6748 {
6749         gva_t off;
6750         bool exn;
6751         struct kvm_segment s;
6752
6753         /*
6754          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6755          * Execution", on an exit, vmx_instruction_info holds most of the
6756          * addressing components of the operand. Only the displacement part
6757          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6758          * For how an actual address is calculated from all these components,
6759          * refer to Vol. 1, "Operand Addressing".
6760          */
6761         int  scaling = vmx_instruction_info & 3;
6762         int  addr_size = (vmx_instruction_info >> 7) & 7;
6763         bool is_reg = vmx_instruction_info & (1u << 10);
6764         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6765         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6766         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6767         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6768         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6769
6770         if (is_reg) {
6771                 kvm_queue_exception(vcpu, UD_VECTOR);
6772                 return 1;
6773         }
6774
6775         /* Addr = segment_base + offset */
6776         /* offset = base + [index * scale] + displacement */
6777         off = exit_qualification; /* holds the displacement */
6778         if (base_is_valid)
6779                 off += kvm_register_read(vcpu, base_reg);
6780         if (index_is_valid)
6781                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6782         vmx_get_segment(vcpu, &s, seg_reg);
6783         *ret = s.base + off;
6784
6785         if (addr_size == 1) /* 32 bit */
6786                 *ret &= 0xffffffff;
6787
6788         /* Checks for #GP/#SS exceptions. */
6789         exn = false;
6790         if (is_long_mode(vcpu)) {
6791                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6792                  * non-canonical form. This is the only check on the memory
6793                  * destination for long mode!
6794                  */
6795                 exn = is_noncanonical_address(*ret);
6796         } else if (is_protmode(vcpu)) {
6797                 /* Protected mode: apply checks for segment validity in the
6798                  * following order:
6799                  * - segment type check (#GP(0) may be thrown)
6800                  * - usability check (#GP(0)/#SS(0))
6801                  * - limit check (#GP(0)/#SS(0))
6802                  */
6803                 if (wr)
6804                         /* #GP(0) if the destination operand is located in a
6805                          * read-only data segment or any code segment.
6806                          */
6807                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6808                 else
6809                         /* #GP(0) if the source operand is located in an
6810                          * execute-only code segment
6811                          */
6812                         exn = ((s.type & 0xa) == 8);
6813                 if (exn) {
6814                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6815                         return 1;
6816                 }
6817                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6818                  */
6819                 exn = (s.unusable != 0);
6820                 /* Protected mode: #GP(0)/#SS(0) if the memory
6821                  * operand is outside the segment limit.
6822                  */
6823                 exn = exn || (off + sizeof(u64) > s.limit);
6824         }
6825         if (exn) {
6826                 kvm_queue_exception_e(vcpu,
6827                                       seg_reg == VCPU_SREG_SS ?
6828                                                 SS_VECTOR : GP_VECTOR,
6829                                       0);
6830                 return 1;
6831         }
6832
6833         return 0;
6834 }
6835
6836 /*
6837  * This function performs the various checks including
6838  * - if it's 4KB aligned
6839  * - No bits beyond the physical address width are set
6840  * - Returns 0 on success or else 1
6841  * (Intel SDM Section 30.3)
6842  */
6843 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6844                                   gpa_t *vmpointer)
6845 {
6846         gva_t gva;
6847         gpa_t vmptr;
6848         struct x86_exception e;
6849         struct page *page;
6850         struct vcpu_vmx *vmx = to_vmx(vcpu);
6851         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6852
6853         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6854                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6855                 return 1;
6856
6857         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6858                                 sizeof(vmptr), &e)) {
6859                 kvm_inject_page_fault(vcpu, &e);
6860                 return 1;
6861         }
6862
6863         switch (exit_reason) {
6864         case EXIT_REASON_VMON:
6865                 /*
6866                  * SDM 3: 24.11.5
6867                  * The first 4 bytes of VMXON region contain the supported
6868                  * VMCS revision identifier
6869                  *
6870                  * Note - IA32_VMX_BASIC[48] will never be 1
6871                  * for the nested case;
6872                  * which replaces physical address width with 32
6873                  *
6874                  */
6875                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6876                         nested_vmx_failInvalid(vcpu);
6877                         skip_emulated_instruction(vcpu);
6878                         return 1;
6879                 }
6880
6881                 page = nested_get_page(vcpu, vmptr);
6882                 if (page == NULL ||
6883                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6884                         nested_vmx_failInvalid(vcpu);
6885                         kunmap(page);
6886                         skip_emulated_instruction(vcpu);
6887                         return 1;
6888                 }
6889                 kunmap(page);
6890                 vmx->nested.vmxon_ptr = vmptr;
6891                 break;
6892         case EXIT_REASON_VMCLEAR:
6893                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6894                         nested_vmx_failValid(vcpu,
6895                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6896                         skip_emulated_instruction(vcpu);
6897                         return 1;
6898                 }
6899
6900                 if (vmptr == vmx->nested.vmxon_ptr) {
6901                         nested_vmx_failValid(vcpu,
6902                                              VMXERR_VMCLEAR_VMXON_POINTER);
6903                         skip_emulated_instruction(vcpu);
6904                         return 1;
6905                 }
6906                 break;
6907         case EXIT_REASON_VMPTRLD:
6908                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6909                         nested_vmx_failValid(vcpu,
6910                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6911                         skip_emulated_instruction(vcpu);
6912                         return 1;
6913                 }
6914
6915                 if (vmptr == vmx->nested.vmxon_ptr) {
6916                         nested_vmx_failValid(vcpu,
6917                                              VMXERR_VMCLEAR_VMXON_POINTER);
6918                         skip_emulated_instruction(vcpu);
6919                         return 1;
6920                 }
6921                 break;
6922         default:
6923                 return 1; /* shouldn't happen */
6924         }
6925
6926         if (vmpointer)
6927                 *vmpointer = vmptr;
6928         return 0;
6929 }
6930
6931 /*
6932  * Emulate the VMXON instruction.
6933  * Currently, we just remember that VMX is active, and do not save or even
6934  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6935  * do not currently need to store anything in that guest-allocated memory
6936  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6937  * argument is different from the VMXON pointer (which the spec says they do).
6938  */
6939 static int handle_vmon(struct kvm_vcpu *vcpu)
6940 {
6941         struct kvm_segment cs;
6942         struct vcpu_vmx *vmx = to_vmx(vcpu);
6943         struct vmcs *shadow_vmcs;
6944         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6945                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6946
6947         /* The Intel VMX Instruction Reference lists a bunch of bits that
6948          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6949          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6950          * Otherwise, we should fail with #UD. We test these now:
6951          */
6952         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6953             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6954             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6955                 kvm_queue_exception(vcpu, UD_VECTOR);
6956                 return 1;
6957         }
6958
6959         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6960         if (is_long_mode(vcpu) && !cs.l) {
6961                 kvm_queue_exception(vcpu, UD_VECTOR);
6962                 return 1;
6963         }
6964
6965         if (vmx_get_cpl(vcpu)) {
6966                 kvm_inject_gp(vcpu, 0);
6967                 return 1;
6968         }
6969
6970         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6971                 return 1;
6972
6973         if (vmx->nested.vmxon) {
6974                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6975                 skip_emulated_instruction(vcpu);
6976                 return 1;
6977         }
6978
6979         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6980                         != VMXON_NEEDED_FEATURES) {
6981                 kvm_inject_gp(vcpu, 0);
6982                 return 1;
6983         }
6984
6985         if (cpu_has_vmx_msr_bitmap()) {
6986                 vmx->nested.msr_bitmap =
6987                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6988                 if (!vmx->nested.msr_bitmap)
6989                         goto out_msr_bitmap;
6990         }
6991
6992         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
6993         if (!vmx->nested.cached_vmcs12)
6994                 goto out_cached_vmcs12;
6995
6996         if (enable_shadow_vmcs) {
6997                 shadow_vmcs = alloc_vmcs();
6998                 if (!shadow_vmcs)
6999                         goto out_shadow_vmcs;
7000                 /* mark vmcs as shadow */
7001                 shadow_vmcs->revision_id |= (1u << 31);
7002                 /* init shadow vmcs */
7003                 vmcs_clear(shadow_vmcs);
7004                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
7005         }
7006
7007         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7008         vmx->nested.vmcs02_num = 0;
7009
7010         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7011                      HRTIMER_MODE_REL);
7012         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7013
7014         vmx->nested.vmxon = true;
7015
7016         skip_emulated_instruction(vcpu);
7017         nested_vmx_succeed(vcpu);
7018         return 1;
7019
7020 out_shadow_vmcs:
7021         kfree(vmx->nested.cached_vmcs12);
7022
7023 out_cached_vmcs12:
7024         free_page((unsigned long)vmx->nested.msr_bitmap);
7025
7026 out_msr_bitmap:
7027         return -ENOMEM;
7028 }
7029
7030 /*
7031  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7032  * for running VMX instructions (except VMXON, whose prerequisites are
7033  * slightly different). It also specifies what exception to inject otherwise.
7034  */
7035 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7036 {
7037         struct kvm_segment cs;
7038         struct vcpu_vmx *vmx = to_vmx(vcpu);
7039
7040         if (!vmx->nested.vmxon) {
7041                 kvm_queue_exception(vcpu, UD_VECTOR);
7042                 return 0;
7043         }
7044
7045         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7046         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7047             (is_long_mode(vcpu) && !cs.l)) {
7048                 kvm_queue_exception(vcpu, UD_VECTOR);
7049                 return 0;
7050         }
7051
7052         if (vmx_get_cpl(vcpu)) {
7053                 kvm_inject_gp(vcpu, 0);
7054                 return 0;
7055         }
7056
7057         return 1;
7058 }
7059
7060 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7061 {
7062         if (vmx->nested.current_vmptr == -1ull)
7063                 return;
7064
7065         /* current_vmptr and current_vmcs12 are always set/reset together */
7066         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7067                 return;
7068
7069         if (enable_shadow_vmcs) {
7070                 /* copy to memory all shadowed fields in case
7071                    they were modified */
7072                 copy_shadow_to_vmcs12(vmx);
7073                 vmx->nested.sync_shadow_vmcs = false;
7074                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7075                                 SECONDARY_EXEC_SHADOW_VMCS);
7076                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7077         }
7078         vmx->nested.posted_intr_nv = -1;
7079
7080         /* Flush VMCS12 to guest memory */
7081         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7082                VMCS12_SIZE);
7083
7084         kunmap(vmx->nested.current_vmcs12_page);
7085         nested_release_page(vmx->nested.current_vmcs12_page);
7086         vmx->nested.current_vmptr = -1ull;
7087         vmx->nested.current_vmcs12 = NULL;
7088 }
7089
7090 /*
7091  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7092  * just stops using VMX.
7093  */
7094 static void free_nested(struct vcpu_vmx *vmx)
7095 {
7096         if (!vmx->nested.vmxon)
7097                 return;
7098
7099         vmx->nested.vmxon = false;
7100         free_vpid(vmx->nested.vpid02);
7101         nested_release_vmcs12(vmx);
7102         if (vmx->nested.msr_bitmap) {
7103                 free_page((unsigned long)vmx->nested.msr_bitmap);
7104                 vmx->nested.msr_bitmap = NULL;
7105         }
7106         if (enable_shadow_vmcs)
7107                 free_vmcs(vmx->nested.current_shadow_vmcs);
7108         kfree(vmx->nested.cached_vmcs12);
7109         /* Unpin physical memory we referred to in current vmcs02 */
7110         if (vmx->nested.apic_access_page) {
7111                 nested_release_page(vmx->nested.apic_access_page);
7112                 vmx->nested.apic_access_page = NULL;
7113         }
7114         if (vmx->nested.virtual_apic_page) {
7115                 nested_release_page(vmx->nested.virtual_apic_page);
7116                 vmx->nested.virtual_apic_page = NULL;
7117         }
7118         if (vmx->nested.pi_desc_page) {
7119                 kunmap(vmx->nested.pi_desc_page);
7120                 nested_release_page(vmx->nested.pi_desc_page);
7121                 vmx->nested.pi_desc_page = NULL;
7122                 vmx->nested.pi_desc = NULL;
7123         }
7124
7125         nested_free_all_saved_vmcss(vmx);
7126 }
7127
7128 /* Emulate the VMXOFF instruction */
7129 static int handle_vmoff(struct kvm_vcpu *vcpu)
7130 {
7131         if (!nested_vmx_check_permission(vcpu))
7132                 return 1;
7133         free_nested(to_vmx(vcpu));
7134         skip_emulated_instruction(vcpu);
7135         nested_vmx_succeed(vcpu);
7136         return 1;
7137 }
7138
7139 /* Emulate the VMCLEAR instruction */
7140 static int handle_vmclear(struct kvm_vcpu *vcpu)
7141 {
7142         struct vcpu_vmx *vmx = to_vmx(vcpu);
7143         gpa_t vmptr;
7144         struct vmcs12 *vmcs12;
7145         struct page *page;
7146
7147         if (!nested_vmx_check_permission(vcpu))
7148                 return 1;
7149
7150         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7151                 return 1;
7152
7153         if (vmptr == vmx->nested.current_vmptr)
7154                 nested_release_vmcs12(vmx);
7155
7156         page = nested_get_page(vcpu, vmptr);
7157         if (page == NULL) {
7158                 /*
7159                  * For accurate processor emulation, VMCLEAR beyond available
7160                  * physical memory should do nothing at all. However, it is
7161                  * possible that a nested vmx bug, not a guest hypervisor bug,
7162                  * resulted in this case, so let's shut down before doing any
7163                  * more damage:
7164                  */
7165                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7166                 return 1;
7167         }
7168         vmcs12 = kmap(page);
7169         vmcs12->launch_state = 0;
7170         kunmap(page);
7171         nested_release_page(page);
7172
7173         nested_free_vmcs02(vmx, vmptr);
7174
7175         skip_emulated_instruction(vcpu);
7176         nested_vmx_succeed(vcpu);
7177         return 1;
7178 }
7179
7180 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7181
7182 /* Emulate the VMLAUNCH instruction */
7183 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7184 {
7185         return nested_vmx_run(vcpu, true);
7186 }
7187
7188 /* Emulate the VMRESUME instruction */
7189 static int handle_vmresume(struct kvm_vcpu *vcpu)
7190 {
7191
7192         return nested_vmx_run(vcpu, false);
7193 }
7194
7195 enum vmcs_field_type {
7196         VMCS_FIELD_TYPE_U16 = 0,
7197         VMCS_FIELD_TYPE_U64 = 1,
7198         VMCS_FIELD_TYPE_U32 = 2,
7199         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7200 };
7201
7202 static inline int vmcs_field_type(unsigned long field)
7203 {
7204         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7205                 return VMCS_FIELD_TYPE_U32;
7206         return (field >> 13) & 0x3 ;
7207 }
7208
7209 static inline int vmcs_field_readonly(unsigned long field)
7210 {
7211         return (((field >> 10) & 0x3) == 1);
7212 }
7213
7214 /*
7215  * Read a vmcs12 field. Since these can have varying lengths and we return
7216  * one type, we chose the biggest type (u64) and zero-extend the return value
7217  * to that size. Note that the caller, handle_vmread, might need to use only
7218  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7219  * 64-bit fields are to be returned).
7220  */
7221 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7222                                   unsigned long field, u64 *ret)
7223 {
7224         short offset = vmcs_field_to_offset(field);
7225         char *p;
7226
7227         if (offset < 0)
7228                 return offset;
7229
7230         p = ((char *)(get_vmcs12(vcpu))) + offset;
7231
7232         switch (vmcs_field_type(field)) {
7233         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7234                 *ret = *((natural_width *)p);
7235                 return 0;
7236         case VMCS_FIELD_TYPE_U16:
7237                 *ret = *((u16 *)p);
7238                 return 0;
7239         case VMCS_FIELD_TYPE_U32:
7240                 *ret = *((u32 *)p);
7241                 return 0;
7242         case VMCS_FIELD_TYPE_U64:
7243                 *ret = *((u64 *)p);
7244                 return 0;
7245         default:
7246                 WARN_ON(1);
7247                 return -ENOENT;
7248         }
7249 }
7250
7251
7252 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7253                                    unsigned long field, u64 field_value){
7254         short offset = vmcs_field_to_offset(field);
7255         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7256         if (offset < 0)
7257                 return offset;
7258
7259         switch (vmcs_field_type(field)) {
7260         case VMCS_FIELD_TYPE_U16:
7261                 *(u16 *)p = field_value;
7262                 return 0;
7263         case VMCS_FIELD_TYPE_U32:
7264                 *(u32 *)p = field_value;
7265                 return 0;
7266         case VMCS_FIELD_TYPE_U64:
7267                 *(u64 *)p = field_value;
7268                 return 0;
7269         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7270                 *(natural_width *)p = field_value;
7271                 return 0;
7272         default:
7273                 WARN_ON(1);
7274                 return -ENOENT;
7275         }
7276
7277 }
7278
7279 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7280 {
7281         int i;
7282         unsigned long field;
7283         u64 field_value;
7284         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7285         const unsigned long *fields = shadow_read_write_fields;
7286         const int num_fields = max_shadow_read_write_fields;
7287
7288         preempt_disable();
7289
7290         vmcs_load(shadow_vmcs);
7291
7292         for (i = 0; i < num_fields; i++) {
7293                 field = fields[i];
7294                 switch (vmcs_field_type(field)) {
7295                 case VMCS_FIELD_TYPE_U16:
7296                         field_value = vmcs_read16(field);
7297                         break;
7298                 case VMCS_FIELD_TYPE_U32:
7299                         field_value = vmcs_read32(field);
7300                         break;
7301                 case VMCS_FIELD_TYPE_U64:
7302                         field_value = vmcs_read64(field);
7303                         break;
7304                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7305                         field_value = vmcs_readl(field);
7306                         break;
7307                 default:
7308                         WARN_ON(1);
7309                         continue;
7310                 }
7311                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7312         }
7313
7314         vmcs_clear(shadow_vmcs);
7315         vmcs_load(vmx->loaded_vmcs->vmcs);
7316
7317         preempt_enable();
7318 }
7319
7320 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7321 {
7322         const unsigned long *fields[] = {
7323                 shadow_read_write_fields,
7324                 shadow_read_only_fields
7325         };
7326         const int max_fields[] = {
7327                 max_shadow_read_write_fields,
7328                 max_shadow_read_only_fields
7329         };
7330         int i, q;
7331         unsigned long field;
7332         u64 field_value = 0;
7333         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7334
7335         vmcs_load(shadow_vmcs);
7336
7337         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7338                 for (i = 0; i < max_fields[q]; i++) {
7339                         field = fields[q][i];
7340                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7341
7342                         switch (vmcs_field_type(field)) {
7343                         case VMCS_FIELD_TYPE_U16:
7344                                 vmcs_write16(field, (u16)field_value);
7345                                 break;
7346                         case VMCS_FIELD_TYPE_U32:
7347                                 vmcs_write32(field, (u32)field_value);
7348                                 break;
7349                         case VMCS_FIELD_TYPE_U64:
7350                                 vmcs_write64(field, (u64)field_value);
7351                                 break;
7352                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7353                                 vmcs_writel(field, (long)field_value);
7354                                 break;
7355                         default:
7356                                 WARN_ON(1);
7357                                 break;
7358                         }
7359                 }
7360         }
7361
7362         vmcs_clear(shadow_vmcs);
7363         vmcs_load(vmx->loaded_vmcs->vmcs);
7364 }
7365
7366 /*
7367  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7368  * used before) all generate the same failure when it is missing.
7369  */
7370 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7371 {
7372         struct vcpu_vmx *vmx = to_vmx(vcpu);
7373         if (vmx->nested.current_vmptr == -1ull) {
7374                 nested_vmx_failInvalid(vcpu);
7375                 skip_emulated_instruction(vcpu);
7376                 return 0;
7377         }
7378         return 1;
7379 }
7380
7381 static int handle_vmread(struct kvm_vcpu *vcpu)
7382 {
7383         unsigned long field;
7384         u64 field_value;
7385         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7386         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7387         gva_t gva = 0;
7388
7389         if (!nested_vmx_check_permission(vcpu) ||
7390             !nested_vmx_check_vmcs12(vcpu))
7391                 return 1;
7392
7393         /* Decode instruction info and find the field to read */
7394         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7395         /* Read the field, zero-extended to a u64 field_value */
7396         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7397                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7398                 skip_emulated_instruction(vcpu);
7399                 return 1;
7400         }
7401         /*
7402          * Now copy part of this value to register or memory, as requested.
7403          * Note that the number of bits actually copied is 32 or 64 depending
7404          * on the guest's mode (32 or 64 bit), not on the given field's length.
7405          */
7406         if (vmx_instruction_info & (1u << 10)) {
7407                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7408                         field_value);
7409         } else {
7410                 if (get_vmx_mem_address(vcpu, exit_qualification,
7411                                 vmx_instruction_info, true, &gva))
7412                         return 1;
7413                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7414                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7415                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7416         }
7417
7418         nested_vmx_succeed(vcpu);
7419         skip_emulated_instruction(vcpu);
7420         return 1;
7421 }
7422
7423
7424 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7425 {
7426         unsigned long field;
7427         gva_t gva;
7428         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7429         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7430         /* The value to write might be 32 or 64 bits, depending on L1's long
7431          * mode, and eventually we need to write that into a field of several
7432          * possible lengths. The code below first zero-extends the value to 64
7433          * bit (field_value), and then copies only the appropriate number of
7434          * bits into the vmcs12 field.
7435          */
7436         u64 field_value = 0;
7437         struct x86_exception e;
7438
7439         if (!nested_vmx_check_permission(vcpu) ||
7440             !nested_vmx_check_vmcs12(vcpu))
7441                 return 1;
7442
7443         if (vmx_instruction_info & (1u << 10))
7444                 field_value = kvm_register_readl(vcpu,
7445                         (((vmx_instruction_info) >> 3) & 0xf));
7446         else {
7447                 if (get_vmx_mem_address(vcpu, exit_qualification,
7448                                 vmx_instruction_info, false, &gva))
7449                         return 1;
7450                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7451                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7452                         kvm_inject_page_fault(vcpu, &e);
7453                         return 1;
7454                 }
7455         }
7456
7457
7458         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7459         if (vmcs_field_readonly(field)) {
7460                 nested_vmx_failValid(vcpu,
7461                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7462                 skip_emulated_instruction(vcpu);
7463                 return 1;
7464         }
7465
7466         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7467                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7468                 skip_emulated_instruction(vcpu);
7469                 return 1;
7470         }
7471
7472         nested_vmx_succeed(vcpu);
7473         skip_emulated_instruction(vcpu);
7474         return 1;
7475 }
7476
7477 /* Emulate the VMPTRLD instruction */
7478 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7479 {
7480         struct vcpu_vmx *vmx = to_vmx(vcpu);
7481         gpa_t vmptr;
7482
7483         if (!nested_vmx_check_permission(vcpu))
7484                 return 1;
7485
7486         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7487                 return 1;
7488
7489         if (vmx->nested.current_vmptr != vmptr) {
7490                 struct vmcs12 *new_vmcs12;
7491                 struct page *page;
7492                 page = nested_get_page(vcpu, vmptr);
7493                 if (page == NULL) {
7494                         nested_vmx_failInvalid(vcpu);
7495                         skip_emulated_instruction(vcpu);
7496                         return 1;
7497                 }
7498                 new_vmcs12 = kmap(page);
7499                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7500                         kunmap(page);
7501                         nested_release_page_clean(page);
7502                         nested_vmx_failValid(vcpu,
7503                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7504                         skip_emulated_instruction(vcpu);
7505                         return 1;
7506                 }
7507
7508                 nested_release_vmcs12(vmx);
7509                 vmx->nested.current_vmptr = vmptr;
7510                 vmx->nested.current_vmcs12 = new_vmcs12;
7511                 vmx->nested.current_vmcs12_page = page;
7512                 /*
7513                  * Load VMCS12 from guest memory since it is not already
7514                  * cached.
7515                  */
7516                 memcpy(vmx->nested.cached_vmcs12,
7517                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7518
7519                 if (enable_shadow_vmcs) {
7520                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7521                                       SECONDARY_EXEC_SHADOW_VMCS);
7522                         vmcs_write64(VMCS_LINK_POINTER,
7523                                      __pa(vmx->nested.current_shadow_vmcs));
7524                         vmx->nested.sync_shadow_vmcs = true;
7525                 }
7526         }
7527
7528         nested_vmx_succeed(vcpu);
7529         skip_emulated_instruction(vcpu);
7530         return 1;
7531 }
7532
7533 /* Emulate the VMPTRST instruction */
7534 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7535 {
7536         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7537         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7538         gva_t vmcs_gva;
7539         struct x86_exception e;
7540
7541         if (!nested_vmx_check_permission(vcpu))
7542                 return 1;
7543
7544         if (get_vmx_mem_address(vcpu, exit_qualification,
7545                         vmx_instruction_info, true, &vmcs_gva))
7546                 return 1;
7547         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7548         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7549                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7550                                  sizeof(u64), &e)) {
7551                 kvm_inject_page_fault(vcpu, &e);
7552                 return 1;
7553         }
7554         nested_vmx_succeed(vcpu);
7555         skip_emulated_instruction(vcpu);
7556         return 1;
7557 }
7558
7559 /* Emulate the INVEPT instruction */
7560 static int handle_invept(struct kvm_vcpu *vcpu)
7561 {
7562         struct vcpu_vmx *vmx = to_vmx(vcpu);
7563         u32 vmx_instruction_info, types;
7564         unsigned long type;
7565         gva_t gva;
7566         struct x86_exception e;
7567         struct {
7568                 u64 eptp, gpa;
7569         } operand;
7570
7571         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7572               SECONDARY_EXEC_ENABLE_EPT) ||
7573             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7574                 kvm_queue_exception(vcpu, UD_VECTOR);
7575                 return 1;
7576         }
7577
7578         if (!nested_vmx_check_permission(vcpu))
7579                 return 1;
7580
7581         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7582                 kvm_queue_exception(vcpu, UD_VECTOR);
7583                 return 1;
7584         }
7585
7586         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7587         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7588
7589         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7590
7591         if (!(types & (1UL << type))) {
7592                 nested_vmx_failValid(vcpu,
7593                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7594                 skip_emulated_instruction(vcpu);
7595                 return 1;
7596         }
7597
7598         /* According to the Intel VMX instruction reference, the memory
7599          * operand is read even if it isn't needed (e.g., for type==global)
7600          */
7601         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7602                         vmx_instruction_info, false, &gva))
7603                 return 1;
7604         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7605                                 sizeof(operand), &e)) {
7606                 kvm_inject_page_fault(vcpu, &e);
7607                 return 1;
7608         }
7609
7610         switch (type) {
7611         case VMX_EPT_EXTENT_GLOBAL:
7612         /*
7613          * TODO: track mappings and invalidate
7614          * single context requests appropriately
7615          */
7616         case VMX_EPT_EXTENT_CONTEXT:
7617                 kvm_mmu_sync_roots(vcpu);
7618                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7619                 nested_vmx_succeed(vcpu);
7620                 break;
7621         default:
7622                 BUG_ON(1);
7623                 break;
7624         }
7625
7626         skip_emulated_instruction(vcpu);
7627         return 1;
7628 }
7629
7630 static int handle_invvpid(struct kvm_vcpu *vcpu)
7631 {
7632         struct vcpu_vmx *vmx = to_vmx(vcpu);
7633         u32 vmx_instruction_info;
7634         unsigned long type, types;
7635         gva_t gva;
7636         struct x86_exception e;
7637         int vpid;
7638
7639         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7640               SECONDARY_EXEC_ENABLE_VPID) ||
7641                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7642                 kvm_queue_exception(vcpu, UD_VECTOR);
7643                 return 1;
7644         }
7645
7646         if (!nested_vmx_check_permission(vcpu))
7647                 return 1;
7648
7649         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7650         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7651
7652         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7653
7654         if (!(types & (1UL << type))) {
7655                 nested_vmx_failValid(vcpu,
7656                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7657                 skip_emulated_instruction(vcpu);
7658                 return 1;
7659         }
7660
7661         /* according to the intel vmx instruction reference, the memory
7662          * operand is read even if it isn't needed (e.g., for type==global)
7663          */
7664         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7665                         vmx_instruction_info, false, &gva))
7666                 return 1;
7667         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7668                                 sizeof(u32), &e)) {
7669                 kvm_inject_page_fault(vcpu, &e);
7670                 return 1;
7671         }
7672
7673         switch (type) {
7674         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7675                 /*
7676                  * Old versions of KVM use the single-context version so we
7677                  * have to support it; just treat it the same as all-context.
7678                  */
7679         case VMX_VPID_EXTENT_ALL_CONTEXT:
7680                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7681                 nested_vmx_succeed(vcpu);
7682                 break;
7683         default:
7684                 /* Trap individual address invalidation invvpid calls */
7685                 BUG_ON(1);
7686                 break;
7687         }
7688
7689         skip_emulated_instruction(vcpu);
7690         return 1;
7691 }
7692
7693 static int handle_pml_full(struct kvm_vcpu *vcpu)
7694 {
7695         unsigned long exit_qualification;
7696
7697         trace_kvm_pml_full(vcpu->vcpu_id);
7698
7699         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7700
7701         /*
7702          * PML buffer FULL happened while executing iret from NMI,
7703          * "blocked by NMI" bit has to be set before next VM entry.
7704          */
7705         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7706                         cpu_has_virtual_nmis() &&
7707                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7708                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7709                                 GUEST_INTR_STATE_NMI);
7710
7711         /*
7712          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7713          * here.., and there's no userspace involvement needed for PML.
7714          */
7715         return 1;
7716 }
7717
7718 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7719 {
7720         kvm_lapic_expired_hv_timer(vcpu);
7721         return 1;
7722 }
7723
7724 /*
7725  * The exit handlers return 1 if the exit was handled fully and guest execution
7726  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7727  * to be done to userspace and return 0.
7728  */
7729 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7730         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7731         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7732         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7733         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7734         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7735         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7736         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7737         [EXIT_REASON_CPUID]                   = handle_cpuid,
7738         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7739         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7740         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7741         [EXIT_REASON_HLT]                     = handle_halt,
7742         [EXIT_REASON_INVD]                    = handle_invd,
7743         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7744         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7745         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7746         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7747         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7748         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7749         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7750         [EXIT_REASON_VMREAD]                  = handle_vmread,
7751         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7752         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7753         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7754         [EXIT_REASON_VMON]                    = handle_vmon,
7755         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7756         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7757         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7758         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7759         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7760         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7761         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7762         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7763         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7764         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7765         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7766         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7767         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7768         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7769         [EXIT_REASON_INVEPT]                  = handle_invept,
7770         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7771         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7772         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7773         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7774         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7775 };
7776
7777 static const int kvm_vmx_max_exit_handlers =
7778         ARRAY_SIZE(kvm_vmx_exit_handlers);
7779
7780 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7781                                        struct vmcs12 *vmcs12)
7782 {
7783         unsigned long exit_qualification;
7784         gpa_t bitmap, last_bitmap;
7785         unsigned int port;
7786         int size;
7787         u8 b;
7788
7789         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7790                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7791
7792         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7793
7794         port = exit_qualification >> 16;
7795         size = (exit_qualification & 7) + 1;
7796
7797         last_bitmap = (gpa_t)-1;
7798         b = -1;
7799
7800         while (size > 0) {
7801                 if (port < 0x8000)
7802                         bitmap = vmcs12->io_bitmap_a;
7803                 else if (port < 0x10000)
7804                         bitmap = vmcs12->io_bitmap_b;
7805                 else
7806                         return true;
7807                 bitmap += (port & 0x7fff) / 8;
7808
7809                 if (last_bitmap != bitmap)
7810                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7811                                 return true;
7812                 if (b & (1 << (port & 7)))
7813                         return true;
7814
7815                 port++;
7816                 size--;
7817                 last_bitmap = bitmap;
7818         }
7819
7820         return false;
7821 }
7822
7823 /*
7824  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7825  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7826  * disinterest in the current event (read or write a specific MSR) by using an
7827  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7828  */
7829 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7830         struct vmcs12 *vmcs12, u32 exit_reason)
7831 {
7832         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7833         gpa_t bitmap;
7834
7835         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7836                 return true;
7837
7838         /*
7839          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7840          * for the four combinations of read/write and low/high MSR numbers.
7841          * First we need to figure out which of the four to use:
7842          */
7843         bitmap = vmcs12->msr_bitmap;
7844         if (exit_reason == EXIT_REASON_MSR_WRITE)
7845                 bitmap += 2048;
7846         if (msr_index >= 0xc0000000) {
7847                 msr_index -= 0xc0000000;
7848                 bitmap += 1024;
7849         }
7850
7851         /* Then read the msr_index'th bit from this bitmap: */
7852         if (msr_index < 1024*8) {
7853                 unsigned char b;
7854                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7855                         return true;
7856                 return 1 & (b >> (msr_index & 7));
7857         } else
7858                 return true; /* let L1 handle the wrong parameter */
7859 }
7860
7861 /*
7862  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7863  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7864  * intercept (via guest_host_mask etc.) the current event.
7865  */
7866 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7867         struct vmcs12 *vmcs12)
7868 {
7869         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7870         int cr = exit_qualification & 15;
7871         int reg = (exit_qualification >> 8) & 15;
7872         unsigned long val = kvm_register_readl(vcpu, reg);
7873
7874         switch ((exit_qualification >> 4) & 3) {
7875         case 0: /* mov to cr */
7876                 switch (cr) {
7877                 case 0:
7878                         if (vmcs12->cr0_guest_host_mask &
7879                             (val ^ vmcs12->cr0_read_shadow))
7880                                 return true;
7881                         break;
7882                 case 3:
7883                         if ((vmcs12->cr3_target_count >= 1 &&
7884                                         vmcs12->cr3_target_value0 == val) ||
7885                                 (vmcs12->cr3_target_count >= 2 &&
7886                                         vmcs12->cr3_target_value1 == val) ||
7887                                 (vmcs12->cr3_target_count >= 3 &&
7888                                         vmcs12->cr3_target_value2 == val) ||
7889                                 (vmcs12->cr3_target_count >= 4 &&
7890                                         vmcs12->cr3_target_value3 == val))
7891                                 return false;
7892                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7893                                 return true;
7894                         break;
7895                 case 4:
7896                         if (vmcs12->cr4_guest_host_mask &
7897                             (vmcs12->cr4_read_shadow ^ val))
7898                                 return true;
7899                         break;
7900                 case 8:
7901                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7902                                 return true;
7903                         break;
7904                 }
7905                 break;
7906         case 2: /* clts */
7907                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7908                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7909                         return true;
7910                 break;
7911         case 1: /* mov from cr */
7912                 switch (cr) {
7913                 case 3:
7914                         if (vmcs12->cpu_based_vm_exec_control &
7915                             CPU_BASED_CR3_STORE_EXITING)
7916                                 return true;
7917                         break;
7918                 case 8:
7919                         if (vmcs12->cpu_based_vm_exec_control &
7920                             CPU_BASED_CR8_STORE_EXITING)
7921                                 return true;
7922                         break;
7923                 }
7924                 break;
7925         case 3: /* lmsw */
7926                 /*
7927                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7928                  * cr0. Other attempted changes are ignored, with no exit.
7929                  */
7930                 if (vmcs12->cr0_guest_host_mask & 0xe &
7931                     (val ^ vmcs12->cr0_read_shadow))
7932                         return true;
7933                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7934                     !(vmcs12->cr0_read_shadow & 0x1) &&
7935                     (val & 0x1))
7936                         return true;
7937                 break;
7938         }
7939         return false;
7940 }
7941
7942 /*
7943  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7944  * should handle it ourselves in L0 (and then continue L2). Only call this
7945  * when in is_guest_mode (L2).
7946  */
7947 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7948 {
7949         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7950         struct vcpu_vmx *vmx = to_vmx(vcpu);
7951         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7952         u32 exit_reason = vmx->exit_reason;
7953
7954         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7955                                 vmcs_readl(EXIT_QUALIFICATION),
7956                                 vmx->idt_vectoring_info,
7957                                 intr_info,
7958                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7959                                 KVM_ISA_VMX);
7960
7961         if (vmx->nested.nested_run_pending)
7962                 return false;
7963
7964         if (unlikely(vmx->fail)) {
7965                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7966                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7967                 return true;
7968         }
7969
7970         switch (exit_reason) {
7971         case EXIT_REASON_EXCEPTION_NMI:
7972                 if (!is_exception(intr_info))
7973                         return false;
7974                 else if (is_page_fault(intr_info))
7975                         return enable_ept;
7976                 else if (is_no_device(intr_info) &&
7977                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7978                         return false;
7979                 else if (is_debug(intr_info) &&
7980                          vcpu->guest_debug &
7981                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7982                         return false;
7983                 else if (is_breakpoint(intr_info) &&
7984                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7985                         return false;
7986                 return vmcs12->exception_bitmap &
7987                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7988         case EXIT_REASON_EXTERNAL_INTERRUPT:
7989                 return false;
7990         case EXIT_REASON_TRIPLE_FAULT:
7991                 return true;
7992         case EXIT_REASON_PENDING_INTERRUPT:
7993                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7994         case EXIT_REASON_NMI_WINDOW:
7995                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7996         case EXIT_REASON_TASK_SWITCH:
7997                 return true;
7998         case EXIT_REASON_CPUID:
7999                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
8000                         return false;
8001                 return true;
8002         case EXIT_REASON_HLT:
8003                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8004         case EXIT_REASON_INVD:
8005                 return true;
8006         case EXIT_REASON_INVLPG:
8007                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8008         case EXIT_REASON_RDPMC:
8009                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8010         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8011                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8012         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8013         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8014         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8015         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8016         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8017         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8018                 /*
8019                  * VMX instructions trap unconditionally. This allows L1 to
8020                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8021                  */
8022                 return true;
8023         case EXIT_REASON_CR_ACCESS:
8024                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8025         case EXIT_REASON_DR_ACCESS:
8026                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8027         case EXIT_REASON_IO_INSTRUCTION:
8028                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8029         case EXIT_REASON_MSR_READ:
8030         case EXIT_REASON_MSR_WRITE:
8031                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8032         case EXIT_REASON_INVALID_STATE:
8033                 return true;
8034         case EXIT_REASON_MWAIT_INSTRUCTION:
8035                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8036         case EXIT_REASON_MONITOR_TRAP_FLAG:
8037                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8038         case EXIT_REASON_MONITOR_INSTRUCTION:
8039                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8040         case EXIT_REASON_PAUSE_INSTRUCTION:
8041                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8042                         nested_cpu_has2(vmcs12,
8043                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8044         case EXIT_REASON_MCE_DURING_VMENTRY:
8045                 return false;
8046         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8047                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8048         case EXIT_REASON_APIC_ACCESS:
8049                 return nested_cpu_has2(vmcs12,
8050                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8051         case EXIT_REASON_APIC_WRITE:
8052         case EXIT_REASON_EOI_INDUCED:
8053                 /* apic_write and eoi_induced should exit unconditionally. */
8054                 return true;
8055         case EXIT_REASON_EPT_VIOLATION:
8056                 /*
8057                  * L0 always deals with the EPT violation. If nested EPT is
8058                  * used, and the nested mmu code discovers that the address is
8059                  * missing in the guest EPT table (EPT12), the EPT violation
8060                  * will be injected with nested_ept_inject_page_fault()
8061                  */
8062                 return false;
8063         case EXIT_REASON_EPT_MISCONFIG:
8064                 /*
8065                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8066                  * table (shadow on EPT) or a merged EPT table that L0 built
8067                  * (EPT on EPT). So any problems with the structure of the
8068                  * table is L0's fault.
8069                  */
8070                 return false;
8071         case EXIT_REASON_WBINVD:
8072                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8073         case EXIT_REASON_XSETBV:
8074                 return true;
8075         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8076                 /*
8077                  * This should never happen, since it is not possible to
8078                  * set XSS to a non-zero value---neither in L1 nor in L2.
8079                  * If if it were, XSS would have to be checked against
8080                  * the XSS exit bitmap in vmcs12.
8081                  */
8082                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8083         case EXIT_REASON_PREEMPTION_TIMER:
8084                 return false;
8085         default:
8086                 return true;
8087         }
8088 }
8089
8090 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8091 {
8092         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8093         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8094 }
8095
8096 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8097 {
8098         if (vmx->pml_pg) {
8099                 __free_page(vmx->pml_pg);
8100                 vmx->pml_pg = NULL;
8101         }
8102 }
8103
8104 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8105 {
8106         struct vcpu_vmx *vmx = to_vmx(vcpu);
8107         u64 *pml_buf;
8108         u16 pml_idx;
8109
8110         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8111
8112         /* Do nothing if PML buffer is empty */
8113         if (pml_idx == (PML_ENTITY_NUM - 1))
8114                 return;
8115
8116         /* PML index always points to next available PML buffer entity */
8117         if (pml_idx >= PML_ENTITY_NUM)
8118                 pml_idx = 0;
8119         else
8120                 pml_idx++;
8121
8122         pml_buf = page_address(vmx->pml_pg);
8123         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8124                 u64 gpa;
8125
8126                 gpa = pml_buf[pml_idx];
8127                 WARN_ON(gpa & (PAGE_SIZE - 1));
8128                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8129         }
8130
8131         /* reset PML index */
8132         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8133 }
8134
8135 /*
8136  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8137  * Called before reporting dirty_bitmap to userspace.
8138  */
8139 static void kvm_flush_pml_buffers(struct kvm *kvm)
8140 {
8141         int i;
8142         struct kvm_vcpu *vcpu;
8143         /*
8144          * We only need to kick vcpu out of guest mode here, as PML buffer
8145          * is flushed at beginning of all VMEXITs, and it's obvious that only
8146          * vcpus running in guest are possible to have unflushed GPAs in PML
8147          * buffer.
8148          */
8149         kvm_for_each_vcpu(i, vcpu, kvm)
8150                 kvm_vcpu_kick(vcpu);
8151 }
8152
8153 static void vmx_dump_sel(char *name, uint32_t sel)
8154 {
8155         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8156                name, vmcs_read32(sel),
8157                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8158                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8159                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8160 }
8161
8162 static void vmx_dump_dtsel(char *name, uint32_t limit)
8163 {
8164         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8165                name, vmcs_read32(limit),
8166                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8167 }
8168
8169 static void dump_vmcs(void)
8170 {
8171         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8172         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8173         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8174         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8175         u32 secondary_exec_control = 0;
8176         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8177         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8178         int i, n;
8179
8180         if (cpu_has_secondary_exec_ctrls())
8181                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8182
8183         pr_err("*** Guest State ***\n");
8184         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8185                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8186                vmcs_readl(CR0_GUEST_HOST_MASK));
8187         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8188                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8189         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8190         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8191             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8192         {
8193                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8194                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8195                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8196                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8197         }
8198         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8199                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8200         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8201                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8202         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8203                vmcs_readl(GUEST_SYSENTER_ESP),
8204                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8205         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8206         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8207         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8208         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8209         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8210         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8211         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8212         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8213         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8214         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8215         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8216             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8217                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8218                        efer, vmcs_read64(GUEST_IA32_PAT));
8219         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8220                vmcs_read64(GUEST_IA32_DEBUGCTL),
8221                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8222         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8223                 pr_err("PerfGlobCtl = 0x%016llx\n",
8224                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8225         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8226                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8227         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8228                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8229                vmcs_read32(GUEST_ACTIVITY_STATE));
8230         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8231                 pr_err("InterruptStatus = %04x\n",
8232                        vmcs_read16(GUEST_INTR_STATUS));
8233
8234         pr_err("*** Host State ***\n");
8235         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8236                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8237         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8238                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8239                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8240                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8241                vmcs_read16(HOST_TR_SELECTOR));
8242         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8243                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8244                vmcs_readl(HOST_TR_BASE));
8245         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8246                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8247         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8248                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8249                vmcs_readl(HOST_CR4));
8250         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8251                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8252                vmcs_read32(HOST_IA32_SYSENTER_CS),
8253                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8254         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8255                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8256                        vmcs_read64(HOST_IA32_EFER),
8257                        vmcs_read64(HOST_IA32_PAT));
8258         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8259                 pr_err("PerfGlobCtl = 0x%016llx\n",
8260                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8261
8262         pr_err("*** Control State ***\n");
8263         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8264                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8265         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8266         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8267                vmcs_read32(EXCEPTION_BITMAP),
8268                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8269                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8270         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8271                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8272                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8273                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8274         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8275                vmcs_read32(VM_EXIT_INTR_INFO),
8276                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8277                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8278         pr_err("        reason=%08x qualification=%016lx\n",
8279                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8280         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8281                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8282                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8283         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8284         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8285                 pr_err("TSC Multiplier = 0x%016llx\n",
8286                        vmcs_read64(TSC_MULTIPLIER));
8287         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8288                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8289         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8290                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8291         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8292                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8293         n = vmcs_read32(CR3_TARGET_COUNT);
8294         for (i = 0; i + 1 < n; i += 4)
8295                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8296                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8297                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8298         if (i < n)
8299                 pr_err("CR3 target%u=%016lx\n",
8300                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8301         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8302                 pr_err("PLE Gap=%08x Window=%08x\n",
8303                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8304         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8305                 pr_err("Virtual processor ID = 0x%04x\n",
8306                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8307 }
8308
8309 /*
8310  * The guest has exited.  See if we can fix it or if we need userspace
8311  * assistance.
8312  */
8313 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8314 {
8315         struct vcpu_vmx *vmx = to_vmx(vcpu);
8316         u32 exit_reason = vmx->exit_reason;
8317         u32 vectoring_info = vmx->idt_vectoring_info;
8318
8319         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8320
8321         /*
8322          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8323          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8324          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8325          * mode as if vcpus is in root mode, the PML buffer must has been
8326          * flushed already.
8327          */
8328         if (enable_pml)
8329                 vmx_flush_pml_buffer(vcpu);
8330
8331         /* If guest state is invalid, start emulating */
8332         if (vmx->emulation_required)
8333                 return handle_invalid_guest_state(vcpu);
8334
8335         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8336                 nested_vmx_vmexit(vcpu, exit_reason,
8337                                   vmcs_read32(VM_EXIT_INTR_INFO),
8338                                   vmcs_readl(EXIT_QUALIFICATION));
8339                 return 1;
8340         }
8341
8342         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8343                 dump_vmcs();
8344                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8345                 vcpu->run->fail_entry.hardware_entry_failure_reason
8346                         = exit_reason;
8347                 return 0;
8348         }
8349
8350         if (unlikely(vmx->fail)) {
8351                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8352                 vcpu->run->fail_entry.hardware_entry_failure_reason
8353                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8354                 return 0;
8355         }
8356
8357         /*
8358          * Note:
8359          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8360          * delivery event since it indicates guest is accessing MMIO.
8361          * The vm-exit can be triggered again after return to guest that
8362          * will cause infinite loop.
8363          */
8364         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8365                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8366                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8367                         exit_reason != EXIT_REASON_PML_FULL &&
8368                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8369                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8370                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8371                 vcpu->run->internal.ndata = 2;
8372                 vcpu->run->internal.data[0] = vectoring_info;
8373                 vcpu->run->internal.data[1] = exit_reason;
8374                 return 0;
8375         }
8376
8377         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8378             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8379                                         get_vmcs12(vcpu))))) {
8380                 if (vmx_interrupt_allowed(vcpu)) {
8381                         vmx->soft_vnmi_blocked = 0;
8382                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8383                            vcpu->arch.nmi_pending) {
8384                         /*
8385                          * This CPU don't support us in finding the end of an
8386                          * NMI-blocked window if the guest runs with IRQs
8387                          * disabled. So we pull the trigger after 1 s of
8388                          * futile waiting, but inform the user about this.
8389                          */
8390                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8391                                "state on VCPU %d after 1 s timeout\n",
8392                                __func__, vcpu->vcpu_id);
8393                         vmx->soft_vnmi_blocked = 0;
8394                 }
8395         }
8396
8397         if (exit_reason < kvm_vmx_max_exit_handlers
8398             && kvm_vmx_exit_handlers[exit_reason])
8399                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8400         else {
8401                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8402                 kvm_queue_exception(vcpu, UD_VECTOR);
8403                 return 1;
8404         }
8405 }
8406
8407 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8408 {
8409         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8410
8411         if (is_guest_mode(vcpu) &&
8412                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8413                 return;
8414
8415         if (irr == -1 || tpr < irr) {
8416                 vmcs_write32(TPR_THRESHOLD, 0);
8417                 return;
8418         }
8419
8420         vmcs_write32(TPR_THRESHOLD, irr);
8421 }
8422
8423 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8424 {
8425         u32 sec_exec_control;
8426
8427         /*
8428          * There is not point to enable virtualize x2apic without enable
8429          * apicv
8430          */
8431         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8432                                 !kvm_vcpu_apicv_active(vcpu))
8433                 return;
8434
8435         if (!cpu_need_tpr_shadow(vcpu))
8436                 return;
8437
8438         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8439
8440         if (set) {
8441                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8442                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8443         } else {
8444                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8445                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8446         }
8447         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8448
8449         vmx_set_msr_bitmap(vcpu);
8450 }
8451
8452 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8453 {
8454         struct vcpu_vmx *vmx = to_vmx(vcpu);
8455
8456         /*
8457          * Currently we do not handle the nested case where L2 has an
8458          * APIC access page of its own; that page is still pinned.
8459          * Hence, we skip the case where the VCPU is in guest mode _and_
8460          * L1 prepared an APIC access page for L2.
8461          *
8462          * For the case where L1 and L2 share the same APIC access page
8463          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8464          * in the vmcs12), this function will only update either the vmcs01
8465          * or the vmcs02.  If the former, the vmcs02 will be updated by
8466          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8467          * the next L2->L1 exit.
8468          */
8469         if (!is_guest_mode(vcpu) ||
8470             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8471                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8472                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8473 }
8474
8475 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8476 {
8477         u16 status;
8478         u8 old;
8479
8480         if (max_isr == -1)
8481                 max_isr = 0;
8482
8483         status = vmcs_read16(GUEST_INTR_STATUS);
8484         old = status >> 8;
8485         if (max_isr != old) {
8486                 status &= 0xff;
8487                 status |= max_isr << 8;
8488                 vmcs_write16(GUEST_INTR_STATUS, status);
8489         }
8490 }
8491
8492 static void vmx_set_rvi(int vector)
8493 {
8494         u16 status;
8495         u8 old;
8496
8497         if (vector == -1)
8498                 vector = 0;
8499
8500         status = vmcs_read16(GUEST_INTR_STATUS);
8501         old = (u8)status & 0xff;
8502         if ((u8)vector != old) {
8503                 status &= ~0xff;
8504                 status |= (u8)vector;
8505                 vmcs_write16(GUEST_INTR_STATUS, status);
8506         }
8507 }
8508
8509 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8510 {
8511         if (!is_guest_mode(vcpu)) {
8512                 vmx_set_rvi(max_irr);
8513                 return;
8514         }
8515
8516         if (max_irr == -1)
8517                 return;
8518
8519         /*
8520          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8521          * handles it.
8522          */
8523         if (nested_exit_on_intr(vcpu))
8524                 return;
8525
8526         /*
8527          * Else, fall back to pre-APICv interrupt injection since L2
8528          * is run without virtual interrupt delivery.
8529          */
8530         if (!kvm_event_needs_reinjection(vcpu) &&
8531             vmx_interrupt_allowed(vcpu)) {
8532                 kvm_queue_interrupt(vcpu, max_irr, false);
8533                 vmx_inject_irq(vcpu);
8534         }
8535 }
8536
8537 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8538 {
8539         if (!kvm_vcpu_apicv_active(vcpu))
8540                 return;
8541
8542         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8543         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8544         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8545         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8546 }
8547
8548 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8549 {
8550         u32 exit_intr_info;
8551
8552         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8553               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8554                 return;
8555
8556         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8557         exit_intr_info = vmx->exit_intr_info;
8558
8559         /* Handle machine checks before interrupts are enabled */
8560         if (is_machine_check(exit_intr_info))
8561                 kvm_machine_check();
8562
8563         /* We need to handle NMIs before interrupts are enabled */
8564         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8565             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8566                 kvm_before_handle_nmi(&vmx->vcpu);
8567                 asm("int $2");
8568                 kvm_after_handle_nmi(&vmx->vcpu);
8569         }
8570 }
8571
8572 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8573 {
8574         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8575         register void *__sp asm(_ASM_SP);
8576
8577         /*
8578          * If external interrupt exists, IF bit is set in rflags/eflags on the
8579          * interrupt stack frame, and interrupt will be enabled on a return
8580          * from interrupt handler.
8581          */
8582         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8583                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8584                 unsigned int vector;
8585                 unsigned long entry;
8586                 gate_desc *desc;
8587                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8588 #ifdef CONFIG_X86_64
8589                 unsigned long tmp;
8590 #endif
8591
8592                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8593                 desc = (gate_desc *)vmx->host_idt_base + vector;
8594                 entry = gate_offset(*desc);
8595                 asm volatile(
8596 #ifdef CONFIG_X86_64
8597                         "mov %%" _ASM_SP ", %[sp]\n\t"
8598                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8599                         "push $%c[ss]\n\t"
8600                         "push %[sp]\n\t"
8601 #endif
8602                         "pushf\n\t"
8603                         __ASM_SIZE(push) " $%c[cs]\n\t"
8604                         "call *%[entry]\n\t"
8605                         :
8606 #ifdef CONFIG_X86_64
8607                         [sp]"=&r"(tmp),
8608 #endif
8609                         "+r"(__sp)
8610                         :
8611                         [entry]"r"(entry),
8612                         [ss]"i"(__KERNEL_DS),
8613                         [cs]"i"(__KERNEL_CS)
8614                         );
8615         }
8616 }
8617
8618 static bool vmx_has_high_real_mode_segbase(void)
8619 {
8620         return enable_unrestricted_guest || emulate_invalid_guest_state;
8621 }
8622
8623 static bool vmx_mpx_supported(void)
8624 {
8625         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8626                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8627 }
8628
8629 static bool vmx_xsaves_supported(void)
8630 {
8631         return vmcs_config.cpu_based_2nd_exec_ctrl &
8632                 SECONDARY_EXEC_XSAVES;
8633 }
8634
8635 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8636 {
8637         u32 exit_intr_info;
8638         bool unblock_nmi;
8639         u8 vector;
8640         bool idtv_info_valid;
8641
8642         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8643
8644         if (cpu_has_virtual_nmis()) {
8645                 if (vmx->nmi_known_unmasked)
8646                         return;
8647                 /*
8648                  * Can't use vmx->exit_intr_info since we're not sure what
8649                  * the exit reason is.
8650                  */
8651                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8652                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8653                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8654                 /*
8655                  * SDM 3: 27.7.1.2 (September 2008)
8656                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8657                  * a guest IRET fault.
8658                  * SDM 3: 23.2.2 (September 2008)
8659                  * Bit 12 is undefined in any of the following cases:
8660                  *  If the VM exit sets the valid bit in the IDT-vectoring
8661                  *   information field.
8662                  *  If the VM exit is due to a double fault.
8663                  */
8664                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8665                     vector != DF_VECTOR && !idtv_info_valid)
8666                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8667                                       GUEST_INTR_STATE_NMI);
8668                 else
8669                         vmx->nmi_known_unmasked =
8670                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8671                                   & GUEST_INTR_STATE_NMI);
8672         } else if (unlikely(vmx->soft_vnmi_blocked))
8673                 vmx->vnmi_blocked_time +=
8674                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8675 }
8676
8677 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8678                                       u32 idt_vectoring_info,
8679                                       int instr_len_field,
8680                                       int error_code_field)
8681 {
8682         u8 vector;
8683         int type;
8684         bool idtv_info_valid;
8685
8686         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8687
8688         vcpu->arch.nmi_injected = false;
8689         kvm_clear_exception_queue(vcpu);
8690         kvm_clear_interrupt_queue(vcpu);
8691
8692         if (!idtv_info_valid)
8693                 return;
8694
8695         kvm_make_request(KVM_REQ_EVENT, vcpu);
8696
8697         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8698         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8699
8700         switch (type) {
8701         case INTR_TYPE_NMI_INTR:
8702                 vcpu->arch.nmi_injected = true;
8703                 /*
8704                  * SDM 3: 27.7.1.2 (September 2008)
8705                  * Clear bit "block by NMI" before VM entry if a NMI
8706                  * delivery faulted.
8707                  */
8708                 vmx_set_nmi_mask(vcpu, false);
8709                 break;
8710         case INTR_TYPE_SOFT_EXCEPTION:
8711                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8712                 /* fall through */
8713         case INTR_TYPE_HARD_EXCEPTION:
8714                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8715                         u32 err = vmcs_read32(error_code_field);
8716                         kvm_requeue_exception_e(vcpu, vector, err);
8717                 } else
8718                         kvm_requeue_exception(vcpu, vector);
8719                 break;
8720         case INTR_TYPE_SOFT_INTR:
8721                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8722                 /* fall through */
8723         case INTR_TYPE_EXT_INTR:
8724                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8725                 break;
8726         default:
8727                 break;
8728         }
8729 }
8730
8731 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8732 {
8733         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8734                                   VM_EXIT_INSTRUCTION_LEN,
8735                                   IDT_VECTORING_ERROR_CODE);
8736 }
8737
8738 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8739 {
8740         __vmx_complete_interrupts(vcpu,
8741                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8742                                   VM_ENTRY_INSTRUCTION_LEN,
8743                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8744
8745         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8746 }
8747
8748 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8749 {
8750         int i, nr_msrs;
8751         struct perf_guest_switch_msr *msrs;
8752
8753         msrs = perf_guest_get_msrs(&nr_msrs);
8754
8755         if (!msrs)
8756                 return;
8757
8758         for (i = 0; i < nr_msrs; i++)
8759                 if (msrs[i].host == msrs[i].guest)
8760                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8761                 else
8762                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8763                                         msrs[i].host);
8764 }
8765
8766 void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8767 {
8768         struct vcpu_vmx *vmx = to_vmx(vcpu);
8769         u64 tscl;
8770         u32 delta_tsc;
8771
8772         if (vmx->hv_deadline_tsc == -1)
8773                 return;
8774
8775         tscl = rdtsc();
8776         if (vmx->hv_deadline_tsc > tscl)
8777                 /* sure to be 32 bit only because checked on set_hv_timer */
8778                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8779                         cpu_preemption_timer_multi);
8780         else
8781                 delta_tsc = 0;
8782
8783         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8784 }
8785
8786 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8787 {
8788         struct vcpu_vmx *vmx = to_vmx(vcpu);
8789         unsigned long debugctlmsr, cr4;
8790
8791         /* Record the guest's net vcpu time for enforced NMI injections. */
8792         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8793                 vmx->entry_time = ktime_get();
8794
8795         /* Don't enter VMX if guest state is invalid, let the exit handler
8796            start emulation until we arrive back to a valid state */
8797         if (vmx->emulation_required)
8798                 return;
8799
8800         if (vmx->ple_window_dirty) {
8801                 vmx->ple_window_dirty = false;
8802                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8803         }
8804
8805         if (vmx->nested.sync_shadow_vmcs) {
8806                 copy_vmcs12_to_shadow(vmx);
8807                 vmx->nested.sync_shadow_vmcs = false;
8808         }
8809
8810         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8811                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8812         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8813                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8814
8815         cr4 = cr4_read_shadow();
8816         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8817                 vmcs_writel(HOST_CR4, cr4);
8818                 vmx->host_state.vmcs_host_cr4 = cr4;
8819         }
8820
8821         /* When single-stepping over STI and MOV SS, we must clear the
8822          * corresponding interruptibility bits in the guest state. Otherwise
8823          * vmentry fails as it then expects bit 14 (BS) in pending debug
8824          * exceptions being set, but that's not correct for the guest debugging
8825          * case. */
8826         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8827                 vmx_set_interrupt_shadow(vcpu, 0);
8828
8829         if (vmx->guest_pkru_valid)
8830                 __write_pkru(vmx->guest_pkru);
8831
8832         atomic_switch_perf_msrs(vmx);
8833         debugctlmsr = get_debugctlmsr();
8834
8835         vmx_arm_hv_timer(vcpu);
8836
8837         vmx->__launched = vmx->loaded_vmcs->launched;
8838         asm(
8839                 /* Store host registers */
8840                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8841                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8842                 "push %%" _ASM_CX " \n\t"
8843                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8844                 "je 1f \n\t"
8845                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8846                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8847                 "1: \n\t"
8848                 /* Reload cr2 if changed */
8849                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8850                 "mov %%cr2, %%" _ASM_DX " \n\t"
8851                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8852                 "je 2f \n\t"
8853                 "mov %%" _ASM_AX", %%cr2 \n\t"
8854                 "2: \n\t"
8855                 /* Check if vmlaunch of vmresume is needed */
8856                 "cmpl $0, %c[launched](%0) \n\t"
8857                 /* Load guest registers.  Don't clobber flags. */
8858                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8859                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8860                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8861                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8862                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8863                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8864 #ifdef CONFIG_X86_64
8865                 "mov %c[r8](%0),  %%r8  \n\t"
8866                 "mov %c[r9](%0),  %%r9  \n\t"
8867                 "mov %c[r10](%0), %%r10 \n\t"
8868                 "mov %c[r11](%0), %%r11 \n\t"
8869                 "mov %c[r12](%0), %%r12 \n\t"
8870                 "mov %c[r13](%0), %%r13 \n\t"
8871                 "mov %c[r14](%0), %%r14 \n\t"
8872                 "mov %c[r15](%0), %%r15 \n\t"
8873 #endif
8874                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8875
8876                 /* Enter guest mode */
8877                 "jne 1f \n\t"
8878                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8879                 "jmp 2f \n\t"
8880                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8881                 "2: "
8882                 /* Save guest registers, load host registers, keep flags */
8883                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8884                 "pop %0 \n\t"
8885                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8886                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8887                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8888                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8889                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8890                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8891                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8892 #ifdef CONFIG_X86_64
8893                 "mov %%r8,  %c[r8](%0) \n\t"
8894                 "mov %%r9,  %c[r9](%0) \n\t"
8895                 "mov %%r10, %c[r10](%0) \n\t"
8896                 "mov %%r11, %c[r11](%0) \n\t"
8897                 "mov %%r12, %c[r12](%0) \n\t"
8898                 "mov %%r13, %c[r13](%0) \n\t"
8899                 "mov %%r14, %c[r14](%0) \n\t"
8900                 "mov %%r15, %c[r15](%0) \n\t"
8901 #endif
8902                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8903                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8904
8905                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8906                 "setbe %c[fail](%0) \n\t"
8907                 ".pushsection .rodata \n\t"
8908                 ".global vmx_return \n\t"
8909                 "vmx_return: " _ASM_PTR " 2b \n\t"
8910                 ".popsection"
8911               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8912                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8913                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8914                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8915                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8916                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8917                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8918                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8919                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8920                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8921                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8922 #ifdef CONFIG_X86_64
8923                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8924                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8925                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8926                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8927                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8928                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8929                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8930                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8931 #endif
8932                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8933                 [wordsize]"i"(sizeof(ulong))
8934               : "cc", "memory"
8935 #ifdef CONFIG_X86_64
8936                 , "rax", "rbx", "rdi", "rsi"
8937                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8938 #else
8939                 , "eax", "ebx", "edi", "esi"
8940 #endif
8941               );
8942
8943         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8944         if (debugctlmsr)
8945                 update_debugctlmsr(debugctlmsr);
8946
8947 #ifndef CONFIG_X86_64
8948         /*
8949          * The sysexit path does not restore ds/es, so we must set them to
8950          * a reasonable value ourselves.
8951          *
8952          * We can't defer this to vmx_load_host_state() since that function
8953          * may be executed in interrupt context, which saves and restore segments
8954          * around it, nullifying its effect.
8955          */
8956         loadsegment(ds, __USER_DS);
8957         loadsegment(es, __USER_DS);
8958 #endif
8959
8960         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8961                                   | (1 << VCPU_EXREG_RFLAGS)
8962                                   | (1 << VCPU_EXREG_PDPTR)
8963                                   | (1 << VCPU_EXREG_SEGMENTS)
8964                                   | (1 << VCPU_EXREG_CR3));
8965         vcpu->arch.regs_dirty = 0;
8966
8967         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8968
8969         vmx->loaded_vmcs->launched = 1;
8970
8971         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8972
8973         /*
8974          * eager fpu is enabled if PKEY is supported and CR4 is switched
8975          * back on host, so it is safe to read guest PKRU from current
8976          * XSAVE.
8977          */
8978         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
8979                 vmx->guest_pkru = __read_pkru();
8980                 if (vmx->guest_pkru != vmx->host_pkru) {
8981                         vmx->guest_pkru_valid = true;
8982                         __write_pkru(vmx->host_pkru);
8983                 } else
8984                         vmx->guest_pkru_valid = false;
8985         }
8986
8987         /*
8988          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8989          * we did not inject a still-pending event to L1 now because of
8990          * nested_run_pending, we need to re-enable this bit.
8991          */
8992         if (vmx->nested.nested_run_pending)
8993                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8994
8995         vmx->nested.nested_run_pending = 0;
8996
8997         vmx_complete_atomic_exit(vmx);
8998         vmx_recover_nmi_blocking(vmx);
8999         vmx_complete_interrupts(vmx);
9000 }
9001
9002 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9003 {
9004         struct vcpu_vmx *vmx = to_vmx(vcpu);
9005         int cpu;
9006
9007         if (vmx->loaded_vmcs == &vmx->vmcs01)
9008                 return;
9009
9010         cpu = get_cpu();
9011         vmx->loaded_vmcs = &vmx->vmcs01;
9012         vmx_vcpu_put(vcpu);
9013         vmx_vcpu_load(vcpu, cpu);
9014         vcpu->cpu = cpu;
9015         put_cpu();
9016 }
9017
9018 /*
9019  * Ensure that the current vmcs of the logical processor is the
9020  * vmcs01 of the vcpu before calling free_nested().
9021  */
9022 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9023 {
9024        struct vcpu_vmx *vmx = to_vmx(vcpu);
9025        int r;
9026
9027        r = vcpu_load(vcpu);
9028        BUG_ON(r);
9029        vmx_load_vmcs01(vcpu);
9030        free_nested(vmx);
9031        vcpu_put(vcpu);
9032 }
9033
9034 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9035 {
9036         struct vcpu_vmx *vmx = to_vmx(vcpu);
9037
9038         if (enable_pml)
9039                 vmx_destroy_pml_buffer(vmx);
9040         free_vpid(vmx->vpid);
9041         leave_guest_mode(vcpu);
9042         vmx_free_vcpu_nested(vcpu);
9043         free_loaded_vmcs(vmx->loaded_vmcs);
9044         kfree(vmx->guest_msrs);
9045         kvm_vcpu_uninit(vcpu);
9046         kmem_cache_free(kvm_vcpu_cache, vmx);
9047 }
9048
9049 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9050 {
9051         int err;
9052         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9053         int cpu;
9054
9055         if (!vmx)
9056                 return ERR_PTR(-ENOMEM);
9057
9058         vmx->vpid = allocate_vpid();
9059
9060         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9061         if (err)
9062                 goto free_vcpu;
9063
9064         err = -ENOMEM;
9065
9066         /*
9067          * If PML is turned on, failure on enabling PML just results in failure
9068          * of creating the vcpu, therefore we can simplify PML logic (by
9069          * avoiding dealing with cases, such as enabling PML partially on vcpus
9070          * for the guest, etc.
9071          */
9072         if (enable_pml) {
9073                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9074                 if (!vmx->pml_pg)
9075                         goto uninit_vcpu;
9076         }
9077
9078         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9079         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9080                      > PAGE_SIZE);
9081
9082         if (!vmx->guest_msrs)
9083                 goto free_pml;
9084
9085         vmx->loaded_vmcs = &vmx->vmcs01;
9086         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9087         if (!vmx->loaded_vmcs->vmcs)
9088                 goto free_msrs;
9089         if (!vmm_exclusive)
9090                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9091         loaded_vmcs_init(vmx->loaded_vmcs);
9092         if (!vmm_exclusive)
9093                 kvm_cpu_vmxoff();
9094
9095         cpu = get_cpu();
9096         vmx_vcpu_load(&vmx->vcpu, cpu);
9097         vmx->vcpu.cpu = cpu;
9098         err = vmx_vcpu_setup(vmx);
9099         vmx_vcpu_put(&vmx->vcpu);
9100         put_cpu();
9101         if (err)
9102                 goto free_vmcs;
9103         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9104                 err = alloc_apic_access_page(kvm);
9105                 if (err)
9106                         goto free_vmcs;
9107         }
9108
9109         if (enable_ept) {
9110                 if (!kvm->arch.ept_identity_map_addr)
9111                         kvm->arch.ept_identity_map_addr =
9112                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9113                 err = init_rmode_identity_map(kvm);
9114                 if (err)
9115                         goto free_vmcs;
9116         }
9117
9118         if (nested) {
9119                 nested_vmx_setup_ctls_msrs(vmx);
9120                 vmx->nested.vpid02 = allocate_vpid();
9121         }
9122
9123         vmx->nested.posted_intr_nv = -1;
9124         vmx->nested.current_vmptr = -1ull;
9125         vmx->nested.current_vmcs12 = NULL;
9126
9127         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9128
9129         return &vmx->vcpu;
9130
9131 free_vmcs:
9132         free_vpid(vmx->nested.vpid02);
9133         free_loaded_vmcs(vmx->loaded_vmcs);
9134 free_msrs:
9135         kfree(vmx->guest_msrs);
9136 free_pml:
9137         vmx_destroy_pml_buffer(vmx);
9138 uninit_vcpu:
9139         kvm_vcpu_uninit(&vmx->vcpu);
9140 free_vcpu:
9141         free_vpid(vmx->vpid);
9142         kmem_cache_free(kvm_vcpu_cache, vmx);
9143         return ERR_PTR(err);
9144 }
9145
9146 static void __init vmx_check_processor_compat(void *rtn)
9147 {
9148         struct vmcs_config vmcs_conf;
9149
9150         *(int *)rtn = 0;
9151         if (setup_vmcs_config(&vmcs_conf) < 0)
9152                 *(int *)rtn = -EIO;
9153         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9154                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9155                                 smp_processor_id());
9156                 *(int *)rtn = -EIO;
9157         }
9158 }
9159
9160 static int get_ept_level(void)
9161 {
9162         return VMX_EPT_DEFAULT_GAW + 1;
9163 }
9164
9165 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9166 {
9167         u8 cache;
9168         u64 ipat = 0;
9169
9170         /* For VT-d and EPT combination
9171          * 1. MMIO: always map as UC
9172          * 2. EPT with VT-d:
9173          *   a. VT-d without snooping control feature: can't guarantee the
9174          *      result, try to trust guest.
9175          *   b. VT-d with snooping control feature: snooping control feature of
9176          *      VT-d engine can guarantee the cache correctness. Just set it
9177          *      to WB to keep consistent with host. So the same as item 3.
9178          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9179          *    consistent with host MTRR
9180          */
9181         if (is_mmio) {
9182                 cache = MTRR_TYPE_UNCACHABLE;
9183                 goto exit;
9184         }
9185
9186         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9187                 ipat = VMX_EPT_IPAT_BIT;
9188                 cache = MTRR_TYPE_WRBACK;
9189                 goto exit;
9190         }
9191
9192         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9193                 ipat = VMX_EPT_IPAT_BIT;
9194                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9195                         cache = MTRR_TYPE_WRBACK;
9196                 else
9197                         cache = MTRR_TYPE_UNCACHABLE;
9198                 goto exit;
9199         }
9200
9201         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9202
9203 exit:
9204         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9205 }
9206
9207 static int vmx_get_lpage_level(void)
9208 {
9209         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9210                 return PT_DIRECTORY_LEVEL;
9211         else
9212                 /* For shadow and EPT supported 1GB page */
9213                 return PT_PDPE_LEVEL;
9214 }
9215
9216 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9217 {
9218         /*
9219          * These bits in the secondary execution controls field
9220          * are dynamic, the others are mostly based on the hypervisor
9221          * architecture and the guest's CPUID.  Do not touch the
9222          * dynamic bits.
9223          */
9224         u32 mask =
9225                 SECONDARY_EXEC_SHADOW_VMCS |
9226                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9227                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9228
9229         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9230
9231         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9232                      (new_ctl & ~mask) | (cur_ctl & mask));
9233 }
9234
9235 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9236 {
9237         struct kvm_cpuid_entry2 *best;
9238         struct vcpu_vmx *vmx = to_vmx(vcpu);
9239         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9240
9241         if (vmx_rdtscp_supported()) {
9242                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9243                 if (!rdtscp_enabled)
9244                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9245
9246                 if (nested) {
9247                         if (rdtscp_enabled)
9248                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9249                                         SECONDARY_EXEC_RDTSCP;
9250                         else
9251                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9252                                         ~SECONDARY_EXEC_RDTSCP;
9253                 }
9254         }
9255
9256         /* Exposing INVPCID only when PCID is exposed */
9257         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9258         if (vmx_invpcid_supported() &&
9259             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9260             !guest_cpuid_has_pcid(vcpu))) {
9261                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9262
9263                 if (best)
9264                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9265         }
9266
9267         if (cpu_has_secondary_exec_ctrls())
9268                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9269
9270         if (nested_vmx_allowed(vcpu))
9271                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9272                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9273         else
9274                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9275                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9276 }
9277
9278 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9279 {
9280         if (func == 1 && nested)
9281                 entry->ecx |= bit(X86_FEATURE_VMX);
9282 }
9283
9284 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9285                 struct x86_exception *fault)
9286 {
9287         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9288         u32 exit_reason;
9289
9290         if (fault->error_code & PFERR_RSVD_MASK)
9291                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9292         else
9293                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9294         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9295         vmcs12->guest_physical_address = fault->address;
9296 }
9297
9298 /* Callbacks for nested_ept_init_mmu_context: */
9299
9300 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9301 {
9302         /* return the page table to be shadowed - in our case, EPT12 */
9303         return get_vmcs12(vcpu)->ept_pointer;
9304 }
9305
9306 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9307 {
9308         WARN_ON(mmu_is_nested(vcpu));
9309         kvm_init_shadow_ept_mmu(vcpu,
9310                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9311                         VMX_EPT_EXECUTE_ONLY_BIT);
9312         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9313         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9314         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9315
9316         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9317 }
9318
9319 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9320 {
9321         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9322 }
9323
9324 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9325                                             u16 error_code)
9326 {
9327         bool inequality, bit;
9328
9329         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9330         inequality =
9331                 (error_code & vmcs12->page_fault_error_code_mask) !=
9332                  vmcs12->page_fault_error_code_match;
9333         return inequality ^ bit;
9334 }
9335
9336 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9337                 struct x86_exception *fault)
9338 {
9339         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9340
9341         WARN_ON(!is_guest_mode(vcpu));
9342
9343         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9344                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9345                                   vmcs_read32(VM_EXIT_INTR_INFO),
9346                                   vmcs_readl(EXIT_QUALIFICATION));
9347         else
9348                 kvm_inject_page_fault(vcpu, fault);
9349 }
9350
9351 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9352                                         struct vmcs12 *vmcs12)
9353 {
9354         struct vcpu_vmx *vmx = to_vmx(vcpu);
9355         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9356
9357         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9358                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9359                     vmcs12->apic_access_addr >> maxphyaddr)
9360                         return false;
9361
9362                 /*
9363                  * Translate L1 physical address to host physical
9364                  * address for vmcs02. Keep the page pinned, so this
9365                  * physical address remains valid. We keep a reference
9366                  * to it so we can release it later.
9367                  */
9368                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9369                         nested_release_page(vmx->nested.apic_access_page);
9370                 vmx->nested.apic_access_page =
9371                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9372         }
9373
9374         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9375                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9376                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9377                         return false;
9378
9379                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9380                         nested_release_page(vmx->nested.virtual_apic_page);
9381                 vmx->nested.virtual_apic_page =
9382                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9383
9384                 /*
9385                  * Failing the vm entry is _not_ what the processor does
9386                  * but it's basically the only possibility we have.
9387                  * We could still enter the guest if CR8 load exits are
9388                  * enabled, CR8 store exits are enabled, and virtualize APIC
9389                  * access is disabled; in this case the processor would never
9390                  * use the TPR shadow and we could simply clear the bit from
9391                  * the execution control.  But such a configuration is useless,
9392                  * so let's keep the code simple.
9393                  */
9394                 if (!vmx->nested.virtual_apic_page)
9395                         return false;
9396         }
9397
9398         if (nested_cpu_has_posted_intr(vmcs12)) {
9399                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9400                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9401                         return false;
9402
9403                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9404                         kunmap(vmx->nested.pi_desc_page);
9405                         nested_release_page(vmx->nested.pi_desc_page);
9406                 }
9407                 vmx->nested.pi_desc_page =
9408                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9409                 if (!vmx->nested.pi_desc_page)
9410                         return false;
9411
9412                 vmx->nested.pi_desc =
9413                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9414                 if (!vmx->nested.pi_desc) {
9415                         nested_release_page_clean(vmx->nested.pi_desc_page);
9416                         return false;
9417                 }
9418                 vmx->nested.pi_desc =
9419                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9420                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9421                         (PAGE_SIZE - 1)));
9422         }
9423
9424         return true;
9425 }
9426
9427 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9428 {
9429         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9430         struct vcpu_vmx *vmx = to_vmx(vcpu);
9431
9432         if (vcpu->arch.virtual_tsc_khz == 0)
9433                 return;
9434
9435         /* Make sure short timeouts reliably trigger an immediate vmexit.
9436          * hrtimer_start does not guarantee this. */
9437         if (preemption_timeout <= 1) {
9438                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9439                 return;
9440         }
9441
9442         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9443         preemption_timeout *= 1000000;
9444         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9445         hrtimer_start(&vmx->nested.preemption_timer,
9446                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9447 }
9448
9449 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9450                                                 struct vmcs12 *vmcs12)
9451 {
9452         int maxphyaddr;
9453         u64 addr;
9454
9455         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9456                 return 0;
9457
9458         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9459                 WARN_ON(1);
9460                 return -EINVAL;
9461         }
9462         maxphyaddr = cpuid_maxphyaddr(vcpu);
9463
9464         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9465            ((addr + PAGE_SIZE) >> maxphyaddr))
9466                 return -EINVAL;
9467
9468         return 0;
9469 }
9470
9471 /*
9472  * Merge L0's and L1's MSR bitmap, return false to indicate that
9473  * we do not use the hardware.
9474  */
9475 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9476                                                struct vmcs12 *vmcs12)
9477 {
9478         int msr;
9479         struct page *page;
9480         unsigned long *msr_bitmap_l1;
9481         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9482
9483         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9484         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9485                 return false;
9486
9487         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9488         if (!page) {
9489                 WARN_ON(1);
9490                 return false;
9491         }
9492         msr_bitmap_l1 = (unsigned long *)kmap(page);
9493         if (!msr_bitmap_l1) {
9494                 nested_release_page_clean(page);
9495                 WARN_ON(1);
9496                 return false;
9497         }
9498
9499         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9500
9501         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9502                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9503                         for (msr = 0x800; msr <= 0x8ff; msr++)
9504                                 nested_vmx_disable_intercept_for_msr(
9505                                         msr_bitmap_l1, msr_bitmap_l0,
9506                                         msr, MSR_TYPE_R);
9507
9508                 nested_vmx_disable_intercept_for_msr(
9509                                 msr_bitmap_l1, msr_bitmap_l0,
9510                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9511                                 MSR_TYPE_R | MSR_TYPE_W);
9512
9513                 if (nested_cpu_has_vid(vmcs12)) {
9514                         nested_vmx_disable_intercept_for_msr(
9515                                 msr_bitmap_l1, msr_bitmap_l0,
9516                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9517                                 MSR_TYPE_W);
9518                         nested_vmx_disable_intercept_for_msr(
9519                                 msr_bitmap_l1, msr_bitmap_l0,
9520                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9521                                 MSR_TYPE_W);
9522                 }
9523         }
9524         kunmap(page);
9525         nested_release_page_clean(page);
9526
9527         return true;
9528 }
9529
9530 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9531                                            struct vmcs12 *vmcs12)
9532 {
9533         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9534             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9535             !nested_cpu_has_vid(vmcs12) &&
9536             !nested_cpu_has_posted_intr(vmcs12))
9537                 return 0;
9538
9539         /*
9540          * If virtualize x2apic mode is enabled,
9541          * virtualize apic access must be disabled.
9542          */
9543         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9544             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9545                 return -EINVAL;
9546
9547         /*
9548          * If virtual interrupt delivery is enabled,
9549          * we must exit on external interrupts.
9550          */
9551         if (nested_cpu_has_vid(vmcs12) &&
9552            !nested_exit_on_intr(vcpu))
9553                 return -EINVAL;
9554
9555         /*
9556          * bits 15:8 should be zero in posted_intr_nv,
9557          * the descriptor address has been already checked
9558          * in nested_get_vmcs12_pages.
9559          */
9560         if (nested_cpu_has_posted_intr(vmcs12) &&
9561            (!nested_cpu_has_vid(vmcs12) ||
9562             !nested_exit_intr_ack_set(vcpu) ||
9563             vmcs12->posted_intr_nv & 0xff00))
9564                 return -EINVAL;
9565
9566         /* tpr shadow is needed by all apicv features. */
9567         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9568                 return -EINVAL;
9569
9570         return 0;
9571 }
9572
9573 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9574                                        unsigned long count_field,
9575                                        unsigned long addr_field)
9576 {
9577         int maxphyaddr;
9578         u64 count, addr;
9579
9580         if (vmcs12_read_any(vcpu, count_field, &count) ||
9581             vmcs12_read_any(vcpu, addr_field, &addr)) {
9582                 WARN_ON(1);
9583                 return -EINVAL;
9584         }
9585         if (count == 0)
9586                 return 0;
9587         maxphyaddr = cpuid_maxphyaddr(vcpu);
9588         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9589             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9590                 pr_warn_ratelimited(
9591                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9592                         addr_field, maxphyaddr, count, addr);
9593                 return -EINVAL;
9594         }
9595         return 0;
9596 }
9597
9598 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9599                                                 struct vmcs12 *vmcs12)
9600 {
9601         if (vmcs12->vm_exit_msr_load_count == 0 &&
9602             vmcs12->vm_exit_msr_store_count == 0 &&
9603             vmcs12->vm_entry_msr_load_count == 0)
9604                 return 0; /* Fast path */
9605         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9606                                         VM_EXIT_MSR_LOAD_ADDR) ||
9607             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9608                                         VM_EXIT_MSR_STORE_ADDR) ||
9609             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9610                                         VM_ENTRY_MSR_LOAD_ADDR))
9611                 return -EINVAL;
9612         return 0;
9613 }
9614
9615 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9616                                        struct vmx_msr_entry *e)
9617 {
9618         /* x2APIC MSR accesses are not allowed */
9619         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9620                 return -EINVAL;
9621         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9622             e->index == MSR_IA32_UCODE_REV)
9623                 return -EINVAL;
9624         if (e->reserved != 0)
9625                 return -EINVAL;
9626         return 0;
9627 }
9628
9629 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9630                                      struct vmx_msr_entry *e)
9631 {
9632         if (e->index == MSR_FS_BASE ||
9633             e->index == MSR_GS_BASE ||
9634             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9635             nested_vmx_msr_check_common(vcpu, e))
9636                 return -EINVAL;
9637         return 0;
9638 }
9639
9640 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9641                                       struct vmx_msr_entry *e)
9642 {
9643         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9644             nested_vmx_msr_check_common(vcpu, e))
9645                 return -EINVAL;
9646         return 0;
9647 }
9648
9649 /*
9650  * Load guest's/host's msr at nested entry/exit.
9651  * return 0 for success, entry index for failure.
9652  */
9653 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9654 {
9655         u32 i;
9656         struct vmx_msr_entry e;
9657         struct msr_data msr;
9658
9659         msr.host_initiated = false;
9660         for (i = 0; i < count; i++) {
9661                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9662                                         &e, sizeof(e))) {
9663                         pr_warn_ratelimited(
9664                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9665                                 __func__, i, gpa + i * sizeof(e));
9666                         goto fail;
9667                 }
9668                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9669                         pr_warn_ratelimited(
9670                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9671                                 __func__, i, e.index, e.reserved);
9672                         goto fail;
9673                 }
9674                 msr.index = e.index;
9675                 msr.data = e.value;
9676                 if (kvm_set_msr(vcpu, &msr)) {
9677                         pr_warn_ratelimited(
9678                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9679                                 __func__, i, e.index, e.value);
9680                         goto fail;
9681                 }
9682         }
9683         return 0;
9684 fail:
9685         return i + 1;
9686 }
9687
9688 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9689 {
9690         u32 i;
9691         struct vmx_msr_entry e;
9692
9693         for (i = 0; i < count; i++) {
9694                 struct msr_data msr_info;
9695                 if (kvm_vcpu_read_guest(vcpu,
9696                                         gpa + i * sizeof(e),
9697                                         &e, 2 * sizeof(u32))) {
9698                         pr_warn_ratelimited(
9699                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9700                                 __func__, i, gpa + i * sizeof(e));
9701                         return -EINVAL;
9702                 }
9703                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9704                         pr_warn_ratelimited(
9705                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9706                                 __func__, i, e.index, e.reserved);
9707                         return -EINVAL;
9708                 }
9709                 msr_info.host_initiated = false;
9710                 msr_info.index = e.index;
9711                 if (kvm_get_msr(vcpu, &msr_info)) {
9712                         pr_warn_ratelimited(
9713                                 "%s cannot read MSR (%u, 0x%x)\n",
9714                                 __func__, i, e.index);
9715                         return -EINVAL;
9716                 }
9717                 if (kvm_vcpu_write_guest(vcpu,
9718                                          gpa + i * sizeof(e) +
9719                                              offsetof(struct vmx_msr_entry, value),
9720                                          &msr_info.data, sizeof(msr_info.data))) {
9721                         pr_warn_ratelimited(
9722                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9723                                 __func__, i, e.index, msr_info.data);
9724                         return -EINVAL;
9725                 }
9726         }
9727         return 0;
9728 }
9729
9730 /*
9731  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9732  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9733  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9734  * guest in a way that will both be appropriate to L1's requests, and our
9735  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9736  * function also has additional necessary side-effects, like setting various
9737  * vcpu->arch fields.
9738  */
9739 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9740 {
9741         struct vcpu_vmx *vmx = to_vmx(vcpu);
9742         u32 exec_control;
9743
9744         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9745         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9746         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9747         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9748         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9749         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9750         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9751         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9752         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9753         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9754         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9755         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9756         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9757         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9758         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9759         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9760         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9761         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9762         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9763         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9764         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9765         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9766         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9767         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9768         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9769         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9770         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9771         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9772         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9773         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9774         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9775         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9776         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9777         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9778         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9779         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9780
9781         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9782                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9783                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9784         } else {
9785                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9786                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9787         }
9788         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9789                 vmcs12->vm_entry_intr_info_field);
9790         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9791                 vmcs12->vm_entry_exception_error_code);
9792         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9793                 vmcs12->vm_entry_instruction_len);
9794         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9795                 vmcs12->guest_interruptibility_info);
9796         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9797         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9798         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9799                 vmcs12->guest_pending_dbg_exceptions);
9800         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9801         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9802
9803         if (nested_cpu_has_xsaves(vmcs12))
9804                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9805         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9806
9807         exec_control = vmcs12->pin_based_vm_exec_control;
9808
9809         /* Preemption timer setting is only taken from vmcs01.  */
9810         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9811         exec_control |= vmcs_config.pin_based_exec_ctrl;
9812         if (vmx->hv_deadline_tsc == -1)
9813                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9814
9815         /* Posted interrupts setting is only taken from vmcs12.  */
9816         if (nested_cpu_has_posted_intr(vmcs12)) {
9817                 /*
9818                  * Note that we use L0's vector here and in
9819                  * vmx_deliver_nested_posted_interrupt.
9820                  */
9821                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9822                 vmx->nested.pi_pending = false;
9823                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9824                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9825                         page_to_phys(vmx->nested.pi_desc_page) +
9826                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9827                         (PAGE_SIZE - 1)));
9828         } else
9829                 exec_control &= ~PIN_BASED_POSTED_INTR;
9830
9831         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9832
9833         vmx->nested.preemption_timer_expired = false;
9834         if (nested_cpu_has_preemption_timer(vmcs12))
9835                 vmx_start_preemption_timer(vcpu);
9836
9837         /*
9838          * Whether page-faults are trapped is determined by a combination of
9839          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9840          * If enable_ept, L0 doesn't care about page faults and we should
9841          * set all of these to L1's desires. However, if !enable_ept, L0 does
9842          * care about (at least some) page faults, and because it is not easy
9843          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9844          * to exit on each and every L2 page fault. This is done by setting
9845          * MASK=MATCH=0 and (see below) EB.PF=1.
9846          * Note that below we don't need special code to set EB.PF beyond the
9847          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9848          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9849          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9850          *
9851          * A problem with this approach (when !enable_ept) is that L1 may be
9852          * injected with more page faults than it asked for. This could have
9853          * caused problems, but in practice existing hypervisors don't care.
9854          * To fix this, we will need to emulate the PFEC checking (on the L1
9855          * page tables), using walk_addr(), when injecting PFs to L1.
9856          */
9857         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9858                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9859         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9860                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9861
9862         if (cpu_has_secondary_exec_ctrls()) {
9863                 exec_control = vmx_secondary_exec_control(vmx);
9864
9865                 /* Take the following fields only from vmcs12 */
9866                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9867                                   SECONDARY_EXEC_RDTSCP |
9868                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9869                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
9870                 if (nested_cpu_has(vmcs12,
9871                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9872                         exec_control |= vmcs12->secondary_vm_exec_control;
9873
9874                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9875                         /*
9876                          * If translation failed, no matter: This feature asks
9877                          * to exit when accessing the given address, and if it
9878                          * can never be accessed, this feature won't do
9879                          * anything anyway.
9880                          */
9881                         if (!vmx->nested.apic_access_page)
9882                                 exec_control &=
9883                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9884                         else
9885                                 vmcs_write64(APIC_ACCESS_ADDR,
9886                                   page_to_phys(vmx->nested.apic_access_page));
9887                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9888                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9889                         exec_control |=
9890                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9891                         kvm_vcpu_reload_apic_access_page(vcpu);
9892                 }
9893
9894                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9895                         vmcs_write64(EOI_EXIT_BITMAP0,
9896                                 vmcs12->eoi_exit_bitmap0);
9897                         vmcs_write64(EOI_EXIT_BITMAP1,
9898                                 vmcs12->eoi_exit_bitmap1);
9899                         vmcs_write64(EOI_EXIT_BITMAP2,
9900                                 vmcs12->eoi_exit_bitmap2);
9901                         vmcs_write64(EOI_EXIT_BITMAP3,
9902                                 vmcs12->eoi_exit_bitmap3);
9903                         vmcs_write16(GUEST_INTR_STATUS,
9904                                 vmcs12->guest_intr_status);
9905                 }
9906
9907                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9908         }
9909
9910
9911         /*
9912          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9913          * Some constant fields are set here by vmx_set_constant_host_state().
9914          * Other fields are different per CPU, and will be set later when
9915          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9916          */
9917         vmx_set_constant_host_state(vmx);
9918
9919         /*
9920          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9921          * entry, but only if the current (host) sp changed from the value
9922          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9923          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9924          * here we just force the write to happen on entry.
9925          */
9926         vmx->host_rsp = 0;
9927
9928         exec_control = vmx_exec_control(vmx); /* L0's desires */
9929         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9930         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9931         exec_control &= ~CPU_BASED_TPR_SHADOW;
9932         exec_control |= vmcs12->cpu_based_vm_exec_control;
9933
9934         if (exec_control & CPU_BASED_TPR_SHADOW) {
9935                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9936                                 page_to_phys(vmx->nested.virtual_apic_page));
9937                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9938         }
9939
9940         if (cpu_has_vmx_msr_bitmap() &&
9941             exec_control & CPU_BASED_USE_MSR_BITMAPS &&
9942             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9943                 ; /* MSR_BITMAP will be set by following vmx_set_efer. */
9944         else
9945                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9946
9947         /*
9948          * Merging of IO bitmap not currently supported.
9949          * Rather, exit every time.
9950          */
9951         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9952         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9953
9954         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9955
9956         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9957          * bitwise-or of what L1 wants to trap for L2, and what we want to
9958          * trap. Note that CR0.TS also needs updating - we do this later.
9959          */
9960         update_exception_bitmap(vcpu);
9961         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9962         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9963
9964         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9965          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9966          * bits are further modified by vmx_set_efer() below.
9967          */
9968         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9969
9970         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9971          * emulated by vmx_set_efer(), below.
9972          */
9973         vm_entry_controls_init(vmx,
9974                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9975                         ~VM_ENTRY_IA32E_MODE) |
9976                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9977
9978         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9979                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9980                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9981         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9982                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9983
9984
9985         set_cr4_guest_host_mask(vmx);
9986
9987         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9988                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9989
9990         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9991                 vmcs_write64(TSC_OFFSET,
9992                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9993         else
9994                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9995
9996         if (enable_vpid) {
9997                 /*
9998                  * There is no direct mapping between vpid02 and vpid12, the
9999                  * vpid02 is per-vCPU for L0 and reused while the value of
10000                  * vpid12 is changed w/ one invvpid during nested vmentry.
10001                  * The vpid12 is allocated by L1 for L2, so it will not
10002                  * influence global bitmap(for vpid01 and vpid02 allocation)
10003                  * even if spawn a lot of nested vCPUs.
10004                  */
10005                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10006                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10007                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10008                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10009                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10010                         }
10011                 } else {
10012                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10013                         vmx_flush_tlb(vcpu);
10014                 }
10015
10016         }
10017
10018         if (nested_cpu_has_ept(vmcs12)) {
10019                 kvm_mmu_unload(vcpu);
10020                 nested_ept_init_mmu_context(vcpu);
10021         }
10022
10023         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
10024                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10025         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10026                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10027         else
10028                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10029         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10030         vmx_set_efer(vcpu, vcpu->arch.efer);
10031
10032         /*
10033          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10034          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10035          * The CR0_READ_SHADOW is what L2 should have expected to read given
10036          * the specifications by L1; It's not enough to take
10037          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10038          * have more bits than L1 expected.
10039          */
10040         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10041         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10042
10043         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10044         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10045
10046         /* shadow page tables on either EPT or shadow page tables */
10047         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
10048         kvm_mmu_reset_context(vcpu);
10049
10050         if (!enable_ept)
10051                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10052
10053         /*
10054          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10055          */
10056         if (enable_ept) {
10057                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10058                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10059                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10060                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10061         }
10062
10063         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10064         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10065 }
10066
10067 /*
10068  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10069  * for running an L2 nested guest.
10070  */
10071 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10072 {
10073         struct vmcs12 *vmcs12;
10074         struct vcpu_vmx *vmx = to_vmx(vcpu);
10075         int cpu;
10076         struct loaded_vmcs *vmcs02;
10077         bool ia32e;
10078         u32 msr_entry_idx;
10079
10080         if (!nested_vmx_check_permission(vcpu) ||
10081             !nested_vmx_check_vmcs12(vcpu))
10082                 return 1;
10083
10084         skip_emulated_instruction(vcpu);
10085         vmcs12 = get_vmcs12(vcpu);
10086
10087         if (enable_shadow_vmcs)
10088                 copy_shadow_to_vmcs12(vmx);
10089
10090         /*
10091          * The nested entry process starts with enforcing various prerequisites
10092          * on vmcs12 as required by the Intel SDM, and act appropriately when
10093          * they fail: As the SDM explains, some conditions should cause the
10094          * instruction to fail, while others will cause the instruction to seem
10095          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10096          * To speed up the normal (success) code path, we should avoid checking
10097          * for misconfigurations which will anyway be caught by the processor
10098          * when using the merged vmcs02.
10099          */
10100         if (vmcs12->launch_state == launch) {
10101                 nested_vmx_failValid(vcpu,
10102                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10103                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10104                 return 1;
10105         }
10106
10107         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10108             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
10109                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10110                 return 1;
10111         }
10112
10113         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
10114                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10115                 return 1;
10116         }
10117
10118         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
10119                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10120                 return 1;
10121         }
10122
10123         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
10124                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10125                 return 1;
10126         }
10127
10128         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
10129                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10130                 return 1;
10131         }
10132
10133         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10134                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
10135                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10136             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10137                                 vmx->nested.nested_vmx_secondary_ctls_low,
10138                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10139             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10140                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10141                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10142             !vmx_control_verify(vmcs12->vm_exit_controls,
10143                                 vmx->nested.nested_vmx_true_exit_ctls_low,
10144                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10145             !vmx_control_verify(vmcs12->vm_entry_controls,
10146                                 vmx->nested.nested_vmx_true_entry_ctls_low,
10147                                 vmx->nested.nested_vmx_entry_ctls_high))
10148         {
10149                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10150                 return 1;
10151         }
10152
10153         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
10154             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10155                 nested_vmx_failValid(vcpu,
10156                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
10157                 return 1;
10158         }
10159
10160         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10161             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10162                 nested_vmx_entry_failure(vcpu, vmcs12,
10163                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10164                 return 1;
10165         }
10166         if (vmcs12->vmcs_link_pointer != -1ull) {
10167                 nested_vmx_entry_failure(vcpu, vmcs12,
10168                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
10169                 return 1;
10170         }
10171
10172         /*
10173          * If the load IA32_EFER VM-entry control is 1, the following checks
10174          * are performed on the field for the IA32_EFER MSR:
10175          * - Bits reserved in the IA32_EFER MSR must be 0.
10176          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10177          *   the IA-32e mode guest VM-exit control. It must also be identical
10178          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10179          *   CR0.PG) is 1.
10180          */
10181         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10182                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10183                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10184                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10185                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10186                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10187                         nested_vmx_entry_failure(vcpu, vmcs12,
10188                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10189                         return 1;
10190                 }
10191         }
10192
10193         /*
10194          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10195          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10196          * the values of the LMA and LME bits in the field must each be that of
10197          * the host address-space size VM-exit control.
10198          */
10199         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10200                 ia32e = (vmcs12->vm_exit_controls &
10201                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10202                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10203                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10204                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10205                         nested_vmx_entry_failure(vcpu, vmcs12,
10206                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10207                         return 1;
10208                 }
10209         }
10210
10211         /*
10212          * We're finally done with prerequisite checking, and can start with
10213          * the nested entry.
10214          */
10215
10216         vmcs02 = nested_get_current_vmcs02(vmx);
10217         if (!vmcs02)
10218                 return -ENOMEM;
10219
10220         enter_guest_mode(vcpu);
10221
10222         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
10223
10224         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10225                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10226
10227         cpu = get_cpu();
10228         vmx->loaded_vmcs = vmcs02;
10229         vmx_vcpu_put(vcpu);
10230         vmx_vcpu_load(vcpu, cpu);
10231         vcpu->cpu = cpu;
10232         put_cpu();
10233
10234         vmx_segment_cache_clear(vmx);
10235
10236         prepare_vmcs02(vcpu, vmcs12);
10237
10238         msr_entry_idx = nested_vmx_load_msr(vcpu,
10239                                             vmcs12->vm_entry_msr_load_addr,
10240                                             vmcs12->vm_entry_msr_load_count);
10241         if (msr_entry_idx) {
10242                 leave_guest_mode(vcpu);
10243                 vmx_load_vmcs01(vcpu);
10244                 nested_vmx_entry_failure(vcpu, vmcs12,
10245                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10246                 return 1;
10247         }
10248
10249         vmcs12->launch_state = 1;
10250
10251         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10252                 return kvm_vcpu_halt(vcpu);
10253
10254         vmx->nested.nested_run_pending = 1;
10255
10256         /*
10257          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10258          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10259          * returned as far as L1 is concerned. It will only return (and set
10260          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10261          */
10262         return 1;
10263 }
10264
10265 /*
10266  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10267  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10268  * This function returns the new value we should put in vmcs12.guest_cr0.
10269  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10270  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10271  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10272  *     didn't trap the bit, because if L1 did, so would L0).
10273  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10274  *     been modified by L2, and L1 knows it. So just leave the old value of
10275  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10276  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10277  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10278  *     changed these bits, and therefore they need to be updated, but L0
10279  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10280  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10281  */
10282 static inline unsigned long
10283 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10284 {
10285         return
10286         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10287         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10288         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10289                         vcpu->arch.cr0_guest_owned_bits));
10290 }
10291
10292 static inline unsigned long
10293 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10294 {
10295         return
10296         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10297         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10298         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10299                         vcpu->arch.cr4_guest_owned_bits));
10300 }
10301
10302 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10303                                        struct vmcs12 *vmcs12)
10304 {
10305         u32 idt_vectoring;
10306         unsigned int nr;
10307
10308         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10309                 nr = vcpu->arch.exception.nr;
10310                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10311
10312                 if (kvm_exception_is_soft(nr)) {
10313                         vmcs12->vm_exit_instruction_len =
10314                                 vcpu->arch.event_exit_inst_len;
10315                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10316                 } else
10317                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10318
10319                 if (vcpu->arch.exception.has_error_code) {
10320                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10321                         vmcs12->idt_vectoring_error_code =
10322                                 vcpu->arch.exception.error_code;
10323                 }
10324
10325                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10326         } else if (vcpu->arch.nmi_injected) {
10327                 vmcs12->idt_vectoring_info_field =
10328                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10329         } else if (vcpu->arch.interrupt.pending) {
10330                 nr = vcpu->arch.interrupt.nr;
10331                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10332
10333                 if (vcpu->arch.interrupt.soft) {
10334                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10335                         vmcs12->vm_entry_instruction_len =
10336                                 vcpu->arch.event_exit_inst_len;
10337                 } else
10338                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10339
10340                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10341         }
10342 }
10343
10344 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10345 {
10346         struct vcpu_vmx *vmx = to_vmx(vcpu);
10347
10348         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10349             vmx->nested.preemption_timer_expired) {
10350                 if (vmx->nested.nested_run_pending)
10351                         return -EBUSY;
10352                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10353                 return 0;
10354         }
10355
10356         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10357                 if (vmx->nested.nested_run_pending ||
10358                     vcpu->arch.interrupt.pending)
10359                         return -EBUSY;
10360                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10361                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10362                                   INTR_INFO_VALID_MASK, 0);
10363                 /*
10364                  * The NMI-triggered VM exit counts as injection:
10365                  * clear this one and block further NMIs.
10366                  */
10367                 vcpu->arch.nmi_pending = 0;
10368                 vmx_set_nmi_mask(vcpu, true);
10369                 return 0;
10370         }
10371
10372         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10373             nested_exit_on_intr(vcpu)) {
10374                 if (vmx->nested.nested_run_pending)
10375                         return -EBUSY;
10376                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10377                 return 0;
10378         }
10379
10380         return vmx_complete_nested_posted_interrupt(vcpu);
10381 }
10382
10383 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10384 {
10385         ktime_t remaining =
10386                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10387         u64 value;
10388
10389         if (ktime_to_ns(remaining) <= 0)
10390                 return 0;
10391
10392         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10393         do_div(value, 1000000);
10394         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10395 }
10396
10397 /*
10398  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10399  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10400  * and this function updates it to reflect the changes to the guest state while
10401  * L2 was running (and perhaps made some exits which were handled directly by L0
10402  * without going back to L1), and to reflect the exit reason.
10403  * Note that we do not have to copy here all VMCS fields, just those that
10404  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10405  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10406  * which already writes to vmcs12 directly.
10407  */
10408 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10409                            u32 exit_reason, u32 exit_intr_info,
10410                            unsigned long exit_qualification)
10411 {
10412         /* update guest state fields: */
10413         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10414         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10415
10416         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10417         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10418         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10419
10420         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10421         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10422         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10423         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10424         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10425         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10426         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10427         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10428         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10429         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10430         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10431         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10432         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10433         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10434         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10435         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10436         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10437         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10438         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10439         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10440         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10441         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10442         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10443         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10444         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10445         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10446         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10447         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10448         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10449         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10450         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10451         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10452         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10453         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10454         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10455         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10456
10457         vmcs12->guest_interruptibility_info =
10458                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10459         vmcs12->guest_pending_dbg_exceptions =
10460                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10461         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10462                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10463         else
10464                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10465
10466         if (nested_cpu_has_preemption_timer(vmcs12)) {
10467                 if (vmcs12->vm_exit_controls &
10468                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10469                         vmcs12->vmx_preemption_timer_value =
10470                                 vmx_get_preemption_timer_value(vcpu);
10471                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10472         }
10473
10474         /*
10475          * In some cases (usually, nested EPT), L2 is allowed to change its
10476          * own CR3 without exiting. If it has changed it, we must keep it.
10477          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10478          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10479          *
10480          * Additionally, restore L2's PDPTR to vmcs12.
10481          */
10482         if (enable_ept) {
10483                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10484                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10485                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10486                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10487                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10488         }
10489
10490         if (nested_cpu_has_vid(vmcs12))
10491                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10492
10493         vmcs12->vm_entry_controls =
10494                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10495                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10496
10497         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10498                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10499                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10500         }
10501
10502         /* TODO: These cannot have changed unless we have MSR bitmaps and
10503          * the relevant bit asks not to trap the change */
10504         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10505                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10506         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10507                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10508         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10509         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10510         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10511         if (kvm_mpx_supported())
10512                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10513         if (nested_cpu_has_xsaves(vmcs12))
10514                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10515
10516         /* update exit information fields: */
10517
10518         vmcs12->vm_exit_reason = exit_reason;
10519         vmcs12->exit_qualification = exit_qualification;
10520
10521         vmcs12->vm_exit_intr_info = exit_intr_info;
10522         if ((vmcs12->vm_exit_intr_info &
10523              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10524             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10525                 vmcs12->vm_exit_intr_error_code =
10526                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10527         vmcs12->idt_vectoring_info_field = 0;
10528         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10529         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10530
10531         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10532                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10533                  * instead of reading the real value. */
10534                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10535
10536                 /*
10537                  * Transfer the event that L0 or L1 may wanted to inject into
10538                  * L2 to IDT_VECTORING_INFO_FIELD.
10539                  */
10540                 vmcs12_save_pending_event(vcpu, vmcs12);
10541         }
10542
10543         /*
10544          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10545          * preserved above and would only end up incorrectly in L1.
10546          */
10547         vcpu->arch.nmi_injected = false;
10548         kvm_clear_exception_queue(vcpu);
10549         kvm_clear_interrupt_queue(vcpu);
10550 }
10551
10552 /*
10553  * A part of what we need to when the nested L2 guest exits and we want to
10554  * run its L1 parent, is to reset L1's guest state to the host state specified
10555  * in vmcs12.
10556  * This function is to be called not only on normal nested exit, but also on
10557  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10558  * Failures During or After Loading Guest State").
10559  * This function should be called when the active VMCS is L1's (vmcs01).
10560  */
10561 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10562                                    struct vmcs12 *vmcs12)
10563 {
10564         struct kvm_segment seg;
10565
10566         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10567                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10568         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10569                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10570         else
10571                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10572         vmx_set_efer(vcpu, vcpu->arch.efer);
10573
10574         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10575         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10576         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10577         /*
10578          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10579          * actually changed, because it depends on the current state of
10580          * fpu_active (which may have changed).
10581          * Note that vmx_set_cr0 refers to efer set above.
10582          */
10583         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10584         /*
10585          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10586          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10587          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10588          */
10589         update_exception_bitmap(vcpu);
10590         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10591         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10592
10593         /*
10594          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10595          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10596          */
10597         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10598         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10599
10600         nested_ept_uninit_mmu_context(vcpu);
10601
10602         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10603         kvm_mmu_reset_context(vcpu);
10604
10605         if (!enable_ept)
10606                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10607
10608         if (enable_vpid) {
10609                 /*
10610                  * Trivially support vpid by letting L2s share their parent
10611                  * L1's vpid. TODO: move to a more elaborate solution, giving
10612                  * each L2 its own vpid and exposing the vpid feature to L1.
10613                  */
10614                 vmx_flush_tlb(vcpu);
10615         }
10616
10617
10618         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10619         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10620         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10621         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10622         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10623
10624         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10625         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10626                 vmcs_write64(GUEST_BNDCFGS, 0);
10627
10628         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10629                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10630                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10631         }
10632         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10633                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10634                         vmcs12->host_ia32_perf_global_ctrl);
10635
10636         /* Set L1 segment info according to Intel SDM
10637             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10638         seg = (struct kvm_segment) {
10639                 .base = 0,
10640                 .limit = 0xFFFFFFFF,
10641                 .selector = vmcs12->host_cs_selector,
10642                 .type = 11,
10643                 .present = 1,
10644                 .s = 1,
10645                 .g = 1
10646         };
10647         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10648                 seg.l = 1;
10649         else
10650                 seg.db = 1;
10651         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10652         seg = (struct kvm_segment) {
10653                 .base = 0,
10654                 .limit = 0xFFFFFFFF,
10655                 .type = 3,
10656                 .present = 1,
10657                 .s = 1,
10658                 .db = 1,
10659                 .g = 1
10660         };
10661         seg.selector = vmcs12->host_ds_selector;
10662         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10663         seg.selector = vmcs12->host_es_selector;
10664         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10665         seg.selector = vmcs12->host_ss_selector;
10666         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10667         seg.selector = vmcs12->host_fs_selector;
10668         seg.base = vmcs12->host_fs_base;
10669         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10670         seg.selector = vmcs12->host_gs_selector;
10671         seg.base = vmcs12->host_gs_base;
10672         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10673         seg = (struct kvm_segment) {
10674                 .base = vmcs12->host_tr_base,
10675                 .limit = 0x67,
10676                 .selector = vmcs12->host_tr_selector,
10677                 .type = 11,
10678                 .present = 1
10679         };
10680         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10681
10682         kvm_set_dr(vcpu, 7, 0x400);
10683         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10684
10685         if (cpu_has_vmx_msr_bitmap())
10686                 vmx_set_msr_bitmap(vcpu);
10687
10688         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10689                                 vmcs12->vm_exit_msr_load_count))
10690                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10691 }
10692
10693 /*
10694  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10695  * and modify vmcs12 to make it see what it would expect to see there if
10696  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10697  */
10698 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10699                               u32 exit_intr_info,
10700                               unsigned long exit_qualification)
10701 {
10702         struct vcpu_vmx *vmx = to_vmx(vcpu);
10703         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10704
10705         /* trying to cancel vmlaunch/vmresume is a bug */
10706         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10707
10708         leave_guest_mode(vcpu);
10709         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10710                        exit_qualification);
10711
10712         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10713                                  vmcs12->vm_exit_msr_store_count))
10714                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10715
10716         vmx_load_vmcs01(vcpu);
10717
10718         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10719             && nested_exit_intr_ack_set(vcpu)) {
10720                 int irq = kvm_cpu_get_interrupt(vcpu);
10721                 WARN_ON(irq < 0);
10722                 vmcs12->vm_exit_intr_info = irq |
10723                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10724         }
10725
10726         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10727                                        vmcs12->exit_qualification,
10728                                        vmcs12->idt_vectoring_info_field,
10729                                        vmcs12->vm_exit_intr_info,
10730                                        vmcs12->vm_exit_intr_error_code,
10731                                        KVM_ISA_VMX);
10732
10733         vm_entry_controls_reset_shadow(vmx);
10734         vm_exit_controls_reset_shadow(vmx);
10735         vmx_segment_cache_clear(vmx);
10736
10737         /* if no vmcs02 cache requested, remove the one we used */
10738         if (VMCS02_POOL_SIZE == 0)
10739                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10740
10741         load_vmcs12_host_state(vcpu, vmcs12);
10742
10743         /* Update any VMCS fields that might have changed while L2 ran */
10744         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10745         if (vmx->hv_deadline_tsc == -1)
10746                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10747                                 PIN_BASED_VMX_PREEMPTION_TIMER);
10748         else
10749                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10750                               PIN_BASED_VMX_PREEMPTION_TIMER);
10751
10752         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10753         vmx->host_rsp = 0;
10754
10755         /* Unpin physical memory we referred to in vmcs02 */
10756         if (vmx->nested.apic_access_page) {
10757                 nested_release_page(vmx->nested.apic_access_page);
10758                 vmx->nested.apic_access_page = NULL;
10759         }
10760         if (vmx->nested.virtual_apic_page) {
10761                 nested_release_page(vmx->nested.virtual_apic_page);
10762                 vmx->nested.virtual_apic_page = NULL;
10763         }
10764         if (vmx->nested.pi_desc_page) {
10765                 kunmap(vmx->nested.pi_desc_page);
10766                 nested_release_page(vmx->nested.pi_desc_page);
10767                 vmx->nested.pi_desc_page = NULL;
10768                 vmx->nested.pi_desc = NULL;
10769         }
10770
10771         /*
10772          * We are now running in L2, mmu_notifier will force to reload the
10773          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10774          */
10775         kvm_vcpu_reload_apic_access_page(vcpu);
10776
10777         /*
10778          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10779          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10780          * success or failure flag accordingly.
10781          */
10782         if (unlikely(vmx->fail)) {
10783                 vmx->fail = 0;
10784                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10785         } else
10786                 nested_vmx_succeed(vcpu);
10787         if (enable_shadow_vmcs)
10788                 vmx->nested.sync_shadow_vmcs = true;
10789
10790         /* in case we halted in L2 */
10791         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10792 }
10793
10794 /*
10795  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10796  */
10797 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10798 {
10799         if (is_guest_mode(vcpu))
10800                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10801         free_nested(to_vmx(vcpu));
10802 }
10803
10804 /*
10805  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10806  * 23.7 "VM-entry failures during or after loading guest state" (this also
10807  * lists the acceptable exit-reason and exit-qualification parameters).
10808  * It should only be called before L2 actually succeeded to run, and when
10809  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10810  */
10811 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10812                         struct vmcs12 *vmcs12,
10813                         u32 reason, unsigned long qualification)
10814 {
10815         load_vmcs12_host_state(vcpu, vmcs12);
10816         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10817         vmcs12->exit_qualification = qualification;
10818         nested_vmx_succeed(vcpu);
10819         if (enable_shadow_vmcs)
10820                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10821 }
10822
10823 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10824                                struct x86_instruction_info *info,
10825                                enum x86_intercept_stage stage)
10826 {
10827         return X86EMUL_CONTINUE;
10828 }
10829
10830 #ifdef CONFIG_X86_64
10831 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
10832 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
10833                                   u64 divisor, u64 *result)
10834 {
10835         u64 low = a << shift, high = a >> (64 - shift);
10836
10837         /* To avoid the overflow on divq */
10838         if (high >= divisor)
10839                 return 1;
10840
10841         /* Low hold the result, high hold rem which is discarded */
10842         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
10843             "rm" (divisor), "0" (low), "1" (high));
10844         *result = low;
10845
10846         return 0;
10847 }
10848
10849 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
10850 {
10851         struct vcpu_vmx *vmx = to_vmx(vcpu);
10852         u64 tscl = rdtsc();
10853         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
10854         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
10855
10856         /* Convert to host delta tsc if tsc scaling is enabled */
10857         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
10858                         u64_shl_div_u64(delta_tsc,
10859                                 kvm_tsc_scaling_ratio_frac_bits,
10860                                 vcpu->arch.tsc_scaling_ratio,
10861                                 &delta_tsc))
10862                 return -ERANGE;
10863
10864         /*
10865          * If the delta tsc can't fit in the 32 bit after the multi shift,
10866          * we can't use the preemption timer.
10867          * It's possible that it fits on later vmentries, but checking
10868          * on every vmentry is costly so we just use an hrtimer.
10869          */
10870         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
10871                 return -ERANGE;
10872
10873         vmx->hv_deadline_tsc = tscl + delta_tsc;
10874         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10875                         PIN_BASED_VMX_PREEMPTION_TIMER);
10876         return 0;
10877 }
10878
10879 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
10880 {
10881         struct vcpu_vmx *vmx = to_vmx(vcpu);
10882         vmx->hv_deadline_tsc = -1;
10883         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10884                         PIN_BASED_VMX_PREEMPTION_TIMER);
10885 }
10886 #endif
10887
10888 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10889 {
10890         if (ple_gap)
10891                 shrink_ple_window(vcpu);
10892 }
10893
10894 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10895                                      struct kvm_memory_slot *slot)
10896 {
10897         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10898         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10899 }
10900
10901 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10902                                        struct kvm_memory_slot *slot)
10903 {
10904         kvm_mmu_slot_set_dirty(kvm, slot);
10905 }
10906
10907 static void vmx_flush_log_dirty(struct kvm *kvm)
10908 {
10909         kvm_flush_pml_buffers(kvm);
10910 }
10911
10912 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10913                                            struct kvm_memory_slot *memslot,
10914                                            gfn_t offset, unsigned long mask)
10915 {
10916         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10917 }
10918
10919 /*
10920  * This routine does the following things for vCPU which is going
10921  * to be blocked if VT-d PI is enabled.
10922  * - Store the vCPU to the wakeup list, so when interrupts happen
10923  *   we can find the right vCPU to wake up.
10924  * - Change the Posted-interrupt descriptor as below:
10925  *      'NDST' <-- vcpu->pre_pcpu
10926  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10927  * - If 'ON' is set during this process, which means at least one
10928  *   interrupt is posted for this vCPU, we cannot block it, in
10929  *   this case, return 1, otherwise, return 0.
10930  *
10931  */
10932 static int pi_pre_block(struct kvm_vcpu *vcpu)
10933 {
10934         unsigned long flags;
10935         unsigned int dest;
10936         struct pi_desc old, new;
10937         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10938
10939         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10940                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
10941                 !kvm_vcpu_apicv_active(vcpu))
10942                 return 0;
10943
10944         vcpu->pre_pcpu = vcpu->cpu;
10945         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10946                           vcpu->pre_pcpu), flags);
10947         list_add_tail(&vcpu->blocked_vcpu_list,
10948                       &per_cpu(blocked_vcpu_on_cpu,
10949                       vcpu->pre_pcpu));
10950         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10951                                vcpu->pre_pcpu), flags);
10952
10953         do {
10954                 old.control = new.control = pi_desc->control;
10955
10956                 /*
10957                  * We should not block the vCPU if
10958                  * an interrupt is posted for it.
10959                  */
10960                 if (pi_test_on(pi_desc) == 1) {
10961                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10962                                           vcpu->pre_pcpu), flags);
10963                         list_del(&vcpu->blocked_vcpu_list);
10964                         spin_unlock_irqrestore(
10965                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10966                                         vcpu->pre_pcpu), flags);
10967                         vcpu->pre_pcpu = -1;
10968
10969                         return 1;
10970                 }
10971
10972                 WARN((pi_desc->sn == 1),
10973                      "Warning: SN field of posted-interrupts "
10974                      "is set before blocking\n");
10975
10976                 /*
10977                  * Since vCPU can be preempted during this process,
10978                  * vcpu->cpu could be different with pre_pcpu, we
10979                  * need to set pre_pcpu as the destination of wakeup
10980                  * notification event, then we can find the right vCPU
10981                  * to wakeup in wakeup handler if interrupts happen
10982                  * when the vCPU is in blocked state.
10983                  */
10984                 dest = cpu_physical_id(vcpu->pre_pcpu);
10985
10986                 if (x2apic_enabled())
10987                         new.ndst = dest;
10988                 else
10989                         new.ndst = (dest << 8) & 0xFF00;
10990
10991                 /* set 'NV' to 'wakeup vector' */
10992                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10993         } while (cmpxchg(&pi_desc->control, old.control,
10994                         new.control) != old.control);
10995
10996         return 0;
10997 }
10998
10999 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11000 {
11001         if (pi_pre_block(vcpu))
11002                 return 1;
11003
11004         if (kvm_lapic_hv_timer_in_use(vcpu))
11005                 kvm_lapic_switch_to_sw_timer(vcpu);
11006
11007         return 0;
11008 }
11009
11010 static void pi_post_block(struct kvm_vcpu *vcpu)
11011 {
11012         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11013         struct pi_desc old, new;
11014         unsigned int dest;
11015         unsigned long flags;
11016
11017         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11018                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11019                 !kvm_vcpu_apicv_active(vcpu))
11020                 return;
11021
11022         do {
11023                 old.control = new.control = pi_desc->control;
11024
11025                 dest = cpu_physical_id(vcpu->cpu);
11026
11027                 if (x2apic_enabled())
11028                         new.ndst = dest;
11029                 else
11030                         new.ndst = (dest << 8) & 0xFF00;
11031
11032                 /* Allow posting non-urgent interrupts */
11033                 new.sn = 0;
11034
11035                 /* set 'NV' to 'notification vector' */
11036                 new.nv = POSTED_INTR_VECTOR;
11037         } while (cmpxchg(&pi_desc->control, old.control,
11038                         new.control) != old.control);
11039
11040         if(vcpu->pre_pcpu != -1) {
11041                 spin_lock_irqsave(
11042                         &per_cpu(blocked_vcpu_on_cpu_lock,
11043                         vcpu->pre_pcpu), flags);
11044                 list_del(&vcpu->blocked_vcpu_list);
11045                 spin_unlock_irqrestore(
11046                         &per_cpu(blocked_vcpu_on_cpu_lock,
11047                         vcpu->pre_pcpu), flags);
11048                 vcpu->pre_pcpu = -1;
11049         }
11050 }
11051
11052 static void vmx_post_block(struct kvm_vcpu *vcpu)
11053 {
11054         if (kvm_x86_ops->set_hv_timer)
11055                 kvm_lapic_switch_to_hv_timer(vcpu);
11056
11057         pi_post_block(vcpu);
11058 }
11059
11060 /*
11061  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11062  *
11063  * @kvm: kvm
11064  * @host_irq: host irq of the interrupt
11065  * @guest_irq: gsi of the interrupt
11066  * @set: set or unset PI
11067  * returns 0 on success, < 0 on failure
11068  */
11069 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11070                               uint32_t guest_irq, bool set)
11071 {
11072         struct kvm_kernel_irq_routing_entry *e;
11073         struct kvm_irq_routing_table *irq_rt;
11074         struct kvm_lapic_irq irq;
11075         struct kvm_vcpu *vcpu;
11076         struct vcpu_data vcpu_info;
11077         int idx, ret = -EINVAL;
11078
11079         if (!kvm_arch_has_assigned_device(kvm) ||
11080                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11081                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11082                 return 0;
11083
11084         idx = srcu_read_lock(&kvm->irq_srcu);
11085         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11086         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11087
11088         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11089                 if (e->type != KVM_IRQ_ROUTING_MSI)
11090                         continue;
11091                 /*
11092                  * VT-d PI cannot support posting multicast/broadcast
11093                  * interrupts to a vCPU, we still use interrupt remapping
11094                  * for these kind of interrupts.
11095                  *
11096                  * For lowest-priority interrupts, we only support
11097                  * those with single CPU as the destination, e.g. user
11098                  * configures the interrupts via /proc/irq or uses
11099                  * irqbalance to make the interrupts single-CPU.
11100                  *
11101                  * We will support full lowest-priority interrupt later.
11102                  */
11103
11104                 kvm_set_msi_irq(kvm, e, &irq);
11105                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11106                         /*
11107                          * Make sure the IRTE is in remapped mode if
11108                          * we don't handle it in posted mode.
11109                          */
11110                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11111                         if (ret < 0) {
11112                                 printk(KERN_INFO
11113                                    "failed to back to remapped mode, irq: %u\n",
11114                                    host_irq);
11115                                 goto out;
11116                         }
11117
11118                         continue;
11119                 }
11120
11121                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11122                 vcpu_info.vector = irq.vector;
11123
11124                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11125                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11126
11127                 if (set)
11128                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11129                 else {
11130                         /* suppress notification event before unposting */
11131                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11132                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11133                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11134                 }
11135
11136                 if (ret < 0) {
11137                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11138                                         __func__);
11139                         goto out;
11140                 }
11141         }
11142
11143         ret = 0;
11144 out:
11145         srcu_read_unlock(&kvm->irq_srcu, idx);
11146         return ret;
11147 }
11148
11149 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11150 {
11151         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11152                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11153                         FEATURE_CONTROL_LMCE;
11154         else
11155                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11156                         ~FEATURE_CONTROL_LMCE;
11157 }
11158
11159 static struct kvm_x86_ops vmx_x86_ops = {
11160         .cpu_has_kvm_support = cpu_has_kvm_support,
11161         .disabled_by_bios = vmx_disabled_by_bios,
11162         .hardware_setup = hardware_setup,
11163         .hardware_unsetup = hardware_unsetup,
11164         .check_processor_compatibility = vmx_check_processor_compat,
11165         .hardware_enable = hardware_enable,
11166         .hardware_disable = hardware_disable,
11167         .cpu_has_accelerated_tpr = report_flexpriority,
11168         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11169
11170         .vcpu_create = vmx_create_vcpu,
11171         .vcpu_free = vmx_free_vcpu,
11172         .vcpu_reset = vmx_vcpu_reset,
11173
11174         .prepare_guest_switch = vmx_save_host_state,
11175         .vcpu_load = vmx_vcpu_load,
11176         .vcpu_put = vmx_vcpu_put,
11177
11178         .update_bp_intercept = update_exception_bitmap,
11179         .get_msr = vmx_get_msr,
11180         .set_msr = vmx_set_msr,
11181         .get_segment_base = vmx_get_segment_base,
11182         .get_segment = vmx_get_segment,
11183         .set_segment = vmx_set_segment,
11184         .get_cpl = vmx_get_cpl,
11185         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11186         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11187         .decache_cr3 = vmx_decache_cr3,
11188         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11189         .set_cr0 = vmx_set_cr0,
11190         .set_cr3 = vmx_set_cr3,
11191         .set_cr4 = vmx_set_cr4,
11192         .set_efer = vmx_set_efer,
11193         .get_idt = vmx_get_idt,
11194         .set_idt = vmx_set_idt,
11195         .get_gdt = vmx_get_gdt,
11196         .set_gdt = vmx_set_gdt,
11197         .get_dr6 = vmx_get_dr6,
11198         .set_dr6 = vmx_set_dr6,
11199         .set_dr7 = vmx_set_dr7,
11200         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11201         .cache_reg = vmx_cache_reg,
11202         .get_rflags = vmx_get_rflags,
11203         .set_rflags = vmx_set_rflags,
11204
11205         .get_pkru = vmx_get_pkru,
11206
11207         .fpu_activate = vmx_fpu_activate,
11208         .fpu_deactivate = vmx_fpu_deactivate,
11209
11210         .tlb_flush = vmx_flush_tlb,
11211
11212         .run = vmx_vcpu_run,
11213         .handle_exit = vmx_handle_exit,
11214         .skip_emulated_instruction = skip_emulated_instruction,
11215         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11216         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11217         .patch_hypercall = vmx_patch_hypercall,
11218         .set_irq = vmx_inject_irq,
11219         .set_nmi = vmx_inject_nmi,
11220         .queue_exception = vmx_queue_exception,
11221         .cancel_injection = vmx_cancel_injection,
11222         .interrupt_allowed = vmx_interrupt_allowed,
11223         .nmi_allowed = vmx_nmi_allowed,
11224         .get_nmi_mask = vmx_get_nmi_mask,
11225         .set_nmi_mask = vmx_set_nmi_mask,
11226         .enable_nmi_window = enable_nmi_window,
11227         .enable_irq_window = enable_irq_window,
11228         .update_cr8_intercept = update_cr8_intercept,
11229         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11230         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11231         .get_enable_apicv = vmx_get_enable_apicv,
11232         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11233         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11234         .hwapic_irr_update = vmx_hwapic_irr_update,
11235         .hwapic_isr_update = vmx_hwapic_isr_update,
11236         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11237         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11238
11239         .set_tss_addr = vmx_set_tss_addr,
11240         .get_tdp_level = get_ept_level,
11241         .get_mt_mask = vmx_get_mt_mask,
11242
11243         .get_exit_info = vmx_get_exit_info,
11244
11245         .get_lpage_level = vmx_get_lpage_level,
11246
11247         .cpuid_update = vmx_cpuid_update,
11248
11249         .rdtscp_supported = vmx_rdtscp_supported,
11250         .invpcid_supported = vmx_invpcid_supported,
11251
11252         .set_supported_cpuid = vmx_set_supported_cpuid,
11253
11254         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11255
11256         .read_tsc_offset = vmx_read_tsc_offset,
11257         .write_tsc_offset = vmx_write_tsc_offset,
11258         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
11259         .read_l1_tsc = vmx_read_l1_tsc,
11260
11261         .set_tdp_cr3 = vmx_set_cr3,
11262
11263         .check_intercept = vmx_check_intercept,
11264         .handle_external_intr = vmx_handle_external_intr,
11265         .mpx_supported = vmx_mpx_supported,
11266         .xsaves_supported = vmx_xsaves_supported,
11267
11268         .check_nested_events = vmx_check_nested_events,
11269
11270         .sched_in = vmx_sched_in,
11271
11272         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11273         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11274         .flush_log_dirty = vmx_flush_log_dirty,
11275         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11276
11277         .pre_block = vmx_pre_block,
11278         .post_block = vmx_post_block,
11279
11280         .pmu_ops = &intel_pmu_ops,
11281
11282         .update_pi_irte = vmx_update_pi_irte,
11283
11284 #ifdef CONFIG_X86_64
11285         .set_hv_timer = vmx_set_hv_timer,
11286         .cancel_hv_timer = vmx_cancel_hv_timer,
11287 #endif
11288
11289         .setup_mce = vmx_setup_mce,
11290 };
11291
11292 static int __init vmx_init(void)
11293 {
11294         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11295                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11296         if (r)
11297                 return r;
11298
11299 #ifdef CONFIG_KEXEC_CORE
11300         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11301                            crash_vmclear_local_loaded_vmcss);
11302 #endif
11303
11304         return 0;
11305 }
11306
11307 static void __exit vmx_exit(void)
11308 {
11309 #ifdef CONFIG_KEXEC_CORE
11310         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11311         synchronize_rcu();
11312 #endif
11313
11314         kvm_exit();
11315 }
11316
11317 module_init(vmx_init)
11318 module_exit(vmx_exit)