arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include "kvm_cache_regs.h"
  38 #include "x86.h"
  39
  40 #include <asm/cpu.h>
  41 #include <asm/io.h>
  42 #include <asm/desc.h>
  43 #include <asm/vmx.h>
  44 #include <asm/virtext.h>
  45 #include <asm/mce.h>
  46 #include <asm/fpu/internal.h>
  47 #include <asm/perf_event.h>
  48 #include <asm/debugreg.h>
  49 #include <asm/kexec.h>
  50 #include <asm/apic.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/mmu_context.h>
  53
  54 #include "trace.h"
  55 #include "pmu.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58 #define __ex_clear(x, reg) \
  59         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  60
  61 MODULE_AUTHOR("Qumranet");
  62 MODULE_LICENSE("GPL");
  63
  64 static const struct x86_cpu_id vmx_cpu_id[] = {
  65         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  66         {}
  67 };
  68 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  69
  70 static bool __read_mostly enable_vpid = 1;
  71 module_param_named(vpid, enable_vpid, bool, 0444);
  72
  73 static bool __read_mostly enable_vnmi = 1;
  74 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  75
  76 static bool __read_mostly flexpriority_enabled = 1;
  77 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  78
  79 static bool __read_mostly enable_ept = 1;
  80 module_param_named(ept, enable_ept, bool, S_IRUGO);
  81
  82 static bool __read_mostly enable_unrestricted_guest = 1;
  83 module_param_named(unrestricted_guest,
  84                         enable_unrestricted_guest, bool, S_IRUGO);
  85
  86 static bool __read_mostly enable_ept_ad_bits = 1;
  87 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  88
  89 static bool __read_mostly emulate_invalid_guest_state = true;
  90 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  91
  92 static bool __read_mostly fasteoi = 1;
  93 module_param(fasteoi, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_apicv = 1;
  96 module_param(enable_apicv, bool, S_IRUGO);
  97
  98 static bool __read_mostly enable_shadow_vmcs = 1;
  99 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
 100 /*
 101  * If nested=1, nested virtualization is supported, i.e., guests may use
 102  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 103  * use VMX instructions.
 104  */
 105 static bool __read_mostly nested = 0;
 106 module_param(nested, bool, S_IRUGO);
 107
 108 static u64 __read_mostly host_xss;
 109
 110 static bool __read_mostly enable_pml = 1;
 111 module_param_named(pml, enable_pml, bool, S_IRUGO);
 112
 113 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 114
 115 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 116 static int __read_mostly cpu_preemption_timer_multi;
 117 static bool __read_mostly enable_preemption_timer = 1;
 118 #ifdef CONFIG_X86_64
 119 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 120 #endif
 121
 122 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 123 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 124 #define KVM_VM_CR0_ALWAYS_ON                                            \
 125         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 126 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 127         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 128          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 129
 130 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 131 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 132
 133 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 134
 135 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 136
 137 /*
 138  * Hyper-V requires all of these, so mark them as supported even though
 139  * they are just treated the same as all-context.
 140  */
 141 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 142         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 143         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 144         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 145         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 146
 147 /*
 148  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 149  * ple_gap:    upper bound on the amount of time between two successive
 150  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 151  *             According to test, this time is usually smaller than 128 cycles.
 152  * ple_window: upper bound on the amount of time a guest is allowed to execute
 153  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 154  *             less than 2^12 cycles
 155  * Time is measured based on a counter that runs at the same rate as the TSC,
 156  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 157  */
 158 #define KVM_VMX_DEFAULT_PLE_GAP           128
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 160 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 161 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 162 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 163                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 164
 165 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 166 module_param(ple_gap, int, S_IRUGO);
 167
 168 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 169 module_param(ple_window, int, S_IRUGO);
 170
 171 /* Default doubles per-vcpu window every exit. */
 172 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 173 module_param(ple_window_grow, int, S_IRUGO);
 174
 175 /* Default resets per-vcpu window every exit to ple_window. */
 176 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 177 module_param(ple_window_shrink, int, S_IRUGO);
 178
 179 /* Default is to compute the maximum so we can never overflow. */
 180 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 181 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 182 module_param(ple_window_max, int, S_IRUGO);
 183
 184 extern const ulong vmx_return;
 185
 186 #define NR_AUTOLOAD_MSRS 8
 187 #define VMCS02_POOL_SIZE 1
 188
 189 struct vmcs {
 190         u32 revision_id;
 191         u32 abort;
 192         char data[0];
 193 };
 194
 195 /*
 196  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 197  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 198  * loaded on this CPU (so we can clear them if the CPU goes down).
 199  */
 200 struct loaded_vmcs {
 201         struct vmcs *vmcs;
 202         struct vmcs *shadow_vmcs;
 203         int cpu;
 204         bool launched;
 205         bool nmi_known_unmasked;
 206         unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 207         unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 208         /* Support for vnmi-less CPUs */
 209         int soft_vnmi_blocked;
 210         ktime_t entry_time;
 211         s64 vnmi_blocked_time;
 212         struct list_head loaded_vmcss_on_cpu_link;
 213 };
 214
 215 struct shared_msr_entry {
 216         unsigned index;
 217         u64 data;
 218         u64 mask;
 219 };
 220
 221 /*
 222  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 223  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 224  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 225  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 226  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 227  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 228  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 229  * underlying hardware which will be used to run L2.
 230  * This structure is packed to ensure that its layout is identical across
 231  * machines (necessary for live migration).
 232  * If there are changes in this struct, VMCS12_REVISION must be changed.
 233  */
 234 typedef u64 natural_width;
 235 struct __packed vmcs12 {
 236         /* According to the Intel spec, a VMCS region must start with the
 237          * following two fields. Then follow implementation-specific data.
 238          */
 239         u32 revision_id;
 240         u32 abort;
 241
 242         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 243         u32 padding[7]; /* room for future expansion */
 244
 245         u64 io_bitmap_a;
 246         u64 io_bitmap_b;
 247         u64 msr_bitmap;
 248         u64 vm_exit_msr_store_addr;
 249         u64 vm_exit_msr_load_addr;
 250         u64 vm_entry_msr_load_addr;
 251         u64 tsc_offset;
 252         u64 virtual_apic_page_addr;
 253         u64 apic_access_addr;
 254         u64 posted_intr_desc_addr;
 255         u64 vm_function_control;
 256         u64 ept_pointer;
 257         u64 eoi_exit_bitmap0;
 258         u64 eoi_exit_bitmap1;
 259         u64 eoi_exit_bitmap2;
 260         u64 eoi_exit_bitmap3;
 261         u64 eptp_list_address;
 262         u64 xss_exit_bitmap;
 263         u64 guest_physical_address;
 264         u64 vmcs_link_pointer;
 265         u64 pml_address;
 266         u64 guest_ia32_debugctl;
 267         u64 guest_ia32_pat;
 268         u64 guest_ia32_efer;
 269         u64 guest_ia32_perf_global_ctrl;
 270         u64 guest_pdptr0;
 271         u64 guest_pdptr1;
 272         u64 guest_pdptr2;
 273         u64 guest_pdptr3;
 274         u64 guest_bndcfgs;
 275         u64 host_ia32_pat;
 276         u64 host_ia32_efer;
 277         u64 host_ia32_perf_global_ctrl;
 278         u64 padding64[8]; /* room for future expansion */
 279         /*
 280          * To allow migration of L1 (complete with its L2 guests) between
 281          * machines of different natural widths (32 or 64 bit), we cannot have
 282          * unsigned long fields with no explict size. We use u64 (aliased
 283          * natural_width) instead. Luckily, x86 is little-endian.
 284          */
 285         natural_width cr0_guest_host_mask;
 286         natural_width cr4_guest_host_mask;
 287         natural_width cr0_read_shadow;
 288         natural_width cr4_read_shadow;
 289         natural_width cr3_target_value0;
 290         natural_width cr3_target_value1;
 291         natural_width cr3_target_value2;
 292         natural_width cr3_target_value3;
 293         natural_width exit_qualification;
 294         natural_width guest_linear_address;
 295         natural_width guest_cr0;
 296         natural_width guest_cr3;
 297         natural_width guest_cr4;
 298         natural_width guest_es_base;
 299         natural_width guest_cs_base;
 300         natural_width guest_ss_base;
 301         natural_width guest_ds_base;
 302         natural_width guest_fs_base;
 303         natural_width guest_gs_base;
 304         natural_width guest_ldtr_base;
 305         natural_width guest_tr_base;
 306         natural_width guest_gdtr_base;
 307         natural_width guest_idtr_base;
 308         natural_width guest_dr7;
 309         natural_width guest_rsp;
 310         natural_width guest_rip;
 311         natural_width guest_rflags;
 312         natural_width guest_pending_dbg_exceptions;
 313         natural_width guest_sysenter_esp;
 314         natural_width guest_sysenter_eip;
 315         natural_width host_cr0;
 316         natural_width host_cr3;
 317         natural_width host_cr4;
 318         natural_width host_fs_base;
 319         natural_width host_gs_base;
 320         natural_width host_tr_base;
 321         natural_width host_gdtr_base;
 322         natural_width host_idtr_base;
 323         natural_width host_ia32_sysenter_esp;
 324         natural_width host_ia32_sysenter_eip;
 325         natural_width host_rsp;
 326         natural_width host_rip;
 327         natural_width paddingl[8]; /* room for future expansion */
 328         u32 pin_based_vm_exec_control;
 329         u32 cpu_based_vm_exec_control;
 330         u32 exception_bitmap;
 331         u32 page_fault_error_code_mask;
 332         u32 page_fault_error_code_match;
 333         u32 cr3_target_count;
 334         u32 vm_exit_controls;
 335         u32 vm_exit_msr_store_count;
 336         u32 vm_exit_msr_load_count;
 337         u32 vm_entry_controls;
 338         u32 vm_entry_msr_load_count;
 339         u32 vm_entry_intr_info_field;
 340         u32 vm_entry_exception_error_code;
 341         u32 vm_entry_instruction_len;
 342         u32 tpr_threshold;
 343         u32 secondary_vm_exec_control;
 344         u32 vm_instruction_error;
 345         u32 vm_exit_reason;
 346         u32 vm_exit_intr_info;
 347         u32 vm_exit_intr_error_code;
 348         u32 idt_vectoring_info_field;
 349         u32 idt_vectoring_error_code;
 350         u32 vm_exit_instruction_len;
 351         u32 vmx_instruction_info;
 352         u32 guest_es_limit;
 353         u32 guest_cs_limit;
 354         u32 guest_ss_limit;
 355         u32 guest_ds_limit;
 356         u32 guest_fs_limit;
 357         u32 guest_gs_limit;
 358         u32 guest_ldtr_limit;
 359         u32 guest_tr_limit;
 360         u32 guest_gdtr_limit;
 361         u32 guest_idtr_limit;
 362         u32 guest_es_ar_bytes;
 363         u32 guest_cs_ar_bytes;
 364         u32 guest_ss_ar_bytes;
 365         u32 guest_ds_ar_bytes;
 366         u32 guest_fs_ar_bytes;
 367         u32 guest_gs_ar_bytes;
 368         u32 guest_ldtr_ar_bytes;
 369         u32 guest_tr_ar_bytes;
 370         u32 guest_interruptibility_info;
 371         u32 guest_activity_state;
 372         u32 guest_sysenter_cs;
 373         u32 host_ia32_sysenter_cs;
 374         u32 vmx_preemption_timer_value;
 375         u32 padding32[7]; /* room for future expansion */
 376         u16 virtual_processor_id;
 377         u16 posted_intr_nv;
 378         u16 guest_es_selector;
 379         u16 guest_cs_selector;
 380         u16 guest_ss_selector;
 381         u16 guest_ds_selector;
 382         u16 guest_fs_selector;
 383         u16 guest_gs_selector;
 384         u16 guest_ldtr_selector;
 385         u16 guest_tr_selector;
 386         u16 guest_intr_status;
 387         u16 guest_pml_index;
 388         u16 host_es_selector;
 389         u16 host_cs_selector;
 390         u16 host_ss_selector;
 391         u16 host_ds_selector;
 392         u16 host_fs_selector;
 393         u16 host_gs_selector;
 394         u16 host_tr_selector;
 395 };
 396
 397 /*
 398  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 399  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 400  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 401  */
 402 #define VMCS12_REVISION 0x11e57ed0
 403
 404 /*
 405  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 406  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 407  * current implementation, 4K are reserved to avoid future complications.
 408  */
 409 #define VMCS12_SIZE 0x1000
 410
 411 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 412 struct vmcs02_list {
 413         struct list_head list;
 414         gpa_t vmptr;
 415         struct loaded_vmcs vmcs02;
 416 };
 417
 418 /*
 419  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 420  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 421  */
 422 struct nested_vmx {
 423         /* Has the level1 guest done vmxon? */
 424         bool vmxon;
 425         gpa_t vmxon_ptr;
 426         bool pml_full;
 427
 428         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 429         gpa_t current_vmptr;
 430         /*
 431          * Cache of the guest's VMCS, existing outside of guest memory.
 432          * Loaded from guest memory during VMPTRLD. Flushed to guest
 433          * memory during VMCLEAR and VMPTRLD.
 434          */
 435         struct vmcs12 *cached_vmcs12;
 436         /*
 437          * Indicates if the shadow vmcs must be updated with the
 438          * data hold by vmcs12
 439          */
 440         bool sync_shadow_vmcs;
 441
 442         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 443         struct list_head vmcs02_pool;
 444         int vmcs02_num;
 445         bool change_vmcs01_virtual_x2apic_mode;
 446         /* L2 must run next, and mustn't decide to exit to L1. */
 447         bool nested_run_pending;
 448         /*
 449          * Guest pages referred to in vmcs02 with host-physical pointers, so
 450          * we must keep them pinned while L2 runs.
 451          */
 452         struct page *apic_access_page;
 453         struct page *virtual_apic_page;
 454         struct page *pi_desc_page;
 455         struct pi_desc *pi_desc;
 456         bool pi_pending;
 457         u16 posted_intr_nv;
 458
 459         unsigned long *msr_bitmap;
 460
 461         struct hrtimer preemption_timer;
 462         bool preemption_timer_expired;
 463
 464         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 465         u64 vmcs01_debugctl;
 466
 467         u16 vpid02;
 468         u16 last_vpid;
 469
 470         /*
 471          * We only store the "true" versions of the VMX capability MSRs. We
 472          * generate the "non-true" versions by setting the must-be-1 bits
 473          * according to the SDM.
 474          */
 475         u32 nested_vmx_procbased_ctls_low;
 476         u32 nested_vmx_procbased_ctls_high;
 477         u32 nested_vmx_secondary_ctls_low;
 478         u32 nested_vmx_secondary_ctls_high;
 479         u32 nested_vmx_pinbased_ctls_low;
 480         u32 nested_vmx_pinbased_ctls_high;
 481         u32 nested_vmx_exit_ctls_low;
 482         u32 nested_vmx_exit_ctls_high;
 483         u32 nested_vmx_entry_ctls_low;
 484         u32 nested_vmx_entry_ctls_high;
 485         u32 nested_vmx_misc_low;
 486         u32 nested_vmx_misc_high;
 487         u32 nested_vmx_ept_caps;
 488         u32 nested_vmx_vpid_caps;
 489         u64 nested_vmx_basic;
 490         u64 nested_vmx_cr0_fixed0;
 491         u64 nested_vmx_cr0_fixed1;
 492         u64 nested_vmx_cr4_fixed0;
 493         u64 nested_vmx_cr4_fixed1;
 494         u64 nested_vmx_vmcs_enum;
 495         u64 nested_vmx_vmfunc_controls;
 496
 497         /* SMM related state */
 498         struct {
 499                 /* in VMX operation on SMM entry? */
 500                 bool vmxon;
 501                 /* in guest mode on SMM entry? */
 502                 bool guest_mode;
 503         } smm;
 504 };
 505
 506 #define POSTED_INTR_ON  0
 507 #define POSTED_INTR_SN  1
 508
 509 /* Posted-Interrupt Descriptor */
 510 struct pi_desc {
 511         u32 pir[8];     /* Posted interrupt requested */
 512         union {
 513                 struct {
 514                                 /* bit 256 - Outstanding Notification */
 515                         u16     on      : 1,
 516                                 /* bit 257 - Suppress Notification */
 517                                 sn      : 1,
 518                                 /* bit 271:258 - Reserved */
 519                                 rsvd_1  : 14;
 520                                 /* bit 279:272 - Notification Vector */
 521                         u8      nv;
 522                                 /* bit 287:280 - Reserved */
 523                         u8      rsvd_2;
 524                                 /* bit 319:288 - Notification Destination */
 525                         u32     ndst;
 526                 };
 527                 u64 control;
 528         };
 529         u32 rsvd[6];
 530 } __aligned(64);
 531
 532 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 533 {
 534         return test_and_set_bit(POSTED_INTR_ON,
 535                         (unsigned long *)&pi_desc->control);
 536 }
 537
 538 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 539 {
 540         return test_and_clear_bit(POSTED_INTR_ON,
 541                         (unsigned long *)&pi_desc->control);
 542 }
 543
 544 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 545 {
 546         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 547 }
 548
 549 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 550 {
 551         return clear_bit(POSTED_INTR_SN,
 552                         (unsigned long *)&pi_desc->control);
 553 }
 554
 555 static inline void pi_set_sn(struct pi_desc *pi_desc)
 556 {
 557         return set_bit(POSTED_INTR_SN,
 558                         (unsigned long *)&pi_desc->control);
 559 }
 560
 561 static inline void pi_clear_on(struct pi_desc *pi_desc)
 562 {
 563         clear_bit(POSTED_INTR_ON,
 564                   (unsigned long *)&pi_desc->control);
 565 }
 566
 567 static inline int pi_test_on(struct pi_desc *pi_desc)
 568 {
 569         return test_bit(POSTED_INTR_ON,
 570                         (unsigned long *)&pi_desc->control);
 571 }
 572
 573 static inline int pi_test_sn(struct pi_desc *pi_desc)
 574 {
 575         return test_bit(POSTED_INTR_SN,
 576                         (unsigned long *)&pi_desc->control);
 577 }
 578
 579 struct vcpu_vmx {
 580         struct kvm_vcpu       vcpu;
 581         unsigned long         host_rsp;
 582         u8                    fail;
 583         u32                   exit_intr_info;
 584         u32                   idt_vectoring_info;
 585         ulong                 rflags;
 586         struct shared_msr_entry *guest_msrs;
 587         int                   nmsrs;
 588         int                   save_nmsrs;
 589         unsigned long         host_idt_base;
 590 #ifdef CONFIG_X86_64
 591         u64                   msr_host_kernel_gs_base;
 592         u64                   msr_guest_kernel_gs_base;
 593 #endif
 594         u32 vm_entry_controls_shadow;
 595         u32 vm_exit_controls_shadow;
 596         u32 secondary_exec_control;
 597
 598         /*
 599          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 600          * non-nested (L1) guest, it always points to vmcs01. For a nested
 601          * guest (L2), it points to a different VMCS.
 602          */
 603         struct loaded_vmcs    vmcs01;
 604         struct loaded_vmcs   *loaded_vmcs;
 605         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 606         struct msr_autoload {
 607                 unsigned nr;
 608                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 609                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 610         } msr_autoload;
 611         struct {
 612                 int           loaded;
 613                 u16           fs_sel, gs_sel, ldt_sel;
 614 #ifdef CONFIG_X86_64
 615                 u16           ds_sel, es_sel;
 616 #endif
 617                 int           gs_ldt_reload_needed;
 618                 int           fs_reload_needed;
 619                 u64           msr_host_bndcfgs;
 620         } host_state;
 621         struct {
 622                 int vm86_active;
 623                 ulong save_rflags;
 624                 struct kvm_segment segs[8];
 625         } rmode;
 626         struct {
 627                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 628                 struct kvm_save_segment {
 629                         u16 selector;
 630                         unsigned long base;
 631                         u32 limit;
 632                         u32 ar;
 633                 } seg[8];
 634         } segment_cache;
 635         int vpid;
 636         bool emulation_required;
 637
 638         u32 exit_reason;
 639
 640         /* Posted interrupt descriptor */
 641         struct pi_desc pi_desc;
 642
 643         /* Support for a guest hypervisor (nested VMX) */
 644         struct nested_vmx nested;
 645
 646         /* Dynamic PLE window. */
 647         int ple_window;
 648         bool ple_window_dirty;
 649
 650         /* Support for PML */
 651 #define PML_ENTITY_NUM          512
 652         struct page *pml_pg;
 653
 654         /* apic deadline value in host tsc */
 655         u64 hv_deadline_tsc;
 656
 657         u64 current_tsc_ratio;
 658
 659         u32 host_pkru;
 660
 661         /*
 662          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 663          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 664          * in msr_ia32_feature_control_valid_bits.
 665          */
 666         u64 msr_ia32_feature_control;
 667         u64 msr_ia32_feature_control_valid_bits;
 668 };
 669
 670 enum segment_cache_field {
 671         SEG_FIELD_SEL = 0,
 672         SEG_FIELD_BASE = 1,
 673         SEG_FIELD_LIMIT = 2,
 674         SEG_FIELD_AR = 3,
 675
 676         SEG_FIELD_NR = 4
 677 };
 678
 679 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 680 {
 681         return container_of(vcpu, struct vcpu_vmx, vcpu);
 682 }
 683
 684 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 685 {
 686         return &(to_vmx(vcpu)->pi_desc);
 687 }
 688
 689 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 690 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 691 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 692                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 693
 694
 695 static unsigned long shadow_read_only_fields[] = {
 696         /*
 697          * We do NOT shadow fields that are modified when L0
 698          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 699          * VMXON...) executed by L1.
 700          * For example, VM_INSTRUCTION_ERROR is read
 701          * by L1 if a vmx instruction fails (part of the error path).
 702          * Note the code assumes this logic. If for some reason
 703          * we start shadowing these fields then we need to
 704          * force a shadow sync when L0 emulates vmx instructions
 705          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 706          * by nested_vmx_failValid)
 707          */
 708         VM_EXIT_REASON,
 709         VM_EXIT_INTR_INFO,
 710         VM_EXIT_INSTRUCTION_LEN,
 711         IDT_VECTORING_INFO_FIELD,
 712         IDT_VECTORING_ERROR_CODE,
 713         VM_EXIT_INTR_ERROR_CODE,
 714         EXIT_QUALIFICATION,
 715         GUEST_LINEAR_ADDRESS,
 716         GUEST_PHYSICAL_ADDRESS
 717 };
 718 static int max_shadow_read_only_fields =
 719         ARRAY_SIZE(shadow_read_only_fields);
 720
 721 static unsigned long shadow_read_write_fields[] = {
 722         TPR_THRESHOLD,
 723         GUEST_RIP,
 724         GUEST_RSP,
 725         GUEST_CR0,
 726         GUEST_CR3,
 727         GUEST_CR4,
 728         GUEST_INTERRUPTIBILITY_INFO,
 729         GUEST_RFLAGS,
 730         GUEST_CS_SELECTOR,
 731         GUEST_CS_AR_BYTES,
 732         GUEST_CS_LIMIT,
 733         GUEST_CS_BASE,
 734         GUEST_ES_BASE,
 735         GUEST_BNDCFGS,
 736         CR0_GUEST_HOST_MASK,
 737         CR0_READ_SHADOW,
 738         CR4_READ_SHADOW,
 739         TSC_OFFSET,
 740         EXCEPTION_BITMAP,
 741         CPU_BASED_VM_EXEC_CONTROL,
 742         VM_ENTRY_EXCEPTION_ERROR_CODE,
 743         VM_ENTRY_INTR_INFO_FIELD,
 744         VM_ENTRY_INSTRUCTION_LEN,
 745         VM_ENTRY_EXCEPTION_ERROR_CODE,
 746         HOST_FS_BASE,
 747         HOST_GS_BASE,
 748         HOST_FS_SELECTOR,
 749         HOST_GS_SELECTOR
 750 };
 751 static int max_shadow_read_write_fields =
 752         ARRAY_SIZE(shadow_read_write_fields);
 753
 754 static const unsigned short vmcs_field_to_offset_table[] = {
 755         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 756         FIELD(POSTED_INTR_NV, posted_intr_nv),
 757         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 758         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 759         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 760         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 761         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 762         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 763         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 764         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 765         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 766         FIELD(GUEST_PML_INDEX, guest_pml_index),
 767         FIELD(HOST_ES_SELECTOR, host_es_selector),
 768         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 769         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 770         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 771         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 772         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 773         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 774         FIELD64(IO_BITMAP_A, io_bitmap_a),
 775         FIELD64(IO_BITMAP_B, io_bitmap_b),
 776         FIELD64(MSR_BITMAP, msr_bitmap),
 777         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 778         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 779         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 780         FIELD64(TSC_OFFSET, tsc_offset),
 781         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 782         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 783         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 784         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
 785         FIELD64(EPT_POINTER, ept_pointer),
 786         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 787         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 788         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 789         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 790         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
 791         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 792         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 793         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 794         FIELD64(PML_ADDRESS, pml_address),
 795         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 796         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 797         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 798         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 799         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 800         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 801         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 802         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 803         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 804         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 805         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 806         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 807         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 808         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 809         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 810         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 811         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 812         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 813         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 814         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 815         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 816         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 817         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 818         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 819         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 820         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 821         FIELD(TPR_THRESHOLD, tpr_threshold),
 822         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 823         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 824         FIELD(VM_EXIT_REASON, vm_exit_reason),
 825         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 826         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 827         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 828         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 829         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 830         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 831         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 832         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 833         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 834         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 835         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 836         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 837         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 838         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 839         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 840         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 841         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 842         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 843         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 844         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 845         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 846         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 847         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 848         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 849         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 850         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 851         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 852         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 853         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 854         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 855         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 856         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 857         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 858         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 859         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 860         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 861         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 862         FIELD(EXIT_QUALIFICATION, exit_qualification),
 863         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 864         FIELD(GUEST_CR0, guest_cr0),
 865         FIELD(GUEST_CR3, guest_cr3),
 866         FIELD(GUEST_CR4, guest_cr4),
 867         FIELD(GUEST_ES_BASE, guest_es_base),
 868         FIELD(GUEST_CS_BASE, guest_cs_base),
 869         FIELD(GUEST_SS_BASE, guest_ss_base),
 870         FIELD(GUEST_DS_BASE, guest_ds_base),
 871         FIELD(GUEST_FS_BASE, guest_fs_base),
 872         FIELD(GUEST_GS_BASE, guest_gs_base),
 873         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 874         FIELD(GUEST_TR_BASE, guest_tr_base),
 875         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 876         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 877         FIELD(GUEST_DR7, guest_dr7),
 878         FIELD(GUEST_RSP, guest_rsp),
 879         FIELD(GUEST_RIP, guest_rip),
 880         FIELD(GUEST_RFLAGS, guest_rflags),
 881         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 882         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 883         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 884         FIELD(HOST_CR0, host_cr0),
 885         FIELD(HOST_CR3, host_cr3),
 886         FIELD(HOST_CR4, host_cr4),
 887         FIELD(HOST_FS_BASE, host_fs_base),
 888         FIELD(HOST_GS_BASE, host_gs_base),
 889         FIELD(HOST_TR_BASE, host_tr_base),
 890         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 891         FIELD(HOST_IDTR_BASE, host_idtr_base),
 892         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 893         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 894         FIELD(HOST_RSP, host_rsp),
 895         FIELD(HOST_RIP, host_rip),
 896 };
 897
 898 static inline short vmcs_field_to_offset(unsigned long field)
 899 {
 900         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 901
 902         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table))
 903                 return -ENOENT;
 904
 905         /*
 906          * FIXME: Mitigation for CVE-2017-5753.  To be replaced with a
 907          * generic mechanism.
 908          */
 909         asm("lfence");
 910
 911         if (vmcs_field_to_offset_table[field] == 0)
 912                 return -ENOENT;
 913
 914         return vmcs_field_to_offset_table[field];
 915 }
 916
 917 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 918 {
 919         return to_vmx(vcpu)->nested.cached_vmcs12;
 920 }
 921
 922 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
 923 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 924 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 925 static bool vmx_xsaves_supported(void);
 926 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 927                             struct kvm_segment *var, int seg);
 928 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 929                             struct kvm_segment *var, int seg);
 930 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 931 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 932 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 933 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 934 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 935 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
 936                                             u16 error_code);
 937
 938 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 939 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 940 /*
 941  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 942  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 943  */
 944 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 945
 946 /*
 947  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 948  * can find which vCPU should be waken up.
 949  */
 950 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 951 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 952
 953 enum {
 954         VMX_IO_BITMAP_A,
 955         VMX_IO_BITMAP_B,
 956         VMX_MSR_BITMAP_LEGACY,
 957         VMX_MSR_BITMAP_LONGMODE,
 958         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 959         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 960         VMX_MSR_BITMAP_LEGACY_X2APIC,
 961         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 962         VMX_VMREAD_BITMAP,
 963         VMX_VMWRITE_BITMAP,
 964         VMX_BITMAP_NR
 965 };
 966
 967 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 968
 969 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 970 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 971 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 972 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 973 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 974 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 975 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 976 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 977 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 978 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 979
 980 static bool cpu_has_load_ia32_efer;
 981 static bool cpu_has_load_perf_global_ctrl;
 982
 983 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 984 static DEFINE_SPINLOCK(vmx_vpid_lock);
 985
 986 static struct vmcs_config {
 987         int size;
 988         int order;
 989         u32 basic_cap;
 990         u32 revision_id;
 991         u32 pin_based_exec_ctrl;
 992         u32 cpu_based_exec_ctrl;
 993         u32 cpu_based_2nd_exec_ctrl;
 994         u32 vmexit_ctrl;
 995         u32 vmentry_ctrl;
 996 } vmcs_config;
 997
 998 static struct vmx_capability {
 999         u32 ept;
1000         u32 vpid;
1001 } vmx_capability;
1002
1003 #define VMX_SEGMENT_FIELD(seg)                                  \
1004         [VCPU_SREG_##seg] = {                                   \
1005                 .selector = GUEST_##seg##_SELECTOR,             \
1006                 .base = GUEST_##seg##_BASE,                     \
1007                 .limit = GUEST_##seg##_LIMIT,                   \
1008                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1009         }
1010
1011 static const struct kvm_vmx_segment_field {
1012         unsigned selector;
1013         unsigned base;
1014         unsigned limit;
1015         unsigned ar_bytes;
1016 } kvm_vmx_segment_fields[] = {
1017         VMX_SEGMENT_FIELD(CS),
1018         VMX_SEGMENT_FIELD(DS),
1019         VMX_SEGMENT_FIELD(ES),
1020         VMX_SEGMENT_FIELD(FS),
1021         VMX_SEGMENT_FIELD(GS),
1022         VMX_SEGMENT_FIELD(SS),
1023         VMX_SEGMENT_FIELD(TR),
1024         VMX_SEGMENT_FIELD(LDTR),
1025 };
1026
1027 static u64 host_efer;
1028
1029 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1030
1031 /*
1032  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1033  * away by decrementing the array size.
1034  */
1035 static const u32 vmx_msr_index[] = {
1036 #ifdef CONFIG_X86_64
1037         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1038 #endif
1039         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1040 };
1041
1042 static inline bool is_exception_n(u32 intr_info, u8 vector)
1043 {
1044         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1045                              INTR_INFO_VALID_MASK)) ==
1046                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1047 }
1048
1049 static inline bool is_debug(u32 intr_info)
1050 {
1051         return is_exception_n(intr_info, DB_VECTOR);
1052 }
1053
1054 static inline bool is_breakpoint(u32 intr_info)
1055 {
1056         return is_exception_n(intr_info, BP_VECTOR);
1057 }
1058
1059 static inline bool is_page_fault(u32 intr_info)
1060 {
1061         return is_exception_n(intr_info, PF_VECTOR);
1062 }
1063
1064 static inline bool is_no_device(u32 intr_info)
1065 {
1066         return is_exception_n(intr_info, NM_VECTOR);
1067 }
1068
1069 static inline bool is_invalid_opcode(u32 intr_info)
1070 {
1071         return is_exception_n(intr_info, UD_VECTOR);
1072 }
1073
1074 static inline bool is_external_interrupt(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1077                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1078 }
1079
1080 static inline bool is_machine_check(u32 intr_info)
1081 {
1082         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1083                              INTR_INFO_VALID_MASK)) ==
1084                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1085 }
1086
1087 static inline bool cpu_has_vmx_msr_bitmap(void)
1088 {
1089         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1090 }
1091
1092 static inline bool cpu_has_vmx_tpr_shadow(void)
1093 {
1094         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1095 }
1096
1097 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1098 {
1099         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1100 }
1101
1102 static inline bool cpu_has_secondary_exec_ctrls(void)
1103 {
1104         return vmcs_config.cpu_based_exec_ctrl &
1105                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1106 }
1107
1108 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1109 {
1110         return vmcs_config.cpu_based_2nd_exec_ctrl &
1111                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1112 }
1113
1114 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1115 {
1116         return vmcs_config.cpu_based_2nd_exec_ctrl &
1117                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1118 }
1119
1120 static inline bool cpu_has_vmx_apic_register_virt(void)
1121 {
1122         return vmcs_config.cpu_based_2nd_exec_ctrl &
1123                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1124 }
1125
1126 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1127 {
1128         return vmcs_config.cpu_based_2nd_exec_ctrl &
1129                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1130 }
1131
1132 /*
1133  * Comment's format: document - errata name - stepping - processor name.
1134  * Refer from
1135  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1136  */
1137 static u32 vmx_preemption_cpu_tfms[] = {
1138 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1139 0x000206E6,
1140 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1141 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1142 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1143 0x00020652,
1144 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1145 0x00020655,
1146 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1147 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1148 /*
1149  * 320767.pdf - AAP86  - B1 -
1150  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1151  */
1152 0x000106E5,
1153 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1154 0x000106A0,
1155 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1156 0x000106A1,
1157 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1158 0x000106A4,
1159  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1160  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1161  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1162 0x000106A5,
1163 };
1164
1165 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1166 {
1167         u32 eax = cpuid_eax(0x00000001), i;
1168
1169         /* Clear the reserved bits */
1170         eax &= ~(0x3U << 14 | 0xfU << 28);
1171         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1172                 if (eax == vmx_preemption_cpu_tfms[i])
1173                         return true;
1174
1175         return false;
1176 }
1177
1178 static inline bool cpu_has_vmx_preemption_timer(void)
1179 {
1180         return vmcs_config.pin_based_exec_ctrl &
1181                 PIN_BASED_VMX_PREEMPTION_TIMER;
1182 }
1183
1184 static inline bool cpu_has_vmx_posted_intr(void)
1185 {
1186         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1187                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1188 }
1189
1190 static inline bool cpu_has_vmx_apicv(void)
1191 {
1192         return cpu_has_vmx_apic_register_virt() &&
1193                 cpu_has_vmx_virtual_intr_delivery() &&
1194                 cpu_has_vmx_posted_intr();
1195 }
1196
1197 static inline bool cpu_has_vmx_flexpriority(void)
1198 {
1199         return cpu_has_vmx_tpr_shadow() &&
1200                 cpu_has_vmx_virtualize_apic_accesses();
1201 }
1202
1203 static inline bool cpu_has_vmx_ept_execute_only(void)
1204 {
1205         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1206 }
1207
1208 static inline bool cpu_has_vmx_ept_2m_page(void)
1209 {
1210         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1211 }
1212
1213 static inline bool cpu_has_vmx_ept_1g_page(void)
1214 {
1215         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1216 }
1217
1218 static inline bool cpu_has_vmx_ept_4levels(void)
1219 {
1220         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1221 }
1222
1223 static inline bool cpu_has_vmx_ept_mt_wb(void)
1224 {
1225         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1226 }
1227
1228 static inline bool cpu_has_vmx_ept_5levels(void)
1229 {
1230         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1231 }
1232
1233 static inline bool cpu_has_vmx_ept_ad_bits(void)
1234 {
1235         return vmx_capability.ept & VMX_EPT_AD_BIT;
1236 }
1237
1238 static inline bool cpu_has_vmx_invept_context(void)
1239 {
1240         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1241 }
1242
1243 static inline bool cpu_has_vmx_invept_global(void)
1244 {
1245         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1246 }
1247
1248 static inline bool cpu_has_vmx_invvpid_single(void)
1249 {
1250         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1251 }
1252
1253 static inline bool cpu_has_vmx_invvpid_global(void)
1254 {
1255         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1256 }
1257
1258 static inline bool cpu_has_vmx_invvpid(void)
1259 {
1260         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1261 }
1262
1263 static inline bool cpu_has_vmx_ept(void)
1264 {
1265         return vmcs_config.cpu_based_2nd_exec_ctrl &
1266                 SECONDARY_EXEC_ENABLE_EPT;
1267 }
1268
1269 static inline bool cpu_has_vmx_unrestricted_guest(void)
1270 {
1271         return vmcs_config.cpu_based_2nd_exec_ctrl &
1272                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1273 }
1274
1275 static inline bool cpu_has_vmx_ple(void)
1276 {
1277         return vmcs_config.cpu_based_2nd_exec_ctrl &
1278                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1279 }
1280
1281 static inline bool cpu_has_vmx_basic_inout(void)
1282 {
1283         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1284 }
1285
1286 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1287 {
1288         return flexpriority_enabled && lapic_in_kernel(vcpu);
1289 }
1290
1291 static inline bool cpu_has_vmx_vpid(void)
1292 {
1293         return vmcs_config.cpu_based_2nd_exec_ctrl &
1294                 SECONDARY_EXEC_ENABLE_VPID;
1295 }
1296
1297 static inline bool cpu_has_vmx_rdtscp(void)
1298 {
1299         return vmcs_config.cpu_based_2nd_exec_ctrl &
1300                 SECONDARY_EXEC_RDTSCP;
1301 }
1302
1303 static inline bool cpu_has_vmx_invpcid(void)
1304 {
1305         return vmcs_config.cpu_based_2nd_exec_ctrl &
1306                 SECONDARY_EXEC_ENABLE_INVPCID;
1307 }
1308
1309 static inline bool cpu_has_virtual_nmis(void)
1310 {
1311         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1312 }
1313
1314 static inline bool cpu_has_vmx_wbinvd_exit(void)
1315 {
1316         return vmcs_config.cpu_based_2nd_exec_ctrl &
1317                 SECONDARY_EXEC_WBINVD_EXITING;
1318 }
1319
1320 static inline bool cpu_has_vmx_shadow_vmcs(void)
1321 {
1322         u64 vmx_msr;
1323         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1324         /* check if the cpu supports writing r/o exit information fields */
1325         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1326                 return false;
1327
1328         return vmcs_config.cpu_based_2nd_exec_ctrl &
1329                 SECONDARY_EXEC_SHADOW_VMCS;
1330 }
1331
1332 static inline bool cpu_has_vmx_pml(void)
1333 {
1334         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1335 }
1336
1337 static inline bool cpu_has_vmx_tsc_scaling(void)
1338 {
1339         return vmcs_config.cpu_based_2nd_exec_ctrl &
1340                 SECONDARY_EXEC_TSC_SCALING;
1341 }
1342
1343 static inline bool cpu_has_vmx_vmfunc(void)
1344 {
1345         return vmcs_config.cpu_based_2nd_exec_ctrl &
1346                 SECONDARY_EXEC_ENABLE_VMFUNC;
1347 }
1348
1349 static inline bool report_flexpriority(void)
1350 {
1351         return flexpriority_enabled;
1352 }
1353
1354 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1355 {
1356         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1357 }
1358
1359 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1360 {
1361         return vmcs12->cpu_based_vm_exec_control & bit;
1362 }
1363
1364 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1365 {
1366         return (vmcs12->cpu_based_vm_exec_control &
1367                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1368                 (vmcs12->secondary_vm_exec_control & bit);
1369 }
1370
1371 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1372 {
1373         return vmcs12->pin_based_vm_exec_control &
1374                 PIN_BASED_VMX_PREEMPTION_TIMER;
1375 }
1376
1377 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1378 {
1379         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1380 }
1381
1382 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1383 {
1384         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1385 }
1386
1387 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1388 {
1389         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1390 }
1391
1392 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1393 {
1394         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1395 }
1396
1397 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1398 {
1399         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1400 }
1401
1402 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1403 {
1404         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1405 }
1406
1407 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1408 {
1409         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1410 }
1411
1412 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1413 {
1414         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1415 }
1416
1417 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1418 {
1419         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1420 }
1421
1422 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1423 {
1424         return nested_cpu_has_vmfunc(vmcs12) &&
1425                 (vmcs12->vm_function_control &
1426                  VMX_VMFUNC_EPTP_SWITCHING);
1427 }
1428
1429 static inline bool is_nmi(u32 intr_info)
1430 {
1431         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1432                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1433 }
1434
1435 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1436                               u32 exit_intr_info,
1437                               unsigned long exit_qualification);
1438 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1439                         struct vmcs12 *vmcs12,
1440                         u32 reason, unsigned long qualification);
1441
1442 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1443 {
1444         int i;
1445
1446         for (i = 0; i < vmx->nmsrs; ++i)
1447                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1448                         return i;
1449         return -1;
1450 }
1451
1452 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1453 {
1454     struct {
1455         u64 vpid : 16;
1456         u64 rsvd : 48;
1457         u64 gva;
1458     } operand = { vpid, 0, gva };
1459
1460     asm volatile (__ex(ASM_VMX_INVVPID)
1461                   /* CF==1 or ZF==1 --> rc = -1 */
1462                   "; ja 1f ; ud2 ; 1:"
1463                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1464 }
1465
1466 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1467 {
1468         struct {
1469                 u64 eptp, gpa;
1470         } operand = {eptp, gpa};
1471
1472         asm volatile (__ex(ASM_VMX_INVEPT)
1473                         /* CF==1 or ZF==1 --> rc = -1 */
1474                         "; ja 1f ; ud2 ; 1:\n"
1475                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1476 }
1477
1478 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1479 {
1480         int i;
1481
1482         i = __find_msr_index(vmx, msr);
1483         if (i >= 0)
1484                 return &vmx->guest_msrs[i];
1485         return NULL;
1486 }
1487
1488 static void vmcs_clear(struct vmcs *vmcs)
1489 {
1490         u64 phys_addr = __pa(vmcs);
1491         u8 error;
1492
1493         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1494                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1495                       : "cc", "memory");
1496         if (error)
1497                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1498                        vmcs, phys_addr);
1499 }
1500
1501 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1502 {
1503         vmcs_clear(loaded_vmcs->vmcs);
1504         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1505                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1506         loaded_vmcs->cpu = -1;
1507         loaded_vmcs->launched = 0;
1508 }
1509
1510 static void vmcs_load(struct vmcs *vmcs)
1511 {
1512         u64 phys_addr = __pa(vmcs);
1513         u8 error;
1514
1515         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1516                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1517                         : "cc", "memory");
1518         if (error)
1519                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1520                        vmcs, phys_addr);
1521 }
1522
1523 #ifdef CONFIG_KEXEC_CORE
1524 /*
1525  * This bitmap is used to indicate whether the vmclear
1526  * operation is enabled on all cpus. All disabled by
1527  * default.
1528  */
1529 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1530
1531 static inline void crash_enable_local_vmclear(int cpu)
1532 {
1533         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1534 }
1535
1536 static inline void crash_disable_local_vmclear(int cpu)
1537 {
1538         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1539 }
1540
1541 static inline int crash_local_vmclear_enabled(int cpu)
1542 {
1543         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1544 }
1545
1546 static void crash_vmclear_local_loaded_vmcss(void)
1547 {
1548         int cpu = raw_smp_processor_id();
1549         struct loaded_vmcs *v;
1550
1551         if (!crash_local_vmclear_enabled(cpu))
1552                 return;
1553
1554         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1555                             loaded_vmcss_on_cpu_link)
1556                 vmcs_clear(v->vmcs);
1557 }
1558 #else
1559 static inline void crash_enable_local_vmclear(int cpu) { }
1560 static inline void crash_disable_local_vmclear(int cpu) { }
1561 #endif /* CONFIG_KEXEC_CORE */
1562
1563 static void __loaded_vmcs_clear(void *arg)
1564 {
1565         struct loaded_vmcs *loaded_vmcs = arg;
1566         int cpu = raw_smp_processor_id();
1567
1568         if (loaded_vmcs->cpu != cpu)
1569                 return; /* vcpu migration can race with cpu offline */
1570         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1571                 per_cpu(current_vmcs, cpu) = NULL;
1572         crash_disable_local_vmclear(cpu);
1573         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1574
1575         /*
1576          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1577          * is before setting loaded_vmcs->vcpu to -1 which is done in
1578          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1579          * then adds the vmcs into percpu list before it is deleted.
1580          */
1581         smp_wmb();
1582
1583         loaded_vmcs_init(loaded_vmcs);
1584         crash_enable_local_vmclear(cpu);
1585 }
1586
1587 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1588 {
1589         int cpu = loaded_vmcs->cpu;
1590
1591         if (cpu != -1)
1592                 smp_call_function_single(cpu,
1593                          __loaded_vmcs_clear, loaded_vmcs, 1);
1594 }
1595
1596 static inline void vpid_sync_vcpu_single(int vpid)
1597 {
1598         if (vpid == 0)
1599                 return;
1600
1601         if (cpu_has_vmx_invvpid_single())
1602                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1603 }
1604
1605 static inline void vpid_sync_vcpu_global(void)
1606 {
1607         if (cpu_has_vmx_invvpid_global())
1608                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1609 }
1610
1611 static inline void vpid_sync_context(int vpid)
1612 {
1613         if (cpu_has_vmx_invvpid_single())
1614                 vpid_sync_vcpu_single(vpid);
1615         else
1616                 vpid_sync_vcpu_global();
1617 }
1618
1619 static inline void ept_sync_global(void)
1620 {
1621         __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1622 }
1623
1624 static inline void ept_sync_context(u64 eptp)
1625 {
1626         if (cpu_has_vmx_invept_context())
1627                 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1628         else
1629                 ept_sync_global();
1630 }
1631
1632 static __always_inline void vmcs_check16(unsigned long field)
1633 {
1634         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1635                          "16-bit accessor invalid for 64-bit field");
1636         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1637                          "16-bit accessor invalid for 64-bit high field");
1638         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1639                          "16-bit accessor invalid for 32-bit high field");
1640         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1641                          "16-bit accessor invalid for natural width field");
1642 }
1643
1644 static __always_inline void vmcs_check32(unsigned long field)
1645 {
1646         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1647                          "32-bit accessor invalid for 16-bit field");
1648         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1649                          "32-bit accessor invalid for natural width field");
1650 }
1651
1652 static __always_inline void vmcs_check64(unsigned long field)
1653 {
1654         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1655                          "64-bit accessor invalid for 16-bit field");
1656         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1657                          "64-bit accessor invalid for 64-bit high field");
1658         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1659                          "64-bit accessor invalid for 32-bit field");
1660         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1661                          "64-bit accessor invalid for natural width field");
1662 }
1663
1664 static __always_inline void vmcs_checkl(unsigned long field)
1665 {
1666         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1667                          "Natural width accessor invalid for 16-bit field");
1668         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1669                          "Natural width accessor invalid for 64-bit field");
1670         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1671                          "Natural width accessor invalid for 64-bit high field");
1672         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1673                          "Natural width accessor invalid for 32-bit field");
1674 }
1675
1676 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1677 {
1678         unsigned long value;
1679
1680         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1681                       : "=a"(value) : "d"(field) : "cc");
1682         return value;
1683 }
1684
1685 static __always_inline u16 vmcs_read16(unsigned long field)
1686 {
1687         vmcs_check16(field);
1688         return __vmcs_readl(field);
1689 }
1690
1691 static __always_inline u32 vmcs_read32(unsigned long field)
1692 {
1693         vmcs_check32(field);
1694         return __vmcs_readl(field);
1695 }
1696
1697 static __always_inline u64 vmcs_read64(unsigned long field)
1698 {
1699         vmcs_check64(field);
1700 #ifdef CONFIG_X86_64
1701         return __vmcs_readl(field);
1702 #else
1703         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1704 #endif
1705 }
1706
1707 static __always_inline unsigned long vmcs_readl(unsigned long field)
1708 {
1709         vmcs_checkl(field);
1710         return __vmcs_readl(field);
1711 }
1712
1713 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1714 {
1715         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1716                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1717         dump_stack();
1718 }
1719
1720 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1721 {
1722         u8 error;
1723
1724         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1725                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1726         if (unlikely(error))
1727                 vmwrite_error(field, value);
1728 }
1729
1730 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1731 {
1732         vmcs_check16(field);
1733         __vmcs_writel(field, value);
1734 }
1735
1736 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1737 {
1738         vmcs_check32(field);
1739         __vmcs_writel(field, value);
1740 }
1741
1742 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1743 {
1744         vmcs_check64(field);
1745         __vmcs_writel(field, value);
1746 #ifndef CONFIG_X86_64
1747         asm volatile ("");
1748         __vmcs_writel(field+1, value >> 32);
1749 #endif
1750 }
1751
1752 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1753 {
1754         vmcs_checkl(field);
1755         __vmcs_writel(field, value);
1756 }
1757
1758 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1759 {
1760         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1761                          "vmcs_clear_bits does not support 64-bit fields");
1762         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1763 }
1764
1765 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1766 {
1767         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1768                          "vmcs_set_bits does not support 64-bit fields");
1769         __vmcs_writel(field, __vmcs_readl(field) | mask);
1770 }
1771
1772 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1773 {
1774         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1775 }
1776
1777 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1778 {
1779         vmcs_write32(VM_ENTRY_CONTROLS, val);
1780         vmx->vm_entry_controls_shadow = val;
1781 }
1782
1783 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1784 {
1785         if (vmx->vm_entry_controls_shadow != val)
1786                 vm_entry_controls_init(vmx, val);
1787 }
1788
1789 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1790 {
1791         return vmx->vm_entry_controls_shadow;
1792 }
1793
1794
1795 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1796 {
1797         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1798 }
1799
1800 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1801 {
1802         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1803 }
1804
1805 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1806 {
1807         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1808 }
1809
1810 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1811 {
1812         vmcs_write32(VM_EXIT_CONTROLS, val);
1813         vmx->vm_exit_controls_shadow = val;
1814 }
1815
1816 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1817 {
1818         if (vmx->vm_exit_controls_shadow != val)
1819                 vm_exit_controls_init(vmx, val);
1820 }
1821
1822 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1823 {
1824         return vmx->vm_exit_controls_shadow;
1825 }
1826
1827
1828 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1829 {
1830         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1831 }
1832
1833 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1834 {
1835         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1836 }
1837
1838 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1839 {
1840         vmx->segment_cache.bitmask = 0;
1841 }
1842
1843 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1844                                        unsigned field)
1845 {
1846         bool ret;
1847         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1848
1849         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1850                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1851                 vmx->segment_cache.bitmask = 0;
1852         }
1853         ret = vmx->segment_cache.bitmask & mask;
1854         vmx->segment_cache.bitmask |= mask;
1855         return ret;
1856 }
1857
1858 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1859 {
1860         u16 *p = &vmx->segment_cache.seg[seg].selector;
1861
1862         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1863                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1864         return *p;
1865 }
1866
1867 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1868 {
1869         ulong *p = &vmx->segment_cache.seg[seg].base;
1870
1871         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1872                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1873         return *p;
1874 }
1875
1876 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1877 {
1878         u32 *p = &vmx->segment_cache.seg[seg].limit;
1879
1880         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1881                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1882         return *p;
1883 }
1884
1885 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1886 {
1887         u32 *p = &vmx->segment_cache.seg[seg].ar;
1888
1889         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1890                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1891         return *p;
1892 }
1893
1894 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1895 {
1896         u32 eb;
1897
1898         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1899              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1900         if ((vcpu->guest_debug &
1901              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1902             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1903                 eb |= 1u << BP_VECTOR;
1904         if (to_vmx(vcpu)->rmode.vm86_active)
1905                 eb = ~0;
1906         if (enable_ept)
1907                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1908
1909         /* When we are running a nested L2 guest and L1 specified for it a
1910          * certain exception bitmap, we must trap the same exceptions and pass
1911          * them to L1. When running L2, we will only handle the exceptions
1912          * specified above if L1 did not want them.
1913          */
1914         if (is_guest_mode(vcpu))
1915                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1916
1917         vmcs_write32(EXCEPTION_BITMAP, eb);
1918 }
1919
1920 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1921                 unsigned long entry, unsigned long exit)
1922 {
1923         vm_entry_controls_clearbit(vmx, entry);
1924         vm_exit_controls_clearbit(vmx, exit);
1925 }
1926
1927 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1928 {
1929         unsigned i;
1930         struct msr_autoload *m = &vmx->msr_autoload;
1931
1932         switch (msr) {
1933         case MSR_EFER:
1934                 if (cpu_has_load_ia32_efer) {
1935                         clear_atomic_switch_msr_special(vmx,
1936                                         VM_ENTRY_LOAD_IA32_EFER,
1937                                         VM_EXIT_LOAD_IA32_EFER);
1938                         return;
1939                 }
1940                 break;
1941         case MSR_CORE_PERF_GLOBAL_CTRL:
1942                 if (cpu_has_load_perf_global_ctrl) {
1943                         clear_atomic_switch_msr_special(vmx,
1944                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1945                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1946                         return;
1947                 }
1948                 break;
1949         }
1950
1951         for (i = 0; i < m->nr; ++i)
1952                 if (m->guest[i].index == msr)
1953                         break;
1954
1955         if (i == m->nr)
1956                 return;
1957         --m->nr;
1958         m->guest[i] = m->guest[m->nr];
1959         m->host[i] = m->host[m->nr];
1960         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1961         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1962 }
1963
1964 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1965                 unsigned long entry, unsigned long exit,
1966                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1967                 u64 guest_val, u64 host_val)
1968 {
1969         vmcs_write64(guest_val_vmcs, guest_val);
1970         vmcs_write64(host_val_vmcs, host_val);
1971         vm_entry_controls_setbit(vmx, entry);
1972         vm_exit_controls_setbit(vmx, exit);
1973 }
1974
1975 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1976                                   u64 guest_val, u64 host_val)
1977 {
1978         unsigned i;
1979         struct msr_autoload *m = &vmx->msr_autoload;
1980
1981         switch (msr) {
1982         case MSR_EFER:
1983                 if (cpu_has_load_ia32_efer) {
1984                         add_atomic_switch_msr_special(vmx,
1985                                         VM_ENTRY_LOAD_IA32_EFER,
1986                                         VM_EXIT_LOAD_IA32_EFER,
1987                                         GUEST_IA32_EFER,
1988                                         HOST_IA32_EFER,
1989                                         guest_val, host_val);
1990                         return;
1991                 }
1992                 break;
1993         case MSR_CORE_PERF_GLOBAL_CTRL:
1994                 if (cpu_has_load_perf_global_ctrl) {
1995                         add_atomic_switch_msr_special(vmx,
1996                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1997                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1998                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1999                                         HOST_IA32_PERF_GLOBAL_CTRL,
2000                                         guest_val, host_val);
2001                         return;
2002                 }
2003                 break;
2004         case MSR_IA32_PEBS_ENABLE:
2005                 /* PEBS needs a quiescent period after being disabled (to write
2006                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
2007                  * provide that period, so a CPU could write host's record into
2008                  * guest's memory.
2009                  */
2010                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2011         }
2012
2013         for (i = 0; i < m->nr; ++i)
2014                 if (m->guest[i].index == msr)
2015                         break;
2016
2017         if (i == NR_AUTOLOAD_MSRS) {
2018                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2019                                 "Can't add msr %x\n", msr);
2020                 return;
2021         } else if (i == m->nr) {
2022                 ++m->nr;
2023                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2024                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2025         }
2026
2027         m->guest[i].index = msr;
2028         m->guest[i].value = guest_val;
2029         m->host[i].index = msr;
2030         m->host[i].value = host_val;
2031 }
2032
2033 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2034 {
2035         u64 guest_efer = vmx->vcpu.arch.efer;
2036         u64 ignore_bits = 0;
2037
2038         if (!enable_ept) {
2039                 /*
2040                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2041                  * host CPUID is more efficient than testing guest CPUID
2042                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2043                  */
2044                 if (boot_cpu_has(X86_FEATURE_SMEP))
2045                         guest_efer |= EFER_NX;
2046                 else if (!(guest_efer & EFER_NX))
2047                         ignore_bits |= EFER_NX;
2048         }
2049
2050         /*
2051          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2052          */
2053         ignore_bits |= EFER_SCE;
2054 #ifdef CONFIG_X86_64
2055         ignore_bits |= EFER_LMA | EFER_LME;
2056         /* SCE is meaningful only in long mode on Intel */
2057         if (guest_efer & EFER_LMA)
2058                 ignore_bits &= ~(u64)EFER_SCE;
2059 #endif
2060
2061         clear_atomic_switch_msr(vmx, MSR_EFER);
2062
2063         /*
2064          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2065          * On CPUs that support "load IA32_EFER", always switch EFER
2066          * atomically, since it's faster than switching it manually.
2067          */
2068         if (cpu_has_load_ia32_efer ||
2069             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2070                 if (!(guest_efer & EFER_LMA))
2071                         guest_efer &= ~EFER_LME;
2072                 if (guest_efer != host_efer)
2073                         add_atomic_switch_msr(vmx, MSR_EFER,
2074                                               guest_efer, host_efer);
2075                 return false;
2076         } else {
2077                 guest_efer &= ~ignore_bits;
2078                 guest_efer |= host_efer & ignore_bits;
2079
2080                 vmx->guest_msrs[efer_offset].data = guest_efer;
2081                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2082
2083                 return true;
2084         }
2085 }
2086
2087 #ifdef CONFIG_X86_32
2088 /*
2089  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2090  * VMCS rather than the segment table.  KVM uses this helper to figure
2091  * out the current bases to poke them into the VMCS before entry.
2092  */
2093 static unsigned long segment_base(u16 selector)
2094 {
2095         struct desc_struct *table;
2096         unsigned long v;
2097
2098         if (!(selector & ~SEGMENT_RPL_MASK))
2099                 return 0;
2100
2101         table = get_current_gdt_ro();
2102
2103         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2104                 u16 ldt_selector = kvm_read_ldt();
2105
2106                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2107                         return 0;
2108
2109                 table = (struct desc_struct *)segment_base(ldt_selector);
2110         }
2111         v = get_desc_base(&table[selector >> 3]);
2112         return v;
2113 }
2114 #endif
2115
2116 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2117 {
2118         struct vcpu_vmx *vmx = to_vmx(vcpu);
2119         int i;
2120
2121         if (vmx->host_state.loaded)
2122                 return;
2123
2124         vmx->host_state.loaded = 1;
2125         /*
2126          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2127          * allow segment selectors with cpl > 0 or ti == 1.
2128          */
2129         vmx->host_state.ldt_sel = kvm_read_ldt();
2130         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2131         savesegment(fs, vmx->host_state.fs_sel);
2132         if (!(vmx->host_state.fs_sel & 7)) {
2133                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2134                 vmx->host_state.fs_reload_needed = 0;
2135         } else {
2136                 vmcs_write16(HOST_FS_SELECTOR, 0);
2137                 vmx->host_state.fs_reload_needed = 1;
2138         }
2139         savesegment(gs, vmx->host_state.gs_sel);
2140         if (!(vmx->host_state.gs_sel & 7))
2141                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2142         else {
2143                 vmcs_write16(HOST_GS_SELECTOR, 0);
2144                 vmx->host_state.gs_ldt_reload_needed = 1;
2145         }
2146
2147 #ifdef CONFIG_X86_64
2148         savesegment(ds, vmx->host_state.ds_sel);
2149         savesegment(es, vmx->host_state.es_sel);
2150 #endif
2151
2152 #ifdef CONFIG_X86_64
2153         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2154         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2155 #else
2156         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2157         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2158 #endif
2159
2160 #ifdef CONFIG_X86_64
2161         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2162         if (is_long_mode(&vmx->vcpu))
2163                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2164 #endif
2165         if (boot_cpu_has(X86_FEATURE_MPX))
2166                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2167         for (i = 0; i < vmx->save_nmsrs; ++i)
2168                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2169                                    vmx->guest_msrs[i].data,
2170                                    vmx->guest_msrs[i].mask);
2171 }
2172
2173 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2174 {
2175         if (!vmx->host_state.loaded)
2176                 return;
2177
2178         ++vmx->vcpu.stat.host_state_reload;
2179         vmx->host_state.loaded = 0;
2180 #ifdef CONFIG_X86_64
2181         if (is_long_mode(&vmx->vcpu))
2182                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2183 #endif
2184         if (vmx->host_state.gs_ldt_reload_needed) {
2185                 kvm_load_ldt(vmx->host_state.ldt_sel);
2186 #ifdef CONFIG_X86_64
2187                 load_gs_index(vmx->host_state.gs_sel);
2188 #else
2189                 loadsegment(gs, vmx->host_state.gs_sel);
2190 #endif
2191         }
2192         if (vmx->host_state.fs_reload_needed)
2193                 loadsegment(fs, vmx->host_state.fs_sel);
2194 #ifdef CONFIG_X86_64
2195         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2196                 loadsegment(ds, vmx->host_state.ds_sel);
2197                 loadsegment(es, vmx->host_state.es_sel);
2198         }
2199 #endif
2200         invalidate_tss_limit();
2201 #ifdef CONFIG_X86_64
2202         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2203 #endif
2204         if (vmx->host_state.msr_host_bndcfgs)
2205                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2206         load_fixmap_gdt(raw_smp_processor_id());
2207 }
2208
2209 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2210 {
2211         preempt_disable();
2212         __vmx_load_host_state(vmx);
2213         preempt_enable();
2214 }
2215
2216 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2217 {
2218         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2219         struct pi_desc old, new;
2220         unsigned int dest;
2221
2222         /*
2223          * In case of hot-plug or hot-unplug, we may have to undo
2224          * vmx_vcpu_pi_put even if there is no assigned device.  And we
2225          * always keep PI.NDST up to date for simplicity: it makes the
2226          * code easier, and CPU migration is not a fast path.
2227          */
2228         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2229                 return;
2230
2231         /*
2232          * First handle the simple case where no cmpxchg is necessary; just
2233          * allow posting non-urgent interrupts.
2234          *
2235          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2236          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2237          * expects the VCPU to be on the blocked_vcpu_list that matches
2238          * PI.NDST.
2239          */
2240         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2241             vcpu->cpu == cpu) {
2242                 pi_clear_sn(pi_desc);
2243                 return;
2244         }
2245
2246         /* The full case.  */
2247         do {
2248                 old.control = new.control = pi_desc->control;
2249
2250                 dest = cpu_physical_id(cpu);
2251
2252                 if (x2apic_enabled())
2253                         new.ndst = dest;
2254                 else
2255                         new.ndst = (dest << 8) & 0xFF00;
2256
2257                 new.sn = 0;
2258         } while (cmpxchg64(&pi_desc->control, old.control,
2259                            new.control) != old.control);
2260 }
2261
2262 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2263 {
2264         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2265         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2266 }
2267
2268 /*
2269  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2270  * vcpu mutex is already taken.
2271  */
2272 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2273 {
2274         struct vcpu_vmx *vmx = to_vmx(vcpu);
2275         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2276
2277         if (!already_loaded) {
2278                 loaded_vmcs_clear(vmx->loaded_vmcs);
2279                 local_irq_disable();
2280                 crash_disable_local_vmclear(cpu);
2281
2282                 /*
2283                  * Read loaded_vmcs->cpu should be before fetching
2284                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2285                  * See the comments in __loaded_vmcs_clear().
2286                  */
2287                 smp_rmb();
2288
2289                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2290                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2291                 crash_enable_local_vmclear(cpu);
2292                 local_irq_enable();
2293         }
2294
2295         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2296                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2297                 vmcs_load(vmx->loaded_vmcs->vmcs);
2298         }
2299
2300         if (!already_loaded) {
2301                 void *gdt = get_current_gdt_ro();
2302                 unsigned long sysenter_esp;
2303
2304                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2305
2306                 /*
2307                  * Linux uses per-cpu TSS and GDT, so set these when switching
2308                  * processors.  See 22.2.4.
2309                  */
2310                 vmcs_writel(HOST_TR_BASE,
2311                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2312                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2313
2314                 /*
2315                  * VM exits change the host TR limit to 0x67 after a VM
2316                  * exit.  This is okay, since 0x67 covers everything except
2317                  * the IO bitmap and have have code to handle the IO bitmap
2318                  * being lost after a VM exit.
2319                  */
2320                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2321
2322                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2323                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2324
2325                 vmx->loaded_vmcs->cpu = cpu;
2326         }
2327
2328         /* Setup TSC multiplier */
2329         if (kvm_has_tsc_control &&
2330             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2331                 decache_tsc_multiplier(vmx);
2332
2333         vmx_vcpu_pi_load(vcpu, cpu);
2334         vmx->host_pkru = read_pkru();
2335 }
2336
2337 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2338 {
2339         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2340
2341         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2342                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2343                 !kvm_vcpu_apicv_active(vcpu))
2344                 return;
2345
2346         /* Set SN when the vCPU is preempted */
2347         if (vcpu->preempted)
2348                 pi_set_sn(pi_desc);
2349 }
2350
2351 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2352 {
2353         vmx_vcpu_pi_put(vcpu);
2354
2355         __vmx_load_host_state(to_vmx(vcpu));
2356 }
2357
2358 static bool emulation_required(struct kvm_vcpu *vcpu)
2359 {
2360         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2361 }
2362
2363 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2364
2365 /*
2366  * Return the cr0 value that a nested guest would read. This is a combination
2367  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2368  * its hypervisor (cr0_read_shadow).
2369  */
2370 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2371 {
2372         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2373                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2374 }
2375 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2376 {
2377         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2378                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2379 }
2380
2381 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2382 {
2383         unsigned long rflags, save_rflags;
2384
2385         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2386                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2387                 rflags = vmcs_readl(GUEST_RFLAGS);
2388                 if (to_vmx(vcpu)->rmode.vm86_active) {
2389                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2390                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2391                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2392                 }
2393                 to_vmx(vcpu)->rflags = rflags;
2394         }
2395         return to_vmx(vcpu)->rflags;
2396 }
2397
2398 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2399 {
2400         unsigned long old_rflags = vmx_get_rflags(vcpu);
2401
2402         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2403         to_vmx(vcpu)->rflags = rflags;
2404         if (to_vmx(vcpu)->rmode.vm86_active) {
2405                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2406                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2407         }
2408         vmcs_writel(GUEST_RFLAGS, rflags);
2409
2410         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2411                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2412 }
2413
2414 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2415 {
2416         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2417         int ret = 0;
2418
2419         if (interruptibility & GUEST_INTR_STATE_STI)
2420                 ret |= KVM_X86_SHADOW_INT_STI;
2421         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2422                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2423
2424         return ret;
2425 }
2426
2427 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2428 {
2429         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2430         u32 interruptibility = interruptibility_old;
2431
2432         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2433
2434         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2435                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2436         else if (mask & KVM_X86_SHADOW_INT_STI)
2437                 interruptibility |= GUEST_INTR_STATE_STI;
2438
2439         if ((interruptibility != interruptibility_old))
2440                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2441 }
2442
2443 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2444 {
2445         unsigned long rip;
2446
2447         rip = kvm_rip_read(vcpu);
2448         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2449         kvm_rip_write(vcpu, rip);
2450
2451         /* skipping an emulated instruction also counts */
2452         vmx_set_interrupt_shadow(vcpu, 0);
2453 }
2454
2455 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2456                                                unsigned long exit_qual)
2457 {
2458         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2459         unsigned int nr = vcpu->arch.exception.nr;
2460         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2461
2462         if (vcpu->arch.exception.has_error_code) {
2463                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2464                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2465         }
2466
2467         if (kvm_exception_is_soft(nr))
2468                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2469         else
2470                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2471
2472         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2473             vmx_get_nmi_mask(vcpu))
2474                 intr_info |= INTR_INFO_UNBLOCK_NMI;
2475
2476         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2477 }
2478
2479 /*
2480  * KVM wants to inject page-faults which it got to the guest. This function
2481  * checks whether in a nested guest, we need to inject them to L1 or L2.
2482  */
2483 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2484 {
2485         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2486         unsigned int nr = vcpu->arch.exception.nr;
2487
2488         if (nr == PF_VECTOR) {
2489                 if (vcpu->arch.exception.nested_apf) {
2490                         *exit_qual = vcpu->arch.apf.nested_apf_token;
2491                         return 1;
2492                 }
2493                 /*
2494                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2495                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
2496                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2497                  * can be written only when inject_pending_event runs.  This should be
2498                  * conditional on a new capability---if the capability is disabled,
2499                  * kvm_multiple_exception would write the ancillary information to
2500                  * CR2 or DR6, for backwards ABI-compatibility.
2501                  */
2502                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2503                                                     vcpu->arch.exception.error_code)) {
2504                         *exit_qual = vcpu->arch.cr2;
2505                         return 1;
2506                 }
2507         } else {
2508                 if (vmcs12->exception_bitmap & (1u << nr)) {
2509                         if (nr == DB_VECTOR)
2510                                 *exit_qual = vcpu->arch.dr6;
2511                         else
2512                                 *exit_qual = 0;
2513                         return 1;
2514                 }
2515         }
2516
2517         return 0;
2518 }
2519
2520 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2521 {
2522         struct vcpu_vmx *vmx = to_vmx(vcpu);
2523         unsigned nr = vcpu->arch.exception.nr;
2524         bool has_error_code = vcpu->arch.exception.has_error_code;
2525         u32 error_code = vcpu->arch.exception.error_code;
2526         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2527
2528         if (has_error_code) {
2529                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2530                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2531         }
2532
2533         if (vmx->rmode.vm86_active) {
2534                 int inc_eip = 0;
2535                 if (kvm_exception_is_soft(nr))
2536                         inc_eip = vcpu->arch.event_exit_inst_len;
2537                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2538                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2539                 return;
2540         }
2541
2542         if (kvm_exception_is_soft(nr)) {
2543                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2544                              vmx->vcpu.arch.event_exit_inst_len);
2545                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2546         } else
2547                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2548
2549         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2550 }
2551
2552 static bool vmx_rdtscp_supported(void)
2553 {
2554         return cpu_has_vmx_rdtscp();
2555 }
2556
2557 static bool vmx_invpcid_supported(void)
2558 {
2559         return cpu_has_vmx_invpcid() && enable_ept;
2560 }
2561
2562 /*
2563  * Swap MSR entry in host/guest MSR entry array.
2564  */
2565 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2566 {
2567         struct shared_msr_entry tmp;
2568
2569         tmp = vmx->guest_msrs[to];
2570         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2571         vmx->guest_msrs[from] = tmp;
2572 }
2573
2574 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2575 {
2576         unsigned long *msr_bitmap;
2577
2578         if (is_guest_mode(vcpu))
2579                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2580         else if (cpu_has_secondary_exec_ctrls() &&
2581                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2582                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2583                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2584                         if (is_long_mode(vcpu))
2585                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2586                         else
2587                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2588                 } else {
2589                         if (is_long_mode(vcpu))
2590                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2591                         else
2592                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2593                 }
2594         } else {
2595                 if (is_long_mode(vcpu))
2596                         msr_bitmap = vmx_msr_bitmap_longmode;
2597                 else
2598                         msr_bitmap = vmx_msr_bitmap_legacy;
2599         }
2600
2601         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2602 }
2603
2604 /*
2605  * Set up the vmcs to automatically save and restore system
2606  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2607  * mode, as fiddling with msrs is very expensive.
2608  */
2609 static void setup_msrs(struct vcpu_vmx *vmx)
2610 {
2611         int save_nmsrs, index;
2612
2613         save_nmsrs = 0;
2614 #ifdef CONFIG_X86_64
2615         if (is_long_mode(&vmx->vcpu)) {
2616                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2617                 if (index >= 0)
2618                         move_msr_up(vmx, index, save_nmsrs++);
2619                 index = __find_msr_index(vmx, MSR_LSTAR);
2620                 if (index >= 0)
2621                         move_msr_up(vmx, index, save_nmsrs++);
2622                 index = __find_msr_index(vmx, MSR_CSTAR);
2623                 if (index >= 0)
2624                         move_msr_up(vmx, index, save_nmsrs++);
2625                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2626                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2627                         move_msr_up(vmx, index, save_nmsrs++);
2628                 /*
2629                  * MSR_STAR is only needed on long mode guests, and only
2630                  * if efer.sce is enabled.
2631                  */
2632                 index = __find_msr_index(vmx, MSR_STAR);
2633                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2634                         move_msr_up(vmx, index, save_nmsrs++);
2635         }
2636 #endif
2637         index = __find_msr_index(vmx, MSR_EFER);
2638         if (index >= 0 && update_transition_efer(vmx, index))
2639                 move_msr_up(vmx, index, save_nmsrs++);
2640
2641         vmx->save_nmsrs = save_nmsrs;
2642
2643         if (cpu_has_vmx_msr_bitmap())
2644                 vmx_set_msr_bitmap(&vmx->vcpu);
2645 }
2646
2647 /*
2648  * reads and returns guest's timestamp counter "register"
2649  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2650  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2651  */
2652 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2653 {
2654         u64 host_tsc, tsc_offset;
2655
2656         host_tsc = rdtsc();
2657         tsc_offset = vmcs_read64(TSC_OFFSET);
2658         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2659 }
2660
2661 /*
2662  * writes 'offset' into guest's timestamp counter offset register
2663  */
2664 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2665 {
2666         if (is_guest_mode(vcpu)) {
2667                 /*
2668                  * We're here if L1 chose not to trap WRMSR to TSC. According
2669                  * to the spec, this should set L1's TSC; The offset that L1
2670                  * set for L2 remains unchanged, and still needs to be added
2671                  * to the newly set TSC to get L2's TSC.
2672                  */
2673                 struct vmcs12 *vmcs12;
2674                 /* recalculate vmcs02.TSC_OFFSET: */
2675                 vmcs12 = get_vmcs12(vcpu);
2676                 vmcs_write64(TSC_OFFSET, offset +
2677                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2678                          vmcs12->tsc_offset : 0));
2679         } else {
2680                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2681                                            vmcs_read64(TSC_OFFSET), offset);
2682                 vmcs_write64(TSC_OFFSET, offset);
2683         }
2684 }
2685
2686 /*
2687  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2688  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2689  * all guests if the "nested" module option is off, and can also be disabled
2690  * for a single guest by disabling its VMX cpuid bit.
2691  */
2692 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2693 {
2694         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2695 }
2696
2697 /*
2698  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2699  * returned for the various VMX controls MSRs when nested VMX is enabled.
2700  * The same values should also be used to verify that vmcs12 control fields are
2701  * valid during nested entry from L1 to L2.
2702  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2703  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2704  * bit in the high half is on if the corresponding bit in the control field
2705  * may be on. See also vmx_control_verify().
2706  */
2707 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2708 {
2709         /*
2710          * Note that as a general rule, the high half of the MSRs (bits in
2711          * the control fields which may be 1) should be initialized by the
2712          * intersection of the underlying hardware's MSR (i.e., features which
2713          * can be supported) and the list of features we want to expose -
2714          * because they are known to be properly supported in our code.
2715          * Also, usually, the low half of the MSRs (bits which must be 1) can
2716          * be set to 0, meaning that L1 may turn off any of these bits. The
2717          * reason is that if one of these bits is necessary, it will appear
2718          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2719          * fields of vmcs01 and vmcs02, will turn these bits off - and
2720          * nested_vmx_exit_reflected() will not pass related exits to L1.
2721          * These rules have exceptions below.
2722          */
2723
2724         /* pin-based controls */
2725         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2726                 vmx->nested.nested_vmx_pinbased_ctls_low,
2727                 vmx->nested.nested_vmx_pinbased_ctls_high);
2728         vmx->nested.nested_vmx_pinbased_ctls_low |=
2729                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2730         vmx->nested.nested_vmx_pinbased_ctls_high &=
2731                 PIN_BASED_EXT_INTR_MASK |
2732                 PIN_BASED_NMI_EXITING |
2733                 PIN_BASED_VIRTUAL_NMIS;
2734         vmx->nested.nested_vmx_pinbased_ctls_high |=
2735                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2736                 PIN_BASED_VMX_PREEMPTION_TIMER;
2737         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2738                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2739                         PIN_BASED_POSTED_INTR;
2740
2741         /* exit controls */
2742         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2743                 vmx->nested.nested_vmx_exit_ctls_low,
2744                 vmx->nested.nested_vmx_exit_ctls_high);
2745         vmx->nested.nested_vmx_exit_ctls_low =
2746                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2747
2748         vmx->nested.nested_vmx_exit_ctls_high &=
2749 #ifdef CONFIG_X86_64
2750                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2751 #endif
2752                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2753         vmx->nested.nested_vmx_exit_ctls_high |=
2754                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2755                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2756                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2757
2758         if (kvm_mpx_supported())
2759                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2760
2761         /* We support free control of debug control saving. */
2762         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2763
2764         /* entry controls */
2765         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2766                 vmx->nested.nested_vmx_entry_ctls_low,
2767                 vmx->nested.nested_vmx_entry_ctls_high);
2768         vmx->nested.nested_vmx_entry_ctls_low =
2769                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2770         vmx->nested.nested_vmx_entry_ctls_high &=
2771 #ifdef CONFIG_X86_64
2772                 VM_ENTRY_IA32E_MODE |
2773 #endif
2774                 VM_ENTRY_LOAD_IA32_PAT;
2775         vmx->nested.nested_vmx_entry_ctls_high |=
2776                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2777         if (kvm_mpx_supported())
2778                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2779
2780         /* We support free control of debug control loading. */
2781         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2782
2783         /* cpu-based controls */
2784         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2785                 vmx->nested.nested_vmx_procbased_ctls_low,
2786                 vmx->nested.nested_vmx_procbased_ctls_high);
2787         vmx->nested.nested_vmx_procbased_ctls_low =
2788                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2789         vmx->nested.nested_vmx_procbased_ctls_high &=
2790                 CPU_BASED_VIRTUAL_INTR_PENDING |
2791                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2792                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2793                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2794                 CPU_BASED_CR3_STORE_EXITING |
2795 #ifdef CONFIG_X86_64
2796                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2797 #endif
2798                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2799                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2800                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2801                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2802                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2803         /*
2804          * We can allow some features even when not supported by the
2805          * hardware. For example, L1 can specify an MSR bitmap - and we
2806          * can use it to avoid exits to L1 - even when L0 runs L2
2807          * without MSR bitmaps.
2808          */
2809         vmx->nested.nested_vmx_procbased_ctls_high |=
2810                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2811                 CPU_BASED_USE_MSR_BITMAPS;
2812
2813         /* We support free control of CR3 access interception. */
2814         vmx->nested.nested_vmx_procbased_ctls_low &=
2815                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2816
2817         /*
2818          * secondary cpu-based controls.  Do not include those that
2819          * depend on CPUID bits, they are added later by vmx_cpuid_update.
2820          */
2821         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2822                 vmx->nested.nested_vmx_secondary_ctls_low,
2823                 vmx->nested.nested_vmx_secondary_ctls_high);
2824         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2825         vmx->nested.nested_vmx_secondary_ctls_high &=
2826                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2827                 SECONDARY_EXEC_DESC |
2828                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2829                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2830                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2831                 SECONDARY_EXEC_WBINVD_EXITING;
2832
2833         if (enable_ept) {
2834                 /* nested EPT: emulate EPT also to L1 */
2835                 vmx->nested.nested_vmx_secondary_ctls_high |=
2836                         SECONDARY_EXEC_ENABLE_EPT;
2837                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2838                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2839                 if (cpu_has_vmx_ept_execute_only())
2840                         vmx->nested.nested_vmx_ept_caps |=
2841                                 VMX_EPT_EXECUTE_ONLY_BIT;
2842                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2843                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2844                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2845                         VMX_EPT_1GB_PAGE_BIT;
2846                 if (enable_ept_ad_bits) {
2847                         vmx->nested.nested_vmx_secondary_ctls_high |=
2848                                 SECONDARY_EXEC_ENABLE_PML;
2849                         vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2850                 }
2851         }
2852
2853         if (cpu_has_vmx_vmfunc()) {
2854                 vmx->nested.nested_vmx_secondary_ctls_high |=
2855                         SECONDARY_EXEC_ENABLE_VMFUNC;
2856                 /*
2857                  * Advertise EPTP switching unconditionally
2858                  * since we emulate it
2859                  */
2860                 if (enable_ept)
2861                         vmx->nested.nested_vmx_vmfunc_controls =
2862                                 VMX_VMFUNC_EPTP_SWITCHING;
2863         }
2864
2865         /*
2866          * Old versions of KVM use the single-context version without
2867          * checking for support, so declare that it is supported even
2868          * though it is treated as global context.  The alternative is
2869          * not failing the single-context invvpid, and it is worse.
2870          */
2871         if (enable_vpid) {
2872                 vmx->nested.nested_vmx_secondary_ctls_high |=
2873                         SECONDARY_EXEC_ENABLE_VPID;
2874                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2875                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2876         }
2877
2878         if (enable_unrestricted_guest)
2879                 vmx->nested.nested_vmx_secondary_ctls_high |=
2880                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2881
2882         /* miscellaneous data */
2883         rdmsr(MSR_IA32_VMX_MISC,
2884                 vmx->nested.nested_vmx_misc_low,
2885                 vmx->nested.nested_vmx_misc_high);
2886         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2887         vmx->nested.nested_vmx_misc_low |=
2888                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2889                 VMX_MISC_ACTIVITY_HLT;
2890         vmx->nested.nested_vmx_misc_high = 0;
2891
2892         /*
2893          * This MSR reports some information about VMX support. We
2894          * should return information about the VMX we emulate for the
2895          * guest, and the VMCS structure we give it - not about the
2896          * VMX support of the underlying hardware.
2897          */
2898         vmx->nested.nested_vmx_basic =
2899                 VMCS12_REVISION |
2900                 VMX_BASIC_TRUE_CTLS |
2901                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2902                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2903
2904         if (cpu_has_vmx_basic_inout())
2905                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2906
2907         /*
2908          * These MSRs specify bits which the guest must keep fixed on
2909          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2910          * We picked the standard core2 setting.
2911          */
2912 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2913 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2914         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2915         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2916
2917         /* These MSRs specify bits which the guest must keep fixed off. */
2918         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2919         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2920
2921         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2922         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2923 }
2924
2925 /*
2926  * if fixed0[i] == 1: val[i] must be 1
2927  * if fixed1[i] == 0: val[i] must be 0
2928  */
2929 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2930 {
2931         return ((val & fixed1) | fixed0) == val;
2932 }
2933
2934 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2935 {
2936         return fixed_bits_valid(control, low, high);
2937 }
2938
2939 static inline u64 vmx_control_msr(u32 low, u32 high)
2940 {
2941         return low | ((u64)high << 32);
2942 }
2943
2944 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2945 {
2946         superset &= mask;
2947         subset &= mask;
2948
2949         return (superset | subset) == superset;
2950 }
2951
2952 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2953 {
2954         const u64 feature_and_reserved =
2955                 /* feature (except bit 48; see below) */
2956                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2957                 /* reserved */
2958                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2959         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2960
2961         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2962                 return -EINVAL;
2963
2964         /*
2965          * KVM does not emulate a version of VMX that constrains physical
2966          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2967          */
2968         if (data & BIT_ULL(48))
2969                 return -EINVAL;
2970
2971         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2972             vmx_basic_vmcs_revision_id(data))
2973                 return -EINVAL;
2974
2975         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2976                 return -EINVAL;
2977
2978         vmx->nested.nested_vmx_basic = data;
2979         return 0;
2980 }
2981
2982 static int
2983 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2984 {
2985         u64 supported;
2986         u32 *lowp, *highp;
2987
2988         switch (msr_index) {
2989         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2990                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2991                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2992                 break;
2993         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2994                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2995                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2996                 break;
2997         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2998                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2999                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
3000                 break;
3001         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3002                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
3003                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
3004                 break;
3005         case MSR_IA32_VMX_PROCBASED_CTLS2:
3006                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
3007                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
3008                 break;
3009         default:
3010                 BUG();
3011         }
3012
3013         supported = vmx_control_msr(*lowp, *highp);
3014
3015         /* Check must-be-1 bits are still 1. */
3016         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3017                 return -EINVAL;
3018
3019         /* Check must-be-0 bits are still 0. */
3020         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3021                 return -EINVAL;
3022
3023         *lowp = data;
3024         *highp = data >> 32;
3025         return 0;
3026 }
3027
3028 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3029 {
3030         const u64 feature_and_reserved_bits =
3031                 /* feature */
3032                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3033                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3034                 /* reserved */
3035                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3036         u64 vmx_misc;
3037
3038         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3039                                    vmx->nested.nested_vmx_misc_high);
3040
3041         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3042                 return -EINVAL;
3043
3044         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3045              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3046             vmx_misc_preemption_timer_rate(data) !=
3047             vmx_misc_preemption_timer_rate(vmx_misc))
3048                 return -EINVAL;
3049
3050         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3051                 return -EINVAL;
3052
3053         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3054                 return -EINVAL;
3055
3056         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3057                 return -EINVAL;
3058
3059         vmx->nested.nested_vmx_misc_low = data;
3060         vmx->nested.nested_vmx_misc_high = data >> 32;
3061         return 0;
3062 }
3063
3064 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3065 {
3066         u64 vmx_ept_vpid_cap;
3067
3068         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3069                                            vmx->nested.nested_vmx_vpid_caps);
3070
3071         /* Every bit is either reserved or a feature bit. */
3072         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3073                 return -EINVAL;
3074
3075         vmx->nested.nested_vmx_ept_caps = data;
3076         vmx->nested.nested_vmx_vpid_caps = data >> 32;
3077         return 0;
3078 }
3079
3080 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3081 {
3082         u64 *msr;
3083
3084         switch (msr_index) {
3085         case MSR_IA32_VMX_CR0_FIXED0:
3086                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3087                 break;
3088         case MSR_IA32_VMX_CR4_FIXED0:
3089                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3090                 break;
3091         default:
3092                 BUG();
3093         }
3094
3095         /*
3096          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3097          * must be 1 in the restored value.
3098          */
3099         if (!is_bitwise_subset(data, *msr, -1ULL))
3100                 return -EINVAL;
3101
3102         *msr = data;
3103         return 0;
3104 }
3105
3106 /*
3107  * Called when userspace is restoring VMX MSRs.
3108  *
3109  * Returns 0 on success, non-0 otherwise.
3110  */
3111 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3112 {
3113         struct vcpu_vmx *vmx = to_vmx(vcpu);
3114
3115         switch (msr_index) {
3116         case MSR_IA32_VMX_BASIC:
3117                 return vmx_restore_vmx_basic(vmx, data);
3118         case MSR_IA32_VMX_PINBASED_CTLS:
3119         case MSR_IA32_VMX_PROCBASED_CTLS:
3120         case MSR_IA32_VMX_EXIT_CTLS:
3121         case MSR_IA32_VMX_ENTRY_CTLS:
3122                 /*
3123                  * The "non-true" VMX capability MSRs are generated from the
3124                  * "true" MSRs, so we do not support restoring them directly.
3125                  *
3126                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3127                  * should restore the "true" MSRs with the must-be-1 bits
3128                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3129                  * DEFAULT SETTINGS".
3130                  */
3131                 return -EINVAL;
3132         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3133         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3134         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3135         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3136         case MSR_IA32_VMX_PROCBASED_CTLS2:
3137                 return vmx_restore_control_msr(vmx, msr_index, data);
3138         case MSR_IA32_VMX_MISC:
3139                 return vmx_restore_vmx_misc(vmx, data);
3140         case MSR_IA32_VMX_CR0_FIXED0:
3141         case MSR_IA32_VMX_CR4_FIXED0:
3142                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3143         case MSR_IA32_VMX_CR0_FIXED1:
3144         case MSR_IA32_VMX_CR4_FIXED1:
3145                 /*
3146                  * These MSRs are generated based on the vCPU's CPUID, so we
3147                  * do not support restoring them directly.
3148                  */
3149                 return -EINVAL;
3150         case MSR_IA32_VMX_EPT_VPID_CAP:
3151                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3152         case MSR_IA32_VMX_VMCS_ENUM:
3153                 vmx->nested.nested_vmx_vmcs_enum = data;
3154                 return 0;
3155         default:
3156                 /*
3157                  * The rest of the VMX capability MSRs do not support restore.
3158                  */
3159                 return -EINVAL;
3160         }
3161 }
3162
3163 /* Returns 0 on success, non-0 otherwise. */
3164 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3165 {
3166         struct vcpu_vmx *vmx = to_vmx(vcpu);
3167
3168         switch (msr_index) {
3169         case MSR_IA32_VMX_BASIC:
3170                 *pdata = vmx->nested.nested_vmx_basic;
3171                 break;
3172         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3173         case MSR_IA32_VMX_PINBASED_CTLS:
3174                 *pdata = vmx_control_msr(
3175                         vmx->nested.nested_vmx_pinbased_ctls_low,
3176                         vmx->nested.nested_vmx_pinbased_ctls_high);
3177                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3178                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3179                 break;
3180         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3181         case MSR_IA32_VMX_PROCBASED_CTLS:
3182                 *pdata = vmx_control_msr(
3183                         vmx->nested.nested_vmx_procbased_ctls_low,
3184                         vmx->nested.nested_vmx_procbased_ctls_high);
3185                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3186                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3187                 break;
3188         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3189         case MSR_IA32_VMX_EXIT_CTLS:
3190                 *pdata = vmx_control_msr(
3191                         vmx->nested.nested_vmx_exit_ctls_low,
3192                         vmx->nested.nested_vmx_exit_ctls_high);
3193                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3194                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3195                 break;
3196         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3197         case MSR_IA32_VMX_ENTRY_CTLS:
3198                 *pdata = vmx_control_msr(
3199                         vmx->nested.nested_vmx_entry_ctls_low,
3200                         vmx->nested.nested_vmx_entry_ctls_high);
3201                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3202                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3203                 break;
3204         case MSR_IA32_VMX_MISC:
3205                 *pdata = vmx_control_msr(
3206                         vmx->nested.nested_vmx_misc_low,
3207                         vmx->nested.nested_vmx_misc_high);
3208                 break;
3209         case MSR_IA32_VMX_CR0_FIXED0:
3210                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3211                 break;
3212         case MSR_IA32_VMX_CR0_FIXED1:
3213                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3214                 break;
3215         case MSR_IA32_VMX_CR4_FIXED0:
3216                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3217                 break;
3218         case MSR_IA32_VMX_CR4_FIXED1:
3219                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3220                 break;
3221         case MSR_IA32_VMX_VMCS_ENUM:
3222                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3223                 break;
3224         case MSR_IA32_VMX_PROCBASED_CTLS2:
3225                 *pdata = vmx_control_msr(
3226                         vmx->nested.nested_vmx_secondary_ctls_low,
3227                         vmx->nested.nested_vmx_secondary_ctls_high);
3228                 break;
3229         case MSR_IA32_VMX_EPT_VPID_CAP:
3230                 *pdata = vmx->nested.nested_vmx_ept_caps |
3231                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3232                 break;
3233         case MSR_IA32_VMX_VMFUNC:
3234                 *pdata = vmx->nested.nested_vmx_vmfunc_controls;
3235                 break;
3236         default:
3237                 return 1;
3238         }
3239
3240         return 0;
3241 }
3242
3243 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3244                                                  uint64_t val)
3245 {
3246         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3247
3248         return !(val & ~valid_bits);
3249 }
3250
3251 /*
3252  * Reads an msr value (of 'msr_index') into 'pdata'.
3253  * Returns 0 on success, non-0 otherwise.
3254  * Assumes vcpu_load() was already called.
3255  */
3256 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3257 {
3258         struct shared_msr_entry *msr;
3259
3260         switch (msr_info->index) {
3261 #ifdef CONFIG_X86_64
3262         case MSR_FS_BASE:
3263                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3264                 break;
3265         case MSR_GS_BASE:
3266                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3267                 break;
3268         case MSR_KERNEL_GS_BASE:
3269                 vmx_load_host_state(to_vmx(vcpu));
3270                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3271                 break;
3272 #endif
3273         case MSR_EFER:
3274                 return kvm_get_msr_common(vcpu, msr_info);
3275         case MSR_IA32_TSC:
3276                 msr_info->data = guest_read_tsc(vcpu);
3277                 break;
3278         case MSR_IA32_SYSENTER_CS:
3279                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3280                 break;
3281         case MSR_IA32_SYSENTER_EIP:
3282                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3283                 break;
3284         case MSR_IA32_SYSENTER_ESP:
3285                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3286                 break;
3287         case MSR_IA32_BNDCFGS:
3288                 if (!kvm_mpx_supported() ||
3289                     (!msr_info->host_initiated &&
3290                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3291                         return 1;
3292                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3293                 break;
3294         case MSR_IA32_MCG_EXT_CTL:
3295                 if (!msr_info->host_initiated &&
3296                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3297                       FEATURE_CONTROL_LMCE))
3298                         return 1;
3299                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3300                 break;
3301         case MSR_IA32_FEATURE_CONTROL:
3302                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3303                 break;
3304         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3305                 if (!nested_vmx_allowed(vcpu))
3306                         return 1;
3307                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3308         case MSR_IA32_XSS:
3309                 if (!vmx_xsaves_supported())
3310                         return 1;
3311                 msr_info->data = vcpu->arch.ia32_xss;
3312                 break;
3313         case MSR_TSC_AUX:
3314                 if (!msr_info->host_initiated &&
3315                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3316                         return 1;
3317                 /* Otherwise falls through */
3318         default:
3319                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3320                 if (msr) {
3321                         msr_info->data = msr->data;
3322                         break;
3323                 }
3324                 return kvm_get_msr_common(vcpu, msr_info);
3325         }
3326
3327         return 0;
3328 }
3329
3330 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3331
3332 /*
3333  * Writes msr value into into the appropriate "register".
3334  * Returns 0 on success, non-0 otherwise.
3335  * Assumes vcpu_load() was already called.
3336  */
3337 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3338 {
3339         struct vcpu_vmx *vmx = to_vmx(vcpu);
3340         struct shared_msr_entry *msr;
3341         int ret = 0;
3342         u32 msr_index = msr_info->index;
3343         u64 data = msr_info->data;
3344
3345         switch (msr_index) {
3346         case MSR_EFER:
3347                 ret = kvm_set_msr_common(vcpu, msr_info);
3348                 break;
3349 #ifdef CONFIG_X86_64
3350         case MSR_FS_BASE:
3351                 vmx_segment_cache_clear(vmx);
3352                 vmcs_writel(GUEST_FS_BASE, data);
3353                 break;
3354         case MSR_GS_BASE:
3355                 vmx_segment_cache_clear(vmx);
3356                 vmcs_writel(GUEST_GS_BASE, data);
3357                 break;
3358         case MSR_KERNEL_GS_BASE:
3359                 vmx_load_host_state(vmx);
3360                 vmx->msr_guest_kernel_gs_base = data;
3361                 break;
3362 #endif
3363         case MSR_IA32_SYSENTER_CS:
3364                 vmcs_write32(GUEST_SYSENTER_CS, data);
3365                 break;
3366         case MSR_IA32_SYSENTER_EIP:
3367                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3368                 break;
3369         case MSR_IA32_SYSENTER_ESP:
3370                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3371                 break;
3372         case MSR_IA32_BNDCFGS:
3373                 if (!kvm_mpx_supported() ||
3374                     (!msr_info->host_initiated &&
3375                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3376                         return 1;
3377                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3378                     (data & MSR_IA32_BNDCFGS_RSVD))
3379                         return 1;
3380                 vmcs_write64(GUEST_BNDCFGS, data);
3381                 break;
3382         case MSR_IA32_TSC:
3383                 kvm_write_tsc(vcpu, msr_info);
3384                 break;
3385         case MSR_IA32_CR_PAT:
3386                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3387                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3388                                 return 1;
3389                         vmcs_write64(GUEST_IA32_PAT, data);
3390                         vcpu->arch.pat = data;
3391                         break;
3392                 }
3393                 ret = kvm_set_msr_common(vcpu, msr_info);
3394                 break;
3395         case MSR_IA32_TSC_ADJUST:
3396                 ret = kvm_set_msr_common(vcpu, msr_info);
3397                 break;
3398         case MSR_IA32_MCG_EXT_CTL:
3399                 if ((!msr_info->host_initiated &&
3400                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3401                        FEATURE_CONTROL_LMCE)) ||
3402                     (data & ~MCG_EXT_CTL_LMCE_EN))
3403                         return 1;
3404                 vcpu->arch.mcg_ext_ctl = data;
3405                 break;
3406         case MSR_IA32_FEATURE_CONTROL:
3407                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3408                     (to_vmx(vcpu)->msr_ia32_feature_control &
3409                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3410                         return 1;
3411                 vmx->msr_ia32_feature_control = data;
3412                 if (msr_info->host_initiated && data == 0)
3413                         vmx_leave_nested(vcpu);
3414                 break;
3415         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3416                 if (!msr_info->host_initiated)
3417                         return 1; /* they are read-only */
3418                 if (!nested_vmx_allowed(vcpu))
3419                         return 1;
3420                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3421         case MSR_IA32_XSS:
3422                 if (!vmx_xsaves_supported())
3423                         return 1;
3424                 /*
3425                  * The only supported bit as of Skylake is bit 8, but
3426                  * it is not supported on KVM.
3427                  */
3428                 if (data != 0)
3429                         return 1;
3430                 vcpu->arch.ia32_xss = data;
3431                 if (vcpu->arch.ia32_xss != host_xss)
3432                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3433                                 vcpu->arch.ia32_xss, host_xss);
3434                 else
3435                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3436                 break;
3437         case MSR_TSC_AUX:
3438                 if (!msr_info->host_initiated &&
3439                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3440                         return 1;
3441                 /* Check reserved bit, higher 32 bits should be zero */
3442                 if ((data >> 32) != 0)
3443                         return 1;
3444                 /* Otherwise falls through */
3445         default:
3446                 msr = find_msr_entry(vmx, msr_index);
3447                 if (msr) {
3448                         u64 old_msr_data = msr->data;
3449                         msr->data = data;
3450                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3451                                 preempt_disable();
3452                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3453                                                          msr->mask);
3454                                 preempt_enable();
3455                                 if (ret)
3456                                         msr->data = old_msr_data;
3457                         }
3458                         break;
3459                 }
3460                 ret = kvm_set_msr_common(vcpu, msr_info);
3461         }
3462
3463         return ret;
3464 }
3465
3466 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3467 {
3468         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3469         switch (reg) {
3470         case VCPU_REGS_RSP:
3471                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3472                 break;
3473         case VCPU_REGS_RIP:
3474                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3475                 break;
3476         case VCPU_EXREG_PDPTR:
3477                 if (enable_ept)
3478                         ept_save_pdptrs(vcpu);
3479                 break;
3480         default:
3481                 break;
3482         }
3483 }
3484
3485 static __init int cpu_has_kvm_support(void)
3486 {
3487         return cpu_has_vmx();
3488 }
3489
3490 static __init int vmx_disabled_by_bios(void)
3491 {
3492         u64 msr;
3493
3494         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3495         if (msr & FEATURE_CONTROL_LOCKED) {
3496                 /* launched w/ TXT and VMX disabled */
3497                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3498                         && tboot_enabled())
3499                         return 1;
3500                 /* launched w/o TXT and VMX only enabled w/ TXT */
3501                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3502                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3503                         && !tboot_enabled()) {
3504                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3505                                 "activate TXT before enabling KVM\n");
3506                         return 1;
3507                 }
3508                 /* launched w/o TXT and VMX disabled */
3509                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3510                         && !tboot_enabled())
3511                         return 1;
3512         }
3513
3514         return 0;
3515 }
3516
3517 static void kvm_cpu_vmxon(u64 addr)
3518 {
3519         cr4_set_bits(X86_CR4_VMXE);
3520         intel_pt_handle_vmx(1);
3521
3522         asm volatile (ASM_VMX_VMXON_RAX
3523                         : : "a"(&addr), "m"(addr)
3524                         : "memory", "cc");
3525 }
3526
3527 static int hardware_enable(void)
3528 {
3529         int cpu = raw_smp_processor_id();
3530         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3531         u64 old, test_bits;
3532
3533         if (cr4_read_shadow() & X86_CR4_VMXE)
3534                 return -EBUSY;
3535
3536         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3537         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3538         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3539
3540         /*
3541          * Now we can enable the vmclear operation in kdump
3542          * since the loaded_vmcss_on_cpu list on this cpu
3543          * has been initialized.
3544          *
3545          * Though the cpu is not in VMX operation now, there
3546          * is no problem to enable the vmclear operation
3547          * for the loaded_vmcss_on_cpu list is empty!
3548          */
3549         crash_enable_local_vmclear(cpu);
3550
3551         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3552
3553         test_bits = FEATURE_CONTROL_LOCKED;
3554         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3555         if (tboot_enabled())
3556                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3557
3558         if ((old & test_bits) != test_bits) {
3559                 /* enable and lock */
3560                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3561         }
3562         kvm_cpu_vmxon(phys_addr);
3563         if (enable_ept)
3564                 ept_sync_global();
3565
3566         return 0;
3567 }
3568
3569 static void vmclear_local_loaded_vmcss(void)
3570 {
3571         int cpu = raw_smp_processor_id();
3572         struct loaded_vmcs *v, *n;
3573
3574         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3575                                  loaded_vmcss_on_cpu_link)
3576                 __loaded_vmcs_clear(v);
3577 }
3578
3579
3580 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3581  * tricks.
3582  */
3583 static void kvm_cpu_vmxoff(void)
3584 {
3585         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3586
3587         intel_pt_handle_vmx(0);
3588         cr4_clear_bits(X86_CR4_VMXE);
3589 }
3590
3591 static void hardware_disable(void)
3592 {
3593         vmclear_local_loaded_vmcss();
3594         kvm_cpu_vmxoff();
3595 }
3596
3597 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3598                                       u32 msr, u32 *result)
3599 {
3600         u32 vmx_msr_low, vmx_msr_high;
3601         u32 ctl = ctl_min | ctl_opt;
3602
3603         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3604
3605         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3606         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3607
3608         /* Ensure minimum (required) set of control bits are supported. */
3609         if (ctl_min & ~ctl)
3610                 return -EIO;
3611
3612         *result = ctl;
3613         return 0;
3614 }
3615
3616 static __init bool allow_1_setting(u32 msr, u32 ctl)
3617 {
3618         u32 vmx_msr_low, vmx_msr_high;
3619
3620         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3621         return vmx_msr_high & ctl;
3622 }
3623
3624 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3625 {
3626         u32 vmx_msr_low, vmx_msr_high;
3627         u32 min, opt, min2, opt2;
3628         u32 _pin_based_exec_control = 0;
3629         u32 _cpu_based_exec_control = 0;
3630         u32 _cpu_based_2nd_exec_control = 0;
3631         u32 _vmexit_control = 0;
3632         u32 _vmentry_control = 0;
3633
3634         min = CPU_BASED_HLT_EXITING |
3635 #ifdef CONFIG_X86_64
3636               CPU_BASED_CR8_LOAD_EXITING |
3637               CPU_BASED_CR8_STORE_EXITING |
3638 #endif
3639               CPU_BASED_CR3_LOAD_EXITING |
3640               CPU_BASED_CR3_STORE_EXITING |
3641               CPU_BASED_USE_IO_BITMAPS |
3642               CPU_BASED_MOV_DR_EXITING |
3643               CPU_BASED_USE_TSC_OFFSETING |
3644               CPU_BASED_INVLPG_EXITING |
3645               CPU_BASED_RDPMC_EXITING;
3646
3647         if (!kvm_mwait_in_guest())
3648                 min |= CPU_BASED_MWAIT_EXITING |
3649                         CPU_BASED_MONITOR_EXITING;
3650
3651         opt = CPU_BASED_TPR_SHADOW |
3652               CPU_BASED_USE_MSR_BITMAPS |
3653               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3654         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3655                                 &_cpu_based_exec_control) < 0)
3656                 return -EIO;
3657 #ifdef CONFIG_X86_64
3658         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3659                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3660                                            ~CPU_BASED_CR8_STORE_EXITING;
3661 #endif
3662         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3663                 min2 = 0;
3664                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3665                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3666                         SECONDARY_EXEC_WBINVD_EXITING |
3667                         SECONDARY_EXEC_ENABLE_VPID |
3668                         SECONDARY_EXEC_ENABLE_EPT |
3669                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3670                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3671                         SECONDARY_EXEC_RDTSCP |
3672                         SECONDARY_EXEC_ENABLE_INVPCID |
3673                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3674                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3675                         SECONDARY_EXEC_SHADOW_VMCS |
3676                         SECONDARY_EXEC_XSAVES |
3677                         SECONDARY_EXEC_RDSEED_EXITING |
3678                         SECONDARY_EXEC_RDRAND_EXITING |
3679                         SECONDARY_EXEC_ENABLE_PML |
3680                         SECONDARY_EXEC_TSC_SCALING |
3681                         SECONDARY_EXEC_ENABLE_VMFUNC;
3682                 if (adjust_vmx_controls(min2, opt2,
3683                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3684                                         &_cpu_based_2nd_exec_control) < 0)
3685                         return -EIO;
3686         }
3687 #ifndef CONFIG_X86_64
3688         if (!(_cpu_based_2nd_exec_control &
3689                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3690                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3691 #endif
3692
3693         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3694                 _cpu_based_2nd_exec_control &= ~(
3695                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3696                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3697                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3698
3699         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
3700                 &vmx_capability.ept, &vmx_capability.vpid);
3701
3702         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3703                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3704                    enabled */
3705                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3706                                              CPU_BASED_CR3_STORE_EXITING |
3707                                              CPU_BASED_INVLPG_EXITING);
3708         } else if (vmx_capability.ept) {
3709                 vmx_capability.ept = 0;
3710                 pr_warn_once("EPT CAP should not exist if not support "
3711                                 "1-setting enable EPT VM-execution control\n");
3712         }
3713         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
3714                 vmx_capability.vpid) {
3715                 vmx_capability.vpid = 0;
3716                 pr_warn_once("VPID CAP should not exist if not support "
3717                                 "1-setting enable VPID VM-execution control\n");
3718         }
3719
3720         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3721 #ifdef CONFIG_X86_64
3722         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3723 #endif
3724         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3725                 VM_EXIT_CLEAR_BNDCFGS;
3726         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3727                                 &_vmexit_control) < 0)
3728                 return -EIO;
3729
3730         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3731         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3732                  PIN_BASED_VMX_PREEMPTION_TIMER;
3733         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3734                                 &_pin_based_exec_control) < 0)
3735                 return -EIO;
3736
3737         if (cpu_has_broken_vmx_preemption_timer())
3738                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3739         if (!(_cpu_based_2nd_exec_control &
3740                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3741                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3742
3743         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3744         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3745         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3746                                 &_vmentry_control) < 0)
3747                 return -EIO;
3748
3749         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3750
3751         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3752         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3753                 return -EIO;
3754
3755 #ifdef CONFIG_X86_64
3756         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3757         if (vmx_msr_high & (1u<<16))
3758                 return -EIO;
3759 #endif
3760
3761         /* Require Write-Back (WB) memory type for VMCS accesses. */
3762         if (((vmx_msr_high >> 18) & 15) != 6)
3763                 return -EIO;
3764
3765         vmcs_conf->size = vmx_msr_high & 0x1fff;
3766         vmcs_conf->order = get_order(vmcs_conf->size);
3767         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3768         vmcs_conf->revision_id = vmx_msr_low;
3769
3770         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3771         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3772         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3773         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3774         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3775
3776         cpu_has_load_ia32_efer =
3777                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3778                                 VM_ENTRY_LOAD_IA32_EFER)
3779                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3780                                    VM_EXIT_LOAD_IA32_EFER);
3781
3782         cpu_has_load_perf_global_ctrl =
3783                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3784                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3785                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3786                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3787
3788         /*
3789          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3790          * but due to errata below it can't be used. Workaround is to use
3791          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3792          *
3793          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3794          *
3795          * AAK155             (model 26)
3796          * AAP115             (model 30)
3797          * AAT100             (model 37)
3798          * BC86,AAY89,BD102   (model 44)
3799          * BA97               (model 46)
3800          *
3801          */
3802         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3803                 switch (boot_cpu_data.x86_model) {
3804                 case 26:
3805                 case 30:
3806                 case 37:
3807                 case 44:
3808                 case 46:
3809                         cpu_has_load_perf_global_ctrl = false;
3810                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3811                                         "does not work properly. Using workaround\n");
3812                         break;
3813                 default:
3814                         break;
3815                 }
3816         }
3817
3818         if (boot_cpu_has(X86_FEATURE_XSAVES))
3819                 rdmsrl(MSR_IA32_XSS, host_xss);
3820
3821         return 0;
3822 }
3823
3824 static struct vmcs *alloc_vmcs_cpu(int cpu)
3825 {
3826         int node = cpu_to_node(cpu);
3827         struct page *pages;
3828         struct vmcs *vmcs;
3829
3830         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3831         if (!pages)
3832                 return NULL;
3833         vmcs = page_address(pages);
3834         memset(vmcs, 0, vmcs_config.size);
3835         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3836         return vmcs;
3837 }
3838
3839 static struct vmcs *alloc_vmcs(void)
3840 {
3841         return alloc_vmcs_cpu(raw_smp_processor_id());
3842 }
3843
3844 static void free_vmcs(struct vmcs *vmcs)
3845 {
3846         free_pages((unsigned long)vmcs, vmcs_config.order);
3847 }
3848
3849 /*
3850  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3851  */
3852 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3853 {
3854         if (!loaded_vmcs->vmcs)
3855                 return;
3856         loaded_vmcs_clear(loaded_vmcs);
3857         free_vmcs(loaded_vmcs->vmcs);
3858         loaded_vmcs->vmcs = NULL;
3859         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3860 }
3861
3862 static void free_kvm_area(void)
3863 {
3864         int cpu;
3865
3866         for_each_possible_cpu(cpu) {
3867                 free_vmcs(per_cpu(vmxarea, cpu));
3868                 per_cpu(vmxarea, cpu) = NULL;
3869         }
3870 }
3871
3872 enum vmcs_field_type {
3873         VMCS_FIELD_TYPE_U16 = 0,
3874         VMCS_FIELD_TYPE_U64 = 1,
3875         VMCS_FIELD_TYPE_U32 = 2,
3876         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3877 };
3878
3879 static inline int vmcs_field_type(unsigned long field)
3880 {
3881         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
3882                 return VMCS_FIELD_TYPE_U32;
3883         return (field >> 13) & 0x3 ;
3884 }
3885
3886 static inline int vmcs_field_readonly(unsigned long field)
3887 {
3888         return (((field >> 10) & 0x3) == 1);
3889 }
3890
3891 static void init_vmcs_shadow_fields(void)
3892 {
3893         int i, j;
3894
3895         /* No checks for read only fields yet */
3896
3897         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3898                 switch (shadow_read_write_fields[i]) {
3899                 case GUEST_BNDCFGS:
3900                         if (!kvm_mpx_supported())
3901                                 continue;
3902                         break;
3903                 default:
3904                         break;
3905                 }
3906
3907                 if (j < i)
3908                         shadow_read_write_fields[j] =
3909                                 shadow_read_write_fields[i];
3910                 j++;
3911         }
3912         max_shadow_read_write_fields = j;
3913
3914         /* shadowed fields guest access without vmexit */
3915         for (i = 0; i < max_shadow_read_write_fields; i++) {
3916                 unsigned long field = shadow_read_write_fields[i];
3917
3918                 clear_bit(field, vmx_vmwrite_bitmap);
3919                 clear_bit(field, vmx_vmread_bitmap);
3920                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3921                         clear_bit(field + 1, vmx_vmwrite_bitmap);
3922                         clear_bit(field + 1, vmx_vmread_bitmap);
3923                 }
3924         }
3925         for (i = 0; i < max_shadow_read_only_fields; i++) {
3926                 unsigned long field = shadow_read_only_fields[i];
3927
3928                 clear_bit(field, vmx_vmread_bitmap);
3929                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3930                         clear_bit(field + 1, vmx_vmread_bitmap);
3931         }
3932 }
3933
3934 static __init int alloc_kvm_area(void)
3935 {
3936         int cpu;
3937
3938         for_each_possible_cpu(cpu) {
3939                 struct vmcs *vmcs;
3940
3941                 vmcs = alloc_vmcs_cpu(cpu);
3942                 if (!vmcs) {
3943                         free_kvm_area();
3944                         return -ENOMEM;
3945                 }
3946
3947                 per_cpu(vmxarea, cpu) = vmcs;
3948         }
3949         return 0;
3950 }
3951
3952 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3953                 struct kvm_segment *save)
3954 {
3955         if (!emulate_invalid_guest_state) {
3956                 /*
3957                  * CS and SS RPL should be equal during guest entry according
3958                  * to VMX spec, but in reality it is not always so. Since vcpu
3959                  * is in the middle of the transition from real mode to
3960                  * protected mode it is safe to assume that RPL 0 is a good
3961                  * default value.
3962                  */
3963                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3964                         save->selector &= ~SEGMENT_RPL_MASK;
3965                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3966                 save->s = 1;
3967         }
3968         vmx_set_segment(vcpu, save, seg);
3969 }
3970
3971 static void enter_pmode(struct kvm_vcpu *vcpu)
3972 {
3973         unsigned long flags;
3974         struct vcpu_vmx *vmx = to_vmx(vcpu);
3975
3976         /*
3977          * Update real mode segment cache. It may be not up-to-date if sement
3978          * register was written while vcpu was in a guest mode.
3979          */
3980         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3981         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3982         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3983         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3984         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3985         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3986
3987         vmx->rmode.vm86_active = 0;
3988
3989         vmx_segment_cache_clear(vmx);
3990
3991         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3992
3993         flags = vmcs_readl(GUEST_RFLAGS);
3994         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3995         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3996         vmcs_writel(GUEST_RFLAGS, flags);
3997
3998         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3999                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4000
4001         update_exception_bitmap(vcpu);
4002
4003         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4004         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4005         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4006         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4007         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4008         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4009 }
4010
4011 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4012 {
4013         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4014         struct kvm_segment var = *save;
4015
4016         var.dpl = 0x3;
4017         if (seg == VCPU_SREG_CS)
4018                 var.type = 0x3;
4019
4020         if (!emulate_invalid_guest_state) {
4021                 var.selector = var.base >> 4;
4022                 var.base = var.base & 0xffff0;
4023                 var.limit = 0xffff;
4024                 var.g = 0;
4025                 var.db = 0;
4026                 var.present = 1;
4027                 var.s = 1;
4028                 var.l = 0;
4029                 var.unusable = 0;
4030                 var.type = 0x3;
4031                 var.avl = 0;
4032                 if (save->base & 0xf)
4033                         printk_once(KERN_WARNING "kvm: segment base is not "
4034                                         "paragraph aligned when entering "
4035                                         "protected mode (seg=%d)", seg);
4036         }
4037
4038         vmcs_write16(sf->selector, var.selector);
4039         vmcs_writel(sf->base, var.base);
4040         vmcs_write32(sf->limit, var.limit);
4041         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4042 }
4043
4044 static void enter_rmode(struct kvm_vcpu *vcpu)
4045 {
4046         unsigned long flags;
4047         struct vcpu_vmx *vmx = to_vmx(vcpu);
4048
4049         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4050         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4051         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4052         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4053         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4054         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4055         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4056
4057         vmx->rmode.vm86_active = 1;
4058
4059         /*
4060          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4061          * vcpu. Warn the user that an update is overdue.
4062          */
4063         if (!vcpu->kvm->arch.tss_addr)
4064                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4065                              "called before entering vcpu\n");
4066
4067         vmx_segment_cache_clear(vmx);
4068
4069         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
4070         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4071         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4072
4073         flags = vmcs_readl(GUEST_RFLAGS);
4074         vmx->rmode.save_rflags = flags;
4075
4076         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4077
4078         vmcs_writel(GUEST_RFLAGS, flags);
4079         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4080         update_exception_bitmap(vcpu);
4081
4082         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4083         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4084         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4085         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4086         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4087         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4088
4089         kvm_mmu_reset_context(vcpu);
4090 }
4091
4092 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4093 {
4094         struct vcpu_vmx *vmx = to_vmx(vcpu);
4095         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4096
4097         if (!msr)
4098                 return;
4099
4100         /*
4101          * Force kernel_gs_base reloading before EFER changes, as control
4102          * of this msr depends on is_long_mode().
4103          */
4104         vmx_load_host_state(to_vmx(vcpu));
4105         vcpu->arch.efer = efer;
4106         if (efer & EFER_LMA) {
4107                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4108                 msr->data = efer;
4109         } else {
4110                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4111
4112                 msr->data = efer & ~EFER_LME;
4113         }
4114         setup_msrs(vmx);
4115 }
4116
4117 #ifdef CONFIG_X86_64
4118
4119 static void enter_lmode(struct kvm_vcpu *vcpu)
4120 {
4121         u32 guest_tr_ar;
4122
4123         vmx_segment_cache_clear(to_vmx(vcpu));
4124
4125         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4126         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4127                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4128                                      __func__);
4129                 vmcs_write32(GUEST_TR_AR_BYTES,
4130                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4131                              | VMX_AR_TYPE_BUSY_64_TSS);
4132         }
4133         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4134 }
4135
4136 static void exit_lmode(struct kvm_vcpu *vcpu)
4137 {
4138         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4139         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4140 }
4141
4142 #endif
4143
4144 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4145 {
4146         if (enable_ept) {
4147                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4148                         return;
4149                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4150         } else {
4151                 vpid_sync_context(vpid);
4152         }
4153 }
4154
4155 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4156 {
4157         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4158 }
4159
4160 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4161 {
4162         if (enable_ept)
4163                 vmx_flush_tlb(vcpu);
4164 }
4165
4166 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4167 {
4168         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4169
4170         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4171         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4172 }
4173
4174 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4175 {
4176         if (enable_ept && is_paging(vcpu))
4177                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4178         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4179 }
4180
4181 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4182 {
4183         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4184
4185         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4186         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4187 }
4188
4189 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4190 {
4191         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4192
4193         if (!test_bit(VCPU_EXREG_PDPTR,
4194                       (unsigned long *)&vcpu->arch.regs_dirty))
4195                 return;
4196
4197         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4198                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4199                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4200                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4201                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4202         }
4203 }
4204
4205 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4206 {
4207         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4208
4209         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4210                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4211                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4212                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4213                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4214         }
4215
4216         __set_bit(VCPU_EXREG_PDPTR,
4217                   (unsigned long *)&vcpu->arch.regs_avail);
4218         __set_bit(VCPU_EXREG_PDPTR,
4219                   (unsigned long *)&vcpu->arch.regs_dirty);
4220 }
4221
4222 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4223 {
4224         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4225         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4226         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4227
4228         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4229                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4230             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4231                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4232
4233         return fixed_bits_valid(val, fixed0, fixed1);
4234 }
4235
4236 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4237 {
4238         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4239         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4240
4241         return fixed_bits_valid(val, fixed0, fixed1);
4242 }
4243
4244 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4245 {
4246         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4247         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4248
4249         return fixed_bits_valid(val, fixed0, fixed1);
4250 }
4251
4252 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4253 #define nested_guest_cr4_valid  nested_cr4_valid
4254 #define nested_host_cr4_valid   nested_cr4_valid
4255
4256 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4257
4258 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4259                                         unsigned long cr0,
4260                                         struct kvm_vcpu *vcpu)
4261 {
4262         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4263                 vmx_decache_cr3(vcpu);
4264         if (!(cr0 & X86_CR0_PG)) {
4265                 /* From paging/starting to nonpaging */
4266                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4267                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4268                              (CPU_BASED_CR3_LOAD_EXITING |
4269                               CPU_BASED_CR3_STORE_EXITING));
4270                 vcpu->arch.cr0 = cr0;
4271                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4272         } else if (!is_paging(vcpu)) {
4273                 /* From nonpaging to paging */
4274                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4275                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4276                              ~(CPU_BASED_CR3_LOAD_EXITING |
4277                                CPU_BASED_CR3_STORE_EXITING));
4278                 vcpu->arch.cr0 = cr0;
4279                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4280         }
4281
4282         if (!(cr0 & X86_CR0_WP))
4283                 *hw_cr0 &= ~X86_CR0_WP;
4284 }
4285
4286 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4287 {
4288         struct vcpu_vmx *vmx = to_vmx(vcpu);
4289         unsigned long hw_cr0;
4290
4291         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4292         if (enable_unrestricted_guest)
4293                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4294         else {
4295                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4296
4297                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4298                         enter_pmode(vcpu);
4299
4300                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4301                         enter_rmode(vcpu);
4302         }
4303
4304 #ifdef CONFIG_X86_64
4305         if (vcpu->arch.efer & EFER_LME) {
4306                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4307                         enter_lmode(vcpu);
4308                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4309                         exit_lmode(vcpu);
4310         }
4311 #endif
4312
4313         if (enable_ept)
4314                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4315
4316         vmcs_writel(CR0_READ_SHADOW, cr0);
4317         vmcs_writel(GUEST_CR0, hw_cr0);
4318         vcpu->arch.cr0 = cr0;
4319
4320         /* depends on vcpu->arch.cr0 to be set to a new value */
4321         vmx->emulation_required = emulation_required(vcpu);
4322 }
4323
4324 static int get_ept_level(struct kvm_vcpu *vcpu)
4325 {
4326         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4327                 return 5;
4328         return 4;
4329 }
4330
4331 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4332 {
4333         u64 eptp = VMX_EPTP_MT_WB;
4334
4335         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4336
4337         if (enable_ept_ad_bits &&
4338             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4339                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4340         eptp |= (root_hpa & PAGE_MASK);
4341
4342         return eptp;
4343 }
4344
4345 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4346 {
4347         unsigned long guest_cr3;
4348         u64 eptp;
4349
4350         guest_cr3 = cr3;
4351         if (enable_ept) {
4352                 eptp = construct_eptp(vcpu, cr3);
4353                 vmcs_write64(EPT_POINTER, eptp);
4354                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4355                         guest_cr3 = kvm_read_cr3(vcpu);
4356                 else
4357                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4358                 ept_load_pdptrs(vcpu);
4359         }
4360
4361         vmx_flush_tlb(vcpu);
4362         vmcs_writel(GUEST_CR3, guest_cr3);
4363 }
4364
4365 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4366 {
4367         /*
4368          * Pass through host's Machine Check Enable value to hw_cr4, which
4369          * is in force while we are in guest mode.  Do not let guests control
4370          * this bit, even if host CR4.MCE == 0.
4371          */
4372         unsigned long hw_cr4 =
4373                 (cr4_read_shadow() & X86_CR4_MCE) |
4374                 (cr4 & ~X86_CR4_MCE) |
4375                 (to_vmx(vcpu)->rmode.vm86_active ?
4376                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4377
4378         if (cr4 & X86_CR4_VMXE) {
4379                 /*
4380                  * To use VMXON (and later other VMX instructions), a guest
4381                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4382                  * So basically the check on whether to allow nested VMX
4383                  * is here.
4384                  */
4385                 if (!nested_vmx_allowed(vcpu))
4386                         return 1;
4387         }
4388
4389         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4390                 return 1;
4391
4392         vcpu->arch.cr4 = cr4;
4393         if (enable_ept) {
4394                 if (!is_paging(vcpu)) {
4395                         hw_cr4 &= ~X86_CR4_PAE;
4396                         hw_cr4 |= X86_CR4_PSE;
4397                 } else if (!(cr4 & X86_CR4_PAE)) {
4398                         hw_cr4 &= ~X86_CR4_PAE;
4399                 }
4400         }
4401
4402         if (!enable_unrestricted_guest && !is_paging(vcpu))
4403                 /*
4404                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4405                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4406                  * to be manually disabled when guest switches to non-paging
4407                  * mode.
4408                  *
4409                  * If !enable_unrestricted_guest, the CPU is always running
4410                  * with CR0.PG=1 and CR4 needs to be modified.
4411                  * If enable_unrestricted_guest, the CPU automatically
4412                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4413                  */
4414                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4415
4416         vmcs_writel(CR4_READ_SHADOW, cr4);
4417         vmcs_writel(GUEST_CR4, hw_cr4);
4418         return 0;
4419 }
4420
4421 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4422                             struct kvm_segment *var, int seg)
4423 {
4424         struct vcpu_vmx *vmx = to_vmx(vcpu);
4425         u32 ar;
4426
4427         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4428                 *var = vmx->rmode.segs[seg];
4429                 if (seg == VCPU_SREG_TR
4430                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4431                         return;
4432                 var->base = vmx_read_guest_seg_base(vmx, seg);
4433                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4434                 return;
4435         }
4436         var->base = vmx_read_guest_seg_base(vmx, seg);
4437         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4438         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4439         ar = vmx_read_guest_seg_ar(vmx, seg);
4440         var->unusable = (ar >> 16) & 1;
4441         var->type = ar & 15;
4442         var->s = (ar >> 4) & 1;
4443         var->dpl = (ar >> 5) & 3;
4444         /*
4445          * Some userspaces do not preserve unusable property. Since usable
4446          * segment has to be present according to VMX spec we can use present
4447          * property to amend userspace bug by making unusable segment always
4448          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4449          * segment as unusable.
4450          */
4451         var->present = !var->unusable;
4452         var->avl = (ar >> 12) & 1;
4453         var->l = (ar >> 13) & 1;
4454         var->db = (ar >> 14) & 1;
4455         var->g = (ar >> 15) & 1;
4456 }
4457
4458 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4459 {
4460         struct kvm_segment s;
4461
4462         if (to_vmx(vcpu)->rmode.vm86_active) {
4463                 vmx_get_segment(vcpu, &s, seg);
4464                 return s.base;
4465         }
4466         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4467 }
4468
4469 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4470 {
4471         struct vcpu_vmx *vmx = to_vmx(vcpu);
4472
4473         if (unlikely(vmx->rmode.vm86_active))
4474                 return 0;
4475         else {
4476                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4477                 return VMX_AR_DPL(ar);
4478         }
4479 }
4480
4481 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4482 {
4483         u32 ar;
4484
4485         if (var->unusable || !var->present)
4486                 ar = 1 << 16;
4487         else {
4488                 ar = var->type & 15;
4489                 ar |= (var->s & 1) << 4;
4490                 ar |= (var->dpl & 3) << 5;
4491                 ar |= (var->present & 1) << 7;
4492                 ar |= (var->avl & 1) << 12;
4493                 ar |= (var->l & 1) << 13;
4494                 ar |= (var->db & 1) << 14;
4495                 ar |= (var->g & 1) << 15;
4496         }
4497
4498         return ar;
4499 }
4500
4501 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4502                             struct kvm_segment *var, int seg)
4503 {
4504         struct vcpu_vmx *vmx = to_vmx(vcpu);
4505         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4506
4507         vmx_segment_cache_clear(vmx);
4508
4509         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4510                 vmx->rmode.segs[seg] = *var;
4511                 if (seg == VCPU_SREG_TR)
4512                         vmcs_write16(sf->selector, var->selector);
4513                 else if (var->s)
4514                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4515                 goto out;
4516         }
4517
4518         vmcs_writel(sf->base, var->base);
4519         vmcs_write32(sf->limit, var->limit);
4520         vmcs_write16(sf->selector, var->selector);
4521
4522         /*
4523          *   Fix the "Accessed" bit in AR field of segment registers for older
4524          * qemu binaries.
4525          *   IA32 arch specifies that at the time of processor reset the
4526          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4527          * is setting it to 0 in the userland code. This causes invalid guest
4528          * state vmexit when "unrestricted guest" mode is turned on.
4529          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4530          * tree. Newer qemu binaries with that qemu fix would not need this
4531          * kvm hack.
4532          */
4533         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4534                 var->type |= 0x1; /* Accessed */
4535
4536         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4537
4538 out:
4539         vmx->emulation_required = emulation_required(vcpu);
4540 }
4541
4542 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4543 {
4544         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4545
4546         *db = (ar >> 14) & 1;
4547         *l = (ar >> 13) & 1;
4548 }
4549
4550 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4551 {
4552         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4553         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4554 }
4555
4556 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4557 {
4558         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4559         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4560 }
4561
4562 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4563 {
4564         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4565         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4566 }
4567
4568 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4569 {
4570         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4571         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4572 }
4573
4574 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4575 {
4576         struct kvm_segment var;
4577         u32 ar;
4578
4579         vmx_get_segment(vcpu, &var, seg);
4580         var.dpl = 0x3;
4581         if (seg == VCPU_SREG_CS)
4582                 var.type = 0x3;
4583         ar = vmx_segment_access_rights(&var);
4584
4585         if (var.base != (var.selector << 4))
4586                 return false;
4587         if (var.limit != 0xffff)
4588                 return false;
4589         if (ar != 0xf3)
4590                 return false;
4591
4592         return true;
4593 }
4594
4595 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4596 {
4597         struct kvm_segment cs;
4598         unsigned int cs_rpl;
4599
4600         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4601         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4602
4603         if (cs.unusable)
4604                 return false;
4605         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4606                 return false;
4607         if (!cs.s)
4608                 return false;
4609         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4610                 if (cs.dpl > cs_rpl)
4611                         return false;
4612         } else {
4613                 if (cs.dpl != cs_rpl)
4614                         return false;
4615         }
4616         if (!cs.present)
4617                 return false;
4618
4619         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4620         return true;
4621 }
4622
4623 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4624 {
4625         struct kvm_segment ss;
4626         unsigned int ss_rpl;
4627
4628         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4629         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4630
4631         if (ss.unusable)
4632                 return true;
4633         if (ss.type != 3 && ss.type != 7)
4634                 return false;
4635         if (!ss.s)
4636                 return false;
4637         if (ss.dpl != ss_rpl) /* DPL != RPL */
4638                 return false;
4639         if (!ss.present)
4640                 return false;
4641
4642         return true;
4643 }
4644
4645 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4646 {
4647         struct kvm_segment var;
4648         unsigned int rpl;
4649
4650         vmx_get_segment(vcpu, &var, seg);
4651         rpl = var.selector & SEGMENT_RPL_MASK;
4652
4653         if (var.unusable)
4654                 return true;
4655         if (!var.s)
4656                 return false;
4657         if (!var.present)
4658                 return false;
4659         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4660                 if (var.dpl < rpl) /* DPL < RPL */
4661                         return false;
4662         }
4663
4664         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4665          * rights flags
4666          */
4667         return true;
4668 }
4669
4670 static bool tr_valid(struct kvm_vcpu *vcpu)
4671 {
4672         struct kvm_segment tr;
4673
4674         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4675
4676         if (tr.unusable)
4677                 return false;
4678         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4679                 return false;
4680         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4681                 return false;
4682         if (!tr.present)
4683                 return false;
4684
4685         return true;
4686 }
4687
4688 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4689 {
4690         struct kvm_segment ldtr;
4691
4692         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4693
4694         if (ldtr.unusable)
4695                 return true;
4696         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4697                 return false;
4698         if (ldtr.type != 2)
4699                 return false;
4700         if (!ldtr.present)
4701                 return false;
4702
4703         return true;
4704 }
4705
4706 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4707 {
4708         struct kvm_segment cs, ss;
4709
4710         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4711         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4712
4713         return ((cs.selector & SEGMENT_RPL_MASK) ==
4714                  (ss.selector & SEGMENT_RPL_MASK));
4715 }
4716
4717 /*
4718  * Check if guest state is valid. Returns true if valid, false if
4719  * not.
4720  * We assume that registers are always usable
4721  */
4722 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4723 {
4724         if (enable_unrestricted_guest)
4725                 return true;
4726
4727         /* real mode guest state checks */
4728         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4729                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4730                         return false;
4731                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4732                         return false;
4733                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4734                         return false;
4735                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4736                         return false;
4737                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4738                         return false;
4739                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4740                         return false;
4741         } else {
4742         /* protected mode guest state checks */
4743                 if (!cs_ss_rpl_check(vcpu))
4744                         return false;
4745                 if (!code_segment_valid(vcpu))
4746                         return false;
4747                 if (!stack_segment_valid(vcpu))
4748                         return false;
4749                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4750                         return false;
4751                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4752                         return false;
4753                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4754                         return false;
4755                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4756                         return false;
4757                 if (!tr_valid(vcpu))
4758                         return false;
4759                 if (!ldtr_valid(vcpu))
4760                         return false;
4761         }
4762         /* TODO:
4763          * - Add checks on RIP
4764          * - Add checks on RFLAGS
4765          */
4766
4767         return true;
4768 }
4769
4770 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4771 {
4772         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4773 }
4774
4775 static int init_rmode_tss(struct kvm *kvm)
4776 {
4777         gfn_t fn;
4778         u16 data = 0;
4779         int idx, r;
4780
4781         idx = srcu_read_lock(&kvm->srcu);
4782         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4783         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4784         if (r < 0)
4785                 goto out;
4786         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4787         r = kvm_write_guest_page(kvm, fn++, &data,
4788                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4789         if (r < 0)
4790                 goto out;
4791         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4792         if (r < 0)
4793                 goto out;
4794         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4795         if (r < 0)
4796                 goto out;
4797         data = ~0;
4798         r = kvm_write_guest_page(kvm, fn, &data,
4799                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4800                                  sizeof(u8));
4801 out:
4802         srcu_read_unlock(&kvm->srcu, idx);
4803         return r;
4804 }
4805
4806 static int init_rmode_identity_map(struct kvm *kvm)
4807 {
4808         int i, idx, r = 0;
4809         kvm_pfn_t identity_map_pfn;
4810         u32 tmp;
4811
4812         /* Protect kvm->arch.ept_identity_pagetable_done. */
4813         mutex_lock(&kvm->slots_lock);
4814
4815         if (likely(kvm->arch.ept_identity_pagetable_done))
4816                 goto out2;
4817
4818         if (!kvm->arch.ept_identity_map_addr)
4819                 kvm->arch.ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4820         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4821
4822         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4823                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4824         if (r < 0)
4825                 goto out2;
4826
4827         idx = srcu_read_lock(&kvm->srcu);
4828         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4829         if (r < 0)
4830                 goto out;
4831         /* Set up identity-mapping pagetable for EPT in real mode */
4832         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4833                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4834                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4835                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4836                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4837                 if (r < 0)
4838                         goto out;
4839         }
4840         kvm->arch.ept_identity_pagetable_done = true;
4841
4842 out:
4843         srcu_read_unlock(&kvm->srcu, idx);
4844
4845 out2:
4846         mutex_unlock(&kvm->slots_lock);
4847         return r;
4848 }
4849
4850 static void seg_setup(int seg)
4851 {
4852         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4853         unsigned int ar;
4854
4855         vmcs_write16(sf->selector, 0);
4856         vmcs_writel(sf->base, 0);
4857         vmcs_write32(sf->limit, 0xffff);
4858         ar = 0x93;
4859         if (seg == VCPU_SREG_CS)
4860                 ar |= 0x08; /* code segment */
4861
4862         vmcs_write32(sf->ar_bytes, ar);
4863 }
4864
4865 static int alloc_apic_access_page(struct kvm *kvm)
4866 {
4867         struct page *page;
4868         int r = 0;
4869
4870         mutex_lock(&kvm->slots_lock);
4871         if (kvm->arch.apic_access_page_done)
4872                 goto out;
4873         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4874                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4875         if (r)
4876                 goto out;
4877
4878         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4879         if (is_error_page(page)) {
4880                 r = -EFAULT;
4881                 goto out;
4882         }
4883
4884         /*
4885          * Do not pin the page in memory, so that memory hot-unplug
4886          * is able to migrate it.
4887          */
4888         put_page(page);
4889         kvm->arch.apic_access_page_done = true;
4890 out:
4891         mutex_unlock(&kvm->slots_lock);
4892         return r;
4893 }
4894
4895 static int allocate_vpid(void)
4896 {
4897         int vpid;
4898
4899         if (!enable_vpid)
4900                 return 0;
4901         spin_lock(&vmx_vpid_lock);
4902         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4903         if (vpid < VMX_NR_VPIDS)
4904                 __set_bit(vpid, vmx_vpid_bitmap);
4905         else
4906                 vpid = 0;
4907         spin_unlock(&vmx_vpid_lock);
4908         return vpid;
4909 }
4910
4911 static void free_vpid(int vpid)
4912 {
4913         if (!enable_vpid || vpid == 0)
4914                 return;
4915         spin_lock(&vmx_vpid_lock);
4916         __clear_bit(vpid, vmx_vpid_bitmap);
4917         spin_unlock(&vmx_vpid_lock);
4918 }
4919
4920 #define MSR_TYPE_R      1
4921 #define MSR_TYPE_W      2
4922 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4923                                                 u32 msr, int type)
4924 {
4925         int f = sizeof(unsigned long);
4926
4927         if (!cpu_has_vmx_msr_bitmap())
4928                 return;
4929
4930         /*
4931          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4932          * have the write-low and read-high bitmap offsets the wrong way round.
4933          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4934          */
4935         if (msr <= 0x1fff) {
4936                 if (type & MSR_TYPE_R)
4937                         /* read-low */
4938                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4939
4940                 if (type & MSR_TYPE_W)
4941                         /* write-low */
4942                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4943
4944         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4945                 msr &= 0x1fff;
4946                 if (type & MSR_TYPE_R)
4947                         /* read-high */
4948                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4949
4950                 if (type & MSR_TYPE_W)
4951                         /* write-high */
4952                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4953
4954         }
4955 }
4956
4957 /*
4958  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4959  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4960  */
4961 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4962                                                unsigned long *msr_bitmap_nested,
4963                                                u32 msr, int type)
4964 {
4965         int f = sizeof(unsigned long);
4966
4967         if (!cpu_has_vmx_msr_bitmap()) {
4968                 WARN_ON(1);
4969                 return;
4970         }
4971
4972         /*
4973          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4974          * have the write-low and read-high bitmap offsets the wrong way round.
4975          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4976          */
4977         if (msr <= 0x1fff) {
4978                 if (type & MSR_TYPE_R &&
4979                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4980                         /* read-low */
4981                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4982
4983                 if (type & MSR_TYPE_W &&
4984                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4985                         /* write-low */
4986                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4987
4988         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4989                 msr &= 0x1fff;
4990                 if (type & MSR_TYPE_R &&
4991                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4992                         /* read-high */
4993                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4994
4995                 if (type & MSR_TYPE_W &&
4996                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4997                         /* write-high */
4998                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4999
5000         }
5001 }
5002
5003 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
5004 {
5005         if (!longmode_only)
5006                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
5007                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
5008         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
5009                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
5010 }
5011
5012 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
5013 {
5014         if (apicv_active) {
5015                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
5016                                 msr, type);
5017                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
5018                                 msr, type);
5019         } else {
5020                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
5021                                 msr, type);
5022                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
5023                                 msr, type);
5024         }
5025 }
5026
5027 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5028 {
5029         return enable_apicv;
5030 }
5031
5032 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5033 {
5034         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5035         gfn_t gfn;
5036
5037         /*
5038          * Don't need to mark the APIC access page dirty; it is never
5039          * written to by the CPU during APIC virtualization.
5040          */
5041
5042         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5043                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5044                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5045         }
5046
5047         if (nested_cpu_has_posted_intr(vmcs12)) {
5048                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5049                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5050         }
5051 }
5052
5053
5054 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5055 {
5056         struct vcpu_vmx *vmx = to_vmx(vcpu);
5057         int max_irr;
5058         void *vapic_page;
5059         u16 status;
5060
5061         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5062                 return;
5063
5064         vmx->nested.pi_pending = false;
5065         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5066                 return;
5067
5068         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5069         if (max_irr != 256) {
5070                 vapic_page = kmap(vmx->nested.virtual_apic_page);
5071                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
5072                 kunmap(vmx->nested.virtual_apic_page);
5073
5074                 status = vmcs_read16(GUEST_INTR_STATUS);
5075                 if ((u8)max_irr > ((u8)status & 0xff)) {
5076                         status &= ~0xff;
5077                         status |= (u8)max_irr;
5078                         vmcs_write16(GUEST_INTR_STATUS, status);
5079                 }
5080         }
5081
5082         nested_mark_vmcs12_pages_dirty(vcpu);
5083 }
5084
5085 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5086                                                      bool nested)
5087 {
5088 #ifdef CONFIG_SMP
5089         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5090
5091         if (vcpu->mode == IN_GUEST_MODE) {
5092                 /*
5093                  * The vector of interrupt to be delivered to vcpu had
5094                  * been set in PIR before this function.
5095                  *
5096                  * Following cases will be reached in this block, and
5097                  * we always send a notification event in all cases as
5098                  * explained below.
5099                  *
5100                  * Case 1: vcpu keeps in non-root mode. Sending a
5101                  * notification event posts the interrupt to vcpu.
5102                  *
5103                  * Case 2: vcpu exits to root mode and is still
5104                  * runnable. PIR will be synced to vIRR before the
5105                  * next vcpu entry. Sending a notification event in
5106                  * this case has no effect, as vcpu is not in root
5107                  * mode.
5108                  *
5109                  * Case 3: vcpu exits to root mode and is blocked.
5110                  * vcpu_block() has already synced PIR to vIRR and
5111                  * never blocks vcpu if vIRR is not cleared. Therefore,
5112                  * a blocked vcpu here does not wait for any requested
5113                  * interrupts in PIR, and sending a notification event
5114                  * which has no effect is safe here.
5115                  */
5116
5117                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5118                 return true;
5119         }
5120 #endif
5121         return false;
5122 }
5123
5124 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5125                                                 int vector)
5126 {
5127         struct vcpu_vmx *vmx = to_vmx(vcpu);
5128
5129         if (is_guest_mode(vcpu) &&
5130             vector == vmx->nested.posted_intr_nv) {
5131                 /* the PIR and ON have been set by L1. */
5132                 kvm_vcpu_trigger_posted_interrupt(vcpu, true);
5133                 /*
5134                  * If a posted intr is not recognized by hardware,
5135                  * we will accomplish it in the next vmentry.
5136                  */
5137                 vmx->nested.pi_pending = true;
5138                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5139                 return 0;
5140         }
5141         return -1;
5142 }
5143 /*
5144  * Send interrupt to vcpu via posted interrupt way.
5145  * 1. If target vcpu is running(non-root mode), send posted interrupt
5146  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5147  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5148  * interrupt from PIR in next vmentry.
5149  */
5150 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5151 {
5152         struct vcpu_vmx *vmx = to_vmx(vcpu);
5153         int r;
5154
5155         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5156         if (!r)
5157                 return;
5158
5159         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5160                 return;
5161
5162         /* If a previous notification has sent the IPI, nothing to do.  */
5163         if (pi_test_and_set_on(&vmx->pi_desc))
5164                 return;
5165
5166         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5167                 kvm_vcpu_kick(vcpu);
5168 }
5169
5170 /*
5171  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5172  * will not change in the lifetime of the guest.
5173  * Note that host-state that does change is set elsewhere. E.g., host-state
5174  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5175  */
5176 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5177 {
5178         u32 low32, high32;
5179         unsigned long tmpl;
5180         struct desc_ptr dt;
5181         unsigned long cr0, cr3, cr4;
5182
5183         cr0 = read_cr0();
5184         WARN_ON(cr0 & X86_CR0_TS);
5185         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5186
5187         /*
5188          * Save the most likely value for this task's CR3 in the VMCS.
5189          * We can't use __get_current_cr3_fast() because we're not atomic.
5190          */
5191         cr3 = __read_cr3();
5192         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5193         vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5194
5195         /* Save the most likely value for this task's CR4 in the VMCS. */
5196         cr4 = cr4_read_shadow();
5197         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5198         vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5199
5200         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5201 #ifdef CONFIG_X86_64
5202         /*
5203          * Load null selectors, so we can avoid reloading them in
5204          * __vmx_load_host_state(), in case userspace uses the null selectors
5205          * too (the expected case).
5206          */
5207         vmcs_write16(HOST_DS_SELECTOR, 0);
5208         vmcs_write16(HOST_ES_SELECTOR, 0);
5209 #else
5210         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5211         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5212 #endif
5213         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5214         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5215
5216         store_idt(&dt);
5217         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5218         vmx->host_idt_base = dt.address;
5219
5220         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5221
5222         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5223         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5224         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5225         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5226
5227         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5228                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5229                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5230         }
5231 }
5232
5233 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5234 {
5235         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5236         if (enable_ept)
5237                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5238         if (is_guest_mode(&vmx->vcpu))
5239                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5240                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5241         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5242 }
5243
5244 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5245 {
5246         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5247
5248         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5249                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5250
5251         if (!enable_vnmi)
5252                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
5253
5254         /* Enable the preemption timer dynamically */
5255         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5256         return pin_based_exec_ctrl;
5257 }
5258
5259 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5260 {
5261         struct vcpu_vmx *vmx = to_vmx(vcpu);
5262
5263         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5264         if (cpu_has_secondary_exec_ctrls()) {
5265                 if (kvm_vcpu_apicv_active(vcpu))
5266                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5267                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5268                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5269                 else
5270                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5271                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5272                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5273         }
5274
5275         if (cpu_has_vmx_msr_bitmap())
5276                 vmx_set_msr_bitmap(vcpu);
5277 }
5278
5279 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5280 {
5281         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5282
5283         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5284                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5285
5286         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5287                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5288 #ifdef CONFIG_X86_64
5289                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5290                                 CPU_BASED_CR8_LOAD_EXITING;
5291 #endif
5292         }
5293         if (!enable_ept)
5294                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5295                                 CPU_BASED_CR3_LOAD_EXITING  |
5296                                 CPU_BASED_INVLPG_EXITING;
5297         return exec_control;
5298 }
5299
5300 static bool vmx_rdrand_supported(void)
5301 {
5302         return vmcs_config.cpu_based_2nd_exec_ctrl &
5303                 SECONDARY_EXEC_RDRAND_EXITING;
5304 }
5305
5306 static bool vmx_rdseed_supported(void)
5307 {
5308         return vmcs_config.cpu_based_2nd_exec_ctrl &
5309                 SECONDARY_EXEC_RDSEED_EXITING;
5310 }
5311
5312 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
5313 {
5314         struct kvm_vcpu *vcpu = &vmx->vcpu;
5315
5316         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5317         if (!cpu_need_virtualize_apic_accesses(vcpu))
5318                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5319         if (vmx->vpid == 0)
5320                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5321         if (!enable_ept) {
5322                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5323                 enable_unrestricted_guest = 0;
5324                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5325                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5326         }
5327         if (!enable_unrestricted_guest)
5328                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5329         if (!ple_gap)
5330                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5331         if (!kvm_vcpu_apicv_active(vcpu))
5332                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5333                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5334         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5335         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5336            (handle_vmptrld).
5337            We can NOT enable shadow_vmcs here because we don't have yet
5338            a current VMCS12
5339         */
5340         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5341
5342         if (!enable_pml)
5343                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5344
5345         if (vmx_xsaves_supported()) {
5346                 /* Exposing XSAVES only when XSAVE is exposed */
5347                 bool xsaves_enabled =
5348                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
5349                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
5350
5351                 if (!xsaves_enabled)
5352                         exec_control &= ~SECONDARY_EXEC_XSAVES;
5353
5354                 if (nested) {
5355                         if (xsaves_enabled)
5356                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5357                                         SECONDARY_EXEC_XSAVES;
5358                         else
5359                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5360                                         ~SECONDARY_EXEC_XSAVES;
5361                 }
5362         }
5363
5364         if (vmx_rdtscp_supported()) {
5365                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
5366                 if (!rdtscp_enabled)
5367                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
5368
5369                 if (nested) {
5370                         if (rdtscp_enabled)
5371                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5372                                         SECONDARY_EXEC_RDTSCP;
5373                         else
5374                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5375                                         ~SECONDARY_EXEC_RDTSCP;
5376                 }
5377         }
5378
5379         if (vmx_invpcid_supported()) {
5380                 /* Exposing INVPCID only when PCID is exposed */
5381                 bool invpcid_enabled =
5382                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
5383                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
5384
5385                 if (!invpcid_enabled) {
5386                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5387                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
5388                 }
5389
5390                 if (nested) {
5391                         if (invpcid_enabled)
5392                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5393                                         SECONDARY_EXEC_ENABLE_INVPCID;
5394                         else
5395                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5396                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
5397                 }
5398         }
5399
5400         if (vmx_rdrand_supported()) {
5401                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
5402                 if (rdrand_enabled)
5403                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
5404
5405                 if (nested) {
5406                         if (rdrand_enabled)
5407                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5408                                         SECONDARY_EXEC_RDRAND_EXITING;
5409                         else
5410                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5411                                         ~SECONDARY_EXEC_RDRAND_EXITING;
5412                 }
5413         }
5414
5415         if (vmx_rdseed_supported()) {
5416                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
5417                 if (rdseed_enabled)
5418                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
5419
5420                 if (nested) {
5421                         if (rdseed_enabled)
5422                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5423                                         SECONDARY_EXEC_RDSEED_EXITING;
5424                         else
5425                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5426                                         ~SECONDARY_EXEC_RDSEED_EXITING;
5427                 }
5428         }
5429
5430         vmx->secondary_exec_control = exec_control;
5431 }
5432
5433 static void ept_set_mmio_spte_mask(void)
5434 {
5435         /*
5436          * EPT Misconfigurations can be generated if the value of bits 2:0
5437          * of an EPT paging-structure entry is 110b (write/execute).
5438          */
5439         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5440                                    VMX_EPT_MISCONFIG_WX_VALUE);
5441 }
5442
5443 #define VMX_XSS_EXIT_BITMAP 0
5444 /*
5445  * Sets up the vmcs for emulated real mode.
5446  */
5447 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
5448 {
5449 #ifdef CONFIG_X86_64
5450         unsigned long a;
5451 #endif
5452         int i;
5453
5454         /* I/O */
5455         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5456         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5457
5458         if (enable_shadow_vmcs) {
5459                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5460                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5461         }
5462         if (cpu_has_vmx_msr_bitmap())
5463                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5464
5465         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5466
5467         /* Control */
5468         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5469         vmx->hv_deadline_tsc = -1;
5470
5471         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5472
5473         if (cpu_has_secondary_exec_ctrls()) {
5474                 vmx_compute_secondary_exec_control(vmx);
5475                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5476                              vmx->secondary_exec_control);
5477         }
5478
5479         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5480                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5481                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5482                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5483                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5484
5485                 vmcs_write16(GUEST_INTR_STATUS, 0);
5486
5487                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5488                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5489         }
5490
5491         if (ple_gap) {
5492                 vmcs_write32(PLE_GAP, ple_gap);
5493                 vmx->ple_window = ple_window;
5494                 vmx->ple_window_dirty = true;
5495         }
5496
5497         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5498         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5499         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5500
5501         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5502         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5503         vmx_set_constant_host_state(vmx);
5504 #ifdef CONFIG_X86_64
5505         rdmsrl(MSR_FS_BASE, a);
5506         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5507         rdmsrl(MSR_GS_BASE, a);
5508         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5509 #else
5510         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5511         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5512 #endif
5513
5514         if (cpu_has_vmx_vmfunc())
5515                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
5516
5517         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5518         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5519         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5520         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5521         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5522
5523         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5524                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5525
5526         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5527                 u32 index = vmx_msr_index[i];
5528                 u32 data_low, data_high;
5529                 int j = vmx->nmsrs;
5530
5531                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5532                         continue;
5533                 if (wrmsr_safe(index, data_low, data_high) < 0)
5534                         continue;
5535                 vmx->guest_msrs[j].index = i;
5536                 vmx->guest_msrs[j].data = 0;
5537                 vmx->guest_msrs[j].mask = -1ull;
5538                 ++vmx->nmsrs;
5539         }
5540
5541
5542         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5543
5544         /* 22.2.1, 20.8.1 */
5545         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5546
5547         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5548         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5549
5550         set_cr4_guest_host_mask(vmx);
5551
5552         if (vmx_xsaves_supported())
5553                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5554
5555         if (enable_pml) {
5556                 ASSERT(vmx->pml_pg);
5557                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5558                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5559         }
5560 }
5561
5562 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5563 {
5564         struct vcpu_vmx *vmx = to_vmx(vcpu);
5565         struct msr_data apic_base_msr;
5566         u64 cr0;
5567
5568         vmx->rmode.vm86_active = 0;
5569
5570         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5571         kvm_set_cr8(vcpu, 0);
5572
5573         if (!init_event) {
5574                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5575                                      MSR_IA32_APICBASE_ENABLE;
5576                 if (kvm_vcpu_is_reset_bsp(vcpu))
5577                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5578                 apic_base_msr.host_initiated = true;
5579                 kvm_set_apic_base(vcpu, &apic_base_msr);
5580         }
5581
5582         vmx_segment_cache_clear(vmx);
5583
5584         seg_setup(VCPU_SREG_CS);
5585         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5586         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5587
5588         seg_setup(VCPU_SREG_DS);
5589         seg_setup(VCPU_SREG_ES);
5590         seg_setup(VCPU_SREG_FS);
5591         seg_setup(VCPU_SREG_GS);
5592         seg_setup(VCPU_SREG_SS);
5593
5594         vmcs_write16(GUEST_TR_SELECTOR, 0);
5595         vmcs_writel(GUEST_TR_BASE, 0);
5596         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5597         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5598
5599         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5600         vmcs_writel(GUEST_LDTR_BASE, 0);
5601         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5602         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5603
5604         if (!init_event) {
5605                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5606                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5607                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5608                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5609         }
5610
5611         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
5612         kvm_rip_write(vcpu, 0xfff0);
5613
5614         vmcs_writel(GUEST_GDTR_BASE, 0);
5615         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5616
5617         vmcs_writel(GUEST_IDTR_BASE, 0);
5618         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5619
5620         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5621         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5622         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5623         if (kvm_mpx_supported())
5624                 vmcs_write64(GUEST_BNDCFGS, 0);
5625
5626         setup_msrs(vmx);
5627
5628         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5629
5630         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5631                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5632                 if (cpu_need_tpr_shadow(vcpu))
5633                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5634                                      __pa(vcpu->arch.apic->regs));
5635                 vmcs_write32(TPR_THRESHOLD, 0);
5636         }
5637
5638         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5639
5640         if (vmx->vpid != 0)
5641                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5642
5643         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5644         vmx->vcpu.arch.cr0 = cr0;
5645         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5646         vmx_set_cr4(vcpu, 0);
5647         vmx_set_efer(vcpu, 0);
5648
5649         update_exception_bitmap(vcpu);
5650
5651         vpid_sync_context(vmx->vpid);
5652 }
5653
5654 /*
5655  * In nested virtualization, check if L1 asked to exit on external interrupts.
5656  * For most existing hypervisors, this will always return true.
5657  */
5658 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5659 {
5660         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5661                 PIN_BASED_EXT_INTR_MASK;
5662 }
5663
5664 /*
5665  * In nested virtualization, check if L1 has set
5666  * VM_EXIT_ACK_INTR_ON_EXIT
5667  */
5668 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5669 {
5670         return get_vmcs12(vcpu)->vm_exit_controls &
5671                 VM_EXIT_ACK_INTR_ON_EXIT;
5672 }
5673
5674 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5675 {
5676         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5677                 PIN_BASED_NMI_EXITING;
5678 }
5679
5680 static void enable_irq_window(struct kvm_vcpu *vcpu)
5681 {
5682         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5683                       CPU_BASED_VIRTUAL_INTR_PENDING);
5684 }
5685
5686 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5687 {
5688         if (!enable_vnmi ||
5689             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5690                 enable_irq_window(vcpu);
5691                 return;
5692         }
5693
5694         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5695                       CPU_BASED_VIRTUAL_NMI_PENDING);
5696 }
5697
5698 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5699 {
5700         struct vcpu_vmx *vmx = to_vmx(vcpu);
5701         uint32_t intr;
5702         int irq = vcpu->arch.interrupt.nr;
5703
5704         trace_kvm_inj_virq(irq);
5705
5706         ++vcpu->stat.irq_injections;
5707         if (vmx->rmode.vm86_active) {
5708                 int inc_eip = 0;
5709                 if (vcpu->arch.interrupt.soft)
5710                         inc_eip = vcpu->arch.event_exit_inst_len;
5711                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5712                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5713                 return;
5714         }
5715         intr = irq | INTR_INFO_VALID_MASK;
5716         if (vcpu->arch.interrupt.soft) {
5717                 intr |= INTR_TYPE_SOFT_INTR;
5718                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5719                              vmx->vcpu.arch.event_exit_inst_len);
5720         } else
5721                 intr |= INTR_TYPE_EXT_INTR;
5722         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5723 }
5724
5725 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5726 {
5727         struct vcpu_vmx *vmx = to_vmx(vcpu);
5728
5729         if (!enable_vnmi) {
5730                 /*
5731                  * Tracking the NMI-blocked state in software is built upon
5732                  * finding the next open IRQ window. This, in turn, depends on
5733                  * well-behaving guests: They have to keep IRQs disabled at
5734                  * least as long as the NMI handler runs. Otherwise we may
5735                  * cause NMI nesting, maybe breaking the guest. But as this is
5736                  * highly unlikely, we can live with the residual risk.
5737                  */
5738                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
5739                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
5740         }
5741
5742         ++vcpu->stat.nmi_injections;
5743         vmx->loaded_vmcs->nmi_known_unmasked = false;
5744
5745         if (vmx->rmode.vm86_active) {
5746                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5747                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5748                 return;
5749         }
5750
5751         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5752                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5753 }
5754
5755 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5756 {
5757         struct vcpu_vmx *vmx = to_vmx(vcpu);
5758         bool masked;
5759
5760         if (!enable_vnmi)
5761                 return vmx->loaded_vmcs->soft_vnmi_blocked;
5762         if (vmx->loaded_vmcs->nmi_known_unmasked)
5763                 return false;
5764         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5765         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5766         return masked;
5767 }
5768
5769 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5770 {
5771         struct vcpu_vmx *vmx = to_vmx(vcpu);
5772
5773         if (!enable_vnmi) {
5774                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
5775                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
5776                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
5777                 }
5778         } else {
5779                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5780                 if (masked)
5781                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5782                                       GUEST_INTR_STATE_NMI);
5783                 else
5784                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5785                                         GUEST_INTR_STATE_NMI);
5786         }
5787 }
5788
5789 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5790 {
5791         if (to_vmx(vcpu)->nested.nested_run_pending)
5792                 return 0;
5793
5794         if (!enable_vnmi &&
5795             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
5796                 return 0;
5797
5798         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5799                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5800                    | GUEST_INTR_STATE_NMI));
5801 }
5802
5803 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5804 {
5805         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5806                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5807                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5808                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5809 }
5810
5811 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5812 {
5813         int ret;
5814
5815         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5816                                     PAGE_SIZE * 3);
5817         if (ret)
5818                 return ret;
5819         kvm->arch.tss_addr = addr;
5820         return init_rmode_tss(kvm);
5821 }
5822
5823 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5824 {
5825         switch (vec) {
5826         case BP_VECTOR:
5827                 /*
5828                  * Update instruction length as we may reinject the exception
5829                  * from user space while in guest debugging mode.
5830                  */
5831                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5832                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5833                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5834                         return false;
5835                 /* fall through */
5836         case DB_VECTOR:
5837                 if (vcpu->guest_debug &
5838                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5839                         return false;
5840                 /* fall through */
5841         case DE_VECTOR:
5842         case OF_VECTOR:
5843         case BR_VECTOR:
5844         case UD_VECTOR:
5845         case DF_VECTOR:
5846         case SS_VECTOR:
5847         case GP_VECTOR:
5848         case MF_VECTOR:
5849                 return true;
5850         break;
5851         }
5852         return false;
5853 }
5854
5855 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5856                                   int vec, u32 err_code)
5857 {
5858         /*
5859          * Instruction with address size override prefix opcode 0x67
5860          * Cause the #SS fault with 0 error code in VM86 mode.
5861          */
5862         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5863                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5864                         if (vcpu->arch.halt_request) {
5865                                 vcpu->arch.halt_request = 0;
5866                                 return kvm_vcpu_halt(vcpu);
5867                         }
5868                         return 1;
5869                 }
5870                 return 0;
5871         }
5872
5873         /*
5874          * Forward all other exceptions that are valid in real mode.
5875          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5876          *        the required debugging infrastructure rework.
5877          */
5878         kvm_queue_exception(vcpu, vec);
5879         return 1;
5880 }
5881
5882 /*
5883  * Trigger machine check on the host. We assume all the MSRs are already set up
5884  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5885  * We pass a fake environment to the machine check handler because we want
5886  * the guest to be always treated like user space, no matter what context
5887  * it used internally.
5888  */
5889 static void kvm_machine_check(void)
5890 {
5891 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5892         struct pt_regs regs = {
5893                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5894                 .flags = X86_EFLAGS_IF,
5895         };
5896
5897         do_machine_check(&regs, 0);
5898 #endif
5899 }
5900
5901 static int handle_machine_check(struct kvm_vcpu *vcpu)
5902 {
5903         /* already handled by vcpu_run */
5904         return 1;
5905 }
5906
5907 static int handle_exception(struct kvm_vcpu *vcpu)
5908 {
5909         struct vcpu_vmx *vmx = to_vmx(vcpu);
5910         struct kvm_run *kvm_run = vcpu->run;
5911         u32 intr_info, ex_no, error_code;
5912         unsigned long cr2, rip, dr6;
5913         u32 vect_info;
5914         enum emulation_result er;
5915
5916         vect_info = vmx->idt_vectoring_info;
5917         intr_info = vmx->exit_intr_info;
5918
5919         if (is_machine_check(intr_info))
5920                 return handle_machine_check(vcpu);
5921
5922         if (is_nmi(intr_info))
5923                 return 1;  /* already handled by vmx_vcpu_run() */
5924
5925         if (is_invalid_opcode(intr_info)) {
5926                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5927                 if (er == EMULATE_USER_EXIT)
5928                         return 0;
5929                 if (er != EMULATE_DONE)
5930                         kvm_queue_exception(vcpu, UD_VECTOR);
5931                 return 1;
5932         }
5933
5934         error_code = 0;
5935         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5936                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5937
5938         /*
5939          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5940          * MMIO, it is better to report an internal error.
5941          * See the comments in vmx_handle_exit.
5942          */
5943         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5944             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5945                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5946                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5947                 vcpu->run->internal.ndata = 3;
5948                 vcpu->run->internal.data[0] = vect_info;
5949                 vcpu->run->internal.data[1] = intr_info;
5950                 vcpu->run->internal.data[2] = error_code;
5951                 return 0;
5952         }
5953
5954         if (is_page_fault(intr_info)) {
5955                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5956                 /* EPT won't cause page fault directly */
5957                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5958                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
5959         }
5960
5961         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5962
5963         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5964                 return handle_rmode_exception(vcpu, ex_no, error_code);
5965
5966         switch (ex_no) {
5967         case AC_VECTOR:
5968                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5969                 return 1;
5970         case DB_VECTOR:
5971                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5972                 if (!(vcpu->guest_debug &
5973                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5974                         vcpu->arch.dr6 &= ~15;
5975                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5976                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5977                                 skip_emulated_instruction(vcpu);
5978
5979                         kvm_queue_exception(vcpu, DB_VECTOR);
5980                         return 1;
5981                 }
5982                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5983                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5984                 /* fall through */
5985         case BP_VECTOR:
5986                 /*
5987                  * Update instruction length as we may reinject #BP from
5988                  * user space while in guest debugging mode. Reading it for
5989                  * #DB as well causes no harm, it is not used in that case.
5990                  */
5991                 vmx->vcpu.arch.event_exit_inst_len =
5992                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5993                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5994                 rip = kvm_rip_read(vcpu);
5995                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5996                 kvm_run->debug.arch.exception = ex_no;
5997                 break;
5998         default:
5999                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6000                 kvm_run->ex.exception = ex_no;
6001                 kvm_run->ex.error_code = error_code;
6002                 break;
6003         }
6004         return 0;
6005 }
6006
6007 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6008 {
6009         ++vcpu->stat.irq_exits;
6010         return 1;
6011 }
6012
6013 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6014 {
6015         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6016         vcpu->mmio_needed = 0;
6017         return 0;
6018 }
6019
6020 static int handle_io(struct kvm_vcpu *vcpu)
6021 {
6022         unsigned long exit_qualification;
6023         int size, in, string, ret;
6024         unsigned port;
6025
6026         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6027         string = (exit_qualification & 16) != 0;
6028         in = (exit_qualification & 8) != 0;
6029
6030         ++vcpu->stat.io_exits;
6031
6032         if (string || in)
6033                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6034
6035         port = exit_qualification >> 16;
6036         size = (exit_qualification & 7) + 1;
6037
6038         ret = kvm_skip_emulated_instruction(vcpu);
6039
6040         /*
6041          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6042          * KVM_EXIT_DEBUG here.
6043          */
6044         return kvm_fast_pio_out(vcpu, size, port) && ret;
6045 }
6046
6047 static void
6048 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6049 {
6050         /*
6051          * Patch in the VMCALL instruction:
6052          */
6053         hypercall[0] = 0x0f;
6054         hypercall[1] = 0x01;
6055         hypercall[2] = 0xc1;
6056 }
6057
6058 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6059 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6060 {
6061         if (is_guest_mode(vcpu)) {
6062                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6063                 unsigned long orig_val = val;
6064
6065                 /*
6066                  * We get here when L2 changed cr0 in a way that did not change
6067                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6068                  * but did change L0 shadowed bits. So we first calculate the
6069                  * effective cr0 value that L1 would like to write into the
6070                  * hardware. It consists of the L2-owned bits from the new
6071                  * value combined with the L1-owned bits from L1's guest_cr0.
6072                  */
6073                 val = (val & ~vmcs12->cr0_guest_host_mask) |
6074                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6075
6076                 if (!nested_guest_cr0_valid(vcpu, val))
6077                         return 1;
6078
6079                 if (kvm_set_cr0(vcpu, val))
6080                         return 1;
6081                 vmcs_writel(CR0_READ_SHADOW, orig_val);
6082                 return 0;
6083         } else {
6084                 if (to_vmx(vcpu)->nested.vmxon &&
6085                     !nested_host_cr0_valid(vcpu, val))
6086                         return 1;
6087
6088                 return kvm_set_cr0(vcpu, val);
6089         }
6090 }
6091
6092 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6093 {
6094         if (is_guest_mode(vcpu)) {
6095                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6096                 unsigned long orig_val = val;
6097
6098                 /* analogously to handle_set_cr0 */
6099                 val = (val & ~vmcs12->cr4_guest_host_mask) |
6100                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6101                 if (kvm_set_cr4(vcpu, val))
6102                         return 1;
6103                 vmcs_writel(CR4_READ_SHADOW, orig_val);
6104                 return 0;
6105         } else
6106                 return kvm_set_cr4(vcpu, val);
6107 }
6108
6109 static int handle_cr(struct kvm_vcpu *vcpu)
6110 {
6111         unsigned long exit_qualification, val;
6112         int cr;
6113         int reg;
6114         int err;
6115         int ret;
6116
6117         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6118         cr = exit_qualification & 15;
6119         reg = (exit_qualification >> 8) & 15;
6120         switch ((exit_qualification >> 4) & 3) {
6121         case 0: /* mov to cr */
6122                 val = kvm_register_readl(vcpu, reg);
6123                 trace_kvm_cr_write(cr, val);
6124                 switch (cr) {
6125                 case 0:
6126                         err = handle_set_cr0(vcpu, val);
6127                         return kvm_complete_insn_gp(vcpu, err);
6128                 case 3:
6129                         err = kvm_set_cr3(vcpu, val);
6130                         return kvm_complete_insn_gp(vcpu, err);
6131                 case 4:
6132                         err = handle_set_cr4(vcpu, val);
6133                         return kvm_complete_insn_gp(vcpu, err);
6134                 case 8: {
6135                                 u8 cr8_prev = kvm_get_cr8(vcpu);
6136                                 u8 cr8 = (u8)val;
6137                                 err = kvm_set_cr8(vcpu, cr8);
6138                                 ret = kvm_complete_insn_gp(vcpu, err);
6139                                 if (lapic_in_kernel(vcpu))
6140                                         return ret;
6141                                 if (cr8_prev <= cr8)
6142                                         return ret;
6143                                 /*
6144                                  * TODO: we might be squashing a
6145                                  * KVM_GUESTDBG_SINGLESTEP-triggered
6146                                  * KVM_EXIT_DEBUG here.
6147                                  */
6148                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6149                                 return 0;
6150                         }
6151                 }
6152                 break;
6153         case 2: /* clts */
6154                 WARN_ONCE(1, "Guest should always own CR0.TS");
6155                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6156                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6157                 return kvm_skip_emulated_instruction(vcpu);
6158         case 1: /*mov from cr*/
6159                 switch (cr) {
6160                 case 3:
6161                         val = kvm_read_cr3(vcpu);
6162                         kvm_register_write(vcpu, reg, val);
6163                         trace_kvm_cr_read(cr, val);
6164                         return kvm_skip_emulated_instruction(vcpu);
6165                 case 8:
6166                         val = kvm_get_cr8(vcpu);
6167                         kvm_register_write(vcpu, reg, val);
6168                         trace_kvm_cr_read(cr, val);
6169                         return kvm_skip_emulated_instruction(vcpu);
6170                 }
6171                 break;
6172         case 3: /* lmsw */
6173                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6174                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6175                 kvm_lmsw(vcpu, val);
6176
6177                 return kvm_skip_emulated_instruction(vcpu);
6178         default:
6179                 break;
6180         }
6181         vcpu->run->exit_reason = 0;
6182         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6183                (int)(exit_qualification >> 4) & 3, cr);
6184         return 0;
6185 }
6186
6187 static int handle_dr(struct kvm_vcpu *vcpu)
6188 {
6189         unsigned long exit_qualification;
6190         int dr, dr7, reg;
6191
6192         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6193         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6194
6195         /* First, if DR does not exist, trigger UD */
6196         if (!kvm_require_dr(vcpu, dr))
6197                 return 1;
6198
6199         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6200         if (!kvm_require_cpl(vcpu, 0))
6201                 return 1;
6202         dr7 = vmcs_readl(GUEST_DR7);
6203         if (dr7 & DR7_GD) {
6204                 /*
6205                  * As the vm-exit takes precedence over the debug trap, we
6206                  * need to emulate the latter, either for the host or the
6207                  * guest debugging itself.
6208                  */
6209                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6210                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6211                         vcpu->run->debug.arch.dr7 = dr7;
6212                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6213                         vcpu->run->debug.arch.exception = DB_VECTOR;
6214                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6215                         return 0;
6216                 } else {
6217                         vcpu->arch.dr6 &= ~15;
6218                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6219                         kvm_queue_exception(vcpu, DB_VECTOR);
6220                         return 1;
6221                 }
6222         }
6223
6224         if (vcpu->guest_debug == 0) {
6225                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6226                                 CPU_BASED_MOV_DR_EXITING);
6227
6228                 /*
6229                  * No more DR vmexits; force a reload of the debug registers
6230                  * and reenter on this instruction.  The next vmexit will
6231                  * retrieve the full state of the debug registers.
6232                  */
6233                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6234                 return 1;
6235         }
6236
6237         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6238         if (exit_qualification & TYPE_MOV_FROM_DR) {
6239                 unsigned long val;
6240
6241                 if (kvm_get_dr(vcpu, dr, &val))
6242                         return 1;
6243                 kvm_register_write(vcpu, reg, val);
6244         } else
6245                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6246                         return 1;
6247
6248         return kvm_skip_emulated_instruction(vcpu);
6249 }
6250
6251 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6252 {
6253         return vcpu->arch.dr6;
6254 }
6255
6256 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6257 {
6258 }
6259
6260 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6261 {
6262         get_debugreg(vcpu->arch.db[0], 0);
6263         get_debugreg(vcpu->arch.db[1], 1);
6264         get_debugreg(vcpu->arch.db[2], 2);
6265         get_debugreg(vcpu->arch.db[3], 3);
6266         get_debugreg(vcpu->arch.dr6, 6);
6267         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6268
6269         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6270         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6271 }
6272
6273 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6274 {
6275         vmcs_writel(GUEST_DR7, val);
6276 }
6277
6278 static int handle_cpuid(struct kvm_vcpu *vcpu)
6279 {
6280         return kvm_emulate_cpuid(vcpu);
6281 }
6282
6283 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6284 {
6285         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6286         struct msr_data msr_info;
6287
6288         msr_info.index = ecx;
6289         msr_info.host_initiated = false;
6290         if (vmx_get_msr(vcpu, &msr_info)) {
6291                 trace_kvm_msr_read_ex(ecx);
6292                 kvm_inject_gp(vcpu, 0);
6293                 return 1;
6294         }
6295
6296         trace_kvm_msr_read(ecx, msr_info.data);
6297
6298         /* FIXME: handling of bits 32:63 of rax, rdx */
6299         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6300         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6301         return kvm_skip_emulated_instruction(vcpu);
6302 }
6303
6304 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6305 {
6306         struct msr_data msr;
6307         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6308         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6309                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6310
6311         msr.data = data;
6312         msr.index = ecx;
6313         msr.host_initiated = false;
6314         if (kvm_set_msr(vcpu, &msr) != 0) {
6315                 trace_kvm_msr_write_ex(ecx, data);
6316                 kvm_inject_gp(vcpu, 0);
6317                 return 1;
6318         }
6319
6320         trace_kvm_msr_write(ecx, data);
6321         return kvm_skip_emulated_instruction(vcpu);
6322 }
6323
6324 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6325 {
6326         kvm_apic_update_ppr(vcpu);
6327         return 1;
6328 }
6329
6330 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6331 {
6332         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6333                         CPU_BASED_VIRTUAL_INTR_PENDING);
6334
6335         kvm_make_request(KVM_REQ_EVENT, vcpu);
6336
6337         ++vcpu->stat.irq_window_exits;
6338         return 1;
6339 }
6340
6341 static int handle_halt(struct kvm_vcpu *vcpu)
6342 {
6343         return kvm_emulate_halt(vcpu);
6344 }
6345
6346 static int handle_vmcall(struct kvm_vcpu *vcpu)
6347 {
6348         return kvm_emulate_hypercall(vcpu);
6349 }
6350
6351 static int handle_invd(struct kvm_vcpu *vcpu)
6352 {
6353         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6354 }
6355
6356 static int handle_invlpg(struct kvm_vcpu *vcpu)
6357 {
6358         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6359
6360         kvm_mmu_invlpg(vcpu, exit_qualification);
6361         return kvm_skip_emulated_instruction(vcpu);
6362 }
6363
6364 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6365 {
6366         int err;
6367
6368         err = kvm_rdpmc(vcpu);
6369         return kvm_complete_insn_gp(vcpu, err);
6370 }
6371
6372 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6373 {
6374         return kvm_emulate_wbinvd(vcpu);
6375 }
6376
6377 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6378 {
6379         u64 new_bv = kvm_read_edx_eax(vcpu);
6380         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6381
6382         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6383                 return kvm_skip_emulated_instruction(vcpu);
6384         return 1;
6385 }
6386
6387 static int handle_xsaves(struct kvm_vcpu *vcpu)
6388 {
6389         kvm_skip_emulated_instruction(vcpu);
6390         WARN(1, "this should never happen\n");
6391         return 1;
6392 }
6393
6394 static int handle_xrstors(struct kvm_vcpu *vcpu)
6395 {
6396         kvm_skip_emulated_instruction(vcpu);
6397         WARN(1, "this should never happen\n");
6398         return 1;
6399 }
6400
6401 static int handle_apic_access(struct kvm_vcpu *vcpu)
6402 {
6403         if (likely(fasteoi)) {
6404                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6405                 int access_type, offset;
6406
6407                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6408                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6409                 /*
6410                  * Sane guest uses MOV to write EOI, with written value
6411                  * not cared. So make a short-circuit here by avoiding
6412                  * heavy instruction emulation.
6413                  */
6414                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6415                     (offset == APIC_EOI)) {
6416                         kvm_lapic_set_eoi(vcpu);
6417                         return kvm_skip_emulated_instruction(vcpu);
6418                 }
6419         }
6420         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6421 }
6422
6423 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6424 {
6425         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6426         int vector = exit_qualification & 0xff;
6427
6428         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6429         kvm_apic_set_eoi_accelerated(vcpu, vector);
6430         return 1;
6431 }
6432
6433 static int handle_apic_write(struct kvm_vcpu *vcpu)
6434 {
6435         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6436         u32 offset = exit_qualification & 0xfff;
6437
6438         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6439         kvm_apic_write_nodecode(vcpu, offset);
6440         return 1;
6441 }
6442
6443 static int handle_task_switch(struct kvm_vcpu *vcpu)
6444 {
6445         struct vcpu_vmx *vmx = to_vmx(vcpu);
6446         unsigned long exit_qualification;
6447         bool has_error_code = false;
6448         u32 error_code = 0;
6449         u16 tss_selector;
6450         int reason, type, idt_v, idt_index;
6451
6452         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6453         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6454         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6455
6456         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6457
6458         reason = (u32)exit_qualification >> 30;
6459         if (reason == TASK_SWITCH_GATE && idt_v) {
6460                 switch (type) {
6461                 case INTR_TYPE_NMI_INTR:
6462                         vcpu->arch.nmi_injected = false;
6463                         vmx_set_nmi_mask(vcpu, true);
6464                         break;
6465                 case INTR_TYPE_EXT_INTR:
6466                 case INTR_TYPE_SOFT_INTR:
6467                         kvm_clear_interrupt_queue(vcpu);
6468                         break;
6469                 case INTR_TYPE_HARD_EXCEPTION:
6470                         if (vmx->idt_vectoring_info &
6471                             VECTORING_INFO_DELIVER_CODE_MASK) {
6472                                 has_error_code = true;
6473                                 error_code =
6474                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6475                         }
6476                         /* fall through */
6477                 case INTR_TYPE_SOFT_EXCEPTION:
6478                         kvm_clear_exception_queue(vcpu);
6479                         break;
6480                 default:
6481                         break;
6482                 }
6483         }
6484         tss_selector = exit_qualification;
6485
6486         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6487                        type != INTR_TYPE_EXT_INTR &&
6488                        type != INTR_TYPE_NMI_INTR))
6489                 skip_emulated_instruction(vcpu);
6490
6491         if (kvm_task_switch(vcpu, tss_selector,
6492                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6493                             has_error_code, error_code) == EMULATE_FAIL) {
6494                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6495                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6496                 vcpu->run->internal.ndata = 0;
6497                 return 0;
6498         }
6499
6500         /*
6501          * TODO: What about debug traps on tss switch?
6502          *       Are we supposed to inject them and update dr6?
6503          */
6504
6505         return 1;
6506 }
6507
6508 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6509 {
6510         unsigned long exit_qualification;
6511         gpa_t gpa;
6512         u64 error_code;
6513
6514         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6515
6516         /*
6517          * EPT violation happened while executing iret from NMI,
6518          * "blocked by NMI" bit has to be set before next VM entry.
6519          * There are errata that may cause this bit to not be set:
6520          * AAK134, BY25.
6521          */
6522         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6523                         enable_vnmi &&
6524                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6525                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6526
6527         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6528         trace_kvm_page_fault(gpa, exit_qualification);
6529
6530         /* Is it a read fault? */
6531         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6532                      ? PFERR_USER_MASK : 0;
6533         /* Is it a write fault? */
6534         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6535                       ? PFERR_WRITE_MASK : 0;
6536         /* Is it a fetch fault? */
6537         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6538                       ? PFERR_FETCH_MASK : 0;
6539         /* ept page table entry is present? */
6540         error_code |= (exit_qualification &
6541                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6542                         EPT_VIOLATION_EXECUTABLE))
6543                       ? PFERR_PRESENT_MASK : 0;
6544
6545         error_code |= (exit_qualification & 0x100) != 0 ?
6546                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
6547
6548         vcpu->arch.exit_qualification = exit_qualification;
6549         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6550 }
6551
6552 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6553 {
6554         int ret;
6555         gpa_t gpa;
6556
6557         /*
6558          * A nested guest cannot optimize MMIO vmexits, because we have an
6559          * nGPA here instead of the required GPA.
6560          */
6561         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6562         if (!is_guest_mode(vcpu) &&
6563             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6564                 trace_kvm_fast_mmio(gpa);
6565                 return kvm_skip_emulated_instruction(vcpu);
6566         }
6567
6568         ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
6569         if (ret >= 0)
6570                 return ret;
6571
6572         /* It is the real ept misconfig */
6573         WARN_ON(1);
6574
6575         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6576         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6577
6578         return 0;
6579 }
6580
6581 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6582 {
6583         WARN_ON_ONCE(!enable_vnmi);
6584         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6585                         CPU_BASED_VIRTUAL_NMI_PENDING);
6586         ++vcpu->stat.nmi_window_exits;
6587         kvm_make_request(KVM_REQ_EVENT, vcpu);
6588
6589         return 1;
6590 }
6591
6592 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6593 {
6594         struct vcpu_vmx *vmx = to_vmx(vcpu);
6595         enum emulation_result err = EMULATE_DONE;
6596         int ret = 1;
6597         u32 cpu_exec_ctrl;
6598         bool intr_window_requested;
6599         unsigned count = 130;
6600
6601         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6602         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6603
6604         while (vmx->emulation_required && count-- != 0) {
6605                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6606                         return handle_interrupt_window(&vmx->vcpu);
6607
6608                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6609                         return 1;
6610
6611                 err = emulate_instruction(vcpu, 0);
6612
6613                 if (err == EMULATE_USER_EXIT) {
6614                         ++vcpu->stat.mmio_exits;
6615                         ret = 0;
6616                         goto out;
6617                 }
6618
6619                 if (err != EMULATE_DONE) {
6620                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6621                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6622                         vcpu->run->internal.ndata = 0;
6623                         return 0;
6624                 }
6625
6626                 if (vcpu->arch.halt_request) {
6627                         vcpu->arch.halt_request = 0;
6628                         ret = kvm_vcpu_halt(vcpu);
6629                         goto out;
6630                 }
6631
6632                 if (signal_pending(current))
6633                         goto out;
6634                 if (need_resched())
6635                         schedule();
6636         }
6637
6638 out:
6639         return ret;
6640 }
6641
6642 static int __grow_ple_window(int val)
6643 {
6644         if (ple_window_grow < 1)
6645                 return ple_window;
6646
6647         val = min(val, ple_window_actual_max);
6648
6649         if (ple_window_grow < ple_window)
6650                 val *= ple_window_grow;
6651         else
6652                 val += ple_window_grow;
6653
6654         return val;
6655 }
6656
6657 static int __shrink_ple_window(int val, int modifier, int minimum)
6658 {
6659         if (modifier < 1)
6660                 return ple_window;
6661
6662         if (modifier < ple_window)
6663                 val /= modifier;
6664         else
6665                 val -= modifier;
6666
6667         return max(val, minimum);
6668 }
6669
6670 static void grow_ple_window(struct kvm_vcpu *vcpu)
6671 {
6672         struct vcpu_vmx *vmx = to_vmx(vcpu);
6673         int old = vmx->ple_window;
6674
6675         vmx->ple_window = __grow_ple_window(old);
6676
6677         if (vmx->ple_window != old)
6678                 vmx->ple_window_dirty = true;
6679
6680         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6681 }
6682
6683 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6684 {
6685         struct vcpu_vmx *vmx = to_vmx(vcpu);
6686         int old = vmx->ple_window;
6687
6688         vmx->ple_window = __shrink_ple_window(old,
6689                                               ple_window_shrink, ple_window);
6690
6691         if (vmx->ple_window != old)
6692                 vmx->ple_window_dirty = true;
6693
6694         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6695 }
6696
6697 /*
6698  * ple_window_actual_max is computed to be one grow_ple_window() below
6699  * ple_window_max. (See __grow_ple_window for the reason.)
6700  * This prevents overflows, because ple_window_max is int.
6701  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6702  * this process.
6703  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6704  */
6705 static void update_ple_window_actual_max(void)
6706 {
6707         ple_window_actual_max =
6708                         __shrink_ple_window(max(ple_window_max, ple_window),
6709                                             ple_window_grow, INT_MIN);
6710 }
6711
6712 /*
6713  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6714  */
6715 static void wakeup_handler(void)
6716 {
6717         struct kvm_vcpu *vcpu;
6718         int cpu = smp_processor_id();
6719
6720         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6721         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6722                         blocked_vcpu_list) {
6723                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6724
6725                 if (pi_test_on(pi_desc) == 1)
6726                         kvm_vcpu_kick(vcpu);
6727         }
6728         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6729 }
6730
6731 void vmx_enable_tdp(void)
6732 {
6733         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6734                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6735                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6736                 0ull, VMX_EPT_EXECUTABLE_MASK,
6737                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6738                 VMX_EPT_RWX_MASK, 0ull);
6739
6740         ept_set_mmio_spte_mask();
6741         kvm_enable_tdp();
6742 }
6743
6744 static __init int hardware_setup(void)
6745 {
6746         int r = -ENOMEM, i, msr;
6747
6748         rdmsrl_safe(MSR_EFER, &host_efer);
6749
6750         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6751                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6752
6753         for (i = 0; i < VMX_BITMAP_NR; i++) {
6754                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6755                 if (!vmx_bitmap[i])
6756                         goto out;
6757         }
6758
6759         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6760         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6761
6762         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6763
6764         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6765
6766         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6767         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6768
6769         if (setup_vmcs_config(&vmcs_config) < 0) {
6770                 r = -EIO;
6771                 goto out;
6772         }
6773
6774         if (boot_cpu_has(X86_FEATURE_NX))
6775                 kvm_enable_efer_bits(EFER_NX);
6776
6777         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6778                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6779                 enable_vpid = 0;
6780
6781         if (!cpu_has_vmx_shadow_vmcs())
6782                 enable_shadow_vmcs = 0;
6783         if (enable_shadow_vmcs)
6784                 init_vmcs_shadow_fields();
6785
6786         if (!cpu_has_vmx_ept() ||
6787             !cpu_has_vmx_ept_4levels() ||
6788             !cpu_has_vmx_ept_mt_wb() ||
6789             !cpu_has_vmx_invept_global())
6790                 enable_ept = 0;
6791
6792         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6793                 enable_ept_ad_bits = 0;
6794
6795         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
6796                 enable_unrestricted_guest = 0;
6797
6798         if (!cpu_has_vmx_flexpriority())
6799                 flexpriority_enabled = 0;
6800
6801         if (!cpu_has_virtual_nmis())
6802                 enable_vnmi = 0;
6803
6804         /*
6805          * set_apic_access_page_addr() is used to reload apic access
6806          * page upon invalidation.  No need to do anything if not
6807          * using the APIC_ACCESS_ADDR VMCS field.
6808          */
6809         if (!flexpriority_enabled)
6810                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6811
6812         if (!cpu_has_vmx_tpr_shadow())
6813                 kvm_x86_ops->update_cr8_intercept = NULL;
6814
6815         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6816                 kvm_disable_largepages();
6817
6818         if (!cpu_has_vmx_ple()) {
6819                 ple_gap = 0;
6820                 ple_window = 0;
6821                 ple_window_grow = 0;
6822                 ple_window_max = 0;
6823                 ple_window_shrink = 0;
6824         }
6825
6826         if (!cpu_has_vmx_apicv()) {
6827                 enable_apicv = 0;
6828                 kvm_x86_ops->sync_pir_to_irr = NULL;
6829         }
6830
6831         if (cpu_has_vmx_tsc_scaling()) {
6832                 kvm_has_tsc_control = true;
6833                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6834                 kvm_tsc_scaling_ratio_frac_bits = 48;
6835         }
6836
6837         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6838         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6839         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6840         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6841         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6842         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6843
6844         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6845                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6846         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6847                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6848         memcpy(vmx_msr_bitmap_legacy_x2apic,
6849                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6850         memcpy(vmx_msr_bitmap_longmode_x2apic,
6851                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6852
6853         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6854
6855         for (msr = 0x800; msr <= 0x8ff; msr++) {
6856                 if (msr == 0x839 /* TMCCT */)
6857                         continue;
6858                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6859         }
6860
6861         /*
6862          * TPR reads and writes can be virtualized even if virtual interrupt
6863          * delivery is not in use.
6864          */
6865         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6866         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6867
6868         /* EOI */
6869         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6870         /* SELF-IPI */
6871         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6872
6873         if (enable_ept)
6874                 vmx_enable_tdp();
6875         else
6876                 kvm_disable_tdp();
6877
6878         update_ple_window_actual_max();
6879
6880         /*
6881          * Only enable PML when hardware supports PML feature, and both EPT
6882          * and EPT A/D bit features are enabled -- PML depends on them to work.
6883          */
6884         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6885                 enable_pml = 0;
6886
6887         if (!enable_pml) {
6888                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6889                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6890                 kvm_x86_ops->flush_log_dirty = NULL;
6891                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6892         }
6893
6894         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6895                 u64 vmx_msr;
6896
6897                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6898                 cpu_preemption_timer_multi =
6899                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6900         } else {
6901                 kvm_x86_ops->set_hv_timer = NULL;
6902                 kvm_x86_ops->cancel_hv_timer = NULL;
6903         }
6904
6905         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6906
6907         kvm_mce_cap_supported |= MCG_LMCE_P;
6908
6909         return alloc_kvm_area();
6910
6911 out:
6912         for (i = 0; i < VMX_BITMAP_NR; i++)
6913                 free_page((unsigned long)vmx_bitmap[i]);
6914
6915     return r;
6916 }
6917
6918 static __exit void hardware_unsetup(void)
6919 {
6920         int i;
6921
6922         for (i = 0; i < VMX_BITMAP_NR; i++)
6923                 free_page((unsigned long)vmx_bitmap[i]);
6924
6925         free_kvm_area();
6926 }
6927
6928 /*
6929  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6930  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6931  */
6932 static int handle_pause(struct kvm_vcpu *vcpu)
6933 {
6934         if (ple_gap)
6935                 grow_ple_window(vcpu);
6936
6937         /*
6938          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6939          * VM-execution control is ignored if CPL > 0. OTOH, KVM
6940          * never set PAUSE_EXITING and just set PLE if supported,
6941          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6942          */
6943         kvm_vcpu_on_spin(vcpu, true);
6944         return kvm_skip_emulated_instruction(vcpu);
6945 }
6946
6947 static int handle_nop(struct kvm_vcpu *vcpu)
6948 {
6949         return kvm_skip_emulated_instruction(vcpu);
6950 }
6951
6952 static int handle_mwait(struct kvm_vcpu *vcpu)
6953 {
6954         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6955         return handle_nop(vcpu);
6956 }
6957
6958 static int handle_invalid_op(struct kvm_vcpu *vcpu)
6959 {
6960         kvm_queue_exception(vcpu, UD_VECTOR);
6961         return 1;
6962 }
6963
6964 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6965 {
6966         return 1;
6967 }
6968
6969 static int handle_monitor(struct kvm_vcpu *vcpu)
6970 {
6971         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6972         return handle_nop(vcpu);
6973 }
6974
6975 /*
6976  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6977  * We could reuse a single VMCS for all the L2 guests, but we also want the
6978  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6979  * allows keeping them loaded on the processor, and in the future will allow
6980  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6981  * every entry if they never change.
6982  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6983  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6984  *
6985  * The following functions allocate and free a vmcs02 in this pool.
6986  */
6987
6988 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6989 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6990 {
6991         struct vmcs02_list *item;
6992         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6993                 if (item->vmptr == vmx->nested.current_vmptr) {
6994                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6995                         return &item->vmcs02;
6996                 }
6997
6998         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6999                 /* Recycle the least recently used VMCS. */
7000                 item = list_last_entry(&vmx->nested.vmcs02_pool,
7001                                        struct vmcs02_list, list);
7002                 item->vmptr = vmx->nested.current_vmptr;
7003                 list_move(&item->list, &vmx->nested.vmcs02_pool);
7004                 return &item->vmcs02;
7005         }
7006
7007         /* Create a new VMCS */
7008         item = kzalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
7009         if (!item)
7010                 return NULL;
7011         item->vmcs02.vmcs = alloc_vmcs();
7012         item->vmcs02.shadow_vmcs = NULL;
7013         if (!item->vmcs02.vmcs) {
7014                 kfree(item);
7015                 return NULL;
7016         }
7017         loaded_vmcs_init(&item->vmcs02);
7018         item->vmptr = vmx->nested.current_vmptr;
7019         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
7020         vmx->nested.vmcs02_num++;
7021         return &item->vmcs02;
7022 }
7023
7024 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
7025 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
7026 {
7027         struct vmcs02_list *item;
7028         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
7029                 if (item->vmptr == vmptr) {
7030                         free_loaded_vmcs(&item->vmcs02);
7031                         list_del(&item->list);
7032                         kfree(item);
7033                         vmx->nested.vmcs02_num--;
7034                         return;
7035                 }
7036 }
7037
7038 /*
7039  * Free all VMCSs saved for this vcpu, except the one pointed by
7040  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
7041  * must be &vmx->vmcs01.
7042  */
7043 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
7044 {
7045         struct vmcs02_list *item, *n;
7046
7047         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
7048         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
7049                 /*
7050                  * Something will leak if the above WARN triggers.  Better than
7051                  * a use-after-free.
7052                  */
7053                 if (vmx->loaded_vmcs == &item->vmcs02)
7054                         continue;
7055
7056                 free_loaded_vmcs(&item->vmcs02);
7057                 list_del(&item->list);
7058                 kfree(item);
7059                 vmx->nested.vmcs02_num--;
7060         }
7061 }
7062
7063 /*
7064  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7065  * set the success or error code of an emulated VMX instruction, as specified
7066  * by Vol 2B, VMX Instruction Reference, "Conventions".
7067  */
7068 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7069 {
7070         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7071                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7072                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7073 }
7074
7075 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7076 {
7077         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7078                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7079                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7080                         | X86_EFLAGS_CF);
7081 }
7082
7083 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7084                                         u32 vm_instruction_error)
7085 {
7086         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7087                 /*
7088                  * failValid writes the error number to the current VMCS, which
7089                  * can't be done there isn't a current VMCS.
7090                  */
7091                 nested_vmx_failInvalid(vcpu);
7092                 return;
7093         }
7094         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7095                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7096                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7097                         | X86_EFLAGS_ZF);
7098         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7099         /*
7100          * We don't need to force a shadow sync because
7101          * VM_INSTRUCTION_ERROR is not shadowed
7102          */
7103 }
7104
7105 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7106 {
7107         /* TODO: not to reset guest simply here. */
7108         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7109         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7110 }
7111
7112 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7113 {
7114         struct vcpu_vmx *vmx =
7115                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7116
7117         vmx->nested.preemption_timer_expired = true;
7118         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7119         kvm_vcpu_kick(&vmx->vcpu);
7120
7121         return HRTIMER_NORESTART;
7122 }
7123
7124 /*
7125  * Decode the memory-address operand of a vmx instruction, as recorded on an
7126  * exit caused by such an instruction (run by a guest hypervisor).
7127  * On success, returns 0. When the operand is invalid, returns 1 and throws
7128  * #UD or #GP.
7129  */
7130 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7131                                  unsigned long exit_qualification,
7132                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
7133 {
7134         gva_t off;
7135         bool exn;
7136         struct kvm_segment s;
7137
7138         /*
7139          * According to Vol. 3B, "Information for VM Exits Due to Instruction
7140          * Execution", on an exit, vmx_instruction_info holds most of the
7141          * addressing components of the operand. Only the displacement part
7142          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7143          * For how an actual address is calculated from all these components,
7144          * refer to Vol. 1, "Operand Addressing".
7145          */
7146         int  scaling = vmx_instruction_info & 3;
7147         int  addr_size = (vmx_instruction_info >> 7) & 7;
7148         bool is_reg = vmx_instruction_info & (1u << 10);
7149         int  seg_reg = (vmx_instruction_info >> 15) & 7;
7150         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
7151         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7152         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
7153         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
7154
7155         if (is_reg) {
7156                 kvm_queue_exception(vcpu, UD_VECTOR);
7157                 return 1;
7158         }
7159
7160         /* Addr = segment_base + offset */
7161         /* offset = base + [index * scale] + displacement */
7162         off = exit_qualification; /* holds the displacement */
7163         if (base_is_valid)
7164                 off += kvm_register_read(vcpu, base_reg);
7165         if (index_is_valid)
7166                 off += kvm_register_read(vcpu, index_reg)<<scaling;
7167         vmx_get_segment(vcpu, &s, seg_reg);
7168         *ret = s.base + off;
7169
7170         if (addr_size == 1) /* 32 bit */
7171                 *ret &= 0xffffffff;
7172
7173         /* Checks for #GP/#SS exceptions. */
7174         exn = false;
7175         if (is_long_mode(vcpu)) {
7176                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7177                  * non-canonical form. This is the only check on the memory
7178                  * destination for long mode!
7179                  */
7180                 exn = is_noncanonical_address(*ret, vcpu);
7181         } else if (is_protmode(vcpu)) {
7182                 /* Protected mode: apply checks for segment validity in the
7183                  * following order:
7184                  * - segment type check (#GP(0) may be thrown)
7185                  * - usability check (#GP(0)/#SS(0))
7186                  * - limit check (#GP(0)/#SS(0))
7187                  */
7188                 if (wr)
7189                         /* #GP(0) if the destination operand is located in a
7190                          * read-only data segment or any code segment.
7191                          */
7192                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
7193                 else
7194                         /* #GP(0) if the source operand is located in an
7195                          * execute-only code segment
7196                          */
7197                         exn = ((s.type & 0xa) == 8);
7198                 if (exn) {
7199                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7200                         return 1;
7201                 }
7202                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7203                  */
7204                 exn = (s.unusable != 0);
7205                 /* Protected mode: #GP(0)/#SS(0) if the memory
7206                  * operand is outside the segment limit.
7207                  */
7208                 exn = exn || (off + sizeof(u64) > s.limit);
7209         }
7210         if (exn) {
7211                 kvm_queue_exception_e(vcpu,
7212                                       seg_reg == VCPU_SREG_SS ?
7213                                                 SS_VECTOR : GP_VECTOR,
7214                                       0);
7215                 return 1;
7216         }
7217
7218         return 0;
7219 }
7220
7221 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7222 {
7223         gva_t gva;
7224         struct x86_exception e;
7225
7226         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7227                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7228                 return 1;
7229
7230         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7231                                 sizeof(*vmpointer), &e)) {
7232                 kvm_inject_page_fault(vcpu, &e);
7233                 return 1;
7234         }
7235
7236         return 0;
7237 }
7238
7239 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7240 {
7241         struct vcpu_vmx *vmx = to_vmx(vcpu);
7242         struct vmcs *shadow_vmcs;
7243
7244         if (cpu_has_vmx_msr_bitmap()) {
7245                 vmx->nested.msr_bitmap =
7246                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7247                 if (!vmx->nested.msr_bitmap)
7248                         goto out_msr_bitmap;
7249         }
7250
7251         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7252         if (!vmx->nested.cached_vmcs12)
7253                 goto out_cached_vmcs12;
7254
7255         if (enable_shadow_vmcs) {
7256                 shadow_vmcs = alloc_vmcs();
7257                 if (!shadow_vmcs)
7258                         goto out_shadow_vmcs;
7259                 /* mark vmcs as shadow */
7260                 shadow_vmcs->revision_id |= (1u << 31);
7261                 /* init shadow vmcs */
7262                 vmcs_clear(shadow_vmcs);
7263                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7264         }
7265
7266         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7267         vmx->nested.vmcs02_num = 0;
7268
7269         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7270                      HRTIMER_MODE_REL_PINNED);
7271         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7272
7273         vmx->nested.vmxon = true;
7274         return 0;
7275
7276 out_shadow_vmcs:
7277         kfree(vmx->nested.cached_vmcs12);
7278
7279 out_cached_vmcs12:
7280         free_page((unsigned long)vmx->nested.msr_bitmap);
7281
7282 out_msr_bitmap:
7283         return -ENOMEM;
7284 }
7285
7286 /*
7287  * Emulate the VMXON instruction.
7288  * Currently, we just remember that VMX is active, and do not save or even
7289  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7290  * do not currently need to store anything in that guest-allocated memory
7291  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7292  * argument is different from the VMXON pointer (which the spec says they do).
7293  */
7294 static int handle_vmon(struct kvm_vcpu *vcpu)
7295 {
7296         int ret;
7297         gpa_t vmptr;
7298         struct page *page;
7299         struct vcpu_vmx *vmx = to_vmx(vcpu);
7300         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7301                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7302
7303         /*
7304          * The Intel VMX Instruction Reference lists a bunch of bits that are
7305          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7306          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7307          * Otherwise, we should fail with #UD.  But most faulting conditions
7308          * have already been checked by hardware, prior to the VM-exit for
7309          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7310          * that bit set to 1 in non-root mode.
7311          */
7312         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7313                 kvm_queue_exception(vcpu, UD_VECTOR);
7314                 return 1;
7315         }
7316
7317         if (vmx->nested.vmxon) {
7318                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7319                 return kvm_skip_emulated_instruction(vcpu);
7320         }
7321
7322         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7323                         != VMXON_NEEDED_FEATURES) {
7324                 kvm_inject_gp(vcpu, 0);
7325                 return 1;
7326         }
7327
7328         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7329                 return 1;
7330
7331         /*
7332          * SDM 3: 24.11.5
7333          * The first 4 bytes of VMXON region contain the supported
7334          * VMCS revision identifier
7335          *
7336          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7337          * which replaces physical address width with 32
7338          */
7339         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7340                 nested_vmx_failInvalid(vcpu);
7341                 return kvm_skip_emulated_instruction(vcpu);
7342         }
7343
7344         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7345         if (is_error_page(page)) {
7346                 nested_vmx_failInvalid(vcpu);
7347                 return kvm_skip_emulated_instruction(vcpu);
7348         }
7349         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7350                 kunmap(page);
7351                 kvm_release_page_clean(page);
7352                 nested_vmx_failInvalid(vcpu);
7353                 return kvm_skip_emulated_instruction(vcpu);
7354         }
7355         kunmap(page);
7356         kvm_release_page_clean(page);
7357
7358         vmx->nested.vmxon_ptr = vmptr;
7359         ret = enter_vmx_operation(vcpu);
7360         if (ret)
7361                 return ret;
7362
7363         nested_vmx_succeed(vcpu);
7364         return kvm_skip_emulated_instruction(vcpu);
7365 }
7366
7367 /*
7368  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7369  * for running VMX instructions (except VMXON, whose prerequisites are
7370  * slightly different). It also specifies what exception to inject otherwise.
7371  * Note that many of these exceptions have priority over VM exits, so they
7372  * don't have to be checked again here.
7373  */
7374 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7375 {
7376         if (!to_vmx(vcpu)->nested.vmxon) {
7377                 kvm_queue_exception(vcpu, UD_VECTOR);
7378                 return 0;
7379         }
7380         return 1;
7381 }
7382
7383 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7384 {
7385         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7386         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7387 }
7388
7389 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7390 {
7391         if (vmx->nested.current_vmptr == -1ull)
7392                 return;
7393
7394         if (enable_shadow_vmcs) {
7395                 /* copy to memory all shadowed fields in case
7396                    they were modified */
7397                 copy_shadow_to_vmcs12(vmx);
7398                 vmx->nested.sync_shadow_vmcs = false;
7399                 vmx_disable_shadow_vmcs(vmx);
7400         }
7401         vmx->nested.posted_intr_nv = -1;
7402
7403         /* Flush VMCS12 to guest memory */
7404         kvm_vcpu_write_guest_page(&vmx->vcpu,
7405                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
7406                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7407
7408         vmx->nested.current_vmptr = -1ull;
7409 }
7410
7411 /*
7412  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7413  * just stops using VMX.
7414  */
7415 static void free_nested(struct vcpu_vmx *vmx)
7416 {
7417         if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
7418                 return;
7419
7420         vmx->nested.vmxon = false;
7421         vmx->nested.smm.vmxon = false;
7422         free_vpid(vmx->nested.vpid02);
7423         vmx->nested.posted_intr_nv = -1;
7424         vmx->nested.current_vmptr = -1ull;
7425         if (vmx->nested.msr_bitmap) {
7426                 free_page((unsigned long)vmx->nested.msr_bitmap);
7427                 vmx->nested.msr_bitmap = NULL;
7428         }
7429         if (enable_shadow_vmcs) {
7430                 vmx_disable_shadow_vmcs(vmx);
7431                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7432                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7433                 vmx->vmcs01.shadow_vmcs = NULL;
7434         }
7435         kfree(vmx->nested.cached_vmcs12);
7436         /* Unpin physical memory we referred to in current vmcs02 */
7437         if (vmx->nested.apic_access_page) {
7438                 kvm_release_page_dirty(vmx->nested.apic_access_page);
7439                 vmx->nested.apic_access_page = NULL;
7440         }
7441         if (vmx->nested.virtual_apic_page) {
7442                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
7443                 vmx->nested.virtual_apic_page = NULL;
7444         }
7445         if (vmx->nested.pi_desc_page) {
7446                 kunmap(vmx->nested.pi_desc_page);
7447                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
7448                 vmx->nested.pi_desc_page = NULL;
7449                 vmx->nested.pi_desc = NULL;
7450         }
7451
7452         nested_free_all_saved_vmcss(vmx);
7453 }
7454
7455 /* Emulate the VMXOFF instruction */
7456 static int handle_vmoff(struct kvm_vcpu *vcpu)
7457 {
7458         if (!nested_vmx_check_permission(vcpu))
7459                 return 1;
7460         free_nested(to_vmx(vcpu));
7461         nested_vmx_succeed(vcpu);
7462         return kvm_skip_emulated_instruction(vcpu);
7463 }
7464
7465 /* Emulate the VMCLEAR instruction */
7466 static int handle_vmclear(struct kvm_vcpu *vcpu)
7467 {
7468         struct vcpu_vmx *vmx = to_vmx(vcpu);
7469         u32 zero = 0;
7470         gpa_t vmptr;
7471
7472         if (!nested_vmx_check_permission(vcpu))
7473                 return 1;
7474
7475         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7476                 return 1;
7477
7478         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7479                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7480                 return kvm_skip_emulated_instruction(vcpu);
7481         }
7482
7483         if (vmptr == vmx->nested.vmxon_ptr) {
7484                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7485                 return kvm_skip_emulated_instruction(vcpu);
7486         }
7487
7488         if (vmptr == vmx->nested.current_vmptr)
7489                 nested_release_vmcs12(vmx);
7490
7491         kvm_vcpu_write_guest(vcpu,
7492                         vmptr + offsetof(struct vmcs12, launch_state),
7493                         &zero, sizeof(zero));
7494
7495         nested_free_vmcs02(vmx, vmptr);
7496
7497         nested_vmx_succeed(vcpu);
7498         return kvm_skip_emulated_instruction(vcpu);
7499 }
7500
7501 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7502
7503 /* Emulate the VMLAUNCH instruction */
7504 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7505 {
7506         return nested_vmx_run(vcpu, true);
7507 }
7508
7509 /* Emulate the VMRESUME instruction */
7510 static int handle_vmresume(struct kvm_vcpu *vcpu)
7511 {
7512
7513         return nested_vmx_run(vcpu, false);
7514 }
7515
7516 /*
7517  * Read a vmcs12 field. Since these can have varying lengths and we return
7518  * one type, we chose the biggest type (u64) and zero-extend the return value
7519  * to that size. Note that the caller, handle_vmread, might need to use only
7520  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7521  * 64-bit fields are to be returned).
7522  */
7523 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7524                                   unsigned long field, u64 *ret)
7525 {
7526         short offset = vmcs_field_to_offset(field);
7527         char *p;
7528
7529         if (offset < 0)
7530                 return offset;
7531
7532         p = ((char *)(get_vmcs12(vcpu))) + offset;
7533
7534         switch (vmcs_field_type(field)) {
7535         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7536                 *ret = *((natural_width *)p);
7537                 return 0;
7538         case VMCS_FIELD_TYPE_U16:
7539                 *ret = *((u16 *)p);
7540                 return 0;
7541         case VMCS_FIELD_TYPE_U32:
7542                 *ret = *((u32 *)p);
7543                 return 0;
7544         case VMCS_FIELD_TYPE_U64:
7545                 *ret = *((u64 *)p);
7546                 return 0;
7547         default:
7548                 WARN_ON(1);
7549                 return -ENOENT;
7550         }
7551 }
7552
7553
7554 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7555                                    unsigned long field, u64 field_value){
7556         short offset = vmcs_field_to_offset(field);
7557         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7558         if (offset < 0)
7559                 return offset;
7560
7561         switch (vmcs_field_type(field)) {
7562         case VMCS_FIELD_TYPE_U16:
7563                 *(u16 *)p = field_value;
7564                 return 0;
7565         case VMCS_FIELD_TYPE_U32:
7566                 *(u32 *)p = field_value;
7567                 return 0;
7568         case VMCS_FIELD_TYPE_U64:
7569                 *(u64 *)p = field_value;
7570                 return 0;
7571         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7572                 *(natural_width *)p = field_value;
7573                 return 0;
7574         default:
7575                 WARN_ON(1);
7576                 return -ENOENT;
7577         }
7578
7579 }
7580
7581 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7582 {
7583         int i;
7584         unsigned long field;
7585         u64 field_value;
7586         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7587         const unsigned long *fields = shadow_read_write_fields;
7588         const int num_fields = max_shadow_read_write_fields;
7589
7590         preempt_disable();
7591
7592         vmcs_load(shadow_vmcs);
7593
7594         for (i = 0; i < num_fields; i++) {
7595                 field = fields[i];
7596                 switch (vmcs_field_type(field)) {
7597                 case VMCS_FIELD_TYPE_U16:
7598                         field_value = vmcs_read16(field);
7599                         break;
7600                 case VMCS_FIELD_TYPE_U32:
7601                         field_value = vmcs_read32(field);
7602                         break;
7603                 case VMCS_FIELD_TYPE_U64:
7604                         field_value = vmcs_read64(field);
7605                         break;
7606                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7607                         field_value = vmcs_readl(field);
7608                         break;
7609                 default:
7610                         WARN_ON(1);
7611                         continue;
7612                 }
7613                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7614         }
7615
7616         vmcs_clear(shadow_vmcs);
7617         vmcs_load(vmx->loaded_vmcs->vmcs);
7618
7619         preempt_enable();
7620 }
7621
7622 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7623 {
7624         const unsigned long *fields[] = {
7625                 shadow_read_write_fields,
7626                 shadow_read_only_fields
7627         };
7628         const int max_fields[] = {
7629                 max_shadow_read_write_fields,
7630                 max_shadow_read_only_fields
7631         };
7632         int i, q;
7633         unsigned long field;
7634         u64 field_value = 0;
7635         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7636
7637         vmcs_load(shadow_vmcs);
7638
7639         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7640                 for (i = 0; i < max_fields[q]; i++) {
7641                         field = fields[q][i];
7642                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7643
7644                         switch (vmcs_field_type(field)) {
7645                         case VMCS_FIELD_TYPE_U16:
7646                                 vmcs_write16(field, (u16)field_value);
7647                                 break;
7648                         case VMCS_FIELD_TYPE_U32:
7649                                 vmcs_write32(field, (u32)field_value);
7650                                 break;
7651                         case VMCS_FIELD_TYPE_U64:
7652                                 vmcs_write64(field, (u64)field_value);
7653                                 break;
7654                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7655                                 vmcs_writel(field, (long)field_value);
7656                                 break;
7657                         default:
7658                                 WARN_ON(1);
7659                                 break;
7660                         }
7661                 }
7662         }
7663
7664         vmcs_clear(shadow_vmcs);
7665         vmcs_load(vmx->loaded_vmcs->vmcs);
7666 }
7667
7668 /*
7669  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7670  * used before) all generate the same failure when it is missing.
7671  */
7672 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7673 {
7674         struct vcpu_vmx *vmx = to_vmx(vcpu);
7675         if (vmx->nested.current_vmptr == -1ull) {
7676                 nested_vmx_failInvalid(vcpu);
7677                 return 0;
7678         }
7679         return 1;
7680 }
7681
7682 static int handle_vmread(struct kvm_vcpu *vcpu)
7683 {
7684         unsigned long field;
7685         u64 field_value;
7686         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7687         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7688         gva_t gva = 0;
7689
7690         if (!nested_vmx_check_permission(vcpu))
7691                 return 1;
7692
7693         if (!nested_vmx_check_vmcs12(vcpu))
7694                 return kvm_skip_emulated_instruction(vcpu);
7695
7696         /* Decode instruction info and find the field to read */
7697         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7698         /* Read the field, zero-extended to a u64 field_value */
7699         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7700                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7701                 return kvm_skip_emulated_instruction(vcpu);
7702         }
7703         /*
7704          * Now copy part of this value to register or memory, as requested.
7705          * Note that the number of bits actually copied is 32 or 64 depending
7706          * on the guest's mode (32 or 64 bit), not on the given field's length.
7707          */
7708         if (vmx_instruction_info & (1u << 10)) {
7709                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7710                         field_value);
7711         } else {
7712                 if (get_vmx_mem_address(vcpu, exit_qualification,
7713                                 vmx_instruction_info, true, &gva))
7714                         return 1;
7715                 /* _system ok, as hardware has verified cpl=0 */
7716                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7717                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7718         }
7719
7720         nested_vmx_succeed(vcpu);
7721         return kvm_skip_emulated_instruction(vcpu);
7722 }
7723
7724
7725 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7726 {
7727         unsigned long field;
7728         gva_t gva;
7729         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7730         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7731         /* The value to write might be 32 or 64 bits, depending on L1's long
7732          * mode, and eventually we need to write that into a field of several
7733          * possible lengths. The code below first zero-extends the value to 64
7734          * bit (field_value), and then copies only the appropriate number of
7735          * bits into the vmcs12 field.
7736          */
7737         u64 field_value = 0;
7738         struct x86_exception e;
7739
7740         if (!nested_vmx_check_permission(vcpu))
7741                 return 1;
7742
7743         if (!nested_vmx_check_vmcs12(vcpu))
7744                 return kvm_skip_emulated_instruction(vcpu);
7745
7746         if (vmx_instruction_info & (1u << 10))
7747                 field_value = kvm_register_readl(vcpu,
7748                         (((vmx_instruction_info) >> 3) & 0xf));
7749         else {
7750                 if (get_vmx_mem_address(vcpu, exit_qualification,
7751                                 vmx_instruction_info, false, &gva))
7752                         return 1;
7753                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7754                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7755                         kvm_inject_page_fault(vcpu, &e);
7756                         return 1;
7757                 }
7758         }
7759
7760
7761         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7762         if (vmcs_field_readonly(field)) {
7763                 nested_vmx_failValid(vcpu,
7764                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7765                 return kvm_skip_emulated_instruction(vcpu);
7766         }
7767
7768         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7769                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7770                 return kvm_skip_emulated_instruction(vcpu);
7771         }
7772
7773         nested_vmx_succeed(vcpu);
7774         return kvm_skip_emulated_instruction(vcpu);
7775 }
7776
7777 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7778 {
7779         vmx->nested.current_vmptr = vmptr;
7780         if (enable_shadow_vmcs) {
7781                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7782                               SECONDARY_EXEC_SHADOW_VMCS);
7783                 vmcs_write64(VMCS_LINK_POINTER,
7784                              __pa(vmx->vmcs01.shadow_vmcs));
7785                 vmx->nested.sync_shadow_vmcs = true;
7786         }
7787 }
7788
7789 /* Emulate the VMPTRLD instruction */
7790 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7791 {
7792         struct vcpu_vmx *vmx = to_vmx(vcpu);
7793         gpa_t vmptr;
7794
7795         if (!nested_vmx_check_permission(vcpu))
7796                 return 1;
7797
7798         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7799                 return 1;
7800
7801         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7802                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7803                 return kvm_skip_emulated_instruction(vcpu);
7804         }
7805
7806         if (vmptr == vmx->nested.vmxon_ptr) {
7807                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7808                 return kvm_skip_emulated_instruction(vcpu);
7809         }
7810
7811         if (vmx->nested.current_vmptr != vmptr) {
7812                 struct vmcs12 *new_vmcs12;
7813                 struct page *page;
7814                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7815                 if (is_error_page(page)) {
7816                         nested_vmx_failInvalid(vcpu);
7817                         return kvm_skip_emulated_instruction(vcpu);
7818                 }
7819                 new_vmcs12 = kmap(page);
7820                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7821                         kunmap(page);
7822                         kvm_release_page_clean(page);
7823                         nested_vmx_failValid(vcpu,
7824                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7825                         return kvm_skip_emulated_instruction(vcpu);
7826                 }
7827
7828                 nested_release_vmcs12(vmx);
7829                 /*
7830                  * Load VMCS12 from guest memory since it is not already
7831                  * cached.
7832                  */
7833                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
7834                 kunmap(page);
7835                 kvm_release_page_clean(page);
7836
7837                 set_current_vmptr(vmx, vmptr);
7838         }
7839
7840         nested_vmx_succeed(vcpu);
7841         return kvm_skip_emulated_instruction(vcpu);
7842 }
7843
7844 /* Emulate the VMPTRST instruction */
7845 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7846 {
7847         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7848         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7849         gva_t vmcs_gva;
7850         struct x86_exception e;
7851
7852         if (!nested_vmx_check_permission(vcpu))
7853                 return 1;
7854
7855         if (get_vmx_mem_address(vcpu, exit_qualification,
7856                         vmx_instruction_info, true, &vmcs_gva))
7857                 return 1;
7858         /* ok to use *_system, as hardware has verified cpl=0 */
7859         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7860                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7861                                  sizeof(u64), &e)) {
7862                 kvm_inject_page_fault(vcpu, &e);
7863                 return 1;
7864         }
7865         nested_vmx_succeed(vcpu);
7866         return kvm_skip_emulated_instruction(vcpu);
7867 }
7868
7869 /* Emulate the INVEPT instruction */
7870 static int handle_invept(struct kvm_vcpu *vcpu)
7871 {
7872         struct vcpu_vmx *vmx = to_vmx(vcpu);
7873         u32 vmx_instruction_info, types;
7874         unsigned long type;
7875         gva_t gva;
7876         struct x86_exception e;
7877         struct {
7878                 u64 eptp, gpa;
7879         } operand;
7880
7881         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7882               SECONDARY_EXEC_ENABLE_EPT) ||
7883             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7884                 kvm_queue_exception(vcpu, UD_VECTOR);
7885                 return 1;
7886         }
7887
7888         if (!nested_vmx_check_permission(vcpu))
7889                 return 1;
7890
7891         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7892         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7893
7894         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7895
7896         if (type >= 32 || !(types & (1 << type))) {
7897                 nested_vmx_failValid(vcpu,
7898                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7899                 return kvm_skip_emulated_instruction(vcpu);
7900         }
7901
7902         /* According to the Intel VMX instruction reference, the memory
7903          * operand is read even if it isn't needed (e.g., for type==global)
7904          */
7905         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7906                         vmx_instruction_info, false, &gva))
7907                 return 1;
7908         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7909                                 sizeof(operand), &e)) {
7910                 kvm_inject_page_fault(vcpu, &e);
7911                 return 1;
7912         }
7913
7914         switch (type) {
7915         case VMX_EPT_EXTENT_GLOBAL:
7916         /*
7917          * TODO: track mappings and invalidate
7918          * single context requests appropriately
7919          */
7920         case VMX_EPT_EXTENT_CONTEXT:
7921                 kvm_mmu_sync_roots(vcpu);
7922                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7923                 nested_vmx_succeed(vcpu);
7924                 break;
7925         default:
7926                 BUG_ON(1);
7927                 break;
7928         }
7929
7930         return kvm_skip_emulated_instruction(vcpu);
7931 }
7932
7933 static int handle_invvpid(struct kvm_vcpu *vcpu)
7934 {
7935         struct vcpu_vmx *vmx = to_vmx(vcpu);
7936         u32 vmx_instruction_info;
7937         unsigned long type, types;
7938         gva_t gva;
7939         struct x86_exception e;
7940         struct {
7941                 u64 vpid;
7942                 u64 gla;
7943         } operand;
7944
7945         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7946               SECONDARY_EXEC_ENABLE_VPID) ||
7947                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7948                 kvm_queue_exception(vcpu, UD_VECTOR);
7949                 return 1;
7950         }
7951
7952         if (!nested_vmx_check_permission(vcpu))
7953                 return 1;
7954
7955         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7956         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7957
7958         types = (vmx->nested.nested_vmx_vpid_caps &
7959                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7960
7961         if (type >= 32 || !(types & (1 << type))) {
7962                 nested_vmx_failValid(vcpu,
7963                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7964                 return kvm_skip_emulated_instruction(vcpu);
7965         }
7966
7967         /* according to the intel vmx instruction reference, the memory
7968          * operand is read even if it isn't needed (e.g., for type==global)
7969          */
7970         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7971                         vmx_instruction_info, false, &gva))
7972                 return 1;
7973         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7974                                 sizeof(operand), &e)) {
7975                 kvm_inject_page_fault(vcpu, &e);
7976                 return 1;
7977         }
7978         if (operand.vpid >> 16) {
7979                 nested_vmx_failValid(vcpu,
7980                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7981                 return kvm_skip_emulated_instruction(vcpu);
7982         }
7983
7984         switch (type) {
7985         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7986                 if (is_noncanonical_address(operand.gla, vcpu)) {
7987                         nested_vmx_failValid(vcpu,
7988                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7989                         return kvm_skip_emulated_instruction(vcpu);
7990                 }
7991                 /* fall through */
7992         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7993         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7994                 if (!operand.vpid) {
7995                         nested_vmx_failValid(vcpu,
7996                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7997                         return kvm_skip_emulated_instruction(vcpu);
7998                 }
7999                 break;
8000         case VMX_VPID_EXTENT_ALL_CONTEXT:
8001                 break;
8002         default:
8003                 WARN_ON_ONCE(1);
8004                 return kvm_skip_emulated_instruction(vcpu);
8005         }
8006
8007         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
8008         nested_vmx_succeed(vcpu);
8009
8010         return kvm_skip_emulated_instruction(vcpu);
8011 }
8012
8013 static int handle_pml_full(struct kvm_vcpu *vcpu)
8014 {
8015         unsigned long exit_qualification;
8016
8017         trace_kvm_pml_full(vcpu->vcpu_id);
8018
8019         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8020
8021         /*
8022          * PML buffer FULL happened while executing iret from NMI,
8023          * "blocked by NMI" bit has to be set before next VM entry.
8024          */
8025         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
8026                         enable_vnmi &&
8027                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
8028                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8029                                 GUEST_INTR_STATE_NMI);
8030
8031         /*
8032          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8033          * here.., and there's no userspace involvement needed for PML.
8034          */
8035         return 1;
8036 }
8037
8038 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8039 {
8040         kvm_lapic_expired_hv_timer(vcpu);
8041         return 1;
8042 }
8043
8044 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8045 {
8046         struct vcpu_vmx *vmx = to_vmx(vcpu);
8047         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8048
8049         /* Check for memory type validity */
8050         switch (address & VMX_EPTP_MT_MASK) {
8051         case VMX_EPTP_MT_UC:
8052                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT))
8053                         return false;
8054                 break;
8055         case VMX_EPTP_MT_WB:
8056                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT))
8057                         return false;
8058                 break;
8059         default:
8060                 return false;
8061         }
8062
8063         /* only 4 levels page-walk length are valid */
8064         if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8065                 return false;
8066
8067         /* Reserved bits should not be set */
8068         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8069                 return false;
8070
8071         /* AD, if set, should be supported */
8072         if (address & VMX_EPTP_AD_ENABLE_BIT) {
8073                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT))
8074                         return false;
8075         }
8076
8077         return true;
8078 }
8079
8080 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8081                                      struct vmcs12 *vmcs12)
8082 {
8083         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8084         u64 address;
8085         bool accessed_dirty;
8086         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8087
8088         if (!nested_cpu_has_eptp_switching(vmcs12) ||
8089             !nested_cpu_has_ept(vmcs12))
8090                 return 1;
8091
8092         if (index >= VMFUNC_EPTP_ENTRIES)
8093                 return 1;
8094
8095
8096         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8097                                      &address, index * 8, 8))
8098                 return 1;
8099
8100         accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8101
8102         /*
8103          * If the (L2) guest does a vmfunc to the currently
8104          * active ept pointer, we don't have to do anything else
8105          */
8106         if (vmcs12->ept_pointer != address) {
8107                 if (!valid_ept_address(vcpu, address))
8108                         return 1;
8109
8110                 kvm_mmu_unload(vcpu);
8111                 mmu->ept_ad = accessed_dirty;
8112                 mmu->base_role.ad_disabled = !accessed_dirty;
8113                 vmcs12->ept_pointer = address;
8114                 /*
8115                  * TODO: Check what's the correct approach in case
8116                  * mmu reload fails. Currently, we just let the next
8117                  * reload potentially fail
8118                  */
8119                 kvm_mmu_reload(vcpu);
8120         }
8121
8122         return 0;
8123 }
8124
8125 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8126 {
8127         struct vcpu_vmx *vmx = to_vmx(vcpu);
8128         struct vmcs12 *vmcs12;
8129         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8130
8131         /*
8132          * VMFUNC is only supported for nested guests, but we always enable the
8133          * secondary control for simplicity; for non-nested mode, fake that we
8134          * didn't by injecting #UD.
8135          */
8136         if (!is_guest_mode(vcpu)) {
8137                 kvm_queue_exception(vcpu, UD_VECTOR);
8138                 return 1;
8139         }
8140
8141         vmcs12 = get_vmcs12(vcpu);
8142         if ((vmcs12->vm_function_control & (1 << function)) == 0)
8143                 goto fail;
8144
8145         switch (function) {
8146         case 0:
8147                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8148                         goto fail;
8149                 break;
8150         default:
8151                 goto fail;
8152         }
8153         return kvm_skip_emulated_instruction(vcpu);
8154
8155 fail:
8156         nested_vmx_vmexit(vcpu, vmx->exit_reason,
8157                           vmcs_read32(VM_EXIT_INTR_INFO),
8158                           vmcs_readl(EXIT_QUALIFICATION));
8159         return 1;
8160 }
8161
8162 /*
8163  * The exit handlers return 1 if the exit was handled fully and guest execution
8164  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
8165  * to be done to userspace and return 0.
8166  */
8167 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8168         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
8169         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
8170         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
8171         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
8172         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
8173         [EXIT_REASON_CR_ACCESS]               = handle_cr,
8174         [EXIT_REASON_DR_ACCESS]               = handle_dr,
8175         [EXIT_REASON_CPUID]                   = handle_cpuid,
8176         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
8177         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
8178         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
8179         [EXIT_REASON_HLT]                     = handle_halt,
8180         [EXIT_REASON_INVD]                    = handle_invd,
8181         [EXIT_REASON_INVLPG]                  = handle_invlpg,
8182         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
8183         [EXIT_REASON_VMCALL]                  = handle_vmcall,
8184         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
8185         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
8186         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
8187         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
8188         [EXIT_REASON_VMREAD]                  = handle_vmread,
8189         [EXIT_REASON_VMRESUME]                = handle_vmresume,
8190         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
8191         [EXIT_REASON_VMOFF]                   = handle_vmoff,
8192         [EXIT_REASON_VMON]                    = handle_vmon,
8193         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
8194         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
8195         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
8196         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
8197         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
8198         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
8199         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
8200         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
8201         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
8202         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
8203         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
8204         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
8205         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
8206         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
8207         [EXIT_REASON_INVEPT]                  = handle_invept,
8208         [EXIT_REASON_INVVPID]                 = handle_invvpid,
8209         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
8210         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
8211         [EXIT_REASON_XSAVES]                  = handle_xsaves,
8212         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
8213         [EXIT_REASON_PML_FULL]                = handle_pml_full,
8214         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
8215         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
8216 };
8217
8218 static const int kvm_vmx_max_exit_handlers =
8219         ARRAY_SIZE(kvm_vmx_exit_handlers);
8220
8221 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8222                                        struct vmcs12 *vmcs12)
8223 {
8224         unsigned long exit_qualification;
8225         gpa_t bitmap, last_bitmap;
8226         unsigned int port;
8227         int size;
8228         u8 b;
8229
8230         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8231                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8232
8233         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8234
8235         port = exit_qualification >> 16;
8236         size = (exit_qualification & 7) + 1;
8237
8238         last_bitmap = (gpa_t)-1;
8239         b = -1;
8240
8241         while (size > 0) {
8242                 if (port < 0x8000)
8243                         bitmap = vmcs12->io_bitmap_a;
8244                 else if (port < 0x10000)
8245                         bitmap = vmcs12->io_bitmap_b;
8246                 else
8247                         return true;
8248                 bitmap += (port & 0x7fff) / 8;
8249
8250                 if (last_bitmap != bitmap)
8251                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8252                                 return true;
8253                 if (b & (1 << (port & 7)))
8254                         return true;
8255
8256                 port++;
8257                 size--;
8258                 last_bitmap = bitmap;
8259         }
8260
8261         return false;
8262 }
8263
8264 /*
8265  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8266  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8267  * disinterest in the current event (read or write a specific MSR) by using an
8268  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8269  */
8270 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8271         struct vmcs12 *vmcs12, u32 exit_reason)
8272 {
8273         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8274         gpa_t bitmap;
8275
8276         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8277                 return true;
8278
8279         /*
8280          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8281          * for the four combinations of read/write and low/high MSR numbers.
8282          * First we need to figure out which of the four to use:
8283          */
8284         bitmap = vmcs12->msr_bitmap;
8285         if (exit_reason == EXIT_REASON_MSR_WRITE)
8286                 bitmap += 2048;
8287         if (msr_index >= 0xc0000000) {
8288                 msr_index -= 0xc0000000;
8289                 bitmap += 1024;
8290         }
8291
8292         /* Then read the msr_index'th bit from this bitmap: */
8293         if (msr_index < 1024*8) {
8294                 unsigned char b;
8295                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8296                         return true;
8297                 return 1 & (b >> (msr_index & 7));
8298         } else
8299                 return true; /* let L1 handle the wrong parameter */
8300 }
8301
8302 /*
8303  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8304  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8305  * intercept (via guest_host_mask etc.) the current event.
8306  */
8307 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8308         struct vmcs12 *vmcs12)
8309 {
8310         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8311         int cr = exit_qualification & 15;
8312         int reg;
8313         unsigned long val;
8314
8315         switch ((exit_qualification >> 4) & 3) {
8316         case 0: /* mov to cr */
8317                 reg = (exit_qualification >> 8) & 15;
8318                 val = kvm_register_readl(vcpu, reg);
8319                 switch (cr) {
8320                 case 0:
8321                         if (vmcs12->cr0_guest_host_mask &
8322                             (val ^ vmcs12->cr0_read_shadow))
8323                                 return true;
8324                         break;
8325                 case 3:
8326                         if ((vmcs12->cr3_target_count >= 1 &&
8327                                         vmcs12->cr3_target_value0 == val) ||
8328                                 (vmcs12->cr3_target_count >= 2 &&
8329                                         vmcs12->cr3_target_value1 == val) ||
8330                                 (vmcs12->cr3_target_count >= 3 &&
8331                                         vmcs12->cr3_target_value2 == val) ||
8332                                 (vmcs12->cr3_target_count >= 4 &&
8333                                         vmcs12->cr3_target_value3 == val))
8334                                 return false;
8335                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8336                                 return true;
8337                         break;
8338                 case 4:
8339                         if (vmcs12->cr4_guest_host_mask &
8340                             (vmcs12->cr4_read_shadow ^ val))
8341                                 return true;
8342                         break;
8343                 case 8:
8344                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8345                                 return true;
8346                         break;
8347                 }
8348                 break;
8349         case 2: /* clts */
8350                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8351                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8352                         return true;
8353                 break;
8354         case 1: /* mov from cr */
8355                 switch (cr) {
8356                 case 3:
8357                         if (vmcs12->cpu_based_vm_exec_control &
8358                             CPU_BASED_CR3_STORE_EXITING)
8359                                 return true;
8360                         break;
8361                 case 8:
8362                         if (vmcs12->cpu_based_vm_exec_control &
8363                             CPU_BASED_CR8_STORE_EXITING)
8364                                 return true;
8365                         break;
8366                 }
8367                 break;
8368         case 3: /* lmsw */
8369                 /*
8370                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8371                  * cr0. Other attempted changes are ignored, with no exit.
8372                  */
8373                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8374                 if (vmcs12->cr0_guest_host_mask & 0xe &
8375                     (val ^ vmcs12->cr0_read_shadow))
8376                         return true;
8377                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8378                     !(vmcs12->cr0_read_shadow & 0x1) &&
8379                     (val & 0x1))
8380                         return true;
8381                 break;
8382         }
8383         return false;
8384 }
8385
8386 /*
8387  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8388  * should handle it ourselves in L0 (and then continue L2). Only call this
8389  * when in is_guest_mode (L2).
8390  */
8391 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8392 {
8393         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8394         struct vcpu_vmx *vmx = to_vmx(vcpu);
8395         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8396
8397         if (vmx->nested.nested_run_pending)
8398                 return false;
8399
8400         if (unlikely(vmx->fail)) {
8401                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8402                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8403                 return true;
8404         }
8405
8406         /*
8407          * The host physical addresses of some pages of guest memory
8408          * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8409          * may write to these pages via their host physical address while
8410          * L2 is running, bypassing any address-translation-based dirty
8411          * tracking (e.g. EPT write protection).
8412          *
8413          * Mark them dirty on every exit from L2 to prevent them from
8414          * getting out of sync with dirty tracking.
8415          */
8416         nested_mark_vmcs12_pages_dirty(vcpu);
8417
8418         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8419                                 vmcs_readl(EXIT_QUALIFICATION),
8420                                 vmx->idt_vectoring_info,
8421                                 intr_info,
8422                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8423                                 KVM_ISA_VMX);
8424
8425         switch (exit_reason) {
8426         case EXIT_REASON_EXCEPTION_NMI:
8427                 if (is_nmi(intr_info))
8428                         return false;
8429                 else if (is_page_fault(intr_info))
8430                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8431                 else if (is_no_device(intr_info) &&
8432                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8433                         return false;
8434                 else if (is_debug(intr_info) &&
8435                          vcpu->guest_debug &
8436                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8437                         return false;
8438                 else if (is_breakpoint(intr_info) &&
8439                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8440                         return false;
8441                 return vmcs12->exception_bitmap &
8442                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8443         case EXIT_REASON_EXTERNAL_INTERRUPT:
8444                 return false;
8445         case EXIT_REASON_TRIPLE_FAULT:
8446                 return true;
8447         case EXIT_REASON_PENDING_INTERRUPT:
8448                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8449         case EXIT_REASON_NMI_WINDOW:
8450                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8451         case EXIT_REASON_TASK_SWITCH:
8452                 return true;
8453         case EXIT_REASON_CPUID:
8454                 return true;
8455         case EXIT_REASON_HLT:
8456                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8457         case EXIT_REASON_INVD:
8458                 return true;
8459         case EXIT_REASON_INVLPG:
8460                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8461         case EXIT_REASON_RDPMC:
8462                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8463         case EXIT_REASON_RDRAND:
8464                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
8465         case EXIT_REASON_RDSEED:
8466                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
8467         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8468                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8469         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8470         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8471         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8472         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8473         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8474         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8475                 /*
8476                  * VMX instructions trap unconditionally. This allows L1 to
8477                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8478                  */
8479                 return true;
8480         case EXIT_REASON_CR_ACCESS:
8481                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8482         case EXIT_REASON_DR_ACCESS:
8483                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8484         case EXIT_REASON_IO_INSTRUCTION:
8485                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8486         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8487                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8488         case EXIT_REASON_MSR_READ:
8489         case EXIT_REASON_MSR_WRITE:
8490                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8491         case EXIT_REASON_INVALID_STATE:
8492                 return true;
8493         case EXIT_REASON_MWAIT_INSTRUCTION:
8494                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8495         case EXIT_REASON_MONITOR_TRAP_FLAG:
8496                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8497         case EXIT_REASON_MONITOR_INSTRUCTION:
8498                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8499         case EXIT_REASON_PAUSE_INSTRUCTION:
8500                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8501                         nested_cpu_has2(vmcs12,
8502                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8503         case EXIT_REASON_MCE_DURING_VMENTRY:
8504                 return false;
8505         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8506                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8507         case EXIT_REASON_APIC_ACCESS:
8508                 return nested_cpu_has2(vmcs12,
8509                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8510         case EXIT_REASON_APIC_WRITE:
8511         case EXIT_REASON_EOI_INDUCED:
8512                 /* apic_write and eoi_induced should exit unconditionally. */
8513                 return true;
8514         case EXIT_REASON_EPT_VIOLATION:
8515                 /*
8516                  * L0 always deals with the EPT violation. If nested EPT is
8517                  * used, and the nested mmu code discovers that the address is
8518                  * missing in the guest EPT table (EPT12), the EPT violation
8519                  * will be injected with nested_ept_inject_page_fault()
8520                  */
8521                 return false;
8522         case EXIT_REASON_EPT_MISCONFIG:
8523                 /*
8524                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8525                  * table (shadow on EPT) or a merged EPT table that L0 built
8526                  * (EPT on EPT). So any problems with the structure of the
8527                  * table is L0's fault.
8528                  */
8529                 return false;
8530         case EXIT_REASON_INVPCID:
8531                 return
8532                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
8533                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8534         case EXIT_REASON_WBINVD:
8535                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8536         case EXIT_REASON_XSETBV:
8537                 return true;
8538         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8539                 /*
8540                  * This should never happen, since it is not possible to
8541                  * set XSS to a non-zero value---neither in L1 nor in L2.
8542                  * If if it were, XSS would have to be checked against
8543                  * the XSS exit bitmap in vmcs12.
8544                  */
8545                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8546         case EXIT_REASON_PREEMPTION_TIMER:
8547                 return false;
8548         case EXIT_REASON_PML_FULL:
8549                 /* We emulate PML support to L1. */
8550                 return false;
8551         case EXIT_REASON_VMFUNC:
8552                 /* VM functions are emulated through L2->L0 vmexits. */
8553                 return false;
8554         default:
8555                 return true;
8556         }
8557 }
8558
8559 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8560 {
8561         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8562
8563         /*
8564          * At this point, the exit interruption info in exit_intr_info
8565          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
8566          * we need to query the in-kernel LAPIC.
8567          */
8568         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8569         if ((exit_intr_info &
8570              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8571             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8572                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8573                 vmcs12->vm_exit_intr_error_code =
8574                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8575         }
8576
8577         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8578                           vmcs_readl(EXIT_QUALIFICATION));
8579         return 1;
8580 }
8581
8582 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8583 {
8584         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8585         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8586 }
8587
8588 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8589 {
8590         if (vmx->pml_pg) {
8591                 __free_page(vmx->pml_pg);
8592                 vmx->pml_pg = NULL;
8593         }
8594 }
8595
8596 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8597 {
8598         struct vcpu_vmx *vmx = to_vmx(vcpu);
8599         u64 *pml_buf;
8600         u16 pml_idx;
8601
8602         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8603
8604         /* Do nothing if PML buffer is empty */
8605         if (pml_idx == (PML_ENTITY_NUM - 1))
8606                 return;
8607
8608         /* PML index always points to next available PML buffer entity */
8609         if (pml_idx >= PML_ENTITY_NUM)
8610                 pml_idx = 0;
8611         else
8612                 pml_idx++;
8613
8614         pml_buf = page_address(vmx->pml_pg);
8615         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8616                 u64 gpa;
8617
8618                 gpa = pml_buf[pml_idx];
8619                 WARN_ON(gpa & (PAGE_SIZE - 1));
8620                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8621         }
8622
8623         /* reset PML index */
8624         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8625 }
8626
8627 /*
8628  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8629  * Called before reporting dirty_bitmap to userspace.
8630  */
8631 static void kvm_flush_pml_buffers(struct kvm *kvm)
8632 {
8633         int i;
8634         struct kvm_vcpu *vcpu;
8635         /*
8636          * We only need to kick vcpu out of guest mode here, as PML buffer
8637          * is flushed at beginning of all VMEXITs, and it's obvious that only
8638          * vcpus running in guest are possible to have unflushed GPAs in PML
8639          * buffer.
8640          */
8641         kvm_for_each_vcpu(i, vcpu, kvm)
8642                 kvm_vcpu_kick(vcpu);
8643 }
8644
8645 static void vmx_dump_sel(char *name, uint32_t sel)
8646 {
8647         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8648                name, vmcs_read16(sel),
8649                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8650                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8651                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8652 }
8653
8654 static void vmx_dump_dtsel(char *name, uint32_t limit)
8655 {
8656         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8657                name, vmcs_read32(limit),
8658                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8659 }
8660
8661 static void dump_vmcs(void)
8662 {
8663         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8664         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8665         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8666         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8667         u32 secondary_exec_control = 0;
8668         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8669         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8670         int i, n;
8671
8672         if (cpu_has_secondary_exec_ctrls())
8673                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8674
8675         pr_err("*** Guest State ***\n");
8676         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8677                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8678                vmcs_readl(CR0_GUEST_HOST_MASK));
8679         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8680                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8681         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8682         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8683             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8684         {
8685                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8686                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8687                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8688                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8689         }
8690         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8691                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8692         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8693                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8694         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8695                vmcs_readl(GUEST_SYSENTER_ESP),
8696                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8697         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8698         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8699         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8700         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8701         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8702         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8703         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8704         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8705         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8706         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8707         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8708             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8709                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8710                        efer, vmcs_read64(GUEST_IA32_PAT));
8711         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8712                vmcs_read64(GUEST_IA32_DEBUGCTL),
8713                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8714         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8715                 pr_err("PerfGlobCtl = 0x%016llx\n",
8716                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8717         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8718                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8719         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8720                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8721                vmcs_read32(GUEST_ACTIVITY_STATE));
8722         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8723                 pr_err("InterruptStatus = %04x\n",
8724                        vmcs_read16(GUEST_INTR_STATUS));
8725
8726         pr_err("*** Host State ***\n");
8727         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8728                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8729         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8730                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8731                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8732                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8733                vmcs_read16(HOST_TR_SELECTOR));
8734         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8735                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8736                vmcs_readl(HOST_TR_BASE));
8737         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8738                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8739         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8740                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8741                vmcs_readl(HOST_CR4));
8742         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8743                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8744                vmcs_read32(HOST_IA32_SYSENTER_CS),
8745                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8746         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8747                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8748                        vmcs_read64(HOST_IA32_EFER),
8749                        vmcs_read64(HOST_IA32_PAT));
8750         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8751                 pr_err("PerfGlobCtl = 0x%016llx\n",
8752                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8753
8754         pr_err("*** Control State ***\n");
8755         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8756                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8757         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8758         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8759                vmcs_read32(EXCEPTION_BITMAP),
8760                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8761                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8762         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8763                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8764                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8765                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8766         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8767                vmcs_read32(VM_EXIT_INTR_INFO),
8768                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8769                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8770         pr_err("        reason=%08x qualification=%016lx\n",
8771                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8772         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8773                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8774                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8775         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8776         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8777                 pr_err("TSC Multiplier = 0x%016llx\n",
8778                        vmcs_read64(TSC_MULTIPLIER));
8779         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8780                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8781         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8782                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8783         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8784                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8785         n = vmcs_read32(CR3_TARGET_COUNT);
8786         for (i = 0; i + 1 < n; i += 4)
8787                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8788                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8789                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8790         if (i < n)
8791                 pr_err("CR3 target%u=%016lx\n",
8792                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8793         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8794                 pr_err("PLE Gap=%08x Window=%08x\n",
8795                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8796         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8797                 pr_err("Virtual processor ID = 0x%04x\n",
8798                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8799 }
8800
8801 /*
8802  * The guest has exited.  See if we can fix it or if we need userspace
8803  * assistance.
8804  */
8805 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8806 {
8807         struct vcpu_vmx *vmx = to_vmx(vcpu);
8808         u32 exit_reason = vmx->exit_reason;
8809         u32 vectoring_info = vmx->idt_vectoring_info;
8810
8811         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8812
8813         /*
8814          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8815          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8816          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8817          * mode as if vcpus is in root mode, the PML buffer must has been
8818          * flushed already.
8819          */
8820         if (enable_pml)
8821                 vmx_flush_pml_buffer(vcpu);
8822
8823         /* If guest state is invalid, start emulating */
8824         if (vmx->emulation_required)
8825                 return handle_invalid_guest_state(vcpu);
8826
8827         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
8828                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
8829
8830         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8831                 dump_vmcs();
8832                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8833                 vcpu->run->fail_entry.hardware_entry_failure_reason
8834                         = exit_reason;
8835                 return 0;
8836         }
8837
8838         if (unlikely(vmx->fail)) {
8839                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8840                 vcpu->run->fail_entry.hardware_entry_failure_reason
8841                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8842                 return 0;
8843         }
8844
8845         /*
8846          * Note:
8847          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8848          * delivery event since it indicates guest is accessing MMIO.
8849          * The vm-exit can be triggered again after return to guest that
8850          * will cause infinite loop.
8851          */
8852         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8853                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8854                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8855                         exit_reason != EXIT_REASON_PML_FULL &&
8856                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8857                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8858                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8859                 vcpu->run->internal.ndata = 3;
8860                 vcpu->run->internal.data[0] = vectoring_info;
8861                 vcpu->run->internal.data[1] = exit_reason;
8862                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8863                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8864                         vcpu->run->internal.ndata++;
8865                         vcpu->run->internal.data[3] =
8866                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8867                 }
8868                 return 0;
8869         }
8870
8871         if (unlikely(!enable_vnmi &&
8872                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
8873                 if (vmx_interrupt_allowed(vcpu)) {
8874                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
8875                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
8876                            vcpu->arch.nmi_pending) {
8877                         /*
8878                          * This CPU don't support us in finding the end of an
8879                          * NMI-blocked window if the guest runs with IRQs
8880                          * disabled. So we pull the trigger after 1 s of
8881                          * futile waiting, but inform the user about this.
8882                          */
8883                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8884                                "state on VCPU %d after 1 s timeout\n",
8885                                __func__, vcpu->vcpu_id);
8886                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
8887                 }
8888         }
8889
8890         if (exit_reason < kvm_vmx_max_exit_handlers
8891             && kvm_vmx_exit_handlers[exit_reason])
8892                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8893         else {
8894                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8895                                 exit_reason);
8896                 kvm_queue_exception(vcpu, UD_VECTOR);
8897                 return 1;
8898         }
8899 }
8900
8901 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8902 {
8903         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8904
8905         if (is_guest_mode(vcpu) &&
8906                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8907                 return;
8908
8909         if (irr == -1 || tpr < irr) {
8910                 vmcs_write32(TPR_THRESHOLD, 0);
8911                 return;
8912         }
8913
8914         vmcs_write32(TPR_THRESHOLD, irr);
8915 }
8916
8917 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8918 {
8919         u32 sec_exec_control;
8920
8921         /* Postpone execution until vmcs01 is the current VMCS. */
8922         if (is_guest_mode(vcpu)) {
8923                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8924                 return;
8925         }
8926
8927         if (!cpu_has_vmx_virtualize_x2apic_mode())
8928                 return;
8929
8930         if (!cpu_need_tpr_shadow(vcpu))
8931                 return;
8932
8933         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8934
8935         if (set) {
8936                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8937                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8938         } else {
8939                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8940                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8941                 vmx_flush_tlb_ept_only(vcpu);
8942         }
8943         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8944
8945         vmx_set_msr_bitmap(vcpu);
8946 }
8947
8948 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8949 {
8950         struct vcpu_vmx *vmx = to_vmx(vcpu);
8951
8952         /*
8953          * Currently we do not handle the nested case where L2 has an
8954          * APIC access page of its own; that page is still pinned.
8955          * Hence, we skip the case where the VCPU is in guest mode _and_
8956          * L1 prepared an APIC access page for L2.
8957          *
8958          * For the case where L1 and L2 share the same APIC access page
8959          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8960          * in the vmcs12), this function will only update either the vmcs01
8961          * or the vmcs02.  If the former, the vmcs02 will be updated by
8962          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8963          * the next L2->L1 exit.
8964          */
8965         if (!is_guest_mode(vcpu) ||
8966             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8967                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8968                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8969                 vmx_flush_tlb_ept_only(vcpu);
8970         }
8971 }
8972
8973 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8974 {
8975         u16 status;
8976         u8 old;
8977
8978         if (max_isr == -1)
8979                 max_isr = 0;
8980
8981         status = vmcs_read16(GUEST_INTR_STATUS);
8982         old = status >> 8;
8983         if (max_isr != old) {
8984                 status &= 0xff;
8985                 status |= max_isr << 8;
8986                 vmcs_write16(GUEST_INTR_STATUS, status);
8987         }
8988 }
8989
8990 static void vmx_set_rvi(int vector)
8991 {
8992         u16 status;
8993         u8 old;
8994
8995         if (vector == -1)
8996                 vector = 0;
8997
8998         status = vmcs_read16(GUEST_INTR_STATUS);
8999         old = (u8)status & 0xff;
9000         if ((u8)vector != old) {
9001                 status &= ~0xff;
9002                 status |= (u8)vector;
9003                 vmcs_write16(GUEST_INTR_STATUS, status);
9004         }
9005 }
9006
9007 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
9008 {
9009         if (!is_guest_mode(vcpu)) {
9010                 vmx_set_rvi(max_irr);
9011                 return;
9012         }
9013
9014         if (max_irr == -1)
9015                 return;
9016
9017         /*
9018          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
9019          * handles it.
9020          */
9021         if (nested_exit_on_intr(vcpu))
9022                 return;
9023
9024         /*
9025          * Else, fall back to pre-APICv interrupt injection since L2
9026          * is run without virtual interrupt delivery.
9027          */
9028         if (!kvm_event_needs_reinjection(vcpu) &&
9029             vmx_interrupt_allowed(vcpu)) {
9030                 kvm_queue_interrupt(vcpu, max_irr, false);
9031                 vmx_inject_irq(vcpu);
9032         }
9033 }
9034
9035 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
9036 {
9037         struct vcpu_vmx *vmx = to_vmx(vcpu);
9038         int max_irr;
9039
9040         WARN_ON(!vcpu->arch.apicv_active);
9041         if (pi_test_on(&vmx->pi_desc)) {
9042                 pi_clear_on(&vmx->pi_desc);
9043                 /*
9044                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9045                  * But on x86 this is just a compiler barrier anyway.
9046                  */
9047                 smp_mb__after_atomic();
9048                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
9049         } else {
9050                 max_irr = kvm_lapic_find_highest_irr(vcpu);
9051         }
9052         vmx_hwapic_irr_update(vcpu, max_irr);
9053         return max_irr;
9054 }
9055
9056 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
9057 {
9058         if (!kvm_vcpu_apicv_active(vcpu))
9059                 return;
9060
9061         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9062         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9063         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9064         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9065 }
9066
9067 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9068 {
9069         struct vcpu_vmx *vmx = to_vmx(vcpu);
9070
9071         pi_clear_on(&vmx->pi_desc);
9072         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9073 }
9074
9075 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9076 {
9077         u32 exit_intr_info = 0;
9078         u16 basic_exit_reason = (u16)vmx->exit_reason;
9079
9080         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9081               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9082                 return;
9083
9084         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9085                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9086         vmx->exit_intr_info = exit_intr_info;
9087
9088         /* if exit due to PF check for async PF */
9089         if (is_page_fault(exit_intr_info))
9090                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9091
9092         /* Handle machine checks before interrupts are enabled */
9093         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9094             is_machine_check(exit_intr_info))
9095                 kvm_machine_check();
9096
9097         /* We need to handle NMIs before interrupts are enabled */
9098         if (is_nmi(exit_intr_info)) {
9099                 kvm_before_handle_nmi(&vmx->vcpu);
9100                 asm("int $2");
9101                 kvm_after_handle_nmi(&vmx->vcpu);
9102         }
9103 }
9104
9105 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9106 {
9107         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9108
9109         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9110                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9111                 unsigned int vector;
9112                 unsigned long entry;
9113                 gate_desc *desc;
9114                 struct vcpu_vmx *vmx = to_vmx(vcpu);
9115 #ifdef CONFIG_X86_64
9116                 unsigned long tmp;
9117 #endif
9118
9119                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
9120                 desc = (gate_desc *)vmx->host_idt_base + vector;
9121                 entry = gate_offset(desc);
9122                 asm volatile(
9123 #ifdef CONFIG_X86_64
9124                         "mov %%" _ASM_SP ", %[sp]\n\t"
9125                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9126                         "push $%c[ss]\n\t"
9127                         "push %[sp]\n\t"
9128 #endif
9129                         "pushf\n\t"
9130                         __ASM_SIZE(push) " $%c[cs]\n\t"
9131                         "call *%[entry]\n\t"
9132                         :
9133 #ifdef CONFIG_X86_64
9134                         [sp]"=&r"(tmp),
9135 #endif
9136                         ASM_CALL_CONSTRAINT
9137                         :
9138                         [entry]"r"(entry),
9139                         [ss]"i"(__KERNEL_DS),
9140                         [cs]"i"(__KERNEL_CS)
9141                         );
9142         }
9143 }
9144 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9145
9146 static bool vmx_has_high_real_mode_segbase(void)
9147 {
9148         return enable_unrestricted_guest || emulate_invalid_guest_state;
9149 }
9150
9151 static bool vmx_mpx_supported(void)
9152 {
9153         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9154                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9155 }
9156
9157 static bool vmx_xsaves_supported(void)
9158 {
9159         return vmcs_config.cpu_based_2nd_exec_ctrl &
9160                 SECONDARY_EXEC_XSAVES;
9161 }
9162
9163 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9164 {
9165         u32 exit_intr_info;
9166         bool unblock_nmi;
9167         u8 vector;
9168         bool idtv_info_valid;
9169
9170         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9171
9172         if (enable_vnmi) {
9173                 if (vmx->loaded_vmcs->nmi_known_unmasked)
9174                         return;
9175                 /*
9176                  * Can't use vmx->exit_intr_info since we're not sure what
9177                  * the exit reason is.
9178                  */
9179                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9180                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9181                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9182                 /*
9183                  * SDM 3: 27.7.1.2 (September 2008)
9184                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
9185                  * a guest IRET fault.
9186                  * SDM 3: 23.2.2 (September 2008)
9187                  * Bit 12 is undefined in any of the following cases:
9188                  *  If the VM exit sets the valid bit in the IDT-vectoring
9189                  *   information field.
9190                  *  If the VM exit is due to a double fault.
9191                  */
9192                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9193                     vector != DF_VECTOR && !idtv_info_valid)
9194                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9195                                       GUEST_INTR_STATE_NMI);
9196                 else
9197                         vmx->loaded_vmcs->nmi_known_unmasked =
9198                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9199                                   & GUEST_INTR_STATE_NMI);
9200         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
9201                 vmx->loaded_vmcs->vnmi_blocked_time +=
9202                         ktime_to_ns(ktime_sub(ktime_get(),
9203                                               vmx->loaded_vmcs->entry_time));
9204 }
9205
9206 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9207                                       u32 idt_vectoring_info,
9208                                       int instr_len_field,
9209                                       int error_code_field)
9210 {
9211         u8 vector;
9212         int type;
9213         bool idtv_info_valid;
9214
9215         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9216
9217         vcpu->arch.nmi_injected = false;
9218         kvm_clear_exception_queue(vcpu);
9219         kvm_clear_interrupt_queue(vcpu);
9220
9221         if (!idtv_info_valid)
9222                 return;
9223
9224         kvm_make_request(KVM_REQ_EVENT, vcpu);
9225
9226         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9227         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9228
9229         switch (type) {
9230         case INTR_TYPE_NMI_INTR:
9231                 vcpu->arch.nmi_injected = true;
9232                 /*
9233                  * SDM 3: 27.7.1.2 (September 2008)
9234                  * Clear bit "block by NMI" before VM entry if a NMI
9235                  * delivery faulted.
9236                  */
9237                 vmx_set_nmi_mask(vcpu, false);
9238                 break;
9239         case INTR_TYPE_SOFT_EXCEPTION:
9240                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9241                 /* fall through */
9242         case INTR_TYPE_HARD_EXCEPTION:
9243                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9244                         u32 err = vmcs_read32(error_code_field);
9245                         kvm_requeue_exception_e(vcpu, vector, err);
9246                 } else
9247                         kvm_requeue_exception(vcpu, vector);
9248                 break;
9249         case INTR_TYPE_SOFT_INTR:
9250                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9251                 /* fall through */
9252         case INTR_TYPE_EXT_INTR:
9253                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9254                 break;
9255         default:
9256                 break;
9257         }
9258 }
9259
9260 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9261 {
9262         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9263                                   VM_EXIT_INSTRUCTION_LEN,
9264                                   IDT_VECTORING_ERROR_CODE);
9265 }
9266
9267 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9268 {
9269         __vmx_complete_interrupts(vcpu,
9270                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9271                                   VM_ENTRY_INSTRUCTION_LEN,
9272                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
9273
9274         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9275 }
9276
9277 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9278 {
9279         int i, nr_msrs;
9280         struct perf_guest_switch_msr *msrs;
9281
9282         msrs = perf_guest_get_msrs(&nr_msrs);
9283
9284         if (!msrs)
9285                 return;
9286
9287         for (i = 0; i < nr_msrs; i++)
9288                 if (msrs[i].host == msrs[i].guest)
9289                         clear_atomic_switch_msr(vmx, msrs[i].msr);
9290                 else
9291                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9292                                         msrs[i].host);
9293 }
9294
9295 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9296 {
9297         struct vcpu_vmx *vmx = to_vmx(vcpu);
9298         u64 tscl;
9299         u32 delta_tsc;
9300
9301         if (vmx->hv_deadline_tsc == -1)
9302                 return;
9303
9304         tscl = rdtsc();
9305         if (vmx->hv_deadline_tsc > tscl)
9306                 /* sure to be 32 bit only because checked on set_hv_timer */
9307                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9308                         cpu_preemption_timer_multi);
9309         else
9310                 delta_tsc = 0;
9311
9312         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9313 }
9314
9315 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9316 {
9317         struct vcpu_vmx *vmx = to_vmx(vcpu);
9318         unsigned long debugctlmsr, cr3, cr4;
9319
9320         /* Record the guest's net vcpu time for enforced NMI injections. */
9321         if (unlikely(!enable_vnmi &&
9322                      vmx->loaded_vmcs->soft_vnmi_blocked))
9323                 vmx->loaded_vmcs->entry_time = ktime_get();
9324
9325         /* Don't enter VMX if guest state is invalid, let the exit handler
9326            start emulation until we arrive back to a valid state */
9327         if (vmx->emulation_required)
9328                 return;
9329
9330         if (vmx->ple_window_dirty) {
9331                 vmx->ple_window_dirty = false;
9332                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9333         }
9334
9335         if (vmx->nested.sync_shadow_vmcs) {
9336                 copy_vmcs12_to_shadow(vmx);
9337                 vmx->nested.sync_shadow_vmcs = false;
9338         }
9339
9340         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9341                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9342         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9343                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9344
9345         cr3 = __get_current_cr3_fast();
9346         if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9347                 vmcs_writel(HOST_CR3, cr3);
9348                 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9349         }
9350
9351         cr4 = cr4_read_shadow();
9352         if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9353                 vmcs_writel(HOST_CR4, cr4);
9354                 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9355         }
9356
9357         /* When single-stepping over STI and MOV SS, we must clear the
9358          * corresponding interruptibility bits in the guest state. Otherwise
9359          * vmentry fails as it then expects bit 14 (BS) in pending debug
9360          * exceptions being set, but that's not correct for the guest debugging
9361          * case. */
9362         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9363                 vmx_set_interrupt_shadow(vcpu, 0);
9364
9365         if (static_cpu_has(X86_FEATURE_PKU) &&
9366             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9367             vcpu->arch.pkru != vmx->host_pkru)
9368                 __write_pkru(vcpu->arch.pkru);
9369
9370         atomic_switch_perf_msrs(vmx);
9371         debugctlmsr = get_debugctlmsr();
9372
9373         vmx_arm_hv_timer(vcpu);
9374
9375         vmx->__launched = vmx->loaded_vmcs->launched;
9376         asm(
9377                 /* Store host registers */
9378                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9379                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9380                 "push %%" _ASM_CX " \n\t"
9381                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9382                 "je 1f \n\t"
9383                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9384                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9385                 "1: \n\t"
9386                 /* Reload cr2 if changed */
9387                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9388                 "mov %%cr2, %%" _ASM_DX " \n\t"
9389                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9390                 "je 2f \n\t"
9391                 "mov %%" _ASM_AX", %%cr2 \n\t"
9392                 "2: \n\t"
9393                 /* Check if vmlaunch of vmresume is needed */
9394                 "cmpl $0, %c[launched](%0) \n\t"
9395                 /* Load guest registers.  Don't clobber flags. */
9396                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9397                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9398                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9399                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9400                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9401                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9402 #ifdef CONFIG_X86_64
9403                 "mov %c[r8](%0),  %%r8  \n\t"
9404                 "mov %c[r9](%0),  %%r9  \n\t"
9405                 "mov %c[r10](%0), %%r10 \n\t"
9406                 "mov %c[r11](%0), %%r11 \n\t"
9407                 "mov %c[r12](%0), %%r12 \n\t"
9408                 "mov %c[r13](%0), %%r13 \n\t"
9409                 "mov %c[r14](%0), %%r14 \n\t"
9410                 "mov %c[r15](%0), %%r15 \n\t"
9411 #endif
9412                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9413
9414                 /* Enter guest mode */
9415                 "jne 1f \n\t"
9416                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9417                 "jmp 2f \n\t"
9418                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9419                 "2: "
9420                 /* Save guest registers, load host registers, keep flags */
9421                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9422                 "pop %0 \n\t"
9423                 "setbe %c[fail](%0)\n\t"
9424                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9425                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9426                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9427                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9428                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9429                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9430                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9431 #ifdef CONFIG_X86_64
9432                 "mov %%r8,  %c[r8](%0) \n\t"
9433                 "mov %%r9,  %c[r9](%0) \n\t"
9434                 "mov %%r10, %c[r10](%0) \n\t"
9435                 "mov %%r11, %c[r11](%0) \n\t"
9436                 "mov %%r12, %c[r12](%0) \n\t"
9437                 "mov %%r13, %c[r13](%0) \n\t"
9438                 "mov %%r14, %c[r14](%0) \n\t"
9439                 "mov %%r15, %c[r15](%0) \n\t"
9440                 "xor %%r8d,  %%r8d \n\t"
9441                 "xor %%r9d,  %%r9d \n\t"
9442                 "xor %%r10d, %%r10d \n\t"
9443                 "xor %%r11d, %%r11d \n\t"
9444                 "xor %%r12d, %%r12d \n\t"
9445                 "xor %%r13d, %%r13d \n\t"
9446                 "xor %%r14d, %%r14d \n\t"
9447                 "xor %%r15d, %%r15d \n\t"
9448 #endif
9449                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9450                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9451
9452                 "xor %%eax, %%eax \n\t"
9453                 "xor %%ebx, %%ebx \n\t"
9454                 "xor %%esi, %%esi \n\t"
9455                 "xor %%edi, %%edi \n\t"
9456                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9457                 ".pushsection .rodata \n\t"
9458                 ".global vmx_return \n\t"
9459                 "vmx_return: " _ASM_PTR " 2b \n\t"
9460                 ".popsection"
9461               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9462                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9463                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9464                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9465                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9466                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9467                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9468                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9469                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9470                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9471                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9472 #ifdef CONFIG_X86_64
9473                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9474                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9475                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9476                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9477                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9478                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9479                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9480                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9481 #endif
9482                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9483                 [wordsize]"i"(sizeof(ulong))
9484               : "cc", "memory"
9485 #ifdef CONFIG_X86_64
9486                 , "rax", "rbx", "rdi", "rsi"
9487                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9488 #else
9489                 , "eax", "ebx", "edi", "esi"
9490 #endif
9491               );
9492
9493         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9494         if (debugctlmsr)
9495                 update_debugctlmsr(debugctlmsr);
9496
9497 #ifndef CONFIG_X86_64
9498         /*
9499          * The sysexit path does not restore ds/es, so we must set them to
9500          * a reasonable value ourselves.
9501          *
9502          * We can't defer this to vmx_load_host_state() since that function
9503          * may be executed in interrupt context, which saves and restore segments
9504          * around it, nullifying its effect.
9505          */
9506         loadsegment(ds, __USER_DS);
9507         loadsegment(es, __USER_DS);
9508 #endif
9509
9510         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9511                                   | (1 << VCPU_EXREG_RFLAGS)
9512                                   | (1 << VCPU_EXREG_PDPTR)
9513                                   | (1 << VCPU_EXREG_SEGMENTS)
9514                                   | (1 << VCPU_EXREG_CR3));
9515         vcpu->arch.regs_dirty = 0;
9516
9517         /*
9518          * eager fpu is enabled if PKEY is supported and CR4 is switched
9519          * back on host, so it is safe to read guest PKRU from current
9520          * XSAVE.
9521          */
9522         if (static_cpu_has(X86_FEATURE_PKU) &&
9523             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
9524                 vcpu->arch.pkru = __read_pkru();
9525                 if (vcpu->arch.pkru != vmx->host_pkru)
9526                         __write_pkru(vmx->host_pkru);
9527         }
9528
9529         /*
9530          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9531          * we did not inject a still-pending event to L1 now because of
9532          * nested_run_pending, we need to re-enable this bit.
9533          */
9534         if (vmx->nested.nested_run_pending)
9535                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9536
9537         vmx->nested.nested_run_pending = 0;
9538         vmx->idt_vectoring_info = 0;
9539
9540         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
9541         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9542                 return;
9543
9544         vmx->loaded_vmcs->launched = 1;
9545         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9546
9547         vmx_complete_atomic_exit(vmx);
9548         vmx_recover_nmi_blocking(vmx);
9549         vmx_complete_interrupts(vmx);
9550 }
9551 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9552
9553 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9554 {
9555         struct vcpu_vmx *vmx = to_vmx(vcpu);
9556         int cpu;
9557
9558         if (vmx->loaded_vmcs == vmcs)
9559                 return;
9560
9561         cpu = get_cpu();
9562         vmx->loaded_vmcs = vmcs;
9563         vmx_vcpu_put(vcpu);
9564         vmx_vcpu_load(vcpu, cpu);
9565         put_cpu();
9566 }
9567
9568 /*
9569  * Ensure that the current vmcs of the logical processor is the
9570  * vmcs01 of the vcpu before calling free_nested().
9571  */
9572 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9573 {
9574        struct vcpu_vmx *vmx = to_vmx(vcpu);
9575        int r;
9576
9577        r = vcpu_load(vcpu);
9578        BUG_ON(r);
9579        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9580        free_nested(vmx);
9581        vcpu_put(vcpu);
9582 }
9583
9584 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9585 {
9586         struct vcpu_vmx *vmx = to_vmx(vcpu);
9587
9588         if (enable_pml)
9589                 vmx_destroy_pml_buffer(vmx);
9590         free_vpid(vmx->vpid);
9591         leave_guest_mode(vcpu);
9592         vmx_free_vcpu_nested(vcpu);
9593         free_loaded_vmcs(vmx->loaded_vmcs);
9594         kfree(vmx->guest_msrs);
9595         kvm_vcpu_uninit(vcpu);
9596         kmem_cache_free(kvm_vcpu_cache, vmx);
9597 }
9598
9599 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9600 {
9601         int err;
9602         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9603         int cpu;
9604
9605         if (!vmx)
9606                 return ERR_PTR(-ENOMEM);
9607
9608         vmx->vpid = allocate_vpid();
9609
9610         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9611         if (err)
9612                 goto free_vcpu;
9613
9614         err = -ENOMEM;
9615
9616         /*
9617          * If PML is turned on, failure on enabling PML just results in failure
9618          * of creating the vcpu, therefore we can simplify PML logic (by
9619          * avoiding dealing with cases, such as enabling PML partially on vcpus
9620          * for the guest, etc.
9621          */
9622         if (enable_pml) {
9623                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9624                 if (!vmx->pml_pg)
9625                         goto uninit_vcpu;
9626         }
9627
9628         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9629         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9630                      > PAGE_SIZE);
9631
9632         if (!vmx->guest_msrs)
9633                 goto free_pml;
9634
9635         vmx->loaded_vmcs = &vmx->vmcs01;
9636         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9637         vmx->loaded_vmcs->shadow_vmcs = NULL;
9638         if (!vmx->loaded_vmcs->vmcs)
9639                 goto free_msrs;
9640         loaded_vmcs_init(vmx->loaded_vmcs);
9641
9642         cpu = get_cpu();
9643         vmx_vcpu_load(&vmx->vcpu, cpu);
9644         vmx->vcpu.cpu = cpu;
9645         vmx_vcpu_setup(vmx);
9646         vmx_vcpu_put(&vmx->vcpu);
9647         put_cpu();
9648         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9649                 err = alloc_apic_access_page(kvm);
9650                 if (err)
9651                         goto free_vmcs;
9652         }
9653
9654         if (enable_ept) {
9655                 err = init_rmode_identity_map(kvm);
9656                 if (err)
9657                         goto free_vmcs;
9658         }
9659
9660         if (nested) {
9661                 nested_vmx_setup_ctls_msrs(vmx);
9662                 vmx->nested.vpid02 = allocate_vpid();
9663         }
9664
9665         vmx->nested.posted_intr_nv = -1;
9666         vmx->nested.current_vmptr = -1ull;
9667
9668         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9669
9670         /*
9671          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9672          * or POSTED_INTR_WAKEUP_VECTOR.
9673          */
9674         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
9675         vmx->pi_desc.sn = 1;
9676
9677         return &vmx->vcpu;
9678
9679 free_vmcs:
9680         free_vpid(vmx->nested.vpid02);
9681         free_loaded_vmcs(vmx->loaded_vmcs);
9682 free_msrs:
9683         kfree(vmx->guest_msrs);
9684 free_pml:
9685         vmx_destroy_pml_buffer(vmx);
9686 uninit_vcpu:
9687         kvm_vcpu_uninit(&vmx->vcpu);
9688 free_vcpu:
9689         free_vpid(vmx->vpid);
9690         kmem_cache_free(kvm_vcpu_cache, vmx);
9691         return ERR_PTR(err);
9692 }
9693
9694 static void __init vmx_check_processor_compat(void *rtn)
9695 {
9696         struct vmcs_config vmcs_conf;
9697
9698         *(int *)rtn = 0;
9699         if (setup_vmcs_config(&vmcs_conf) < 0)
9700                 *(int *)rtn = -EIO;
9701         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9702                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9703                                 smp_processor_id());
9704                 *(int *)rtn = -EIO;
9705         }
9706 }
9707
9708 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9709 {
9710         u8 cache;
9711         u64 ipat = 0;
9712
9713         /* For VT-d and EPT combination
9714          * 1. MMIO: always map as UC
9715          * 2. EPT with VT-d:
9716          *   a. VT-d without snooping control feature: can't guarantee the
9717          *      result, try to trust guest.
9718          *   b. VT-d with snooping control feature: snooping control feature of
9719          *      VT-d engine can guarantee the cache correctness. Just set it
9720          *      to WB to keep consistent with host. So the same as item 3.
9721          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9722          *    consistent with host MTRR
9723          */
9724         if (is_mmio) {
9725                 cache = MTRR_TYPE_UNCACHABLE;
9726                 goto exit;
9727         }
9728
9729         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9730                 ipat = VMX_EPT_IPAT_BIT;
9731                 cache = MTRR_TYPE_WRBACK;
9732                 goto exit;
9733         }
9734
9735         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9736                 ipat = VMX_EPT_IPAT_BIT;
9737                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9738                         cache = MTRR_TYPE_WRBACK;
9739                 else
9740                         cache = MTRR_TYPE_UNCACHABLE;
9741                 goto exit;
9742         }
9743
9744         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9745
9746 exit:
9747         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9748 }
9749
9750 static int vmx_get_lpage_level(void)
9751 {
9752         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9753                 return PT_DIRECTORY_LEVEL;
9754         else
9755                 /* For shadow and EPT supported 1GB page */
9756                 return PT_PDPE_LEVEL;
9757 }
9758
9759 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9760 {
9761         /*
9762          * These bits in the secondary execution controls field
9763          * are dynamic, the others are mostly based on the hypervisor
9764          * architecture and the guest's CPUID.  Do not touch the
9765          * dynamic bits.
9766          */
9767         u32 mask =
9768                 SECONDARY_EXEC_SHADOW_VMCS |
9769                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9770                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9771
9772         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9773
9774         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9775                      (new_ctl & ~mask) | (cur_ctl & mask));
9776 }
9777
9778 /*
9779  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9780  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9781  */
9782 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9783 {
9784         struct vcpu_vmx *vmx = to_vmx(vcpu);
9785         struct kvm_cpuid_entry2 *entry;
9786
9787         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9788         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9789
9790 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9791         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9792                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9793 } while (0)
9794
9795         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9796         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9797         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9798         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9799         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9800         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9801         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9802         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9803         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9804         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9805         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9806         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9807         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9808         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9809         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9810
9811         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9812         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9813         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9814         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9815         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9816         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
9817
9818 #undef cr4_fixed1_update
9819 }
9820
9821 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9822 {
9823         struct vcpu_vmx *vmx = to_vmx(vcpu);
9824
9825         if (cpu_has_secondary_exec_ctrls()) {
9826                 vmx_compute_secondary_exec_control(vmx);
9827                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
9828         }
9829
9830         if (nested_vmx_allowed(vcpu))
9831                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9832                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9833         else
9834                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9835                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9836
9837         if (nested_vmx_allowed(vcpu))
9838                 nested_vmx_cr_fixed1_bits_update(vcpu);
9839 }
9840
9841 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9842 {
9843         if (func == 1 && nested)
9844                 entry->ecx |= bit(X86_FEATURE_VMX);
9845 }
9846
9847 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9848                 struct x86_exception *fault)
9849 {
9850         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9851         struct vcpu_vmx *vmx = to_vmx(vcpu);
9852         u32 exit_reason;
9853         unsigned long exit_qualification = vcpu->arch.exit_qualification;
9854
9855         if (vmx->nested.pml_full) {
9856                 exit_reason = EXIT_REASON_PML_FULL;
9857                 vmx->nested.pml_full = false;
9858                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9859         } else if (fault->error_code & PFERR_RSVD_MASK)
9860                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9861         else
9862                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9863
9864         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9865         vmcs12->guest_physical_address = fault->address;
9866 }
9867
9868 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9869 {
9870         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
9871 }
9872
9873 /* Callbacks for nested_ept_init_mmu_context: */
9874
9875 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9876 {
9877         /* return the page table to be shadowed - in our case, EPT12 */
9878         return get_vmcs12(vcpu)->ept_pointer;
9879 }
9880
9881 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9882 {
9883         WARN_ON(mmu_is_nested(vcpu));
9884         if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
9885                 return 1;
9886
9887         kvm_mmu_unload(vcpu);
9888         kvm_init_shadow_ept_mmu(vcpu,
9889                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9890                         VMX_EPT_EXECUTE_ONLY_BIT,
9891                         nested_ept_ad_enabled(vcpu));
9892         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9893         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9894         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9895
9896         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9897         return 0;
9898 }
9899
9900 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9901 {
9902         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9903 }
9904
9905 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9906                                             u16 error_code)
9907 {
9908         bool inequality, bit;
9909
9910         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9911         inequality =
9912                 (error_code & vmcs12->page_fault_error_code_mask) !=
9913                  vmcs12->page_fault_error_code_match;
9914         return inequality ^ bit;
9915 }
9916
9917 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9918                 struct x86_exception *fault)
9919 {
9920         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9921
9922         WARN_ON(!is_guest_mode(vcpu));
9923
9924         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
9925                 !to_vmx(vcpu)->nested.nested_run_pending) {
9926                 vmcs12->vm_exit_intr_error_code = fault->error_code;
9927                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9928                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
9929                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
9930                                   fault->address);
9931         } else {
9932                 kvm_inject_page_fault(vcpu, fault);
9933         }
9934 }
9935
9936 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9937                                                struct vmcs12 *vmcs12);
9938
9939 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9940                                         struct vmcs12 *vmcs12)
9941 {
9942         struct vcpu_vmx *vmx = to_vmx(vcpu);
9943         struct page *page;
9944         u64 hpa;
9945
9946         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9947                 /*
9948                  * Translate L1 physical address to host physical
9949                  * address for vmcs02. Keep the page pinned, so this
9950                  * physical address remains valid. We keep a reference
9951                  * to it so we can release it later.
9952                  */
9953                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
9954                         kvm_release_page_dirty(vmx->nested.apic_access_page);
9955                         vmx->nested.apic_access_page = NULL;
9956                 }
9957                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
9958                 /*
9959                  * If translation failed, no matter: This feature asks
9960                  * to exit when accessing the given address, and if it
9961                  * can never be accessed, this feature won't do
9962                  * anything anyway.
9963                  */
9964                 if (!is_error_page(page)) {
9965                         vmx->nested.apic_access_page = page;
9966                         hpa = page_to_phys(vmx->nested.apic_access_page);
9967                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9968                 } else {
9969                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9970                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9971                 }
9972         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9973                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9974                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9975                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9976                 kvm_vcpu_reload_apic_access_page(vcpu);
9977         }
9978
9979         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9980                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
9981                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
9982                         vmx->nested.virtual_apic_page = NULL;
9983                 }
9984                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
9985
9986                 /*
9987                  * If translation failed, VM entry will fail because
9988                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9989                  * Failing the vm entry is _not_ what the processor
9990                  * does but it's basically the only possibility we
9991                  * have.  We could still enter the guest if CR8 load
9992                  * exits are enabled, CR8 store exits are enabled, and
9993                  * virtualize APIC access is disabled; in this case
9994                  * the processor would never use the TPR shadow and we
9995                  * could simply clear the bit from the execution
9996                  * control.  But such a configuration is useless, so
9997                  * let's keep the code simple.
9998                  */
9999                 if (!is_error_page(page)) {
10000                         vmx->nested.virtual_apic_page = page;
10001                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
10002                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
10003                 }
10004         }
10005
10006         if (nested_cpu_has_posted_intr(vmcs12)) {
10007                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
10008                         kunmap(vmx->nested.pi_desc_page);
10009                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
10010                         vmx->nested.pi_desc_page = NULL;
10011                 }
10012                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
10013                 if (is_error_page(page))
10014                         return;
10015                 vmx->nested.pi_desc_page = page;
10016                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
10017                 vmx->nested.pi_desc =
10018                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
10019                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10020                         (PAGE_SIZE - 1)));
10021                 vmcs_write64(POSTED_INTR_DESC_ADDR,
10022                         page_to_phys(vmx->nested.pi_desc_page) +
10023                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10024                         (PAGE_SIZE - 1)));
10025         }
10026         if (cpu_has_vmx_msr_bitmap() &&
10027             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
10028             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
10029                 ;
10030         else
10031                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
10032                                 CPU_BASED_USE_MSR_BITMAPS);
10033 }
10034
10035 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
10036 {
10037         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
10038         struct vcpu_vmx *vmx = to_vmx(vcpu);
10039
10040         if (vcpu->arch.virtual_tsc_khz == 0)
10041                 return;
10042
10043         /* Make sure short timeouts reliably trigger an immediate vmexit.
10044          * hrtimer_start does not guarantee this. */
10045         if (preemption_timeout <= 1) {
10046                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
10047                 return;
10048         }
10049
10050         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10051         preemption_timeout *= 1000000;
10052         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
10053         hrtimer_start(&vmx->nested.preemption_timer,
10054                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
10055 }
10056
10057 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
10058                                                struct vmcs12 *vmcs12)
10059 {
10060         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
10061                 return 0;
10062
10063         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
10064             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
10065                 return -EINVAL;
10066
10067         return 0;
10068 }
10069
10070 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
10071                                                 struct vmcs12 *vmcs12)
10072 {
10073         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10074                 return 0;
10075
10076         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10077                 return -EINVAL;
10078
10079         return 0;
10080 }
10081
10082 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10083                                                 struct vmcs12 *vmcs12)
10084 {
10085         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10086                 return 0;
10087
10088         if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10089                 return -EINVAL;
10090
10091         return 0;
10092 }
10093
10094 /*
10095  * Merge L0's and L1's MSR bitmap, return false to indicate that
10096  * we do not use the hardware.
10097  */
10098 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
10099                                                struct vmcs12 *vmcs12)
10100 {
10101         int msr;
10102         struct page *page;
10103         unsigned long *msr_bitmap_l1;
10104         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
10105
10106         /* This shortcut is ok because we support only x2APIC MSRs so far. */
10107         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
10108                 return false;
10109
10110         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10111         if (is_error_page(page))
10112                 return false;
10113         msr_bitmap_l1 = (unsigned long *)kmap(page);
10114
10115         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
10116
10117         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
10118                 if (nested_cpu_has_apic_reg_virt(vmcs12))
10119                         for (msr = 0x800; msr <= 0x8ff; msr++)
10120                                 nested_vmx_disable_intercept_for_msr(
10121                                         msr_bitmap_l1, msr_bitmap_l0,
10122                                         msr, MSR_TYPE_R);
10123
10124                 nested_vmx_disable_intercept_for_msr(
10125                                 msr_bitmap_l1, msr_bitmap_l0,
10126                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
10127                                 MSR_TYPE_R | MSR_TYPE_W);
10128
10129                 if (nested_cpu_has_vid(vmcs12)) {
10130                         nested_vmx_disable_intercept_for_msr(
10131                                 msr_bitmap_l1, msr_bitmap_l0,
10132                                 APIC_BASE_MSR + (APIC_EOI >> 4),
10133                                 MSR_TYPE_W);
10134                         nested_vmx_disable_intercept_for_msr(
10135                                 msr_bitmap_l1, msr_bitmap_l0,
10136                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
10137                                 MSR_TYPE_W);
10138                 }
10139         }
10140         kunmap(page);
10141         kvm_release_page_clean(page);
10142
10143         return true;
10144 }
10145
10146 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10147                                            struct vmcs12 *vmcs12)
10148 {
10149         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10150             !nested_cpu_has_apic_reg_virt(vmcs12) &&
10151             !nested_cpu_has_vid(vmcs12) &&
10152             !nested_cpu_has_posted_intr(vmcs12))
10153                 return 0;
10154
10155         /*
10156          * If virtualize x2apic mode is enabled,
10157          * virtualize apic access must be disabled.
10158          */
10159         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10160             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10161                 return -EINVAL;
10162
10163         /*
10164          * If virtual interrupt delivery is enabled,
10165          * we must exit on external interrupts.
10166          */
10167         if (nested_cpu_has_vid(vmcs12) &&
10168            !nested_exit_on_intr(vcpu))
10169                 return -EINVAL;
10170
10171         /*
10172          * bits 15:8 should be zero in posted_intr_nv,
10173          * the descriptor address has been already checked
10174          * in nested_get_vmcs12_pages.
10175          */
10176         if (nested_cpu_has_posted_intr(vmcs12) &&
10177            (!nested_cpu_has_vid(vmcs12) ||
10178             !nested_exit_intr_ack_set(vcpu) ||
10179             vmcs12->posted_intr_nv & 0xff00))
10180                 return -EINVAL;
10181
10182         /* tpr shadow is needed by all apicv features. */
10183         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10184                 return -EINVAL;
10185
10186         return 0;
10187 }
10188
10189 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10190                                        unsigned long count_field,
10191                                        unsigned long addr_field)
10192 {
10193         int maxphyaddr;
10194         u64 count, addr;
10195
10196         if (vmcs12_read_any(vcpu, count_field, &count) ||
10197             vmcs12_read_any(vcpu, addr_field, &addr)) {
10198                 WARN_ON(1);
10199                 return -EINVAL;
10200         }
10201         if (count == 0)
10202                 return 0;
10203         maxphyaddr = cpuid_maxphyaddr(vcpu);
10204         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10205             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10206                 pr_debug_ratelimited(
10207                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10208                         addr_field, maxphyaddr, count, addr);
10209                 return -EINVAL;
10210         }
10211         return 0;
10212 }
10213
10214 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10215                                                 struct vmcs12 *vmcs12)
10216 {
10217         if (vmcs12->vm_exit_msr_load_count == 0 &&
10218             vmcs12->vm_exit_msr_store_count == 0 &&
10219             vmcs12->vm_entry_msr_load_count == 0)
10220                 return 0; /* Fast path */
10221         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10222                                         VM_EXIT_MSR_LOAD_ADDR) ||
10223             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10224                                         VM_EXIT_MSR_STORE_ADDR) ||
10225             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10226                                         VM_ENTRY_MSR_LOAD_ADDR))
10227                 return -EINVAL;
10228         return 0;
10229 }
10230
10231 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10232                                          struct vmcs12 *vmcs12)
10233 {
10234         u64 address = vmcs12->pml_address;
10235         int maxphyaddr = cpuid_maxphyaddr(vcpu);
10236
10237         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10238                 if (!nested_cpu_has_ept(vmcs12) ||
10239                     !IS_ALIGNED(address, 4096)  ||
10240                     address >> maxphyaddr)
10241                         return -EINVAL;
10242         }
10243
10244         return 0;
10245 }
10246
10247 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10248                                        struct vmx_msr_entry *e)
10249 {
10250         /* x2APIC MSR accesses are not allowed */
10251         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10252                 return -EINVAL;
10253         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10254             e->index == MSR_IA32_UCODE_REV)
10255                 return -EINVAL;
10256         if (e->reserved != 0)
10257                 return -EINVAL;
10258         return 0;
10259 }
10260
10261 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10262                                      struct vmx_msr_entry *e)
10263 {
10264         if (e->index == MSR_FS_BASE ||
10265             e->index == MSR_GS_BASE ||
10266             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10267             nested_vmx_msr_check_common(vcpu, e))
10268                 return -EINVAL;
10269         return 0;
10270 }
10271
10272 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10273                                       struct vmx_msr_entry *e)
10274 {
10275         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
10276             nested_vmx_msr_check_common(vcpu, e))
10277                 return -EINVAL;
10278         return 0;
10279 }
10280
10281 /*
10282  * Load guest's/host's msr at nested entry/exit.
10283  * return 0 for success, entry index for failure.
10284  */
10285 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10286 {
10287         u32 i;
10288         struct vmx_msr_entry e;
10289         struct msr_data msr;
10290
10291         msr.host_initiated = false;
10292         for (i = 0; i < count; i++) {
10293                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
10294                                         &e, sizeof(e))) {
10295                         pr_debug_ratelimited(
10296                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10297                                 __func__, i, gpa + i * sizeof(e));
10298                         goto fail;
10299                 }
10300                 if (nested_vmx_load_msr_check(vcpu, &e)) {
10301                         pr_debug_ratelimited(
10302                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10303                                 __func__, i, e.index, e.reserved);
10304                         goto fail;
10305                 }
10306                 msr.index = e.index;
10307                 msr.data = e.value;
10308                 if (kvm_set_msr(vcpu, &msr)) {
10309                         pr_debug_ratelimited(
10310                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10311                                 __func__, i, e.index, e.value);
10312                         goto fail;
10313                 }
10314         }
10315         return 0;
10316 fail:
10317         return i + 1;
10318 }
10319
10320 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10321 {
10322         u32 i;
10323         struct vmx_msr_entry e;
10324
10325         for (i = 0; i < count; i++) {
10326                 struct msr_data msr_info;
10327                 if (kvm_vcpu_read_guest(vcpu,
10328                                         gpa + i * sizeof(e),
10329                                         &e, 2 * sizeof(u32))) {
10330                         pr_debug_ratelimited(
10331                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10332                                 __func__, i, gpa + i * sizeof(e));
10333                         return -EINVAL;
10334                 }
10335                 if (nested_vmx_store_msr_check(vcpu, &e)) {
10336                         pr_debug_ratelimited(
10337                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10338                                 __func__, i, e.index, e.reserved);
10339                         return -EINVAL;
10340                 }
10341                 msr_info.host_initiated = false;
10342                 msr_info.index = e.index;
10343                 if (kvm_get_msr(vcpu, &msr_info)) {
10344                         pr_debug_ratelimited(
10345                                 "%s cannot read MSR (%u, 0x%x)\n",
10346                                 __func__, i, e.index);
10347                         return -EINVAL;
10348                 }
10349                 if (kvm_vcpu_write_guest(vcpu,
10350                                          gpa + i * sizeof(e) +
10351                                              offsetof(struct vmx_msr_entry, value),
10352                                          &msr_info.data, sizeof(msr_info.data))) {
10353                         pr_debug_ratelimited(
10354                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10355                                 __func__, i, e.index, msr_info.data);
10356                         return -EINVAL;
10357                 }
10358         }
10359         return 0;
10360 }
10361
10362 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10363 {
10364         unsigned long invalid_mask;
10365
10366         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10367         return (val & invalid_mask) == 0;
10368 }
10369
10370 /*
10371  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10372  * emulating VM entry into a guest with EPT enabled.
10373  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10374  * is assigned to entry_failure_code on failure.
10375  */
10376 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10377                                u32 *entry_failure_code)
10378 {
10379         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10380                 if (!nested_cr3_valid(vcpu, cr3)) {
10381                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10382                         return 1;
10383                 }
10384
10385                 /*
10386                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10387                  * must not be dereferenced.
10388                  */
10389                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10390                     !nested_ept) {
10391                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10392                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
10393                                 return 1;
10394                         }
10395                 }
10396
10397                 vcpu->arch.cr3 = cr3;
10398                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10399         }
10400
10401         kvm_mmu_reset_context(vcpu);
10402         return 0;
10403 }
10404
10405 /*
10406  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10407  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10408  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10409  * guest in a way that will both be appropriate to L1's requests, and our
10410  * needs. In addition to modifying the active vmcs (which is vmcs02), this
10411  * function also has additional necessary side-effects, like setting various
10412  * vcpu->arch fields.
10413  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10414  * is assigned to entry_failure_code on failure.
10415  */
10416 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10417                           bool from_vmentry, u32 *entry_failure_code)
10418 {
10419         struct vcpu_vmx *vmx = to_vmx(vcpu);
10420         u32 exec_control, vmcs12_exec_ctrl;
10421
10422         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10423         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10424         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10425         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10426         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10427         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10428         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10429         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10430         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10431         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10432         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10433         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10434         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10435         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10436         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10437         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10438         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10439         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10440         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10441         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10442         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10443         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10444         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10445         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10446         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10447         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10448         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10449         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10450         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10451         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10452         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10453         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10454         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10455         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10456         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10457         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10458
10459         if (from_vmentry &&
10460             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10461                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10462                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10463         } else {
10464                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10465                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10466         }
10467         if (from_vmentry) {
10468                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10469                              vmcs12->vm_entry_intr_info_field);
10470                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10471                              vmcs12->vm_entry_exception_error_code);
10472                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10473                              vmcs12->vm_entry_instruction_len);
10474                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10475                              vmcs12->guest_interruptibility_info);
10476                 vmx->loaded_vmcs->nmi_known_unmasked =
10477                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
10478         } else {
10479                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10480         }
10481         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10482         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10483         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10484                 vmcs12->guest_pending_dbg_exceptions);
10485         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10486         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10487
10488         if (nested_cpu_has_xsaves(vmcs12))
10489                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10490         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10491
10492         exec_control = vmcs12->pin_based_vm_exec_control;
10493
10494         /* Preemption timer setting is only taken from vmcs01.  */
10495         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10496         exec_control |= vmcs_config.pin_based_exec_ctrl;
10497         if (vmx->hv_deadline_tsc == -1)
10498                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10499
10500         /* Posted interrupts setting is only taken from vmcs12.  */
10501         if (nested_cpu_has_posted_intr(vmcs12)) {
10502                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10503                 vmx->nested.pi_pending = false;
10504                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10505         } else {
10506                 exec_control &= ~PIN_BASED_POSTED_INTR;
10507         }
10508
10509         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10510
10511         vmx->nested.preemption_timer_expired = false;
10512         if (nested_cpu_has_preemption_timer(vmcs12))
10513                 vmx_start_preemption_timer(vcpu);
10514
10515         /*
10516          * Whether page-faults are trapped is determined by a combination of
10517          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10518          * If enable_ept, L0 doesn't care about page faults and we should
10519          * set all of these to L1's desires. However, if !enable_ept, L0 does
10520          * care about (at least some) page faults, and because it is not easy
10521          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10522          * to exit on each and every L2 page fault. This is done by setting
10523          * MASK=MATCH=0 and (see below) EB.PF=1.
10524          * Note that below we don't need special code to set EB.PF beyond the
10525          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10526          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10527          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10528          */
10529         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10530                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10531         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10532                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10533
10534         if (cpu_has_secondary_exec_ctrls()) {
10535                 exec_control = vmx->secondary_exec_control;
10536
10537                 /* Take the following fields only from vmcs12 */
10538                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10539                                   SECONDARY_EXEC_ENABLE_INVPCID |
10540                                   SECONDARY_EXEC_RDTSCP |
10541                                   SECONDARY_EXEC_XSAVES |
10542                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10543                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
10544                                   SECONDARY_EXEC_ENABLE_VMFUNC);
10545                 if (nested_cpu_has(vmcs12,
10546                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10547                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10548                                 ~SECONDARY_EXEC_ENABLE_PML;
10549                         exec_control |= vmcs12_exec_ctrl;
10550                 }
10551
10552                 /* All VMFUNCs are currently emulated through L0 vmexits.  */
10553                 if (exec_control & SECONDARY_EXEC_ENABLE_VMFUNC)
10554                         vmcs_write64(VM_FUNCTION_CONTROL, 0);
10555
10556                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10557                         vmcs_write64(EOI_EXIT_BITMAP0,
10558                                 vmcs12->eoi_exit_bitmap0);
10559                         vmcs_write64(EOI_EXIT_BITMAP1,
10560                                 vmcs12->eoi_exit_bitmap1);
10561                         vmcs_write64(EOI_EXIT_BITMAP2,
10562                                 vmcs12->eoi_exit_bitmap2);
10563                         vmcs_write64(EOI_EXIT_BITMAP3,
10564                                 vmcs12->eoi_exit_bitmap3);
10565                         vmcs_write16(GUEST_INTR_STATUS,
10566                                 vmcs12->guest_intr_status);
10567                 }
10568
10569                 /*
10570                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10571                  * nested_get_vmcs12_pages will either fix it up or
10572                  * remove the VM execution control.
10573                  */
10574                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10575                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10576
10577                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10578         }
10579
10580
10581         /*
10582          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10583          * Some constant fields are set here by vmx_set_constant_host_state().
10584          * Other fields are different per CPU, and will be set later when
10585          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10586          */
10587         vmx_set_constant_host_state(vmx);
10588
10589         /*
10590          * Set the MSR load/store lists to match L0's settings.
10591          */
10592         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10593         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10594         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10595         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10596         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10597
10598         /*
10599          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10600          * entry, but only if the current (host) sp changed from the value
10601          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10602          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10603          * here we just force the write to happen on entry.
10604          */
10605         vmx->host_rsp = 0;
10606
10607         exec_control = vmx_exec_control(vmx); /* L0's desires */
10608         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10609         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10610         exec_control &= ~CPU_BASED_TPR_SHADOW;
10611         exec_control |= vmcs12->cpu_based_vm_exec_control;
10612
10613         /*
10614          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10615          * nested_get_vmcs12_pages can't fix it up, the illegal value
10616          * will result in a VM entry failure.
10617          */
10618         if (exec_control & CPU_BASED_TPR_SHADOW) {
10619                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10620                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10621         } else {
10622 #ifdef CONFIG_X86_64
10623                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
10624                                 CPU_BASED_CR8_STORE_EXITING;
10625 #endif
10626         }
10627
10628         /*
10629          * Merging of IO bitmap not currently supported.
10630          * Rather, exit every time.
10631          */
10632         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10633         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10634
10635         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10636
10637         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10638          * bitwise-or of what L1 wants to trap for L2, and what we want to
10639          * trap. Note that CR0.TS also needs updating - we do this later.
10640          */
10641         update_exception_bitmap(vcpu);
10642         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10643         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10644
10645         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10646          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10647          * bits are further modified by vmx_set_efer() below.
10648          */
10649         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10650
10651         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10652          * emulated by vmx_set_efer(), below.
10653          */
10654         vm_entry_controls_init(vmx,
10655                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10656                         ~VM_ENTRY_IA32E_MODE) |
10657                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10658
10659         if (from_vmentry &&
10660             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10661                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10662                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10663         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10664                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10665         }
10666
10667         set_cr4_guest_host_mask(vmx);
10668
10669         if (from_vmentry &&
10670             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10671                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10672
10673         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10674                 vmcs_write64(TSC_OFFSET,
10675                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10676         else
10677                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10678         if (kvm_has_tsc_control)
10679                 decache_tsc_multiplier(vmx);
10680
10681         if (enable_vpid) {
10682                 /*
10683                  * There is no direct mapping between vpid02 and vpid12, the
10684                  * vpid02 is per-vCPU for L0 and reused while the value of
10685                  * vpid12 is changed w/ one invvpid during nested vmentry.
10686                  * The vpid12 is allocated by L1 for L2, so it will not
10687                  * influence global bitmap(for vpid01 and vpid02 allocation)
10688                  * even if spawn a lot of nested vCPUs.
10689                  */
10690                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10691                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10692                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10693                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10694                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10695                         }
10696                 } else {
10697                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10698                         vmx_flush_tlb(vcpu);
10699                 }
10700
10701         }
10702
10703         if (enable_pml) {
10704                 /*
10705                  * Conceptually we want to copy the PML address and index from
10706                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10707                  * since we always flush the log on each vmexit, this happens
10708                  * to be equivalent to simply resetting the fields in vmcs02.
10709                  */
10710                 ASSERT(vmx->pml_pg);
10711                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10712                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10713         }
10714
10715         if (nested_cpu_has_ept(vmcs12)) {
10716                 if (nested_ept_init_mmu_context(vcpu)) {
10717                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10718                         return 1;
10719                 }
10720         } else if (nested_cpu_has2(vmcs12,
10721                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10722                 vmx_flush_tlb_ept_only(vcpu);
10723         }
10724
10725         /*
10726          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10727          * bits which we consider mandatory enabled.
10728          * The CR0_READ_SHADOW is what L2 should have expected to read given
10729          * the specifications by L1; It's not enough to take
10730          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10731          * have more bits than L1 expected.
10732          */
10733         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10734         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10735
10736         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10737         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10738
10739         if (from_vmentry &&
10740             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10741                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10742         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10743                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10744         else
10745                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10746         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10747         vmx_set_efer(vcpu, vcpu->arch.efer);
10748
10749         /* Shadow page tables on either EPT or shadow page tables. */
10750         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10751                                 entry_failure_code))
10752                 return 1;
10753
10754         if (!enable_ept)
10755                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10756
10757         /*
10758          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10759          */
10760         if (enable_ept) {
10761                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10762                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10763                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10764                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10765         }
10766
10767         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10768         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10769         return 0;
10770 }
10771
10772 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10773 {
10774         struct vcpu_vmx *vmx = to_vmx(vcpu);
10775
10776         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10777             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10778                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10779
10780         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10781                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10782
10783         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10784                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10785
10786         if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
10787                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10788
10789         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10790                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10791
10792         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10793                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10794
10795         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10796                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10797
10798         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10799                                 vmx->nested.nested_vmx_procbased_ctls_low,
10800                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10801             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10802              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10803                                  vmx->nested.nested_vmx_secondary_ctls_low,
10804                                  vmx->nested.nested_vmx_secondary_ctls_high)) ||
10805             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10806                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10807                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10808             !vmx_control_verify(vmcs12->vm_exit_controls,
10809                                 vmx->nested.nested_vmx_exit_ctls_low,
10810                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10811             !vmx_control_verify(vmcs12->vm_entry_controls,
10812                                 vmx->nested.nested_vmx_entry_ctls_low,
10813                                 vmx->nested.nested_vmx_entry_ctls_high))
10814                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10815
10816         if (nested_cpu_has_vmfunc(vmcs12)) {
10817                 if (vmcs12->vm_function_control &
10818                     ~vmx->nested.nested_vmx_vmfunc_controls)
10819                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10820
10821                 if (nested_cpu_has_eptp_switching(vmcs12)) {
10822                         if (!nested_cpu_has_ept(vmcs12) ||
10823                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
10824                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10825                 }
10826         }
10827
10828         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10829                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10830
10831         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10832             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10833             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10834                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10835
10836         return 0;
10837 }
10838
10839 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10840                                   u32 *exit_qual)
10841 {
10842         bool ia32e;
10843
10844         *exit_qual = ENTRY_FAIL_DEFAULT;
10845
10846         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10847             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10848                 return 1;
10849
10850         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10851             vmcs12->vmcs_link_pointer != -1ull) {
10852                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10853                 return 1;
10854         }
10855
10856         /*
10857          * If the load IA32_EFER VM-entry control is 1, the following checks
10858          * are performed on the field for the IA32_EFER MSR:
10859          * - Bits reserved in the IA32_EFER MSR must be 0.
10860          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10861          *   the IA-32e mode guest VM-exit control. It must also be identical
10862          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10863          *   CR0.PG) is 1.
10864          */
10865         if (to_vmx(vcpu)->nested.nested_run_pending &&
10866             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10867                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10868                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10869                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10870                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10871                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10872                         return 1;
10873         }
10874
10875         /*
10876          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10877          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10878          * the values of the LMA and LME bits in the field must each be that of
10879          * the host address-space size VM-exit control.
10880          */
10881         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10882                 ia32e = (vmcs12->vm_exit_controls &
10883                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10884                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10885                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10886                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10887                         return 1;
10888         }
10889
10890         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
10891                 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
10892                 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
10893                         return 1;
10894
10895         return 0;
10896 }
10897
10898 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10899 {
10900         struct vcpu_vmx *vmx = to_vmx(vcpu);
10901         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10902         struct loaded_vmcs *vmcs02;
10903         u32 msr_entry_idx;
10904         u32 exit_qual;
10905
10906         vmcs02 = nested_get_current_vmcs02(vmx);
10907         if (!vmcs02)
10908                 return -ENOMEM;
10909
10910         enter_guest_mode(vcpu);
10911
10912         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10913                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10914
10915         vmx_switch_vmcs(vcpu, vmcs02);
10916         vmx_segment_cache_clear(vmx);
10917
10918         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10919                 leave_guest_mode(vcpu);
10920                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10921                 nested_vmx_entry_failure(vcpu, vmcs12,
10922                                          EXIT_REASON_INVALID_STATE, exit_qual);
10923                 return 1;
10924         }
10925
10926         nested_get_vmcs12_pages(vcpu, vmcs12);
10927
10928         msr_entry_idx = nested_vmx_load_msr(vcpu,
10929                                             vmcs12->vm_entry_msr_load_addr,
10930                                             vmcs12->vm_entry_msr_load_count);
10931         if (msr_entry_idx) {
10932                 leave_guest_mode(vcpu);
10933                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10934                 nested_vmx_entry_failure(vcpu, vmcs12,
10935                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10936                 return 1;
10937         }
10938
10939         /*
10940          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10941          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10942          * returned as far as L1 is concerned. It will only return (and set
10943          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10944          */
10945         return 0;
10946 }
10947
10948 /*
10949  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10950  * for running an L2 nested guest.
10951  */
10952 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10953 {
10954         struct vmcs12 *vmcs12;
10955         struct vcpu_vmx *vmx = to_vmx(vcpu);
10956         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
10957         u32 exit_qual;
10958         int ret;
10959
10960         if (!nested_vmx_check_permission(vcpu))
10961                 return 1;
10962
10963         if (!nested_vmx_check_vmcs12(vcpu))
10964                 goto out;
10965
10966         vmcs12 = get_vmcs12(vcpu);
10967
10968         if (enable_shadow_vmcs)
10969                 copy_shadow_to_vmcs12(vmx);
10970
10971         /*
10972          * The nested entry process starts with enforcing various prerequisites
10973          * on vmcs12 as required by the Intel SDM, and act appropriately when
10974          * they fail: As the SDM explains, some conditions should cause the
10975          * instruction to fail, while others will cause the instruction to seem
10976          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10977          * To speed up the normal (success) code path, we should avoid checking
10978          * for misconfigurations which will anyway be caught by the processor
10979          * when using the merged vmcs02.
10980          */
10981         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
10982                 nested_vmx_failValid(vcpu,
10983                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
10984                 goto out;
10985         }
10986
10987         if (vmcs12->launch_state == launch) {
10988                 nested_vmx_failValid(vcpu,
10989                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10990                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10991                 goto out;
10992         }
10993
10994         ret = check_vmentry_prereqs(vcpu, vmcs12);
10995         if (ret) {
10996                 nested_vmx_failValid(vcpu, ret);
10997                 goto out;
10998         }
10999
11000         /*
11001          * After this point, the trap flag no longer triggers a singlestep trap
11002          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11003          * This is not 100% correct; for performance reasons, we delegate most
11004          * of the checks on host state to the processor.  If those fail,
11005          * the singlestep trap is missed.
11006          */
11007         skip_emulated_instruction(vcpu);
11008
11009         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
11010         if (ret) {
11011                 nested_vmx_entry_failure(vcpu, vmcs12,
11012                                          EXIT_REASON_INVALID_STATE, exit_qual);
11013                 return 1;
11014         }
11015
11016         /*
11017          * We're finally done with prerequisite checking, and can start with
11018          * the nested entry.
11019          */
11020
11021         ret = enter_vmx_non_root_mode(vcpu, true);
11022         if (ret)
11023                 return ret;
11024
11025         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
11026                 return kvm_vcpu_halt(vcpu);
11027
11028         vmx->nested.nested_run_pending = 1;
11029
11030         return 1;
11031
11032 out:
11033         return kvm_skip_emulated_instruction(vcpu);
11034 }
11035
11036 /*
11037  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11038  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11039  * This function returns the new value we should put in vmcs12.guest_cr0.
11040  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11041  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11042  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11043  *     didn't trap the bit, because if L1 did, so would L0).
11044  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11045  *     been modified by L2, and L1 knows it. So just leave the old value of
11046  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11047  *     isn't relevant, because if L0 traps this bit it can set it to anything.
11048  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11049  *     changed these bits, and therefore they need to be updated, but L0
11050  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11051  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11052  */
11053 static inline unsigned long
11054 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11055 {
11056         return
11057         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
11058         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
11059         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
11060                         vcpu->arch.cr0_guest_owned_bits));
11061 }
11062
11063 static inline unsigned long
11064 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11065 {
11066         return
11067         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
11068         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
11069         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
11070                         vcpu->arch.cr4_guest_owned_bits));
11071 }
11072
11073 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
11074                                        struct vmcs12 *vmcs12)
11075 {
11076         u32 idt_vectoring;
11077         unsigned int nr;
11078
11079         if (vcpu->arch.exception.injected) {
11080                 nr = vcpu->arch.exception.nr;
11081                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11082
11083                 if (kvm_exception_is_soft(nr)) {
11084                         vmcs12->vm_exit_instruction_len =
11085                                 vcpu->arch.event_exit_inst_len;
11086                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11087                 } else
11088                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11089
11090                 if (vcpu->arch.exception.has_error_code) {
11091                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11092                         vmcs12->idt_vectoring_error_code =
11093                                 vcpu->arch.exception.error_code;
11094                 }
11095
11096                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11097         } else if (vcpu->arch.nmi_injected) {
11098                 vmcs12->idt_vectoring_info_field =
11099                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11100         } else if (vcpu->arch.interrupt.pending) {
11101                 nr = vcpu->arch.interrupt.nr;
11102                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11103
11104                 if (vcpu->arch.interrupt.soft) {
11105                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
11106                         vmcs12->vm_entry_instruction_len =
11107                                 vcpu->arch.event_exit_inst_len;
11108                 } else
11109                         idt_vectoring |= INTR_TYPE_EXT_INTR;
11110
11111                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11112         }
11113 }
11114
11115 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
11116 {
11117         struct vcpu_vmx *vmx = to_vmx(vcpu);
11118         unsigned long exit_qual;
11119         bool block_nested_events =
11120             vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
11121
11122         if (vcpu->arch.exception.pending &&
11123                 nested_vmx_check_exception(vcpu, &exit_qual)) {
11124                 if (block_nested_events)
11125                         return -EBUSY;
11126                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11127                 vcpu->arch.exception.pending = false;
11128                 return 0;
11129         }
11130
11131         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11132             vmx->nested.preemption_timer_expired) {
11133                 if (block_nested_events)
11134                         return -EBUSY;
11135                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11136                 return 0;
11137         }
11138
11139         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11140                 if (block_nested_events)
11141                         return -EBUSY;
11142                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11143                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
11144                                   INTR_INFO_VALID_MASK, 0);
11145                 /*
11146                  * The NMI-triggered VM exit counts as injection:
11147                  * clear this one and block further NMIs.
11148                  */
11149                 vcpu->arch.nmi_pending = 0;
11150                 vmx_set_nmi_mask(vcpu, true);
11151                 return 0;
11152         }
11153
11154         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
11155             nested_exit_on_intr(vcpu)) {
11156                 if (block_nested_events)
11157                         return -EBUSY;
11158                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
11159                 return 0;
11160         }
11161
11162         vmx_complete_nested_posted_interrupt(vcpu);
11163         return 0;
11164 }
11165
11166 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
11167 {
11168         ktime_t remaining =
11169                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
11170         u64 value;
11171
11172         if (ktime_to_ns(remaining) <= 0)
11173                 return 0;
11174
11175         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
11176         do_div(value, 1000000);
11177         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11178 }
11179
11180 /*
11181  * Update the guest state fields of vmcs12 to reflect changes that
11182  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11183  * VM-entry controls is also updated, since this is really a guest
11184  * state bit.)
11185  */
11186 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11187 {
11188         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
11189         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
11190
11191         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
11192         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
11193         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
11194
11195         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
11196         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
11197         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
11198         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
11199         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11200         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11201         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11202         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11203         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11204         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11205         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
11206         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
11207         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
11208         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
11209         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
11210         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
11211         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
11212         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
11213         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
11214         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
11215         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
11216         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
11217         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
11218         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
11219         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
11220         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
11221         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
11222         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
11223         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
11224         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
11225         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
11226         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
11227         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
11228         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
11229         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
11230         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
11231
11232         vmcs12->guest_interruptibility_info =
11233                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
11234         vmcs12->guest_pending_dbg_exceptions =
11235                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
11236         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11237                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
11238         else
11239                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
11240
11241         if (nested_cpu_has_preemption_timer(vmcs12)) {
11242                 if (vmcs12->vm_exit_controls &
11243                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
11244                         vmcs12->vmx_preemption_timer_value =
11245                                 vmx_get_preemption_timer_value(vcpu);
11246                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
11247         }
11248
11249         /*
11250          * In some cases (usually, nested EPT), L2 is allowed to change its
11251          * own CR3 without exiting. If it has changed it, we must keep it.
11252          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11253          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11254          *
11255          * Additionally, restore L2's PDPTR to vmcs12.
11256          */
11257         if (enable_ept) {
11258                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
11259                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
11260                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
11261                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
11262                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
11263         }
11264
11265         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
11266
11267         if (nested_cpu_has_vid(vmcs12))
11268                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
11269
11270         vmcs12->vm_entry_controls =
11271                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
11272                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
11273
11274         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
11275                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
11276                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11277         }
11278
11279         /* TODO: These cannot have changed unless we have MSR bitmaps and
11280          * the relevant bit asks not to trap the change */
11281         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
11282                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
11283         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
11284                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
11285         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
11286         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
11287         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
11288         if (kvm_mpx_supported())
11289                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
11290 }
11291
11292 /*
11293  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11294  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11295  * and this function updates it to reflect the changes to the guest state while
11296  * L2 was running (and perhaps made some exits which were handled directly by L0
11297  * without going back to L1), and to reflect the exit reason.
11298  * Note that we do not have to copy here all VMCS fields, just those that
11299  * could have changed by the L2 guest or the exit - i.e., the guest-state and
11300  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11301  * which already writes to vmcs12 directly.
11302  */
11303 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11304                            u32 exit_reason, u32 exit_intr_info,
11305                            unsigned long exit_qualification)
11306 {
11307         /* update guest state fields: */
11308         sync_vmcs12(vcpu, vmcs12);
11309
11310         /* update exit information fields: */
11311
11312         vmcs12->vm_exit_reason = exit_reason;
11313         vmcs12->exit_qualification = exit_qualification;
11314         vmcs12->vm_exit_intr_info = exit_intr_info;
11315
11316         vmcs12->idt_vectoring_info_field = 0;
11317         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
11318         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
11319
11320         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
11321                 vmcs12->launch_state = 1;
11322
11323                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11324                  * instead of reading the real value. */
11325                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
11326
11327                 /*
11328                  * Transfer the event that L0 or L1 may wanted to inject into
11329                  * L2 to IDT_VECTORING_INFO_FIELD.
11330                  */
11331                 vmcs12_save_pending_event(vcpu, vmcs12);
11332         }
11333
11334         /*
11335          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11336          * preserved above and would only end up incorrectly in L1.
11337          */
11338         vcpu->arch.nmi_injected = false;
11339         kvm_clear_exception_queue(vcpu);
11340         kvm_clear_interrupt_queue(vcpu);
11341 }
11342
11343 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
11344                         struct vmcs12 *vmcs12)
11345 {
11346         u32 entry_failure_code;
11347
11348         nested_ept_uninit_mmu_context(vcpu);
11349
11350         /*
11351          * Only PDPTE load can fail as the value of cr3 was checked on entry and
11352          * couldn't have changed.
11353          */
11354         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
11355                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
11356
11357         if (!enable_ept)
11358                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11359 }
11360
11361 /*
11362  * A part of what we need to when the nested L2 guest exits and we want to
11363  * run its L1 parent, is to reset L1's guest state to the host state specified
11364  * in vmcs12.
11365  * This function is to be called not only on normal nested exit, but also on
11366  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11367  * Failures During or After Loading Guest State").
11368  * This function should be called when the active VMCS is L1's (vmcs01).
11369  */
11370 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
11371                                    struct vmcs12 *vmcs12)
11372 {
11373         struct kvm_segment seg;
11374
11375         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
11376                 vcpu->arch.efer = vmcs12->host_ia32_efer;
11377         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11378                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11379         else
11380                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11381         vmx_set_efer(vcpu, vcpu->arch.efer);
11382
11383         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11384         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
11385         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
11386         /*
11387          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11388          * actually changed, because vmx_set_cr0 refers to efer set above.
11389          *
11390          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11391          * (KVM doesn't change it);
11392          */
11393         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
11394         vmx_set_cr0(vcpu, vmcs12->host_cr0);
11395
11396         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
11397         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
11398         vmx_set_cr4(vcpu, vmcs12->host_cr4);
11399
11400         load_vmcs12_mmu_host_state(vcpu, vmcs12);
11401
11402         if (enable_vpid) {
11403                 /*
11404                  * Trivially support vpid by letting L2s share their parent
11405                  * L1's vpid. TODO: move to a more elaborate solution, giving
11406                  * each L2 its own vpid and exposing the vpid feature to L1.
11407                  */
11408                 vmx_flush_tlb(vcpu);
11409         }
11410         /* Restore posted intr vector. */
11411         if (nested_cpu_has_posted_intr(vmcs12))
11412                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
11413
11414         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11415         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11416         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11417         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11418         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11419         vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
11420         vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
11421
11422         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
11423         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11424                 vmcs_write64(GUEST_BNDCFGS, 0);
11425
11426         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11427                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11428                 vcpu->arch.pat = vmcs12->host_ia32_pat;
11429         }
11430         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11431                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11432                         vmcs12->host_ia32_perf_global_ctrl);
11433
11434         /* Set L1 segment info according to Intel SDM
11435             27.5.2 Loading Host Segment and Descriptor-Table Registers */
11436         seg = (struct kvm_segment) {
11437                 .base = 0,
11438                 .limit = 0xFFFFFFFF,
11439                 .selector = vmcs12->host_cs_selector,
11440                 .type = 11,
11441                 .present = 1,
11442                 .s = 1,
11443                 .g = 1
11444         };
11445         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11446                 seg.l = 1;
11447         else
11448                 seg.db = 1;
11449         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11450         seg = (struct kvm_segment) {
11451                 .base = 0,
11452                 .limit = 0xFFFFFFFF,
11453                 .type = 3,
11454                 .present = 1,
11455                 .s = 1,
11456                 .db = 1,
11457                 .g = 1
11458         };
11459         seg.selector = vmcs12->host_ds_selector;
11460         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11461         seg.selector = vmcs12->host_es_selector;
11462         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11463         seg.selector = vmcs12->host_ss_selector;
11464         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11465         seg.selector = vmcs12->host_fs_selector;
11466         seg.base = vmcs12->host_fs_base;
11467         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11468         seg.selector = vmcs12->host_gs_selector;
11469         seg.base = vmcs12->host_gs_base;
11470         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11471         seg = (struct kvm_segment) {
11472                 .base = vmcs12->host_tr_base,
11473                 .limit = 0x67,
11474                 .selector = vmcs12->host_tr_selector,
11475                 .type = 11,
11476                 .present = 1
11477         };
11478         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11479
11480         kvm_set_dr(vcpu, 7, 0x400);
11481         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11482
11483         if (cpu_has_vmx_msr_bitmap())
11484                 vmx_set_msr_bitmap(vcpu);
11485
11486         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11487                                 vmcs12->vm_exit_msr_load_count))
11488                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11489 }
11490
11491 /*
11492  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11493  * and modify vmcs12 to make it see what it would expect to see there if
11494  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11495  */
11496 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11497                               u32 exit_intr_info,
11498                               unsigned long exit_qualification)
11499 {
11500         struct vcpu_vmx *vmx = to_vmx(vcpu);
11501         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11502
11503         /* trying to cancel vmlaunch/vmresume is a bug */
11504         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11505
11506         /*
11507          * The only expected VM-instruction error is "VM entry with
11508          * invalid control field(s)." Anything else indicates a
11509          * problem with L0.
11510          */
11511         WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
11512                                    VMXERR_ENTRY_INVALID_CONTROL_FIELD));
11513
11514         leave_guest_mode(vcpu);
11515
11516         if (likely(!vmx->fail)) {
11517                 if (exit_reason == -1)
11518                         sync_vmcs12(vcpu, vmcs12);
11519                 else
11520                         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11521                                        exit_qualification);
11522
11523                 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11524                                          vmcs12->vm_exit_msr_store_count))
11525                         nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11526         }
11527
11528         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11529         vm_entry_controls_reset_shadow(vmx);
11530         vm_exit_controls_reset_shadow(vmx);
11531         vmx_segment_cache_clear(vmx);
11532
11533         /* if no vmcs02 cache requested, remove the one we used */
11534         if (VMCS02_POOL_SIZE == 0)
11535                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11536
11537         /* Update any VMCS fields that might have changed while L2 ran */
11538         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11539         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11540         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11541         if (vmx->hv_deadline_tsc == -1)
11542                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11543                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11544         else
11545                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11546                               PIN_BASED_VMX_PREEMPTION_TIMER);
11547         if (kvm_has_tsc_control)
11548                 decache_tsc_multiplier(vmx);
11549
11550         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11551                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11552                 vmx_set_virtual_x2apic_mode(vcpu,
11553                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11554         } else if (!nested_cpu_has_ept(vmcs12) &&
11555                    nested_cpu_has2(vmcs12,
11556                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11557                 vmx_flush_tlb_ept_only(vcpu);
11558         }
11559
11560         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11561         vmx->host_rsp = 0;
11562
11563         /* Unpin physical memory we referred to in vmcs02 */
11564         if (vmx->nested.apic_access_page) {
11565                 kvm_release_page_dirty(vmx->nested.apic_access_page);
11566                 vmx->nested.apic_access_page = NULL;
11567         }
11568         if (vmx->nested.virtual_apic_page) {
11569                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11570                 vmx->nested.virtual_apic_page = NULL;
11571         }
11572         if (vmx->nested.pi_desc_page) {
11573                 kunmap(vmx->nested.pi_desc_page);
11574                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
11575                 vmx->nested.pi_desc_page = NULL;
11576                 vmx->nested.pi_desc = NULL;
11577         }
11578
11579         /*
11580          * We are now running in L2, mmu_notifier will force to reload the
11581          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11582          */
11583         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11584
11585         if (enable_shadow_vmcs && exit_reason != -1)
11586                 vmx->nested.sync_shadow_vmcs = true;
11587
11588         /* in case we halted in L2 */
11589         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11590
11591         if (likely(!vmx->fail)) {
11592                 /*
11593                  * TODO: SDM says that with acknowledge interrupt on
11594                  * exit, bit 31 of the VM-exit interrupt information
11595                  * (valid interrupt) is always set to 1 on
11596                  * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11597                  * need kvm_cpu_has_interrupt().  See the commit
11598                  * message for details.
11599                  */
11600                 if (nested_exit_intr_ack_set(vcpu) &&
11601                     exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
11602                     kvm_cpu_has_interrupt(vcpu)) {
11603                         int irq = kvm_cpu_get_interrupt(vcpu);
11604                         WARN_ON(irq < 0);
11605                         vmcs12->vm_exit_intr_info = irq |
11606                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11607                 }
11608
11609                 if (exit_reason != -1)
11610                         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11611                                                        vmcs12->exit_qualification,
11612                                                        vmcs12->idt_vectoring_info_field,
11613                                                        vmcs12->vm_exit_intr_info,
11614                                                        vmcs12->vm_exit_intr_error_code,
11615                                                        KVM_ISA_VMX);
11616
11617                 load_vmcs12_host_state(vcpu, vmcs12);
11618
11619                 return;
11620         }
11621
11622         /*
11623          * After an early L2 VM-entry failure, we're now back
11624          * in L1 which thinks it just finished a VMLAUNCH or
11625          * VMRESUME instruction, so we need to set the failure
11626          * flag and the VM-instruction error field of the VMCS
11627          * accordingly.
11628          */
11629         nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
11630
11631         load_vmcs12_mmu_host_state(vcpu, vmcs12);
11632
11633         /*
11634          * The emulated instruction was already skipped in
11635          * nested_vmx_run, but the updated RIP was never
11636          * written back to the vmcs01.
11637          */
11638         skip_emulated_instruction(vcpu);
11639         vmx->fail = 0;
11640 }
11641
11642 /*
11643  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11644  */
11645 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11646 {
11647         if (is_guest_mode(vcpu)) {
11648                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11649                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11650         }
11651         free_nested(to_vmx(vcpu));
11652 }
11653
11654 /*
11655  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11656  * 23.7 "VM-entry failures during or after loading guest state" (this also
11657  * lists the acceptable exit-reason and exit-qualification parameters).
11658  * It should only be called before L2 actually succeeded to run, and when
11659  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11660  */
11661 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11662                         struct vmcs12 *vmcs12,
11663                         u32 reason, unsigned long qualification)
11664 {
11665         load_vmcs12_host_state(vcpu, vmcs12);
11666         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11667         vmcs12->exit_qualification = qualification;
11668         nested_vmx_succeed(vcpu);
11669         if (enable_shadow_vmcs)
11670                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11671 }
11672
11673 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11674                                struct x86_instruction_info *info,
11675                                enum x86_intercept_stage stage)
11676 {
11677         return X86EMUL_CONTINUE;
11678 }
11679
11680 #ifdef CONFIG_X86_64
11681 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11682 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11683                                   u64 divisor, u64 *result)
11684 {
11685         u64 low = a << shift, high = a >> (64 - shift);
11686
11687         /* To avoid the overflow on divq */
11688         if (high >= divisor)
11689                 return 1;
11690
11691         /* Low hold the result, high hold rem which is discarded */
11692         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11693             "rm" (divisor), "0" (low), "1" (high));
11694         *result = low;
11695
11696         return 0;
11697 }
11698
11699 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11700 {
11701         struct vcpu_vmx *vmx = to_vmx(vcpu);
11702         u64 tscl = rdtsc();
11703         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11704         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11705
11706         /* Convert to host delta tsc if tsc scaling is enabled */
11707         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11708                         u64_shl_div_u64(delta_tsc,
11709                                 kvm_tsc_scaling_ratio_frac_bits,
11710                                 vcpu->arch.tsc_scaling_ratio,
11711                                 &delta_tsc))
11712                 return -ERANGE;
11713
11714         /*
11715          * If the delta tsc can't fit in the 32 bit after the multi shift,
11716          * we can't use the preemption timer.
11717          * It's possible that it fits on later vmentries, but checking
11718          * on every vmentry is costly so we just use an hrtimer.
11719          */
11720         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11721                 return -ERANGE;
11722
11723         vmx->hv_deadline_tsc = tscl + delta_tsc;
11724         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11725                         PIN_BASED_VMX_PREEMPTION_TIMER);
11726
11727         return delta_tsc == 0;
11728 }
11729
11730 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11731 {
11732         struct vcpu_vmx *vmx = to_vmx(vcpu);
11733         vmx->hv_deadline_tsc = -1;
11734         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11735                         PIN_BASED_VMX_PREEMPTION_TIMER);
11736 }
11737 #endif
11738
11739 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11740 {
11741         if (ple_gap)
11742                 shrink_ple_window(vcpu);
11743 }
11744
11745 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11746                                      struct kvm_memory_slot *slot)
11747 {
11748         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11749         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11750 }
11751
11752 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11753                                        struct kvm_memory_slot *slot)
11754 {
11755         kvm_mmu_slot_set_dirty(kvm, slot);
11756 }
11757
11758 static void vmx_flush_log_dirty(struct kvm *kvm)
11759 {
11760         kvm_flush_pml_buffers(kvm);
11761 }
11762
11763 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11764 {
11765         struct vmcs12 *vmcs12;
11766         struct vcpu_vmx *vmx = to_vmx(vcpu);
11767         gpa_t gpa;
11768         struct page *page = NULL;
11769         u64 *pml_address;
11770
11771         if (is_guest_mode(vcpu)) {
11772                 WARN_ON_ONCE(vmx->nested.pml_full);
11773
11774                 /*
11775                  * Check if PML is enabled for the nested guest.
11776                  * Whether eptp bit 6 is set is already checked
11777                  * as part of A/D emulation.
11778                  */
11779                 vmcs12 = get_vmcs12(vcpu);
11780                 if (!nested_cpu_has_pml(vmcs12))
11781                         return 0;
11782
11783                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11784                         vmx->nested.pml_full = true;
11785                         return 1;
11786                 }
11787
11788                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11789
11790                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
11791                 if (is_error_page(page))
11792                         return 0;
11793
11794                 pml_address = kmap(page);
11795                 pml_address[vmcs12->guest_pml_index--] = gpa;
11796                 kunmap(page);
11797                 kvm_release_page_clean(page);
11798         }
11799
11800         return 0;
11801 }
11802
11803 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11804                                            struct kvm_memory_slot *memslot,
11805                                            gfn_t offset, unsigned long mask)
11806 {
11807         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11808 }
11809
11810 static void __pi_post_block(struct kvm_vcpu *vcpu)
11811 {
11812         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11813         struct pi_desc old, new;
11814         unsigned int dest;
11815
11816         do {
11817                 old.control = new.control = pi_desc->control;
11818                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
11819                      "Wakeup handler not enabled while the VCPU is blocked\n");
11820
11821                 dest = cpu_physical_id(vcpu->cpu);
11822
11823                 if (x2apic_enabled())
11824                         new.ndst = dest;
11825                 else
11826                         new.ndst = (dest << 8) & 0xFF00;
11827
11828                 /* set 'NV' to 'notification vector' */
11829                 new.nv = POSTED_INTR_VECTOR;
11830         } while (cmpxchg64(&pi_desc->control, old.control,
11831                            new.control) != old.control);
11832
11833         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
11834                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11835                 list_del(&vcpu->blocked_vcpu_list);
11836                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11837                 vcpu->pre_pcpu = -1;
11838         }
11839 }
11840
11841 /*
11842  * This routine does the following things for vCPU which is going
11843  * to be blocked if VT-d PI is enabled.
11844  * - Store the vCPU to the wakeup list, so when interrupts happen
11845  *   we can find the right vCPU to wake up.
11846  * - Change the Posted-interrupt descriptor as below:
11847  *      'NDST' <-- vcpu->pre_pcpu
11848  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11849  * - If 'ON' is set during this process, which means at least one
11850  *   interrupt is posted for this vCPU, we cannot block it, in
11851  *   this case, return 1, otherwise, return 0.
11852  *
11853  */
11854 static int pi_pre_block(struct kvm_vcpu *vcpu)
11855 {
11856         unsigned int dest;
11857         struct pi_desc old, new;
11858         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11859
11860         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11861                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11862                 !kvm_vcpu_apicv_active(vcpu))
11863                 return 0;
11864
11865         WARN_ON(irqs_disabled());
11866         local_irq_disable();
11867         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
11868                 vcpu->pre_pcpu = vcpu->cpu;
11869                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11870                 list_add_tail(&vcpu->blocked_vcpu_list,
11871                               &per_cpu(blocked_vcpu_on_cpu,
11872                                        vcpu->pre_pcpu));
11873                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11874         }
11875
11876         do {
11877                 old.control = new.control = pi_desc->control;
11878
11879                 WARN((pi_desc->sn == 1),
11880                      "Warning: SN field of posted-interrupts "
11881                      "is set before blocking\n");
11882
11883                 /*
11884                  * Since vCPU can be preempted during this process,
11885                  * vcpu->cpu could be different with pre_pcpu, we
11886                  * need to set pre_pcpu as the destination of wakeup
11887                  * notification event, then we can find the right vCPU
11888                  * to wakeup in wakeup handler if interrupts happen
11889                  * when the vCPU is in blocked state.
11890                  */
11891                 dest = cpu_physical_id(vcpu->pre_pcpu);
11892
11893                 if (x2apic_enabled())
11894                         new.ndst = dest;
11895                 else
11896                         new.ndst = (dest << 8) & 0xFF00;
11897
11898                 /* set 'NV' to 'wakeup vector' */
11899                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11900         } while (cmpxchg64(&pi_desc->control, old.control,
11901                            new.control) != old.control);
11902
11903         /* We should not block the vCPU if an interrupt is posted for it.  */
11904         if (pi_test_on(pi_desc) == 1)
11905                 __pi_post_block(vcpu);
11906
11907         local_irq_enable();
11908         return (vcpu->pre_pcpu == -1);
11909 }
11910
11911 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11912 {
11913         if (pi_pre_block(vcpu))
11914                 return 1;
11915
11916         if (kvm_lapic_hv_timer_in_use(vcpu))
11917                 kvm_lapic_switch_to_sw_timer(vcpu);
11918
11919         return 0;
11920 }
11921
11922 static void pi_post_block(struct kvm_vcpu *vcpu)
11923 {
11924         if (vcpu->pre_pcpu == -1)
11925                 return;
11926
11927         WARN_ON(irqs_disabled());
11928         local_irq_disable();
11929         __pi_post_block(vcpu);
11930         local_irq_enable();
11931 }
11932
11933 static void vmx_post_block(struct kvm_vcpu *vcpu)
11934 {
11935         if (kvm_x86_ops->set_hv_timer)
11936                 kvm_lapic_switch_to_hv_timer(vcpu);
11937
11938         pi_post_block(vcpu);
11939 }
11940
11941 /*
11942  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11943  *
11944  * @kvm: kvm
11945  * @host_irq: host irq of the interrupt
11946  * @guest_irq: gsi of the interrupt
11947  * @set: set or unset PI
11948  * returns 0 on success, < 0 on failure
11949  */
11950 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11951                               uint32_t guest_irq, bool set)
11952 {
11953         struct kvm_kernel_irq_routing_entry *e;
11954         struct kvm_irq_routing_table *irq_rt;
11955         struct kvm_lapic_irq irq;
11956         struct kvm_vcpu *vcpu;
11957         struct vcpu_data vcpu_info;
11958         int idx, ret = 0;
11959
11960         if (!kvm_arch_has_assigned_device(kvm) ||
11961                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11962                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11963                 return 0;
11964
11965         idx = srcu_read_lock(&kvm->irq_srcu);
11966         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11967         if (guest_irq >= irq_rt->nr_rt_entries ||
11968             hlist_empty(&irq_rt->map[guest_irq])) {
11969                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11970                              guest_irq, irq_rt->nr_rt_entries);
11971                 goto out;
11972         }
11973
11974         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11975                 if (e->type != KVM_IRQ_ROUTING_MSI)
11976                         continue;
11977                 /*
11978                  * VT-d PI cannot support posting multicast/broadcast
11979                  * interrupts to a vCPU, we still use interrupt remapping
11980                  * for these kind of interrupts.
11981                  *
11982                  * For lowest-priority interrupts, we only support
11983                  * those with single CPU as the destination, e.g. user
11984                  * configures the interrupts via /proc/irq or uses
11985                  * irqbalance to make the interrupts single-CPU.
11986                  *
11987                  * We will support full lowest-priority interrupt later.
11988                  */
11989
11990                 kvm_set_msi_irq(kvm, e, &irq);
11991                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11992                         /*
11993                          * Make sure the IRTE is in remapped mode if
11994                          * we don't handle it in posted mode.
11995                          */
11996                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11997                         if (ret < 0) {
11998                                 printk(KERN_INFO
11999                                    "failed to back to remapped mode, irq: %u\n",
12000                                    host_irq);
12001                                 goto out;
12002                         }
12003
12004                         continue;
12005                 }
12006
12007                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
12008                 vcpu_info.vector = irq.vector;
12009
12010                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
12011                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
12012
12013                 if (set)
12014                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
12015                 else
12016                         ret = irq_set_vcpu_affinity(host_irq, NULL);
12017
12018                 if (ret < 0) {
12019                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
12020                                         __func__);
12021                         goto out;
12022                 }
12023         }
12024
12025         ret = 0;
12026 out:
12027         srcu_read_unlock(&kvm->irq_srcu, idx);
12028         return ret;
12029 }
12030
12031 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
12032 {
12033         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
12034                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
12035                         FEATURE_CONTROL_LMCE;
12036         else
12037                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
12038                         ~FEATURE_CONTROL_LMCE;
12039 }
12040
12041 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
12042 {
12043         /* we need a nested vmexit to enter SMM, postpone if run is pending */
12044         if (to_vmx(vcpu)->nested.nested_run_pending)
12045                 return 0;
12046         return 1;
12047 }
12048
12049 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
12050 {
12051         struct vcpu_vmx *vmx = to_vmx(vcpu);
12052
12053         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
12054         if (vmx->nested.smm.guest_mode)
12055                 nested_vmx_vmexit(vcpu, -1, 0, 0);
12056
12057         vmx->nested.smm.vmxon = vmx->nested.vmxon;
12058         vmx->nested.vmxon = false;
12059         return 0;
12060 }
12061
12062 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
12063 {
12064         struct vcpu_vmx *vmx = to_vmx(vcpu);
12065         int ret;
12066
12067         if (vmx->nested.smm.vmxon) {
12068                 vmx->nested.vmxon = true;
12069                 vmx->nested.smm.vmxon = false;
12070         }
12071
12072         if (vmx->nested.smm.guest_mode) {
12073                 vcpu->arch.hflags &= ~HF_SMM_MASK;
12074                 ret = enter_vmx_non_root_mode(vcpu, false);
12075                 vcpu->arch.hflags |= HF_SMM_MASK;
12076                 if (ret)
12077                         return ret;
12078
12079                 vmx->nested.smm.guest_mode = false;
12080         }
12081         return 0;
12082 }
12083
12084 static int enable_smi_window(struct kvm_vcpu *vcpu)
12085 {
12086         return 0;
12087 }
12088
12089 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
12090         .cpu_has_kvm_support = cpu_has_kvm_support,
12091         .disabled_by_bios = vmx_disabled_by_bios,
12092         .hardware_setup = hardware_setup,
12093         .hardware_unsetup = hardware_unsetup,
12094         .check_processor_compatibility = vmx_check_processor_compat,
12095         .hardware_enable = hardware_enable,
12096         .hardware_disable = hardware_disable,
12097         .cpu_has_accelerated_tpr = report_flexpriority,
12098         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
12099
12100         .vcpu_create = vmx_create_vcpu,
12101         .vcpu_free = vmx_free_vcpu,
12102         .vcpu_reset = vmx_vcpu_reset,
12103
12104         .prepare_guest_switch = vmx_save_host_state,
12105         .vcpu_load = vmx_vcpu_load,
12106         .vcpu_put = vmx_vcpu_put,
12107
12108         .update_bp_intercept = update_exception_bitmap,
12109         .get_msr = vmx_get_msr,
12110         .set_msr = vmx_set_msr,
12111         .get_segment_base = vmx_get_segment_base,
12112         .get_segment = vmx_get_segment,
12113         .set_segment = vmx_set_segment,
12114         .get_cpl = vmx_get_cpl,
12115         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
12116         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
12117         .decache_cr3 = vmx_decache_cr3,
12118         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
12119         .set_cr0 = vmx_set_cr0,
12120         .set_cr3 = vmx_set_cr3,
12121         .set_cr4 = vmx_set_cr4,
12122         .set_efer = vmx_set_efer,
12123         .get_idt = vmx_get_idt,
12124         .set_idt = vmx_set_idt,
12125         .get_gdt = vmx_get_gdt,
12126         .set_gdt = vmx_set_gdt,
12127         .get_dr6 = vmx_get_dr6,
12128         .set_dr6 = vmx_set_dr6,
12129         .set_dr7 = vmx_set_dr7,
12130         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
12131         .cache_reg = vmx_cache_reg,
12132         .get_rflags = vmx_get_rflags,
12133         .set_rflags = vmx_set_rflags,
12134
12135         .tlb_flush = vmx_flush_tlb,
12136
12137         .run = vmx_vcpu_run,
12138         .handle_exit = vmx_handle_exit,
12139         .skip_emulated_instruction = skip_emulated_instruction,
12140         .set_interrupt_shadow = vmx_set_interrupt_shadow,
12141         .get_interrupt_shadow = vmx_get_interrupt_shadow,
12142         .patch_hypercall = vmx_patch_hypercall,
12143         .set_irq = vmx_inject_irq,
12144         .set_nmi = vmx_inject_nmi,
12145         .queue_exception = vmx_queue_exception,
12146         .cancel_injection = vmx_cancel_injection,
12147         .interrupt_allowed = vmx_interrupt_allowed,
12148         .nmi_allowed = vmx_nmi_allowed,
12149         .get_nmi_mask = vmx_get_nmi_mask,
12150         .set_nmi_mask = vmx_set_nmi_mask,
12151         .enable_nmi_window = enable_nmi_window,
12152         .enable_irq_window = enable_irq_window,
12153         .update_cr8_intercept = update_cr8_intercept,
12154         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
12155         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
12156         .get_enable_apicv = vmx_get_enable_apicv,
12157         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
12158         .load_eoi_exitmap = vmx_load_eoi_exitmap,
12159         .apicv_post_state_restore = vmx_apicv_post_state_restore,
12160         .hwapic_irr_update = vmx_hwapic_irr_update,
12161         .hwapic_isr_update = vmx_hwapic_isr_update,
12162         .sync_pir_to_irr = vmx_sync_pir_to_irr,
12163         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
12164
12165         .set_tss_addr = vmx_set_tss_addr,
12166         .get_tdp_level = get_ept_level,
12167         .get_mt_mask = vmx_get_mt_mask,
12168
12169         .get_exit_info = vmx_get_exit_info,
12170
12171         .get_lpage_level = vmx_get_lpage_level,
12172
12173         .cpuid_update = vmx_cpuid_update,
12174
12175         .rdtscp_supported = vmx_rdtscp_supported,
12176         .invpcid_supported = vmx_invpcid_supported,
12177
12178         .set_supported_cpuid = vmx_set_supported_cpuid,
12179
12180         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
12181
12182         .write_tsc_offset = vmx_write_tsc_offset,
12183
12184         .set_tdp_cr3 = vmx_set_cr3,
12185
12186         .check_intercept = vmx_check_intercept,
12187         .handle_external_intr = vmx_handle_external_intr,
12188         .mpx_supported = vmx_mpx_supported,
12189         .xsaves_supported = vmx_xsaves_supported,
12190
12191         .check_nested_events = vmx_check_nested_events,
12192
12193         .sched_in = vmx_sched_in,
12194
12195         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
12196         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
12197         .flush_log_dirty = vmx_flush_log_dirty,
12198         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
12199         .write_log_dirty = vmx_write_pml_buffer,
12200
12201         .pre_block = vmx_pre_block,
12202         .post_block = vmx_post_block,
12203
12204         .pmu_ops = &intel_pmu_ops,
12205
12206         .update_pi_irte = vmx_update_pi_irte,
12207
12208 #ifdef CONFIG_X86_64
12209         .set_hv_timer = vmx_set_hv_timer,
12210         .cancel_hv_timer = vmx_cancel_hv_timer,
12211 #endif
12212
12213         .setup_mce = vmx_setup_mce,
12214
12215         .smi_allowed = vmx_smi_allowed,
12216         .pre_enter_smm = vmx_pre_enter_smm,
12217         .pre_leave_smm = vmx_pre_leave_smm,
12218         .enable_smi_window = enable_smi_window,
12219 };
12220
12221 static int __init vmx_init(void)
12222 {
12223         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
12224                      __alignof__(struct vcpu_vmx), THIS_MODULE);
12225         if (r)
12226                 return r;
12227
12228 #ifdef CONFIG_KEXEC_CORE
12229         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
12230                            crash_vmclear_local_loaded_vmcss);
12231 #endif
12232
12233         return 0;
12234 }
12235
12236 static void __exit vmx_exit(void)
12237 {
12238 #ifdef CONFIG_KEXEC_CORE
12239         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
12240         synchronize_rcu();
12241 #endif
12242
12243         kvm_exit();
12244 }
12245
12246 module_init(vmx_init)
12247 module_exit(vmx_exit)