arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45
  46 #include "trace.h"
  47
  48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  49 #define __ex_clear(x, reg) \
  50         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  51
  52 MODULE_AUTHOR("Qumranet");
  53 MODULE_LICENSE("GPL");
  54
  55 static const struct x86_cpu_id vmx_cpu_id[] = {
  56         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  57         {}
  58 };
  59 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  60
  61 static bool __read_mostly enable_vpid = 1;
  62 module_param_named(vpid, enable_vpid, bool, 0444);
  63
  64 static bool __read_mostly flexpriority_enabled = 1;
  65 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  66
  67 static bool __read_mostly enable_ept = 1;
  68 module_param_named(ept, enable_ept, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_unrestricted_guest = 1;
  71 module_param_named(unrestricted_guest,
  72                         enable_unrestricted_guest, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept_ad_bits = 1;
  75 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  76
  77 static bool __read_mostly emulate_invalid_guest_state = true;
  78 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  79
  80 static bool __read_mostly vmm_exclusive = 1;
  81 module_param(vmm_exclusive, bool, S_IRUGO);
  82
  83 static bool __read_mostly fasteoi = 1;
  84 module_param(fasteoi, bool, S_IRUGO);
  85
  86 /*
  87  * If nested=1, nested virtualization is supported, i.e., guests may use
  88  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  89  * use VMX instructions.
  90  */
  91 static bool __read_mostly nested = 0;
  92 module_param(nested, bool, S_IRUGO);
  93
  94 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  95         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  96 #define KVM_GUEST_CR0_MASK                                              \
  97         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  99         (X86_CR0_WP | X86_CR0_NE)
 100 #define KVM_VM_CR0_ALWAYS_ON                                            \
 101         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 102 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 103         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 104          | X86_CR4_OSXMMEXCPT)
 105
 106 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 107 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 108
 109 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 110
 111 /*
 112  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 113  * ple_gap:    upper bound on the amount of time between two successive
 114  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 115  *             According to test, this time is usually smaller than 128 cycles.
 116  * ple_window: upper bound on the amount of time a guest is allowed to execute
 117  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 118  *             less than 2^12 cycles
 119  * Time is measured based on a counter that runs at the same rate as the TSC,
 120  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 121  */
 122 #define KVM_VMX_DEFAULT_PLE_GAP    128
 123 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 124 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 125 module_param(ple_gap, int, S_IRUGO);
 126
 127 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 128 module_param(ple_window, int, S_IRUGO);
 129
 130 extern const ulong vmx_return;
 131
 132 #define NR_AUTOLOAD_MSRS 8
 133 #define VMCS02_POOL_SIZE 1
 134
 135 struct vmcs {
 136         u32 revision_id;
 137         u32 abort;
 138         char data[0];
 139 };
 140
 141 /*
 142  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 143  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 144  * loaded on this CPU (so we can clear them if the CPU goes down).
 145  */
 146 struct loaded_vmcs {
 147         struct vmcs *vmcs;
 148         int cpu;
 149         int launched;
 150         struct list_head loaded_vmcss_on_cpu_link;
 151 };
 152
 153 struct shared_msr_entry {
 154         unsigned index;
 155         u64 data;
 156         u64 mask;
 157 };
 158
 159 /*
 160  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 161  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 162  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 163  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 164  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 165  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 166  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 167  * underlying hardware which will be used to run L2.
 168  * This structure is packed to ensure that its layout is identical across
 169  * machines (necessary for live migration).
 170  * If there are changes in this struct, VMCS12_REVISION must be changed.
 171  */
 172 typedef u64 natural_width;
 173 struct __packed vmcs12 {
 174         /* According to the Intel spec, a VMCS region must start with the
 175          * following two fields. Then follow implementation-specific data.
 176          */
 177         u32 revision_id;
 178         u32 abort;
 179
 180         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 181         u32 padding[7]; /* room for future expansion */
 182
 183         u64 io_bitmap_a;
 184         u64 io_bitmap_b;
 185         u64 msr_bitmap;
 186         u64 vm_exit_msr_store_addr;
 187         u64 vm_exit_msr_load_addr;
 188         u64 vm_entry_msr_load_addr;
 189         u64 tsc_offset;
 190         u64 virtual_apic_page_addr;
 191         u64 apic_access_addr;
 192         u64 ept_pointer;
 193         u64 guest_physical_address;
 194         u64 vmcs_link_pointer;
 195         u64 guest_ia32_debugctl;
 196         u64 guest_ia32_pat;
 197         u64 guest_ia32_efer;
 198         u64 guest_ia32_perf_global_ctrl;
 199         u64 guest_pdptr0;
 200         u64 guest_pdptr1;
 201         u64 guest_pdptr2;
 202         u64 guest_pdptr3;
 203         u64 host_ia32_pat;
 204         u64 host_ia32_efer;
 205         u64 host_ia32_perf_global_ctrl;
 206         u64 padding64[8]; /* room for future expansion */
 207         /*
 208          * To allow migration of L1 (complete with its L2 guests) between
 209          * machines of different natural widths (32 or 64 bit), we cannot have
 210          * unsigned long fields with no explict size. We use u64 (aliased
 211          * natural_width) instead. Luckily, x86 is little-endian.
 212          */
 213         natural_width cr0_guest_host_mask;
 214         natural_width cr4_guest_host_mask;
 215         natural_width cr0_read_shadow;
 216         natural_width cr4_read_shadow;
 217         natural_width cr3_target_value0;
 218         natural_width cr3_target_value1;
 219         natural_width cr3_target_value2;
 220         natural_width cr3_target_value3;
 221         natural_width exit_qualification;
 222         natural_width guest_linear_address;
 223         natural_width guest_cr0;
 224         natural_width guest_cr3;
 225         natural_width guest_cr4;
 226         natural_width guest_es_base;
 227         natural_width guest_cs_base;
 228         natural_width guest_ss_base;
 229         natural_width guest_ds_base;
 230         natural_width guest_fs_base;
 231         natural_width guest_gs_base;
 232         natural_width guest_ldtr_base;
 233         natural_width guest_tr_base;
 234         natural_width guest_gdtr_base;
 235         natural_width guest_idtr_base;
 236         natural_width guest_dr7;
 237         natural_width guest_rsp;
 238         natural_width guest_rip;
 239         natural_width guest_rflags;
 240         natural_width guest_pending_dbg_exceptions;
 241         natural_width guest_sysenter_esp;
 242         natural_width guest_sysenter_eip;
 243         natural_width host_cr0;
 244         natural_width host_cr3;
 245         natural_width host_cr4;
 246         natural_width host_fs_base;
 247         natural_width host_gs_base;
 248         natural_width host_tr_base;
 249         natural_width host_gdtr_base;
 250         natural_width host_idtr_base;
 251         natural_width host_ia32_sysenter_esp;
 252         natural_width host_ia32_sysenter_eip;
 253         natural_width host_rsp;
 254         natural_width host_rip;
 255         natural_width paddingl[8]; /* room for future expansion */
 256         u32 pin_based_vm_exec_control;
 257         u32 cpu_based_vm_exec_control;
 258         u32 exception_bitmap;
 259         u32 page_fault_error_code_mask;
 260         u32 page_fault_error_code_match;
 261         u32 cr3_target_count;
 262         u32 vm_exit_controls;
 263         u32 vm_exit_msr_store_count;
 264         u32 vm_exit_msr_load_count;
 265         u32 vm_entry_controls;
 266         u32 vm_entry_msr_load_count;
 267         u32 vm_entry_intr_info_field;
 268         u32 vm_entry_exception_error_code;
 269         u32 vm_entry_instruction_len;
 270         u32 tpr_threshold;
 271         u32 secondary_vm_exec_control;
 272         u32 vm_instruction_error;
 273         u32 vm_exit_reason;
 274         u32 vm_exit_intr_info;
 275         u32 vm_exit_intr_error_code;
 276         u32 idt_vectoring_info_field;
 277         u32 idt_vectoring_error_code;
 278         u32 vm_exit_instruction_len;
 279         u32 vmx_instruction_info;
 280         u32 guest_es_limit;
 281         u32 guest_cs_limit;
 282         u32 guest_ss_limit;
 283         u32 guest_ds_limit;
 284         u32 guest_fs_limit;
 285         u32 guest_gs_limit;
 286         u32 guest_ldtr_limit;
 287         u32 guest_tr_limit;
 288         u32 guest_gdtr_limit;
 289         u32 guest_idtr_limit;
 290         u32 guest_es_ar_bytes;
 291         u32 guest_cs_ar_bytes;
 292         u32 guest_ss_ar_bytes;
 293         u32 guest_ds_ar_bytes;
 294         u32 guest_fs_ar_bytes;
 295         u32 guest_gs_ar_bytes;
 296         u32 guest_ldtr_ar_bytes;
 297         u32 guest_tr_ar_bytes;
 298         u32 guest_interruptibility_info;
 299         u32 guest_activity_state;
 300         u32 guest_sysenter_cs;
 301         u32 host_ia32_sysenter_cs;
 302         u32 padding32[8]; /* room for future expansion */
 303         u16 virtual_processor_id;
 304         u16 guest_es_selector;
 305         u16 guest_cs_selector;
 306         u16 guest_ss_selector;
 307         u16 guest_ds_selector;
 308         u16 guest_fs_selector;
 309         u16 guest_gs_selector;
 310         u16 guest_ldtr_selector;
 311         u16 guest_tr_selector;
 312         u16 host_es_selector;
 313         u16 host_cs_selector;
 314         u16 host_ss_selector;
 315         u16 host_ds_selector;
 316         u16 host_fs_selector;
 317         u16 host_gs_selector;
 318         u16 host_tr_selector;
 319 };
 320
 321 /*
 322  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 323  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 324  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 325  */
 326 #define VMCS12_REVISION 0x11e57ed0
 327
 328 /*
 329  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 330  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 331  * current implementation, 4K are reserved to avoid future complications.
 332  */
 333 #define VMCS12_SIZE 0x1000
 334
 335 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 336 struct vmcs02_list {
 337         struct list_head list;
 338         gpa_t vmptr;
 339         struct loaded_vmcs vmcs02;
 340 };
 341
 342 /*
 343  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 344  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 345  */
 346 struct nested_vmx {
 347         /* Has the level1 guest done vmxon? */
 348         bool vmxon;
 349
 350         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 351         gpa_t current_vmptr;
 352         /* The host-usable pointer to the above */
 353         struct page *current_vmcs12_page;
 354         struct vmcs12 *current_vmcs12;
 355
 356         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 357         struct list_head vmcs02_pool;
 358         int vmcs02_num;
 359         u64 vmcs01_tsc_offset;
 360         /* L2 must run next, and mustn't decide to exit to L1. */
 361         bool nested_run_pending;
 362         /*
 363          * Guest pages referred to in vmcs02 with host-physical pointers, so
 364          * we must keep them pinned while L2 runs.
 365          */
 366         struct page *apic_access_page;
 367 };
 368
 369 struct vcpu_vmx {
 370         struct kvm_vcpu       vcpu;
 371         unsigned long         host_rsp;
 372         u8                    fail;
 373         u8                    cpl;
 374         bool                  nmi_known_unmasked;
 375         u32                   exit_intr_info;
 376         u32                   idt_vectoring_info;
 377         ulong                 rflags;
 378         struct shared_msr_entry *guest_msrs;
 379         int                   nmsrs;
 380         int                   save_nmsrs;
 381 #ifdef CONFIG_X86_64
 382         u64                   msr_host_kernel_gs_base;
 383         u64                   msr_guest_kernel_gs_base;
 384 #endif
 385         /*
 386          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 387          * non-nested (L1) guest, it always points to vmcs01. For a nested
 388          * guest (L2), it points to a different VMCS.
 389          */
 390         struct loaded_vmcs    vmcs01;
 391         struct loaded_vmcs   *loaded_vmcs;
 392         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 393         struct msr_autoload {
 394                 unsigned nr;
 395                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 396                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 397         } msr_autoload;
 398         struct {
 399                 int           loaded;
 400                 u16           fs_sel, gs_sel, ldt_sel;
 401 #ifdef CONFIG_X86_64
 402                 u16           ds_sel, es_sel;
 403 #endif
 404                 int           gs_ldt_reload_needed;
 405                 int           fs_reload_needed;
 406         } host_state;
 407         struct {
 408                 int vm86_active;
 409                 ulong save_rflags;
 410                 struct kvm_segment segs[8];
 411         } rmode;
 412         struct {
 413                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 414                 struct kvm_save_segment {
 415                         u16 selector;
 416                         unsigned long base;
 417                         u32 limit;
 418                         u32 ar;
 419                 } seg[8];
 420         } segment_cache;
 421         int vpid;
 422         bool emulation_required;
 423
 424         /* Support for vnmi-less CPUs */
 425         int soft_vnmi_blocked;
 426         ktime_t entry_time;
 427         s64 vnmi_blocked_time;
 428         u32 exit_reason;
 429
 430         bool rdtscp_enabled;
 431
 432         /* Support for a guest hypervisor (nested VMX) */
 433         struct nested_vmx nested;
 434 };
 435
 436 enum segment_cache_field {
 437         SEG_FIELD_SEL = 0,
 438         SEG_FIELD_BASE = 1,
 439         SEG_FIELD_LIMIT = 2,
 440         SEG_FIELD_AR = 3,
 441
 442         SEG_FIELD_NR = 4
 443 };
 444
 445 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 446 {
 447         return container_of(vcpu, struct vcpu_vmx, vcpu);
 448 }
 449
 450 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 451 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 452 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 453                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 454
 455 static const unsigned short vmcs_field_to_offset_table[] = {
 456         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 457         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 458         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 459         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 460         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 461         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 462         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 463         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 464         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 465         FIELD(HOST_ES_SELECTOR, host_es_selector),
 466         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 467         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 468         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 469         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 470         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 471         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 472         FIELD64(IO_BITMAP_A, io_bitmap_a),
 473         FIELD64(IO_BITMAP_B, io_bitmap_b),
 474         FIELD64(MSR_BITMAP, msr_bitmap),
 475         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 476         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 477         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 478         FIELD64(TSC_OFFSET, tsc_offset),
 479         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 480         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 481         FIELD64(EPT_POINTER, ept_pointer),
 482         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 483         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 484         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 485         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 486         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 487         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 488         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 489         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 490         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 491         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 492         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 493         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 494         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 495         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 496         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 497         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 498         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 499         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 500         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 501         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 502         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 503         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 504         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 505         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 506         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 507         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 508         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 509         FIELD(TPR_THRESHOLD, tpr_threshold),
 510         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 511         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 512         FIELD(VM_EXIT_REASON, vm_exit_reason),
 513         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 514         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 515         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 516         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 517         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 518         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 519         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 520         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 521         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 522         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 523         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 524         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 525         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 526         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 527         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 528         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 529         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 530         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 531         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 532         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 533         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 534         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 535         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 536         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 537         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 538         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 539         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 540         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 541         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 542         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 543         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 544         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 545         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 546         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 547         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 548         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 549         FIELD(EXIT_QUALIFICATION, exit_qualification),
 550         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 551         FIELD(GUEST_CR0, guest_cr0),
 552         FIELD(GUEST_CR3, guest_cr3),
 553         FIELD(GUEST_CR4, guest_cr4),
 554         FIELD(GUEST_ES_BASE, guest_es_base),
 555         FIELD(GUEST_CS_BASE, guest_cs_base),
 556         FIELD(GUEST_SS_BASE, guest_ss_base),
 557         FIELD(GUEST_DS_BASE, guest_ds_base),
 558         FIELD(GUEST_FS_BASE, guest_fs_base),
 559         FIELD(GUEST_GS_BASE, guest_gs_base),
 560         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 561         FIELD(GUEST_TR_BASE, guest_tr_base),
 562         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 563         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 564         FIELD(GUEST_DR7, guest_dr7),
 565         FIELD(GUEST_RSP, guest_rsp),
 566         FIELD(GUEST_RIP, guest_rip),
 567         FIELD(GUEST_RFLAGS, guest_rflags),
 568         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 569         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 570         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 571         FIELD(HOST_CR0, host_cr0),
 572         FIELD(HOST_CR3, host_cr3),
 573         FIELD(HOST_CR4, host_cr4),
 574         FIELD(HOST_FS_BASE, host_fs_base),
 575         FIELD(HOST_GS_BASE, host_gs_base),
 576         FIELD(HOST_TR_BASE, host_tr_base),
 577         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 578         FIELD(HOST_IDTR_BASE, host_idtr_base),
 579         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 580         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 581         FIELD(HOST_RSP, host_rsp),
 582         FIELD(HOST_RIP, host_rip),
 583 };
 584 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 585
 586 static inline short vmcs_field_to_offset(unsigned long field)
 587 {
 588         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 589                 return -1;
 590         return vmcs_field_to_offset_table[field];
 591 }
 592
 593 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 594 {
 595         return to_vmx(vcpu)->nested.current_vmcs12;
 596 }
 597
 598 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 599 {
 600         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 601         if (is_error_page(page))
 602                 return NULL;
 603
 604         return page;
 605 }
 606
 607 static void nested_release_page(struct page *page)
 608 {
 609         kvm_release_page_dirty(page);
 610 }
 611
 612 static void nested_release_page_clean(struct page *page)
 613 {
 614         kvm_release_page_clean(page);
 615 }
 616
 617 static u64 construct_eptp(unsigned long root_hpa);
 618 static void kvm_cpu_vmxon(u64 addr);
 619 static void kvm_cpu_vmxoff(void);
 620 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 621 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 622 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 623                             struct kvm_segment *var, int seg);
 624 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 625                             struct kvm_segment *var, int seg);
 626
 627 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 628 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 629 /*
 630  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 631  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 632  */
 633 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 634 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 635
 636 static unsigned long *vmx_io_bitmap_a;
 637 static unsigned long *vmx_io_bitmap_b;
 638 static unsigned long *vmx_msr_bitmap_legacy;
 639 static unsigned long *vmx_msr_bitmap_longmode;
 640
 641 static bool cpu_has_load_ia32_efer;
 642 static bool cpu_has_load_perf_global_ctrl;
 643
 644 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 645 static DEFINE_SPINLOCK(vmx_vpid_lock);
 646
 647 static struct vmcs_config {
 648         int size;
 649         int order;
 650         u32 revision_id;
 651         u32 pin_based_exec_ctrl;
 652         u32 cpu_based_exec_ctrl;
 653         u32 cpu_based_2nd_exec_ctrl;
 654         u32 vmexit_ctrl;
 655         u32 vmentry_ctrl;
 656 } vmcs_config;
 657
 658 static struct vmx_capability {
 659         u32 ept;
 660         u32 vpid;
 661 } vmx_capability;
 662
 663 #define VMX_SEGMENT_FIELD(seg)                                  \
 664         [VCPU_SREG_##seg] = {                                   \
 665                 .selector = GUEST_##seg##_SELECTOR,             \
 666                 .base = GUEST_##seg##_BASE,                     \
 667                 .limit = GUEST_##seg##_LIMIT,                   \
 668                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 669         }
 670
 671 static const struct kvm_vmx_segment_field {
 672         unsigned selector;
 673         unsigned base;
 674         unsigned limit;
 675         unsigned ar_bytes;
 676 } kvm_vmx_segment_fields[] = {
 677         VMX_SEGMENT_FIELD(CS),
 678         VMX_SEGMENT_FIELD(DS),
 679         VMX_SEGMENT_FIELD(ES),
 680         VMX_SEGMENT_FIELD(FS),
 681         VMX_SEGMENT_FIELD(GS),
 682         VMX_SEGMENT_FIELD(SS),
 683         VMX_SEGMENT_FIELD(TR),
 684         VMX_SEGMENT_FIELD(LDTR),
 685 };
 686
 687 static u64 host_efer;
 688
 689 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 690
 691 /*
 692  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 693  * away by decrementing the array size.
 694  */
 695 static const u32 vmx_msr_index[] = {
 696 #ifdef CONFIG_X86_64
 697         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 698 #endif
 699         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 700 };
 701 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 702
 703 static inline bool is_page_fault(u32 intr_info)
 704 {
 705         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 706                              INTR_INFO_VALID_MASK)) ==
 707                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 708 }
 709
 710 static inline bool is_no_device(u32 intr_info)
 711 {
 712         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 713                              INTR_INFO_VALID_MASK)) ==
 714                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 715 }
 716
 717 static inline bool is_invalid_opcode(u32 intr_info)
 718 {
 719         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 720                              INTR_INFO_VALID_MASK)) ==
 721                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 722 }
 723
 724 static inline bool is_external_interrupt(u32 intr_info)
 725 {
 726         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 727                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 728 }
 729
 730 static inline bool is_machine_check(u32 intr_info)
 731 {
 732         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 733                              INTR_INFO_VALID_MASK)) ==
 734                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 735 }
 736
 737 static inline bool cpu_has_vmx_msr_bitmap(void)
 738 {
 739         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 740 }
 741
 742 static inline bool cpu_has_vmx_tpr_shadow(void)
 743 {
 744         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 745 }
 746
 747 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 748 {
 749         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 750 }
 751
 752 static inline bool cpu_has_secondary_exec_ctrls(void)
 753 {
 754         return vmcs_config.cpu_based_exec_ctrl &
 755                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 756 }
 757
 758 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 759 {
 760         return vmcs_config.cpu_based_2nd_exec_ctrl &
 761                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 762 }
 763
 764 static inline bool cpu_has_vmx_flexpriority(void)
 765 {
 766         return cpu_has_vmx_tpr_shadow() &&
 767                 cpu_has_vmx_virtualize_apic_accesses();
 768 }
 769
 770 static inline bool cpu_has_vmx_ept_execute_only(void)
 771 {
 772         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 773 }
 774
 775 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 776 {
 777         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 778 }
 779
 780 static inline bool cpu_has_vmx_eptp_writeback(void)
 781 {
 782         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 783 }
 784
 785 static inline bool cpu_has_vmx_ept_2m_page(void)
 786 {
 787         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 788 }
 789
 790 static inline bool cpu_has_vmx_ept_1g_page(void)
 791 {
 792         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 793 }
 794
 795 static inline bool cpu_has_vmx_ept_4levels(void)
 796 {
 797         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 798 }
 799
 800 static inline bool cpu_has_vmx_ept_ad_bits(void)
 801 {
 802         return vmx_capability.ept & VMX_EPT_AD_BIT;
 803 }
 804
 805 static inline bool cpu_has_vmx_invept_individual_addr(void)
 806 {
 807         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 808 }
 809
 810 static inline bool cpu_has_vmx_invept_context(void)
 811 {
 812         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 813 }
 814
 815 static inline bool cpu_has_vmx_invept_global(void)
 816 {
 817         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 818 }
 819
 820 static inline bool cpu_has_vmx_invvpid_single(void)
 821 {
 822         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 823 }
 824
 825 static inline bool cpu_has_vmx_invvpid_global(void)
 826 {
 827         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 828 }
 829
 830 static inline bool cpu_has_vmx_ept(void)
 831 {
 832         return vmcs_config.cpu_based_2nd_exec_ctrl &
 833                 SECONDARY_EXEC_ENABLE_EPT;
 834 }
 835
 836 static inline bool cpu_has_vmx_unrestricted_guest(void)
 837 {
 838         return vmcs_config.cpu_based_2nd_exec_ctrl &
 839                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 840 }
 841
 842 static inline bool cpu_has_vmx_ple(void)
 843 {
 844         return vmcs_config.cpu_based_2nd_exec_ctrl &
 845                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 846 }
 847
 848 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 849 {
 850         return flexpriority_enabled && irqchip_in_kernel(kvm);
 851 }
 852
 853 static inline bool cpu_has_vmx_vpid(void)
 854 {
 855         return vmcs_config.cpu_based_2nd_exec_ctrl &
 856                 SECONDARY_EXEC_ENABLE_VPID;
 857 }
 858
 859 static inline bool cpu_has_vmx_rdtscp(void)
 860 {
 861         return vmcs_config.cpu_based_2nd_exec_ctrl &
 862                 SECONDARY_EXEC_RDTSCP;
 863 }
 864
 865 static inline bool cpu_has_vmx_invpcid(void)
 866 {
 867         return vmcs_config.cpu_based_2nd_exec_ctrl &
 868                 SECONDARY_EXEC_ENABLE_INVPCID;
 869 }
 870
 871 static inline bool cpu_has_virtual_nmis(void)
 872 {
 873         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 874 }
 875
 876 static inline bool cpu_has_vmx_wbinvd_exit(void)
 877 {
 878         return vmcs_config.cpu_based_2nd_exec_ctrl &
 879                 SECONDARY_EXEC_WBINVD_EXITING;
 880 }
 881
 882 static inline bool report_flexpriority(void)
 883 {
 884         return flexpriority_enabled;
 885 }
 886
 887 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 888 {
 889         return vmcs12->cpu_based_vm_exec_control & bit;
 890 }
 891
 892 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 893 {
 894         return (vmcs12->cpu_based_vm_exec_control &
 895                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 896                 (vmcs12->secondary_vm_exec_control & bit);
 897 }
 898
 899 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 900         struct kvm_vcpu *vcpu)
 901 {
 902         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 903 }
 904
 905 static inline bool is_exception(u32 intr_info)
 906 {
 907         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 908                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 909 }
 910
 911 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 912 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 913                         struct vmcs12 *vmcs12,
 914                         u32 reason, unsigned long qualification);
 915
 916 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 917 {
 918         int i;
 919
 920         for (i = 0; i < vmx->nmsrs; ++i)
 921                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 922                         return i;
 923         return -1;
 924 }
 925
 926 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 927 {
 928     struct {
 929         u64 vpid : 16;
 930         u64 rsvd : 48;
 931         u64 gva;
 932     } operand = { vpid, 0, gva };
 933
 934     asm volatile (__ex(ASM_VMX_INVVPID)
 935                   /* CF==1 or ZF==1 --> rc = -1 */
 936                   "; ja 1f ; ud2 ; 1:"
 937                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 938 }
 939
 940 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 941 {
 942         struct {
 943                 u64 eptp, gpa;
 944         } operand = {eptp, gpa};
 945
 946         asm volatile (__ex(ASM_VMX_INVEPT)
 947                         /* CF==1 or ZF==1 --> rc = -1 */
 948                         "; ja 1f ; ud2 ; 1:\n"
 949                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 950 }
 951
 952 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 953 {
 954         int i;
 955
 956         i = __find_msr_index(vmx, msr);
 957         if (i >= 0)
 958                 return &vmx->guest_msrs[i];
 959         return NULL;
 960 }
 961
 962 static void vmcs_clear(struct vmcs *vmcs)
 963 {
 964         u64 phys_addr = __pa(vmcs);
 965         u8 error;
 966
 967         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 968                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 969                       : "cc", "memory");
 970         if (error)
 971                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 972                        vmcs, phys_addr);
 973 }
 974
 975 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 976 {
 977         vmcs_clear(loaded_vmcs->vmcs);
 978         loaded_vmcs->cpu = -1;
 979         loaded_vmcs->launched = 0;
 980 }
 981
 982 static void vmcs_load(struct vmcs *vmcs)
 983 {
 984         u64 phys_addr = __pa(vmcs);
 985         u8 error;
 986
 987         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 988                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 989                         : "cc", "memory");
 990         if (error)
 991                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 992                        vmcs, phys_addr);
 993 }
 994
 995 static void __loaded_vmcs_clear(void *arg)
 996 {
 997         struct loaded_vmcs *loaded_vmcs = arg;
 998         int cpu = raw_smp_processor_id();
 999
1000         if (loaded_vmcs->cpu != cpu)
1001                 return; /* vcpu migration can race with cpu offline */
1002         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1003                 per_cpu(current_vmcs, cpu) = NULL;
1004         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1005         loaded_vmcs_init(loaded_vmcs);
1006 }
1007
1008 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1009 {
1010         if (loaded_vmcs->cpu != -1)
1011                 smp_call_function_single(
1012                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
1013 }
1014
1015 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1016 {
1017         if (vmx->vpid == 0)
1018                 return;
1019
1020         if (cpu_has_vmx_invvpid_single())
1021                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1022 }
1023
1024 static inline void vpid_sync_vcpu_global(void)
1025 {
1026         if (cpu_has_vmx_invvpid_global())
1027                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1028 }
1029
1030 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1031 {
1032         if (cpu_has_vmx_invvpid_single())
1033                 vpid_sync_vcpu_single(vmx);
1034         else
1035                 vpid_sync_vcpu_global();
1036 }
1037
1038 static inline void ept_sync_global(void)
1039 {
1040         if (cpu_has_vmx_invept_global())
1041                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1042 }
1043
1044 static inline void ept_sync_context(u64 eptp)
1045 {
1046         if (enable_ept) {
1047                 if (cpu_has_vmx_invept_context())
1048                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1049                 else
1050                         ept_sync_global();
1051         }
1052 }
1053
1054 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1055 {
1056         if (enable_ept) {
1057                 if (cpu_has_vmx_invept_individual_addr())
1058                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1059                                         eptp, gpa);
1060                 else
1061                         ept_sync_context(eptp);
1062         }
1063 }
1064
1065 static __always_inline unsigned long vmcs_readl(unsigned long field)
1066 {
1067         unsigned long value;
1068
1069         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1070                       : "=a"(value) : "d"(field) : "cc");
1071         return value;
1072 }
1073
1074 static __always_inline u16 vmcs_read16(unsigned long field)
1075 {
1076         return vmcs_readl(field);
1077 }
1078
1079 static __always_inline u32 vmcs_read32(unsigned long field)
1080 {
1081         return vmcs_readl(field);
1082 }
1083
1084 static __always_inline u64 vmcs_read64(unsigned long field)
1085 {
1086 #ifdef CONFIG_X86_64
1087         return vmcs_readl(field);
1088 #else
1089         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1090 #endif
1091 }
1092
1093 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1094 {
1095         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1096                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1097         dump_stack();
1098 }
1099
1100 static void vmcs_writel(unsigned long field, unsigned long value)
1101 {
1102         u8 error;
1103
1104         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1105                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1106         if (unlikely(error))
1107                 vmwrite_error(field, value);
1108 }
1109
1110 static void vmcs_write16(unsigned long field, u16 value)
1111 {
1112         vmcs_writel(field, value);
1113 }
1114
1115 static void vmcs_write32(unsigned long field, u32 value)
1116 {
1117         vmcs_writel(field, value);
1118 }
1119
1120 static void vmcs_write64(unsigned long field, u64 value)
1121 {
1122         vmcs_writel(field, value);
1123 #ifndef CONFIG_X86_64
1124         asm volatile ("");
1125         vmcs_writel(field+1, value >> 32);
1126 #endif
1127 }
1128
1129 static void vmcs_clear_bits(unsigned long field, u32 mask)
1130 {
1131         vmcs_writel(field, vmcs_readl(field) & ~mask);
1132 }
1133
1134 static void vmcs_set_bits(unsigned long field, u32 mask)
1135 {
1136         vmcs_writel(field, vmcs_readl(field) | mask);
1137 }
1138
1139 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1140 {
1141         vmx->segment_cache.bitmask = 0;
1142 }
1143
1144 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1145                                        unsigned field)
1146 {
1147         bool ret;
1148         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1149
1150         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1151                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1152                 vmx->segment_cache.bitmask = 0;
1153         }
1154         ret = vmx->segment_cache.bitmask & mask;
1155         vmx->segment_cache.bitmask |= mask;
1156         return ret;
1157 }
1158
1159 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1160 {
1161         u16 *p = &vmx->segment_cache.seg[seg].selector;
1162
1163         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1164                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1165         return *p;
1166 }
1167
1168 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1169 {
1170         ulong *p = &vmx->segment_cache.seg[seg].base;
1171
1172         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1173                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1174         return *p;
1175 }
1176
1177 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1178 {
1179         u32 *p = &vmx->segment_cache.seg[seg].limit;
1180
1181         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1182                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1183         return *p;
1184 }
1185
1186 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1187 {
1188         u32 *p = &vmx->segment_cache.seg[seg].ar;
1189
1190         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1191                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1192         return *p;
1193 }
1194
1195 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1196 {
1197         u32 eb;
1198
1199         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1200              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1201         if ((vcpu->guest_debug &
1202              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1203             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1204                 eb |= 1u << BP_VECTOR;
1205         if (to_vmx(vcpu)->rmode.vm86_active)
1206                 eb = ~0;
1207         if (enable_ept)
1208                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1209         if (vcpu->fpu_active)
1210                 eb &= ~(1u << NM_VECTOR);
1211
1212         /* When we are running a nested L2 guest and L1 specified for it a
1213          * certain exception bitmap, we must trap the same exceptions and pass
1214          * them to L1. When running L2, we will only handle the exceptions
1215          * specified above if L1 did not want them.
1216          */
1217         if (is_guest_mode(vcpu))
1218                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1219
1220         vmcs_write32(EXCEPTION_BITMAP, eb);
1221 }
1222
1223 static void clear_atomic_switch_msr_special(unsigned long entry,
1224                 unsigned long exit)
1225 {
1226         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1227         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1228 }
1229
1230 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1231 {
1232         unsigned i;
1233         struct msr_autoload *m = &vmx->msr_autoload;
1234
1235         switch (msr) {
1236         case MSR_EFER:
1237                 if (cpu_has_load_ia32_efer) {
1238                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1239                                         VM_EXIT_LOAD_IA32_EFER);
1240                         return;
1241                 }
1242                 break;
1243         case MSR_CORE_PERF_GLOBAL_CTRL:
1244                 if (cpu_has_load_perf_global_ctrl) {
1245                         clear_atomic_switch_msr_special(
1246                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1247                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1248                         return;
1249                 }
1250                 break;
1251         }
1252
1253         for (i = 0; i < m->nr; ++i)
1254                 if (m->guest[i].index == msr)
1255                         break;
1256
1257         if (i == m->nr)
1258                 return;
1259         --m->nr;
1260         m->guest[i] = m->guest[m->nr];
1261         m->host[i] = m->host[m->nr];
1262         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1263         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1264 }
1265
1266 static void add_atomic_switch_msr_special(unsigned long entry,
1267                 unsigned long exit, unsigned long guest_val_vmcs,
1268                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1269 {
1270         vmcs_write64(guest_val_vmcs, guest_val);
1271         vmcs_write64(host_val_vmcs, host_val);
1272         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1273         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1274 }
1275
1276 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1277                                   u64 guest_val, u64 host_val)
1278 {
1279         unsigned i;
1280         struct msr_autoload *m = &vmx->msr_autoload;
1281
1282         switch (msr) {
1283         case MSR_EFER:
1284                 if (cpu_has_load_ia32_efer) {
1285                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1286                                         VM_EXIT_LOAD_IA32_EFER,
1287                                         GUEST_IA32_EFER,
1288                                         HOST_IA32_EFER,
1289                                         guest_val, host_val);
1290                         return;
1291                 }
1292                 break;
1293         case MSR_CORE_PERF_GLOBAL_CTRL:
1294                 if (cpu_has_load_perf_global_ctrl) {
1295                         add_atomic_switch_msr_special(
1296                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1297                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1298                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1299                                         HOST_IA32_PERF_GLOBAL_CTRL,
1300                                         guest_val, host_val);
1301                         return;
1302                 }
1303                 break;
1304         }
1305
1306         for (i = 0; i < m->nr; ++i)
1307                 if (m->guest[i].index == msr)
1308                         break;
1309
1310         if (i == NR_AUTOLOAD_MSRS) {
1311                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1312                                 "Can't add msr %x\n", msr);
1313                 return;
1314         } else if (i == m->nr) {
1315                 ++m->nr;
1316                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1317                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1318         }
1319
1320         m->guest[i].index = msr;
1321         m->guest[i].value = guest_val;
1322         m->host[i].index = msr;
1323         m->host[i].value = host_val;
1324 }
1325
1326 static void reload_tss(void)
1327 {
1328         /*
1329          * VT restores TR but not its size.  Useless.
1330          */
1331         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1332         struct desc_struct *descs;
1333
1334         descs = (void *)gdt->address;
1335         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1336         load_TR_desc();
1337 }
1338
1339 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1340 {
1341         u64 guest_efer;
1342         u64 ignore_bits;
1343
1344         guest_efer = vmx->vcpu.arch.efer;
1345
1346         /*
1347          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1348          * outside long mode
1349          */
1350         ignore_bits = EFER_NX | EFER_SCE;
1351 #ifdef CONFIG_X86_64
1352         ignore_bits |= EFER_LMA | EFER_LME;
1353         /* SCE is meaningful only in long mode on Intel */
1354         if (guest_efer & EFER_LMA)
1355                 ignore_bits &= ~(u64)EFER_SCE;
1356 #endif
1357         guest_efer &= ~ignore_bits;
1358         guest_efer |= host_efer & ignore_bits;
1359         vmx->guest_msrs[efer_offset].data = guest_efer;
1360         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1361
1362         clear_atomic_switch_msr(vmx, MSR_EFER);
1363         /* On ept, can't emulate nx, and must switch nx atomically */
1364         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1365                 guest_efer = vmx->vcpu.arch.efer;
1366                 if (!(guest_efer & EFER_LMA))
1367                         guest_efer &= ~EFER_LME;
1368                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1369                 return false;
1370         }
1371
1372         return true;
1373 }
1374
1375 static unsigned long segment_base(u16 selector)
1376 {
1377         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1378         struct desc_struct *d;
1379         unsigned long table_base;
1380         unsigned long v;
1381
1382         if (!(selector & ~3))
1383                 return 0;
1384
1385         table_base = gdt->address;
1386
1387         if (selector & 4) {           /* from ldt */
1388                 u16 ldt_selector = kvm_read_ldt();
1389
1390                 if (!(ldt_selector & ~3))
1391                         return 0;
1392
1393                 table_base = segment_base(ldt_selector);
1394         }
1395         d = (struct desc_struct *)(table_base + (selector & ~7));
1396         v = get_desc_base(d);
1397 #ifdef CONFIG_X86_64
1398        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1399                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1400 #endif
1401         return v;
1402 }
1403
1404 static inline unsigned long kvm_read_tr_base(void)
1405 {
1406         u16 tr;
1407         asm("str %0" : "=g"(tr));
1408         return segment_base(tr);
1409 }
1410
1411 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1412 {
1413         struct vcpu_vmx *vmx = to_vmx(vcpu);
1414         int i;
1415
1416         if (vmx->host_state.loaded)
1417                 return;
1418
1419         vmx->host_state.loaded = 1;
1420         /*
1421          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1422          * allow segment selectors with cpl > 0 or ti == 1.
1423          */
1424         vmx->host_state.ldt_sel = kvm_read_ldt();
1425         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1426         savesegment(fs, vmx->host_state.fs_sel);
1427         if (!(vmx->host_state.fs_sel & 7)) {
1428                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1429                 vmx->host_state.fs_reload_needed = 0;
1430         } else {
1431                 vmcs_write16(HOST_FS_SELECTOR, 0);
1432                 vmx->host_state.fs_reload_needed = 1;
1433         }
1434         savesegment(gs, vmx->host_state.gs_sel);
1435         if (!(vmx->host_state.gs_sel & 7))
1436                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1437         else {
1438                 vmcs_write16(HOST_GS_SELECTOR, 0);
1439                 vmx->host_state.gs_ldt_reload_needed = 1;
1440         }
1441
1442 #ifdef CONFIG_X86_64
1443         savesegment(ds, vmx->host_state.ds_sel);
1444         savesegment(es, vmx->host_state.es_sel);
1445 #endif
1446
1447 #ifdef CONFIG_X86_64
1448         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1449         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1450 #else
1451         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1452         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1453 #endif
1454
1455 #ifdef CONFIG_X86_64
1456         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1457         if (is_long_mode(&vmx->vcpu))
1458                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1459 #endif
1460         for (i = 0; i < vmx->save_nmsrs; ++i)
1461                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1462                                    vmx->guest_msrs[i].data,
1463                                    vmx->guest_msrs[i].mask);
1464 }
1465
1466 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1467 {
1468         if (!vmx->host_state.loaded)
1469                 return;
1470
1471         ++vmx->vcpu.stat.host_state_reload;
1472         vmx->host_state.loaded = 0;
1473 #ifdef CONFIG_X86_64
1474         if (is_long_mode(&vmx->vcpu))
1475                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1476 #endif
1477         if (vmx->host_state.gs_ldt_reload_needed) {
1478                 kvm_load_ldt(vmx->host_state.ldt_sel);
1479 #ifdef CONFIG_X86_64
1480                 load_gs_index(vmx->host_state.gs_sel);
1481 #else
1482                 loadsegment(gs, vmx->host_state.gs_sel);
1483 #endif
1484         }
1485         if (vmx->host_state.fs_reload_needed)
1486                 loadsegment(fs, vmx->host_state.fs_sel);
1487 #ifdef CONFIG_X86_64
1488         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1489                 loadsegment(ds, vmx->host_state.ds_sel);
1490                 loadsegment(es, vmx->host_state.es_sel);
1491         }
1492 #endif
1493         reload_tss();
1494 #ifdef CONFIG_X86_64
1495         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1496 #endif
1497         if (user_has_fpu())
1498                 clts();
1499         load_gdt(&__get_cpu_var(host_gdt));
1500 }
1501
1502 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1503 {
1504         preempt_disable();
1505         __vmx_load_host_state(vmx);
1506         preempt_enable();
1507 }
1508
1509 /*
1510  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1511  * vcpu mutex is already taken.
1512  */
1513 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1514 {
1515         struct vcpu_vmx *vmx = to_vmx(vcpu);
1516         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1517
1518         if (!vmm_exclusive)
1519                 kvm_cpu_vmxon(phys_addr);
1520         else if (vmx->loaded_vmcs->cpu != cpu)
1521                 loaded_vmcs_clear(vmx->loaded_vmcs);
1522
1523         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1524                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1525                 vmcs_load(vmx->loaded_vmcs->vmcs);
1526         }
1527
1528         if (vmx->loaded_vmcs->cpu != cpu) {
1529                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1530                 unsigned long sysenter_esp;
1531
1532                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1533                 local_irq_disable();
1534                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1535                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1536                 local_irq_enable();
1537
1538                 /*
1539                  * Linux uses per-cpu TSS and GDT, so set these when switching
1540                  * processors.
1541                  */
1542                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1543                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1544
1545                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1546                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1547                 vmx->loaded_vmcs->cpu = cpu;
1548         }
1549 }
1550
1551 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1552 {
1553         __vmx_load_host_state(to_vmx(vcpu));
1554         if (!vmm_exclusive) {
1555                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1556                 vcpu->cpu = -1;
1557                 kvm_cpu_vmxoff();
1558         }
1559 }
1560
1561 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1562 {
1563         ulong cr0;
1564
1565         if (vcpu->fpu_active)
1566                 return;
1567         vcpu->fpu_active = 1;
1568         cr0 = vmcs_readl(GUEST_CR0);
1569         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1570         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1571         vmcs_writel(GUEST_CR0, cr0);
1572         update_exception_bitmap(vcpu);
1573         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1574         if (is_guest_mode(vcpu))
1575                 vcpu->arch.cr0_guest_owned_bits &=
1576                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1577         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1578 }
1579
1580 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1581
1582 /*
1583  * Return the cr0 value that a nested guest would read. This is a combination
1584  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1585  * its hypervisor (cr0_read_shadow).
1586  */
1587 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1588 {
1589         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1590                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1591 }
1592 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1593 {
1594         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1595                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1596 }
1597
1598 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1599 {
1600         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1601          * set this *before* calling this function.
1602          */
1603         vmx_decache_cr0_guest_bits(vcpu);
1604         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1605         update_exception_bitmap(vcpu);
1606         vcpu->arch.cr0_guest_owned_bits = 0;
1607         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1608         if (is_guest_mode(vcpu)) {
1609                 /*
1610                  * L1's specified read shadow might not contain the TS bit,
1611                  * so now that we turned on shadowing of this bit, we need to
1612                  * set this bit of the shadow. Like in nested_vmx_run we need
1613                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1614                  * up-to-date here because we just decached cr0.TS (and we'll
1615                  * only update vmcs12->guest_cr0 on nested exit).
1616                  */
1617                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1618                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1619                         (vcpu->arch.cr0 & X86_CR0_TS);
1620                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1621         } else
1622                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1623 }
1624
1625 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1626 {
1627         unsigned long rflags, save_rflags;
1628
1629         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1630                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1631                 rflags = vmcs_readl(GUEST_RFLAGS);
1632                 if (to_vmx(vcpu)->rmode.vm86_active) {
1633                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1634                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1635                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1636                 }
1637                 to_vmx(vcpu)->rflags = rflags;
1638         }
1639         return to_vmx(vcpu)->rflags;
1640 }
1641
1642 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1643 {
1644         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1645         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1646         to_vmx(vcpu)->rflags = rflags;
1647         if (to_vmx(vcpu)->rmode.vm86_active) {
1648                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1649                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1650         }
1651         vmcs_writel(GUEST_RFLAGS, rflags);
1652 }
1653
1654 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1655 {
1656         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1657         int ret = 0;
1658
1659         if (interruptibility & GUEST_INTR_STATE_STI)
1660                 ret |= KVM_X86_SHADOW_INT_STI;
1661         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1662                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1663
1664         return ret & mask;
1665 }
1666
1667 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1668 {
1669         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1670         u32 interruptibility = interruptibility_old;
1671
1672         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1673
1674         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1675                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1676         else if (mask & KVM_X86_SHADOW_INT_STI)
1677                 interruptibility |= GUEST_INTR_STATE_STI;
1678
1679         if ((interruptibility != interruptibility_old))
1680                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1681 }
1682
1683 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1684 {
1685         unsigned long rip;
1686
1687         rip = kvm_rip_read(vcpu);
1688         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1689         kvm_rip_write(vcpu, rip);
1690
1691         /* skipping an emulated instruction also counts */
1692         vmx_set_interrupt_shadow(vcpu, 0);
1693 }
1694
1695 /*
1696  * KVM wants to inject page-faults which it got to the guest. This function
1697  * checks whether in a nested guest, we need to inject them to L1 or L2.
1698  * This function assumes it is called with the exit reason in vmcs02 being
1699  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1700  * is running).
1701  */
1702 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1703 {
1704         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1705
1706         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1707         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1708                 return 0;
1709
1710         nested_vmx_vmexit(vcpu);
1711         return 1;
1712 }
1713
1714 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1715                                 bool has_error_code, u32 error_code,
1716                                 bool reinject)
1717 {
1718         struct vcpu_vmx *vmx = to_vmx(vcpu);
1719         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1720
1721         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1722                 nested_pf_handled(vcpu))
1723                 return;
1724
1725         if (has_error_code) {
1726                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1727                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1728         }
1729
1730         if (vmx->rmode.vm86_active) {
1731                 int inc_eip = 0;
1732                 if (kvm_exception_is_soft(nr))
1733                         inc_eip = vcpu->arch.event_exit_inst_len;
1734                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1735                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1736                 return;
1737         }
1738
1739         if (kvm_exception_is_soft(nr)) {
1740                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1741                              vmx->vcpu.arch.event_exit_inst_len);
1742                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1743         } else
1744                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1745
1746         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1747 }
1748
1749 static bool vmx_rdtscp_supported(void)
1750 {
1751         return cpu_has_vmx_rdtscp();
1752 }
1753
1754 static bool vmx_invpcid_supported(void)
1755 {
1756         return cpu_has_vmx_invpcid() && enable_ept;
1757 }
1758
1759 /*
1760  * Swap MSR entry in host/guest MSR entry array.
1761  */
1762 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1763 {
1764         struct shared_msr_entry tmp;
1765
1766         tmp = vmx->guest_msrs[to];
1767         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1768         vmx->guest_msrs[from] = tmp;
1769 }
1770
1771 /*
1772  * Set up the vmcs to automatically save and restore system
1773  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1774  * mode, as fiddling with msrs is very expensive.
1775  */
1776 static void setup_msrs(struct vcpu_vmx *vmx)
1777 {
1778         int save_nmsrs, index;
1779         unsigned long *msr_bitmap;
1780
1781         save_nmsrs = 0;
1782 #ifdef CONFIG_X86_64
1783         if (is_long_mode(&vmx->vcpu)) {
1784                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1785                 if (index >= 0)
1786                         move_msr_up(vmx, index, save_nmsrs++);
1787                 index = __find_msr_index(vmx, MSR_LSTAR);
1788                 if (index >= 0)
1789                         move_msr_up(vmx, index, save_nmsrs++);
1790                 index = __find_msr_index(vmx, MSR_CSTAR);
1791                 if (index >= 0)
1792                         move_msr_up(vmx, index, save_nmsrs++);
1793                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1794                 if (index >= 0 && vmx->rdtscp_enabled)
1795                         move_msr_up(vmx, index, save_nmsrs++);
1796                 /*
1797                  * MSR_STAR is only needed on long mode guests, and only
1798                  * if efer.sce is enabled.
1799                  */
1800                 index = __find_msr_index(vmx, MSR_STAR);
1801                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1802                         move_msr_up(vmx, index, save_nmsrs++);
1803         }
1804 #endif
1805         index = __find_msr_index(vmx, MSR_EFER);
1806         if (index >= 0 && update_transition_efer(vmx, index))
1807                 move_msr_up(vmx, index, save_nmsrs++);
1808
1809         vmx->save_nmsrs = save_nmsrs;
1810
1811         if (cpu_has_vmx_msr_bitmap()) {
1812                 if (is_long_mode(&vmx->vcpu))
1813                         msr_bitmap = vmx_msr_bitmap_longmode;
1814                 else
1815                         msr_bitmap = vmx_msr_bitmap_legacy;
1816
1817                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1818         }
1819 }
1820
1821 /*
1822  * reads and returns guest's timestamp counter "register"
1823  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1824  */
1825 static u64 guest_read_tsc(void)
1826 {
1827         u64 host_tsc, tsc_offset;
1828
1829         rdtscll(host_tsc);
1830         tsc_offset = vmcs_read64(TSC_OFFSET);
1831         return host_tsc + tsc_offset;
1832 }
1833
1834 /*
1835  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1836  * counter, even if a nested guest (L2) is currently running.
1837  */
1838 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1839 {
1840         u64 host_tsc, tsc_offset;
1841
1842         rdtscll(host_tsc);
1843         tsc_offset = is_guest_mode(vcpu) ?
1844                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1845                 vmcs_read64(TSC_OFFSET);
1846         return host_tsc + tsc_offset;
1847 }
1848
1849 /*
1850  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1851  * software catchup for faster rates on slower CPUs.
1852  */
1853 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1854 {
1855         if (!scale)
1856                 return;
1857
1858         if (user_tsc_khz > tsc_khz) {
1859                 vcpu->arch.tsc_catchup = 1;
1860                 vcpu->arch.tsc_always_catchup = 1;
1861         } else
1862                 WARN(1, "user requested TSC rate below hardware speed\n");
1863 }
1864
1865 /*
1866  * writes 'offset' into guest's timestamp counter offset register
1867  */
1868 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1869 {
1870         if (is_guest_mode(vcpu)) {
1871                 /*
1872                  * We're here if L1 chose not to trap WRMSR to TSC. According
1873                  * to the spec, this should set L1's TSC; The offset that L1
1874                  * set for L2 remains unchanged, and still needs to be added
1875                  * to the newly set TSC to get L2's TSC.
1876                  */
1877                 struct vmcs12 *vmcs12;
1878                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1879                 /* recalculate vmcs02.TSC_OFFSET: */
1880                 vmcs12 = get_vmcs12(vcpu);
1881                 vmcs_write64(TSC_OFFSET, offset +
1882                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1883                          vmcs12->tsc_offset : 0));
1884         } else {
1885                 vmcs_write64(TSC_OFFSET, offset);
1886         }
1887 }
1888
1889 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1890 {
1891         u64 offset = vmcs_read64(TSC_OFFSET);
1892         vmcs_write64(TSC_OFFSET, offset + adjustment);
1893         if (is_guest_mode(vcpu)) {
1894                 /* Even when running L2, the adjustment needs to apply to L1 */
1895                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1896         }
1897 }
1898
1899 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1900 {
1901         return target_tsc - native_read_tsc();
1902 }
1903
1904 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1905 {
1906         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1907         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1908 }
1909
1910 /*
1911  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1912  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1913  * all guests if the "nested" module option is off, and can also be disabled
1914  * for a single guest by disabling its VMX cpuid bit.
1915  */
1916 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1917 {
1918         return nested && guest_cpuid_has_vmx(vcpu);
1919 }
1920
1921 /*
1922  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1923  * returned for the various VMX controls MSRs when nested VMX is enabled.
1924  * The same values should also be used to verify that vmcs12 control fields are
1925  * valid during nested entry from L1 to L2.
1926  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1927  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1928  * bit in the high half is on if the corresponding bit in the control field
1929  * may be on. See also vmx_control_verify().
1930  * TODO: allow these variables to be modified (downgraded) by module options
1931  * or other means.
1932  */
1933 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1934 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1935 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1936 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1937 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1938 static __init void nested_vmx_setup_ctls_msrs(void)
1939 {
1940         /*
1941          * Note that as a general rule, the high half of the MSRs (bits in
1942          * the control fields which may be 1) should be initialized by the
1943          * intersection of the underlying hardware's MSR (i.e., features which
1944          * can be supported) and the list of features we want to expose -
1945          * because they are known to be properly supported in our code.
1946          * Also, usually, the low half of the MSRs (bits which must be 1) can
1947          * be set to 0, meaning that L1 may turn off any of these bits. The
1948          * reason is that if one of these bits is necessary, it will appear
1949          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1950          * fields of vmcs01 and vmcs02, will turn these bits off - and
1951          * nested_vmx_exit_handled() will not pass related exits to L1.
1952          * These rules have exceptions below.
1953          */
1954
1955         /* pin-based controls */
1956         /*
1957          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1958          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1959          */
1960         nested_vmx_pinbased_ctls_low = 0x16 ;
1961         nested_vmx_pinbased_ctls_high = 0x16 |
1962                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1963                 PIN_BASED_VIRTUAL_NMIS;
1964
1965         /* exit controls */
1966         nested_vmx_exit_ctls_low = 0;
1967         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1968 #ifdef CONFIG_X86_64
1969         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1970 #else
1971         nested_vmx_exit_ctls_high = 0;
1972 #endif
1973
1974         /* entry controls */
1975         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1976                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1977         nested_vmx_entry_ctls_low = 0;
1978         nested_vmx_entry_ctls_high &=
1979                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1980
1981         /* cpu-based controls */
1982         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1983                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1984         nested_vmx_procbased_ctls_low = 0;
1985         nested_vmx_procbased_ctls_high &=
1986                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1987                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1988                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1989                 CPU_BASED_CR3_STORE_EXITING |
1990 #ifdef CONFIG_X86_64
1991                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1992 #endif
1993                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1994                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1995                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
1996                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1997         /*
1998          * We can allow some features even when not supported by the
1999          * hardware. For example, L1 can specify an MSR bitmap - and we
2000          * can use it to avoid exits to L1 - even when L0 runs L2
2001          * without MSR bitmaps.
2002          */
2003         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2004
2005         /* secondary cpu-based controls */
2006         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2007                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2008         nested_vmx_secondary_ctls_low = 0;
2009         nested_vmx_secondary_ctls_high &=
2010                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2011 }
2012
2013 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2014 {
2015         /*
2016          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2017          */
2018         return ((control & high) | low) == control;
2019 }
2020
2021 static inline u64 vmx_control_msr(u32 low, u32 high)
2022 {
2023         return low | ((u64)high << 32);
2024 }
2025
2026 /*
2027  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2028  * also let it use VMX-specific MSRs.
2029  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2030  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2031  * like all other MSRs).
2032  */
2033 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2034 {
2035         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2036                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2037                 /*
2038                  * According to the spec, processors which do not support VMX
2039                  * should throw a #GP(0) when VMX capability MSRs are read.
2040                  */
2041                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2042                 return 1;
2043         }
2044
2045         switch (msr_index) {
2046         case MSR_IA32_FEATURE_CONTROL:
2047                 *pdata = 0;
2048                 break;
2049         case MSR_IA32_VMX_BASIC:
2050                 /*
2051                  * This MSR reports some information about VMX support. We
2052                  * should return information about the VMX we emulate for the
2053                  * guest, and the VMCS structure we give it - not about the
2054                  * VMX support of the underlying hardware.
2055                  */
2056                 *pdata = VMCS12_REVISION |
2057                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2058                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2059                 break;
2060         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2061         case MSR_IA32_VMX_PINBASED_CTLS:
2062                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2063                                         nested_vmx_pinbased_ctls_high);
2064                 break;
2065         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2066         case MSR_IA32_VMX_PROCBASED_CTLS:
2067                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2068                                         nested_vmx_procbased_ctls_high);
2069                 break;
2070         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2071         case MSR_IA32_VMX_EXIT_CTLS:
2072                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2073                                         nested_vmx_exit_ctls_high);
2074                 break;
2075         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2076         case MSR_IA32_VMX_ENTRY_CTLS:
2077                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2078                                         nested_vmx_entry_ctls_high);
2079                 break;
2080         case MSR_IA32_VMX_MISC:
2081                 *pdata = 0;
2082                 break;
2083         /*
2084          * These MSRs specify bits which the guest must keep fixed (on or off)
2085          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2086          * We picked the standard core2 setting.
2087          */
2088 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2089 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2090         case MSR_IA32_VMX_CR0_FIXED0:
2091                 *pdata = VMXON_CR0_ALWAYSON;
2092                 break;
2093         case MSR_IA32_VMX_CR0_FIXED1:
2094                 *pdata = -1ULL;
2095                 break;
2096         case MSR_IA32_VMX_CR4_FIXED0:
2097                 *pdata = VMXON_CR4_ALWAYSON;
2098                 break;
2099         case MSR_IA32_VMX_CR4_FIXED1:
2100                 *pdata = -1ULL;
2101                 break;
2102         case MSR_IA32_VMX_VMCS_ENUM:
2103                 *pdata = 0x1f;
2104                 break;
2105         case MSR_IA32_VMX_PROCBASED_CTLS2:
2106                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2107                                         nested_vmx_secondary_ctls_high);
2108                 break;
2109         case MSR_IA32_VMX_EPT_VPID_CAP:
2110                 /* Currently, no nested ept or nested vpid */
2111                 *pdata = 0;
2112                 break;
2113         default:
2114                 return 0;
2115         }
2116
2117         return 1;
2118 }
2119
2120 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2121 {
2122         if (!nested_vmx_allowed(vcpu))
2123                 return 0;
2124
2125         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2126                 /* TODO: the right thing. */
2127                 return 1;
2128         /*
2129          * No need to treat VMX capability MSRs specially: If we don't handle
2130          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2131          */
2132         return 0;
2133 }
2134
2135 /*
2136  * Reads an msr value (of 'msr_index') into 'pdata'.
2137  * Returns 0 on success, non-0 otherwise.
2138  * Assumes vcpu_load() was already called.
2139  */
2140 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2141 {
2142         u64 data;
2143         struct shared_msr_entry *msr;
2144
2145         if (!pdata) {
2146                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2147                 return -EINVAL;
2148         }
2149
2150         switch (msr_index) {
2151 #ifdef CONFIG_X86_64
2152         case MSR_FS_BASE:
2153                 data = vmcs_readl(GUEST_FS_BASE);
2154                 break;
2155         case MSR_GS_BASE:
2156                 data = vmcs_readl(GUEST_GS_BASE);
2157                 break;
2158         case MSR_KERNEL_GS_BASE:
2159                 vmx_load_host_state(to_vmx(vcpu));
2160                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2161                 break;
2162 #endif
2163         case MSR_EFER:
2164                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2165         case MSR_IA32_TSC:
2166                 data = guest_read_tsc();
2167                 break;
2168         case MSR_IA32_SYSENTER_CS:
2169                 data = vmcs_read32(GUEST_SYSENTER_CS);
2170                 break;
2171         case MSR_IA32_SYSENTER_EIP:
2172                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2173                 break;
2174         case MSR_IA32_SYSENTER_ESP:
2175                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2176                 break;
2177         case MSR_TSC_AUX:
2178                 if (!to_vmx(vcpu)->rdtscp_enabled)
2179                         return 1;
2180                 /* Otherwise falls through */
2181         default:
2182                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2183                         return 0;
2184                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2185                 if (msr) {
2186                         data = msr->data;
2187                         break;
2188                 }
2189                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2190         }
2191
2192         *pdata = data;
2193         return 0;
2194 }
2195
2196 /*
2197  * Writes msr value into into the appropriate "register".
2198  * Returns 0 on success, non-0 otherwise.
2199  * Assumes vcpu_load() was already called.
2200  */
2201 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2202 {
2203         struct vcpu_vmx *vmx = to_vmx(vcpu);
2204         struct shared_msr_entry *msr;
2205         int ret = 0;
2206
2207         switch (msr_index) {
2208         case MSR_EFER:
2209                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2210                 break;
2211 #ifdef CONFIG_X86_64
2212         case MSR_FS_BASE:
2213                 vmx_segment_cache_clear(vmx);
2214                 vmcs_writel(GUEST_FS_BASE, data);
2215                 break;
2216         case MSR_GS_BASE:
2217                 vmx_segment_cache_clear(vmx);
2218                 vmcs_writel(GUEST_GS_BASE, data);
2219                 break;
2220         case MSR_KERNEL_GS_BASE:
2221                 vmx_load_host_state(vmx);
2222                 vmx->msr_guest_kernel_gs_base = data;
2223                 break;
2224 #endif
2225         case MSR_IA32_SYSENTER_CS:
2226                 vmcs_write32(GUEST_SYSENTER_CS, data);
2227                 break;
2228         case MSR_IA32_SYSENTER_EIP:
2229                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2230                 break;
2231         case MSR_IA32_SYSENTER_ESP:
2232                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2233                 break;
2234         case MSR_IA32_TSC:
2235                 kvm_write_tsc(vcpu, data);
2236                 break;
2237         case MSR_IA32_CR_PAT:
2238                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2239                         vmcs_write64(GUEST_IA32_PAT, data);
2240                         vcpu->arch.pat = data;
2241                         break;
2242                 }
2243                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2244                 break;
2245         case MSR_TSC_AUX:
2246                 if (!vmx->rdtscp_enabled)
2247                         return 1;
2248                 /* Check reserved bit, higher 32 bits should be zero */
2249                 if ((data >> 32) != 0)
2250                         return 1;
2251                 /* Otherwise falls through */
2252         default:
2253                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2254                         break;
2255                 msr = find_msr_entry(vmx, msr_index);
2256                 if (msr) {
2257                         msr->data = data;
2258                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2259                                 preempt_disable();
2260                                 kvm_set_shared_msr(msr->index, msr->data,
2261                                                    msr->mask);
2262                                 preempt_enable();
2263                         }
2264                         break;
2265                 }
2266                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2267         }
2268
2269         return ret;
2270 }
2271
2272 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2273 {
2274         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2275         switch (reg) {
2276         case VCPU_REGS_RSP:
2277                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2278                 break;
2279         case VCPU_REGS_RIP:
2280                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2281                 break;
2282         case VCPU_EXREG_PDPTR:
2283                 if (enable_ept)
2284                         ept_save_pdptrs(vcpu);
2285                 break;
2286         default:
2287                 break;
2288         }
2289 }
2290
2291 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2292 {
2293         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2294                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2295         else
2296                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2297
2298         update_exception_bitmap(vcpu);
2299 }
2300
2301 static __init int cpu_has_kvm_support(void)
2302 {
2303         return cpu_has_vmx();
2304 }
2305
2306 static __init int vmx_disabled_by_bios(void)
2307 {
2308         u64 msr;
2309
2310         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2311         if (msr & FEATURE_CONTROL_LOCKED) {
2312                 /* launched w/ TXT and VMX disabled */
2313                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2314                         && tboot_enabled())
2315                         return 1;
2316                 /* launched w/o TXT and VMX only enabled w/ TXT */
2317                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2318                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2319                         && !tboot_enabled()) {
2320                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2321                                 "activate TXT before enabling KVM\n");
2322                         return 1;
2323                 }
2324                 /* launched w/o TXT and VMX disabled */
2325                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2326                         && !tboot_enabled())
2327                         return 1;
2328         }
2329
2330         return 0;
2331 }
2332
2333 static void kvm_cpu_vmxon(u64 addr)
2334 {
2335         asm volatile (ASM_VMX_VMXON_RAX
2336                         : : "a"(&addr), "m"(addr)
2337                         : "memory", "cc");
2338 }
2339
2340 static int hardware_enable(void *garbage)
2341 {
2342         int cpu = raw_smp_processor_id();
2343         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2344         u64 old, test_bits;
2345
2346         if (read_cr4() & X86_CR4_VMXE)
2347                 return -EBUSY;
2348
2349         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2350         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2351
2352         test_bits = FEATURE_CONTROL_LOCKED;
2353         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2354         if (tboot_enabled())
2355                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2356
2357         if ((old & test_bits) != test_bits) {
2358                 /* enable and lock */
2359                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2360         }
2361         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2362
2363         if (vmm_exclusive) {
2364                 kvm_cpu_vmxon(phys_addr);
2365                 ept_sync_global();
2366         }
2367
2368         store_gdt(&__get_cpu_var(host_gdt));
2369
2370         return 0;
2371 }
2372
2373 static void vmclear_local_loaded_vmcss(void)
2374 {
2375         int cpu = raw_smp_processor_id();
2376         struct loaded_vmcs *v, *n;
2377
2378         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2379                                  loaded_vmcss_on_cpu_link)
2380                 __loaded_vmcs_clear(v);
2381 }
2382
2383
2384 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2385  * tricks.
2386  */
2387 static void kvm_cpu_vmxoff(void)
2388 {
2389         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2390 }
2391
2392 static void hardware_disable(void *garbage)
2393 {
2394         if (vmm_exclusive) {
2395                 vmclear_local_loaded_vmcss();
2396                 kvm_cpu_vmxoff();
2397         }
2398         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2399 }
2400
2401 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2402                                       u32 msr, u32 *result)
2403 {
2404         u32 vmx_msr_low, vmx_msr_high;
2405         u32 ctl = ctl_min | ctl_opt;
2406
2407         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2408
2409         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2410         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2411
2412         /* Ensure minimum (required) set of control bits are supported. */
2413         if (ctl_min & ~ctl)
2414                 return -EIO;
2415
2416         *result = ctl;
2417         return 0;
2418 }
2419
2420 static __init bool allow_1_setting(u32 msr, u32 ctl)
2421 {
2422         u32 vmx_msr_low, vmx_msr_high;
2423
2424         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2425         return vmx_msr_high & ctl;
2426 }
2427
2428 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2429 {
2430         u32 vmx_msr_low, vmx_msr_high;
2431         u32 min, opt, min2, opt2;
2432         u32 _pin_based_exec_control = 0;
2433         u32 _cpu_based_exec_control = 0;
2434         u32 _cpu_based_2nd_exec_control = 0;
2435         u32 _vmexit_control = 0;
2436         u32 _vmentry_control = 0;
2437
2438         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2439         opt = PIN_BASED_VIRTUAL_NMIS;
2440         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2441                                 &_pin_based_exec_control) < 0)
2442                 return -EIO;
2443
2444         min = CPU_BASED_HLT_EXITING |
2445 #ifdef CONFIG_X86_64
2446               CPU_BASED_CR8_LOAD_EXITING |
2447               CPU_BASED_CR8_STORE_EXITING |
2448 #endif
2449               CPU_BASED_CR3_LOAD_EXITING |
2450               CPU_BASED_CR3_STORE_EXITING |
2451               CPU_BASED_USE_IO_BITMAPS |
2452               CPU_BASED_MOV_DR_EXITING |
2453               CPU_BASED_USE_TSC_OFFSETING |
2454               CPU_BASED_MWAIT_EXITING |
2455               CPU_BASED_MONITOR_EXITING |
2456               CPU_BASED_INVLPG_EXITING |
2457               CPU_BASED_RDPMC_EXITING;
2458
2459         opt = CPU_BASED_TPR_SHADOW |
2460               CPU_BASED_USE_MSR_BITMAPS |
2461               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2462         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2463                                 &_cpu_based_exec_control) < 0)
2464                 return -EIO;
2465 #ifdef CONFIG_X86_64
2466         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2467                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2468                                            ~CPU_BASED_CR8_STORE_EXITING;
2469 #endif
2470         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2471                 min2 = 0;
2472                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2473                         SECONDARY_EXEC_WBINVD_EXITING |
2474                         SECONDARY_EXEC_ENABLE_VPID |
2475                         SECONDARY_EXEC_ENABLE_EPT |
2476                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2477                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2478                         SECONDARY_EXEC_RDTSCP |
2479                         SECONDARY_EXEC_ENABLE_INVPCID;
2480                 if (adjust_vmx_controls(min2, opt2,
2481                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2482                                         &_cpu_based_2nd_exec_control) < 0)
2483                         return -EIO;
2484         }
2485 #ifndef CONFIG_X86_64
2486         if (!(_cpu_based_2nd_exec_control &
2487                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2488                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2489 #endif
2490         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2491                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2492                    enabled */
2493                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2494                                              CPU_BASED_CR3_STORE_EXITING |
2495                                              CPU_BASED_INVLPG_EXITING);
2496                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2497                       vmx_capability.ept, vmx_capability.vpid);
2498         }
2499
2500         min = 0;
2501 #ifdef CONFIG_X86_64
2502         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2503 #endif
2504         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2505         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2506                                 &_vmexit_control) < 0)
2507                 return -EIO;
2508
2509         min = 0;
2510         opt = VM_ENTRY_LOAD_IA32_PAT;
2511         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2512                                 &_vmentry_control) < 0)
2513                 return -EIO;
2514
2515         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2516
2517         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2518         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2519                 return -EIO;
2520
2521 #ifdef CONFIG_X86_64
2522         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2523         if (vmx_msr_high & (1u<<16))
2524                 return -EIO;
2525 #endif
2526
2527         /* Require Write-Back (WB) memory type for VMCS accesses. */
2528         if (((vmx_msr_high >> 18) & 15) != 6)
2529                 return -EIO;
2530
2531         vmcs_conf->size = vmx_msr_high & 0x1fff;
2532         vmcs_conf->order = get_order(vmcs_config.size);
2533         vmcs_conf->revision_id = vmx_msr_low;
2534
2535         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2536         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2537         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2538         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2539         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2540
2541         cpu_has_load_ia32_efer =
2542                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2543                                 VM_ENTRY_LOAD_IA32_EFER)
2544                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2545                                    VM_EXIT_LOAD_IA32_EFER);
2546
2547         cpu_has_load_perf_global_ctrl =
2548                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2549                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2550                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2551                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2552
2553         /*
2554          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2555          * but due to arrata below it can't be used. Workaround is to use
2556          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2557          *
2558          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2559          *
2560          * AAK155             (model 26)
2561          * AAP115             (model 30)
2562          * AAT100             (model 37)
2563          * BC86,AAY89,BD102   (model 44)
2564          * BA97               (model 46)
2565          *
2566          */
2567         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2568                 switch (boot_cpu_data.x86_model) {
2569                 case 26:
2570                 case 30:
2571                 case 37:
2572                 case 44:
2573                 case 46:
2574                         cpu_has_load_perf_global_ctrl = false;
2575                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2576                                         "does not work properly. Using workaround\n");
2577                         break;
2578                 default:
2579                         break;
2580                 }
2581         }
2582
2583         return 0;
2584 }
2585
2586 static struct vmcs *alloc_vmcs_cpu(int cpu)
2587 {
2588         int node = cpu_to_node(cpu);
2589         struct page *pages;
2590         struct vmcs *vmcs;
2591
2592         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2593         if (!pages)
2594                 return NULL;
2595         vmcs = page_address(pages);
2596         memset(vmcs, 0, vmcs_config.size);
2597         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2598         return vmcs;
2599 }
2600
2601 static struct vmcs *alloc_vmcs(void)
2602 {
2603         return alloc_vmcs_cpu(raw_smp_processor_id());
2604 }
2605
2606 static void free_vmcs(struct vmcs *vmcs)
2607 {
2608         free_pages((unsigned long)vmcs, vmcs_config.order);
2609 }
2610
2611 /*
2612  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2613  */
2614 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2615 {
2616         if (!loaded_vmcs->vmcs)
2617                 return;
2618         loaded_vmcs_clear(loaded_vmcs);
2619         free_vmcs(loaded_vmcs->vmcs);
2620         loaded_vmcs->vmcs = NULL;
2621 }
2622
2623 static void free_kvm_area(void)
2624 {
2625         int cpu;
2626
2627         for_each_possible_cpu(cpu) {
2628                 free_vmcs(per_cpu(vmxarea, cpu));
2629                 per_cpu(vmxarea, cpu) = NULL;
2630         }
2631 }
2632
2633 static __init int alloc_kvm_area(void)
2634 {
2635         int cpu;
2636
2637         for_each_possible_cpu(cpu) {
2638                 struct vmcs *vmcs;
2639
2640                 vmcs = alloc_vmcs_cpu(cpu);
2641                 if (!vmcs) {
2642                         free_kvm_area();
2643                         return -ENOMEM;
2644                 }
2645
2646                 per_cpu(vmxarea, cpu) = vmcs;
2647         }
2648         return 0;
2649 }
2650
2651 static __init int hardware_setup(void)
2652 {
2653         if (setup_vmcs_config(&vmcs_config) < 0)
2654                 return -EIO;
2655
2656         if (boot_cpu_has(X86_FEATURE_NX))
2657                 kvm_enable_efer_bits(EFER_NX);
2658
2659         if (!cpu_has_vmx_vpid())
2660                 enable_vpid = 0;
2661
2662         if (!cpu_has_vmx_ept() ||
2663             !cpu_has_vmx_ept_4levels()) {
2664                 enable_ept = 0;
2665                 enable_unrestricted_guest = 0;
2666                 enable_ept_ad_bits = 0;
2667         }
2668
2669         if (!cpu_has_vmx_ept_ad_bits())
2670                 enable_ept_ad_bits = 0;
2671
2672         if (!cpu_has_vmx_unrestricted_guest())
2673                 enable_unrestricted_guest = 0;
2674
2675         if (!cpu_has_vmx_flexpriority())
2676                 flexpriority_enabled = 0;
2677
2678         if (!cpu_has_vmx_tpr_shadow())
2679                 kvm_x86_ops->update_cr8_intercept = NULL;
2680
2681         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2682                 kvm_disable_largepages();
2683
2684         if (!cpu_has_vmx_ple())
2685                 ple_gap = 0;
2686
2687         if (nested)
2688                 nested_vmx_setup_ctls_msrs();
2689
2690         return alloc_kvm_area();
2691 }
2692
2693 static __exit void hardware_unsetup(void)
2694 {
2695         free_kvm_area();
2696 }
2697
2698 static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg, struct kvm_segment *save)
2699 {
2700         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2701         struct kvm_segment tmp = *save;
2702
2703         if (!(vmcs_readl(sf->base) == tmp.base && tmp.s)) {
2704                 tmp.base = vmcs_readl(sf->base);
2705                 tmp.selector = vmcs_read16(sf->selector);
2706                 tmp.s = 1;
2707         }
2708         vmx_set_segment(vcpu, &tmp, seg);
2709 }
2710
2711 static void enter_pmode(struct kvm_vcpu *vcpu)
2712 {
2713         unsigned long flags;
2714         struct vcpu_vmx *vmx = to_vmx(vcpu);
2715
2716         vmx->emulation_required = 1;
2717         vmx->rmode.vm86_active = 0;
2718
2719         vmx_segment_cache_clear(vmx);
2720
2721         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2722
2723         flags = vmcs_readl(GUEST_RFLAGS);
2724         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2725         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2726         vmcs_writel(GUEST_RFLAGS, flags);
2727
2728         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2729                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2730
2731         update_exception_bitmap(vcpu);
2732
2733         if (emulate_invalid_guest_state)
2734                 return;
2735
2736         fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2737         fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2738         fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2739         fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2740
2741         vmx_segment_cache_clear(vmx);
2742
2743         vmcs_write16(GUEST_SS_SELECTOR, 0);
2744         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2745
2746         vmcs_write16(GUEST_CS_SELECTOR,
2747                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2748         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2749 }
2750
2751 static gva_t rmode_tss_base(struct kvm *kvm)
2752 {
2753         if (!kvm->arch.tss_addr) {
2754                 struct kvm_memslots *slots;
2755                 struct kvm_memory_slot *slot;
2756                 gfn_t base_gfn;
2757
2758                 slots = kvm_memslots(kvm);
2759                 slot = id_to_memslot(slots, 0);
2760                 base_gfn = slot->base_gfn + slot->npages - 3;
2761
2762                 return base_gfn << PAGE_SHIFT;
2763         }
2764         return kvm->arch.tss_addr;
2765 }
2766
2767 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2768 {
2769         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2770
2771         vmcs_write16(sf->selector, save->base >> 4);
2772         vmcs_write32(sf->base, save->base & 0xffff0);
2773         vmcs_write32(sf->limit, 0xffff);
2774         vmcs_write32(sf->ar_bytes, 0xf3);
2775         if (save->base & 0xf)
2776                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2777                             " aligned when entering protected mode (seg=%d)",
2778                             seg);
2779 }
2780
2781 static void enter_rmode(struct kvm_vcpu *vcpu)
2782 {
2783         unsigned long flags;
2784         struct vcpu_vmx *vmx = to_vmx(vcpu);
2785         struct kvm_segment var;
2786
2787         if (enable_unrestricted_guest)
2788                 return;
2789
2790         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2791         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2792         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2793         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2794         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2795
2796         vmx->emulation_required = 1;
2797         vmx->rmode.vm86_active = 1;
2798
2799
2800         /*
2801          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2802          * vcpu. Call it here with phys address pointing 16M below 4G.
2803          */
2804         if (!vcpu->kvm->arch.tss_addr) {
2805                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2806                              "called before entering vcpu\n");
2807                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2808                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2809                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2810         }
2811
2812         vmx_segment_cache_clear(vmx);
2813
2814         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2815         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2816         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2817
2818         flags = vmcs_readl(GUEST_RFLAGS);
2819         vmx->rmode.save_rflags = flags;
2820
2821         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2822
2823         vmcs_writel(GUEST_RFLAGS, flags);
2824         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2825         update_exception_bitmap(vcpu);
2826
2827         if (emulate_invalid_guest_state)
2828                 goto continue_rmode;
2829
2830         vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2831         vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2832
2833         vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2834         vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2835
2836         vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2837         vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2838
2839         vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2840         vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
2841
2842         vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2843         vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
2844
2845         vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2846         vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
2847
2848 continue_rmode:
2849         kvm_mmu_reset_context(vcpu);
2850 }
2851
2852 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2853 {
2854         struct vcpu_vmx *vmx = to_vmx(vcpu);
2855         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2856
2857         if (!msr)
2858                 return;
2859
2860         /*
2861          * Force kernel_gs_base reloading before EFER changes, as control
2862          * of this msr depends on is_long_mode().
2863          */
2864         vmx_load_host_state(to_vmx(vcpu));
2865         vcpu->arch.efer = efer;
2866         if (efer & EFER_LMA) {
2867                 vmcs_write32(VM_ENTRY_CONTROLS,
2868                              vmcs_read32(VM_ENTRY_CONTROLS) |
2869                              VM_ENTRY_IA32E_MODE);
2870                 msr->data = efer;
2871         } else {
2872                 vmcs_write32(VM_ENTRY_CONTROLS,
2873                              vmcs_read32(VM_ENTRY_CONTROLS) &
2874                              ~VM_ENTRY_IA32E_MODE);
2875
2876                 msr->data = efer & ~EFER_LME;
2877         }
2878         setup_msrs(vmx);
2879 }
2880
2881 #ifdef CONFIG_X86_64
2882
2883 static void enter_lmode(struct kvm_vcpu *vcpu)
2884 {
2885         u32 guest_tr_ar;
2886
2887         vmx_segment_cache_clear(to_vmx(vcpu));
2888
2889         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2890         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2891                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2892                                      __func__);
2893                 vmcs_write32(GUEST_TR_AR_BYTES,
2894                              (guest_tr_ar & ~AR_TYPE_MASK)
2895                              | AR_TYPE_BUSY_64_TSS);
2896         }
2897         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2898 }
2899
2900 static void exit_lmode(struct kvm_vcpu *vcpu)
2901 {
2902         vmcs_write32(VM_ENTRY_CONTROLS,
2903                      vmcs_read32(VM_ENTRY_CONTROLS)
2904                      & ~VM_ENTRY_IA32E_MODE);
2905         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2906 }
2907
2908 #endif
2909
2910 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2911 {
2912         vpid_sync_context(to_vmx(vcpu));
2913         if (enable_ept) {
2914                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2915                         return;
2916                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2917         }
2918 }
2919
2920 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2921 {
2922         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2923
2924         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2925         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2926 }
2927
2928 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2929 {
2930         if (enable_ept && is_paging(vcpu))
2931                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2932         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2933 }
2934
2935 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2936 {
2937         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2938
2939         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2940         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2941 }
2942
2943 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2944 {
2945         if (!test_bit(VCPU_EXREG_PDPTR,
2946                       (unsigned long *)&vcpu->arch.regs_dirty))
2947                 return;
2948
2949         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2950                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2951                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2952                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2953                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2954         }
2955 }
2956
2957 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2958 {
2959         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2960                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2961                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2962                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2963                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2964         }
2965
2966         __set_bit(VCPU_EXREG_PDPTR,
2967                   (unsigned long *)&vcpu->arch.regs_avail);
2968         __set_bit(VCPU_EXREG_PDPTR,
2969                   (unsigned long *)&vcpu->arch.regs_dirty);
2970 }
2971
2972 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2973
2974 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2975                                         unsigned long cr0,
2976                                         struct kvm_vcpu *vcpu)
2977 {
2978         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2979                 vmx_decache_cr3(vcpu);
2980         if (!(cr0 & X86_CR0_PG)) {
2981                 /* From paging/starting to nonpaging */
2982                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2983                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2984                              (CPU_BASED_CR3_LOAD_EXITING |
2985                               CPU_BASED_CR3_STORE_EXITING));
2986                 vcpu->arch.cr0 = cr0;
2987                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2988         } else if (!is_paging(vcpu)) {
2989                 /* From nonpaging to paging */
2990                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2991                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2992                              ~(CPU_BASED_CR3_LOAD_EXITING |
2993                                CPU_BASED_CR3_STORE_EXITING));
2994                 vcpu->arch.cr0 = cr0;
2995                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2996         }
2997
2998         if (!(cr0 & X86_CR0_WP))
2999                 *hw_cr0 &= ~X86_CR0_WP;
3000 }
3001
3002 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3003 {
3004         struct vcpu_vmx *vmx = to_vmx(vcpu);
3005         unsigned long hw_cr0;
3006
3007         if (enable_unrestricted_guest)
3008                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3009                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3010         else
3011                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
3012
3013         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3014                 enter_pmode(vcpu);
3015
3016         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3017                 enter_rmode(vcpu);
3018
3019 #ifdef CONFIG_X86_64
3020         if (vcpu->arch.efer & EFER_LME) {
3021                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3022                         enter_lmode(vcpu);
3023                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3024                         exit_lmode(vcpu);
3025         }
3026 #endif
3027
3028         if (enable_ept)
3029                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3030
3031         if (!vcpu->fpu_active)
3032                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3033
3034         vmcs_writel(CR0_READ_SHADOW, cr0);
3035         vmcs_writel(GUEST_CR0, hw_cr0);
3036         vcpu->arch.cr0 = cr0;
3037         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3038 }
3039
3040 static u64 construct_eptp(unsigned long root_hpa)
3041 {
3042         u64 eptp;
3043
3044         /* TODO write the value reading from MSR */
3045         eptp = VMX_EPT_DEFAULT_MT |
3046                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3047         if (enable_ept_ad_bits)
3048                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3049         eptp |= (root_hpa & PAGE_MASK);
3050
3051         return eptp;
3052 }
3053
3054 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3055 {
3056         unsigned long guest_cr3;
3057         u64 eptp;
3058
3059         guest_cr3 = cr3;
3060         if (enable_ept) {
3061                 eptp = construct_eptp(cr3);
3062                 vmcs_write64(EPT_POINTER, eptp);
3063                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3064                         vcpu->kvm->arch.ept_identity_map_addr;
3065                 ept_load_pdptrs(vcpu);
3066         }
3067
3068         vmx_flush_tlb(vcpu);
3069         vmcs_writel(GUEST_CR3, guest_cr3);
3070 }
3071
3072 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3073 {
3074         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3075                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3076
3077         if (cr4 & X86_CR4_VMXE) {
3078                 /*
3079                  * To use VMXON (and later other VMX instructions), a guest
3080                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3081                  * So basically the check on whether to allow nested VMX
3082                  * is here.
3083                  */
3084                 if (!nested_vmx_allowed(vcpu))
3085                         return 1;
3086         } else if (to_vmx(vcpu)->nested.vmxon)
3087                 return 1;
3088
3089         vcpu->arch.cr4 = cr4;
3090         if (enable_ept) {
3091                 if (!is_paging(vcpu)) {
3092                         hw_cr4 &= ~X86_CR4_PAE;
3093                         hw_cr4 |= X86_CR4_PSE;
3094                 } else if (!(cr4 & X86_CR4_PAE)) {
3095                         hw_cr4 &= ~X86_CR4_PAE;
3096                 }
3097         }
3098
3099         vmcs_writel(CR4_READ_SHADOW, cr4);
3100         vmcs_writel(GUEST_CR4, hw_cr4);
3101         return 0;
3102 }
3103
3104 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3105                             struct kvm_segment *var, int seg)
3106 {
3107         struct vcpu_vmx *vmx = to_vmx(vcpu);
3108         u32 ar;
3109
3110         if (vmx->rmode.vm86_active
3111             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3112                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3113                 || seg == VCPU_SREG_GS)) {
3114                 *var = vmx->rmode.segs[seg];
3115                 if (seg == VCPU_SREG_TR
3116                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3117                         return;
3118                 var->base = vmx_read_guest_seg_base(vmx, seg);
3119                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3120                 return;
3121         }
3122         var->base = vmx_read_guest_seg_base(vmx, seg);
3123         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3124         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3125         ar = vmx_read_guest_seg_ar(vmx, seg);
3126         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3127                 ar = 0;
3128         var->type = ar & 15;
3129         var->s = (ar >> 4) & 1;
3130         var->dpl = (ar >> 5) & 3;
3131         var->present = (ar >> 7) & 1;
3132         var->avl = (ar >> 12) & 1;
3133         var->l = (ar >> 13) & 1;
3134         var->db = (ar >> 14) & 1;
3135         var->g = (ar >> 15) & 1;
3136         var->unusable = (ar >> 16) & 1;
3137 }
3138
3139 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3140 {
3141         struct kvm_segment s;
3142
3143         if (to_vmx(vcpu)->rmode.vm86_active) {
3144                 vmx_get_segment(vcpu, &s, seg);
3145                 return s.base;
3146         }
3147         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3148 }
3149
3150 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3151 {
3152         if (!is_protmode(vcpu))
3153                 return 0;
3154
3155         if (!is_long_mode(vcpu)
3156             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3157                 return 3;
3158
3159         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3160 }
3161
3162 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3163 {
3164         struct vcpu_vmx *vmx = to_vmx(vcpu);
3165
3166         /*
3167          * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3168          * fail; use the cache instead.
3169          */
3170         if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3171                 return vmx->cpl;
3172         }
3173
3174         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3175                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3176                 vmx->cpl = __vmx_get_cpl(vcpu);
3177         }
3178
3179         return vmx->cpl;
3180 }
3181
3182
3183 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3184 {
3185         u32 ar;
3186
3187         if (var->unusable || !var->present)
3188                 ar = 1 << 16;
3189         else {
3190                 ar = var->type & 15;
3191                 ar |= (var->s & 1) << 4;
3192                 ar |= (var->dpl & 3) << 5;
3193                 ar |= (var->present & 1) << 7;
3194                 ar |= (var->avl & 1) << 12;
3195                 ar |= (var->l & 1) << 13;
3196                 ar |= (var->db & 1) << 14;
3197                 ar |= (var->g & 1) << 15;
3198         }
3199
3200         return ar;
3201 }
3202
3203 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3204                             struct kvm_segment *var, int seg)
3205 {
3206         struct vcpu_vmx *vmx = to_vmx(vcpu);
3207         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3208         u32 ar;
3209
3210         vmx_segment_cache_clear(vmx);
3211
3212         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3213                 vmcs_write16(sf->selector, var->selector);
3214                 vmx->rmode.segs[VCPU_SREG_TR] = *var;
3215                 return;
3216         }
3217         vmcs_writel(sf->base, var->base);
3218         vmcs_write32(sf->limit, var->limit);
3219         vmcs_write16(sf->selector, var->selector);
3220         if (vmx->rmode.vm86_active && var->s) {
3221                 vmx->rmode.segs[seg] = *var;
3222                 /*
3223                  * Hack real-mode segments into vm86 compatibility.
3224                  */
3225                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3226                         vmcs_writel(sf->base, 0xf0000);
3227                 ar = 0xf3;
3228         } else
3229                 ar = vmx_segment_access_rights(var);
3230
3231         /*
3232          *   Fix the "Accessed" bit in AR field of segment registers for older
3233          * qemu binaries.
3234          *   IA32 arch specifies that at the time of processor reset the
3235          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3236          * is setting it to 0 in the userland code. This causes invalid guest
3237          * state vmexit when "unrestricted guest" mode is turned on.
3238          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3239          * tree. Newer qemu binaries with that qemu fix would not need this
3240          * kvm hack.
3241          */
3242         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3243                 ar |= 0x1; /* Accessed */
3244
3245         vmcs_write32(sf->ar_bytes, ar);
3246         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3247
3248         /*
3249          * Fix segments for real mode guest in hosts that don't have
3250          * "unrestricted_mode" or it was disabled.
3251          * This is done to allow migration of the guests from hosts with
3252          * unrestricted guest like Westmere to older host that don't have
3253          * unrestricted guest like Nehelem.
3254          */
3255         if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3256                 switch (seg) {
3257                 case VCPU_SREG_CS:
3258                         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3259                         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3260                         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3261                                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3262                         vmcs_write16(GUEST_CS_SELECTOR,
3263                                      vmcs_readl(GUEST_CS_BASE) >> 4);
3264                         break;
3265                 case VCPU_SREG_ES:
3266                 case VCPU_SREG_DS:
3267                 case VCPU_SREG_GS:
3268                 case VCPU_SREG_FS:
3269                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3270                         break;
3271                 case VCPU_SREG_SS:
3272                         vmcs_write16(GUEST_SS_SELECTOR,
3273                                      vmcs_readl(GUEST_SS_BASE) >> 4);
3274                         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3275                         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3276                         break;
3277                 }
3278         }
3279 }
3280
3281 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3282 {
3283         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3284
3285         *db = (ar >> 14) & 1;
3286         *l = (ar >> 13) & 1;
3287 }
3288
3289 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3290 {
3291         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3292         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3293 }
3294
3295 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3296 {
3297         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3298         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3299 }
3300
3301 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3302 {
3303         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3304         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3305 }
3306
3307 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3308 {
3309         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3310         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3311 }
3312
3313 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3314 {
3315         struct kvm_segment var;
3316         u32 ar;
3317
3318         vmx_get_segment(vcpu, &var, seg);
3319         ar = vmx_segment_access_rights(&var);
3320
3321         if (var.base != (var.selector << 4))
3322                 return false;
3323         if (var.limit < 0xffff)
3324                 return false;
3325         if (((ar | (3 << AR_DPL_SHIFT)) & ~(AR_G_MASK | AR_DB_MASK)) != 0xf3)
3326                 return false;
3327
3328         return true;
3329 }
3330
3331 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3332 {
3333         struct kvm_segment cs;
3334         unsigned int cs_rpl;
3335
3336         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3337         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3338
3339         if (cs.unusable)
3340                 return false;
3341         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3342                 return false;
3343         if (!cs.s)
3344                 return false;
3345         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3346                 if (cs.dpl > cs_rpl)
3347                         return false;
3348         } else {
3349                 if (cs.dpl != cs_rpl)
3350                         return false;
3351         }
3352         if (!cs.present)
3353                 return false;
3354
3355         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3356         return true;
3357 }
3358
3359 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3360 {
3361         struct kvm_segment ss;
3362         unsigned int ss_rpl;
3363
3364         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3365         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3366
3367         if (ss.unusable)
3368                 return true;
3369         if (ss.type != 3 && ss.type != 7)
3370                 return false;
3371         if (!ss.s)
3372                 return false;
3373         if (ss.dpl != ss_rpl) /* DPL != RPL */
3374                 return false;
3375         if (!ss.present)
3376                 return false;
3377
3378         return true;
3379 }
3380
3381 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3382 {
3383         struct kvm_segment var;
3384         unsigned int rpl;
3385
3386         vmx_get_segment(vcpu, &var, seg);
3387         rpl = var.selector & SELECTOR_RPL_MASK;
3388
3389         if (var.unusable)
3390                 return true;
3391         if (!var.s)
3392                 return false;
3393         if (!var.present)
3394                 return false;
3395         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3396                 if (var.dpl < rpl) /* DPL < RPL */
3397                         return false;
3398         }
3399
3400         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3401          * rights flags
3402          */
3403         return true;
3404 }
3405
3406 static bool tr_valid(struct kvm_vcpu *vcpu)
3407 {
3408         struct kvm_segment tr;
3409
3410         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3411
3412         if (tr.unusable)
3413                 return false;
3414         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3415                 return false;
3416         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3417                 return false;
3418         if (!tr.present)
3419                 return false;
3420
3421         return true;
3422 }
3423
3424 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3425 {
3426         struct kvm_segment ldtr;
3427
3428         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3429
3430         if (ldtr.unusable)
3431                 return true;
3432         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3433                 return false;
3434         if (ldtr.type != 2)
3435                 return false;
3436         if (!ldtr.present)
3437                 return false;
3438
3439         return true;
3440 }
3441
3442 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3443 {
3444         struct kvm_segment cs, ss;
3445
3446         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3447         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3448
3449         return ((cs.selector & SELECTOR_RPL_MASK) ==
3450                  (ss.selector & SELECTOR_RPL_MASK));
3451 }
3452
3453 /*
3454  * Check if guest state is valid. Returns true if valid, false if
3455  * not.
3456  * We assume that registers are always usable
3457  */
3458 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3459 {
3460         /* real mode guest state checks */
3461         if (!is_protmode(vcpu)) {
3462                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3463                         return false;
3464                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3465                         return false;
3466                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3467                         return false;
3468                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3469                         return false;
3470                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3471                         return false;
3472                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3473                         return false;
3474         } else {
3475         /* protected mode guest state checks */
3476                 if (!cs_ss_rpl_check(vcpu))
3477                         return false;
3478                 if (!code_segment_valid(vcpu))
3479                         return false;
3480                 if (!stack_segment_valid(vcpu))
3481                         return false;
3482                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3483                         return false;
3484                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3485                         return false;
3486                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3487                         return false;
3488                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3489                         return false;
3490                 if (!tr_valid(vcpu))
3491                         return false;
3492                 if (!ldtr_valid(vcpu))
3493                         return false;
3494         }
3495         /* TODO:
3496          * - Add checks on RIP
3497          * - Add checks on RFLAGS
3498          */
3499
3500         return true;
3501 }
3502
3503 static int init_rmode_tss(struct kvm *kvm)
3504 {
3505         gfn_t fn;
3506         u16 data = 0;
3507         int r, idx, ret = 0;
3508
3509         idx = srcu_read_lock(&kvm->srcu);
3510         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3511         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3512         if (r < 0)
3513                 goto out;
3514         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3515         r = kvm_write_guest_page(kvm, fn++, &data,
3516                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3517         if (r < 0)
3518                 goto out;
3519         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3520         if (r < 0)
3521                 goto out;
3522         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3523         if (r < 0)
3524                 goto out;
3525         data = ~0;
3526         r = kvm_write_guest_page(kvm, fn, &data,
3527                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3528                                  sizeof(u8));
3529         if (r < 0)
3530                 goto out;
3531
3532         ret = 1;
3533 out:
3534         srcu_read_unlock(&kvm->srcu, idx);
3535         return ret;
3536 }
3537
3538 static int init_rmode_identity_map(struct kvm *kvm)
3539 {
3540         int i, idx, r, ret;
3541         pfn_t identity_map_pfn;
3542         u32 tmp;
3543
3544         if (!enable_ept)
3545                 return 1;
3546         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3547                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3548                         "haven't been allocated!\n");
3549                 return 0;
3550         }
3551         if (likely(kvm->arch.ept_identity_pagetable_done))
3552                 return 1;
3553         ret = 0;
3554         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3555         idx = srcu_read_lock(&kvm->srcu);
3556         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3557         if (r < 0)
3558                 goto out;
3559         /* Set up identity-mapping pagetable for EPT in real mode */
3560         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3561                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3562                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3563                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3564                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3565                 if (r < 0)
3566                         goto out;
3567         }
3568         kvm->arch.ept_identity_pagetable_done = true;
3569         ret = 1;
3570 out:
3571         srcu_read_unlock(&kvm->srcu, idx);
3572         return ret;
3573 }
3574
3575 static void seg_setup(int seg)
3576 {
3577         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3578         unsigned int ar;
3579
3580         vmcs_write16(sf->selector, 0);
3581         vmcs_writel(sf->base, 0);
3582         vmcs_write32(sf->limit, 0xffff);
3583         if (enable_unrestricted_guest) {
3584                 ar = 0x93;
3585                 if (seg == VCPU_SREG_CS)
3586                         ar |= 0x08; /* code segment */
3587         } else
3588                 ar = 0xf3;
3589
3590         vmcs_write32(sf->ar_bytes, ar);
3591 }
3592
3593 static int alloc_apic_access_page(struct kvm *kvm)
3594 {
3595         struct kvm_userspace_memory_region kvm_userspace_mem;
3596         int r = 0;
3597
3598         mutex_lock(&kvm->slots_lock);
3599         if (kvm->arch.apic_access_page)
3600                 goto out;
3601         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3602         kvm_userspace_mem.flags = 0;
3603         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3604         kvm_userspace_mem.memory_size = PAGE_SIZE;
3605         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3606         if (r)
3607                 goto out;
3608
3609         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3610 out:
3611         mutex_unlock(&kvm->slots_lock);
3612         return r;
3613 }
3614
3615 static int alloc_identity_pagetable(struct kvm *kvm)
3616 {
3617         struct kvm_userspace_memory_region kvm_userspace_mem;
3618         int r = 0;
3619
3620         mutex_lock(&kvm->slots_lock);
3621         if (kvm->arch.ept_identity_pagetable)
3622                 goto out;
3623         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3624         kvm_userspace_mem.flags = 0;
3625         kvm_userspace_mem.guest_phys_addr =
3626                 kvm->arch.ept_identity_map_addr;
3627         kvm_userspace_mem.memory_size = PAGE_SIZE;
3628         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3629         if (r)
3630                 goto out;
3631
3632         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3633                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3634 out:
3635         mutex_unlock(&kvm->slots_lock);
3636         return r;
3637 }
3638
3639 static void allocate_vpid(struct vcpu_vmx *vmx)
3640 {
3641         int vpid;
3642
3643         vmx->vpid = 0;
3644         if (!enable_vpid)
3645                 return;
3646         spin_lock(&vmx_vpid_lock);
3647         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3648         if (vpid < VMX_NR_VPIDS) {
3649                 vmx->vpid = vpid;
3650                 __set_bit(vpid, vmx_vpid_bitmap);
3651         }
3652         spin_unlock(&vmx_vpid_lock);
3653 }
3654
3655 static void free_vpid(struct vcpu_vmx *vmx)
3656 {
3657         if (!enable_vpid)
3658                 return;
3659         spin_lock(&vmx_vpid_lock);
3660         if (vmx->vpid != 0)
3661                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3662         spin_unlock(&vmx_vpid_lock);
3663 }
3664
3665 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3666 {
3667         int f = sizeof(unsigned long);
3668
3669         if (!cpu_has_vmx_msr_bitmap())
3670                 return;
3671
3672         /*
3673          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3674          * have the write-low and read-high bitmap offsets the wrong way round.
3675          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3676          */
3677         if (msr <= 0x1fff) {
3678                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3679                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3680         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3681                 msr &= 0x1fff;
3682                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3683                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3684         }
3685 }
3686
3687 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3688 {
3689         if (!longmode_only)
3690                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3691         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3692 }
3693
3694 /*
3695  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3696  * will not change in the lifetime of the guest.
3697  * Note that host-state that does change is set elsewhere. E.g., host-state
3698  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3699  */
3700 static void vmx_set_constant_host_state(void)
3701 {
3702         u32 low32, high32;
3703         unsigned long tmpl;
3704         struct desc_ptr dt;
3705
3706         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3707         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3708         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3709
3710         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3711 #ifdef CONFIG_X86_64
3712         /*
3713          * Load null selectors, so we can avoid reloading them in
3714          * __vmx_load_host_state(), in case userspace uses the null selectors
3715          * too (the expected case).
3716          */
3717         vmcs_write16(HOST_DS_SELECTOR, 0);
3718         vmcs_write16(HOST_ES_SELECTOR, 0);
3719 #else
3720         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3721         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3722 #endif
3723         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3724         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3725
3726         native_store_idt(&dt);
3727         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3728
3729         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
3730
3731         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3732         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3733         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3734         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3735
3736         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3737                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3738                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3739         }
3740 }
3741
3742 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3743 {
3744         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3745         if (enable_ept)
3746                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3747         if (is_guest_mode(&vmx->vcpu))
3748                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3749                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3750         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3751 }
3752
3753 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3754 {
3755         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3756         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3757                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3758 #ifdef CONFIG_X86_64
3759                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3760                                 CPU_BASED_CR8_LOAD_EXITING;
3761 #endif
3762         }
3763         if (!enable_ept)
3764                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3765                                 CPU_BASED_CR3_LOAD_EXITING  |
3766                                 CPU_BASED_INVLPG_EXITING;
3767         return exec_control;
3768 }
3769
3770 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3771 {
3772         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3773         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3774                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3775         if (vmx->vpid == 0)
3776                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3777         if (!enable_ept) {
3778                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3779                 enable_unrestricted_guest = 0;
3780                 /* Enable INVPCID for non-ept guests may cause performance regression. */
3781                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3782         }
3783         if (!enable_unrestricted_guest)
3784                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3785         if (!ple_gap)
3786                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3787         return exec_control;
3788 }
3789
3790 static void ept_set_mmio_spte_mask(void)
3791 {
3792         /*
3793          * EPT Misconfigurations can be generated if the value of bits 2:0
3794          * of an EPT paging-structure entry is 110b (write/execute).
3795          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3796          * spte.
3797          */
3798         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3799 }
3800
3801 /*
3802  * Sets up the vmcs for emulated real mode.
3803  */
3804 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3805 {
3806 #ifdef CONFIG_X86_64
3807         unsigned long a;
3808 #endif
3809         int i;
3810
3811         /* I/O */
3812         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3813         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3814
3815         if (cpu_has_vmx_msr_bitmap())
3816                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3817
3818         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3819
3820         /* Control */
3821         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3822                 vmcs_config.pin_based_exec_ctrl);
3823
3824         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3825
3826         if (cpu_has_secondary_exec_ctrls()) {
3827                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3828                                 vmx_secondary_exec_control(vmx));
3829         }
3830
3831         if (ple_gap) {
3832                 vmcs_write32(PLE_GAP, ple_gap);
3833                 vmcs_write32(PLE_WINDOW, ple_window);
3834         }
3835
3836         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3837         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3838         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3839
3840         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3841         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3842         vmx_set_constant_host_state();
3843 #ifdef CONFIG_X86_64
3844         rdmsrl(MSR_FS_BASE, a);
3845         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3846         rdmsrl(MSR_GS_BASE, a);
3847         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3848 #else
3849         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3850         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3851 #endif
3852
3853         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3854         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3855         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3856         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3857         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3858
3859         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3860                 u32 msr_low, msr_high;
3861                 u64 host_pat;
3862                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3863                 host_pat = msr_low | ((u64) msr_high << 32);
3864                 /* Write the default value follow host pat */
3865                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3866                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3867                 vmx->vcpu.arch.pat = host_pat;
3868         }
3869
3870         for (i = 0; i < NR_VMX_MSR; ++i) {
3871                 u32 index = vmx_msr_index[i];
3872                 u32 data_low, data_high;
3873                 int j = vmx->nmsrs;
3874
3875                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3876                         continue;
3877                 if (wrmsr_safe(index, data_low, data_high) < 0)
3878                         continue;
3879                 vmx->guest_msrs[j].index = i;
3880                 vmx->guest_msrs[j].data = 0;
3881                 vmx->guest_msrs[j].mask = -1ull;
3882                 ++vmx->nmsrs;
3883         }
3884
3885         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3886
3887         /* 22.2.1, 20.8.1 */
3888         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3889
3890         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3891         set_cr4_guest_host_mask(vmx);
3892
3893         kvm_write_tsc(&vmx->vcpu, 0);
3894
3895         return 0;
3896 }
3897
3898 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3899 {
3900         struct vcpu_vmx *vmx = to_vmx(vcpu);
3901         u64 msr;
3902         int ret;
3903
3904         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3905
3906         vmx->rmode.vm86_active = 0;
3907
3908         vmx->soft_vnmi_blocked = 0;
3909
3910         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3911         kvm_set_cr8(&vmx->vcpu, 0);
3912         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3913         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3914                 msr |= MSR_IA32_APICBASE_BSP;
3915         kvm_set_apic_base(&vmx->vcpu, msr);
3916
3917         ret = fx_init(&vmx->vcpu);
3918         if (ret != 0)
3919                 goto out;
3920
3921         vmx_segment_cache_clear(vmx);
3922
3923         seg_setup(VCPU_SREG_CS);
3924         /*
3925          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3926          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3927          */
3928         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3929                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3930                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3931         } else {
3932                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3933                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3934         }
3935
3936         seg_setup(VCPU_SREG_DS);
3937         seg_setup(VCPU_SREG_ES);
3938         seg_setup(VCPU_SREG_FS);
3939         seg_setup(VCPU_SREG_GS);
3940         seg_setup(VCPU_SREG_SS);
3941
3942         vmcs_write16(GUEST_TR_SELECTOR, 0);
3943         vmcs_writel(GUEST_TR_BASE, 0);
3944         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3945         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3946
3947         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3948         vmcs_writel(GUEST_LDTR_BASE, 0);
3949         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3950         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3951
3952         vmcs_write32(GUEST_SYSENTER_CS, 0);
3953         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3954         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3955
3956         vmcs_writel(GUEST_RFLAGS, 0x02);
3957         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3958                 kvm_rip_write(vcpu, 0xfff0);
3959         else
3960                 kvm_rip_write(vcpu, 0);
3961         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3962
3963         vmcs_writel(GUEST_DR7, 0x400);
3964
3965         vmcs_writel(GUEST_GDTR_BASE, 0);
3966         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3967
3968         vmcs_writel(GUEST_IDTR_BASE, 0);
3969         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3970
3971         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3972         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3973         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3974
3975         /* Special registers */
3976         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3977
3978         setup_msrs(vmx);
3979
3980         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3981
3982         if (cpu_has_vmx_tpr_shadow()) {
3983                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3984                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3985                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3986                                      __pa(vmx->vcpu.arch.apic->regs));
3987                 vmcs_write32(TPR_THRESHOLD, 0);
3988         }
3989
3990         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3991                 vmcs_write64(APIC_ACCESS_ADDR,
3992                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3993
3994         if (vmx->vpid != 0)
3995                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3996
3997         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3998         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3999         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4000         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4001         vmx_set_cr4(&vmx->vcpu, 0);
4002         vmx_set_efer(&vmx->vcpu, 0);
4003         vmx_fpu_activate(&vmx->vcpu);
4004         update_exception_bitmap(&vmx->vcpu);
4005
4006         vpid_sync_context(vmx);
4007
4008         ret = 0;
4009
4010         /* HACK: Don't enable emulation on guest boot/reset */
4011         vmx->emulation_required = 0;
4012
4013 out:
4014         return ret;
4015 }
4016
4017 /*
4018  * In nested virtualization, check if L1 asked to exit on external interrupts.
4019  * For most existing hypervisors, this will always return true.
4020  */
4021 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4022 {
4023         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4024                 PIN_BASED_EXT_INTR_MASK;
4025 }
4026
4027 static void enable_irq_window(struct kvm_vcpu *vcpu)
4028 {
4029         u32 cpu_based_vm_exec_control;
4030         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4031                 /*
4032                  * We get here if vmx_interrupt_allowed() said we can't
4033                  * inject to L1 now because L2 must run. Ask L2 to exit
4034                  * right after entry, so we can inject to L1 more promptly.
4035                  */
4036                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4037                 return;
4038         }
4039
4040         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4041         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4042         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4043 }
4044
4045 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4046 {
4047         u32 cpu_based_vm_exec_control;
4048
4049         if (!cpu_has_virtual_nmis()) {
4050                 enable_irq_window(vcpu);
4051                 return;
4052         }
4053
4054         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4055                 enable_irq_window(vcpu);
4056                 return;
4057         }
4058         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4059         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4060         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4061 }
4062
4063 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4064 {
4065         struct vcpu_vmx *vmx = to_vmx(vcpu);
4066         uint32_t intr;
4067         int irq = vcpu->arch.interrupt.nr;
4068
4069         trace_kvm_inj_virq(irq);
4070
4071         ++vcpu->stat.irq_injections;
4072         if (vmx->rmode.vm86_active) {
4073                 int inc_eip = 0;
4074                 if (vcpu->arch.interrupt.soft)
4075                         inc_eip = vcpu->arch.event_exit_inst_len;
4076                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4077                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4078                 return;
4079         }
4080         intr = irq | INTR_INFO_VALID_MASK;
4081         if (vcpu->arch.interrupt.soft) {
4082                 intr |= INTR_TYPE_SOFT_INTR;
4083                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4084                              vmx->vcpu.arch.event_exit_inst_len);
4085         } else
4086                 intr |= INTR_TYPE_EXT_INTR;
4087         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4088 }
4089
4090 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4091 {
4092         struct vcpu_vmx *vmx = to_vmx(vcpu);
4093
4094         if (is_guest_mode(vcpu))
4095                 return;
4096
4097         if (!cpu_has_virtual_nmis()) {
4098                 /*
4099                  * Tracking the NMI-blocked state in software is built upon
4100                  * finding the next open IRQ window. This, in turn, depends on
4101                  * well-behaving guests: They have to keep IRQs disabled at
4102                  * least as long as the NMI handler runs. Otherwise we may
4103                  * cause NMI nesting, maybe breaking the guest. But as this is
4104                  * highly unlikely, we can live with the residual risk.
4105                  */
4106                 vmx->soft_vnmi_blocked = 1;
4107                 vmx->vnmi_blocked_time = 0;
4108         }
4109
4110         ++vcpu->stat.nmi_injections;
4111         vmx->nmi_known_unmasked = false;
4112         if (vmx->rmode.vm86_active) {
4113                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4114                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4115                 return;
4116         }
4117         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4118                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4119 }
4120
4121 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4122 {
4123         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4124                 return 0;
4125
4126         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4127                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4128                    | GUEST_INTR_STATE_NMI));
4129 }
4130
4131 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4132 {
4133         if (!cpu_has_virtual_nmis())
4134                 return to_vmx(vcpu)->soft_vnmi_blocked;
4135         if (to_vmx(vcpu)->nmi_known_unmasked)
4136                 return false;
4137         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4138 }
4139
4140 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4141 {
4142         struct vcpu_vmx *vmx = to_vmx(vcpu);
4143
4144         if (!cpu_has_virtual_nmis()) {
4145                 if (vmx->soft_vnmi_blocked != masked) {
4146                         vmx->soft_vnmi_blocked = masked;
4147                         vmx->vnmi_blocked_time = 0;
4148                 }
4149         } else {
4150                 vmx->nmi_known_unmasked = !masked;
4151                 if (masked)
4152                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4153                                       GUEST_INTR_STATE_NMI);
4154                 else
4155                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4156                                         GUEST_INTR_STATE_NMI);
4157         }
4158 }
4159
4160 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4161 {
4162         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4163                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4164                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4165                     (vmcs12->idt_vectoring_info_field &
4166                      VECTORING_INFO_VALID_MASK))
4167                         return 0;
4168                 nested_vmx_vmexit(vcpu);
4169                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4170                 vmcs12->vm_exit_intr_info = 0;
4171                 /* fall through to normal code, but now in L1, not L2 */
4172         }
4173
4174         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4175                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4176                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4177 }
4178
4179 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4180 {
4181         int ret;
4182         struct kvm_userspace_memory_region tss_mem = {
4183                 .slot = TSS_PRIVATE_MEMSLOT,
4184                 .guest_phys_addr = addr,
4185                 .memory_size = PAGE_SIZE * 3,
4186                 .flags = 0,
4187         };
4188
4189         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4190         if (ret)
4191                 return ret;
4192         kvm->arch.tss_addr = addr;
4193         if (!init_rmode_tss(kvm))
4194                 return  -ENOMEM;
4195
4196         return 0;
4197 }
4198
4199 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4200                                   int vec, u32 err_code)
4201 {
4202         /*
4203          * Instruction with address size override prefix opcode 0x67
4204          * Cause the #SS fault with 0 error code in VM86 mode.
4205          */
4206         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4207                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4208                         return 1;
4209         /*
4210          * Forward all other exceptions that are valid in real mode.
4211          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4212          *        the required debugging infrastructure rework.
4213          */
4214         switch (vec) {
4215         case DB_VECTOR:
4216                 if (vcpu->guest_debug &
4217                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4218                         return 0;
4219                 kvm_queue_exception(vcpu, vec);
4220                 return 1;
4221         case BP_VECTOR:
4222                 /*
4223                  * Update instruction length as we may reinject the exception
4224                  * from user space while in guest debugging mode.
4225                  */
4226                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4227                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4228                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4229                         return 0;
4230                 /* fall through */
4231         case DE_VECTOR:
4232         case OF_VECTOR:
4233         case BR_VECTOR:
4234         case UD_VECTOR:
4235         case DF_VECTOR:
4236         case SS_VECTOR:
4237         case GP_VECTOR:
4238         case MF_VECTOR:
4239                 kvm_queue_exception(vcpu, vec);
4240                 return 1;
4241         }
4242         return 0;
4243 }
4244
4245 /*
4246  * Trigger machine check on the host. We assume all the MSRs are already set up
4247  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4248  * We pass a fake environment to the machine check handler because we want
4249  * the guest to be always treated like user space, no matter what context
4250  * it used internally.
4251  */
4252 static void kvm_machine_check(void)
4253 {
4254 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4255         struct pt_regs regs = {
4256                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4257                 .flags = X86_EFLAGS_IF,
4258         };
4259
4260         do_machine_check(&regs, 0);
4261 #endif
4262 }
4263
4264 static int handle_machine_check(struct kvm_vcpu *vcpu)
4265 {
4266         /* already handled by vcpu_run */
4267         return 1;
4268 }
4269
4270 static int handle_exception(struct kvm_vcpu *vcpu)
4271 {
4272         struct vcpu_vmx *vmx = to_vmx(vcpu);
4273         struct kvm_run *kvm_run = vcpu->run;
4274         u32 intr_info, ex_no, error_code;
4275         unsigned long cr2, rip, dr6;
4276         u32 vect_info;
4277         enum emulation_result er;
4278
4279         vect_info = vmx->idt_vectoring_info;
4280         intr_info = vmx->exit_intr_info;
4281
4282         if (is_machine_check(intr_info))
4283                 return handle_machine_check(vcpu);
4284
4285         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4286             !is_page_fault(intr_info)) {
4287                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4288                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4289                 vcpu->run->internal.ndata = 2;
4290                 vcpu->run->internal.data[0] = vect_info;
4291                 vcpu->run->internal.data[1] = intr_info;
4292                 return 0;
4293         }
4294
4295         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4296                 return 1;  /* already handled by vmx_vcpu_run() */
4297
4298         if (is_no_device(intr_info)) {
4299                 vmx_fpu_activate(vcpu);
4300                 return 1;
4301         }
4302
4303         if (is_invalid_opcode(intr_info)) {
4304                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4305                 if (er != EMULATE_DONE)
4306                         kvm_queue_exception(vcpu, UD_VECTOR);
4307                 return 1;
4308         }
4309
4310         error_code = 0;
4311         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4312                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4313         if (is_page_fault(intr_info)) {
4314                 /* EPT won't cause page fault directly */
4315                 BUG_ON(enable_ept);
4316                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4317                 trace_kvm_page_fault(cr2, error_code);
4318
4319                 if (kvm_event_needs_reinjection(vcpu))
4320                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4321                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4322         }
4323
4324         if (vmx->rmode.vm86_active &&
4325             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4326                                                                 error_code)) {
4327                 if (vcpu->arch.halt_request) {
4328                         vcpu->arch.halt_request = 0;
4329                         return kvm_emulate_halt(vcpu);
4330                 }
4331                 return 1;
4332         }
4333
4334         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4335         switch (ex_no) {
4336         case DB_VECTOR:
4337                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4338                 if (!(vcpu->guest_debug &
4339                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4340                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4341                         kvm_queue_exception(vcpu, DB_VECTOR);
4342                         return 1;
4343                 }
4344                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4345                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4346                 /* fall through */
4347         case BP_VECTOR:
4348                 /*
4349                  * Update instruction length as we may reinject #BP from
4350                  * user space while in guest debugging mode. Reading it for
4351                  * #DB as well causes no harm, it is not used in that case.
4352                  */
4353                 vmx->vcpu.arch.event_exit_inst_len =
4354                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4355                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4356                 rip = kvm_rip_read(vcpu);
4357                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4358                 kvm_run->debug.arch.exception = ex_no;
4359                 break;
4360         default:
4361                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4362                 kvm_run->ex.exception = ex_no;
4363                 kvm_run->ex.error_code = error_code;
4364                 break;
4365         }
4366         return 0;
4367 }
4368
4369 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4370 {
4371         ++vcpu->stat.irq_exits;
4372         return 1;
4373 }
4374
4375 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4376 {
4377         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4378         return 0;
4379 }
4380
4381 static int handle_io(struct kvm_vcpu *vcpu)
4382 {
4383         unsigned long exit_qualification;
4384         int size, in, string;
4385         unsigned port;
4386
4387         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4388         string = (exit_qualification & 16) != 0;
4389         in = (exit_qualification & 8) != 0;
4390
4391         ++vcpu->stat.io_exits;
4392
4393         if (string || in)
4394                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4395
4396         port = exit_qualification >> 16;
4397         size = (exit_qualification & 7) + 1;
4398         skip_emulated_instruction(vcpu);
4399
4400         return kvm_fast_pio_out(vcpu, size, port);
4401 }
4402
4403 static void
4404 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4405 {
4406         /*
4407          * Patch in the VMCALL instruction:
4408          */
4409         hypercall[0] = 0x0f;
4410         hypercall[1] = 0x01;
4411         hypercall[2] = 0xc1;
4412 }
4413
4414 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4415 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4416 {
4417         if (to_vmx(vcpu)->nested.vmxon &&
4418             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4419                 return 1;
4420
4421         if (is_guest_mode(vcpu)) {
4422                 /*
4423                  * We get here when L2 changed cr0 in a way that did not change
4424                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4425                  * but did change L0 shadowed bits. This can currently happen
4426                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4427                  * loading) while pretending to allow the guest to change it.
4428                  */
4429                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4430                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4431                         return 1;
4432                 vmcs_writel(CR0_READ_SHADOW, val);
4433                 return 0;
4434         } else
4435                 return kvm_set_cr0(vcpu, val);
4436 }
4437
4438 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4439 {
4440         if (is_guest_mode(vcpu)) {
4441                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4442                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4443                         return 1;
4444                 vmcs_writel(CR4_READ_SHADOW, val);
4445                 return 0;
4446         } else
4447                 return kvm_set_cr4(vcpu, val);
4448 }
4449
4450 /* called to set cr0 as approriate for clts instruction exit. */
4451 static void handle_clts(struct kvm_vcpu *vcpu)
4452 {
4453         if (is_guest_mode(vcpu)) {
4454                 /*
4455                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4456                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4457                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4458                  */
4459                 vmcs_writel(CR0_READ_SHADOW,
4460                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4461                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4462         } else
4463                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4464 }
4465
4466 static int handle_cr(struct kvm_vcpu *vcpu)
4467 {
4468         unsigned long exit_qualification, val;
4469         int cr;
4470         int reg;
4471         int err;
4472
4473         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4474         cr = exit_qualification & 15;
4475         reg = (exit_qualification >> 8) & 15;
4476         switch ((exit_qualification >> 4) & 3) {
4477         case 0: /* mov to cr */
4478                 val = kvm_register_read(vcpu, reg);
4479                 trace_kvm_cr_write(cr, val);
4480                 switch (cr) {
4481                 case 0:
4482                         err = handle_set_cr0(vcpu, val);
4483                         kvm_complete_insn_gp(vcpu, err);
4484                         return 1;
4485                 case 3:
4486                         err = kvm_set_cr3(vcpu, val);
4487                         kvm_complete_insn_gp(vcpu, err);
4488                         return 1;
4489                 case 4:
4490                         err = handle_set_cr4(vcpu, val);
4491                         kvm_complete_insn_gp(vcpu, err);
4492                         return 1;
4493                 case 8: {
4494                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4495                                 u8 cr8 = kvm_register_read(vcpu, reg);
4496                                 err = kvm_set_cr8(vcpu, cr8);
4497                                 kvm_complete_insn_gp(vcpu, err);
4498                                 if (irqchip_in_kernel(vcpu->kvm))
4499                                         return 1;
4500                                 if (cr8_prev <= cr8)
4501                                         return 1;
4502                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4503                                 return 0;
4504                         }
4505                 };
4506                 break;
4507         case 2: /* clts */
4508                 handle_clts(vcpu);
4509                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4510                 skip_emulated_instruction(vcpu);
4511                 vmx_fpu_activate(vcpu);
4512                 return 1;
4513         case 1: /*mov from cr*/
4514                 switch (cr) {
4515                 case 3:
4516                         val = kvm_read_cr3(vcpu);
4517                         kvm_register_write(vcpu, reg, val);
4518                         trace_kvm_cr_read(cr, val);
4519                         skip_emulated_instruction(vcpu);
4520                         return 1;
4521                 case 8:
4522                         val = kvm_get_cr8(vcpu);
4523                         kvm_register_write(vcpu, reg, val);
4524                         trace_kvm_cr_read(cr, val);
4525                         skip_emulated_instruction(vcpu);
4526                         return 1;
4527                 }
4528                 break;
4529         case 3: /* lmsw */
4530                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4531                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4532                 kvm_lmsw(vcpu, val);
4533
4534                 skip_emulated_instruction(vcpu);
4535                 return 1;
4536         default:
4537                 break;
4538         }
4539         vcpu->run->exit_reason = 0;
4540         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4541                (int)(exit_qualification >> 4) & 3, cr);
4542         return 0;
4543 }
4544
4545 static int handle_dr(struct kvm_vcpu *vcpu)
4546 {
4547         unsigned long exit_qualification;
4548         int dr, reg;
4549
4550         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4551         if (!kvm_require_cpl(vcpu, 0))
4552                 return 1;
4553         dr = vmcs_readl(GUEST_DR7);
4554         if (dr & DR7_GD) {
4555                 /*
4556                  * As the vm-exit takes precedence over the debug trap, we
4557                  * need to emulate the latter, either for the host or the
4558                  * guest debugging itself.
4559                  */
4560                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4561                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4562                         vcpu->run->debug.arch.dr7 = dr;
4563                         vcpu->run->debug.arch.pc =
4564                                 vmcs_readl(GUEST_CS_BASE) +
4565                                 vmcs_readl(GUEST_RIP);
4566                         vcpu->run->debug.arch.exception = DB_VECTOR;
4567                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4568                         return 0;
4569                 } else {
4570                         vcpu->arch.dr7 &= ~DR7_GD;
4571                         vcpu->arch.dr6 |= DR6_BD;
4572                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4573                         kvm_queue_exception(vcpu, DB_VECTOR);
4574                         return 1;
4575                 }
4576         }
4577
4578         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4579         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4580         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4581         if (exit_qualification & TYPE_MOV_FROM_DR) {
4582                 unsigned long val;
4583                 if (!kvm_get_dr(vcpu, dr, &val))
4584                         kvm_register_write(vcpu, reg, val);
4585         } else
4586                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4587         skip_emulated_instruction(vcpu);
4588         return 1;
4589 }
4590
4591 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4592 {
4593         vmcs_writel(GUEST_DR7, val);
4594 }
4595
4596 static int handle_cpuid(struct kvm_vcpu *vcpu)
4597 {
4598         kvm_emulate_cpuid(vcpu);
4599         return 1;
4600 }
4601
4602 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4603 {
4604         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4605         u64 data;
4606
4607         if (vmx_get_msr(vcpu, ecx, &data)) {
4608                 trace_kvm_msr_read_ex(ecx);
4609                 kvm_inject_gp(vcpu, 0);
4610                 return 1;
4611         }
4612
4613         trace_kvm_msr_read(ecx, data);
4614
4615         /* FIXME: handling of bits 32:63 of rax, rdx */
4616         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4617         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4618         skip_emulated_instruction(vcpu);
4619         return 1;
4620 }
4621
4622 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4623 {
4624         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4625         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4626                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4627
4628         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4629                 trace_kvm_msr_write_ex(ecx, data);
4630                 kvm_inject_gp(vcpu, 0);
4631                 return 1;
4632         }
4633
4634         trace_kvm_msr_write(ecx, data);
4635         skip_emulated_instruction(vcpu);
4636         return 1;
4637 }
4638
4639 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4640 {
4641         kvm_make_request(KVM_REQ_EVENT, vcpu);
4642         return 1;
4643 }
4644
4645 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4646 {
4647         u32 cpu_based_vm_exec_control;
4648
4649         /* clear pending irq */
4650         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4651         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4652         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4653
4654         kvm_make_request(KVM_REQ_EVENT, vcpu);
4655
4656         ++vcpu->stat.irq_window_exits;
4657
4658         /*
4659          * If the user space waits to inject interrupts, exit as soon as
4660          * possible
4661          */
4662         if (!irqchip_in_kernel(vcpu->kvm) &&
4663             vcpu->run->request_interrupt_window &&
4664             !kvm_cpu_has_interrupt(vcpu)) {
4665                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4666                 return 0;
4667         }
4668         return 1;
4669 }
4670
4671 static int handle_halt(struct kvm_vcpu *vcpu)
4672 {
4673         skip_emulated_instruction(vcpu);
4674         return kvm_emulate_halt(vcpu);
4675 }
4676
4677 static int handle_vmcall(struct kvm_vcpu *vcpu)
4678 {
4679         skip_emulated_instruction(vcpu);
4680         kvm_emulate_hypercall(vcpu);
4681         return 1;
4682 }
4683
4684 static int handle_invd(struct kvm_vcpu *vcpu)
4685 {
4686         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4687 }
4688
4689 static int handle_invlpg(struct kvm_vcpu *vcpu)
4690 {
4691         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4692
4693         kvm_mmu_invlpg(vcpu, exit_qualification);
4694         skip_emulated_instruction(vcpu);
4695         return 1;
4696 }
4697
4698 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4699 {
4700         int err;
4701
4702         err = kvm_rdpmc(vcpu);
4703         kvm_complete_insn_gp(vcpu, err);
4704
4705         return 1;
4706 }
4707
4708 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4709 {
4710         skip_emulated_instruction(vcpu);
4711         kvm_emulate_wbinvd(vcpu);
4712         return 1;
4713 }
4714
4715 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4716 {
4717         u64 new_bv = kvm_read_edx_eax(vcpu);
4718         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4719
4720         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4721                 skip_emulated_instruction(vcpu);
4722         return 1;
4723 }
4724
4725 static int handle_apic_access(struct kvm_vcpu *vcpu)
4726 {
4727         if (likely(fasteoi)) {
4728                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4729                 int access_type, offset;
4730
4731                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4732                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4733                 /*
4734                  * Sane guest uses MOV to write EOI, with written value
4735                  * not cared. So make a short-circuit here by avoiding
4736                  * heavy instruction emulation.
4737                  */
4738                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4739                     (offset == APIC_EOI)) {
4740                         kvm_lapic_set_eoi(vcpu);
4741                         skip_emulated_instruction(vcpu);
4742                         return 1;
4743                 }
4744         }
4745         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4746 }
4747
4748 static int handle_task_switch(struct kvm_vcpu *vcpu)
4749 {
4750         struct vcpu_vmx *vmx = to_vmx(vcpu);
4751         unsigned long exit_qualification;
4752         bool has_error_code = false;
4753         u32 error_code = 0;
4754         u16 tss_selector;
4755         int reason, type, idt_v, idt_index;
4756
4757         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4758         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4759         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4760
4761         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4762
4763         reason = (u32)exit_qualification >> 30;
4764         if (reason == TASK_SWITCH_GATE && idt_v) {
4765                 switch (type) {
4766                 case INTR_TYPE_NMI_INTR:
4767                         vcpu->arch.nmi_injected = false;
4768                         vmx_set_nmi_mask(vcpu, true);
4769                         break;
4770                 case INTR_TYPE_EXT_INTR:
4771                 case INTR_TYPE_SOFT_INTR:
4772                         kvm_clear_interrupt_queue(vcpu);
4773                         break;
4774                 case INTR_TYPE_HARD_EXCEPTION:
4775                         if (vmx->idt_vectoring_info &
4776                             VECTORING_INFO_DELIVER_CODE_MASK) {
4777                                 has_error_code = true;
4778                                 error_code =
4779                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4780                         }
4781                         /* fall through */
4782                 case INTR_TYPE_SOFT_EXCEPTION:
4783                         kvm_clear_exception_queue(vcpu);
4784                         break;
4785                 default:
4786                         break;
4787                 }
4788         }
4789         tss_selector = exit_qualification;
4790
4791         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4792                        type != INTR_TYPE_EXT_INTR &&
4793                        type != INTR_TYPE_NMI_INTR))
4794                 skip_emulated_instruction(vcpu);
4795
4796         if (kvm_task_switch(vcpu, tss_selector,
4797                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4798                             has_error_code, error_code) == EMULATE_FAIL) {
4799                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4800                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4801                 vcpu->run->internal.ndata = 0;
4802                 return 0;
4803         }
4804
4805         /* clear all local breakpoint enable flags */
4806         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4807
4808         /*
4809          * TODO: What about debug traps on tss switch?
4810          *       Are we supposed to inject them and update dr6?
4811          */
4812
4813         return 1;
4814 }
4815
4816 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4817 {
4818         unsigned long exit_qualification;
4819         gpa_t gpa;
4820         u32 error_code;
4821         int gla_validity;
4822
4823         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4824
4825         if (exit_qualification & (1 << 6)) {
4826                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4827                 return -EINVAL;
4828         }
4829
4830         gla_validity = (exit_qualification >> 7) & 0x3;
4831         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4832                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4833                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4834                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4835                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4836                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4837                         (long unsigned int)exit_qualification);
4838                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4839                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4840                 return 0;
4841         }
4842
4843         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4844         trace_kvm_page_fault(gpa, exit_qualification);
4845
4846         /* It is a write fault? */
4847         error_code = exit_qualification & (1U << 1);
4848         /* ept page table is present? */
4849         error_code |= (exit_qualification >> 3) & 0x1;
4850
4851         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
4852 }
4853
4854 static u64 ept_rsvd_mask(u64 spte, int level)
4855 {
4856         int i;
4857         u64 mask = 0;
4858
4859         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4860                 mask |= (1ULL << i);
4861
4862         if (level > 2)
4863                 /* bits 7:3 reserved */
4864                 mask |= 0xf8;
4865         else if (level == 2) {
4866                 if (spte & (1ULL << 7))
4867                         /* 2MB ref, bits 20:12 reserved */
4868                         mask |= 0x1ff000;
4869                 else
4870                         /* bits 6:3 reserved */
4871                         mask |= 0x78;
4872         }
4873
4874         return mask;
4875 }
4876
4877 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4878                                        int level)
4879 {
4880         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4881
4882         /* 010b (write-only) */
4883         WARN_ON((spte & 0x7) == 0x2);
4884
4885         /* 110b (write/execute) */
4886         WARN_ON((spte & 0x7) == 0x6);
4887
4888         /* 100b (execute-only) and value not supported by logical processor */
4889         if (!cpu_has_vmx_ept_execute_only())
4890                 WARN_ON((spte & 0x7) == 0x4);
4891
4892         /* not 000b */
4893         if ((spte & 0x7)) {
4894                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4895
4896                 if (rsvd_bits != 0) {
4897                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4898                                          __func__, rsvd_bits);
4899                         WARN_ON(1);
4900                 }
4901
4902                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4903                         u64 ept_mem_type = (spte & 0x38) >> 3;
4904
4905                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4906                             ept_mem_type == 7) {
4907                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4908                                                 __func__, ept_mem_type);
4909                                 WARN_ON(1);
4910                         }
4911                 }
4912         }
4913 }
4914
4915 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4916 {
4917         u64 sptes[4];
4918         int nr_sptes, i, ret;
4919         gpa_t gpa;
4920
4921         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4922
4923         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4924         if (likely(ret == 1))
4925                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4926                                               EMULATE_DONE;
4927         if (unlikely(!ret))
4928                 return 1;
4929
4930         /* It is the real ept misconfig */
4931         printk(KERN_ERR "EPT: Misconfiguration.\n");
4932         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4933
4934         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4935
4936         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4937                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4938
4939         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4940         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4941
4942         return 0;
4943 }
4944
4945 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4946 {
4947         u32 cpu_based_vm_exec_control;
4948
4949         /* clear pending NMI */
4950         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4951         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4952         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4953         ++vcpu->stat.nmi_window_exits;
4954         kvm_make_request(KVM_REQ_EVENT, vcpu);
4955
4956         return 1;
4957 }
4958
4959 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4960 {
4961         struct vcpu_vmx *vmx = to_vmx(vcpu);
4962         enum emulation_result err = EMULATE_DONE;
4963         int ret = 1;
4964         u32 cpu_exec_ctrl;
4965         bool intr_window_requested;
4966         unsigned count = 130;
4967
4968         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4969         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4970
4971         while (!guest_state_valid(vcpu) && count-- != 0) {
4972                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
4973                         return handle_interrupt_window(&vmx->vcpu);
4974
4975                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
4976                         return 1;
4977
4978                 err = emulate_instruction(vcpu, 0);
4979
4980                 if (err == EMULATE_DO_MMIO) {
4981                         ret = 0;
4982                         goto out;
4983                 }
4984
4985                 if (err != EMULATE_DONE) {
4986                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4987                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4988                         vcpu->run->internal.ndata = 0;
4989                         return 0;
4990                 }
4991
4992                 if (signal_pending(current))
4993                         goto out;
4994                 if (need_resched())
4995                         schedule();
4996         }
4997
4998         vmx->emulation_required = !guest_state_valid(vcpu);
4999 out:
5000         return ret;
5001 }
5002
5003 /*
5004  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5005  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5006  */
5007 static int handle_pause(struct kvm_vcpu *vcpu)
5008 {
5009         skip_emulated_instruction(vcpu);
5010         kvm_vcpu_on_spin(vcpu);
5011
5012         return 1;
5013 }
5014
5015 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5016 {
5017         kvm_queue_exception(vcpu, UD_VECTOR);
5018         return 1;
5019 }
5020
5021 /*
5022  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5023  * We could reuse a single VMCS for all the L2 guests, but we also want the
5024  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5025  * allows keeping them loaded on the processor, and in the future will allow
5026  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5027  * every entry if they never change.
5028  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5029  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5030  *
5031  * The following functions allocate and free a vmcs02 in this pool.
5032  */
5033
5034 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5035 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5036 {
5037         struct vmcs02_list *item;
5038         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5039                 if (item->vmptr == vmx->nested.current_vmptr) {
5040                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5041                         return &item->vmcs02;
5042                 }
5043
5044         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5045                 /* Recycle the least recently used VMCS. */
5046                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5047                         struct vmcs02_list, list);
5048                 item->vmptr = vmx->nested.current_vmptr;
5049                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5050                 return &item->vmcs02;
5051         }
5052
5053         /* Create a new VMCS */
5054         item = (struct vmcs02_list *)
5055                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5056         if (!item)
5057                 return NULL;
5058         item->vmcs02.vmcs = alloc_vmcs();
5059         if (!item->vmcs02.vmcs) {
5060                 kfree(item);
5061                 return NULL;
5062         }
5063         loaded_vmcs_init(&item->vmcs02);
5064         item->vmptr = vmx->nested.current_vmptr;
5065         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5066         vmx->nested.vmcs02_num++;
5067         return &item->vmcs02;
5068 }
5069
5070 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5071 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5072 {
5073         struct vmcs02_list *item;
5074         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5075                 if (item->vmptr == vmptr) {
5076                         free_loaded_vmcs(&item->vmcs02);
5077                         list_del(&item->list);
5078                         kfree(item);
5079                         vmx->nested.vmcs02_num--;
5080                         return;
5081                 }
5082 }
5083
5084 /*
5085  * Free all VMCSs saved for this vcpu, except the one pointed by
5086  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5087  * currently used, if running L2), and vmcs01 when running L2.
5088  */
5089 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5090 {
5091         struct vmcs02_list *item, *n;
5092         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5093                 if (vmx->loaded_vmcs != &item->vmcs02)
5094                         free_loaded_vmcs(&item->vmcs02);
5095                 list_del(&item->list);
5096                 kfree(item);
5097         }
5098         vmx->nested.vmcs02_num = 0;
5099
5100         if (vmx->loaded_vmcs != &vmx->vmcs01)
5101                 free_loaded_vmcs(&vmx->vmcs01);
5102 }
5103
5104 /*
5105  * Emulate the VMXON instruction.
5106  * Currently, we just remember that VMX is active, and do not save or even
5107  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5108  * do not currently need to store anything in that guest-allocated memory
5109  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5110  * argument is different from the VMXON pointer (which the spec says they do).
5111  */
5112 static int handle_vmon(struct kvm_vcpu *vcpu)
5113 {
5114         struct kvm_segment cs;
5115         struct vcpu_vmx *vmx = to_vmx(vcpu);
5116
5117         /* The Intel VMX Instruction Reference lists a bunch of bits that
5118          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5119          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5120          * Otherwise, we should fail with #UD. We test these now:
5121          */
5122         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5123             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5124             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5125                 kvm_queue_exception(vcpu, UD_VECTOR);
5126                 return 1;
5127         }
5128
5129         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5130         if (is_long_mode(vcpu) && !cs.l) {
5131                 kvm_queue_exception(vcpu, UD_VECTOR);
5132                 return 1;
5133         }
5134
5135         if (vmx_get_cpl(vcpu)) {
5136                 kvm_inject_gp(vcpu, 0);
5137                 return 1;
5138         }
5139
5140         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5141         vmx->nested.vmcs02_num = 0;
5142
5143         vmx->nested.vmxon = true;
5144
5145         skip_emulated_instruction(vcpu);
5146         return 1;
5147 }
5148
5149 /*
5150  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5151  * for running VMX instructions (except VMXON, whose prerequisites are
5152  * slightly different). It also specifies what exception to inject otherwise.
5153  */
5154 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5155 {
5156         struct kvm_segment cs;
5157         struct vcpu_vmx *vmx = to_vmx(vcpu);
5158
5159         if (!vmx->nested.vmxon) {
5160                 kvm_queue_exception(vcpu, UD_VECTOR);
5161                 return 0;
5162         }
5163
5164         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5165         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5166             (is_long_mode(vcpu) && !cs.l)) {
5167                 kvm_queue_exception(vcpu, UD_VECTOR);
5168                 return 0;
5169         }
5170
5171         if (vmx_get_cpl(vcpu)) {
5172                 kvm_inject_gp(vcpu, 0);
5173                 return 0;
5174         }
5175
5176         return 1;
5177 }
5178
5179 /*
5180  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5181  * just stops using VMX.
5182  */
5183 static void free_nested(struct vcpu_vmx *vmx)
5184 {
5185         if (!vmx->nested.vmxon)
5186                 return;
5187         vmx->nested.vmxon = false;
5188         if (vmx->nested.current_vmptr != -1ull) {
5189                 kunmap(vmx->nested.current_vmcs12_page);
5190                 nested_release_page(vmx->nested.current_vmcs12_page);
5191                 vmx->nested.current_vmptr = -1ull;
5192                 vmx->nested.current_vmcs12 = NULL;
5193         }
5194         /* Unpin physical memory we referred to in current vmcs02 */
5195         if (vmx->nested.apic_access_page) {
5196                 nested_release_page(vmx->nested.apic_access_page);
5197                 vmx->nested.apic_access_page = 0;
5198         }
5199
5200         nested_free_all_saved_vmcss(vmx);
5201 }
5202
5203 /* Emulate the VMXOFF instruction */
5204 static int handle_vmoff(struct kvm_vcpu *vcpu)
5205 {
5206         if (!nested_vmx_check_permission(vcpu))
5207                 return 1;
5208         free_nested(to_vmx(vcpu));
5209         skip_emulated_instruction(vcpu);
5210         return 1;
5211 }
5212
5213 /*
5214  * Decode the memory-address operand of a vmx instruction, as recorded on an
5215  * exit caused by such an instruction (run by a guest hypervisor).
5216  * On success, returns 0. When the operand is invalid, returns 1 and throws
5217  * #UD or #GP.
5218  */
5219 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5220                                  unsigned long exit_qualification,
5221                                  u32 vmx_instruction_info, gva_t *ret)
5222 {
5223         /*
5224          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5225          * Execution", on an exit, vmx_instruction_info holds most of the
5226          * addressing components of the operand. Only the displacement part
5227          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5228          * For how an actual address is calculated from all these components,
5229          * refer to Vol. 1, "Operand Addressing".
5230          */
5231         int  scaling = vmx_instruction_info & 3;
5232         int  addr_size = (vmx_instruction_info >> 7) & 7;
5233         bool is_reg = vmx_instruction_info & (1u << 10);
5234         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5235         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5236         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5237         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5238         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5239
5240         if (is_reg) {
5241                 kvm_queue_exception(vcpu, UD_VECTOR);
5242                 return 1;
5243         }
5244
5245         /* Addr = segment_base + offset */
5246         /* offset = base + [index * scale] + displacement */
5247         *ret = vmx_get_segment_base(vcpu, seg_reg);
5248         if (base_is_valid)
5249                 *ret += kvm_register_read(vcpu, base_reg);
5250         if (index_is_valid)
5251                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5252         *ret += exit_qualification; /* holds the displacement */
5253
5254         if (addr_size == 1) /* 32 bit */
5255                 *ret &= 0xffffffff;
5256
5257         /*
5258          * TODO: throw #GP (and return 1) in various cases that the VM*
5259          * instructions require it - e.g., offset beyond segment limit,
5260          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5261          * address, and so on. Currently these are not checked.
5262          */
5263         return 0;
5264 }
5265
5266 /*
5267  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5268  * set the success or error code of an emulated VMX instruction, as specified
5269  * by Vol 2B, VMX Instruction Reference, "Conventions".
5270  */
5271 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5272 {
5273         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5274                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5275                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5276 }
5277
5278 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5279 {
5280         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5281                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5282                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5283                         | X86_EFLAGS_CF);
5284 }
5285
5286 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5287                                         u32 vm_instruction_error)
5288 {
5289         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5290                 /*
5291                  * failValid writes the error number to the current VMCS, which
5292                  * can't be done there isn't a current VMCS.
5293                  */
5294                 nested_vmx_failInvalid(vcpu);
5295                 return;
5296         }
5297         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5298                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5299                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5300                         | X86_EFLAGS_ZF);
5301         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5302 }
5303
5304 /* Emulate the VMCLEAR instruction */
5305 static int handle_vmclear(struct kvm_vcpu *vcpu)
5306 {
5307         struct vcpu_vmx *vmx = to_vmx(vcpu);
5308         gva_t gva;
5309         gpa_t vmptr;
5310         struct vmcs12 *vmcs12;
5311         struct page *page;
5312         struct x86_exception e;
5313
5314         if (!nested_vmx_check_permission(vcpu))
5315                 return 1;
5316
5317         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5318                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5319                 return 1;
5320
5321         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5322                                 sizeof(vmptr), &e)) {
5323                 kvm_inject_page_fault(vcpu, &e);
5324                 return 1;
5325         }
5326
5327         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5328                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5329                 skip_emulated_instruction(vcpu);
5330                 return 1;
5331         }
5332
5333         if (vmptr == vmx->nested.current_vmptr) {
5334                 kunmap(vmx->nested.current_vmcs12_page);
5335                 nested_release_page(vmx->nested.current_vmcs12_page);
5336                 vmx->nested.current_vmptr = -1ull;
5337                 vmx->nested.current_vmcs12 = NULL;
5338         }
5339
5340         page = nested_get_page(vcpu, vmptr);
5341         if (page == NULL) {
5342                 /*
5343                  * For accurate processor emulation, VMCLEAR beyond available
5344                  * physical memory should do nothing at all. However, it is
5345                  * possible that a nested vmx bug, not a guest hypervisor bug,
5346                  * resulted in this case, so let's shut down before doing any
5347                  * more damage:
5348                  */
5349                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5350                 return 1;
5351         }
5352         vmcs12 = kmap(page);
5353         vmcs12->launch_state = 0;
5354         kunmap(page);
5355         nested_release_page(page);
5356
5357         nested_free_vmcs02(vmx, vmptr);
5358
5359         skip_emulated_instruction(vcpu);
5360         nested_vmx_succeed(vcpu);
5361         return 1;
5362 }
5363
5364 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5365
5366 /* Emulate the VMLAUNCH instruction */
5367 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5368 {
5369         return nested_vmx_run(vcpu, true);
5370 }
5371
5372 /* Emulate the VMRESUME instruction */
5373 static int handle_vmresume(struct kvm_vcpu *vcpu)
5374 {
5375
5376         return nested_vmx_run(vcpu, false);
5377 }
5378
5379 enum vmcs_field_type {
5380         VMCS_FIELD_TYPE_U16 = 0,
5381         VMCS_FIELD_TYPE_U64 = 1,
5382         VMCS_FIELD_TYPE_U32 = 2,
5383         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5384 };
5385
5386 static inline int vmcs_field_type(unsigned long field)
5387 {
5388         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5389                 return VMCS_FIELD_TYPE_U32;
5390         return (field >> 13) & 0x3 ;
5391 }
5392
5393 static inline int vmcs_field_readonly(unsigned long field)
5394 {
5395         return (((field >> 10) & 0x3) == 1);
5396 }
5397
5398 /*
5399  * Read a vmcs12 field. Since these can have varying lengths and we return
5400  * one type, we chose the biggest type (u64) and zero-extend the return value
5401  * to that size. Note that the caller, handle_vmread, might need to use only
5402  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5403  * 64-bit fields are to be returned).
5404  */
5405 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5406                                         unsigned long field, u64 *ret)
5407 {
5408         short offset = vmcs_field_to_offset(field);
5409         char *p;
5410
5411         if (offset < 0)
5412                 return 0;
5413
5414         p = ((char *)(get_vmcs12(vcpu))) + offset;
5415
5416         switch (vmcs_field_type(field)) {
5417         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5418                 *ret = *((natural_width *)p);
5419                 return 1;
5420         case VMCS_FIELD_TYPE_U16:
5421                 *ret = *((u16 *)p);
5422                 return 1;
5423         case VMCS_FIELD_TYPE_U32:
5424                 *ret = *((u32 *)p);
5425                 return 1;
5426         case VMCS_FIELD_TYPE_U64:
5427                 *ret = *((u64 *)p);
5428                 return 1;
5429         default:
5430                 return 0; /* can never happen. */
5431         }
5432 }
5433
5434 /*
5435  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5436  * used before) all generate the same failure when it is missing.
5437  */
5438 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5439 {
5440         struct vcpu_vmx *vmx = to_vmx(vcpu);
5441         if (vmx->nested.current_vmptr == -1ull) {
5442                 nested_vmx_failInvalid(vcpu);
5443                 skip_emulated_instruction(vcpu);
5444                 return 0;
5445         }
5446         return 1;
5447 }
5448
5449 static int handle_vmread(struct kvm_vcpu *vcpu)
5450 {
5451         unsigned long field;
5452         u64 field_value;
5453         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5454         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5455         gva_t gva = 0;
5456
5457         if (!nested_vmx_check_permission(vcpu) ||
5458             !nested_vmx_check_vmcs12(vcpu))
5459                 return 1;
5460
5461         /* Decode instruction info and find the field to read */
5462         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5463         /* Read the field, zero-extended to a u64 field_value */
5464         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5465                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5466                 skip_emulated_instruction(vcpu);
5467                 return 1;
5468         }
5469         /*
5470          * Now copy part of this value to register or memory, as requested.
5471          * Note that the number of bits actually copied is 32 or 64 depending
5472          * on the guest's mode (32 or 64 bit), not on the given field's length.
5473          */
5474         if (vmx_instruction_info & (1u << 10)) {
5475                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5476                         field_value);
5477         } else {
5478                 if (get_vmx_mem_address(vcpu, exit_qualification,
5479                                 vmx_instruction_info, &gva))
5480                         return 1;
5481                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5482                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5483                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5484         }
5485
5486         nested_vmx_succeed(vcpu);
5487         skip_emulated_instruction(vcpu);
5488         return 1;
5489 }
5490
5491
5492 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5493 {
5494         unsigned long field;
5495         gva_t gva;
5496         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5497         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5498         char *p;
5499         short offset;
5500         /* The value to write might be 32 or 64 bits, depending on L1's long
5501          * mode, and eventually we need to write that into a field of several
5502          * possible lengths. The code below first zero-extends the value to 64
5503          * bit (field_value), and then copies only the approriate number of
5504          * bits into the vmcs12 field.
5505          */
5506         u64 field_value = 0;
5507         struct x86_exception e;
5508
5509         if (!nested_vmx_check_permission(vcpu) ||
5510             !nested_vmx_check_vmcs12(vcpu))
5511                 return 1;
5512
5513         if (vmx_instruction_info & (1u << 10))
5514                 field_value = kvm_register_read(vcpu,
5515                         (((vmx_instruction_info) >> 3) & 0xf));
5516         else {
5517                 if (get_vmx_mem_address(vcpu, exit_qualification,
5518                                 vmx_instruction_info, &gva))
5519                         return 1;
5520                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5521                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5522                         kvm_inject_page_fault(vcpu, &e);
5523                         return 1;
5524                 }
5525         }
5526
5527
5528         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5529         if (vmcs_field_readonly(field)) {
5530                 nested_vmx_failValid(vcpu,
5531                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5532                 skip_emulated_instruction(vcpu);
5533                 return 1;
5534         }
5535
5536         offset = vmcs_field_to_offset(field);
5537         if (offset < 0) {
5538                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5539                 skip_emulated_instruction(vcpu);
5540                 return 1;
5541         }
5542         p = ((char *) get_vmcs12(vcpu)) + offset;
5543
5544         switch (vmcs_field_type(field)) {
5545         case VMCS_FIELD_TYPE_U16:
5546                 *(u16 *)p = field_value;
5547                 break;
5548         case VMCS_FIELD_TYPE_U32:
5549                 *(u32 *)p = field_value;
5550                 break;
5551         case VMCS_FIELD_TYPE_U64:
5552                 *(u64 *)p = field_value;
5553                 break;
5554         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5555                 *(natural_width *)p = field_value;
5556                 break;
5557         default:
5558                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5559                 skip_emulated_instruction(vcpu);
5560                 return 1;
5561         }
5562
5563         nested_vmx_succeed(vcpu);
5564         skip_emulated_instruction(vcpu);
5565         return 1;
5566 }
5567
5568 /* Emulate the VMPTRLD instruction */
5569 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5570 {
5571         struct vcpu_vmx *vmx = to_vmx(vcpu);
5572         gva_t gva;
5573         gpa_t vmptr;
5574         struct x86_exception e;
5575
5576         if (!nested_vmx_check_permission(vcpu))
5577                 return 1;
5578
5579         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5580                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5581                 return 1;
5582
5583         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5584                                 sizeof(vmptr), &e)) {
5585                 kvm_inject_page_fault(vcpu, &e);
5586                 return 1;
5587         }
5588
5589         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5590                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5591                 skip_emulated_instruction(vcpu);
5592                 return 1;
5593         }
5594
5595         if (vmx->nested.current_vmptr != vmptr) {
5596                 struct vmcs12 *new_vmcs12;
5597                 struct page *page;
5598                 page = nested_get_page(vcpu, vmptr);
5599                 if (page == NULL) {
5600                         nested_vmx_failInvalid(vcpu);
5601                         skip_emulated_instruction(vcpu);
5602                         return 1;
5603                 }
5604                 new_vmcs12 = kmap(page);
5605                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5606                         kunmap(page);
5607                         nested_release_page_clean(page);
5608                         nested_vmx_failValid(vcpu,
5609                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5610                         skip_emulated_instruction(vcpu);
5611                         return 1;
5612                 }
5613                 if (vmx->nested.current_vmptr != -1ull) {
5614                         kunmap(vmx->nested.current_vmcs12_page);
5615                         nested_release_page(vmx->nested.current_vmcs12_page);
5616                 }
5617
5618                 vmx->nested.current_vmptr = vmptr;
5619                 vmx->nested.current_vmcs12 = new_vmcs12;
5620                 vmx->nested.current_vmcs12_page = page;
5621         }
5622
5623         nested_vmx_succeed(vcpu);
5624         skip_emulated_instruction(vcpu);
5625         return 1;
5626 }
5627
5628 /* Emulate the VMPTRST instruction */
5629 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5630 {
5631         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5632         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5633         gva_t vmcs_gva;
5634         struct x86_exception e;
5635
5636         if (!nested_vmx_check_permission(vcpu))
5637                 return 1;
5638
5639         if (get_vmx_mem_address(vcpu, exit_qualification,
5640                         vmx_instruction_info, &vmcs_gva))
5641                 return 1;
5642         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5643         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5644                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5645                                  sizeof(u64), &e)) {
5646                 kvm_inject_page_fault(vcpu, &e);
5647                 return 1;
5648         }
5649         nested_vmx_succeed(vcpu);
5650         skip_emulated_instruction(vcpu);
5651         return 1;
5652 }
5653
5654 /*
5655  * The exit handlers return 1 if the exit was handled fully and guest execution
5656  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5657  * to be done to userspace and return 0.
5658  */
5659 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5660         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5661         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5662         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5663         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5664         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5665         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5666         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5667         [EXIT_REASON_CPUID]                   = handle_cpuid,
5668         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5669         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5670         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5671         [EXIT_REASON_HLT]                     = handle_halt,
5672         [EXIT_REASON_INVD]                    = handle_invd,
5673         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5674         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5675         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5676         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5677         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5678         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5679         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5680         [EXIT_REASON_VMREAD]                  = handle_vmread,
5681         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5682         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5683         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5684         [EXIT_REASON_VMON]                    = handle_vmon,
5685         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5686         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5687         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5688         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5689         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5690         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5691         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5692         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5693         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5694         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5695         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5696 };
5697
5698 static const int kvm_vmx_max_exit_handlers =
5699         ARRAY_SIZE(kvm_vmx_exit_handlers);
5700
5701 /*
5702  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5703  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5704  * disinterest in the current event (read or write a specific MSR) by using an
5705  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5706  */
5707 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5708         struct vmcs12 *vmcs12, u32 exit_reason)
5709 {
5710         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5711         gpa_t bitmap;
5712
5713         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5714                 return 1;
5715
5716         /*
5717          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5718          * for the four combinations of read/write and low/high MSR numbers.
5719          * First we need to figure out which of the four to use:
5720          */
5721         bitmap = vmcs12->msr_bitmap;
5722         if (exit_reason == EXIT_REASON_MSR_WRITE)
5723                 bitmap += 2048;
5724         if (msr_index >= 0xc0000000) {
5725                 msr_index -= 0xc0000000;
5726                 bitmap += 1024;
5727         }
5728
5729         /* Then read the msr_index'th bit from this bitmap: */
5730         if (msr_index < 1024*8) {
5731                 unsigned char b;
5732                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5733                 return 1 & (b >> (msr_index & 7));
5734         } else
5735                 return 1; /* let L1 handle the wrong parameter */
5736 }
5737
5738 /*
5739  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5740  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5741  * intercept (via guest_host_mask etc.) the current event.
5742  */
5743 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5744         struct vmcs12 *vmcs12)
5745 {
5746         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5747         int cr = exit_qualification & 15;
5748         int reg = (exit_qualification >> 8) & 15;
5749         unsigned long val = kvm_register_read(vcpu, reg);
5750
5751         switch ((exit_qualification >> 4) & 3) {
5752         case 0: /* mov to cr */
5753                 switch (cr) {
5754                 case 0:
5755                         if (vmcs12->cr0_guest_host_mask &
5756                             (val ^ vmcs12->cr0_read_shadow))
5757                                 return 1;
5758                         break;
5759                 case 3:
5760                         if ((vmcs12->cr3_target_count >= 1 &&
5761                                         vmcs12->cr3_target_value0 == val) ||
5762                                 (vmcs12->cr3_target_count >= 2 &&
5763                                         vmcs12->cr3_target_value1 == val) ||
5764                                 (vmcs12->cr3_target_count >= 3 &&
5765                                         vmcs12->cr3_target_value2 == val) ||
5766                                 (vmcs12->cr3_target_count >= 4 &&
5767                                         vmcs12->cr3_target_value3 == val))
5768                                 return 0;
5769                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5770                                 return 1;
5771                         break;
5772                 case 4:
5773                         if (vmcs12->cr4_guest_host_mask &
5774                             (vmcs12->cr4_read_shadow ^ val))
5775                                 return 1;
5776                         break;
5777                 case 8:
5778                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5779                                 return 1;
5780                         break;
5781                 }
5782                 break;
5783         case 2: /* clts */
5784                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5785                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5786                         return 1;
5787                 break;
5788         case 1: /* mov from cr */
5789                 switch (cr) {
5790                 case 3:
5791                         if (vmcs12->cpu_based_vm_exec_control &
5792                             CPU_BASED_CR3_STORE_EXITING)
5793                                 return 1;
5794                         break;
5795                 case 8:
5796                         if (vmcs12->cpu_based_vm_exec_control &
5797                             CPU_BASED_CR8_STORE_EXITING)
5798                                 return 1;
5799                         break;
5800                 }
5801                 break;
5802         case 3: /* lmsw */
5803                 /*
5804                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5805                  * cr0. Other attempted changes are ignored, with no exit.
5806                  */
5807                 if (vmcs12->cr0_guest_host_mask & 0xe &
5808                     (val ^ vmcs12->cr0_read_shadow))
5809                         return 1;
5810                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5811                     !(vmcs12->cr0_read_shadow & 0x1) &&
5812                     (val & 0x1))
5813                         return 1;
5814                 break;
5815         }
5816         return 0;
5817 }
5818
5819 /*
5820  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5821  * should handle it ourselves in L0 (and then continue L2). Only call this
5822  * when in is_guest_mode (L2).
5823  */
5824 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5825 {
5826         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5827         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5828         struct vcpu_vmx *vmx = to_vmx(vcpu);
5829         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5830
5831         if (vmx->nested.nested_run_pending)
5832                 return 0;
5833
5834         if (unlikely(vmx->fail)) {
5835                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5836                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5837                 return 1;
5838         }
5839
5840         switch (exit_reason) {
5841         case EXIT_REASON_EXCEPTION_NMI:
5842                 if (!is_exception(intr_info))
5843                         return 0;
5844                 else if (is_page_fault(intr_info))
5845                         return enable_ept;
5846                 return vmcs12->exception_bitmap &
5847                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5848         case EXIT_REASON_EXTERNAL_INTERRUPT:
5849                 return 0;
5850         case EXIT_REASON_TRIPLE_FAULT:
5851                 return 1;
5852         case EXIT_REASON_PENDING_INTERRUPT:
5853         case EXIT_REASON_NMI_WINDOW:
5854                 /*
5855                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5856                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5857                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5858                  * Same for NMI Window Exiting.
5859                  */
5860                 return 1;
5861         case EXIT_REASON_TASK_SWITCH:
5862                 return 1;
5863         case EXIT_REASON_CPUID:
5864                 return 1;
5865         case EXIT_REASON_HLT:
5866                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5867         case EXIT_REASON_INVD:
5868                 return 1;
5869         case EXIT_REASON_INVLPG:
5870                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5871         case EXIT_REASON_RDPMC:
5872                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5873         case EXIT_REASON_RDTSC:
5874                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5875         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5876         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5877         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5878         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5879         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5880                 /*
5881                  * VMX instructions trap unconditionally. This allows L1 to
5882                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5883                  */
5884                 return 1;
5885         case EXIT_REASON_CR_ACCESS:
5886                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5887         case EXIT_REASON_DR_ACCESS:
5888                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5889         case EXIT_REASON_IO_INSTRUCTION:
5890                 /* TODO: support IO bitmaps */
5891                 return 1;
5892         case EXIT_REASON_MSR_READ:
5893         case EXIT_REASON_MSR_WRITE:
5894                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5895         case EXIT_REASON_INVALID_STATE:
5896                 return 1;
5897         case EXIT_REASON_MWAIT_INSTRUCTION:
5898                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5899         case EXIT_REASON_MONITOR_INSTRUCTION:
5900                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5901         case EXIT_REASON_PAUSE_INSTRUCTION:
5902                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5903                         nested_cpu_has2(vmcs12,
5904                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5905         case EXIT_REASON_MCE_DURING_VMENTRY:
5906                 return 0;
5907         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5908                 return 1;
5909         case EXIT_REASON_APIC_ACCESS:
5910                 return nested_cpu_has2(vmcs12,
5911                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5912         case EXIT_REASON_EPT_VIOLATION:
5913         case EXIT_REASON_EPT_MISCONFIG:
5914                 return 0;
5915         case EXIT_REASON_WBINVD:
5916                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5917         case EXIT_REASON_XSETBV:
5918                 return 1;
5919         default:
5920                 return 1;
5921         }
5922 }
5923
5924 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5925 {
5926         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5927         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5928 }
5929
5930 /*
5931  * The guest has exited.  See if we can fix it or if we need userspace
5932  * assistance.
5933  */
5934 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5935 {
5936         struct vcpu_vmx *vmx = to_vmx(vcpu);
5937         u32 exit_reason = vmx->exit_reason;
5938         u32 vectoring_info = vmx->idt_vectoring_info;
5939
5940         /* If guest state is invalid, start emulating */
5941         if (vmx->emulation_required && emulate_invalid_guest_state)
5942                 return handle_invalid_guest_state(vcpu);
5943
5944         /*
5945          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5946          * we did not inject a still-pending event to L1 now because of
5947          * nested_run_pending, we need to re-enable this bit.
5948          */
5949         if (vmx->nested.nested_run_pending)
5950                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5951
5952         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5953             exit_reason == EXIT_REASON_VMRESUME))
5954                 vmx->nested.nested_run_pending = 1;
5955         else
5956                 vmx->nested.nested_run_pending = 0;
5957
5958         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5959                 nested_vmx_vmexit(vcpu);
5960                 return 1;
5961         }
5962
5963         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5964                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5965                 vcpu->run->fail_entry.hardware_entry_failure_reason
5966                         = exit_reason;
5967                 return 0;
5968         }
5969
5970         if (unlikely(vmx->fail)) {
5971                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5972                 vcpu->run->fail_entry.hardware_entry_failure_reason
5973                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5974                 return 0;
5975         }
5976
5977         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5978                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5979                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5980                         exit_reason != EXIT_REASON_TASK_SWITCH))
5981                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5982                        "(0x%x) and exit reason is 0x%x\n",
5983                        __func__, vectoring_info, exit_reason);
5984
5985         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5986             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5987                                         get_vmcs12(vcpu), vcpu)))) {
5988                 if (vmx_interrupt_allowed(vcpu)) {
5989                         vmx->soft_vnmi_blocked = 0;
5990                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5991                            vcpu->arch.nmi_pending) {
5992                         /*
5993                          * This CPU don't support us in finding the end of an
5994                          * NMI-blocked window if the guest runs with IRQs
5995                          * disabled. So we pull the trigger after 1 s of
5996                          * futile waiting, but inform the user about this.
5997                          */
5998                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5999                                "state on VCPU %d after 1 s timeout\n",
6000                                __func__, vcpu->vcpu_id);
6001                         vmx->soft_vnmi_blocked = 0;
6002                 }
6003         }
6004
6005         if (exit_reason < kvm_vmx_max_exit_handlers
6006             && kvm_vmx_exit_handlers[exit_reason])
6007                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6008         else {
6009                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6010                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6011         }
6012         return 0;
6013 }
6014
6015 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6016 {
6017         if (irr == -1 || tpr < irr) {
6018                 vmcs_write32(TPR_THRESHOLD, 0);
6019                 return;
6020         }
6021
6022         vmcs_write32(TPR_THRESHOLD, irr);
6023 }
6024
6025 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6026 {
6027         u32 exit_intr_info;
6028
6029         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6030               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6031                 return;
6032
6033         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6034         exit_intr_info = vmx->exit_intr_info;
6035
6036         /* Handle machine checks before interrupts are enabled */
6037         if (is_machine_check(exit_intr_info))
6038                 kvm_machine_check();
6039
6040         /* We need to handle NMIs before interrupts are enabled */
6041         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6042             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6043                 kvm_before_handle_nmi(&vmx->vcpu);
6044                 asm("int $2");
6045                 kvm_after_handle_nmi(&vmx->vcpu);
6046         }
6047 }
6048
6049 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6050 {
6051         u32 exit_intr_info;
6052         bool unblock_nmi;
6053         u8 vector;
6054         bool idtv_info_valid;
6055
6056         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6057
6058         if (cpu_has_virtual_nmis()) {
6059                 if (vmx->nmi_known_unmasked)
6060                         return;
6061                 /*
6062                  * Can't use vmx->exit_intr_info since we're not sure what
6063                  * the exit reason is.
6064                  */
6065                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6066                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6067                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6068                 /*
6069                  * SDM 3: 27.7.1.2 (September 2008)
6070                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6071                  * a guest IRET fault.
6072                  * SDM 3: 23.2.2 (September 2008)
6073                  * Bit 12 is undefined in any of the following cases:
6074                  *  If the VM exit sets the valid bit in the IDT-vectoring
6075                  *   information field.
6076                  *  If the VM exit is due to a double fault.
6077                  */
6078                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6079                     vector != DF_VECTOR && !idtv_info_valid)
6080                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6081                                       GUEST_INTR_STATE_NMI);
6082                 else
6083                         vmx->nmi_known_unmasked =
6084                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6085                                   & GUEST_INTR_STATE_NMI);
6086         } else if (unlikely(vmx->soft_vnmi_blocked))
6087                 vmx->vnmi_blocked_time +=
6088                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6089 }
6090
6091 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6092                                       u32 idt_vectoring_info,
6093                                       int instr_len_field,
6094                                       int error_code_field)
6095 {
6096         u8 vector;
6097         int type;
6098         bool idtv_info_valid;
6099
6100         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6101
6102         vmx->vcpu.arch.nmi_injected = false;
6103         kvm_clear_exception_queue(&vmx->vcpu);
6104         kvm_clear_interrupt_queue(&vmx->vcpu);
6105
6106         if (!idtv_info_valid)
6107                 return;
6108
6109         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6110
6111         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6112         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6113
6114         switch (type) {
6115         case INTR_TYPE_NMI_INTR:
6116                 vmx->vcpu.arch.nmi_injected = true;
6117                 /*
6118                  * SDM 3: 27.7.1.2 (September 2008)
6119                  * Clear bit "block by NMI" before VM entry if a NMI
6120                  * delivery faulted.
6121                  */
6122                 vmx_set_nmi_mask(&vmx->vcpu, false);
6123                 break;
6124         case INTR_TYPE_SOFT_EXCEPTION:
6125                 vmx->vcpu.arch.event_exit_inst_len =
6126                         vmcs_read32(instr_len_field);
6127                 /* fall through */
6128         case INTR_TYPE_HARD_EXCEPTION:
6129                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6130                         u32 err = vmcs_read32(error_code_field);
6131                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6132                 } else
6133                         kvm_queue_exception(&vmx->vcpu, vector);
6134                 break;
6135         case INTR_TYPE_SOFT_INTR:
6136                 vmx->vcpu.arch.event_exit_inst_len =
6137                         vmcs_read32(instr_len_field);
6138                 /* fall through */
6139         case INTR_TYPE_EXT_INTR:
6140                 kvm_queue_interrupt(&vmx->vcpu, vector,
6141                         type == INTR_TYPE_SOFT_INTR);
6142                 break;
6143         default:
6144                 break;
6145         }
6146 }
6147
6148 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6149 {
6150         if (is_guest_mode(&vmx->vcpu))
6151                 return;
6152         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6153                                   VM_EXIT_INSTRUCTION_LEN,
6154                                   IDT_VECTORING_ERROR_CODE);
6155 }
6156
6157 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6158 {
6159         if (is_guest_mode(vcpu))
6160                 return;
6161         __vmx_complete_interrupts(to_vmx(vcpu),
6162                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6163                                   VM_ENTRY_INSTRUCTION_LEN,
6164                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6165
6166         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6167 }
6168
6169 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6170 {
6171         int i, nr_msrs;
6172         struct perf_guest_switch_msr *msrs;
6173
6174         msrs = perf_guest_get_msrs(&nr_msrs);
6175
6176         if (!msrs)
6177                 return;
6178
6179         for (i = 0; i < nr_msrs; i++)
6180                 if (msrs[i].host == msrs[i].guest)
6181                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6182                 else
6183                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6184                                         msrs[i].host);
6185 }
6186
6187 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6188 {
6189         struct vcpu_vmx *vmx = to_vmx(vcpu);
6190         unsigned long debugctlmsr;
6191
6192         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6193                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6194                 if (vmcs12->idt_vectoring_info_field &
6195                                 VECTORING_INFO_VALID_MASK) {
6196                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6197                                 vmcs12->idt_vectoring_info_field);
6198                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6199                                 vmcs12->vm_exit_instruction_len);
6200                         if (vmcs12->idt_vectoring_info_field &
6201                                         VECTORING_INFO_DELIVER_CODE_MASK)
6202                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6203                                         vmcs12->idt_vectoring_error_code);
6204                 }
6205         }
6206
6207         /* Record the guest's net vcpu time for enforced NMI injections. */
6208         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6209                 vmx->entry_time = ktime_get();
6210
6211         /* Don't enter VMX if guest state is invalid, let the exit handler
6212            start emulation until we arrive back to a valid state */
6213         if (vmx->emulation_required && emulate_invalid_guest_state)
6214                 return;
6215
6216         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6217                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6218         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6219                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6220
6221         /* When single-stepping over STI and MOV SS, we must clear the
6222          * corresponding interruptibility bits in the guest state. Otherwise
6223          * vmentry fails as it then expects bit 14 (BS) in pending debug
6224          * exceptions being set, but that's not correct for the guest debugging
6225          * case. */
6226         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6227                 vmx_set_interrupt_shadow(vcpu, 0);
6228
6229         atomic_switch_perf_msrs(vmx);
6230         debugctlmsr = get_debugctlmsr();
6231
6232         vmx->__launched = vmx->loaded_vmcs->launched;
6233         asm(
6234                 /* Store host registers */
6235                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6236                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6237                 "push %%" _ASM_CX " \n\t"
6238                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6239                 "je 1f \n\t"
6240                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6241                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6242                 "1: \n\t"
6243                 /* Reload cr2 if changed */
6244                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6245                 "mov %%cr2, %%" _ASM_DX " \n\t"
6246                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
6247                 "je 2f \n\t"
6248                 "mov %%" _ASM_AX", %%cr2 \n\t"
6249                 "2: \n\t"
6250                 /* Check if vmlaunch of vmresume is needed */
6251                 "cmpl $0, %c[launched](%0) \n\t"
6252                 /* Load guest registers.  Don't clobber flags. */
6253                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6254                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6255                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6256                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6257                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6258                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
6259 #ifdef CONFIG_X86_64
6260                 "mov %c[r8](%0),  %%r8  \n\t"
6261                 "mov %c[r9](%0),  %%r9  \n\t"
6262                 "mov %c[r10](%0), %%r10 \n\t"
6263                 "mov %c[r11](%0), %%r11 \n\t"
6264                 "mov %c[r12](%0), %%r12 \n\t"
6265                 "mov %c[r13](%0), %%r13 \n\t"
6266                 "mov %c[r14](%0), %%r14 \n\t"
6267                 "mov %c[r15](%0), %%r15 \n\t"
6268 #endif
6269                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
6270
6271                 /* Enter guest mode */
6272                 "jne 1f \n\t"
6273                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6274                 "jmp 2f \n\t"
6275                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6276                 "2: "
6277                 /* Save guest registers, load host registers, keep flags */
6278                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
6279                 "pop %0 \n\t"
6280                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6281                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6282                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6283                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6284                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6285                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6286                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
6287 #ifdef CONFIG_X86_64
6288                 "mov %%r8,  %c[r8](%0) \n\t"
6289                 "mov %%r9,  %c[r9](%0) \n\t"
6290                 "mov %%r10, %c[r10](%0) \n\t"
6291                 "mov %%r11, %c[r11](%0) \n\t"
6292                 "mov %%r12, %c[r12](%0) \n\t"
6293                 "mov %%r13, %c[r13](%0) \n\t"
6294                 "mov %%r14, %c[r14](%0) \n\t"
6295                 "mov %%r15, %c[r15](%0) \n\t"
6296 #endif
6297                 "mov %%cr2, %%" _ASM_AX "   \n\t"
6298                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
6299
6300                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
6301                 "setbe %c[fail](%0) \n\t"
6302                 ".pushsection .rodata \n\t"
6303                 ".global vmx_return \n\t"
6304                 "vmx_return: " _ASM_PTR " 2b \n\t"
6305                 ".popsection"
6306               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6307                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6308                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6309                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6310                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6311                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6312                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6313                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6314                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6315                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6316                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6317 #ifdef CONFIG_X86_64
6318                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6319                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6320                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6321                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6322                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6323                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6324                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6325                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6326 #endif
6327                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6328                 [wordsize]"i"(sizeof(ulong))
6329               : "cc", "memory"
6330 #ifdef CONFIG_X86_64
6331                 , "rax", "rbx", "rdi", "rsi"
6332                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6333 #else
6334                 , "eax", "ebx", "edi", "esi"
6335 #endif
6336               );
6337
6338         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6339         if (debugctlmsr)
6340                 update_debugctlmsr(debugctlmsr);
6341
6342 #ifndef CONFIG_X86_64
6343         /*
6344          * The sysexit path does not restore ds/es, so we must set them to
6345          * a reasonable value ourselves.
6346          *
6347          * We can't defer this to vmx_load_host_state() since that function
6348          * may be executed in interrupt context, which saves and restore segments
6349          * around it, nullifying its effect.
6350          */
6351         loadsegment(ds, __USER_DS);
6352         loadsegment(es, __USER_DS);
6353 #endif
6354
6355         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6356                                   | (1 << VCPU_EXREG_RFLAGS)
6357                                   | (1 << VCPU_EXREG_CPL)
6358                                   | (1 << VCPU_EXREG_PDPTR)
6359                                   | (1 << VCPU_EXREG_SEGMENTS)
6360                                   | (1 << VCPU_EXREG_CR3));
6361         vcpu->arch.regs_dirty = 0;
6362
6363         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6364
6365         if (is_guest_mode(vcpu)) {
6366                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6367                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6368                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6369                         vmcs12->idt_vectoring_error_code =
6370                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6371                         vmcs12->vm_exit_instruction_len =
6372                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6373                 }
6374         }
6375
6376         vmx->loaded_vmcs->launched = 1;
6377
6378         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6379         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6380
6381         vmx_complete_atomic_exit(vmx);
6382         vmx_recover_nmi_blocking(vmx);
6383         vmx_complete_interrupts(vmx);
6384 }
6385
6386 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6387 {
6388         struct vcpu_vmx *vmx = to_vmx(vcpu);
6389
6390         free_vpid(vmx);
6391         free_nested(vmx);
6392         free_loaded_vmcs(vmx->loaded_vmcs);
6393         kfree(vmx->guest_msrs);
6394         kvm_vcpu_uninit(vcpu);
6395         kmem_cache_free(kvm_vcpu_cache, vmx);
6396 }
6397
6398 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6399 {
6400         int err;
6401         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6402         int cpu;
6403
6404         if (!vmx)
6405                 return ERR_PTR(-ENOMEM);
6406
6407         allocate_vpid(vmx);
6408
6409         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6410         if (err)
6411                 goto free_vcpu;
6412
6413         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6414         err = -ENOMEM;
6415         if (!vmx->guest_msrs) {
6416                 goto uninit_vcpu;
6417         }
6418
6419         vmx->loaded_vmcs = &vmx->vmcs01;
6420         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6421         if (!vmx->loaded_vmcs->vmcs)
6422                 goto free_msrs;
6423         if (!vmm_exclusive)
6424                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6425         loaded_vmcs_init(vmx->loaded_vmcs);
6426         if (!vmm_exclusive)
6427                 kvm_cpu_vmxoff();
6428
6429         cpu = get_cpu();
6430         vmx_vcpu_load(&vmx->vcpu, cpu);
6431         vmx->vcpu.cpu = cpu;
6432         err = vmx_vcpu_setup(vmx);
6433         vmx_vcpu_put(&vmx->vcpu);
6434         put_cpu();
6435         if (err)
6436                 goto free_vmcs;
6437         if (vm_need_virtualize_apic_accesses(kvm))
6438                 err = alloc_apic_access_page(kvm);
6439                 if (err)
6440                         goto free_vmcs;
6441
6442         if (enable_ept) {
6443                 if (!kvm->arch.ept_identity_map_addr)
6444                         kvm->arch.ept_identity_map_addr =
6445                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6446                 err = -ENOMEM;
6447                 if (alloc_identity_pagetable(kvm) != 0)
6448                         goto free_vmcs;
6449                 if (!init_rmode_identity_map(kvm))
6450                         goto free_vmcs;
6451         }
6452
6453         vmx->nested.current_vmptr = -1ull;
6454         vmx->nested.current_vmcs12 = NULL;
6455
6456         return &vmx->vcpu;
6457
6458 free_vmcs:
6459         free_loaded_vmcs(vmx->loaded_vmcs);
6460 free_msrs:
6461         kfree(vmx->guest_msrs);
6462 uninit_vcpu:
6463         kvm_vcpu_uninit(&vmx->vcpu);
6464 free_vcpu:
6465         free_vpid(vmx);
6466         kmem_cache_free(kvm_vcpu_cache, vmx);
6467         return ERR_PTR(err);
6468 }
6469
6470 static void __init vmx_check_processor_compat(void *rtn)
6471 {
6472         struct vmcs_config vmcs_conf;
6473
6474         *(int *)rtn = 0;
6475         if (setup_vmcs_config(&vmcs_conf) < 0)
6476                 *(int *)rtn = -EIO;
6477         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6478                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6479                                 smp_processor_id());
6480                 *(int *)rtn = -EIO;
6481         }
6482 }
6483
6484 static int get_ept_level(void)
6485 {
6486         return VMX_EPT_DEFAULT_GAW + 1;
6487 }
6488
6489 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6490 {
6491         u64 ret;
6492
6493         /* For VT-d and EPT combination
6494          * 1. MMIO: always map as UC
6495          * 2. EPT with VT-d:
6496          *   a. VT-d without snooping control feature: can't guarantee the
6497          *      result, try to trust guest.
6498          *   b. VT-d with snooping control feature: snooping control feature of
6499          *      VT-d engine can guarantee the cache correctness. Just set it
6500          *      to WB to keep consistent with host. So the same as item 3.
6501          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6502          *    consistent with host MTRR
6503          */
6504         if (is_mmio)
6505                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6506         else if (vcpu->kvm->arch.iommu_domain &&
6507                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6508                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6509                       VMX_EPT_MT_EPTE_SHIFT;
6510         else
6511                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6512                         | VMX_EPT_IPAT_BIT;
6513
6514         return ret;
6515 }
6516
6517 static int vmx_get_lpage_level(void)
6518 {
6519         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6520                 return PT_DIRECTORY_LEVEL;
6521         else
6522                 /* For shadow and EPT supported 1GB page */
6523                 return PT_PDPE_LEVEL;
6524 }
6525
6526 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6527 {
6528         struct kvm_cpuid_entry2 *best;
6529         struct vcpu_vmx *vmx = to_vmx(vcpu);
6530         u32 exec_control;
6531
6532         vmx->rdtscp_enabled = false;
6533         if (vmx_rdtscp_supported()) {
6534                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6535                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6536                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6537                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6538                                 vmx->rdtscp_enabled = true;
6539                         else {
6540                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6541                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6542                                                 exec_control);
6543                         }
6544                 }
6545         }
6546
6547         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6548         /* Exposing INVPCID only when PCID is exposed */
6549         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6550         if (vmx_invpcid_supported() &&
6551             best && (best->ecx & bit(X86_FEATURE_INVPCID)) &&
6552             guest_cpuid_has_pcid(vcpu)) {
6553                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6554                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6555                              exec_control);
6556         } else {
6557                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6558                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6559                              exec_control);
6560                 if (best)
6561                         best->ecx &= ~bit(X86_FEATURE_INVPCID);
6562         }
6563 }
6564
6565 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6566 {
6567         if (func == 1 && nested)
6568                 entry->ecx |= bit(X86_FEATURE_VMX);
6569 }
6570
6571 /*
6572  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6573  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6574  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6575  * guest in a way that will both be appropriate to L1's requests, and our
6576  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6577  * function also has additional necessary side-effects, like setting various
6578  * vcpu->arch fields.
6579  */
6580 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6581 {
6582         struct vcpu_vmx *vmx = to_vmx(vcpu);
6583         u32 exec_control;
6584
6585         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6586         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6587         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6588         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6589         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6590         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6591         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6592         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6593         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6594         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6595         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6596         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6597         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6598         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6599         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6600         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6601         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6602         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6603         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6604         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6605         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6606         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6607         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6608         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6609         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6610         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6611         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6612         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6613         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6614         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6615         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6616         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6617         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6618         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6619         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6620         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6621
6622         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6623         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6624                 vmcs12->vm_entry_intr_info_field);
6625         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6626                 vmcs12->vm_entry_exception_error_code);
6627         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6628                 vmcs12->vm_entry_instruction_len);
6629         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6630                 vmcs12->guest_interruptibility_info);
6631         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6632         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6633         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6634         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6635         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6636                 vmcs12->guest_pending_dbg_exceptions);
6637         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6638         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6639
6640         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6641
6642         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6643                 (vmcs_config.pin_based_exec_ctrl |
6644                  vmcs12->pin_based_vm_exec_control));
6645
6646         /*
6647          * Whether page-faults are trapped is determined by a combination of
6648          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6649          * If enable_ept, L0 doesn't care about page faults and we should
6650          * set all of these to L1's desires. However, if !enable_ept, L0 does
6651          * care about (at least some) page faults, and because it is not easy
6652          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6653          * to exit on each and every L2 page fault. This is done by setting
6654          * MASK=MATCH=0 and (see below) EB.PF=1.
6655          * Note that below we don't need special code to set EB.PF beyond the
6656          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6657          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6658          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6659          *
6660          * A problem with this approach (when !enable_ept) is that L1 may be
6661          * injected with more page faults than it asked for. This could have
6662          * caused problems, but in practice existing hypervisors don't care.
6663          * To fix this, we will need to emulate the PFEC checking (on the L1
6664          * page tables), using walk_addr(), when injecting PFs to L1.
6665          */
6666         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6667                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6668         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6669                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6670
6671         if (cpu_has_secondary_exec_ctrls()) {
6672                 u32 exec_control = vmx_secondary_exec_control(vmx);
6673                 if (!vmx->rdtscp_enabled)
6674                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6675                 /* Take the following fields only from vmcs12 */
6676                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6677                 if (nested_cpu_has(vmcs12,
6678                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6679                         exec_control |= vmcs12->secondary_vm_exec_control;
6680
6681                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6682                         /*
6683                          * Translate L1 physical address to host physical
6684                          * address for vmcs02. Keep the page pinned, so this
6685                          * physical address remains valid. We keep a reference
6686                          * to it so we can release it later.
6687                          */
6688                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6689                                 nested_release_page(vmx->nested.apic_access_page);
6690                         vmx->nested.apic_access_page =
6691                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6692                         /*
6693                          * If translation failed, no matter: This feature asks
6694                          * to exit when accessing the given address, and if it
6695                          * can never be accessed, this feature won't do
6696                          * anything anyway.
6697                          */
6698                         if (!vmx->nested.apic_access_page)
6699                                 exec_control &=
6700                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6701                         else
6702                                 vmcs_write64(APIC_ACCESS_ADDR,
6703                                   page_to_phys(vmx->nested.apic_access_page));
6704                 }
6705
6706                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6707         }
6708
6709
6710         /*
6711          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6712          * Some constant fields are set here by vmx_set_constant_host_state().
6713          * Other fields are different per CPU, and will be set later when
6714          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6715          */
6716         vmx_set_constant_host_state();
6717
6718         /*
6719          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6720          * entry, but only if the current (host) sp changed from the value
6721          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6722          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6723          * here we just force the write to happen on entry.
6724          */
6725         vmx->host_rsp = 0;
6726
6727         exec_control = vmx_exec_control(vmx); /* L0's desires */
6728         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6729         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6730         exec_control &= ~CPU_BASED_TPR_SHADOW;
6731         exec_control |= vmcs12->cpu_based_vm_exec_control;
6732         /*
6733          * Merging of IO and MSR bitmaps not currently supported.
6734          * Rather, exit every time.
6735          */
6736         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6737         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6738         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6739
6740         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6741
6742         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6743          * bitwise-or of what L1 wants to trap for L2, and what we want to
6744          * trap. Note that CR0.TS also needs updating - we do this later.
6745          */
6746         update_exception_bitmap(vcpu);
6747         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6748         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6749
6750         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6751         vmcs_write32(VM_EXIT_CONTROLS,
6752                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6753         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6754                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6755
6756         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6757                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6758         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6759                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6760
6761
6762         set_cr4_guest_host_mask(vmx);
6763
6764         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6765                 vmcs_write64(TSC_OFFSET,
6766                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6767         else
6768                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6769
6770         if (enable_vpid) {
6771                 /*
6772                  * Trivially support vpid by letting L2s share their parent
6773                  * L1's vpid. TODO: move to a more elaborate solution, giving
6774                  * each L2 its own vpid and exposing the vpid feature to L1.
6775                  */
6776                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6777                 vmx_flush_tlb(vcpu);
6778         }
6779
6780         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6781                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6782         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6783                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6784         else
6785                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6786         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6787         vmx_set_efer(vcpu, vcpu->arch.efer);
6788
6789         /*
6790          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6791          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6792          * The CR0_READ_SHADOW is what L2 should have expected to read given
6793          * the specifications by L1; It's not enough to take
6794          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6795          * have more bits than L1 expected.
6796          */
6797         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6798         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6799
6800         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6801         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6802
6803         /* shadow page tables on either EPT or shadow page tables */
6804         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6805         kvm_mmu_reset_context(vcpu);
6806
6807         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6808         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6809 }
6810
6811 /*
6812  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6813  * for running an L2 nested guest.
6814  */
6815 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6816 {
6817         struct vmcs12 *vmcs12;
6818         struct vcpu_vmx *vmx = to_vmx(vcpu);
6819         int cpu;
6820         struct loaded_vmcs *vmcs02;
6821
6822         if (!nested_vmx_check_permission(vcpu) ||
6823             !nested_vmx_check_vmcs12(vcpu))
6824                 return 1;
6825
6826         skip_emulated_instruction(vcpu);
6827         vmcs12 = get_vmcs12(vcpu);
6828
6829         /*
6830          * The nested entry process starts with enforcing various prerequisites
6831          * on vmcs12 as required by the Intel SDM, and act appropriately when
6832          * they fail: As the SDM explains, some conditions should cause the
6833          * instruction to fail, while others will cause the instruction to seem
6834          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6835          * To speed up the normal (success) code path, we should avoid checking
6836          * for misconfigurations which will anyway be caught by the processor
6837          * when using the merged vmcs02.
6838          */
6839         if (vmcs12->launch_state == launch) {
6840                 nested_vmx_failValid(vcpu,
6841                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6842                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6843                 return 1;
6844         }
6845
6846         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6847                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6848                 /*TODO: Also verify bits beyond physical address width are 0*/
6849                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6850                 return 1;
6851         }
6852
6853         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6854                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6855                 /*TODO: Also verify bits beyond physical address width are 0*/
6856                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6857                 return 1;
6858         }
6859
6860         if (vmcs12->vm_entry_msr_load_count > 0 ||
6861             vmcs12->vm_exit_msr_load_count > 0 ||
6862             vmcs12->vm_exit_msr_store_count > 0) {
6863                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6864                                     __func__);
6865                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6866                 return 1;
6867         }
6868
6869         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6870               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6871             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6872               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6873             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6874               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6875             !vmx_control_verify(vmcs12->vm_exit_controls,
6876               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6877             !vmx_control_verify(vmcs12->vm_entry_controls,
6878               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6879         {
6880                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6881                 return 1;
6882         }
6883
6884         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6885             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6886                 nested_vmx_failValid(vcpu,
6887                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6888                 return 1;
6889         }
6890
6891         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6892             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6893                 nested_vmx_entry_failure(vcpu, vmcs12,
6894                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6895                 return 1;
6896         }
6897         if (vmcs12->vmcs_link_pointer != -1ull) {
6898                 nested_vmx_entry_failure(vcpu, vmcs12,
6899                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6900                 return 1;
6901         }
6902
6903         /*
6904          * We're finally done with prerequisite checking, and can start with
6905          * the nested entry.
6906          */
6907
6908         vmcs02 = nested_get_current_vmcs02(vmx);
6909         if (!vmcs02)
6910                 return -ENOMEM;
6911
6912         enter_guest_mode(vcpu);
6913
6914         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6915
6916         cpu = get_cpu();
6917         vmx->loaded_vmcs = vmcs02;
6918         vmx_vcpu_put(vcpu);
6919         vmx_vcpu_load(vcpu, cpu);
6920         vcpu->cpu = cpu;
6921         put_cpu();
6922
6923         vmcs12->launch_state = 1;
6924
6925         prepare_vmcs02(vcpu, vmcs12);
6926
6927         /*
6928          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6929          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6930          * returned as far as L1 is concerned. It will only return (and set
6931          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6932          */
6933         return 1;
6934 }
6935
6936 /*
6937  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6938  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6939  * This function returns the new value we should put in vmcs12.guest_cr0.
6940  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6941  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6942  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6943  *     didn't trap the bit, because if L1 did, so would L0).
6944  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6945  *     been modified by L2, and L1 knows it. So just leave the old value of
6946  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6947  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6948  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6949  *     changed these bits, and therefore they need to be updated, but L0
6950  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6951  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6952  */
6953 static inline unsigned long
6954 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6955 {
6956         return
6957         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6958         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6959         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6960                         vcpu->arch.cr0_guest_owned_bits));
6961 }
6962
6963 static inline unsigned long
6964 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6965 {
6966         return
6967         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6968         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6969         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6970                         vcpu->arch.cr4_guest_owned_bits));
6971 }
6972
6973 /*
6974  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6975  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6976  * and this function updates it to reflect the changes to the guest state while
6977  * L2 was running (and perhaps made some exits which were handled directly by L0
6978  * without going back to L1), and to reflect the exit reason.
6979  * Note that we do not have to copy here all VMCS fields, just those that
6980  * could have changed by the L2 guest or the exit - i.e., the guest-state and
6981  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6982  * which already writes to vmcs12 directly.
6983  */
6984 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6985 {
6986         /* update guest state fields: */
6987         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6988         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6989
6990         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6991         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6992         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6993         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6994
6995         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6996         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6997         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6998         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6999         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7000         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7001         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7002         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7003         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7004         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7005         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7006         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7007         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7008         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7009         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7010         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7011         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7012         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7013         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7014         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7015         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7016         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7017         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7018         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7019         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7020         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7021         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7022         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7023         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7024         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7025         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7026         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7027         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7028         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7029         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7030         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7031
7032         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7033         vmcs12->guest_interruptibility_info =
7034                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7035         vmcs12->guest_pending_dbg_exceptions =
7036                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7037
7038         /* TODO: These cannot have changed unless we have MSR bitmaps and
7039          * the relevant bit asks not to trap the change */
7040         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7041         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7042                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7043         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7044         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7045         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7046
7047         /* update exit information fields: */
7048
7049         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
7050         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7051
7052         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7053         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7054         vmcs12->idt_vectoring_info_field =
7055                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7056         vmcs12->idt_vectoring_error_code =
7057                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7058         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7059         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7060
7061         /* clear vm-entry fields which are to be cleared on exit */
7062         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7063                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7064 }
7065
7066 /*
7067  * A part of what we need to when the nested L2 guest exits and we want to
7068  * run its L1 parent, is to reset L1's guest state to the host state specified
7069  * in vmcs12.
7070  * This function is to be called not only on normal nested exit, but also on
7071  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7072  * Failures During or After Loading Guest State").
7073  * This function should be called when the active VMCS is L1's (vmcs01).
7074  */
7075 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7076 {
7077         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7078                 vcpu->arch.efer = vmcs12->host_ia32_efer;
7079         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7080                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7081         else
7082                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7083         vmx_set_efer(vcpu, vcpu->arch.efer);
7084
7085         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7086         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7087         /*
7088          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7089          * actually changed, because it depends on the current state of
7090          * fpu_active (which may have changed).
7091          * Note that vmx_set_cr0 refers to efer set above.
7092          */
7093         kvm_set_cr0(vcpu, vmcs12->host_cr0);
7094         /*
7095          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7096          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7097          * but we also need to update cr0_guest_host_mask and exception_bitmap.
7098          */
7099         update_exception_bitmap(vcpu);
7100         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7101         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7102
7103         /*
7104          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7105          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7106          */
7107         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7108         kvm_set_cr4(vcpu, vmcs12->host_cr4);
7109
7110         /* shadow page tables on either EPT or shadow page tables */
7111         kvm_set_cr3(vcpu, vmcs12->host_cr3);
7112         kvm_mmu_reset_context(vcpu);
7113
7114         if (enable_vpid) {
7115                 /*
7116                  * Trivially support vpid by letting L2s share their parent
7117                  * L1's vpid. TODO: move to a more elaborate solution, giving
7118                  * each L2 its own vpid and exposing the vpid feature to L1.
7119                  */
7120                 vmx_flush_tlb(vcpu);
7121         }
7122
7123
7124         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7125         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7126         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7127         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7128         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7129         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7130         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7131         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7132         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7133         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7134         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7135         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7136         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7137         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7138         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7139
7140         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7141                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7142         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7143                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7144                         vmcs12->host_ia32_perf_global_ctrl);
7145 }
7146
7147 /*
7148  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7149  * and modify vmcs12 to make it see what it would expect to see there if
7150  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7151  */
7152 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7153 {
7154         struct vcpu_vmx *vmx = to_vmx(vcpu);
7155         int cpu;
7156         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7157
7158         leave_guest_mode(vcpu);
7159         prepare_vmcs12(vcpu, vmcs12);
7160
7161         cpu = get_cpu();
7162         vmx->loaded_vmcs = &vmx->vmcs01;
7163         vmx_vcpu_put(vcpu);
7164         vmx_vcpu_load(vcpu, cpu);
7165         vcpu->cpu = cpu;
7166         put_cpu();
7167
7168         /* if no vmcs02 cache requested, remove the one we used */
7169         if (VMCS02_POOL_SIZE == 0)
7170                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7171
7172         load_vmcs12_host_state(vcpu, vmcs12);
7173
7174         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7175         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7176
7177         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7178         vmx->host_rsp = 0;
7179
7180         /* Unpin physical memory we referred to in vmcs02 */
7181         if (vmx->nested.apic_access_page) {
7182                 nested_release_page(vmx->nested.apic_access_page);
7183                 vmx->nested.apic_access_page = 0;
7184         }
7185
7186         /*
7187          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7188          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7189          * success or failure flag accordingly.
7190          */
7191         if (unlikely(vmx->fail)) {
7192                 vmx->fail = 0;
7193                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7194         } else
7195                 nested_vmx_succeed(vcpu);
7196 }
7197
7198 /*
7199  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7200  * 23.7 "VM-entry failures during or after loading guest state" (this also
7201  * lists the acceptable exit-reason and exit-qualification parameters).
7202  * It should only be called before L2 actually succeeded to run, and when
7203  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7204  */
7205 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7206                         struct vmcs12 *vmcs12,
7207                         u32 reason, unsigned long qualification)
7208 {
7209         load_vmcs12_host_state(vcpu, vmcs12);
7210         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7211         vmcs12->exit_qualification = qualification;
7212         nested_vmx_succeed(vcpu);
7213 }
7214
7215 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7216                                struct x86_instruction_info *info,
7217                                enum x86_intercept_stage stage)
7218 {
7219         return X86EMUL_CONTINUE;
7220 }
7221
7222 static struct kvm_x86_ops vmx_x86_ops = {
7223         .cpu_has_kvm_support = cpu_has_kvm_support,
7224         .disabled_by_bios = vmx_disabled_by_bios,
7225         .hardware_setup = hardware_setup,
7226         .hardware_unsetup = hardware_unsetup,
7227         .check_processor_compatibility = vmx_check_processor_compat,
7228         .hardware_enable = hardware_enable,
7229         .hardware_disable = hardware_disable,
7230         .cpu_has_accelerated_tpr = report_flexpriority,
7231
7232         .vcpu_create = vmx_create_vcpu,
7233         .vcpu_free = vmx_free_vcpu,
7234         .vcpu_reset = vmx_vcpu_reset,
7235
7236         .prepare_guest_switch = vmx_save_host_state,
7237         .vcpu_load = vmx_vcpu_load,
7238         .vcpu_put = vmx_vcpu_put,
7239
7240         .set_guest_debug = set_guest_debug,
7241         .get_msr = vmx_get_msr,
7242         .set_msr = vmx_set_msr,
7243         .get_segment_base = vmx_get_segment_base,
7244         .get_segment = vmx_get_segment,
7245         .set_segment = vmx_set_segment,
7246         .get_cpl = vmx_get_cpl,
7247         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7248         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7249         .decache_cr3 = vmx_decache_cr3,
7250         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7251         .set_cr0 = vmx_set_cr0,
7252         .set_cr3 = vmx_set_cr3,
7253         .set_cr4 = vmx_set_cr4,
7254         .set_efer = vmx_set_efer,
7255         .get_idt = vmx_get_idt,
7256         .set_idt = vmx_set_idt,
7257         .get_gdt = vmx_get_gdt,
7258         .set_gdt = vmx_set_gdt,
7259         .set_dr7 = vmx_set_dr7,
7260         .cache_reg = vmx_cache_reg,
7261         .get_rflags = vmx_get_rflags,
7262         .set_rflags = vmx_set_rflags,
7263         .fpu_activate = vmx_fpu_activate,
7264         .fpu_deactivate = vmx_fpu_deactivate,
7265
7266         .tlb_flush = vmx_flush_tlb,
7267
7268         .run = vmx_vcpu_run,
7269         .handle_exit = vmx_handle_exit,
7270         .skip_emulated_instruction = skip_emulated_instruction,
7271         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7272         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7273         .patch_hypercall = vmx_patch_hypercall,
7274         .set_irq = vmx_inject_irq,
7275         .set_nmi = vmx_inject_nmi,
7276         .queue_exception = vmx_queue_exception,
7277         .cancel_injection = vmx_cancel_injection,
7278         .interrupt_allowed = vmx_interrupt_allowed,
7279         .nmi_allowed = vmx_nmi_allowed,
7280         .get_nmi_mask = vmx_get_nmi_mask,
7281         .set_nmi_mask = vmx_set_nmi_mask,
7282         .enable_nmi_window = enable_nmi_window,
7283         .enable_irq_window = enable_irq_window,
7284         .update_cr8_intercept = update_cr8_intercept,
7285
7286         .set_tss_addr = vmx_set_tss_addr,
7287         .get_tdp_level = get_ept_level,
7288         .get_mt_mask = vmx_get_mt_mask,
7289
7290         .get_exit_info = vmx_get_exit_info,
7291
7292         .get_lpage_level = vmx_get_lpage_level,
7293
7294         .cpuid_update = vmx_cpuid_update,
7295
7296         .rdtscp_supported = vmx_rdtscp_supported,
7297         .invpcid_supported = vmx_invpcid_supported,
7298
7299         .set_supported_cpuid = vmx_set_supported_cpuid,
7300
7301         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7302
7303         .set_tsc_khz = vmx_set_tsc_khz,
7304         .write_tsc_offset = vmx_write_tsc_offset,
7305         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7306         .compute_tsc_offset = vmx_compute_tsc_offset,
7307         .read_l1_tsc = vmx_read_l1_tsc,
7308
7309         .set_tdp_cr3 = vmx_set_cr3,
7310
7311         .check_intercept = vmx_check_intercept,
7312 };
7313
7314 static int __init vmx_init(void)
7315 {
7316         int r, i;
7317
7318         rdmsrl_safe(MSR_EFER, &host_efer);
7319
7320         for (i = 0; i < NR_VMX_MSR; ++i)
7321                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7322
7323         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7324         if (!vmx_io_bitmap_a)
7325                 return -ENOMEM;
7326
7327         r = -ENOMEM;
7328
7329         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7330         if (!vmx_io_bitmap_b)
7331                 goto out;
7332
7333         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7334         if (!vmx_msr_bitmap_legacy)
7335                 goto out1;
7336
7337
7338         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7339         if (!vmx_msr_bitmap_longmode)
7340                 goto out2;
7341
7342
7343         /*
7344          * Allow direct access to the PC debug port (it is often used for I/O
7345          * delays, but the vmexits simply slow things down).
7346          */
7347         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7348         clear_bit(0x80, vmx_io_bitmap_a);
7349
7350         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7351
7352         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7353         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7354
7355         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7356
7357         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7358                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7359         if (r)
7360                 goto out3;
7361
7362         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7363         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7364         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7365         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7366         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7367         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7368
7369         if (enable_ept) {
7370                 kvm_mmu_set_mask_ptes(0ull,
7371                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7372                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7373                         0ull, VMX_EPT_EXECUTABLE_MASK);
7374                 ept_set_mmio_spte_mask();
7375                 kvm_enable_tdp();
7376         } else
7377                 kvm_disable_tdp();
7378
7379         return 0;
7380
7381 out3:
7382         free_page((unsigned long)vmx_msr_bitmap_longmode);
7383 out2:
7384         free_page((unsigned long)vmx_msr_bitmap_legacy);
7385 out1:
7386         free_page((unsigned long)vmx_io_bitmap_b);
7387 out:
7388         free_page((unsigned long)vmx_io_bitmap_a);
7389         return r;
7390 }
7391
7392 static void __exit vmx_exit(void)
7393 {
7394         free_page((unsigned long)vmx_msr_bitmap_legacy);
7395         free_page((unsigned long)vmx_msr_bitmap_longmode);
7396         free_page((unsigned long)vmx_io_bitmap_b);
7397         free_page((unsigned long)vmx_io_bitmap_a);
7398
7399         kvm_exit();
7400 }
7401
7402 module_init(vmx_init)
7403 module_exit(vmx_exit)