2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include <linux/ftrace_event.h>
29 #include "kvm_cache_regs.h"
35 #include <asm/virtext.h>
40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
42 MODULE_AUTHOR("Qumranet");
43 MODULE_LICENSE("GPL");
45 static int __read_mostly bypass_guest_pf = 1;
46 module_param(bypass_guest_pf, bool, S_IRUGO);
48 static int __read_mostly enable_vpid = 1;
49 module_param_named(vpid, enable_vpid, bool, 0444);
51 static int __read_mostly flexpriority_enabled = 1;
52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
54 static int __read_mostly enable_ept = 1;
55 module_param_named(ept, enable_ept, bool, S_IRUGO);
57 static int __read_mostly enable_unrestricted_guest = 1;
58 module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
61 static int __read_mostly emulate_invalid_guest_state = 0;
62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
64 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
65 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
66 #define KVM_GUEST_CR0_MASK \
67 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
68 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
69 (X86_CR0_WP | X86_CR0_NE | X86_CR0_TS | X86_CR0_MP)
70 #define KVM_VM_CR0_ALWAYS_ON \
71 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
72 #define KVM_CR4_GUEST_OWNED_BITS \
73 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
76 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
77 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
80 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
81 * ple_gap: upper bound on the amount of time between two successive
82 * executions of PAUSE in a loop. Also indicate if ple enabled.
83 * According to test, this time is usually small than 41 cycles.
84 * ple_window: upper bound on the amount of time a guest is allowed to execute
85 * in a PAUSE loop. Tests indicate that most spinlocks are held for
86 * less than 2^12 cycles
87 * Time is measured based on a counter that runs at the same rate as the TSC,
88 * refer SDM volume 3b section 21.6.13 & 22.1.3.
90 #define KVM_VMX_DEFAULT_PLE_GAP 41
91 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
92 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
93 module_param(ple_gap, int, S_IRUGO);
95 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
96 module_param(ple_window, int, S_IRUGO);
104 struct shared_msr_entry {
111 struct kvm_vcpu vcpu;
112 struct list_head local_vcpus_link;
113 unsigned long host_rsp;
116 u32 idt_vectoring_info;
117 struct shared_msr_entry *guest_msrs;
121 u64 msr_host_kernel_gs_base;
122 u64 msr_guest_kernel_gs_base;
127 u16 fs_sel, gs_sel, ldt_sel;
128 int gs_ldt_reload_needed;
129 int fs_reload_needed;
134 struct kvm_save_segment {
139 } tr, es, ds, fs, gs;
147 bool emulation_required;
149 /* Support for vnmi-less CPUs */
150 int soft_vnmi_blocked;
152 s64 vnmi_blocked_time;
158 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
160 return container_of(vcpu, struct vcpu_vmx, vcpu);
163 static int init_rmode(struct kvm *kvm);
164 static u64 construct_eptp(unsigned long root_hpa);
166 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
167 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
168 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
170 static unsigned long *vmx_io_bitmap_a;
171 static unsigned long *vmx_io_bitmap_b;
172 static unsigned long *vmx_msr_bitmap_legacy;
173 static unsigned long *vmx_msr_bitmap_longmode;
175 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
176 static DEFINE_SPINLOCK(vmx_vpid_lock);
178 static struct vmcs_config {
182 u32 pin_based_exec_ctrl;
183 u32 cpu_based_exec_ctrl;
184 u32 cpu_based_2nd_exec_ctrl;
189 static struct vmx_capability {
194 #define VMX_SEGMENT_FIELD(seg) \
195 [VCPU_SREG_##seg] = { \
196 .selector = GUEST_##seg##_SELECTOR, \
197 .base = GUEST_##seg##_BASE, \
198 .limit = GUEST_##seg##_LIMIT, \
199 .ar_bytes = GUEST_##seg##_AR_BYTES, \
202 static struct kvm_vmx_segment_field {
207 } kvm_vmx_segment_fields[] = {
208 VMX_SEGMENT_FIELD(CS),
209 VMX_SEGMENT_FIELD(DS),
210 VMX_SEGMENT_FIELD(ES),
211 VMX_SEGMENT_FIELD(FS),
212 VMX_SEGMENT_FIELD(GS),
213 VMX_SEGMENT_FIELD(SS),
214 VMX_SEGMENT_FIELD(TR),
215 VMX_SEGMENT_FIELD(LDTR),
218 static u64 host_efer;
220 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
223 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
224 * away by decrementing the array size.
226 static const u32 vmx_msr_index[] = {
228 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
230 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
232 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
234 static inline int is_page_fault(u32 intr_info)
236 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
237 INTR_INFO_VALID_MASK)) ==
238 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
241 static inline int is_no_device(u32 intr_info)
243 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
244 INTR_INFO_VALID_MASK)) ==
245 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
248 static inline int is_invalid_opcode(u32 intr_info)
250 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
251 INTR_INFO_VALID_MASK)) ==
252 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
255 static inline int is_external_interrupt(u32 intr_info)
257 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
258 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
261 static inline int is_machine_check(u32 intr_info)
263 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
264 INTR_INFO_VALID_MASK)) ==
265 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
268 static inline int cpu_has_vmx_msr_bitmap(void)
270 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
273 static inline int cpu_has_vmx_tpr_shadow(void)
275 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
278 static inline int vm_need_tpr_shadow(struct kvm *kvm)
280 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
283 static inline int cpu_has_secondary_exec_ctrls(void)
285 return vmcs_config.cpu_based_exec_ctrl &
286 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
289 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
291 return vmcs_config.cpu_based_2nd_exec_ctrl &
292 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
295 static inline bool cpu_has_vmx_flexpriority(void)
297 return cpu_has_vmx_tpr_shadow() &&
298 cpu_has_vmx_virtualize_apic_accesses();
301 static inline bool cpu_has_vmx_ept_execute_only(void)
303 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
306 static inline bool cpu_has_vmx_eptp_uncacheable(void)
308 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
311 static inline bool cpu_has_vmx_eptp_writeback(void)
313 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
316 static inline bool cpu_has_vmx_ept_2m_page(void)
318 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
321 static inline int cpu_has_vmx_invept_individual_addr(void)
323 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
326 static inline int cpu_has_vmx_invept_context(void)
328 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
331 static inline int cpu_has_vmx_invept_global(void)
333 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
336 static inline int cpu_has_vmx_ept(void)
338 return vmcs_config.cpu_based_2nd_exec_ctrl &
339 SECONDARY_EXEC_ENABLE_EPT;
342 static inline int cpu_has_vmx_unrestricted_guest(void)
344 return vmcs_config.cpu_based_2nd_exec_ctrl &
345 SECONDARY_EXEC_UNRESTRICTED_GUEST;
348 static inline int cpu_has_vmx_ple(void)
350 return vmcs_config.cpu_based_2nd_exec_ctrl &
351 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
354 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
356 return flexpriority_enabled &&
357 (cpu_has_vmx_virtualize_apic_accesses()) &&
358 (irqchip_in_kernel(kvm));
361 static inline int cpu_has_vmx_vpid(void)
363 return vmcs_config.cpu_based_2nd_exec_ctrl &
364 SECONDARY_EXEC_ENABLE_VPID;
367 static inline int cpu_has_vmx_rdtscp(void)
369 return vmcs_config.cpu_based_2nd_exec_ctrl &
370 SECONDARY_EXEC_RDTSCP;
373 static inline int cpu_has_virtual_nmis(void)
375 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
378 static inline bool report_flexpriority(void)
380 return flexpriority_enabled;
383 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
387 for (i = 0; i < vmx->nmsrs; ++i)
388 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
393 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
399 } operand = { vpid, 0, gva };
401 asm volatile (__ex(ASM_VMX_INVVPID)
402 /* CF==1 or ZF==1 --> rc = -1 */
404 : : "a"(&operand), "c"(ext) : "cc", "memory");
407 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
411 } operand = {eptp, gpa};
413 asm volatile (__ex(ASM_VMX_INVEPT)
414 /* CF==1 or ZF==1 --> rc = -1 */
415 "; ja 1f ; ud2 ; 1:\n"
416 : : "a" (&operand), "c" (ext) : "cc", "memory");
419 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
423 i = __find_msr_index(vmx, msr);
425 return &vmx->guest_msrs[i];
429 static void vmcs_clear(struct vmcs *vmcs)
431 u64 phys_addr = __pa(vmcs);
434 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
435 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
438 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
442 static void __vcpu_clear(void *arg)
444 struct vcpu_vmx *vmx = arg;
445 int cpu = raw_smp_processor_id();
447 if (vmx->vcpu.cpu == cpu)
448 vmcs_clear(vmx->vmcs);
449 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
450 per_cpu(current_vmcs, cpu) = NULL;
451 rdtscll(vmx->vcpu.arch.host_tsc);
452 list_del(&vmx->local_vcpus_link);
457 static void vcpu_clear(struct vcpu_vmx *vmx)
459 if (vmx->vcpu.cpu == -1)
461 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
464 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
469 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
472 static inline void ept_sync_global(void)
474 if (cpu_has_vmx_invept_global())
475 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
478 static inline void ept_sync_context(u64 eptp)
481 if (cpu_has_vmx_invept_context())
482 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
488 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
491 if (cpu_has_vmx_invept_individual_addr())
492 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
495 ept_sync_context(eptp);
499 static unsigned long vmcs_readl(unsigned long field)
503 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
504 : "=a"(value) : "d"(field) : "cc");
508 static u16 vmcs_read16(unsigned long field)
510 return vmcs_readl(field);
513 static u32 vmcs_read32(unsigned long field)
515 return vmcs_readl(field);
518 static u64 vmcs_read64(unsigned long field)
521 return vmcs_readl(field);
523 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
527 static noinline void vmwrite_error(unsigned long field, unsigned long value)
529 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
530 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
534 static void vmcs_writel(unsigned long field, unsigned long value)
538 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
539 : "=q"(error) : "a"(value), "d"(field) : "cc");
541 vmwrite_error(field, value);
544 static void vmcs_write16(unsigned long field, u16 value)
546 vmcs_writel(field, value);
549 static void vmcs_write32(unsigned long field, u32 value)
551 vmcs_writel(field, value);
554 static void vmcs_write64(unsigned long field, u64 value)
556 vmcs_writel(field, value);
557 #ifndef CONFIG_X86_64
559 vmcs_writel(field+1, value >> 32);
563 static void vmcs_clear_bits(unsigned long field, u32 mask)
565 vmcs_writel(field, vmcs_readl(field) & ~mask);
568 static void vmcs_set_bits(unsigned long field, u32 mask)
570 vmcs_writel(field, vmcs_readl(field) | mask);
573 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
577 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
578 if (!vcpu->fpu_active)
579 eb |= 1u << NM_VECTOR;
581 * Unconditionally intercept #DB so we can maintain dr6 without
582 * reading it every exit.
584 eb |= 1u << DB_VECTOR;
585 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
586 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
587 eb |= 1u << BP_VECTOR;
589 if (to_vmx(vcpu)->rmode.vm86_active)
592 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
593 vmcs_write32(EXCEPTION_BITMAP, eb);
596 static void reload_tss(void)
599 * VT restores TR but not its size. Useless.
601 struct descriptor_table gdt;
602 struct desc_struct *descs;
605 descs = (void *)gdt.base;
606 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
610 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
615 guest_efer = vmx->vcpu.arch.shadow_efer;
618 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
621 ignore_bits = EFER_NX | EFER_SCE;
623 ignore_bits |= EFER_LMA | EFER_LME;
624 /* SCE is meaningful only in long mode on Intel */
625 if (guest_efer & EFER_LMA)
626 ignore_bits &= ~(u64)EFER_SCE;
628 guest_efer &= ~ignore_bits;
629 guest_efer |= host_efer & ignore_bits;
630 vmx->guest_msrs[efer_offset].data = guest_efer;
631 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
635 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
637 struct vcpu_vmx *vmx = to_vmx(vcpu);
640 if (vmx->host_state.loaded)
643 vmx->host_state.loaded = 1;
645 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
646 * allow segment selectors with cpl > 0 or ti == 1.
648 vmx->host_state.ldt_sel = kvm_read_ldt();
649 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
650 vmx->host_state.fs_sel = kvm_read_fs();
651 if (!(vmx->host_state.fs_sel & 7)) {
652 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
653 vmx->host_state.fs_reload_needed = 0;
655 vmcs_write16(HOST_FS_SELECTOR, 0);
656 vmx->host_state.fs_reload_needed = 1;
658 vmx->host_state.gs_sel = kvm_read_gs();
659 if (!(vmx->host_state.gs_sel & 7))
660 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
662 vmcs_write16(HOST_GS_SELECTOR, 0);
663 vmx->host_state.gs_ldt_reload_needed = 1;
667 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
668 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
670 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
671 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
675 if (is_long_mode(&vmx->vcpu)) {
676 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
677 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
680 for (i = 0; i < vmx->save_nmsrs; ++i)
681 kvm_set_shared_msr(vmx->guest_msrs[i].index,
682 vmx->guest_msrs[i].data,
683 vmx->guest_msrs[i].mask);
686 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
690 if (!vmx->host_state.loaded)
693 ++vmx->vcpu.stat.host_state_reload;
694 vmx->host_state.loaded = 0;
695 if (vmx->host_state.fs_reload_needed)
696 kvm_load_fs(vmx->host_state.fs_sel);
697 if (vmx->host_state.gs_ldt_reload_needed) {
698 kvm_load_ldt(vmx->host_state.ldt_sel);
700 * If we have to reload gs, we must take care to
701 * preserve our gs base.
703 local_irq_save(flags);
704 kvm_load_gs(vmx->host_state.gs_sel);
706 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
708 local_irq_restore(flags);
712 if (is_long_mode(&vmx->vcpu)) {
713 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
714 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
719 static void vmx_load_host_state(struct vcpu_vmx *vmx)
722 __vmx_load_host_state(vmx);
727 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
728 * vcpu mutex is already taken.
730 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
732 struct vcpu_vmx *vmx = to_vmx(vcpu);
733 u64 phys_addr = __pa(vmx->vmcs);
734 u64 tsc_this, delta, new_offset;
736 if (vcpu->cpu != cpu) {
738 kvm_migrate_timers(vcpu);
739 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
741 list_add(&vmx->local_vcpus_link,
742 &per_cpu(vcpus_on_cpu, cpu));
746 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
749 per_cpu(current_vmcs, cpu) = vmx->vmcs;
750 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
751 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
754 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
755 vmx->vmcs, phys_addr);
758 if (vcpu->cpu != cpu) {
759 struct descriptor_table dt;
760 unsigned long sysenter_esp;
764 * Linux uses per-cpu TSS and GDT, so set these when switching
767 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
769 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
771 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
772 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
775 * Make sure the time stamp counter is monotonous.
778 if (tsc_this < vcpu->arch.host_tsc) {
779 delta = vcpu->arch.host_tsc - tsc_this;
780 new_offset = vmcs_read64(TSC_OFFSET) + delta;
781 vmcs_write64(TSC_OFFSET, new_offset);
786 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
788 __vmx_load_host_state(to_vmx(vcpu));
791 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
793 if (vcpu->fpu_active)
795 vcpu->fpu_active = 1;
796 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
797 if (vcpu->arch.cr0 & X86_CR0_TS)
798 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
799 update_exception_bitmap(vcpu);
802 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
804 if (!vcpu->fpu_active)
806 vcpu->fpu_active = 0;
807 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
808 update_exception_bitmap(vcpu);
811 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
813 unsigned long rflags;
815 rflags = vmcs_readl(GUEST_RFLAGS);
816 if (to_vmx(vcpu)->rmode.vm86_active)
817 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
821 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
823 if (to_vmx(vcpu)->rmode.vm86_active)
824 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
825 vmcs_writel(GUEST_RFLAGS, rflags);
828 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
830 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
833 if (interruptibility & GUEST_INTR_STATE_STI)
834 ret |= X86_SHADOW_INT_STI;
835 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
836 ret |= X86_SHADOW_INT_MOV_SS;
841 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
843 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
844 u32 interruptibility = interruptibility_old;
846 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
848 if (mask & X86_SHADOW_INT_MOV_SS)
849 interruptibility |= GUEST_INTR_STATE_MOV_SS;
850 if (mask & X86_SHADOW_INT_STI)
851 interruptibility |= GUEST_INTR_STATE_STI;
853 if ((interruptibility != interruptibility_old))
854 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
857 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
861 rip = kvm_rip_read(vcpu);
862 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
863 kvm_rip_write(vcpu, rip);
865 /* skipping an emulated instruction also counts */
866 vmx_set_interrupt_shadow(vcpu, 0);
869 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
870 bool has_error_code, u32 error_code)
872 struct vcpu_vmx *vmx = to_vmx(vcpu);
873 u32 intr_info = nr | INTR_INFO_VALID_MASK;
875 if (has_error_code) {
876 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
877 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
880 if (vmx->rmode.vm86_active) {
881 vmx->rmode.irq.pending = true;
882 vmx->rmode.irq.vector = nr;
883 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
884 if (kvm_exception_is_soft(nr))
885 vmx->rmode.irq.rip +=
886 vmx->vcpu.arch.event_exit_inst_len;
887 intr_info |= INTR_TYPE_SOFT_INTR;
888 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
889 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
890 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
894 if (kvm_exception_is_soft(nr)) {
895 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
896 vmx->vcpu.arch.event_exit_inst_len);
897 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
899 intr_info |= INTR_TYPE_HARD_EXCEPTION;
901 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
904 static bool vmx_rdtscp_supported(void)
906 return cpu_has_vmx_rdtscp();
910 * Swap MSR entry in host/guest MSR entry array.
912 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
914 struct shared_msr_entry tmp;
916 tmp = vmx->guest_msrs[to];
917 vmx->guest_msrs[to] = vmx->guest_msrs[from];
918 vmx->guest_msrs[from] = tmp;
922 * Set up the vmcs to automatically save and restore system
923 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
924 * mode, as fiddling with msrs is very expensive.
926 static void setup_msrs(struct vcpu_vmx *vmx)
928 int save_nmsrs, index;
929 unsigned long *msr_bitmap;
931 vmx_load_host_state(vmx);
934 if (is_long_mode(&vmx->vcpu)) {
935 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
937 move_msr_up(vmx, index, save_nmsrs++);
938 index = __find_msr_index(vmx, MSR_LSTAR);
940 move_msr_up(vmx, index, save_nmsrs++);
941 index = __find_msr_index(vmx, MSR_CSTAR);
943 move_msr_up(vmx, index, save_nmsrs++);
944 index = __find_msr_index(vmx, MSR_TSC_AUX);
945 if (index >= 0 && vmx->rdtscp_enabled)
946 move_msr_up(vmx, index, save_nmsrs++);
948 * MSR_K6_STAR is only needed on long mode guests, and only
949 * if efer.sce is enabled.
951 index = __find_msr_index(vmx, MSR_K6_STAR);
952 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
953 move_msr_up(vmx, index, save_nmsrs++);
956 index = __find_msr_index(vmx, MSR_EFER);
957 if (index >= 0 && update_transition_efer(vmx, index))
958 move_msr_up(vmx, index, save_nmsrs++);
960 vmx->save_nmsrs = save_nmsrs;
962 if (cpu_has_vmx_msr_bitmap()) {
963 if (is_long_mode(&vmx->vcpu))
964 msr_bitmap = vmx_msr_bitmap_longmode;
966 msr_bitmap = vmx_msr_bitmap_legacy;
968 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
973 * reads and returns guest's timestamp counter "register"
974 * guest_tsc = host_tsc + tsc_offset -- 21.3
976 static u64 guest_read_tsc(void)
978 u64 host_tsc, tsc_offset;
981 tsc_offset = vmcs_read64(TSC_OFFSET);
982 return host_tsc + tsc_offset;
986 * writes 'guest_tsc' into guest's timestamp counter "register"
987 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
989 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
991 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
995 * Reads an msr value (of 'msr_index') into 'pdata'.
996 * Returns 0 on success, non-0 otherwise.
997 * Assumes vcpu_load() was already called.
999 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1002 struct shared_msr_entry *msr;
1005 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1009 switch (msr_index) {
1010 #ifdef CONFIG_X86_64
1012 data = vmcs_readl(GUEST_FS_BASE);
1015 data = vmcs_readl(GUEST_GS_BASE);
1017 case MSR_KERNEL_GS_BASE:
1018 vmx_load_host_state(to_vmx(vcpu));
1019 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1023 return kvm_get_msr_common(vcpu, msr_index, pdata);
1025 data = guest_read_tsc();
1027 case MSR_IA32_SYSENTER_CS:
1028 data = vmcs_read32(GUEST_SYSENTER_CS);
1030 case MSR_IA32_SYSENTER_EIP:
1031 data = vmcs_readl(GUEST_SYSENTER_EIP);
1033 case MSR_IA32_SYSENTER_ESP:
1034 data = vmcs_readl(GUEST_SYSENTER_ESP);
1037 if (!to_vmx(vcpu)->rdtscp_enabled)
1039 /* Otherwise falls through */
1041 vmx_load_host_state(to_vmx(vcpu));
1042 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1044 vmx_load_host_state(to_vmx(vcpu));
1048 return kvm_get_msr_common(vcpu, msr_index, pdata);
1056 * Writes msr value into into the appropriate "register".
1057 * Returns 0 on success, non-0 otherwise.
1058 * Assumes vcpu_load() was already called.
1060 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1062 struct vcpu_vmx *vmx = to_vmx(vcpu);
1063 struct shared_msr_entry *msr;
1067 switch (msr_index) {
1069 vmx_load_host_state(vmx);
1070 ret = kvm_set_msr_common(vcpu, msr_index, data);
1072 #ifdef CONFIG_X86_64
1074 vmcs_writel(GUEST_FS_BASE, data);
1077 vmcs_writel(GUEST_GS_BASE, data);
1079 case MSR_KERNEL_GS_BASE:
1080 vmx_load_host_state(vmx);
1081 vmx->msr_guest_kernel_gs_base = data;
1084 case MSR_IA32_SYSENTER_CS:
1085 vmcs_write32(GUEST_SYSENTER_CS, data);
1087 case MSR_IA32_SYSENTER_EIP:
1088 vmcs_writel(GUEST_SYSENTER_EIP, data);
1090 case MSR_IA32_SYSENTER_ESP:
1091 vmcs_writel(GUEST_SYSENTER_ESP, data);
1095 guest_write_tsc(data, host_tsc);
1097 case MSR_IA32_CR_PAT:
1098 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1099 vmcs_write64(GUEST_IA32_PAT, data);
1100 vcpu->arch.pat = data;
1103 ret = kvm_set_msr_common(vcpu, msr_index, data);
1106 if (!vmx->rdtscp_enabled)
1108 /* Check reserved bit, higher 32 bits should be zero */
1109 if ((data >> 32) != 0)
1111 /* Otherwise falls through */
1113 msr = find_msr_entry(vmx, msr_index);
1115 vmx_load_host_state(vmx);
1119 ret = kvm_set_msr_common(vcpu, msr_index, data);
1125 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1127 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1130 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1133 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1135 case VCPU_EXREG_PDPTR:
1137 ept_save_pdptrs(vcpu);
1144 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1146 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1147 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1149 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1151 update_exception_bitmap(vcpu);
1154 static __init int cpu_has_kvm_support(void)
1156 return cpu_has_vmx();
1159 static __init int vmx_disabled_by_bios(void)
1163 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1164 return (msr & (FEATURE_CONTROL_LOCKED |
1165 FEATURE_CONTROL_VMXON_ENABLED))
1166 == FEATURE_CONTROL_LOCKED;
1167 /* locked but not enabled */
1170 static int hardware_enable(void *garbage)
1172 int cpu = raw_smp_processor_id();
1173 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1176 if (read_cr4() & X86_CR4_VMXE)
1179 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1180 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1181 if ((old & (FEATURE_CONTROL_LOCKED |
1182 FEATURE_CONTROL_VMXON_ENABLED))
1183 != (FEATURE_CONTROL_LOCKED |
1184 FEATURE_CONTROL_VMXON_ENABLED))
1185 /* enable and lock */
1186 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1187 FEATURE_CONTROL_LOCKED |
1188 FEATURE_CONTROL_VMXON_ENABLED);
1189 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1190 asm volatile (ASM_VMX_VMXON_RAX
1191 : : "a"(&phys_addr), "m"(phys_addr)
1199 static void vmclear_local_vcpus(void)
1201 int cpu = raw_smp_processor_id();
1202 struct vcpu_vmx *vmx, *n;
1204 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1210 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1213 static void kvm_cpu_vmxoff(void)
1215 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1216 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1219 static void hardware_disable(void *garbage)
1221 vmclear_local_vcpus();
1225 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1226 u32 msr, u32 *result)
1228 u32 vmx_msr_low, vmx_msr_high;
1229 u32 ctl = ctl_min | ctl_opt;
1231 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1233 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1234 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1236 /* Ensure minimum (required) set of control bits are supported. */
1244 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1246 u32 vmx_msr_low, vmx_msr_high;
1247 u32 min, opt, min2, opt2;
1248 u32 _pin_based_exec_control = 0;
1249 u32 _cpu_based_exec_control = 0;
1250 u32 _cpu_based_2nd_exec_control = 0;
1251 u32 _vmexit_control = 0;
1252 u32 _vmentry_control = 0;
1254 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1255 opt = PIN_BASED_VIRTUAL_NMIS;
1256 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1257 &_pin_based_exec_control) < 0)
1260 min = CPU_BASED_HLT_EXITING |
1261 #ifdef CONFIG_X86_64
1262 CPU_BASED_CR8_LOAD_EXITING |
1263 CPU_BASED_CR8_STORE_EXITING |
1265 CPU_BASED_CR3_LOAD_EXITING |
1266 CPU_BASED_CR3_STORE_EXITING |
1267 CPU_BASED_USE_IO_BITMAPS |
1268 CPU_BASED_MOV_DR_EXITING |
1269 CPU_BASED_USE_TSC_OFFSETING |
1270 CPU_BASED_MWAIT_EXITING |
1271 CPU_BASED_MONITOR_EXITING |
1272 CPU_BASED_INVLPG_EXITING;
1273 opt = CPU_BASED_TPR_SHADOW |
1274 CPU_BASED_USE_MSR_BITMAPS |
1275 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1276 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1277 &_cpu_based_exec_control) < 0)
1279 #ifdef CONFIG_X86_64
1280 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1281 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1282 ~CPU_BASED_CR8_STORE_EXITING;
1284 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1286 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1287 SECONDARY_EXEC_WBINVD_EXITING |
1288 SECONDARY_EXEC_ENABLE_VPID |
1289 SECONDARY_EXEC_ENABLE_EPT |
1290 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1291 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1292 SECONDARY_EXEC_RDTSCP;
1293 if (adjust_vmx_controls(min2, opt2,
1294 MSR_IA32_VMX_PROCBASED_CTLS2,
1295 &_cpu_based_2nd_exec_control) < 0)
1298 #ifndef CONFIG_X86_64
1299 if (!(_cpu_based_2nd_exec_control &
1300 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1301 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1303 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1304 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1306 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1307 CPU_BASED_CR3_STORE_EXITING |
1308 CPU_BASED_INVLPG_EXITING);
1309 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1310 vmx_capability.ept, vmx_capability.vpid);
1314 #ifdef CONFIG_X86_64
1315 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1317 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1318 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1319 &_vmexit_control) < 0)
1323 opt = VM_ENTRY_LOAD_IA32_PAT;
1324 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1325 &_vmentry_control) < 0)
1328 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1330 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1331 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1334 #ifdef CONFIG_X86_64
1335 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1336 if (vmx_msr_high & (1u<<16))
1340 /* Require Write-Back (WB) memory type for VMCS accesses. */
1341 if (((vmx_msr_high >> 18) & 15) != 6)
1344 vmcs_conf->size = vmx_msr_high & 0x1fff;
1345 vmcs_conf->order = get_order(vmcs_config.size);
1346 vmcs_conf->revision_id = vmx_msr_low;
1348 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1349 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1350 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1351 vmcs_conf->vmexit_ctrl = _vmexit_control;
1352 vmcs_conf->vmentry_ctrl = _vmentry_control;
1357 static struct vmcs *alloc_vmcs_cpu(int cpu)
1359 int node = cpu_to_node(cpu);
1363 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1366 vmcs = page_address(pages);
1367 memset(vmcs, 0, vmcs_config.size);
1368 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1372 static struct vmcs *alloc_vmcs(void)
1374 return alloc_vmcs_cpu(raw_smp_processor_id());
1377 static void free_vmcs(struct vmcs *vmcs)
1379 free_pages((unsigned long)vmcs, vmcs_config.order);
1382 static void free_kvm_area(void)
1386 for_each_possible_cpu(cpu) {
1387 free_vmcs(per_cpu(vmxarea, cpu));
1388 per_cpu(vmxarea, cpu) = NULL;
1392 static __init int alloc_kvm_area(void)
1396 for_each_possible_cpu(cpu) {
1399 vmcs = alloc_vmcs_cpu(cpu);
1405 per_cpu(vmxarea, cpu) = vmcs;
1410 static __init int hardware_setup(void)
1412 if (setup_vmcs_config(&vmcs_config) < 0)
1415 if (boot_cpu_has(X86_FEATURE_NX))
1416 kvm_enable_efer_bits(EFER_NX);
1418 if (!cpu_has_vmx_vpid())
1421 if (!cpu_has_vmx_ept()) {
1423 enable_unrestricted_guest = 0;
1426 if (!cpu_has_vmx_unrestricted_guest())
1427 enable_unrestricted_guest = 0;
1429 if (!cpu_has_vmx_flexpriority())
1430 flexpriority_enabled = 0;
1432 if (!cpu_has_vmx_tpr_shadow())
1433 kvm_x86_ops->update_cr8_intercept = NULL;
1435 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1436 kvm_disable_largepages();
1438 if (!cpu_has_vmx_ple())
1441 return alloc_kvm_area();
1444 static __exit void hardware_unsetup(void)
1449 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1451 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1453 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1454 vmcs_write16(sf->selector, save->selector);
1455 vmcs_writel(sf->base, save->base);
1456 vmcs_write32(sf->limit, save->limit);
1457 vmcs_write32(sf->ar_bytes, save->ar);
1459 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1461 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1465 static void enter_pmode(struct kvm_vcpu *vcpu)
1467 unsigned long flags;
1468 struct vcpu_vmx *vmx = to_vmx(vcpu);
1470 vmx->emulation_required = 1;
1471 vmx->rmode.vm86_active = 0;
1473 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1474 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1475 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1477 flags = vmcs_readl(GUEST_RFLAGS);
1478 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1479 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1480 vmcs_writel(GUEST_RFLAGS, flags);
1482 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1483 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1485 update_exception_bitmap(vcpu);
1487 if (emulate_invalid_guest_state)
1490 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1491 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1492 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1493 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1495 vmcs_write16(GUEST_SS_SELECTOR, 0);
1496 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1498 vmcs_write16(GUEST_CS_SELECTOR,
1499 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1500 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1503 static gva_t rmode_tss_base(struct kvm *kvm)
1505 if (!kvm->arch.tss_addr) {
1506 gfn_t base_gfn = kvm->memslots->memslots[0].base_gfn +
1507 kvm->memslots->memslots[0].npages - 3;
1508 return base_gfn << PAGE_SHIFT;
1510 return kvm->arch.tss_addr;
1513 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1515 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1517 save->selector = vmcs_read16(sf->selector);
1518 save->base = vmcs_readl(sf->base);
1519 save->limit = vmcs_read32(sf->limit);
1520 save->ar = vmcs_read32(sf->ar_bytes);
1521 vmcs_write16(sf->selector, save->base >> 4);
1522 vmcs_write32(sf->base, save->base & 0xfffff);
1523 vmcs_write32(sf->limit, 0xffff);
1524 vmcs_write32(sf->ar_bytes, 0xf3);
1527 static void enter_rmode(struct kvm_vcpu *vcpu)
1529 unsigned long flags;
1530 struct vcpu_vmx *vmx = to_vmx(vcpu);
1532 if (enable_unrestricted_guest)
1535 vmx->emulation_required = 1;
1536 vmx->rmode.vm86_active = 1;
1538 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1539 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1541 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1542 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1544 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1545 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1547 flags = vmcs_readl(GUEST_RFLAGS);
1548 vmx->rmode.save_iopl
1549 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1551 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1553 vmcs_writel(GUEST_RFLAGS, flags);
1554 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1555 update_exception_bitmap(vcpu);
1557 if (emulate_invalid_guest_state)
1558 goto continue_rmode;
1560 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1561 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1562 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1564 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1565 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1566 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1567 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1568 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1570 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1571 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1572 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1573 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1576 kvm_mmu_reset_context(vcpu);
1577 init_rmode(vcpu->kvm);
1580 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1582 struct vcpu_vmx *vmx = to_vmx(vcpu);
1583 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1589 * Force kernel_gs_base reloading before EFER changes, as control
1590 * of this msr depends on is_long_mode().
1592 vmx_load_host_state(to_vmx(vcpu));
1593 vcpu->arch.shadow_efer = efer;
1596 if (efer & EFER_LMA) {
1597 vmcs_write32(VM_ENTRY_CONTROLS,
1598 vmcs_read32(VM_ENTRY_CONTROLS) |
1599 VM_ENTRY_IA32E_MODE);
1602 vmcs_write32(VM_ENTRY_CONTROLS,
1603 vmcs_read32(VM_ENTRY_CONTROLS) &
1604 ~VM_ENTRY_IA32E_MODE);
1606 msr->data = efer & ~EFER_LME;
1611 #ifdef CONFIG_X86_64
1613 static void enter_lmode(struct kvm_vcpu *vcpu)
1617 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1618 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1619 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1621 vmcs_write32(GUEST_TR_AR_BYTES,
1622 (guest_tr_ar & ~AR_TYPE_MASK)
1623 | AR_TYPE_BUSY_64_TSS);
1625 vcpu->arch.shadow_efer |= EFER_LMA;
1626 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1629 static void exit_lmode(struct kvm_vcpu *vcpu)
1631 vcpu->arch.shadow_efer &= ~EFER_LMA;
1633 vmcs_write32(VM_ENTRY_CONTROLS,
1634 vmcs_read32(VM_ENTRY_CONTROLS)
1635 & ~VM_ENTRY_IA32E_MODE);
1640 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1642 vpid_sync_vcpu_all(to_vmx(vcpu));
1644 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1647 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1649 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1651 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1652 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1655 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1657 if (!test_bit(VCPU_EXREG_PDPTR,
1658 (unsigned long *)&vcpu->arch.regs_dirty))
1661 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1662 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1663 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1664 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1665 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1669 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1671 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1672 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1673 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1674 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1675 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1678 __set_bit(VCPU_EXREG_PDPTR,
1679 (unsigned long *)&vcpu->arch.regs_avail);
1680 __set_bit(VCPU_EXREG_PDPTR,
1681 (unsigned long *)&vcpu->arch.regs_dirty);
1684 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1686 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1688 struct kvm_vcpu *vcpu)
1690 if (!(cr0 & X86_CR0_PG)) {
1691 /* From paging/starting to nonpaging */
1692 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1693 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1694 (CPU_BASED_CR3_LOAD_EXITING |
1695 CPU_BASED_CR3_STORE_EXITING));
1696 vcpu->arch.cr0 = cr0;
1697 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1698 } else if (!is_paging(vcpu)) {
1699 /* From nonpaging to paging */
1700 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1701 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1702 ~(CPU_BASED_CR3_LOAD_EXITING |
1703 CPU_BASED_CR3_STORE_EXITING));
1704 vcpu->arch.cr0 = cr0;
1705 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1708 if (!(cr0 & X86_CR0_WP))
1709 *hw_cr0 &= ~X86_CR0_WP;
1712 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1714 struct vcpu_vmx *vmx = to_vmx(vcpu);
1715 unsigned long hw_cr0;
1717 if (enable_unrestricted_guest)
1718 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1719 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1721 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1723 vmx_fpu_deactivate(vcpu);
1725 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1728 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1731 #ifdef CONFIG_X86_64
1732 if (vcpu->arch.shadow_efer & EFER_LME) {
1733 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1735 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1741 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1743 vmcs_writel(CR0_READ_SHADOW, cr0);
1744 vmcs_writel(GUEST_CR0, hw_cr0);
1745 vcpu->arch.cr0 = cr0;
1747 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1748 vmx_fpu_activate(vcpu);
1751 static u64 construct_eptp(unsigned long root_hpa)
1755 /* TODO write the value reading from MSR */
1756 eptp = VMX_EPT_DEFAULT_MT |
1757 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1758 eptp |= (root_hpa & PAGE_MASK);
1763 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1765 unsigned long guest_cr3;
1770 eptp = construct_eptp(cr3);
1771 vmcs_write64(EPT_POINTER, eptp);
1772 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1773 vcpu->kvm->arch.ept_identity_map_addr;
1774 ept_load_pdptrs(vcpu);
1777 vmx_flush_tlb(vcpu);
1778 vmcs_writel(GUEST_CR3, guest_cr3);
1779 if (vcpu->arch.cr0 & X86_CR0_PE)
1780 vmx_fpu_deactivate(vcpu);
1783 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1785 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1786 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1788 vcpu->arch.cr4 = cr4;
1790 if (!is_paging(vcpu)) {
1791 hw_cr4 &= ~X86_CR4_PAE;
1792 hw_cr4 |= X86_CR4_PSE;
1793 } else if (!(cr4 & X86_CR4_PAE)) {
1794 hw_cr4 &= ~X86_CR4_PAE;
1798 vmcs_writel(CR4_READ_SHADOW, cr4);
1799 vmcs_writel(GUEST_CR4, hw_cr4);
1802 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1804 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1806 return vmcs_readl(sf->base);
1809 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1810 struct kvm_segment *var, int seg)
1812 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1815 var->base = vmcs_readl(sf->base);
1816 var->limit = vmcs_read32(sf->limit);
1817 var->selector = vmcs_read16(sf->selector);
1818 ar = vmcs_read32(sf->ar_bytes);
1819 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1821 var->type = ar & 15;
1822 var->s = (ar >> 4) & 1;
1823 var->dpl = (ar >> 5) & 3;
1824 var->present = (ar >> 7) & 1;
1825 var->avl = (ar >> 12) & 1;
1826 var->l = (ar >> 13) & 1;
1827 var->db = (ar >> 14) & 1;
1828 var->g = (ar >> 15) & 1;
1829 var->unusable = (ar >> 16) & 1;
1832 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1834 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1837 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1840 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1843 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1850 ar = var->type & 15;
1851 ar |= (var->s & 1) << 4;
1852 ar |= (var->dpl & 3) << 5;
1853 ar |= (var->present & 1) << 7;
1854 ar |= (var->avl & 1) << 12;
1855 ar |= (var->l & 1) << 13;
1856 ar |= (var->db & 1) << 14;
1857 ar |= (var->g & 1) << 15;
1859 if (ar == 0) /* a 0 value means unusable */
1860 ar = AR_UNUSABLE_MASK;
1865 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1866 struct kvm_segment *var, int seg)
1868 struct vcpu_vmx *vmx = to_vmx(vcpu);
1869 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1872 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1873 vmx->rmode.tr.selector = var->selector;
1874 vmx->rmode.tr.base = var->base;
1875 vmx->rmode.tr.limit = var->limit;
1876 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1879 vmcs_writel(sf->base, var->base);
1880 vmcs_write32(sf->limit, var->limit);
1881 vmcs_write16(sf->selector, var->selector);
1882 if (vmx->rmode.vm86_active && var->s) {
1884 * Hack real-mode segments into vm86 compatibility.
1886 if (var->base == 0xffff0000 && var->selector == 0xf000)
1887 vmcs_writel(sf->base, 0xf0000);
1890 ar = vmx_segment_access_rights(var);
1893 * Fix the "Accessed" bit in AR field of segment registers for older
1895 * IA32 arch specifies that at the time of processor reset the
1896 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1897 * is setting it to 0 in the usedland code. This causes invalid guest
1898 * state vmexit when "unrestricted guest" mode is turned on.
1899 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1900 * tree. Newer qemu binaries with that qemu fix would not need this
1903 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1904 ar |= 0x1; /* Accessed */
1906 vmcs_write32(sf->ar_bytes, ar);
1909 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1911 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1913 *db = (ar >> 14) & 1;
1914 *l = (ar >> 13) & 1;
1917 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1919 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1920 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1923 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1925 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1926 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1929 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1931 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1932 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1935 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1937 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1938 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1941 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1943 struct kvm_segment var;
1946 vmx_get_segment(vcpu, &var, seg);
1947 ar = vmx_segment_access_rights(&var);
1949 if (var.base != (var.selector << 4))
1951 if (var.limit != 0xffff)
1959 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1961 struct kvm_segment cs;
1962 unsigned int cs_rpl;
1964 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1965 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1969 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1973 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1974 if (cs.dpl > cs_rpl)
1977 if (cs.dpl != cs_rpl)
1983 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1987 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1989 struct kvm_segment ss;
1990 unsigned int ss_rpl;
1992 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1993 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1997 if (ss.type != 3 && ss.type != 7)
2001 if (ss.dpl != ss_rpl) /* DPL != RPL */
2009 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2011 struct kvm_segment var;
2014 vmx_get_segment(vcpu, &var, seg);
2015 rpl = var.selector & SELECTOR_RPL_MASK;
2023 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2024 if (var.dpl < rpl) /* DPL < RPL */
2028 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2034 static bool tr_valid(struct kvm_vcpu *vcpu)
2036 struct kvm_segment tr;
2038 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2042 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2044 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2052 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2054 struct kvm_segment ldtr;
2056 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2060 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2070 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2072 struct kvm_segment cs, ss;
2074 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2075 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2077 return ((cs.selector & SELECTOR_RPL_MASK) ==
2078 (ss.selector & SELECTOR_RPL_MASK));
2082 * Check if guest state is valid. Returns true if valid, false if
2084 * We assume that registers are always usable
2086 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2088 /* real mode guest state checks */
2089 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2090 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2092 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2094 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2096 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2098 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2100 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2103 /* protected mode guest state checks */
2104 if (!cs_ss_rpl_check(vcpu))
2106 if (!code_segment_valid(vcpu))
2108 if (!stack_segment_valid(vcpu))
2110 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2112 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2114 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2116 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2118 if (!tr_valid(vcpu))
2120 if (!ldtr_valid(vcpu))
2124 * - Add checks on RIP
2125 * - Add checks on RFLAGS
2131 static int init_rmode_tss(struct kvm *kvm)
2133 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2138 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2141 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2142 r = kvm_write_guest_page(kvm, fn++, &data,
2143 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2146 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2149 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2153 r = kvm_write_guest_page(kvm, fn, &data,
2154 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2164 static int init_rmode_identity_map(struct kvm *kvm)
2167 pfn_t identity_map_pfn;
2172 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2173 printk(KERN_ERR "EPT: identity-mapping pagetable "
2174 "haven't been allocated!\n");
2177 if (likely(kvm->arch.ept_identity_pagetable_done))
2180 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2181 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2184 /* Set up identity-mapping pagetable for EPT in real mode */
2185 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2186 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2187 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2188 r = kvm_write_guest_page(kvm, identity_map_pfn,
2189 &tmp, i * sizeof(tmp), sizeof(tmp));
2193 kvm->arch.ept_identity_pagetable_done = true;
2199 static void seg_setup(int seg)
2201 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2204 vmcs_write16(sf->selector, 0);
2205 vmcs_writel(sf->base, 0);
2206 vmcs_write32(sf->limit, 0xffff);
2207 if (enable_unrestricted_guest) {
2209 if (seg == VCPU_SREG_CS)
2210 ar |= 0x08; /* code segment */
2214 vmcs_write32(sf->ar_bytes, ar);
2217 static int alloc_apic_access_page(struct kvm *kvm)
2219 struct kvm_userspace_memory_region kvm_userspace_mem;
2222 down_write(&kvm->slots_lock);
2223 if (kvm->arch.apic_access_page)
2225 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2226 kvm_userspace_mem.flags = 0;
2227 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2228 kvm_userspace_mem.memory_size = PAGE_SIZE;
2229 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2233 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2235 up_write(&kvm->slots_lock);
2239 static int alloc_identity_pagetable(struct kvm *kvm)
2241 struct kvm_userspace_memory_region kvm_userspace_mem;
2244 down_write(&kvm->slots_lock);
2245 if (kvm->arch.ept_identity_pagetable)
2247 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2248 kvm_userspace_mem.flags = 0;
2249 kvm_userspace_mem.guest_phys_addr =
2250 kvm->arch.ept_identity_map_addr;
2251 kvm_userspace_mem.memory_size = PAGE_SIZE;
2252 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2256 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2257 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2259 up_write(&kvm->slots_lock);
2263 static void allocate_vpid(struct vcpu_vmx *vmx)
2270 spin_lock(&vmx_vpid_lock);
2271 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2272 if (vpid < VMX_NR_VPIDS) {
2274 __set_bit(vpid, vmx_vpid_bitmap);
2276 spin_unlock(&vmx_vpid_lock);
2279 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2281 int f = sizeof(unsigned long);
2283 if (!cpu_has_vmx_msr_bitmap())
2287 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2288 * have the write-low and read-high bitmap offsets the wrong way round.
2289 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2291 if (msr <= 0x1fff) {
2292 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2293 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2294 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2296 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2297 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2301 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2304 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2305 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2309 * Sets up the vmcs for emulated real mode.
2311 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2313 u32 host_sysenter_cs, msr_low, msr_high;
2315 u64 host_pat, tsc_this, tsc_base;
2317 struct descriptor_table dt;
2319 unsigned long kvm_vmx_return;
2323 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2324 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2326 if (cpu_has_vmx_msr_bitmap())
2327 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2329 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2332 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2333 vmcs_config.pin_based_exec_ctrl);
2335 exec_control = vmcs_config.cpu_based_exec_ctrl;
2336 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2337 exec_control &= ~CPU_BASED_TPR_SHADOW;
2338 #ifdef CONFIG_X86_64
2339 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2340 CPU_BASED_CR8_LOAD_EXITING;
2344 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2345 CPU_BASED_CR3_LOAD_EXITING |
2346 CPU_BASED_INVLPG_EXITING;
2347 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2349 if (cpu_has_secondary_exec_ctrls()) {
2350 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2351 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2353 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2355 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2357 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2358 enable_unrestricted_guest = 0;
2360 if (!enable_unrestricted_guest)
2361 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2363 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2364 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2368 vmcs_write32(PLE_GAP, ple_gap);
2369 vmcs_write32(PLE_WINDOW, ple_window);
2372 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2373 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2374 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2376 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2377 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2378 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2380 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2381 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2382 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2383 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2384 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2385 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2386 #ifdef CONFIG_X86_64
2387 rdmsrl(MSR_FS_BASE, a);
2388 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2389 rdmsrl(MSR_GS_BASE, a);
2390 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2392 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2393 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2396 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2399 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2401 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2402 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2403 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2404 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2405 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2407 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2408 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2409 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2410 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2411 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2412 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2414 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2415 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2416 host_pat = msr_low | ((u64) msr_high << 32);
2417 vmcs_write64(HOST_IA32_PAT, host_pat);
2419 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2420 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2421 host_pat = msr_low | ((u64) msr_high << 32);
2422 /* Write the default value follow host pat */
2423 vmcs_write64(GUEST_IA32_PAT, host_pat);
2424 /* Keep arch.pat sync with GUEST_IA32_PAT */
2425 vmx->vcpu.arch.pat = host_pat;
2428 for (i = 0; i < NR_VMX_MSR; ++i) {
2429 u32 index = vmx_msr_index[i];
2430 u32 data_low, data_high;
2433 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2435 if (wrmsr_safe(index, data_low, data_high) < 0)
2437 vmx->guest_msrs[j].index = i;
2438 vmx->guest_msrs[j].data = 0;
2439 vmx->guest_msrs[j].mask = -1ull;
2443 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2445 /* 22.2.1, 20.8.1 */
2446 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2448 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2449 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2451 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2452 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2454 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2456 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2457 tsc_base = tsc_this;
2459 guest_write_tsc(0, tsc_base);
2464 static int init_rmode(struct kvm *kvm)
2466 if (!init_rmode_tss(kvm))
2468 if (!init_rmode_identity_map(kvm))
2473 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2475 struct vcpu_vmx *vmx = to_vmx(vcpu);
2479 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2480 down_read(&vcpu->kvm->slots_lock);
2481 if (!init_rmode(vmx->vcpu.kvm)) {
2486 vmx->rmode.vm86_active = 0;
2488 vmx->soft_vnmi_blocked = 0;
2490 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2491 kvm_set_cr8(&vmx->vcpu, 0);
2492 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2493 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2494 msr |= MSR_IA32_APICBASE_BSP;
2495 kvm_set_apic_base(&vmx->vcpu, msr);
2497 fx_init(&vmx->vcpu);
2499 seg_setup(VCPU_SREG_CS);
2501 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2502 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2504 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2505 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2506 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2508 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2509 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2512 seg_setup(VCPU_SREG_DS);
2513 seg_setup(VCPU_SREG_ES);
2514 seg_setup(VCPU_SREG_FS);
2515 seg_setup(VCPU_SREG_GS);
2516 seg_setup(VCPU_SREG_SS);
2518 vmcs_write16(GUEST_TR_SELECTOR, 0);
2519 vmcs_writel(GUEST_TR_BASE, 0);
2520 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2521 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2523 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2524 vmcs_writel(GUEST_LDTR_BASE, 0);
2525 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2526 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2528 vmcs_write32(GUEST_SYSENTER_CS, 0);
2529 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2530 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2532 vmcs_writel(GUEST_RFLAGS, 0x02);
2533 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2534 kvm_rip_write(vcpu, 0xfff0);
2536 kvm_rip_write(vcpu, 0);
2537 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2539 vmcs_writel(GUEST_DR7, 0x400);
2541 vmcs_writel(GUEST_GDTR_BASE, 0);
2542 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2544 vmcs_writel(GUEST_IDTR_BASE, 0);
2545 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2547 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2548 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2549 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2551 /* Special registers */
2552 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2556 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2558 if (cpu_has_vmx_tpr_shadow()) {
2559 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2560 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2561 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2562 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2563 vmcs_write32(TPR_THRESHOLD, 0);
2566 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2567 vmcs_write64(APIC_ACCESS_ADDR,
2568 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2571 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2573 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2574 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2575 vmx_set_cr4(&vmx->vcpu, 0);
2576 vmx_set_efer(&vmx->vcpu, 0);
2577 vmx_fpu_activate(&vmx->vcpu);
2578 update_exception_bitmap(&vmx->vcpu);
2580 vpid_sync_vcpu_all(vmx);
2584 /* HACK: Don't enable emulation on guest boot/reset */
2585 vmx->emulation_required = 0;
2588 up_read(&vcpu->kvm->slots_lock);
2592 static void enable_irq_window(struct kvm_vcpu *vcpu)
2594 u32 cpu_based_vm_exec_control;
2596 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2597 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2598 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2601 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2603 u32 cpu_based_vm_exec_control;
2605 if (!cpu_has_virtual_nmis()) {
2606 enable_irq_window(vcpu);
2610 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2611 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2612 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2615 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2617 struct vcpu_vmx *vmx = to_vmx(vcpu);
2619 int irq = vcpu->arch.interrupt.nr;
2621 trace_kvm_inj_virq(irq);
2623 ++vcpu->stat.irq_injections;
2624 if (vmx->rmode.vm86_active) {
2625 vmx->rmode.irq.pending = true;
2626 vmx->rmode.irq.vector = irq;
2627 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2628 if (vcpu->arch.interrupt.soft)
2629 vmx->rmode.irq.rip +=
2630 vmx->vcpu.arch.event_exit_inst_len;
2631 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2632 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2633 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2634 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2637 intr = irq | INTR_INFO_VALID_MASK;
2638 if (vcpu->arch.interrupt.soft) {
2639 intr |= INTR_TYPE_SOFT_INTR;
2640 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2641 vmx->vcpu.arch.event_exit_inst_len);
2643 intr |= INTR_TYPE_EXT_INTR;
2644 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2647 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2649 struct vcpu_vmx *vmx = to_vmx(vcpu);
2651 if (!cpu_has_virtual_nmis()) {
2653 * Tracking the NMI-blocked state in software is built upon
2654 * finding the next open IRQ window. This, in turn, depends on
2655 * well-behaving guests: They have to keep IRQs disabled at
2656 * least as long as the NMI handler runs. Otherwise we may
2657 * cause NMI nesting, maybe breaking the guest. But as this is
2658 * highly unlikely, we can live with the residual risk.
2660 vmx->soft_vnmi_blocked = 1;
2661 vmx->vnmi_blocked_time = 0;
2664 ++vcpu->stat.nmi_injections;
2665 if (vmx->rmode.vm86_active) {
2666 vmx->rmode.irq.pending = true;
2667 vmx->rmode.irq.vector = NMI_VECTOR;
2668 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2669 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2670 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2671 INTR_INFO_VALID_MASK);
2672 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2673 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2676 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2677 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2680 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2682 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2685 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2686 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2687 GUEST_INTR_STATE_NMI));
2690 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2692 if (!cpu_has_virtual_nmis())
2693 return to_vmx(vcpu)->soft_vnmi_blocked;
2695 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2696 GUEST_INTR_STATE_NMI);
2699 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2701 struct vcpu_vmx *vmx = to_vmx(vcpu);
2703 if (!cpu_has_virtual_nmis()) {
2704 if (vmx->soft_vnmi_blocked != masked) {
2705 vmx->soft_vnmi_blocked = masked;
2706 vmx->vnmi_blocked_time = 0;
2710 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2711 GUEST_INTR_STATE_NMI);
2713 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2714 GUEST_INTR_STATE_NMI);
2718 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2720 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2721 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2722 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2725 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2728 struct kvm_userspace_memory_region tss_mem = {
2729 .slot = TSS_PRIVATE_MEMSLOT,
2730 .guest_phys_addr = addr,
2731 .memory_size = PAGE_SIZE * 3,
2735 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2738 kvm->arch.tss_addr = addr;
2742 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2743 int vec, u32 err_code)
2746 * Instruction with address size override prefix opcode 0x67
2747 * Cause the #SS fault with 0 error code in VM86 mode.
2749 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2750 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2753 * Forward all other exceptions that are valid in real mode.
2754 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2755 * the required debugging infrastructure rework.
2759 if (vcpu->guest_debug &
2760 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2762 kvm_queue_exception(vcpu, vec);
2765 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2776 kvm_queue_exception(vcpu, vec);
2783 * Trigger machine check on the host. We assume all the MSRs are already set up
2784 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2785 * We pass a fake environment to the machine check handler because we want
2786 * the guest to be always treated like user space, no matter what context
2787 * it used internally.
2789 static void kvm_machine_check(void)
2791 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2792 struct pt_regs regs = {
2793 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2794 .flags = X86_EFLAGS_IF,
2797 do_machine_check(®s, 0);
2801 static int handle_machine_check(struct kvm_vcpu *vcpu)
2803 /* already handled by vcpu_run */
2807 static int handle_exception(struct kvm_vcpu *vcpu)
2809 struct vcpu_vmx *vmx = to_vmx(vcpu);
2810 struct kvm_run *kvm_run = vcpu->run;
2811 u32 intr_info, ex_no, error_code;
2812 unsigned long cr2, rip, dr6;
2814 enum emulation_result er;
2816 vect_info = vmx->idt_vectoring_info;
2817 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2819 if (is_machine_check(intr_info))
2820 return handle_machine_check(vcpu);
2822 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2823 !is_page_fault(intr_info)) {
2824 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2825 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2826 vcpu->run->internal.ndata = 2;
2827 vcpu->run->internal.data[0] = vect_info;
2828 vcpu->run->internal.data[1] = intr_info;
2832 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2833 return 1; /* already handled by vmx_vcpu_run() */
2835 if (is_no_device(intr_info)) {
2836 vmx_fpu_activate(vcpu);
2840 if (is_invalid_opcode(intr_info)) {
2841 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2842 if (er != EMULATE_DONE)
2843 kvm_queue_exception(vcpu, UD_VECTOR);
2848 rip = kvm_rip_read(vcpu);
2849 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2850 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2851 if (is_page_fault(intr_info)) {
2852 /* EPT won't cause page fault directly */
2855 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2856 trace_kvm_page_fault(cr2, error_code);
2858 if (kvm_event_needs_reinjection(vcpu))
2859 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2860 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2863 if (vmx->rmode.vm86_active &&
2864 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2866 if (vcpu->arch.halt_request) {
2867 vcpu->arch.halt_request = 0;
2868 return kvm_emulate_halt(vcpu);
2873 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2876 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2877 if (!(vcpu->guest_debug &
2878 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2879 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2880 kvm_queue_exception(vcpu, DB_VECTOR);
2883 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2884 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2887 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2888 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2889 kvm_run->debug.arch.exception = ex_no;
2892 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2893 kvm_run->ex.exception = ex_no;
2894 kvm_run->ex.error_code = error_code;
2900 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2902 ++vcpu->stat.irq_exits;
2906 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2908 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2912 static int handle_io(struct kvm_vcpu *vcpu)
2914 unsigned long exit_qualification;
2915 int size, in, string;
2918 ++vcpu->stat.io_exits;
2919 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2920 string = (exit_qualification & 16) != 0;
2923 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2928 size = (exit_qualification & 7) + 1;
2929 in = (exit_qualification & 8) != 0;
2930 port = exit_qualification >> 16;
2932 skip_emulated_instruction(vcpu);
2933 return kvm_emulate_pio(vcpu, in, size, port);
2937 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2940 * Patch in the VMCALL instruction:
2942 hypercall[0] = 0x0f;
2943 hypercall[1] = 0x01;
2944 hypercall[2] = 0xc1;
2947 static int handle_cr(struct kvm_vcpu *vcpu)
2949 unsigned long exit_qualification, val;
2953 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2954 cr = exit_qualification & 15;
2955 reg = (exit_qualification >> 8) & 15;
2956 switch ((exit_qualification >> 4) & 3) {
2957 case 0: /* mov to cr */
2958 val = kvm_register_read(vcpu, reg);
2959 trace_kvm_cr_write(cr, val);
2962 kvm_set_cr0(vcpu, val);
2963 skip_emulated_instruction(vcpu);
2966 kvm_set_cr3(vcpu, val);
2967 skip_emulated_instruction(vcpu);
2970 kvm_set_cr4(vcpu, val);
2971 skip_emulated_instruction(vcpu);
2974 u8 cr8_prev = kvm_get_cr8(vcpu);
2975 u8 cr8 = kvm_register_read(vcpu, reg);
2976 kvm_set_cr8(vcpu, cr8);
2977 skip_emulated_instruction(vcpu);
2978 if (irqchip_in_kernel(vcpu->kvm))
2980 if (cr8_prev <= cr8)
2982 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2988 vmx_fpu_deactivate(vcpu);
2989 vcpu->arch.cr0 &= ~X86_CR0_TS;
2990 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2991 vmx_fpu_activate(vcpu);
2992 skip_emulated_instruction(vcpu);
2994 case 1: /*mov from cr*/
2997 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2998 trace_kvm_cr_read(cr, vcpu->arch.cr3);
2999 skip_emulated_instruction(vcpu);
3002 val = kvm_get_cr8(vcpu);
3003 kvm_register_write(vcpu, reg, val);
3004 trace_kvm_cr_read(cr, val);
3005 skip_emulated_instruction(vcpu);
3010 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
3012 skip_emulated_instruction(vcpu);
3017 vcpu->run->exit_reason = 0;
3018 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3019 (int)(exit_qualification >> 4) & 3, cr);
3023 static int handle_dr(struct kvm_vcpu *vcpu)
3025 unsigned long exit_qualification;
3029 if (!kvm_require_cpl(vcpu, 0))
3031 dr = vmcs_readl(GUEST_DR7);
3034 * As the vm-exit takes precedence over the debug trap, we
3035 * need to emulate the latter, either for the host or the
3036 * guest debugging itself.
3038 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3039 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3040 vcpu->run->debug.arch.dr7 = dr;
3041 vcpu->run->debug.arch.pc =
3042 vmcs_readl(GUEST_CS_BASE) +
3043 vmcs_readl(GUEST_RIP);
3044 vcpu->run->debug.arch.exception = DB_VECTOR;
3045 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3048 vcpu->arch.dr7 &= ~DR7_GD;
3049 vcpu->arch.dr6 |= DR6_BD;
3050 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3051 kvm_queue_exception(vcpu, DB_VECTOR);
3056 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3057 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3058 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3059 if (exit_qualification & TYPE_MOV_FROM_DR) {
3062 val = vcpu->arch.db[dr];
3065 val = vcpu->arch.dr6;
3068 val = vcpu->arch.dr7;
3073 kvm_register_write(vcpu, reg, val);
3075 val = vcpu->arch.regs[reg];
3078 vcpu->arch.db[dr] = val;
3079 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3080 vcpu->arch.eff_db[dr] = val;
3083 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
3084 kvm_queue_exception(vcpu, UD_VECTOR);
3087 if (val & 0xffffffff00000000ULL) {
3088 kvm_queue_exception(vcpu, GP_VECTOR);
3091 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3094 if (val & 0xffffffff00000000ULL) {
3095 kvm_queue_exception(vcpu, GP_VECTOR);
3098 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3099 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3100 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3101 vcpu->arch.switch_db_regs =
3102 (val & DR7_BP_EN_MASK);
3107 skip_emulated_instruction(vcpu);
3111 static int handle_cpuid(struct kvm_vcpu *vcpu)
3113 kvm_emulate_cpuid(vcpu);
3117 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3119 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3122 if (vmx_get_msr(vcpu, ecx, &data)) {
3123 kvm_inject_gp(vcpu, 0);
3127 trace_kvm_msr_read(ecx, data);
3129 /* FIXME: handling of bits 32:63 of rax, rdx */
3130 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3131 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3132 skip_emulated_instruction(vcpu);
3136 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3138 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3139 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3140 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3142 trace_kvm_msr_write(ecx, data);
3144 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3145 kvm_inject_gp(vcpu, 0);
3149 skip_emulated_instruction(vcpu);
3153 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3158 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3160 u32 cpu_based_vm_exec_control;
3162 /* clear pending irq */
3163 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3164 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3165 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3167 ++vcpu->stat.irq_window_exits;
3170 * If the user space waits to inject interrupts, exit as soon as
3173 if (!irqchip_in_kernel(vcpu->kvm) &&
3174 vcpu->run->request_interrupt_window &&
3175 !kvm_cpu_has_interrupt(vcpu)) {
3176 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3182 static int handle_halt(struct kvm_vcpu *vcpu)
3184 skip_emulated_instruction(vcpu);
3185 return kvm_emulate_halt(vcpu);
3188 static int handle_vmcall(struct kvm_vcpu *vcpu)
3190 skip_emulated_instruction(vcpu);
3191 kvm_emulate_hypercall(vcpu);
3195 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3197 kvm_queue_exception(vcpu, UD_VECTOR);
3201 static int handle_invlpg(struct kvm_vcpu *vcpu)
3203 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3205 kvm_mmu_invlpg(vcpu, exit_qualification);
3206 skip_emulated_instruction(vcpu);
3210 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3212 skip_emulated_instruction(vcpu);
3213 /* TODO: Add support for VT-d/pass-through device */
3217 static int handle_apic_access(struct kvm_vcpu *vcpu)
3219 unsigned long exit_qualification;
3220 enum emulation_result er;
3221 unsigned long offset;
3223 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3224 offset = exit_qualification & 0xffful;
3226 er = emulate_instruction(vcpu, 0, 0, 0);
3228 if (er != EMULATE_DONE) {
3230 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3237 static int handle_task_switch(struct kvm_vcpu *vcpu)
3239 struct vcpu_vmx *vmx = to_vmx(vcpu);
3240 unsigned long exit_qualification;
3242 int reason, type, idt_v;
3244 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3245 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3247 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3249 reason = (u32)exit_qualification >> 30;
3250 if (reason == TASK_SWITCH_GATE && idt_v) {
3252 case INTR_TYPE_NMI_INTR:
3253 vcpu->arch.nmi_injected = false;
3254 if (cpu_has_virtual_nmis())
3255 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3256 GUEST_INTR_STATE_NMI);
3258 case INTR_TYPE_EXT_INTR:
3259 case INTR_TYPE_SOFT_INTR:
3260 kvm_clear_interrupt_queue(vcpu);
3262 case INTR_TYPE_HARD_EXCEPTION:
3263 case INTR_TYPE_SOFT_EXCEPTION:
3264 kvm_clear_exception_queue(vcpu);
3270 tss_selector = exit_qualification;
3272 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3273 type != INTR_TYPE_EXT_INTR &&
3274 type != INTR_TYPE_NMI_INTR))
3275 skip_emulated_instruction(vcpu);
3277 if (!kvm_task_switch(vcpu, tss_selector, reason))
3280 /* clear all local breakpoint enable flags */
3281 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3284 * TODO: What about debug traps on tss switch?
3285 * Are we supposed to inject them and update dr6?
3291 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3293 unsigned long exit_qualification;
3297 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3299 if (exit_qualification & (1 << 6)) {
3300 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3304 gla_validity = (exit_qualification >> 7) & 0x3;
3305 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3306 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3307 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3308 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3309 vmcs_readl(GUEST_LINEAR_ADDRESS));
3310 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3311 (long unsigned int)exit_qualification);
3312 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3313 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3317 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3318 trace_kvm_page_fault(gpa, exit_qualification);
3319 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3322 static u64 ept_rsvd_mask(u64 spte, int level)
3327 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3328 mask |= (1ULL << i);
3331 /* bits 7:3 reserved */
3333 else if (level == 2) {
3334 if (spte & (1ULL << 7))
3335 /* 2MB ref, bits 20:12 reserved */
3338 /* bits 6:3 reserved */
3345 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3348 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3350 /* 010b (write-only) */
3351 WARN_ON((spte & 0x7) == 0x2);
3353 /* 110b (write/execute) */
3354 WARN_ON((spte & 0x7) == 0x6);
3356 /* 100b (execute-only) and value not supported by logical processor */
3357 if (!cpu_has_vmx_ept_execute_only())
3358 WARN_ON((spte & 0x7) == 0x4);
3362 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3364 if (rsvd_bits != 0) {
3365 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3366 __func__, rsvd_bits);
3370 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3371 u64 ept_mem_type = (spte & 0x38) >> 3;
3373 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3374 ept_mem_type == 7) {
3375 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3376 __func__, ept_mem_type);
3383 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3389 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3391 printk(KERN_ERR "EPT: Misconfiguration.\n");
3392 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3394 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3396 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3397 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3399 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3400 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3405 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3407 u32 cpu_based_vm_exec_control;
3409 /* clear pending NMI */
3410 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3411 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3412 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3413 ++vcpu->stat.nmi_window_exits;
3418 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3420 struct vcpu_vmx *vmx = to_vmx(vcpu);
3421 enum emulation_result err = EMULATE_DONE;
3424 while (!guest_state_valid(vcpu)) {
3425 err = emulate_instruction(vcpu, 0, 0, 0);
3427 if (err == EMULATE_DO_MMIO) {
3432 if (err != EMULATE_DONE) {
3433 kvm_report_emulation_failure(vcpu, "emulation failure");
3434 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3435 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3436 vcpu->run->internal.ndata = 0;
3441 if (signal_pending(current))
3447 vmx->emulation_required = 0;
3453 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3454 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3456 static int handle_pause(struct kvm_vcpu *vcpu)
3458 skip_emulated_instruction(vcpu);
3459 kvm_vcpu_on_spin(vcpu);
3464 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3466 kvm_queue_exception(vcpu, UD_VECTOR);
3471 * The exit handlers return 1 if the exit was handled fully and guest execution
3472 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3473 * to be done to userspace and return 0.
3475 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3476 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3477 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3478 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3479 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3480 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3481 [EXIT_REASON_CR_ACCESS] = handle_cr,
3482 [EXIT_REASON_DR_ACCESS] = handle_dr,
3483 [EXIT_REASON_CPUID] = handle_cpuid,
3484 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3485 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3486 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3487 [EXIT_REASON_HLT] = handle_halt,
3488 [EXIT_REASON_INVLPG] = handle_invlpg,
3489 [EXIT_REASON_VMCALL] = handle_vmcall,
3490 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3491 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3492 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3493 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3494 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3495 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3496 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3497 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3498 [EXIT_REASON_VMON] = handle_vmx_insn,
3499 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3500 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3501 [EXIT_REASON_WBINVD] = handle_wbinvd,
3502 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3503 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3504 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3505 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3506 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3507 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3508 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3511 static const int kvm_vmx_max_exit_handlers =
3512 ARRAY_SIZE(kvm_vmx_exit_handlers);
3515 * The guest has exited. See if we can fix it or if we need userspace
3518 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3520 struct vcpu_vmx *vmx = to_vmx(vcpu);
3521 u32 exit_reason = vmx->exit_reason;
3522 u32 vectoring_info = vmx->idt_vectoring_info;
3524 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3526 /* If guest state is invalid, start emulating */
3527 if (vmx->emulation_required && emulate_invalid_guest_state)
3528 return handle_invalid_guest_state(vcpu);
3530 /* Access CR3 don't cause VMExit in paging mode, so we need
3531 * to sync with guest real CR3. */
3532 if (enable_ept && is_paging(vcpu))
3533 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3535 if (unlikely(vmx->fail)) {
3536 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3537 vcpu->run->fail_entry.hardware_entry_failure_reason
3538 = vmcs_read32(VM_INSTRUCTION_ERROR);
3542 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3543 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3544 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3545 exit_reason != EXIT_REASON_TASK_SWITCH))
3546 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3547 "(0x%x) and exit reason is 0x%x\n",
3548 __func__, vectoring_info, exit_reason);
3550 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3551 if (vmx_interrupt_allowed(vcpu)) {
3552 vmx->soft_vnmi_blocked = 0;
3553 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3554 vcpu->arch.nmi_pending) {
3556 * This CPU don't support us in finding the end of an
3557 * NMI-blocked window if the guest runs with IRQs
3558 * disabled. So we pull the trigger after 1 s of
3559 * futile waiting, but inform the user about this.
3561 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3562 "state on VCPU %d after 1 s timeout\n",
3563 __func__, vcpu->vcpu_id);
3564 vmx->soft_vnmi_blocked = 0;
3568 if (exit_reason < kvm_vmx_max_exit_handlers
3569 && kvm_vmx_exit_handlers[exit_reason])
3570 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3572 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3573 vcpu->run->hw.hardware_exit_reason = exit_reason;
3578 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3580 if (irr == -1 || tpr < irr) {
3581 vmcs_write32(TPR_THRESHOLD, 0);
3585 vmcs_write32(TPR_THRESHOLD, irr);
3588 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3591 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3595 bool idtv_info_valid;
3597 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3599 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3601 /* Handle machine checks before interrupts are enabled */
3602 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3603 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3604 && is_machine_check(exit_intr_info)))
3605 kvm_machine_check();
3607 /* We need to handle NMIs before interrupts are enabled */
3608 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3609 (exit_intr_info & INTR_INFO_VALID_MASK))
3612 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3614 if (cpu_has_virtual_nmis()) {
3615 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3616 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3618 * SDM 3: 27.7.1.2 (September 2008)
3619 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3620 * a guest IRET fault.
3621 * SDM 3: 23.2.2 (September 2008)
3622 * Bit 12 is undefined in any of the following cases:
3623 * If the VM exit sets the valid bit in the IDT-vectoring
3624 * information field.
3625 * If the VM exit is due to a double fault.
3627 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3628 vector != DF_VECTOR && !idtv_info_valid)
3629 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3630 GUEST_INTR_STATE_NMI);
3631 } else if (unlikely(vmx->soft_vnmi_blocked))
3632 vmx->vnmi_blocked_time +=
3633 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3635 vmx->vcpu.arch.nmi_injected = false;
3636 kvm_clear_exception_queue(&vmx->vcpu);
3637 kvm_clear_interrupt_queue(&vmx->vcpu);
3639 if (!idtv_info_valid)
3642 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3643 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3646 case INTR_TYPE_NMI_INTR:
3647 vmx->vcpu.arch.nmi_injected = true;
3649 * SDM 3: 27.7.1.2 (September 2008)
3650 * Clear bit "block by NMI" before VM entry if a NMI
3653 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3654 GUEST_INTR_STATE_NMI);
3656 case INTR_TYPE_SOFT_EXCEPTION:
3657 vmx->vcpu.arch.event_exit_inst_len =
3658 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3660 case INTR_TYPE_HARD_EXCEPTION:
3661 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3662 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3663 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3665 kvm_queue_exception(&vmx->vcpu, vector);
3667 case INTR_TYPE_SOFT_INTR:
3668 vmx->vcpu.arch.event_exit_inst_len =
3669 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3671 case INTR_TYPE_EXT_INTR:
3672 kvm_queue_interrupt(&vmx->vcpu, vector,
3673 type == INTR_TYPE_SOFT_INTR);
3681 * Failure to inject an interrupt should give us the information
3682 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3683 * when fetching the interrupt redirection bitmap in the real-mode
3684 * tss, this doesn't happen. So we do it ourselves.
3686 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3688 vmx->rmode.irq.pending = 0;
3689 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3691 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3692 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3693 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3694 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3697 vmx->idt_vectoring_info =
3698 VECTORING_INFO_VALID_MASK
3699 | INTR_TYPE_EXT_INTR
3700 | vmx->rmode.irq.vector;
3703 #ifdef CONFIG_X86_64
3711 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3713 struct vcpu_vmx *vmx = to_vmx(vcpu);
3715 /* Record the guest's net vcpu time for enforced NMI injections. */
3716 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3717 vmx->entry_time = ktime_get();
3719 /* Don't enter VMX if guest state is invalid, let the exit handler
3720 start emulation until we arrive back to a valid state */
3721 if (vmx->emulation_required && emulate_invalid_guest_state)
3724 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3725 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3726 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3727 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3729 /* When single-stepping over STI and MOV SS, we must clear the
3730 * corresponding interruptibility bits in the guest state. Otherwise
3731 * vmentry fails as it then expects bit 14 (BS) in pending debug
3732 * exceptions being set, but that's not correct for the guest debugging
3734 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3735 vmx_set_interrupt_shadow(vcpu, 0);
3738 * Loading guest fpu may have cleared host cr0.ts
3740 vmcs_writel(HOST_CR0, read_cr0());
3742 if (vcpu->arch.switch_db_regs)
3743 set_debugreg(vcpu->arch.dr6, 6);
3746 /* Store host registers */
3747 "push %%"R"dx; push %%"R"bp;"
3749 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3751 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3752 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3754 /* Reload cr2 if changed */
3755 "mov %c[cr2](%0), %%"R"ax \n\t"
3756 "mov %%cr2, %%"R"dx \n\t"
3757 "cmp %%"R"ax, %%"R"dx \n\t"
3759 "mov %%"R"ax, %%cr2 \n\t"
3761 /* Check if vmlaunch of vmresume is needed */
3762 "cmpl $0, %c[launched](%0) \n\t"
3763 /* Load guest registers. Don't clobber flags. */
3764 "mov %c[rax](%0), %%"R"ax \n\t"
3765 "mov %c[rbx](%0), %%"R"bx \n\t"
3766 "mov %c[rdx](%0), %%"R"dx \n\t"
3767 "mov %c[rsi](%0), %%"R"si \n\t"
3768 "mov %c[rdi](%0), %%"R"di \n\t"
3769 "mov %c[rbp](%0), %%"R"bp \n\t"
3770 #ifdef CONFIG_X86_64
3771 "mov %c[r8](%0), %%r8 \n\t"
3772 "mov %c[r9](%0), %%r9 \n\t"
3773 "mov %c[r10](%0), %%r10 \n\t"
3774 "mov %c[r11](%0), %%r11 \n\t"
3775 "mov %c[r12](%0), %%r12 \n\t"
3776 "mov %c[r13](%0), %%r13 \n\t"
3777 "mov %c[r14](%0), %%r14 \n\t"
3778 "mov %c[r15](%0), %%r15 \n\t"
3780 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3782 /* Enter guest mode */
3783 "jne .Llaunched \n\t"
3784 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3785 "jmp .Lkvm_vmx_return \n\t"
3786 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3787 ".Lkvm_vmx_return: "
3788 /* Save guest registers, load host registers, keep flags */
3789 "xchg %0, (%%"R"sp) \n\t"
3790 "mov %%"R"ax, %c[rax](%0) \n\t"
3791 "mov %%"R"bx, %c[rbx](%0) \n\t"
3792 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3793 "mov %%"R"dx, %c[rdx](%0) \n\t"
3794 "mov %%"R"si, %c[rsi](%0) \n\t"
3795 "mov %%"R"di, %c[rdi](%0) \n\t"
3796 "mov %%"R"bp, %c[rbp](%0) \n\t"
3797 #ifdef CONFIG_X86_64
3798 "mov %%r8, %c[r8](%0) \n\t"
3799 "mov %%r9, %c[r9](%0) \n\t"
3800 "mov %%r10, %c[r10](%0) \n\t"
3801 "mov %%r11, %c[r11](%0) \n\t"
3802 "mov %%r12, %c[r12](%0) \n\t"
3803 "mov %%r13, %c[r13](%0) \n\t"
3804 "mov %%r14, %c[r14](%0) \n\t"
3805 "mov %%r15, %c[r15](%0) \n\t"
3807 "mov %%cr2, %%"R"ax \n\t"
3808 "mov %%"R"ax, %c[cr2](%0) \n\t"
3810 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3811 "setbe %c[fail](%0) \n\t"
3812 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3813 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3814 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3815 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3816 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3817 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3818 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3819 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3820 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3821 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3822 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3823 #ifdef CONFIG_X86_64
3824 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3825 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3826 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3827 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3828 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3829 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3830 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3831 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3833 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3835 , R"bx", R"di", R"si"
3836 #ifdef CONFIG_X86_64
3837 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3841 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3842 | (1 << VCPU_EXREG_PDPTR));
3843 vcpu->arch.regs_dirty = 0;
3845 if (vcpu->arch.switch_db_regs)
3846 get_debugreg(vcpu->arch.dr6, 6);
3848 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3849 if (vmx->rmode.irq.pending)
3850 fixup_rmode_irq(vmx);
3852 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3855 vmx_complete_interrupts(vmx);
3861 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3863 struct vcpu_vmx *vmx = to_vmx(vcpu);
3867 free_vmcs(vmx->vmcs);
3872 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3874 struct vcpu_vmx *vmx = to_vmx(vcpu);
3876 spin_lock(&vmx_vpid_lock);
3878 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3879 spin_unlock(&vmx_vpid_lock);
3880 vmx_free_vmcs(vcpu);
3881 kfree(vmx->guest_msrs);
3882 kvm_vcpu_uninit(vcpu);
3883 kmem_cache_free(kvm_vcpu_cache, vmx);
3886 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3889 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3893 return ERR_PTR(-ENOMEM);
3897 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3901 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3902 if (!vmx->guest_msrs) {
3907 vmx->vmcs = alloc_vmcs();
3911 vmcs_clear(vmx->vmcs);
3914 vmx_vcpu_load(&vmx->vcpu, cpu);
3915 err = vmx_vcpu_setup(vmx);
3916 vmx_vcpu_put(&vmx->vcpu);
3920 if (vm_need_virtualize_apic_accesses(kvm))
3921 if (alloc_apic_access_page(kvm) != 0)
3925 if (!kvm->arch.ept_identity_map_addr)
3926 kvm->arch.ept_identity_map_addr =
3927 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3928 if (alloc_identity_pagetable(kvm) != 0)
3935 free_vmcs(vmx->vmcs);
3937 kfree(vmx->guest_msrs);
3939 kvm_vcpu_uninit(&vmx->vcpu);
3941 kmem_cache_free(kvm_vcpu_cache, vmx);
3942 return ERR_PTR(err);
3945 static void __init vmx_check_processor_compat(void *rtn)
3947 struct vmcs_config vmcs_conf;
3950 if (setup_vmcs_config(&vmcs_conf) < 0)
3952 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3953 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3954 smp_processor_id());
3959 static int get_ept_level(void)
3961 return VMX_EPT_DEFAULT_GAW + 1;
3964 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3968 /* For VT-d and EPT combination
3969 * 1. MMIO: always map as UC
3971 * a. VT-d without snooping control feature: can't guarantee the
3972 * result, try to trust guest.
3973 * b. VT-d with snooping control feature: snooping control feature of
3974 * VT-d engine can guarantee the cache correctness. Just set it
3975 * to WB to keep consistent with host. So the same as item 3.
3976 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3977 * consistent with host MTRR
3980 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3981 else if (vcpu->kvm->arch.iommu_domain &&
3982 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3983 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3984 VMX_EPT_MT_EPTE_SHIFT;
3986 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3992 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3993 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3994 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3995 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3996 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3997 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3998 { EXIT_REASON_CR_ACCESS, "cr_access" },
3999 { EXIT_REASON_DR_ACCESS, "dr_access" },
4000 { EXIT_REASON_CPUID, "cpuid" },
4001 { EXIT_REASON_MSR_READ, "rdmsr" },
4002 { EXIT_REASON_MSR_WRITE, "wrmsr" },
4003 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
4004 { EXIT_REASON_HLT, "halt" },
4005 { EXIT_REASON_INVLPG, "invlpg" },
4006 { EXIT_REASON_VMCALL, "hypercall" },
4007 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
4008 { EXIT_REASON_APIC_ACCESS, "apic_access" },
4009 { EXIT_REASON_WBINVD, "wbinvd" },
4010 { EXIT_REASON_TASK_SWITCH, "task_switch" },
4011 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
4015 static bool vmx_gb_page_enable(void)
4020 static inline u32 bit(int bitno)
4022 return 1 << (bitno & 31);
4025 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4027 struct kvm_cpuid_entry2 *best;
4028 struct vcpu_vmx *vmx = to_vmx(vcpu);
4031 vmx->rdtscp_enabled = false;
4032 if (vmx_rdtscp_supported()) {
4033 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4034 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4035 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4036 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4037 vmx->rdtscp_enabled = true;
4039 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4040 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4047 static struct kvm_x86_ops vmx_x86_ops = {
4048 .cpu_has_kvm_support = cpu_has_kvm_support,
4049 .disabled_by_bios = vmx_disabled_by_bios,
4050 .hardware_setup = hardware_setup,
4051 .hardware_unsetup = hardware_unsetup,
4052 .check_processor_compatibility = vmx_check_processor_compat,
4053 .hardware_enable = hardware_enable,
4054 .hardware_disable = hardware_disable,
4055 .cpu_has_accelerated_tpr = report_flexpriority,
4057 .vcpu_create = vmx_create_vcpu,
4058 .vcpu_free = vmx_free_vcpu,
4059 .vcpu_reset = vmx_vcpu_reset,
4061 .prepare_guest_switch = vmx_save_host_state,
4062 .vcpu_load = vmx_vcpu_load,
4063 .vcpu_put = vmx_vcpu_put,
4065 .set_guest_debug = set_guest_debug,
4066 .get_msr = vmx_get_msr,
4067 .set_msr = vmx_set_msr,
4068 .get_segment_base = vmx_get_segment_base,
4069 .get_segment = vmx_get_segment,
4070 .set_segment = vmx_set_segment,
4071 .get_cpl = vmx_get_cpl,
4072 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4073 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4074 .set_cr0 = vmx_set_cr0,
4075 .set_cr3 = vmx_set_cr3,
4076 .set_cr4 = vmx_set_cr4,
4077 .set_efer = vmx_set_efer,
4078 .get_idt = vmx_get_idt,
4079 .set_idt = vmx_set_idt,
4080 .get_gdt = vmx_get_gdt,
4081 .set_gdt = vmx_set_gdt,
4082 .cache_reg = vmx_cache_reg,
4083 .get_rflags = vmx_get_rflags,
4084 .set_rflags = vmx_set_rflags,
4086 .tlb_flush = vmx_flush_tlb,
4088 .run = vmx_vcpu_run,
4089 .handle_exit = vmx_handle_exit,
4090 .skip_emulated_instruction = skip_emulated_instruction,
4091 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4092 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4093 .patch_hypercall = vmx_patch_hypercall,
4094 .set_irq = vmx_inject_irq,
4095 .set_nmi = vmx_inject_nmi,
4096 .queue_exception = vmx_queue_exception,
4097 .interrupt_allowed = vmx_interrupt_allowed,
4098 .nmi_allowed = vmx_nmi_allowed,
4099 .get_nmi_mask = vmx_get_nmi_mask,
4100 .set_nmi_mask = vmx_set_nmi_mask,
4101 .enable_nmi_window = enable_nmi_window,
4102 .enable_irq_window = enable_irq_window,
4103 .update_cr8_intercept = update_cr8_intercept,
4105 .set_tss_addr = vmx_set_tss_addr,
4106 .get_tdp_level = get_ept_level,
4107 .get_mt_mask = vmx_get_mt_mask,
4109 .exit_reasons_str = vmx_exit_reasons_str,
4110 .gb_page_enable = vmx_gb_page_enable,
4112 .cpuid_update = vmx_cpuid_update,
4114 .rdtscp_supported = vmx_rdtscp_supported,
4117 static int __init vmx_init(void)
4121 rdmsrl_safe(MSR_EFER, &host_efer);
4123 for (i = 0; i < NR_VMX_MSR; ++i)
4124 kvm_define_shared_msr(i, vmx_msr_index[i]);
4126 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4127 if (!vmx_io_bitmap_a)
4130 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4131 if (!vmx_io_bitmap_b) {
4136 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4137 if (!vmx_msr_bitmap_legacy) {
4142 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4143 if (!vmx_msr_bitmap_longmode) {
4149 * Allow direct access to the PC debug port (it is often used for I/O
4150 * delays, but the vmexits simply slow things down).
4152 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4153 clear_bit(0x80, vmx_io_bitmap_a);
4155 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4157 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4158 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4160 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4162 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4166 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4167 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4168 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4169 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4170 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4171 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4174 bypass_guest_pf = 0;
4175 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4176 VMX_EPT_WRITABLE_MASK);
4177 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4178 VMX_EPT_EXECUTABLE_MASK);
4183 if (bypass_guest_pf)
4184 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4189 free_page((unsigned long)vmx_msr_bitmap_longmode);
4191 free_page((unsigned long)vmx_msr_bitmap_legacy);
4193 free_page((unsigned long)vmx_io_bitmap_b);
4195 free_page((unsigned long)vmx_io_bitmap_a);
4199 static void __exit vmx_exit(void)
4201 free_page((unsigned long)vmx_msr_bitmap_legacy);
4202 free_page((unsigned long)vmx_msr_bitmap_longmode);
4203 free_page((unsigned long)vmx_io_bitmap_b);
4204 free_page((unsigned long)vmx_io_bitmap_a);
4209 module_init(vmx_init)
4210 module_exit(vmx_exit)