arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/frame.h>
  17 #include <linux/highmem.h>
  18 #include <linux/hrtimer.h>
  19 #include <linux/kernel.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/mm.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30
  31 #include <asm/apic.h>
  32 #include <asm/asm.h>
  33 #include <asm/cpu.h>
  34 #include <asm/cpu_device_id.h>
  35 #include <asm/debugreg.h>
  36 #include <asm/desc.h>
  37 #include <asm/fpu/internal.h>
  38 #include <asm/io.h>
  39 #include <asm/irq_remapping.h>
  40 #include <asm/kexec.h>
  41 #include <asm/perf_event.h>
  42 #include <asm/mce.h>
  43 #include <asm/mmu_context.h>
  44 #include <asm/mshyperv.h>
  45 #include <asm/mwait.h>
  46 #include <asm/spec-ctrl.h>
  47 #include <asm/virtext.h>
  48 #include <asm/vmx.h>
  49
  50 #include "capabilities.h"
  51 #include "cpuid.h"
  52 #include "evmcs.h"
  53 #include "irq.h"
  54 #include "kvm_cache_regs.h"
  55 #include "lapic.h"
  56 #include "mmu.h"
  57 #include "nested.h"
  58 #include "ops.h"
  59 #include "pmu.h"
  60 #include "trace.h"
  61 #include "vmcs.h"
  62 #include "vmcs12.h"
  63 #include "vmx.h"
  64 #include "x86.h"
  65
  66 MODULE_AUTHOR("Qumranet");
  67 MODULE_LICENSE("GPL");
  68
  69 #ifdef MODULE
  70 static const struct x86_cpu_id vmx_cpu_id[] = {
  71         X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
  72         {}
  73 };
  74 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  75 #endif
  76
  77 bool __read_mostly enable_vpid = 1;
  78 module_param_named(vpid, enable_vpid, bool, 0444);
  79
  80 static bool __read_mostly enable_vnmi = 1;
  81 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  82
  83 bool __read_mostly flexpriority_enabled = 1;
  84 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  85
  86 bool __read_mostly enable_ept = 1;
  87 module_param_named(ept, enable_ept, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_unrestricted_guest = 1;
  90 module_param_named(unrestricted_guest,
  91                         enable_unrestricted_guest, bool, S_IRUGO);
  92
  93 bool __read_mostly enable_ept_ad_bits = 1;
  94 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  95
  96 static bool __read_mostly emulate_invalid_guest_state = true;
  97 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  98
  99 static bool __read_mostly fasteoi = 1;
 100 module_param(fasteoi, bool, S_IRUGO);
 101
 102 bool __read_mostly enable_apicv = 1;
 103 module_param(enable_apicv, bool, S_IRUGO);
 104
 105 /*
 106  * If nested=1, nested virtualization is supported, i.e., guests may use
 107  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 108  * use VMX instructions.
 109  */
 110 static bool __read_mostly nested = 1;
 111 module_param(nested, bool, S_IRUGO);
 112
 113 bool __read_mostly enable_pml = 1;
 114 module_param_named(pml, enable_pml, bool, S_IRUGO);
 115
 116 static bool __read_mostly dump_invalid_vmcs = 0;
 117 module_param(dump_invalid_vmcs, bool, 0644);
 118
 119 #define MSR_BITMAP_MODE_X2APIC          1
 120 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 121
 122 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 123
 124 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 125 static int __read_mostly cpu_preemption_timer_multi;
 126 static bool __read_mostly enable_preemption_timer = 1;
 127 #ifdef CONFIG_X86_64
 128 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 129 #endif
 130
 131 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 132 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 133 #define KVM_VM_CR0_ALWAYS_ON                            \
 134         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 135          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 136 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 137         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 138          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 139
 140 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 141 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 142 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 143
 144 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 145
 146 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 147         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 148         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 149         RTIT_STATUS_BYTECNT))
 150
 151 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
 152         (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
 153
 154 /*
 155  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 156  * ple_gap:    upper bound on the amount of time between two successive
 157  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 158  *             According to test, this time is usually smaller than 128 cycles.
 159  * ple_window: upper bound on the amount of time a guest is allowed to execute
 160  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 161  *             less than 2^12 cycles
 162  * Time is measured based on a counter that runs at the same rate as the TSC,
 163  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 164  */
 165 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 166 module_param(ple_gap, uint, 0444);
 167
 168 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 169 module_param(ple_window, uint, 0444);
 170
 171 /* Default doubles per-vcpu window every exit. */
 172 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 173 module_param(ple_window_grow, uint, 0444);
 174
 175 /* Default resets per-vcpu window every exit to ple_window. */
 176 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 177 module_param(ple_window_shrink, uint, 0444);
 178
 179 /* Default is to compute the maximum so we can never overflow. */
 180 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 181 module_param(ple_window_max, uint, 0444);
 182
 183 /* Default is SYSTEM mode, 1 for host-guest mode */
 184 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 185 module_param(pt_mode, int, S_IRUGO);
 186
 187 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 188 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 189 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 190
 191 /* Storage for pre module init parameter parsing */
 192 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 193
 194 static const struct {
 195         const char *option;
 196         bool for_parse;
 197 } vmentry_l1d_param[] = {
 198         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 199         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 200         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 201         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 202         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 203         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 204 };
 205
 206 #define L1D_CACHE_ORDER 4
 207 static void *vmx_l1d_flush_pages;
 208
 209 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 210 {
 211         struct page *page;
 212         unsigned int i;
 213
 214         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 215                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 216                 return 0;
 217         }
 218
 219         if (!enable_ept) {
 220                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 221                 return 0;
 222         }
 223
 224         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 225                 u64 msr;
 226
 227                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 228                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 229                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 230                         return 0;
 231                 }
 232         }
 233
 234         /* If set to auto use the default l1tf mitigation method */
 235         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 236                 switch (l1tf_mitigation) {
 237                 case L1TF_MITIGATION_OFF:
 238                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 239                         break;
 240                 case L1TF_MITIGATION_FLUSH_NOWARN:
 241                 case L1TF_MITIGATION_FLUSH:
 242                 case L1TF_MITIGATION_FLUSH_NOSMT:
 243                         l1tf = VMENTER_L1D_FLUSH_COND;
 244                         break;
 245                 case L1TF_MITIGATION_FULL:
 246                 case L1TF_MITIGATION_FULL_FORCE:
 247                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 248                         break;
 249                 }
 250         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 251                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 252         }
 253
 254         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 255             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 256                 /*
 257                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 258                  * lifetime and so should not be charged to a memcg.
 259                  */
 260                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 261                 if (!page)
 262                         return -ENOMEM;
 263                 vmx_l1d_flush_pages = page_address(page);
 264
 265                 /*
 266                  * Initialize each page with a different pattern in
 267                  * order to protect against KSM in the nested
 268                  * virtualization case.
 269                  */
 270                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 271                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 272                                PAGE_SIZE);
 273                 }
 274         }
 275
 276         l1tf_vmx_mitigation = l1tf;
 277
 278         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 279                 static_branch_enable(&vmx_l1d_should_flush);
 280         else
 281                 static_branch_disable(&vmx_l1d_should_flush);
 282
 283         if (l1tf == VMENTER_L1D_FLUSH_COND)
 284                 static_branch_enable(&vmx_l1d_flush_cond);
 285         else
 286                 static_branch_disable(&vmx_l1d_flush_cond);
 287         return 0;
 288 }
 289
 290 static int vmentry_l1d_flush_parse(const char *s)
 291 {
 292         unsigned int i;
 293
 294         if (s) {
 295                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 296                         if (vmentry_l1d_param[i].for_parse &&
 297                             sysfs_streq(s, vmentry_l1d_param[i].option))
 298                                 return i;
 299                 }
 300         }
 301         return -EINVAL;
 302 }
 303
 304 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 305 {
 306         int l1tf, ret;
 307
 308         l1tf = vmentry_l1d_flush_parse(s);
 309         if (l1tf < 0)
 310                 return l1tf;
 311
 312         if (!boot_cpu_has(X86_BUG_L1TF))
 313                 return 0;
 314
 315         /*
 316          * Has vmx_init() run already? If not then this is the pre init
 317          * parameter parsing. In that case just store the value and let
 318          * vmx_init() do the proper setup after enable_ept has been
 319          * established.
 320          */
 321         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 322                 vmentry_l1d_flush_param = l1tf;
 323                 return 0;
 324         }
 325
 326         mutex_lock(&vmx_l1d_flush_mutex);
 327         ret = vmx_setup_l1d_flush(l1tf);
 328         mutex_unlock(&vmx_l1d_flush_mutex);
 329         return ret;
 330 }
 331
 332 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 333 {
 334         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 335                 return sprintf(s, "???\n");
 336
 337         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 338 }
 339
 340 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 341         .set = vmentry_l1d_flush_set,
 342         .get = vmentry_l1d_flush_get,
 343 };
 344 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 345
 346 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 347 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 348 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 349                                                           u32 msr, int type);
 350
 351 void vmx_vmexit(void);
 352
 353 #define vmx_insn_failed(fmt...)         \
 354 do {                                    \
 355         WARN_ONCE(1, fmt);              \
 356         pr_warn_ratelimited(fmt);       \
 357 } while (0)
 358
 359 asmlinkage void vmread_error(unsigned long field, bool fault)
 360 {
 361         if (fault)
 362                 kvm_spurious_fault();
 363         else
 364                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 365 }
 366
 367 noinline void vmwrite_error(unsigned long field, unsigned long value)
 368 {
 369         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 370                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 371 }
 372
 373 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 374 {
 375         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 376 }
 377
 378 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 379 {
 380         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 381 }
 382
 383 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 384 {
 385         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 386                         ext, vpid, gva);
 387 }
 388
 389 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 390 {
 391         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 392                         ext, eptp, gpa);
 393 }
 394
 395 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 396 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 397 /*
 398  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 399  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 400  */
 401 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 402
 403 /*
 404  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 405  * can find which vCPU should be waken up.
 406  */
 407 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 408 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 409
 410 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 411 static DEFINE_SPINLOCK(vmx_vpid_lock);
 412
 413 struct vmcs_config vmcs_config;
 414 struct vmx_capability vmx_capability;
 415
 416 #define VMX_SEGMENT_FIELD(seg)                                  \
 417         [VCPU_SREG_##seg] = {                                   \
 418                 .selector = GUEST_##seg##_SELECTOR,             \
 419                 .base = GUEST_##seg##_BASE,                     \
 420                 .limit = GUEST_##seg##_LIMIT,                   \
 421                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 422         }
 423
 424 static const struct kvm_vmx_segment_field {
 425         unsigned selector;
 426         unsigned base;
 427         unsigned limit;
 428         unsigned ar_bytes;
 429 } kvm_vmx_segment_fields[] = {
 430         VMX_SEGMENT_FIELD(CS),
 431         VMX_SEGMENT_FIELD(DS),
 432         VMX_SEGMENT_FIELD(ES),
 433         VMX_SEGMENT_FIELD(FS),
 434         VMX_SEGMENT_FIELD(GS),
 435         VMX_SEGMENT_FIELD(SS),
 436         VMX_SEGMENT_FIELD(TR),
 437         VMX_SEGMENT_FIELD(LDTR),
 438 };
 439
 440 static unsigned long host_idt_base;
 441
 442 /*
 443  * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
 444  * will emulate SYSCALL in legacy mode if the vendor string in guest
 445  * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
 446  * support this emulation, IA32_STAR must always be included in
 447  * vmx_msr_index[], even in i386 builds.
 448  */
 449 const u32 vmx_msr_index[] = {
 450 #ifdef CONFIG_X86_64
 451         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 452 #endif
 453         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 454         MSR_IA32_TSX_CTRL,
 455 };
 456
 457 #if IS_ENABLED(CONFIG_HYPERV)
 458 static bool __read_mostly enlightened_vmcs = true;
 459 module_param(enlightened_vmcs, bool, 0444);
 460
 461 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
 462 static void check_ept_pointer_match(struct kvm *kvm)
 463 {
 464         struct kvm_vcpu *vcpu;
 465         u64 tmp_eptp = INVALID_PAGE;
 466         int i;
 467
 468         kvm_for_each_vcpu(i, vcpu, kvm) {
 469                 if (!VALID_PAGE(tmp_eptp)) {
 470                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
 471                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
 472                         to_kvm_vmx(kvm)->ept_pointers_match
 473                                 = EPT_POINTERS_MISMATCH;
 474                         return;
 475                 }
 476         }
 477
 478         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
 479 }
 480
 481 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
 482                 void *data)
 483 {
 484         struct kvm_tlb_range *range = data;
 485
 486         return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
 487                         range->pages);
 488 }
 489
 490 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
 491                 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
 492 {
 493         u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
 494
 495         /*
 496          * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
 497          * of the base of EPT PML4 table, strip off EPT configuration
 498          * information.
 499          */
 500         if (range)
 501                 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
 502                                 kvm_fill_hv_flush_list_func, (void *)range);
 503         else
 504                 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
 505 }
 506
 507 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
 508                 struct kvm_tlb_range *range)
 509 {
 510         struct kvm_vcpu *vcpu;
 511         int ret = 0, i;
 512
 513         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 514
 515         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
 516                 check_ept_pointer_match(kvm);
 517
 518         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
 519                 kvm_for_each_vcpu(i, vcpu, kvm) {
 520                         /* If ept_pointer is invalid pointer, bypass flush request. */
 521                         if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
 522                                 ret |= __hv_remote_flush_tlb_with_range(
 523                                         kvm, vcpu, range);
 524                 }
 525         } else {
 526                 ret = __hv_remote_flush_tlb_with_range(kvm,
 527                                 kvm_get_vcpu(kvm, 0), range);
 528         }
 529
 530         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 531         return ret;
 532 }
 533 static int hv_remote_flush_tlb(struct kvm *kvm)
 534 {
 535         return hv_remote_flush_tlb_with_range(kvm, NULL);
 536 }
 537
 538 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 539 {
 540         struct hv_enlightened_vmcs *evmcs;
 541         struct hv_partition_assist_pg **p_hv_pa_pg =
 542                         &vcpu->kvm->arch.hyperv.hv_pa_pg;
 543         /*
 544          * Synthetic VM-Exit is not enabled in current code and so All
 545          * evmcs in singe VM shares same assist page.
 546          */
 547         if (!*p_hv_pa_pg)
 548                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
 549
 550         if (!*p_hv_pa_pg)
 551                 return -ENOMEM;
 552
 553         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 554
 555         evmcs->partition_assist_page =
 556                 __pa(*p_hv_pa_pg);
 557         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 558         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 559
 560         return 0;
 561 }
 562
 563 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 564
 565 /*
 566  * Comment's format: document - errata name - stepping - processor name.
 567  * Refer from
 568  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 569  */
 570 static u32 vmx_preemption_cpu_tfms[] = {
 571 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 572 0x000206E6,
 573 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 574 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 575 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 576 0x00020652,
 577 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 578 0x00020655,
 579 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 580 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 581 /*
 582  * 320767.pdf - AAP86  - B1 -
 583  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 584  */
 585 0x000106E5,
 586 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 587 0x000106A0,
 588 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 589 0x000106A1,
 590 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 591 0x000106A4,
 592  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 593  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 594  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 595 0x000106A5,
 596  /* Xeon E3-1220 V2 */
 597 0x000306A8,
 598 };
 599
 600 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 601 {
 602         u32 eax = cpuid_eax(0x00000001), i;
 603
 604         /* Clear the reserved bits */
 605         eax &= ~(0x3U << 14 | 0xfU << 28);
 606         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 607                 if (eax == vmx_preemption_cpu_tfms[i])
 608                         return true;
 609
 610         return false;
 611 }
 612
 613 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 614 {
 615         return flexpriority_enabled && lapic_in_kernel(vcpu);
 616 }
 617
 618 static inline bool report_flexpriority(void)
 619 {
 620         return flexpriority_enabled;
 621 }
 622
 623 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 624 {
 625         int i;
 626
 627         for (i = 0; i < vmx->nmsrs; ++i)
 628                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 629                         return i;
 630         return -1;
 631 }
 632
 633 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 634 {
 635         int i;
 636
 637         i = __find_msr_index(vmx, msr);
 638         if (i >= 0)
 639                 return &vmx->guest_msrs[i];
 640         return NULL;
 641 }
 642
 643 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
 644 {
 645         int ret = 0;
 646
 647         u64 old_msr_data = msr->data;
 648         msr->data = data;
 649         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
 650                 preempt_disable();
 651                 ret = kvm_set_shared_msr(msr->index, msr->data,
 652                                          msr->mask);
 653                 preempt_enable();
 654                 if (ret)
 655                         msr->data = old_msr_data;
 656         }
 657         return ret;
 658 }
 659
 660 #ifdef CONFIG_KEXEC_CORE
 661 static void crash_vmclear_local_loaded_vmcss(void)
 662 {
 663         int cpu = raw_smp_processor_id();
 664         struct loaded_vmcs *v;
 665
 666         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 667                             loaded_vmcss_on_cpu_link)
 668                 vmcs_clear(v->vmcs);
 669 }
 670 #endif /* CONFIG_KEXEC_CORE */
 671
 672 static void __loaded_vmcs_clear(void *arg)
 673 {
 674         struct loaded_vmcs *loaded_vmcs = arg;
 675         int cpu = raw_smp_processor_id();
 676
 677         if (loaded_vmcs->cpu != cpu)
 678                 return; /* vcpu migration can race with cpu offline */
 679         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 680                 per_cpu(current_vmcs, cpu) = NULL;
 681
 682         vmcs_clear(loaded_vmcs->vmcs);
 683         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 684                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 685
 686         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 687
 688         /*
 689          * Ensure all writes to loaded_vmcs, including deleting it from its
 690          * current percpu list, complete before setting loaded_vmcs->vcpu to
 691          * -1, otherwise a different cpu can see vcpu == -1 first and add
 692          * loaded_vmcs to its percpu list before it's deleted from this cpu's
 693          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
 694          */
 695         smp_wmb();
 696
 697         loaded_vmcs->cpu = -1;
 698         loaded_vmcs->launched = 0;
 699 }
 700
 701 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 702 {
 703         int cpu = loaded_vmcs->cpu;
 704
 705         if (cpu != -1)
 706                 smp_call_function_single(cpu,
 707                          __loaded_vmcs_clear, loaded_vmcs, 1);
 708 }
 709
 710 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 711                                        unsigned field)
 712 {
 713         bool ret;
 714         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 715
 716         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
 717                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
 718                 vmx->segment_cache.bitmask = 0;
 719         }
 720         ret = vmx->segment_cache.bitmask & mask;
 721         vmx->segment_cache.bitmask |= mask;
 722         return ret;
 723 }
 724
 725 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 726 {
 727         u16 *p = &vmx->segment_cache.seg[seg].selector;
 728
 729         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 730                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 731         return *p;
 732 }
 733
 734 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 735 {
 736         ulong *p = &vmx->segment_cache.seg[seg].base;
 737
 738         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 739                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 740         return *p;
 741 }
 742
 743 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 744 {
 745         u32 *p = &vmx->segment_cache.seg[seg].limit;
 746
 747         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 748                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 749         return *p;
 750 }
 751
 752 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 753 {
 754         u32 *p = &vmx->segment_cache.seg[seg].ar;
 755
 756         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 757                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 758         return *p;
 759 }
 760
 761 void update_exception_bitmap(struct kvm_vcpu *vcpu)
 762 {
 763         u32 eb;
 764
 765         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 766              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 767         /*
 768          * Guest access to VMware backdoor ports could legitimately
 769          * trigger #GP because of TSS I/O permission bitmap.
 770          * We intercept those #GP and allow access to them anyway
 771          * as VMware does.
 772          */
 773         if (enable_vmware_backdoor)
 774                 eb |= (1u << GP_VECTOR);
 775         if ((vcpu->guest_debug &
 776              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 777             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 778                 eb |= 1u << BP_VECTOR;
 779         if (to_vmx(vcpu)->rmode.vm86_active)
 780                 eb = ~0;
 781         if (enable_ept)
 782                 eb &= ~(1u << PF_VECTOR);
 783
 784         /* When we are running a nested L2 guest and L1 specified for it a
 785          * certain exception bitmap, we must trap the same exceptions and pass
 786          * them to L1. When running L2, we will only handle the exceptions
 787          * specified above if L1 did not want them.
 788          */
 789         if (is_guest_mode(vcpu))
 790                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 791
 792         vmcs_write32(EXCEPTION_BITMAP, eb);
 793 }
 794
 795 /*
 796  * Check if MSR is intercepted for currently loaded MSR bitmap.
 797  */
 798 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 799 {
 800         unsigned long *msr_bitmap;
 801         int f = sizeof(unsigned long);
 802
 803         if (!cpu_has_vmx_msr_bitmap())
 804                 return true;
 805
 806         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 807
 808         if (msr <= 0x1fff) {
 809                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 810         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 811                 msr &= 0x1fff;
 812                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 813         }
 814
 815         return true;
 816 }
 817
 818 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 819                 unsigned long entry, unsigned long exit)
 820 {
 821         vm_entry_controls_clearbit(vmx, entry);
 822         vm_exit_controls_clearbit(vmx, exit);
 823 }
 824
 825 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
 826 {
 827         unsigned int i;
 828
 829         for (i = 0; i < m->nr; ++i) {
 830                 if (m->val[i].index == msr)
 831                         return i;
 832         }
 833         return -ENOENT;
 834 }
 835
 836 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 837 {
 838         int i;
 839         struct msr_autoload *m = &vmx->msr_autoload;
 840
 841         switch (msr) {
 842         case MSR_EFER:
 843                 if (cpu_has_load_ia32_efer()) {
 844                         clear_atomic_switch_msr_special(vmx,
 845                                         VM_ENTRY_LOAD_IA32_EFER,
 846                                         VM_EXIT_LOAD_IA32_EFER);
 847                         return;
 848                 }
 849                 break;
 850         case MSR_CORE_PERF_GLOBAL_CTRL:
 851                 if (cpu_has_load_perf_global_ctrl()) {
 852                         clear_atomic_switch_msr_special(vmx,
 853                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 854                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 855                         return;
 856                 }
 857                 break;
 858         }
 859         i = vmx_find_msr_index(&m->guest, msr);
 860         if (i < 0)
 861                 goto skip_guest;
 862         --m->guest.nr;
 863         m->guest.val[i] = m->guest.val[m->guest.nr];
 864         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 865
 866 skip_guest:
 867         i = vmx_find_msr_index(&m->host, msr);
 868         if (i < 0)
 869                 return;
 870
 871         --m->host.nr;
 872         m->host.val[i] = m->host.val[m->host.nr];
 873         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 874 }
 875
 876 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 877                 unsigned long entry, unsigned long exit,
 878                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 879                 u64 guest_val, u64 host_val)
 880 {
 881         vmcs_write64(guest_val_vmcs, guest_val);
 882         if (host_val_vmcs != HOST_IA32_EFER)
 883                 vmcs_write64(host_val_vmcs, host_val);
 884         vm_entry_controls_setbit(vmx, entry);
 885         vm_exit_controls_setbit(vmx, exit);
 886 }
 887
 888 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 889                                   u64 guest_val, u64 host_val, bool entry_only)
 890 {
 891         int i, j = 0;
 892         struct msr_autoload *m = &vmx->msr_autoload;
 893
 894         switch (msr) {
 895         case MSR_EFER:
 896                 if (cpu_has_load_ia32_efer()) {
 897                         add_atomic_switch_msr_special(vmx,
 898                                         VM_ENTRY_LOAD_IA32_EFER,
 899                                         VM_EXIT_LOAD_IA32_EFER,
 900                                         GUEST_IA32_EFER,
 901                                         HOST_IA32_EFER,
 902                                         guest_val, host_val);
 903                         return;
 904                 }
 905                 break;
 906         case MSR_CORE_PERF_GLOBAL_CTRL:
 907                 if (cpu_has_load_perf_global_ctrl()) {
 908                         add_atomic_switch_msr_special(vmx,
 909                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 910                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 911                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 912                                         HOST_IA32_PERF_GLOBAL_CTRL,
 913                                         guest_val, host_val);
 914                         return;
 915                 }
 916                 break;
 917         case MSR_IA32_PEBS_ENABLE:
 918                 /* PEBS needs a quiescent period after being disabled (to write
 919                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 920                  * provide that period, so a CPU could write host's record into
 921                  * guest's memory.
 922                  */
 923                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 924         }
 925
 926         i = vmx_find_msr_index(&m->guest, msr);
 927         if (!entry_only)
 928                 j = vmx_find_msr_index(&m->host, msr);
 929
 930         if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
 931                 (j < 0 &&  m->host.nr == NR_LOADSTORE_MSRS)) {
 932                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 933                                 "Can't add msr %x\n", msr);
 934                 return;
 935         }
 936         if (i < 0) {
 937                 i = m->guest.nr++;
 938                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 939         }
 940         m->guest.val[i].index = msr;
 941         m->guest.val[i].value = guest_val;
 942
 943         if (entry_only)
 944                 return;
 945
 946         if (j < 0) {
 947                 j = m->host.nr++;
 948                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 949         }
 950         m->host.val[j].index = msr;
 951         m->host.val[j].value = host_val;
 952 }
 953
 954 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 955 {
 956         u64 guest_efer = vmx->vcpu.arch.efer;
 957         u64 ignore_bits = 0;
 958
 959         /* Shadow paging assumes NX to be available.  */
 960         if (!enable_ept)
 961                 guest_efer |= EFER_NX;
 962
 963         /*
 964          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 965          */
 966         ignore_bits |= EFER_SCE;
 967 #ifdef CONFIG_X86_64
 968         ignore_bits |= EFER_LMA | EFER_LME;
 969         /* SCE is meaningful only in long mode on Intel */
 970         if (guest_efer & EFER_LMA)
 971                 ignore_bits &= ~(u64)EFER_SCE;
 972 #endif
 973
 974         /*
 975          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 976          * On CPUs that support "load IA32_EFER", always switch EFER
 977          * atomically, since it's faster than switching it manually.
 978          */
 979         if (cpu_has_load_ia32_efer() ||
 980             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 981                 if (!(guest_efer & EFER_LMA))
 982                         guest_efer &= ~EFER_LME;
 983                 if (guest_efer != host_efer)
 984                         add_atomic_switch_msr(vmx, MSR_EFER,
 985                                               guest_efer, host_efer, false);
 986                 else
 987                         clear_atomic_switch_msr(vmx, MSR_EFER);
 988                 return false;
 989         } else {
 990                 clear_atomic_switch_msr(vmx, MSR_EFER);
 991
 992                 guest_efer &= ~ignore_bits;
 993                 guest_efer |= host_efer & ignore_bits;
 994
 995                 vmx->guest_msrs[efer_offset].data = guest_efer;
 996                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 997
 998                 return true;
 999         }
1000 }
1001
1002 #ifdef CONFIG_X86_32
1003 /*
1004  * On 32-bit kernels, VM exits still load the FS and GS bases from the
1005  * VMCS rather than the segment table.  KVM uses this helper to figure
1006  * out the current bases to poke them into the VMCS before entry.
1007  */
1008 static unsigned long segment_base(u16 selector)
1009 {
1010         struct desc_struct *table;
1011         unsigned long v;
1012
1013         if (!(selector & ~SEGMENT_RPL_MASK))
1014                 return 0;
1015
1016         table = get_current_gdt_ro();
1017
1018         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1019                 u16 ldt_selector = kvm_read_ldt();
1020
1021                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1022                         return 0;
1023
1024                 table = (struct desc_struct *)segment_base(ldt_selector);
1025         }
1026         v = get_desc_base(&table[selector >> 3]);
1027         return v;
1028 }
1029 #endif
1030
1031 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1032 {
1033         return vmx_pt_mode_is_host_guest() &&
1034                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1035 }
1036
1037 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1038 {
1039         u32 i;
1040
1041         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1042         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1043         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1044         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1045         for (i = 0; i < addr_range; i++) {
1046                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1047                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1048         }
1049 }
1050
1051 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1052 {
1053         u32 i;
1054
1055         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1056         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1057         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1058         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1059         for (i = 0; i < addr_range; i++) {
1060                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1061                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1062         }
1063 }
1064
1065 static void pt_guest_enter(struct vcpu_vmx *vmx)
1066 {
1067         if (vmx_pt_mode_is_system())
1068                 return;
1069
1070         /*
1071          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1072          * Save host state before VM entry.
1073          */
1074         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1075         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1076                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1077                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1078                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1079         }
1080 }
1081
1082 static void pt_guest_exit(struct vcpu_vmx *vmx)
1083 {
1084         if (vmx_pt_mode_is_system())
1085                 return;
1086
1087         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1088                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1089                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1090         }
1091
1092         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1093         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1094 }
1095
1096 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1097                         unsigned long fs_base, unsigned long gs_base)
1098 {
1099         if (unlikely(fs_sel != host->fs_sel)) {
1100                 if (!(fs_sel & 7))
1101                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1102                 else
1103                         vmcs_write16(HOST_FS_SELECTOR, 0);
1104                 host->fs_sel = fs_sel;
1105         }
1106         if (unlikely(gs_sel != host->gs_sel)) {
1107                 if (!(gs_sel & 7))
1108                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1109                 else
1110                         vmcs_write16(HOST_GS_SELECTOR, 0);
1111                 host->gs_sel = gs_sel;
1112         }
1113         if (unlikely(fs_base != host->fs_base)) {
1114                 vmcs_writel(HOST_FS_BASE, fs_base);
1115                 host->fs_base = fs_base;
1116         }
1117         if (unlikely(gs_base != host->gs_base)) {
1118                 vmcs_writel(HOST_GS_BASE, gs_base);
1119                 host->gs_base = gs_base;
1120         }
1121 }
1122
1123 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1124 {
1125         struct vcpu_vmx *vmx = to_vmx(vcpu);
1126         struct vmcs_host_state *host_state;
1127 #ifdef CONFIG_X86_64
1128         int cpu = raw_smp_processor_id();
1129 #endif
1130         unsigned long fs_base, gs_base;
1131         u16 fs_sel, gs_sel;
1132         int i;
1133
1134         vmx->req_immediate_exit = false;
1135
1136         /*
1137          * Note that guest MSRs to be saved/restored can also be changed
1138          * when guest state is loaded. This happens when guest transitions
1139          * to/from long-mode by setting MSR_EFER.LMA.
1140          */
1141         if (!vmx->guest_msrs_ready) {
1142                 vmx->guest_msrs_ready = true;
1143                 for (i = 0; i < vmx->save_nmsrs; ++i)
1144                         kvm_set_shared_msr(vmx->guest_msrs[i].index,
1145                                            vmx->guest_msrs[i].data,
1146                                            vmx->guest_msrs[i].mask);
1147
1148         }
1149
1150         if (vmx->nested.need_vmcs12_to_shadow_sync)
1151                 nested_sync_vmcs12_to_shadow(vcpu);
1152
1153         if (vmx->guest_state_loaded)
1154                 return;
1155
1156         host_state = &vmx->loaded_vmcs->host_state;
1157
1158         /*
1159          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1160          * allow segment selectors with cpl > 0 or ti == 1.
1161          */
1162         host_state->ldt_sel = kvm_read_ldt();
1163
1164 #ifdef CONFIG_X86_64
1165         savesegment(ds, host_state->ds_sel);
1166         savesegment(es, host_state->es_sel);
1167
1168         gs_base = cpu_kernelmode_gs_base(cpu);
1169         if (likely(is_64bit_mm(current->mm))) {
1170                 save_fsgs_for_kvm();
1171                 fs_sel = current->thread.fsindex;
1172                 gs_sel = current->thread.gsindex;
1173                 fs_base = current->thread.fsbase;
1174                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1175         } else {
1176                 savesegment(fs, fs_sel);
1177                 savesegment(gs, gs_sel);
1178                 fs_base = read_msr(MSR_FS_BASE);
1179                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1180         }
1181
1182         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1183 #else
1184         savesegment(fs, fs_sel);
1185         savesegment(gs, gs_sel);
1186         fs_base = segment_base(fs_sel);
1187         gs_base = segment_base(gs_sel);
1188 #endif
1189
1190         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1191         vmx->guest_state_loaded = true;
1192 }
1193
1194 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1195 {
1196         struct vmcs_host_state *host_state;
1197
1198         if (!vmx->guest_state_loaded)
1199                 return;
1200
1201         host_state = &vmx->loaded_vmcs->host_state;
1202
1203         ++vmx->vcpu.stat.host_state_reload;
1204
1205 #ifdef CONFIG_X86_64
1206         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1207 #endif
1208         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1209                 kvm_load_ldt(host_state->ldt_sel);
1210 #ifdef CONFIG_X86_64
1211                 load_gs_index(host_state->gs_sel);
1212 #else
1213                 loadsegment(gs, host_state->gs_sel);
1214 #endif
1215         }
1216         if (host_state->fs_sel & 7)
1217                 loadsegment(fs, host_state->fs_sel);
1218 #ifdef CONFIG_X86_64
1219         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1220                 loadsegment(ds, host_state->ds_sel);
1221                 loadsegment(es, host_state->es_sel);
1222         }
1223 #endif
1224         invalidate_tss_limit();
1225 #ifdef CONFIG_X86_64
1226         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1227 #endif
1228         load_fixmap_gdt(raw_smp_processor_id());
1229         vmx->guest_state_loaded = false;
1230         vmx->guest_msrs_ready = false;
1231 }
1232
1233 #ifdef CONFIG_X86_64
1234 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1235 {
1236         preempt_disable();
1237         if (vmx->guest_state_loaded)
1238                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1239         preempt_enable();
1240         return vmx->msr_guest_kernel_gs_base;
1241 }
1242
1243 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1244 {
1245         preempt_disable();
1246         if (vmx->guest_state_loaded)
1247                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1248         preempt_enable();
1249         vmx->msr_guest_kernel_gs_base = data;
1250 }
1251 #endif
1252
1253 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1254 {
1255         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1256         struct pi_desc old, new;
1257         unsigned int dest;
1258
1259         /*
1260          * In case of hot-plug or hot-unplug, we may have to undo
1261          * vmx_vcpu_pi_put even if there is no assigned device.  And we
1262          * always keep PI.NDST up to date for simplicity: it makes the
1263          * code easier, and CPU migration is not a fast path.
1264          */
1265         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1266                 return;
1267
1268         /*
1269          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1270          * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1271          * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1272          * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1273          * correctly.
1274          */
1275         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1276                 pi_clear_sn(pi_desc);
1277                 goto after_clear_sn;
1278         }
1279
1280         /* The full case.  */
1281         do {
1282                 old.control = new.control = pi_desc->control;
1283
1284                 dest = cpu_physical_id(cpu);
1285
1286                 if (x2apic_enabled())
1287                         new.ndst = dest;
1288                 else
1289                         new.ndst = (dest << 8) & 0xFF00;
1290
1291                 new.sn = 0;
1292         } while (cmpxchg64(&pi_desc->control, old.control,
1293                            new.control) != old.control);
1294
1295 after_clear_sn:
1296
1297         /*
1298          * Clear SN before reading the bitmap.  The VT-d firmware
1299          * writes the bitmap and reads SN atomically (5.2.3 in the
1300          * spec), so it doesn't really have a memory barrier that
1301          * pairs with this, but we cannot do that and we need one.
1302          */
1303         smp_mb__after_atomic();
1304
1305         if (!pi_is_pir_empty(pi_desc))
1306                 pi_set_on(pi_desc);
1307 }
1308
1309 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1310 {
1311         struct vcpu_vmx *vmx = to_vmx(vcpu);
1312         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1313
1314         if (!already_loaded) {
1315                 loaded_vmcs_clear(vmx->loaded_vmcs);
1316                 local_irq_disable();
1317
1318                 /*
1319                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1320                  * this cpu's percpu list, otherwise it may not yet be deleted
1321                  * from its previous cpu's percpu list.  Pairs with the
1322                  * smb_wmb() in __loaded_vmcs_clear().
1323                  */
1324                 smp_rmb();
1325
1326                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1327                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1328                 local_irq_enable();
1329         }
1330
1331         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1332                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1333                 vmcs_load(vmx->loaded_vmcs->vmcs);
1334                 indirect_branch_prediction_barrier();
1335         }
1336
1337         if (!already_loaded) {
1338                 void *gdt = get_current_gdt_ro();
1339                 unsigned long sysenter_esp;
1340
1341                 /*
1342                  * Flush all EPTP/VPID contexts, the new pCPU may have stale
1343                  * TLB entries from its previous association with the vCPU.
1344                  */
1345                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1346
1347                 /*
1348                  * Linux uses per-cpu TSS and GDT, so set these when switching
1349                  * processors.  See 22.2.4.
1350                  */
1351                 vmcs_writel(HOST_TR_BASE,
1352                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1353                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1354
1355                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1356                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1357
1358                 vmx->loaded_vmcs->cpu = cpu;
1359         }
1360
1361         /* Setup TSC multiplier */
1362         if (kvm_has_tsc_control &&
1363             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1364                 decache_tsc_multiplier(vmx);
1365 }
1366
1367 /*
1368  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1369  * vcpu mutex is already taken.
1370  */
1371 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1372 {
1373         struct vcpu_vmx *vmx = to_vmx(vcpu);
1374
1375         vmx_vcpu_load_vmcs(vcpu, cpu);
1376
1377         vmx_vcpu_pi_load(vcpu, cpu);
1378
1379         vmx->host_pkru = read_pkru();
1380         vmx->host_debugctlmsr = get_debugctlmsr();
1381 }
1382
1383 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1384 {
1385         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1386
1387         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1388                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
1389                 !kvm_vcpu_apicv_active(vcpu))
1390                 return;
1391
1392         /* Set SN when the vCPU is preempted */
1393         if (vcpu->preempted)
1394                 pi_set_sn(pi_desc);
1395 }
1396
1397 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1398 {
1399         vmx_vcpu_pi_put(vcpu);
1400
1401         vmx_prepare_switch_to_host(to_vmx(vcpu));
1402 }
1403
1404 static bool emulation_required(struct kvm_vcpu *vcpu)
1405 {
1406         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1407 }
1408
1409 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1410 {
1411         struct vcpu_vmx *vmx = to_vmx(vcpu);
1412         unsigned long rflags, save_rflags;
1413
1414         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1415                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1416                 rflags = vmcs_readl(GUEST_RFLAGS);
1417                 if (vmx->rmode.vm86_active) {
1418                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1419                         save_rflags = vmx->rmode.save_rflags;
1420                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1421                 }
1422                 vmx->rflags = rflags;
1423         }
1424         return vmx->rflags;
1425 }
1426
1427 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1428 {
1429         struct vcpu_vmx *vmx = to_vmx(vcpu);
1430         unsigned long old_rflags;
1431
1432         if (enable_unrestricted_guest) {
1433                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1434                 vmx->rflags = rflags;
1435                 vmcs_writel(GUEST_RFLAGS, rflags);
1436                 return;
1437         }
1438
1439         old_rflags = vmx_get_rflags(vcpu);
1440         vmx->rflags = rflags;
1441         if (vmx->rmode.vm86_active) {
1442                 vmx->rmode.save_rflags = rflags;
1443                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1444         }
1445         vmcs_writel(GUEST_RFLAGS, rflags);
1446
1447         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1448                 vmx->emulation_required = emulation_required(vcpu);
1449 }
1450
1451 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1452 {
1453         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1454         int ret = 0;
1455
1456         if (interruptibility & GUEST_INTR_STATE_STI)
1457                 ret |= KVM_X86_SHADOW_INT_STI;
1458         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1459                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1460
1461         return ret;
1462 }
1463
1464 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1465 {
1466         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1467         u32 interruptibility = interruptibility_old;
1468
1469         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1470
1471         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1472                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1473         else if (mask & KVM_X86_SHADOW_INT_STI)
1474                 interruptibility |= GUEST_INTR_STATE_STI;
1475
1476         if ((interruptibility != interruptibility_old))
1477                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1478 }
1479
1480 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1481 {
1482         struct vcpu_vmx *vmx = to_vmx(vcpu);
1483         unsigned long value;
1484
1485         /*
1486          * Any MSR write that attempts to change bits marked reserved will
1487          * case a #GP fault.
1488          */
1489         if (data & vmx->pt_desc.ctl_bitmask)
1490                 return 1;
1491
1492         /*
1493          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1494          * result in a #GP unless the same write also clears TraceEn.
1495          */
1496         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1497                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1498                 return 1;
1499
1500         /*
1501          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1502          * and FabricEn would cause #GP, if
1503          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1504          */
1505         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1506                 !(data & RTIT_CTL_FABRIC_EN) &&
1507                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1508                                         PT_CAP_single_range_output))
1509                 return 1;
1510
1511         /*
1512          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1513          * utilize encodings marked reserved will casue a #GP fault.
1514          */
1515         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1516         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1517                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1518                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1519                 return 1;
1520         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1521                                                 PT_CAP_cycle_thresholds);
1522         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1523                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1524                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1525                 return 1;
1526         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1527         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1528                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1529                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1530                 return 1;
1531
1532         /*
1533          * If ADDRx_CFG is reserved or the encodings is >2 will
1534          * cause a #GP fault.
1535          */
1536         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1537         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1538                 return 1;
1539         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1540         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1541                 return 1;
1542         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1543         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1544                 return 1;
1545         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1546         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1547                 return 1;
1548
1549         return 0;
1550 }
1551
1552 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1553 {
1554         unsigned long rip;
1555
1556         /*
1557          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1558          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1559          * set when EPT misconfig occurs.  In practice, real hardware updates
1560          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1561          * (namely Hyper-V) don't set it due to it being undefined behavior,
1562          * i.e. we end up advancing IP with some random value.
1563          */
1564         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1565             to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1566                 rip = kvm_rip_read(vcpu);
1567                 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1568                 kvm_rip_write(vcpu, rip);
1569         } else {
1570                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1571                         return 0;
1572         }
1573
1574         /* skipping an emulated instruction also counts */
1575         vmx_set_interrupt_shadow(vcpu, 0);
1576
1577         return 1;
1578 }
1579
1580
1581 /*
1582  * Recognizes a pending MTF VM-exit and records the nested state for later
1583  * delivery.
1584  */
1585 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1586 {
1587         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1588         struct vcpu_vmx *vmx = to_vmx(vcpu);
1589
1590         if (!is_guest_mode(vcpu))
1591                 return;
1592
1593         /*
1594          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1595          * T-bit traps. As instruction emulation is completed (i.e. at the
1596          * instruction boundary), any #DB exception pending delivery must be a
1597          * debug-trap. Record the pending MTF state to be delivered in
1598          * vmx_check_nested_events().
1599          */
1600         if (nested_cpu_has_mtf(vmcs12) &&
1601             (!vcpu->arch.exception.pending ||
1602              vcpu->arch.exception.nr == DB_VECTOR))
1603                 vmx->nested.mtf_pending = true;
1604         else
1605                 vmx->nested.mtf_pending = false;
1606 }
1607
1608 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1609 {
1610         vmx_update_emulated_instruction(vcpu);
1611         return skip_emulated_instruction(vcpu);
1612 }
1613
1614 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1615 {
1616         /*
1617          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1618          * explicitly skip the instruction because if the HLT state is set,
1619          * then the instruction is already executing and RIP has already been
1620          * advanced.
1621          */
1622         if (kvm_hlt_in_guest(vcpu->kvm) &&
1623                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1624                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1625 }
1626
1627 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1628 {
1629         struct vcpu_vmx *vmx = to_vmx(vcpu);
1630         unsigned nr = vcpu->arch.exception.nr;
1631         bool has_error_code = vcpu->arch.exception.has_error_code;
1632         u32 error_code = vcpu->arch.exception.error_code;
1633         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1634
1635         kvm_deliver_exception_payload(vcpu);
1636
1637         if (has_error_code) {
1638                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1639                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1640         }
1641
1642         if (vmx->rmode.vm86_active) {
1643                 int inc_eip = 0;
1644                 if (kvm_exception_is_soft(nr))
1645                         inc_eip = vcpu->arch.event_exit_inst_len;
1646                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1647                 return;
1648         }
1649
1650         WARN_ON_ONCE(vmx->emulation_required);
1651
1652         if (kvm_exception_is_soft(nr)) {
1653                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1654                              vmx->vcpu.arch.event_exit_inst_len);
1655                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1656         } else
1657                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1658
1659         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1660
1661         vmx_clear_hlt(vcpu);
1662 }
1663
1664 /*
1665  * Swap MSR entry in host/guest MSR entry array.
1666  */
1667 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1668 {
1669         struct shared_msr_entry tmp;
1670
1671         tmp = vmx->guest_msrs[to];
1672         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1673         vmx->guest_msrs[from] = tmp;
1674 }
1675
1676 /*
1677  * Set up the vmcs to automatically save and restore system
1678  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1679  * mode, as fiddling with msrs is very expensive.
1680  */
1681 static void setup_msrs(struct vcpu_vmx *vmx)
1682 {
1683         int save_nmsrs, index;
1684
1685         save_nmsrs = 0;
1686 #ifdef CONFIG_X86_64
1687         /*
1688          * The SYSCALL MSRs are only needed on long mode guests, and only
1689          * when EFER.SCE is set.
1690          */
1691         if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1692                 index = __find_msr_index(vmx, MSR_STAR);
1693                 if (index >= 0)
1694                         move_msr_up(vmx, index, save_nmsrs++);
1695                 index = __find_msr_index(vmx, MSR_LSTAR);
1696                 if (index >= 0)
1697                         move_msr_up(vmx, index, save_nmsrs++);
1698                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1699                 if (index >= 0)
1700                         move_msr_up(vmx, index, save_nmsrs++);
1701         }
1702 #endif
1703         index = __find_msr_index(vmx, MSR_EFER);
1704         if (index >= 0 && update_transition_efer(vmx, index))
1705                 move_msr_up(vmx, index, save_nmsrs++);
1706         index = __find_msr_index(vmx, MSR_TSC_AUX);
1707         if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1708                 move_msr_up(vmx, index, save_nmsrs++);
1709         index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1710         if (index >= 0)
1711                 move_msr_up(vmx, index, save_nmsrs++);
1712
1713         vmx->save_nmsrs = save_nmsrs;
1714         vmx->guest_msrs_ready = false;
1715
1716         if (cpu_has_vmx_msr_bitmap())
1717                 vmx_update_msr_bitmap(&vmx->vcpu);
1718 }
1719
1720 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1721 {
1722         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1723
1724         if (is_guest_mode(vcpu) &&
1725             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1726                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1727
1728         return vcpu->arch.tsc_offset;
1729 }
1730
1731 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1732 {
1733         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1734         u64 g_tsc_offset = 0;
1735
1736         /*
1737          * We're here if L1 chose not to trap WRMSR to TSC. According
1738          * to the spec, this should set L1's TSC; The offset that L1
1739          * set for L2 remains unchanged, and still needs to be added
1740          * to the newly set TSC to get L2's TSC.
1741          */
1742         if (is_guest_mode(vcpu) &&
1743             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1744                 g_tsc_offset = vmcs12->tsc_offset;
1745
1746         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1747                                    vcpu->arch.tsc_offset - g_tsc_offset,
1748                                    offset);
1749         vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1750         return offset + g_tsc_offset;
1751 }
1752
1753 /*
1754  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1755  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1756  * all guests if the "nested" module option is off, and can also be disabled
1757  * for a single guest by disabling its VMX cpuid bit.
1758  */
1759 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1760 {
1761         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1762 }
1763
1764 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1765                                                  uint64_t val)
1766 {
1767         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1768
1769         return !(val & ~valid_bits);
1770 }
1771
1772 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1773 {
1774         switch (msr->index) {
1775         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1776                 if (!nested)
1777                         return 1;
1778                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1779         default:
1780                 return 1;
1781         }
1782 }
1783
1784 /*
1785  * Reads an msr value (of 'msr_index') into 'pdata'.
1786  * Returns 0 on success, non-0 otherwise.
1787  * Assumes vcpu_load() was already called.
1788  */
1789 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1790 {
1791         struct vcpu_vmx *vmx = to_vmx(vcpu);
1792         struct shared_msr_entry *msr;
1793         u32 index;
1794
1795         switch (msr_info->index) {
1796 #ifdef CONFIG_X86_64
1797         case MSR_FS_BASE:
1798                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1799                 break;
1800         case MSR_GS_BASE:
1801                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1802                 break;
1803         case MSR_KERNEL_GS_BASE:
1804                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1805                 break;
1806 #endif
1807         case MSR_EFER:
1808                 return kvm_get_msr_common(vcpu, msr_info);
1809         case MSR_IA32_TSX_CTRL:
1810                 if (!msr_info->host_initiated &&
1811                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1812                         return 1;
1813                 goto find_shared_msr;
1814         case MSR_IA32_UMWAIT_CONTROL:
1815                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1816                         return 1;
1817
1818                 msr_info->data = vmx->msr_ia32_umwait_control;
1819                 break;
1820         case MSR_IA32_SPEC_CTRL:
1821                 if (!msr_info->host_initiated &&
1822                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1823                         return 1;
1824
1825                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1826                 break;
1827         case MSR_IA32_SYSENTER_CS:
1828                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1829                 break;
1830         case MSR_IA32_SYSENTER_EIP:
1831                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1832                 break;
1833         case MSR_IA32_SYSENTER_ESP:
1834                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1835                 break;
1836         case MSR_IA32_BNDCFGS:
1837                 if (!kvm_mpx_supported() ||
1838                     (!msr_info->host_initiated &&
1839                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1840                         return 1;
1841                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1842                 break;
1843         case MSR_IA32_MCG_EXT_CTL:
1844                 if (!msr_info->host_initiated &&
1845                     !(vmx->msr_ia32_feature_control &
1846                       FEAT_CTL_LMCE_ENABLED))
1847                         return 1;
1848                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1849                 break;
1850         case MSR_IA32_FEAT_CTL:
1851                 msr_info->data = vmx->msr_ia32_feature_control;
1852                 break;
1853         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1854                 if (!nested_vmx_allowed(vcpu))
1855                         return 1;
1856                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1857                                     &msr_info->data))
1858                         return 1;
1859                 /*
1860                  * Enlightened VMCS v1 doesn't have certain fields, but buggy
1861                  * Hyper-V versions are still trying to use corresponding
1862                  * features when they are exposed. Filter out the essential
1863                  * minimum.
1864                  */
1865                 if (!msr_info->host_initiated &&
1866                     vmx->nested.enlightened_vmcs_enabled)
1867                         nested_evmcs_filter_control_msr(msr_info->index,
1868                                                         &msr_info->data);
1869                 break;
1870         case MSR_IA32_RTIT_CTL:
1871                 if (!vmx_pt_mode_is_host_guest())
1872                         return 1;
1873                 msr_info->data = vmx->pt_desc.guest.ctl;
1874                 break;
1875         case MSR_IA32_RTIT_STATUS:
1876                 if (!vmx_pt_mode_is_host_guest())
1877                         return 1;
1878                 msr_info->data = vmx->pt_desc.guest.status;
1879                 break;
1880         case MSR_IA32_RTIT_CR3_MATCH:
1881                 if (!vmx_pt_mode_is_host_guest() ||
1882                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1883                                                 PT_CAP_cr3_filtering))
1884                         return 1;
1885                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1886                 break;
1887         case MSR_IA32_RTIT_OUTPUT_BASE:
1888                 if (!vmx_pt_mode_is_host_guest() ||
1889                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1890                                         PT_CAP_topa_output) &&
1891                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1892                                         PT_CAP_single_range_output)))
1893                         return 1;
1894                 msr_info->data = vmx->pt_desc.guest.output_base;
1895                 break;
1896         case MSR_IA32_RTIT_OUTPUT_MASK:
1897                 if (!vmx_pt_mode_is_host_guest() ||
1898                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1899                                         PT_CAP_topa_output) &&
1900                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1901                                         PT_CAP_single_range_output)))
1902                         return 1;
1903                 msr_info->data = vmx->pt_desc.guest.output_mask;
1904                 break;
1905         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1906                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1907                 if (!vmx_pt_mode_is_host_guest() ||
1908                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1909                                         PT_CAP_num_address_ranges)))
1910                         return 1;
1911                 if (index % 2)
1912                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1913                 else
1914                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1915                 break;
1916         case MSR_TSC_AUX:
1917                 if (!msr_info->host_initiated &&
1918                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1919                         return 1;
1920                 goto find_shared_msr;
1921         default:
1922         find_shared_msr:
1923                 msr = find_msr_entry(vmx, msr_info->index);
1924                 if (msr) {
1925                         msr_info->data = msr->data;
1926                         break;
1927                 }
1928                 return kvm_get_msr_common(vcpu, msr_info);
1929         }
1930
1931         return 0;
1932 }
1933
1934 /*
1935  * Writes msr value into the appropriate "register".
1936  * Returns 0 on success, non-0 otherwise.
1937  * Assumes vcpu_load() was already called.
1938  */
1939 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1940 {
1941         struct vcpu_vmx *vmx = to_vmx(vcpu);
1942         struct shared_msr_entry *msr;
1943         int ret = 0;
1944         u32 msr_index = msr_info->index;
1945         u64 data = msr_info->data;
1946         u32 index;
1947
1948         switch (msr_index) {
1949         case MSR_EFER:
1950                 ret = kvm_set_msr_common(vcpu, msr_info);
1951                 break;
1952 #ifdef CONFIG_X86_64
1953         case MSR_FS_BASE:
1954                 vmx_segment_cache_clear(vmx);
1955                 vmcs_writel(GUEST_FS_BASE, data);
1956                 break;
1957         case MSR_GS_BASE:
1958                 vmx_segment_cache_clear(vmx);
1959                 vmcs_writel(GUEST_GS_BASE, data);
1960                 break;
1961         case MSR_KERNEL_GS_BASE:
1962                 vmx_write_guest_kernel_gs_base(vmx, data);
1963                 break;
1964 #endif
1965         case MSR_IA32_SYSENTER_CS:
1966                 if (is_guest_mode(vcpu))
1967                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1968                 vmcs_write32(GUEST_SYSENTER_CS, data);
1969                 break;
1970         case MSR_IA32_SYSENTER_EIP:
1971                 if (is_guest_mode(vcpu))
1972                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1973                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1974                 break;
1975         case MSR_IA32_SYSENTER_ESP:
1976                 if (is_guest_mode(vcpu))
1977                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1978                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1979                 break;
1980         case MSR_IA32_DEBUGCTLMSR:
1981                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1982                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
1983                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1984
1985                 ret = kvm_set_msr_common(vcpu, msr_info);
1986                 break;
1987
1988         case MSR_IA32_BNDCFGS:
1989                 if (!kvm_mpx_supported() ||
1990                     (!msr_info->host_initiated &&
1991                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1992                         return 1;
1993                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1994                     (data & MSR_IA32_BNDCFGS_RSVD))
1995                         return 1;
1996                 vmcs_write64(GUEST_BNDCFGS, data);
1997                 break;
1998         case MSR_IA32_UMWAIT_CONTROL:
1999                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2000                         return 1;
2001
2002                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2003                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2004                         return 1;
2005
2006                 vmx->msr_ia32_umwait_control = data;
2007                 break;
2008         case MSR_IA32_SPEC_CTRL:
2009                 if (!msr_info->host_initiated &&
2010                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2011                         return 1;
2012
2013                 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
2014                         return 1;
2015
2016                 vmx->spec_ctrl = data;
2017                 if (!data)
2018                         break;
2019
2020                 /*
2021                  * For non-nested:
2022                  * When it's written (to non-zero) for the first time, pass
2023                  * it through.
2024                  *
2025                  * For nested:
2026                  * The handling of the MSR bitmap for L2 guests is done in
2027                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2028                  * vmcs02.msr_bitmap here since it gets completely overwritten
2029                  * in the merging. We update the vmcs01 here for L1 as well
2030                  * since it will end up touching the MSR anyway now.
2031                  */
2032                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2033                                               MSR_IA32_SPEC_CTRL,
2034                                               MSR_TYPE_RW);
2035                 break;
2036         case MSR_IA32_TSX_CTRL:
2037                 if (!msr_info->host_initiated &&
2038                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2039                         return 1;
2040                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2041                         return 1;
2042                 goto find_shared_msr;
2043         case MSR_IA32_PRED_CMD:
2044                 if (!msr_info->host_initiated &&
2045                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2046                         return 1;
2047
2048                 if (data & ~PRED_CMD_IBPB)
2049                         return 1;
2050                 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2051                         return 1;
2052                 if (!data)
2053                         break;
2054
2055                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2056
2057                 /*
2058                  * For non-nested:
2059                  * When it's written (to non-zero) for the first time, pass
2060                  * it through.
2061                  *
2062                  * For nested:
2063                  * The handling of the MSR bitmap for L2 guests is done in
2064                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2065                  * vmcs02.msr_bitmap here since it gets completely overwritten
2066                  * in the merging.
2067                  */
2068                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2069                                               MSR_TYPE_W);
2070                 break;
2071         case MSR_IA32_CR_PAT:
2072                 if (!kvm_pat_valid(data))
2073                         return 1;
2074
2075                 if (is_guest_mode(vcpu) &&
2076                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2077                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2078
2079                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2080                         vmcs_write64(GUEST_IA32_PAT, data);
2081                         vcpu->arch.pat = data;
2082                         break;
2083                 }
2084                 ret = kvm_set_msr_common(vcpu, msr_info);
2085                 break;
2086         case MSR_IA32_TSC_ADJUST:
2087                 ret = kvm_set_msr_common(vcpu, msr_info);
2088                 break;
2089         case MSR_IA32_MCG_EXT_CTL:
2090                 if ((!msr_info->host_initiated &&
2091                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2092                        FEAT_CTL_LMCE_ENABLED)) ||
2093                     (data & ~MCG_EXT_CTL_LMCE_EN))
2094                         return 1;
2095                 vcpu->arch.mcg_ext_ctl = data;
2096                 break;
2097         case MSR_IA32_FEAT_CTL:
2098                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2099                     (to_vmx(vcpu)->msr_ia32_feature_control &
2100                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2101                         return 1;
2102                 vmx->msr_ia32_feature_control = data;
2103                 if (msr_info->host_initiated && data == 0)
2104                         vmx_leave_nested(vcpu);
2105                 break;
2106         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2107                 if (!msr_info->host_initiated)
2108                         return 1; /* they are read-only */
2109                 if (!nested_vmx_allowed(vcpu))
2110                         return 1;
2111                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2112         case MSR_IA32_RTIT_CTL:
2113                 if (!vmx_pt_mode_is_host_guest() ||
2114                         vmx_rtit_ctl_check(vcpu, data) ||
2115                         vmx->nested.vmxon)
2116                         return 1;
2117                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2118                 vmx->pt_desc.guest.ctl = data;
2119                 pt_update_intercept_for_msr(vmx);
2120                 break;
2121         case MSR_IA32_RTIT_STATUS:
2122                 if (!pt_can_write_msr(vmx))
2123                         return 1;
2124                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2125                         return 1;
2126                 vmx->pt_desc.guest.status = data;
2127                 break;
2128         case MSR_IA32_RTIT_CR3_MATCH:
2129                 if (!pt_can_write_msr(vmx))
2130                         return 1;
2131                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2132                                            PT_CAP_cr3_filtering))
2133                         return 1;
2134                 vmx->pt_desc.guest.cr3_match = data;
2135                 break;
2136         case MSR_IA32_RTIT_OUTPUT_BASE:
2137                 if (!pt_can_write_msr(vmx))
2138                         return 1;
2139                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2140                                            PT_CAP_topa_output) &&
2141                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2142                                            PT_CAP_single_range_output))
2143                         return 1;
2144                 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
2145                         return 1;
2146                 vmx->pt_desc.guest.output_base = data;
2147                 break;
2148         case MSR_IA32_RTIT_OUTPUT_MASK:
2149                 if (!pt_can_write_msr(vmx))
2150                         return 1;
2151                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2152                                            PT_CAP_topa_output) &&
2153                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2154                                            PT_CAP_single_range_output))
2155                         return 1;
2156                 vmx->pt_desc.guest.output_mask = data;
2157                 break;
2158         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2159                 if (!pt_can_write_msr(vmx))
2160                         return 1;
2161                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2162                 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2163                                                        PT_CAP_num_address_ranges))
2164                         return 1;
2165                 if (is_noncanonical_address(data, vcpu))
2166                         return 1;
2167                 if (index % 2)
2168                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2169                 else
2170                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2171                 break;
2172         case MSR_TSC_AUX:
2173                 if (!msr_info->host_initiated &&
2174                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2175                         return 1;
2176                 /* Check reserved bit, higher 32 bits should be zero */
2177                 if ((data >> 32) != 0)
2178                         return 1;
2179                 goto find_shared_msr;
2180
2181         default:
2182         find_shared_msr:
2183                 msr = find_msr_entry(vmx, msr_index);
2184                 if (msr)
2185                         ret = vmx_set_guest_msr(vmx, msr, data);
2186                 else
2187                         ret = kvm_set_msr_common(vcpu, msr_info);
2188         }
2189
2190         return ret;
2191 }
2192
2193 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2194 {
2195         kvm_register_mark_available(vcpu, reg);
2196
2197         switch (reg) {
2198         case VCPU_REGS_RSP:
2199                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2200                 break;
2201         case VCPU_REGS_RIP:
2202                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2203                 break;
2204         case VCPU_EXREG_PDPTR:
2205                 if (enable_ept)
2206                         ept_save_pdptrs(vcpu);
2207                 break;
2208         case VCPU_EXREG_CR3:
2209                 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2210                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2211                 break;
2212         default:
2213                 WARN_ON_ONCE(1);
2214                 break;
2215         }
2216 }
2217
2218 static __init int cpu_has_kvm_support(void)
2219 {
2220         return cpu_has_vmx();
2221 }
2222
2223 static __init int vmx_disabled_by_bios(void)
2224 {
2225         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2226                !boot_cpu_has(X86_FEATURE_VMX);
2227 }
2228
2229 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2230 {
2231         u64 msr;
2232
2233         cr4_set_bits(X86_CR4_VMXE);
2234         intel_pt_handle_vmx(1);
2235
2236         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2237                           _ASM_EXTABLE(1b, %l[fault])
2238                           : : [vmxon_pointer] "m"(vmxon_pointer)
2239                           : : fault);
2240         return 0;
2241
2242 fault:
2243         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2244                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2245         intel_pt_handle_vmx(0);
2246         cr4_clear_bits(X86_CR4_VMXE);
2247
2248         return -EFAULT;
2249 }
2250
2251 static int hardware_enable(void)
2252 {
2253         int cpu = raw_smp_processor_id();
2254         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2255         int r;
2256
2257         if (cr4_read_shadow() & X86_CR4_VMXE)
2258                 return -EBUSY;
2259
2260         /*
2261          * This can happen if we hot-added a CPU but failed to allocate
2262          * VP assist page for it.
2263          */
2264         if (static_branch_unlikely(&enable_evmcs) &&
2265             !hv_get_vp_assist_page(cpu))
2266                 return -EFAULT;
2267
2268         r = kvm_cpu_vmxon(phys_addr);
2269         if (r)
2270                 return r;
2271
2272         if (enable_ept)
2273                 ept_sync_global();
2274
2275         return 0;
2276 }
2277
2278 static void vmclear_local_loaded_vmcss(void)
2279 {
2280         int cpu = raw_smp_processor_id();
2281         struct loaded_vmcs *v, *n;
2282
2283         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2284                                  loaded_vmcss_on_cpu_link)
2285                 __loaded_vmcs_clear(v);
2286 }
2287
2288
2289 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2290  * tricks.
2291  */
2292 static void kvm_cpu_vmxoff(void)
2293 {
2294         asm volatile (__ex("vmxoff"));
2295
2296         intel_pt_handle_vmx(0);
2297         cr4_clear_bits(X86_CR4_VMXE);
2298 }
2299
2300 static void hardware_disable(void)
2301 {
2302         vmclear_local_loaded_vmcss();
2303         kvm_cpu_vmxoff();
2304 }
2305
2306 /*
2307  * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2308  * directly instead of going through cpu_has(), to ensure KVM is trapping
2309  * ENCLS whenever it's supported in hardware.  It does not matter whether
2310  * the host OS supports or has enabled SGX.
2311  */
2312 static bool cpu_has_sgx(void)
2313 {
2314         return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2315 }
2316
2317 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2318                                       u32 msr, u32 *result)
2319 {
2320         u32 vmx_msr_low, vmx_msr_high;
2321         u32 ctl = ctl_min | ctl_opt;
2322
2323         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2324
2325         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2326         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2327
2328         /* Ensure minimum (required) set of control bits are supported. */
2329         if (ctl_min & ~ctl)
2330                 return -EIO;
2331
2332         *result = ctl;
2333         return 0;
2334 }
2335
2336 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2337                                     struct vmx_capability *vmx_cap)
2338 {
2339         u32 vmx_msr_low, vmx_msr_high;
2340         u32 min, opt, min2, opt2;
2341         u32 _pin_based_exec_control = 0;
2342         u32 _cpu_based_exec_control = 0;
2343         u32 _cpu_based_2nd_exec_control = 0;
2344         u32 _vmexit_control = 0;
2345         u32 _vmentry_control = 0;
2346
2347         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2348         min = CPU_BASED_HLT_EXITING |
2349 #ifdef CONFIG_X86_64
2350               CPU_BASED_CR8_LOAD_EXITING |
2351               CPU_BASED_CR8_STORE_EXITING |
2352 #endif
2353               CPU_BASED_CR3_LOAD_EXITING |
2354               CPU_BASED_CR3_STORE_EXITING |
2355               CPU_BASED_UNCOND_IO_EXITING |
2356               CPU_BASED_MOV_DR_EXITING |
2357               CPU_BASED_USE_TSC_OFFSETTING |
2358               CPU_BASED_MWAIT_EXITING |
2359               CPU_BASED_MONITOR_EXITING |
2360               CPU_BASED_INVLPG_EXITING |
2361               CPU_BASED_RDPMC_EXITING;
2362
2363         opt = CPU_BASED_TPR_SHADOW |
2364               CPU_BASED_USE_MSR_BITMAPS |
2365               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2366         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2367                                 &_cpu_based_exec_control) < 0)
2368                 return -EIO;
2369 #ifdef CONFIG_X86_64
2370         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2371                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2372                                            ~CPU_BASED_CR8_STORE_EXITING;
2373 #endif
2374         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2375                 min2 = 0;
2376                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2377                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2378                         SECONDARY_EXEC_WBINVD_EXITING |
2379                         SECONDARY_EXEC_ENABLE_VPID |
2380                         SECONDARY_EXEC_ENABLE_EPT |
2381                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2382                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2383                         SECONDARY_EXEC_DESC |
2384                         SECONDARY_EXEC_RDTSCP |
2385                         SECONDARY_EXEC_ENABLE_INVPCID |
2386                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2387                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2388                         SECONDARY_EXEC_SHADOW_VMCS |
2389                         SECONDARY_EXEC_XSAVES |
2390                         SECONDARY_EXEC_RDSEED_EXITING |
2391                         SECONDARY_EXEC_RDRAND_EXITING |
2392                         SECONDARY_EXEC_ENABLE_PML |
2393                         SECONDARY_EXEC_TSC_SCALING |
2394                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2395                         SECONDARY_EXEC_PT_USE_GPA |
2396                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2397                         SECONDARY_EXEC_ENABLE_VMFUNC;
2398                 if (cpu_has_sgx())
2399                         opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2400                 if (adjust_vmx_controls(min2, opt2,
2401                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2402                                         &_cpu_based_2nd_exec_control) < 0)
2403                         return -EIO;
2404         }
2405 #ifndef CONFIG_X86_64
2406         if (!(_cpu_based_2nd_exec_control &
2407                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2408                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2409 #endif
2410
2411         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2412                 _cpu_based_2nd_exec_control &= ~(
2413                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2414                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2415                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2416
2417         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2418                 &vmx_cap->ept, &vmx_cap->vpid);
2419
2420         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2421                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2422                    enabled */
2423                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2424                                              CPU_BASED_CR3_STORE_EXITING |
2425                                              CPU_BASED_INVLPG_EXITING);
2426         } else if (vmx_cap->ept) {
2427                 vmx_cap->ept = 0;
2428                 pr_warn_once("EPT CAP should not exist if not support "
2429                                 "1-setting enable EPT VM-execution control\n");
2430         }
2431         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2432                 vmx_cap->vpid) {
2433                 vmx_cap->vpid = 0;
2434                 pr_warn_once("VPID CAP should not exist if not support "
2435                                 "1-setting enable VPID VM-execution control\n");
2436         }
2437
2438         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2439 #ifdef CONFIG_X86_64
2440         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2441 #endif
2442         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2443               VM_EXIT_LOAD_IA32_PAT |
2444               VM_EXIT_LOAD_IA32_EFER |
2445               VM_EXIT_CLEAR_BNDCFGS |
2446               VM_EXIT_PT_CONCEAL_PIP |
2447               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2448         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2449                                 &_vmexit_control) < 0)
2450                 return -EIO;
2451
2452         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2453         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2454                  PIN_BASED_VMX_PREEMPTION_TIMER;
2455         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2456                                 &_pin_based_exec_control) < 0)
2457                 return -EIO;
2458
2459         if (cpu_has_broken_vmx_preemption_timer())
2460                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2461         if (!(_cpu_based_2nd_exec_control &
2462                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2463                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2464
2465         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2466         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2467               VM_ENTRY_LOAD_IA32_PAT |
2468               VM_ENTRY_LOAD_IA32_EFER |
2469               VM_ENTRY_LOAD_BNDCFGS |
2470               VM_ENTRY_PT_CONCEAL_PIP |
2471               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2472         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2473                                 &_vmentry_control) < 0)
2474                 return -EIO;
2475
2476         /*
2477          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2478          * can't be used due to an errata where VM Exit may incorrectly clear
2479          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2480          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2481          */
2482         if (boot_cpu_data.x86 == 0x6) {
2483                 switch (boot_cpu_data.x86_model) {
2484                 case 26: /* AAK155 */
2485                 case 30: /* AAP115 */
2486                 case 37: /* AAT100 */
2487                 case 44: /* BC86,AAY89,BD102 */
2488                 case 46: /* BA97 */
2489                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2490                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2491                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2492                                         "does not work properly. Using workaround\n");
2493                         break;
2494                 default:
2495                         break;
2496                 }
2497         }
2498
2499
2500         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2501
2502         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2503         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2504                 return -EIO;
2505
2506 #ifdef CONFIG_X86_64
2507         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2508         if (vmx_msr_high & (1u<<16))
2509                 return -EIO;
2510 #endif
2511
2512         /* Require Write-Back (WB) memory type for VMCS accesses. */
2513         if (((vmx_msr_high >> 18) & 15) != 6)
2514                 return -EIO;
2515
2516         vmcs_conf->size = vmx_msr_high & 0x1fff;
2517         vmcs_conf->order = get_order(vmcs_conf->size);
2518         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2519
2520         vmcs_conf->revision_id = vmx_msr_low;
2521
2522         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2523         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2524         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2525         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2526         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2527
2528         if (static_branch_unlikely(&enable_evmcs))
2529                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2530
2531         return 0;
2532 }
2533
2534 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2535 {
2536         int node = cpu_to_node(cpu);
2537         struct page *pages;
2538         struct vmcs *vmcs;
2539
2540         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2541         if (!pages)
2542                 return NULL;
2543         vmcs = page_address(pages);
2544         memset(vmcs, 0, vmcs_config.size);
2545
2546         /* KVM supports Enlightened VMCS v1 only */
2547         if (static_branch_unlikely(&enable_evmcs))
2548                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2549         else
2550                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2551
2552         if (shadow)
2553                 vmcs->hdr.shadow_vmcs = 1;
2554         return vmcs;
2555 }
2556
2557 void free_vmcs(struct vmcs *vmcs)
2558 {
2559         free_pages((unsigned long)vmcs, vmcs_config.order);
2560 }
2561
2562 /*
2563  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2564  */
2565 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2566 {
2567         if (!loaded_vmcs->vmcs)
2568                 return;
2569         loaded_vmcs_clear(loaded_vmcs);
2570         free_vmcs(loaded_vmcs->vmcs);
2571         loaded_vmcs->vmcs = NULL;
2572         if (loaded_vmcs->msr_bitmap)
2573                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2574         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2575 }
2576
2577 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2578 {
2579         loaded_vmcs->vmcs = alloc_vmcs(false);
2580         if (!loaded_vmcs->vmcs)
2581                 return -ENOMEM;
2582
2583         vmcs_clear(loaded_vmcs->vmcs);
2584
2585         loaded_vmcs->shadow_vmcs = NULL;
2586         loaded_vmcs->hv_timer_soft_disabled = false;
2587         loaded_vmcs->cpu = -1;
2588         loaded_vmcs->launched = 0;
2589
2590         if (cpu_has_vmx_msr_bitmap()) {
2591                 loaded_vmcs->msr_bitmap = (unsigned long *)
2592                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2593                 if (!loaded_vmcs->msr_bitmap)
2594                         goto out_vmcs;
2595                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2596
2597                 if (IS_ENABLED(CONFIG_HYPERV) &&
2598                     static_branch_unlikely(&enable_evmcs) &&
2599                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2600                         struct hv_enlightened_vmcs *evmcs =
2601                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2602
2603                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2604                 }
2605         }
2606
2607         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2608         memset(&loaded_vmcs->controls_shadow, 0,
2609                 sizeof(struct vmcs_controls_shadow));
2610
2611         return 0;
2612
2613 out_vmcs:
2614         free_loaded_vmcs(loaded_vmcs);
2615         return -ENOMEM;
2616 }
2617
2618 static void free_kvm_area(void)
2619 {
2620         int cpu;
2621
2622         for_each_possible_cpu(cpu) {
2623                 free_vmcs(per_cpu(vmxarea, cpu));
2624                 per_cpu(vmxarea, cpu) = NULL;
2625         }
2626 }
2627
2628 static __init int alloc_kvm_area(void)
2629 {
2630         int cpu;
2631
2632         for_each_possible_cpu(cpu) {
2633                 struct vmcs *vmcs;
2634
2635                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2636                 if (!vmcs) {
2637                         free_kvm_area();
2638                         return -ENOMEM;
2639                 }
2640
2641                 /*
2642                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2643                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2644                  * revision_id reported by MSR_IA32_VMX_BASIC.
2645                  *
2646                  * However, even though not explicitly documented by
2647                  * TLFS, VMXArea passed as VMXON argument should
2648                  * still be marked with revision_id reported by
2649                  * physical CPU.
2650                  */
2651                 if (static_branch_unlikely(&enable_evmcs))
2652                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2653
2654                 per_cpu(vmxarea, cpu) = vmcs;
2655         }
2656         return 0;
2657 }
2658
2659 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2660                 struct kvm_segment *save)
2661 {
2662         if (!emulate_invalid_guest_state) {
2663                 /*
2664                  * CS and SS RPL should be equal during guest entry according
2665                  * to VMX spec, but in reality it is not always so. Since vcpu
2666                  * is in the middle of the transition from real mode to
2667                  * protected mode it is safe to assume that RPL 0 is a good
2668                  * default value.
2669                  */
2670                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2671                         save->selector &= ~SEGMENT_RPL_MASK;
2672                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2673                 save->s = 1;
2674         }
2675         vmx_set_segment(vcpu, save, seg);
2676 }
2677
2678 static void enter_pmode(struct kvm_vcpu *vcpu)
2679 {
2680         unsigned long flags;
2681         struct vcpu_vmx *vmx = to_vmx(vcpu);
2682
2683         /*
2684          * Update real mode segment cache. It may be not up-to-date if sement
2685          * register was written while vcpu was in a guest mode.
2686          */
2687         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2688         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2689         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2690         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2691         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2692         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2693
2694         vmx->rmode.vm86_active = 0;
2695
2696         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2697
2698         flags = vmcs_readl(GUEST_RFLAGS);
2699         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2700         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2701         vmcs_writel(GUEST_RFLAGS, flags);
2702
2703         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2704                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2705
2706         update_exception_bitmap(vcpu);
2707
2708         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2709         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2710         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2711         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2712         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2713         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2714 }
2715
2716 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2717 {
2718         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2719         struct kvm_segment var = *save;
2720
2721         var.dpl = 0x3;
2722         if (seg == VCPU_SREG_CS)
2723                 var.type = 0x3;
2724
2725         if (!emulate_invalid_guest_state) {
2726                 var.selector = var.base >> 4;
2727                 var.base = var.base & 0xffff0;
2728                 var.limit = 0xffff;
2729                 var.g = 0;
2730                 var.db = 0;
2731                 var.present = 1;
2732                 var.s = 1;
2733                 var.l = 0;
2734                 var.unusable = 0;
2735                 var.type = 0x3;
2736                 var.avl = 0;
2737                 if (save->base & 0xf)
2738                         printk_once(KERN_WARNING "kvm: segment base is not "
2739                                         "paragraph aligned when entering "
2740                                         "protected mode (seg=%d)", seg);
2741         }
2742
2743         vmcs_write16(sf->selector, var.selector);
2744         vmcs_writel(sf->base, var.base);
2745         vmcs_write32(sf->limit, var.limit);
2746         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2747 }
2748
2749 static void enter_rmode(struct kvm_vcpu *vcpu)
2750 {
2751         unsigned long flags;
2752         struct vcpu_vmx *vmx = to_vmx(vcpu);
2753         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2754
2755         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2756         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2757         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2758         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2759         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2760         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2761         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2762
2763         vmx->rmode.vm86_active = 1;
2764
2765         /*
2766          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2767          * vcpu. Warn the user that an update is overdue.
2768          */
2769         if (!kvm_vmx->tss_addr)
2770                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2771                              "called before entering vcpu\n");
2772
2773         vmx_segment_cache_clear(vmx);
2774
2775         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2776         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2777         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2778
2779         flags = vmcs_readl(GUEST_RFLAGS);
2780         vmx->rmode.save_rflags = flags;
2781
2782         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2783
2784         vmcs_writel(GUEST_RFLAGS, flags);
2785         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2786         update_exception_bitmap(vcpu);
2787
2788         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2789         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2790         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2791         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2792         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2793         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2794
2795         kvm_mmu_reset_context(vcpu);
2796 }
2797
2798 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2799 {
2800         struct vcpu_vmx *vmx = to_vmx(vcpu);
2801         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2802
2803         if (!msr)
2804                 return;
2805
2806         vcpu->arch.efer = efer;
2807         if (efer & EFER_LMA) {
2808                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2809                 msr->data = efer;
2810         } else {
2811                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2812
2813                 msr->data = efer & ~EFER_LME;
2814         }
2815         setup_msrs(vmx);
2816 }
2817
2818 #ifdef CONFIG_X86_64
2819
2820 static void enter_lmode(struct kvm_vcpu *vcpu)
2821 {
2822         u32 guest_tr_ar;
2823
2824         vmx_segment_cache_clear(to_vmx(vcpu));
2825
2826         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2827         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2828                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2829                                      __func__);
2830                 vmcs_write32(GUEST_TR_AR_BYTES,
2831                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2832                              | VMX_AR_TYPE_BUSY_64_TSS);
2833         }
2834         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2835 }
2836
2837 static void exit_lmode(struct kvm_vcpu *vcpu)
2838 {
2839         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2840         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2841 }
2842
2843 #endif
2844
2845 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2846 {
2847         struct vcpu_vmx *vmx = to_vmx(vcpu);
2848
2849         /*
2850          * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2851          * the CPU is not required to invalidate guest-physical mappings on
2852          * VM-Entry, even if VPID is disabled.  Guest-physical mappings are
2853          * associated with the root EPT structure and not any particular VPID
2854          * (INVVPID also isn't required to invalidate guest-physical mappings).
2855          */
2856         if (enable_ept) {
2857                 ept_sync_global();
2858         } else if (enable_vpid) {
2859                 if (cpu_has_vmx_invvpid_global()) {
2860                         vpid_sync_vcpu_global();
2861                 } else {
2862                         vpid_sync_vcpu_single(vmx->vpid);
2863                         vpid_sync_vcpu_single(vmx->nested.vpid02);
2864                 }
2865         }
2866 }
2867
2868 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2869 {
2870         u64 root_hpa = vcpu->arch.mmu->root_hpa;
2871
2872         /* No flush required if the current context is invalid. */
2873         if (!VALID_PAGE(root_hpa))
2874                 return;
2875
2876         if (enable_ept)
2877                 ept_sync_context(construct_eptp(vcpu, root_hpa));
2878         else if (!is_guest_mode(vcpu))
2879                 vpid_sync_context(to_vmx(vcpu)->vpid);
2880         else
2881                 vpid_sync_context(nested_get_vpid02(vcpu));
2882 }
2883
2884 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2885 {
2886         /*
2887          * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2888          * vmx_flush_tlb_guest() for an explanation of why this is ok.
2889          */
2890         vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2891 }
2892
2893 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2894 {
2895         /*
2896          * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2897          * or a vpid couldn't be allocated for this vCPU.  VM-Enter and VM-Exit
2898          * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2899          * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2900          * i.e. no explicit INVVPID is necessary.
2901          */
2902         vpid_sync_context(to_vmx(vcpu)->vpid);
2903 }
2904
2905 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2906 {
2907         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2908
2909         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2910         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2911 }
2912
2913 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2914 {
2915         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2916
2917         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2918         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2919 }
2920
2921 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2922 {
2923         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2924
2925         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2926                 return;
2927
2928         if (is_pae_paging(vcpu)) {
2929                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2930                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2931                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2932                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2933         }
2934 }
2935
2936 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2937 {
2938         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2939
2940         if (is_pae_paging(vcpu)) {
2941                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2942                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2943                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2944                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2945         }
2946
2947         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2948 }
2949
2950 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2951                                         unsigned long cr0,
2952                                         struct kvm_vcpu *vcpu)
2953 {
2954         struct vcpu_vmx *vmx = to_vmx(vcpu);
2955
2956         if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2957                 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2958         if (!(cr0 & X86_CR0_PG)) {
2959                 /* From paging/starting to nonpaging */
2960                 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2961                                           CPU_BASED_CR3_STORE_EXITING);
2962                 vcpu->arch.cr0 = cr0;
2963                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2964         } else if (!is_paging(vcpu)) {
2965                 /* From nonpaging to paging */
2966                 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2967                                             CPU_BASED_CR3_STORE_EXITING);
2968                 vcpu->arch.cr0 = cr0;
2969                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2970         }
2971
2972         if (!(cr0 & X86_CR0_WP))
2973                 *hw_cr0 &= ~X86_CR0_WP;
2974 }
2975
2976 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2977 {
2978         struct vcpu_vmx *vmx = to_vmx(vcpu);
2979         unsigned long hw_cr0;
2980
2981         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2982         if (enable_unrestricted_guest)
2983                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2984         else {
2985                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2986
2987                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2988                         enter_pmode(vcpu);
2989
2990                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2991                         enter_rmode(vcpu);
2992         }
2993
2994 #ifdef CONFIG_X86_64
2995         if (vcpu->arch.efer & EFER_LME) {
2996                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2997                         enter_lmode(vcpu);
2998                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2999                         exit_lmode(vcpu);
3000         }
3001 #endif
3002
3003         if (enable_ept && !enable_unrestricted_guest)
3004                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3005
3006         vmcs_writel(CR0_READ_SHADOW, cr0);
3007         vmcs_writel(GUEST_CR0, hw_cr0);
3008         vcpu->arch.cr0 = cr0;
3009
3010         /* depends on vcpu->arch.cr0 to be set to a new value */
3011         vmx->emulation_required = emulation_required(vcpu);
3012 }
3013
3014 static int get_ept_level(struct kvm_vcpu *vcpu)
3015 {
3016         if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu)))
3017                 return vmx_eptp_page_walk_level(nested_ept_get_eptp(vcpu));
3018         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
3019                 return 5;
3020         return 4;
3021 }
3022
3023 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
3024 {
3025         u64 eptp = VMX_EPTP_MT_WB;
3026
3027         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3028
3029         if (enable_ept_ad_bits &&
3030             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3031                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3032         eptp |= (root_hpa & PAGE_MASK);
3033
3034         return eptp;
3035 }
3036
3037 void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long pgd)
3038 {
3039         struct kvm *kvm = vcpu->kvm;
3040         bool update_guest_cr3 = true;
3041         unsigned long guest_cr3;
3042         u64 eptp;
3043
3044         if (enable_ept) {
3045                 eptp = construct_eptp(vcpu, pgd);
3046                 vmcs_write64(EPT_POINTER, eptp);
3047
3048                 if (kvm_x86_ops.tlb_remote_flush) {
3049                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3050                         to_vmx(vcpu)->ept_pointer = eptp;
3051                         to_kvm_vmx(kvm)->ept_pointers_match
3052                                 = EPT_POINTERS_CHECK;
3053                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3054                 }
3055
3056                 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3057                 if (is_guest_mode(vcpu))
3058                         update_guest_cr3 = false;
3059                 else if (!enable_unrestricted_guest && !is_paging(vcpu))
3060                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3061                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3062                         guest_cr3 = vcpu->arch.cr3;
3063                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3064                         update_guest_cr3 = false;
3065                 ept_load_pdptrs(vcpu);
3066         } else {
3067                 guest_cr3 = pgd;
3068         }
3069
3070         if (update_guest_cr3)
3071                 vmcs_writel(GUEST_CR3, guest_cr3);
3072 }
3073
3074 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3075 {
3076         struct vcpu_vmx *vmx = to_vmx(vcpu);
3077         /*
3078          * Pass through host's Machine Check Enable value to hw_cr4, which
3079          * is in force while we are in guest mode.  Do not let guests control
3080          * this bit, even if host CR4.MCE == 0.
3081          */
3082         unsigned long hw_cr4;
3083
3084         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3085         if (enable_unrestricted_guest)
3086                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3087         else if (vmx->rmode.vm86_active)
3088                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3089         else
3090                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3091
3092         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3093                 if (cr4 & X86_CR4_UMIP) {
3094                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3095                         hw_cr4 &= ~X86_CR4_UMIP;
3096                 } else if (!is_guest_mode(vcpu) ||
3097                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3098                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3099                 }
3100         }
3101
3102         if (cr4 & X86_CR4_VMXE) {
3103                 /*
3104                  * To use VMXON (and later other VMX instructions), a guest
3105                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3106                  * So basically the check on whether to allow nested VMX
3107                  * is here.  We operate under the default treatment of SMM,
3108                  * so VMX cannot be enabled under SMM.
3109                  */
3110                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3111                         return 1;
3112         }
3113
3114         if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3115                 return 1;
3116
3117         vcpu->arch.cr4 = cr4;
3118
3119         if (!enable_unrestricted_guest) {
3120                 if (enable_ept) {
3121                         if (!is_paging(vcpu)) {
3122                                 hw_cr4 &= ~X86_CR4_PAE;
3123                                 hw_cr4 |= X86_CR4_PSE;
3124                         } else if (!(cr4 & X86_CR4_PAE)) {
3125                                 hw_cr4 &= ~X86_CR4_PAE;
3126                         }
3127                 }
3128
3129                 /*
3130                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3131                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3132                  * to be manually disabled when guest switches to non-paging
3133                  * mode.
3134                  *
3135                  * If !enable_unrestricted_guest, the CPU is always running
3136                  * with CR0.PG=1 and CR4 needs to be modified.
3137                  * If enable_unrestricted_guest, the CPU automatically
3138                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3139                  */
3140                 if (!is_paging(vcpu))
3141                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3142         }
3143
3144         vmcs_writel(CR4_READ_SHADOW, cr4);
3145         vmcs_writel(GUEST_CR4, hw_cr4);
3146         return 0;
3147 }
3148
3149 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3150 {
3151         struct vcpu_vmx *vmx = to_vmx(vcpu);
3152         u32 ar;
3153
3154         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3155                 *var = vmx->rmode.segs[seg];
3156                 if (seg == VCPU_SREG_TR
3157                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3158                         return;
3159                 var->base = vmx_read_guest_seg_base(vmx, seg);
3160                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3161                 return;
3162         }
3163         var->base = vmx_read_guest_seg_base(vmx, seg);
3164         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3165         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3166         ar = vmx_read_guest_seg_ar(vmx, seg);
3167         var->unusable = (ar >> 16) & 1;
3168         var->type = ar & 15;
3169         var->s = (ar >> 4) & 1;
3170         var->dpl = (ar >> 5) & 3;
3171         /*
3172          * Some userspaces do not preserve unusable property. Since usable
3173          * segment has to be present according to VMX spec we can use present
3174          * property to amend userspace bug by making unusable segment always
3175          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3176          * segment as unusable.
3177          */
3178         var->present = !var->unusable;
3179         var->avl = (ar >> 12) & 1;
3180         var->l = (ar >> 13) & 1;
3181         var->db = (ar >> 14) & 1;
3182         var->g = (ar >> 15) & 1;
3183 }
3184
3185 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3186 {
3187         struct kvm_segment s;
3188
3189         if (to_vmx(vcpu)->rmode.vm86_active) {
3190                 vmx_get_segment(vcpu, &s, seg);
3191                 return s.base;
3192         }
3193         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3194 }
3195
3196 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3197 {
3198         struct vcpu_vmx *vmx = to_vmx(vcpu);
3199
3200         if (unlikely(vmx->rmode.vm86_active))
3201                 return 0;
3202         else {
3203                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3204                 return VMX_AR_DPL(ar);
3205         }
3206 }
3207
3208 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3209 {
3210         u32 ar;
3211
3212         if (var->unusable || !var->present)
3213                 ar = 1 << 16;
3214         else {
3215                 ar = var->type & 15;
3216                 ar |= (var->s & 1) << 4;
3217                 ar |= (var->dpl & 3) << 5;
3218                 ar |= (var->present & 1) << 7;
3219                 ar |= (var->avl & 1) << 12;
3220                 ar |= (var->l & 1) << 13;
3221                 ar |= (var->db & 1) << 14;
3222                 ar |= (var->g & 1) << 15;
3223         }
3224
3225         return ar;
3226 }
3227
3228 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3229 {
3230         struct vcpu_vmx *vmx = to_vmx(vcpu);
3231         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3232
3233         vmx_segment_cache_clear(vmx);
3234
3235         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3236                 vmx->rmode.segs[seg] = *var;
3237                 if (seg == VCPU_SREG_TR)
3238                         vmcs_write16(sf->selector, var->selector);
3239                 else if (var->s)
3240                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3241                 goto out;
3242         }
3243
3244         vmcs_writel(sf->base, var->base);
3245         vmcs_write32(sf->limit, var->limit);
3246         vmcs_write16(sf->selector, var->selector);
3247
3248         /*
3249          *   Fix the "Accessed" bit in AR field of segment registers for older
3250          * qemu binaries.
3251          *   IA32 arch specifies that at the time of processor reset the
3252          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3253          * is setting it to 0 in the userland code. This causes invalid guest
3254          * state vmexit when "unrestricted guest" mode is turned on.
3255          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3256          * tree. Newer qemu binaries with that qemu fix would not need this
3257          * kvm hack.
3258          */
3259         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3260                 var->type |= 0x1; /* Accessed */
3261
3262         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3263
3264 out:
3265         vmx->emulation_required = emulation_required(vcpu);
3266 }
3267
3268 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3269 {
3270         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3271
3272         *db = (ar >> 14) & 1;
3273         *l = (ar >> 13) & 1;
3274 }
3275
3276 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3277 {
3278         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3279         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3280 }
3281
3282 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3283 {
3284         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3285         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3286 }
3287
3288 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3289 {
3290         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3291         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3292 }
3293
3294 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3295 {
3296         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3297         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3298 }
3299
3300 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3301 {
3302         struct kvm_segment var;
3303         u32 ar;
3304
3305         vmx_get_segment(vcpu, &var, seg);
3306         var.dpl = 0x3;
3307         if (seg == VCPU_SREG_CS)
3308                 var.type = 0x3;
3309         ar = vmx_segment_access_rights(&var);
3310
3311         if (var.base != (var.selector << 4))
3312                 return false;
3313         if (var.limit != 0xffff)
3314                 return false;
3315         if (ar != 0xf3)
3316                 return false;
3317
3318         return true;
3319 }
3320
3321 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3322 {
3323         struct kvm_segment cs;
3324         unsigned int cs_rpl;
3325
3326         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3327         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3328
3329         if (cs.unusable)
3330                 return false;
3331         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3332                 return false;
3333         if (!cs.s)
3334                 return false;
3335         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3336                 if (cs.dpl > cs_rpl)
3337                         return false;
3338         } else {
3339                 if (cs.dpl != cs_rpl)
3340                         return false;
3341         }
3342         if (!cs.present)
3343                 return false;
3344
3345         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3346         return true;
3347 }
3348
3349 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3350 {
3351         struct kvm_segment ss;
3352         unsigned int ss_rpl;
3353
3354         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3355         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3356
3357         if (ss.unusable)
3358                 return true;
3359         if (ss.type != 3 && ss.type != 7)
3360                 return false;
3361         if (!ss.s)
3362                 return false;
3363         if (ss.dpl != ss_rpl) /* DPL != RPL */
3364                 return false;
3365         if (!ss.present)
3366                 return false;
3367
3368         return true;
3369 }
3370
3371 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3372 {
3373         struct kvm_segment var;
3374         unsigned int rpl;
3375
3376         vmx_get_segment(vcpu, &var, seg);
3377         rpl = var.selector & SEGMENT_RPL_MASK;
3378
3379         if (var.unusable)
3380                 return true;
3381         if (!var.s)
3382                 return false;
3383         if (!var.present)
3384                 return false;
3385         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3386                 if (var.dpl < rpl) /* DPL < RPL */
3387                         return false;
3388         }
3389
3390         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3391          * rights flags
3392          */
3393         return true;
3394 }
3395
3396 static bool tr_valid(struct kvm_vcpu *vcpu)
3397 {
3398         struct kvm_segment tr;
3399
3400         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3401
3402         if (tr.unusable)
3403                 return false;
3404         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3405                 return false;
3406         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3407                 return false;
3408         if (!tr.present)
3409                 return false;
3410
3411         return true;
3412 }
3413
3414 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3415 {
3416         struct kvm_segment ldtr;
3417
3418         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3419
3420         if (ldtr.unusable)
3421                 return true;
3422         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3423                 return false;
3424         if (ldtr.type != 2)
3425                 return false;
3426         if (!ldtr.present)
3427                 return false;
3428
3429         return true;
3430 }
3431
3432 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3433 {
3434         struct kvm_segment cs, ss;
3435
3436         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3437         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3438
3439         return ((cs.selector & SEGMENT_RPL_MASK) ==
3440                  (ss.selector & SEGMENT_RPL_MASK));
3441 }
3442
3443 /*
3444  * Check if guest state is valid. Returns true if valid, false if
3445  * not.
3446  * We assume that registers are always usable
3447  */
3448 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3449 {
3450         if (enable_unrestricted_guest)
3451                 return true;
3452
3453         /* real mode guest state checks */
3454         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3455                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3456                         return false;
3457                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3458                         return false;
3459                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3460                         return false;
3461                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3462                         return false;
3463                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3464                         return false;
3465                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3466                         return false;
3467         } else {
3468         /* protected mode guest state checks */
3469                 if (!cs_ss_rpl_check(vcpu))
3470                         return false;
3471                 if (!code_segment_valid(vcpu))
3472                         return false;
3473                 if (!stack_segment_valid(vcpu))
3474                         return false;
3475                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3476                         return false;
3477                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3478                         return false;
3479                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3480                         return false;
3481                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3482                         return false;
3483                 if (!tr_valid(vcpu))
3484                         return false;
3485                 if (!ldtr_valid(vcpu))
3486                         return false;
3487         }
3488         /* TODO:
3489          * - Add checks on RIP
3490          * - Add checks on RFLAGS
3491          */
3492
3493         return true;
3494 }
3495
3496 static int init_rmode_tss(struct kvm *kvm)
3497 {
3498         gfn_t fn;
3499         u16 data = 0;
3500         int idx, r;
3501
3502         idx = srcu_read_lock(&kvm->srcu);
3503         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3504         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3505         if (r < 0)
3506                 goto out;
3507         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3508         r = kvm_write_guest_page(kvm, fn++, &data,
3509                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3510         if (r < 0)
3511                 goto out;
3512         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3513         if (r < 0)
3514                 goto out;
3515         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3516         if (r < 0)
3517                 goto out;
3518         data = ~0;
3519         r = kvm_write_guest_page(kvm, fn, &data,
3520                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3521                                  sizeof(u8));
3522 out:
3523         srcu_read_unlock(&kvm->srcu, idx);
3524         return r;
3525 }
3526
3527 static int init_rmode_identity_map(struct kvm *kvm)
3528 {
3529         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3530         int i, r = 0;
3531         kvm_pfn_t identity_map_pfn;
3532         u32 tmp;
3533
3534         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3535         mutex_lock(&kvm->slots_lock);
3536
3537         if (likely(kvm_vmx->ept_identity_pagetable_done))
3538                 goto out;
3539
3540         if (!kvm_vmx->ept_identity_map_addr)
3541                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3542         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3543
3544         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3545                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3546         if (r < 0)
3547                 goto out;
3548
3549         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3550         if (r < 0)
3551                 goto out;
3552         /* Set up identity-mapping pagetable for EPT in real mode */
3553         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3554                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3555                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3556                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3557                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3558                 if (r < 0)
3559                         goto out;
3560         }
3561         kvm_vmx->ept_identity_pagetable_done = true;
3562
3563 out:
3564         mutex_unlock(&kvm->slots_lock);
3565         return r;
3566 }
3567
3568 static void seg_setup(int seg)
3569 {
3570         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3571         unsigned int ar;
3572
3573         vmcs_write16(sf->selector, 0);
3574         vmcs_writel(sf->base, 0);
3575         vmcs_write32(sf->limit, 0xffff);
3576         ar = 0x93;
3577         if (seg == VCPU_SREG_CS)
3578                 ar |= 0x08; /* code segment */
3579
3580         vmcs_write32(sf->ar_bytes, ar);
3581 }
3582
3583 static int alloc_apic_access_page(struct kvm *kvm)
3584 {
3585         struct page *page;
3586         int r = 0;
3587
3588         mutex_lock(&kvm->slots_lock);
3589         if (kvm->arch.apic_access_page_done)
3590                 goto out;
3591         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3592                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3593         if (r)
3594                 goto out;
3595
3596         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3597         if (is_error_page(page)) {
3598                 r = -EFAULT;
3599                 goto out;
3600         }
3601
3602         /*
3603          * Do not pin the page in memory, so that memory hot-unplug
3604          * is able to migrate it.
3605          */
3606         put_page(page);
3607         kvm->arch.apic_access_page_done = true;
3608 out:
3609         mutex_unlock(&kvm->slots_lock);
3610         return r;
3611 }
3612
3613 int allocate_vpid(void)
3614 {
3615         int vpid;
3616
3617         if (!enable_vpid)
3618                 return 0;
3619         spin_lock(&vmx_vpid_lock);
3620         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3621         if (vpid < VMX_NR_VPIDS)
3622                 __set_bit(vpid, vmx_vpid_bitmap);
3623         else
3624                 vpid = 0;
3625         spin_unlock(&vmx_vpid_lock);
3626         return vpid;
3627 }
3628
3629 void free_vpid(int vpid)
3630 {
3631         if (!enable_vpid || vpid == 0)
3632                 return;
3633         spin_lock(&vmx_vpid_lock);
3634         __clear_bit(vpid, vmx_vpid_bitmap);
3635         spin_unlock(&vmx_vpid_lock);
3636 }
3637
3638 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3639                                                           u32 msr, int type)
3640 {
3641         int f = sizeof(unsigned long);
3642
3643         if (!cpu_has_vmx_msr_bitmap())
3644                 return;
3645
3646         if (static_branch_unlikely(&enable_evmcs))
3647                 evmcs_touch_msr_bitmap();
3648
3649         /*
3650          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3651          * have the write-low and read-high bitmap offsets the wrong way round.
3652          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3653          */
3654         if (msr <= 0x1fff) {
3655                 if (type & MSR_TYPE_R)
3656                         /* read-low */
3657                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3658
3659                 if (type & MSR_TYPE_W)
3660                         /* write-low */
3661                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3662
3663         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3664                 msr &= 0x1fff;
3665                 if (type & MSR_TYPE_R)
3666                         /* read-high */
3667                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3668
3669                 if (type & MSR_TYPE_W)
3670                         /* write-high */
3671                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3672
3673         }
3674 }
3675
3676 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3677                                                          u32 msr, int type)
3678 {
3679         int f = sizeof(unsigned long);
3680
3681         if (!cpu_has_vmx_msr_bitmap())
3682                 return;
3683
3684         if (static_branch_unlikely(&enable_evmcs))
3685                 evmcs_touch_msr_bitmap();
3686
3687         /*
3688          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3689          * have the write-low and read-high bitmap offsets the wrong way round.
3690          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3691          */
3692         if (msr <= 0x1fff) {
3693                 if (type & MSR_TYPE_R)
3694                         /* read-low */
3695                         __set_bit(msr, msr_bitmap + 0x000 / f);
3696
3697                 if (type & MSR_TYPE_W)
3698                         /* write-low */
3699                         __set_bit(msr, msr_bitmap + 0x800 / f);
3700
3701         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3702                 msr &= 0x1fff;
3703                 if (type & MSR_TYPE_R)
3704                         /* read-high */
3705                         __set_bit(msr, msr_bitmap + 0x400 / f);
3706
3707                 if (type & MSR_TYPE_W)
3708                         /* write-high */
3709                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3710
3711         }
3712 }
3713
3714 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3715                                                       u32 msr, int type, bool value)
3716 {
3717         if (value)
3718                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3719         else
3720                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3721 }
3722
3723 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3724 {
3725         u8 mode = 0;
3726
3727         if (cpu_has_secondary_exec_ctrls() &&
3728             (secondary_exec_controls_get(to_vmx(vcpu)) &
3729              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3730                 mode |= MSR_BITMAP_MODE_X2APIC;
3731                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3732                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3733         }
3734
3735         return mode;
3736 }
3737
3738 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3739                                          u8 mode)
3740 {
3741         int msr;
3742
3743         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3744                 unsigned word = msr / BITS_PER_LONG;
3745                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3746                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3747         }
3748
3749         if (mode & MSR_BITMAP_MODE_X2APIC) {
3750                 /*
3751                  * TPR reads and writes can be virtualized even if virtual interrupt
3752                  * delivery is not in use.
3753                  */
3754                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3755                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3756                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3757                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3758                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3759                 }
3760         }
3761 }
3762
3763 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3764 {
3765         struct vcpu_vmx *vmx = to_vmx(vcpu);
3766         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3767         u8 mode = vmx_msr_bitmap_mode(vcpu);
3768         u8 changed = mode ^ vmx->msr_bitmap_mode;
3769
3770         if (!changed)
3771                 return;
3772
3773         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3774                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3775
3776         vmx->msr_bitmap_mode = mode;
3777 }
3778
3779 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3780 {
3781         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3782         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3783         u32 i;
3784
3785         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3786                                                         MSR_TYPE_RW, flag);
3787         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3788                                                         MSR_TYPE_RW, flag);
3789         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3790                                                         MSR_TYPE_RW, flag);
3791         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3792                                                         MSR_TYPE_RW, flag);
3793         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3794                 vmx_set_intercept_for_msr(msr_bitmap,
3795                         MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3796                 vmx_set_intercept_for_msr(msr_bitmap,
3797                         MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3798         }
3799 }
3800
3801 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3802 {
3803         struct vcpu_vmx *vmx = to_vmx(vcpu);
3804         void *vapic_page;
3805         u32 vppr;
3806         int rvi;
3807
3808         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3809                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3810                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3811                 return false;
3812
3813         rvi = vmx_get_rvi();
3814
3815         vapic_page = vmx->nested.virtual_apic_map.hva;
3816         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3817
3818         return ((rvi & 0xf0) > (vppr & 0xf0));
3819 }
3820
3821 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3822                                                      bool nested)
3823 {
3824 #ifdef CONFIG_SMP
3825         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3826
3827         if (vcpu->mode == IN_GUEST_MODE) {
3828                 /*
3829                  * The vector of interrupt to be delivered to vcpu had
3830                  * been set in PIR before this function.
3831                  *
3832                  * Following cases will be reached in this block, and
3833                  * we always send a notification event in all cases as
3834                  * explained below.
3835                  *
3836                  * Case 1: vcpu keeps in non-root mode. Sending a
3837                  * notification event posts the interrupt to vcpu.
3838                  *
3839                  * Case 2: vcpu exits to root mode and is still
3840                  * runnable. PIR will be synced to vIRR before the
3841                  * next vcpu entry. Sending a notification event in
3842                  * this case has no effect, as vcpu is not in root
3843                  * mode.
3844                  *
3845                  * Case 3: vcpu exits to root mode and is blocked.
3846                  * vcpu_block() has already synced PIR to vIRR and
3847                  * never blocks vcpu if vIRR is not cleared. Therefore,
3848                  * a blocked vcpu here does not wait for any requested
3849                  * interrupts in PIR, and sending a notification event
3850                  * which has no effect is safe here.
3851                  */
3852
3853                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3854                 return true;
3855         }
3856 #endif
3857         return false;
3858 }
3859
3860 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3861                                                 int vector)
3862 {
3863         struct vcpu_vmx *vmx = to_vmx(vcpu);
3864
3865         if (is_guest_mode(vcpu) &&
3866             vector == vmx->nested.posted_intr_nv) {
3867                 /*
3868                  * If a posted intr is not recognized by hardware,
3869                  * we will accomplish it in the next vmentry.
3870                  */
3871                 vmx->nested.pi_pending = true;
3872                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3873                 /* the PIR and ON have been set by L1. */
3874                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3875                         kvm_vcpu_kick(vcpu);
3876                 return 0;
3877         }
3878         return -1;
3879 }
3880 /*
3881  * Send interrupt to vcpu via posted interrupt way.
3882  * 1. If target vcpu is running(non-root mode), send posted interrupt
3883  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3884  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3885  * interrupt from PIR in next vmentry.
3886  */
3887 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3888 {
3889         struct vcpu_vmx *vmx = to_vmx(vcpu);
3890         int r;
3891
3892         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3893         if (!r)
3894                 return 0;
3895
3896         if (!vcpu->arch.apicv_active)
3897                 return -1;
3898
3899         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3900                 return 0;
3901
3902         /* If a previous notification has sent the IPI, nothing to do.  */
3903         if (pi_test_and_set_on(&vmx->pi_desc))
3904                 return 0;
3905
3906         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3907                 kvm_vcpu_kick(vcpu);
3908
3909         return 0;
3910 }
3911
3912 /*
3913  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3914  * will not change in the lifetime of the guest.
3915  * Note that host-state that does change is set elsewhere. E.g., host-state
3916  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3917  */
3918 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3919 {
3920         u32 low32, high32;
3921         unsigned long tmpl;
3922         unsigned long cr0, cr3, cr4;
3923
3924         cr0 = read_cr0();
3925         WARN_ON(cr0 & X86_CR0_TS);
3926         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3927
3928         /*
3929          * Save the most likely value for this task's CR3 in the VMCS.
3930          * We can't use __get_current_cr3_fast() because we're not atomic.
3931          */
3932         cr3 = __read_cr3();
3933         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
3934         vmx->loaded_vmcs->host_state.cr3 = cr3;
3935
3936         /* Save the most likely value for this task's CR4 in the VMCS. */
3937         cr4 = cr4_read_shadow();
3938         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
3939         vmx->loaded_vmcs->host_state.cr4 = cr4;
3940
3941         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3942 #ifdef CONFIG_X86_64
3943         /*
3944          * Load null selectors, so we can avoid reloading them in
3945          * vmx_prepare_switch_to_host(), in case userspace uses
3946          * the null selectors too (the expected case).
3947          */
3948         vmcs_write16(HOST_DS_SELECTOR, 0);
3949         vmcs_write16(HOST_ES_SELECTOR, 0);
3950 #else
3951         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3952         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3953 #endif
3954         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3955         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3956
3957         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
3958
3959         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3960
3961         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3962         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3963         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3964         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3965
3966         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3967                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3968                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3969         }
3970
3971         if (cpu_has_load_ia32_efer())
3972                 vmcs_write64(HOST_IA32_EFER, host_efer);
3973 }
3974
3975 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3976 {
3977         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3978         if (enable_ept)
3979                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3980         if (is_guest_mode(&vmx->vcpu))
3981                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3982                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3983         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3984 }
3985
3986 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3987 {
3988         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3989
3990         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3991                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3992
3993         if (!enable_vnmi)
3994                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3995
3996         if (!enable_preemption_timer)
3997                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3998
3999         return pin_based_exec_ctrl;
4000 }
4001
4002 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4003 {
4004         struct vcpu_vmx *vmx = to_vmx(vcpu);
4005
4006         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4007         if (cpu_has_secondary_exec_ctrls()) {
4008                 if (kvm_vcpu_apicv_active(vcpu))
4009                         secondary_exec_controls_setbit(vmx,
4010                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4011                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4012                 else
4013                         secondary_exec_controls_clearbit(vmx,
4014                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4015                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4016         }
4017
4018         if (cpu_has_vmx_msr_bitmap())
4019                 vmx_update_msr_bitmap(vcpu);
4020 }
4021
4022 u32 vmx_exec_control(struct vcpu_vmx *vmx)
4023 {
4024         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4025
4026         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4027                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4028
4029         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4030                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4031 #ifdef CONFIG_X86_64
4032                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4033                                 CPU_BASED_CR8_LOAD_EXITING;
4034 #endif
4035         }
4036         if (!enable_ept)
4037                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4038                                 CPU_BASED_CR3_LOAD_EXITING  |
4039                                 CPU_BASED_INVLPG_EXITING;
4040         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4041                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4042                                 CPU_BASED_MONITOR_EXITING);
4043         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4044                 exec_control &= ~CPU_BASED_HLT_EXITING;
4045         return exec_control;
4046 }
4047
4048
4049 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4050 {
4051         struct kvm_vcpu *vcpu = &vmx->vcpu;
4052
4053         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4054
4055         if (vmx_pt_mode_is_system())
4056                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4057         if (!cpu_need_virtualize_apic_accesses(vcpu))
4058                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4059         if (vmx->vpid == 0)
4060                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4061         if (!enable_ept) {
4062                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4063                 enable_unrestricted_guest = 0;
4064         }
4065         if (!enable_unrestricted_guest)
4066                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4067         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4068                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4069         if (!kvm_vcpu_apicv_active(vcpu))
4070                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4071                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4072         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4073
4074         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4075          * in vmx_set_cr4.  */
4076         exec_control &= ~SECONDARY_EXEC_DESC;
4077
4078         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4079            (handle_vmptrld).
4080            We can NOT enable shadow_vmcs here because we don't have yet
4081            a current VMCS12
4082         */
4083         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4084
4085         if (!enable_pml)
4086                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4087
4088         if (vmx_xsaves_supported()) {
4089                 /* Exposing XSAVES only when XSAVE is exposed */
4090                 bool xsaves_enabled =
4091                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4092                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4093                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4094
4095                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4096
4097                 if (!xsaves_enabled)
4098                         exec_control &= ~SECONDARY_EXEC_XSAVES;
4099
4100                 if (nested) {
4101                         if (xsaves_enabled)
4102                                 vmx->nested.msrs.secondary_ctls_high |=
4103                                         SECONDARY_EXEC_XSAVES;
4104                         else
4105                                 vmx->nested.msrs.secondary_ctls_high &=
4106                                         ~SECONDARY_EXEC_XSAVES;
4107                 }
4108         }
4109
4110         if (cpu_has_vmx_rdtscp()) {
4111                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4112                 if (!rdtscp_enabled)
4113                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
4114
4115                 if (nested) {
4116                         if (rdtscp_enabled)
4117                                 vmx->nested.msrs.secondary_ctls_high |=
4118                                         SECONDARY_EXEC_RDTSCP;
4119                         else
4120                                 vmx->nested.msrs.secondary_ctls_high &=
4121                                         ~SECONDARY_EXEC_RDTSCP;
4122                 }
4123         }
4124
4125         if (cpu_has_vmx_invpcid()) {
4126                 /* Exposing INVPCID only when PCID is exposed */
4127                 bool invpcid_enabled =
4128                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4129                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4130
4131                 if (!invpcid_enabled) {
4132                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4133                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4134                 }
4135
4136                 if (nested) {
4137                         if (invpcid_enabled)
4138                                 vmx->nested.msrs.secondary_ctls_high |=
4139                                         SECONDARY_EXEC_ENABLE_INVPCID;
4140                         else
4141                                 vmx->nested.msrs.secondary_ctls_high &=
4142                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
4143                 }
4144         }
4145
4146         if (vmx_rdrand_supported()) {
4147                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4148                 if (rdrand_enabled)
4149                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4150
4151                 if (nested) {
4152                         if (rdrand_enabled)
4153                                 vmx->nested.msrs.secondary_ctls_high |=
4154                                         SECONDARY_EXEC_RDRAND_EXITING;
4155                         else
4156                                 vmx->nested.msrs.secondary_ctls_high &=
4157                                         ~SECONDARY_EXEC_RDRAND_EXITING;
4158                 }
4159         }
4160
4161         if (vmx_rdseed_supported()) {
4162                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4163                 if (rdseed_enabled)
4164                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4165
4166                 if (nested) {
4167                         if (rdseed_enabled)
4168                                 vmx->nested.msrs.secondary_ctls_high |=
4169                                         SECONDARY_EXEC_RDSEED_EXITING;
4170                         else
4171                                 vmx->nested.msrs.secondary_ctls_high &=
4172                                         ~SECONDARY_EXEC_RDSEED_EXITING;
4173                 }
4174         }
4175
4176         if (vmx_waitpkg_supported()) {
4177                 bool waitpkg_enabled =
4178                         guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4179
4180                 if (!waitpkg_enabled)
4181                         exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4182
4183                 if (nested) {
4184                         if (waitpkg_enabled)
4185                                 vmx->nested.msrs.secondary_ctls_high |=
4186                                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4187                         else
4188                                 vmx->nested.msrs.secondary_ctls_high &=
4189                                         ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4190                 }
4191         }
4192
4193         vmx->secondary_exec_control = exec_control;
4194 }
4195
4196 static void ept_set_mmio_spte_mask(void)
4197 {
4198         /*
4199          * EPT Misconfigurations can be generated if the value of bits 2:0
4200          * of an EPT paging-structure entry is 110b (write/execute).
4201          */
4202         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4203                                    VMX_EPT_MISCONFIG_WX_VALUE, 0);
4204 }
4205
4206 #define VMX_XSS_EXIT_BITMAP 0
4207
4208 /*
4209  * Noting that the initialization of Guest-state Area of VMCS is in
4210  * vmx_vcpu_reset().
4211  */
4212 static void init_vmcs(struct vcpu_vmx *vmx)
4213 {
4214         if (nested)
4215                 nested_vmx_set_vmcs_shadowing_bitmap();
4216
4217         if (cpu_has_vmx_msr_bitmap())
4218                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4219
4220         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4221
4222         /* Control */
4223         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4224
4225         exec_controls_set(vmx, vmx_exec_control(vmx));
4226
4227         if (cpu_has_secondary_exec_ctrls()) {
4228                 vmx_compute_secondary_exec_control(vmx);
4229                 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4230         }
4231
4232         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4233                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4234                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4235                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4236                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4237
4238                 vmcs_write16(GUEST_INTR_STATUS, 0);
4239
4240                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4241                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4242         }
4243
4244         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4245                 vmcs_write32(PLE_GAP, ple_gap);
4246                 vmx->ple_window = ple_window;
4247                 vmx->ple_window_dirty = true;
4248         }
4249
4250         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4251         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4252         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4253
4254         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4255         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4256         vmx_set_constant_host_state(vmx);
4257         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4258         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4259
4260         if (cpu_has_vmx_vmfunc())
4261                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4262
4263         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4264         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4265         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4266         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4267         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4268
4269         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4270                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4271
4272         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4273
4274         /* 22.2.1, 20.8.1 */
4275         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4276
4277         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4278         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4279
4280         set_cr4_guest_host_mask(vmx);
4281
4282         if (vmx->vpid != 0)
4283                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4284
4285         if (vmx_xsaves_supported())
4286                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4287
4288         if (enable_pml) {
4289                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4290                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4291         }
4292
4293         if (cpu_has_vmx_encls_vmexit())
4294                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4295
4296         if (vmx_pt_mode_is_host_guest()) {
4297                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4298                 /* Bit[6~0] are forced to 1, writes are ignored. */
4299                 vmx->pt_desc.guest.output_mask = 0x7F;
4300                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4301         }
4302 }
4303
4304 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4305 {
4306         struct vcpu_vmx *vmx = to_vmx(vcpu);
4307         struct msr_data apic_base_msr;
4308         u64 cr0;
4309
4310         vmx->rmode.vm86_active = 0;
4311         vmx->spec_ctrl = 0;
4312
4313         vmx->msr_ia32_umwait_control = 0;
4314
4315         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4316         vmx->hv_deadline_tsc = -1;
4317         kvm_set_cr8(vcpu, 0);
4318
4319         if (!init_event) {
4320                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4321                                      MSR_IA32_APICBASE_ENABLE;
4322                 if (kvm_vcpu_is_reset_bsp(vcpu))
4323                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4324                 apic_base_msr.host_initiated = true;
4325                 kvm_set_apic_base(vcpu, &apic_base_msr);
4326         }
4327
4328         vmx_segment_cache_clear(vmx);
4329
4330         seg_setup(VCPU_SREG_CS);
4331         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4332         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4333
4334         seg_setup(VCPU_SREG_DS);
4335         seg_setup(VCPU_SREG_ES);
4336         seg_setup(VCPU_SREG_FS);
4337         seg_setup(VCPU_SREG_GS);
4338         seg_setup(VCPU_SREG_SS);
4339
4340         vmcs_write16(GUEST_TR_SELECTOR, 0);
4341         vmcs_writel(GUEST_TR_BASE, 0);
4342         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4343         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4344
4345         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4346         vmcs_writel(GUEST_LDTR_BASE, 0);
4347         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4348         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4349
4350         if (!init_event) {
4351                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4352                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4353                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4354                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4355         }
4356
4357         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4358         kvm_rip_write(vcpu, 0xfff0);
4359
4360         vmcs_writel(GUEST_GDTR_BASE, 0);
4361         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4362
4363         vmcs_writel(GUEST_IDTR_BASE, 0);
4364         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4365
4366         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4367         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4368         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4369         if (kvm_mpx_supported())
4370                 vmcs_write64(GUEST_BNDCFGS, 0);
4371
4372         setup_msrs(vmx);
4373
4374         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4375
4376         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4377                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4378                 if (cpu_need_tpr_shadow(vcpu))
4379                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4380                                      __pa(vcpu->arch.apic->regs));
4381                 vmcs_write32(TPR_THRESHOLD, 0);
4382         }
4383
4384         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4385
4386         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4387         vmx->vcpu.arch.cr0 = cr0;
4388         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4389         vmx_set_cr4(vcpu, 0);
4390         vmx_set_efer(vcpu, 0);
4391
4392         update_exception_bitmap(vcpu);
4393
4394         vpid_sync_context(vmx->vpid);
4395         if (init_event)
4396                 vmx_clear_hlt(vcpu);
4397 }
4398
4399 static void enable_irq_window(struct kvm_vcpu *vcpu)
4400 {
4401         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4402 }
4403
4404 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4405 {
4406         if (!enable_vnmi ||
4407             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4408                 enable_irq_window(vcpu);
4409                 return;
4410         }
4411
4412         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4413 }
4414
4415 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4416 {
4417         struct vcpu_vmx *vmx = to_vmx(vcpu);
4418         uint32_t intr;
4419         int irq = vcpu->arch.interrupt.nr;
4420
4421         trace_kvm_inj_virq(irq);
4422
4423         ++vcpu->stat.irq_injections;
4424         if (vmx->rmode.vm86_active) {
4425                 int inc_eip = 0;
4426                 if (vcpu->arch.interrupt.soft)
4427                         inc_eip = vcpu->arch.event_exit_inst_len;
4428                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4429                 return;
4430         }
4431         intr = irq | INTR_INFO_VALID_MASK;
4432         if (vcpu->arch.interrupt.soft) {
4433                 intr |= INTR_TYPE_SOFT_INTR;
4434                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4435                              vmx->vcpu.arch.event_exit_inst_len);
4436         } else
4437                 intr |= INTR_TYPE_EXT_INTR;
4438         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4439
4440         vmx_clear_hlt(vcpu);
4441 }
4442
4443 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4444 {
4445         struct vcpu_vmx *vmx = to_vmx(vcpu);
4446
4447         if (!enable_vnmi) {
4448                 /*
4449                  * Tracking the NMI-blocked state in software is built upon
4450                  * finding the next open IRQ window. This, in turn, depends on
4451                  * well-behaving guests: They have to keep IRQs disabled at
4452                  * least as long as the NMI handler runs. Otherwise we may
4453                  * cause NMI nesting, maybe breaking the guest. But as this is
4454                  * highly unlikely, we can live with the residual risk.
4455                  */
4456                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4457                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4458         }
4459
4460         ++vcpu->stat.nmi_injections;
4461         vmx->loaded_vmcs->nmi_known_unmasked = false;
4462
4463         if (vmx->rmode.vm86_active) {
4464                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4465                 return;
4466         }
4467
4468         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4469                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4470
4471         vmx_clear_hlt(vcpu);
4472 }
4473
4474 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4475 {
4476         struct vcpu_vmx *vmx = to_vmx(vcpu);
4477         bool masked;
4478
4479         if (!enable_vnmi)
4480                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4481         if (vmx->loaded_vmcs->nmi_known_unmasked)
4482                 return false;
4483         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4484         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4485         return masked;
4486 }
4487
4488 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4489 {
4490         struct vcpu_vmx *vmx = to_vmx(vcpu);
4491
4492         if (!enable_vnmi) {
4493                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4494                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4495                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4496                 }
4497         } else {
4498                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4499                 if (masked)
4500                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4501                                       GUEST_INTR_STATE_NMI);
4502                 else
4503                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4504                                         GUEST_INTR_STATE_NMI);
4505         }
4506 }
4507
4508 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4509 {
4510         if (to_vmx(vcpu)->nested.nested_run_pending)
4511                 return 0;
4512
4513         if (!enable_vnmi &&
4514             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4515                 return 0;
4516
4517         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4518                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4519                    | GUEST_INTR_STATE_NMI));
4520 }
4521
4522 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4523 {
4524         if (to_vmx(vcpu)->nested.nested_run_pending)
4525                 return false;
4526
4527         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4528                 return true;
4529
4530         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4531                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4532                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4533 }
4534
4535 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4536 {
4537         int ret;
4538
4539         if (enable_unrestricted_guest)
4540                 return 0;
4541
4542         mutex_lock(&kvm->slots_lock);
4543         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4544                                       PAGE_SIZE * 3);
4545         mutex_unlock(&kvm->slots_lock);
4546
4547         if (ret)
4548                 return ret;
4549         to_kvm_vmx(kvm)->tss_addr = addr;
4550         return init_rmode_tss(kvm);
4551 }
4552
4553 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4554 {
4555         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4556         return 0;
4557 }
4558
4559 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4560 {
4561         switch (vec) {
4562         case BP_VECTOR:
4563                 /*
4564                  * Update instruction length as we may reinject the exception
4565                  * from user space while in guest debugging mode.
4566                  */
4567                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4568                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4569                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4570                         return false;
4571                 /* fall through */
4572         case DB_VECTOR:
4573                 if (vcpu->guest_debug &
4574                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4575                         return false;
4576                 /* fall through */
4577         case DE_VECTOR:
4578         case OF_VECTOR:
4579         case BR_VECTOR:
4580         case UD_VECTOR:
4581         case DF_VECTOR:
4582         case SS_VECTOR:
4583         case GP_VECTOR:
4584         case MF_VECTOR:
4585                 return true;
4586         }
4587         return false;
4588 }
4589
4590 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4591                                   int vec, u32 err_code)
4592 {
4593         /*
4594          * Instruction with address size override prefix opcode 0x67
4595          * Cause the #SS fault with 0 error code in VM86 mode.
4596          */
4597         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4598                 if (kvm_emulate_instruction(vcpu, 0)) {
4599                         if (vcpu->arch.halt_request) {
4600                                 vcpu->arch.halt_request = 0;
4601                                 return kvm_vcpu_halt(vcpu);
4602                         }
4603                         return 1;
4604                 }
4605                 return 0;
4606         }
4607
4608         /*
4609          * Forward all other exceptions that are valid in real mode.
4610          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4611          *        the required debugging infrastructure rework.
4612          */
4613         kvm_queue_exception(vcpu, vec);
4614         return 1;
4615 }
4616
4617 /*
4618  * Trigger machine check on the host. We assume all the MSRs are already set up
4619  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4620  * We pass a fake environment to the machine check handler because we want
4621  * the guest to be always treated like user space, no matter what context
4622  * it used internally.
4623  */
4624 static void kvm_machine_check(void)
4625 {
4626 #if defined(CONFIG_X86_MCE)
4627         struct pt_regs regs = {
4628                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4629                 .flags = X86_EFLAGS_IF,
4630         };
4631
4632         do_machine_check(&regs, 0);
4633 #endif
4634 }
4635
4636 static int handle_machine_check(struct kvm_vcpu *vcpu)
4637 {
4638         /* handled by vmx_vcpu_run() */
4639         return 1;
4640 }
4641
4642 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4643 {
4644         struct vcpu_vmx *vmx = to_vmx(vcpu);
4645         struct kvm_run *kvm_run = vcpu->run;
4646         u32 intr_info, ex_no, error_code;
4647         unsigned long cr2, rip, dr6;
4648         u32 vect_info;
4649
4650         vect_info = vmx->idt_vectoring_info;
4651         intr_info = vmx->exit_intr_info;
4652
4653         if (is_machine_check(intr_info) || is_nmi(intr_info))
4654                 return 1; /* handled by handle_exception_nmi_irqoff() */
4655
4656         if (is_invalid_opcode(intr_info))
4657                 return handle_ud(vcpu);
4658
4659         error_code = 0;
4660         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4661                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4662
4663         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4664                 WARN_ON_ONCE(!enable_vmware_backdoor);
4665
4666                 /*
4667                  * VMware backdoor emulation on #GP interception only handles
4668                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4669                  * error code on #GP.
4670                  */
4671                 if (error_code) {
4672                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4673                         return 1;
4674                 }
4675                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4676         }
4677
4678         /*
4679          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4680          * MMIO, it is better to report an internal error.
4681          * See the comments in vmx_handle_exit.
4682          */
4683         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4684             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4685                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4686                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4687                 vcpu->run->internal.ndata = 3;
4688                 vcpu->run->internal.data[0] = vect_info;
4689                 vcpu->run->internal.data[1] = intr_info;
4690                 vcpu->run->internal.data[2] = error_code;
4691                 return 0;
4692         }
4693
4694         if (is_page_fault(intr_info)) {
4695                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4696                 /* EPT won't cause page fault directly */
4697                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4698                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4699         }
4700
4701         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4702
4703         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4704                 return handle_rmode_exception(vcpu, ex_no, error_code);
4705
4706         switch (ex_no) {
4707         case AC_VECTOR:
4708                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4709                 return 1;
4710         case DB_VECTOR:
4711                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4712                 if (!(vcpu->guest_debug &
4713                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4714                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4715                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4716                         if (is_icebp(intr_info))
4717                                 WARN_ON(!skip_emulated_instruction(vcpu));
4718
4719                         kvm_queue_exception(vcpu, DB_VECTOR);
4720                         return 1;
4721                 }
4722                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4723                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4724                 /* fall through */
4725         case BP_VECTOR:
4726                 /*
4727                  * Update instruction length as we may reinject #BP from
4728                  * user space while in guest debugging mode. Reading it for
4729                  * #DB as well causes no harm, it is not used in that case.
4730                  */
4731                 vmx->vcpu.arch.event_exit_inst_len =
4732                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4733                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4734                 rip = kvm_rip_read(vcpu);
4735                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4736                 kvm_run->debug.arch.exception = ex_no;
4737                 break;
4738         default:
4739                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4740                 kvm_run->ex.exception = ex_no;
4741                 kvm_run->ex.error_code = error_code;
4742                 break;
4743         }
4744         return 0;
4745 }
4746
4747 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4748 {
4749         ++vcpu->stat.irq_exits;
4750         return 1;
4751 }
4752
4753 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4754 {
4755         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4756         vcpu->mmio_needed = 0;
4757         return 0;
4758 }
4759
4760 static int handle_io(struct kvm_vcpu *vcpu)
4761 {
4762         unsigned long exit_qualification;
4763         int size, in, string;
4764         unsigned port;
4765
4766         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4767         string = (exit_qualification & 16) != 0;
4768
4769         ++vcpu->stat.io_exits;
4770
4771         if (string)
4772                 return kvm_emulate_instruction(vcpu, 0);
4773
4774         port = exit_qualification >> 16;
4775         size = (exit_qualification & 7) + 1;
4776         in = (exit_qualification & 8) != 0;
4777
4778         return kvm_fast_pio(vcpu, size, port, in);
4779 }
4780
4781 static void
4782 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4783 {
4784         /*
4785          * Patch in the VMCALL instruction:
4786          */
4787         hypercall[0] = 0x0f;
4788         hypercall[1] = 0x01;
4789         hypercall[2] = 0xc1;
4790 }
4791
4792 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4793 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4794 {
4795         if (is_guest_mode(vcpu)) {
4796                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4797                 unsigned long orig_val = val;
4798
4799                 /*
4800                  * We get here when L2 changed cr0 in a way that did not change
4801                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4802                  * but did change L0 shadowed bits. So we first calculate the
4803                  * effective cr0 value that L1 would like to write into the
4804                  * hardware. It consists of the L2-owned bits from the new
4805                  * value combined with the L1-owned bits from L1's guest_cr0.
4806                  */
4807                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4808                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4809
4810                 if (!nested_guest_cr0_valid(vcpu, val))
4811                         return 1;
4812
4813                 if (kvm_set_cr0(vcpu, val))
4814                         return 1;
4815                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4816                 return 0;
4817         } else {
4818                 if (to_vmx(vcpu)->nested.vmxon &&
4819                     !nested_host_cr0_valid(vcpu, val))
4820                         return 1;
4821
4822                 return kvm_set_cr0(vcpu, val);
4823         }
4824 }
4825
4826 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4827 {
4828         if (is_guest_mode(vcpu)) {
4829                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4830                 unsigned long orig_val = val;
4831
4832                 /* analogously to handle_set_cr0 */
4833                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4834                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4835                 if (kvm_set_cr4(vcpu, val))
4836                         return 1;
4837                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4838                 return 0;
4839         } else
4840                 return kvm_set_cr4(vcpu, val);
4841 }
4842
4843 static int handle_desc(struct kvm_vcpu *vcpu)
4844 {
4845         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4846         return kvm_emulate_instruction(vcpu, 0);
4847 }
4848
4849 static int handle_cr(struct kvm_vcpu *vcpu)
4850 {
4851         unsigned long exit_qualification, val;
4852         int cr;
4853         int reg;
4854         int err;
4855         int ret;
4856
4857         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4858         cr = exit_qualification & 15;
4859         reg = (exit_qualification >> 8) & 15;
4860         switch ((exit_qualification >> 4) & 3) {
4861         case 0: /* mov to cr */
4862                 val = kvm_register_readl(vcpu, reg);
4863                 trace_kvm_cr_write(cr, val);
4864                 switch (cr) {
4865                 case 0:
4866                         err = handle_set_cr0(vcpu, val);
4867                         return kvm_complete_insn_gp(vcpu, err);
4868                 case 3:
4869                         WARN_ON_ONCE(enable_unrestricted_guest);
4870                         err = kvm_set_cr3(vcpu, val);
4871                         return kvm_complete_insn_gp(vcpu, err);
4872                 case 4:
4873                         err = handle_set_cr4(vcpu, val);
4874                         return kvm_complete_insn_gp(vcpu, err);
4875                 case 8: {
4876                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4877                                 u8 cr8 = (u8)val;
4878                                 err = kvm_set_cr8(vcpu, cr8);
4879                                 ret = kvm_complete_insn_gp(vcpu, err);
4880                                 if (lapic_in_kernel(vcpu))
4881                                         return ret;
4882                                 if (cr8_prev <= cr8)
4883                                         return ret;
4884                                 /*
4885                                  * TODO: we might be squashing a
4886                                  * KVM_GUESTDBG_SINGLESTEP-triggered
4887                                  * KVM_EXIT_DEBUG here.
4888                                  */
4889                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4890                                 return 0;
4891                         }
4892                 }
4893                 break;
4894         case 2: /* clts */
4895                 WARN_ONCE(1, "Guest should always own CR0.TS");
4896                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4897                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4898                 return kvm_skip_emulated_instruction(vcpu);
4899         case 1: /*mov from cr*/
4900                 switch (cr) {
4901                 case 3:
4902                         WARN_ON_ONCE(enable_unrestricted_guest);
4903                         val = kvm_read_cr3(vcpu);
4904                         kvm_register_write(vcpu, reg, val);
4905                         trace_kvm_cr_read(cr, val);
4906                         return kvm_skip_emulated_instruction(vcpu);
4907                 case 8:
4908                         val = kvm_get_cr8(vcpu);
4909                         kvm_register_write(vcpu, reg, val);
4910                         trace_kvm_cr_read(cr, val);
4911                         return kvm_skip_emulated_instruction(vcpu);
4912                 }
4913                 break;
4914         case 3: /* lmsw */
4915                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4916                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4917                 kvm_lmsw(vcpu, val);
4918
4919                 return kvm_skip_emulated_instruction(vcpu);
4920         default:
4921                 break;
4922         }
4923         vcpu->run->exit_reason = 0;
4924         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4925                (int)(exit_qualification >> 4) & 3, cr);
4926         return 0;
4927 }
4928
4929 static int handle_dr(struct kvm_vcpu *vcpu)
4930 {
4931         unsigned long exit_qualification;
4932         int dr, dr7, reg;
4933
4934         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4935         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4936
4937         /* First, if DR does not exist, trigger UD */
4938         if (!kvm_require_dr(vcpu, dr))
4939                 return 1;
4940
4941         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4942         if (!kvm_require_cpl(vcpu, 0))
4943                 return 1;
4944         dr7 = vmcs_readl(GUEST_DR7);
4945         if (dr7 & DR7_GD) {
4946                 /*
4947                  * As the vm-exit takes precedence over the debug trap, we
4948                  * need to emulate the latter, either for the host or the
4949                  * guest debugging itself.
4950                  */
4951                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4952                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4953                         vcpu->run->debug.arch.dr7 = dr7;
4954                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4955                         vcpu->run->debug.arch.exception = DB_VECTOR;
4956                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4957                         return 0;
4958                 } else {
4959                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4960                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4961                         kvm_queue_exception(vcpu, DB_VECTOR);
4962                         return 1;
4963                 }
4964         }
4965
4966         if (vcpu->guest_debug == 0) {
4967                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4968
4969                 /*
4970                  * No more DR vmexits; force a reload of the debug registers
4971                  * and reenter on this instruction.  The next vmexit will
4972                  * retrieve the full state of the debug registers.
4973                  */
4974                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4975                 return 1;
4976         }
4977
4978         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4979         if (exit_qualification & TYPE_MOV_FROM_DR) {
4980                 unsigned long val;
4981
4982                 if (kvm_get_dr(vcpu, dr, &val))
4983                         return 1;
4984                 kvm_register_write(vcpu, reg, val);
4985         } else
4986                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4987                         return 1;
4988
4989         return kvm_skip_emulated_instruction(vcpu);
4990 }
4991
4992 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4993 {
4994         return vcpu->arch.dr6;
4995 }
4996
4997 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4998 {
4999 }
5000
5001 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5002 {
5003         get_debugreg(vcpu->arch.db[0], 0);
5004         get_debugreg(vcpu->arch.db[1], 1);
5005         get_debugreg(vcpu->arch.db[2], 2);
5006         get_debugreg(vcpu->arch.db[3], 3);
5007         get_debugreg(vcpu->arch.dr6, 6);
5008         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5009
5010         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5011         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5012 }
5013
5014 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5015 {
5016         vmcs_writel(GUEST_DR7, val);
5017 }
5018
5019 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5020 {
5021         kvm_apic_update_ppr(vcpu);
5022         return 1;
5023 }
5024
5025 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5026 {
5027         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5028
5029         kvm_make_request(KVM_REQ_EVENT, vcpu);
5030
5031         ++vcpu->stat.irq_window_exits;
5032         return 1;
5033 }
5034
5035 static int handle_vmcall(struct kvm_vcpu *vcpu)
5036 {
5037         return kvm_emulate_hypercall(vcpu);
5038 }
5039
5040 static int handle_invd(struct kvm_vcpu *vcpu)
5041 {
5042         return kvm_emulate_instruction(vcpu, 0);
5043 }
5044
5045 static int handle_invlpg(struct kvm_vcpu *vcpu)
5046 {
5047         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5048
5049         kvm_mmu_invlpg(vcpu, exit_qualification);
5050         return kvm_skip_emulated_instruction(vcpu);
5051 }
5052
5053 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5054 {
5055         int err;
5056
5057         err = kvm_rdpmc(vcpu);
5058         return kvm_complete_insn_gp(vcpu, err);
5059 }
5060
5061 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5062 {
5063         return kvm_emulate_wbinvd(vcpu);
5064 }
5065
5066 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5067 {
5068         u64 new_bv = kvm_read_edx_eax(vcpu);
5069         u32 index = kvm_rcx_read(vcpu);
5070
5071         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5072                 return kvm_skip_emulated_instruction(vcpu);
5073         return 1;
5074 }
5075
5076 static int handle_apic_access(struct kvm_vcpu *vcpu)
5077 {
5078         if (likely(fasteoi)) {
5079                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5080                 int access_type, offset;
5081
5082                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5083                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5084                 /*
5085                  * Sane guest uses MOV to write EOI, with written value
5086                  * not cared. So make a short-circuit here by avoiding
5087                  * heavy instruction emulation.
5088                  */
5089                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5090                     (offset == APIC_EOI)) {
5091                         kvm_lapic_set_eoi(vcpu);
5092                         return kvm_skip_emulated_instruction(vcpu);
5093                 }
5094         }
5095         return kvm_emulate_instruction(vcpu, 0);
5096 }
5097
5098 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5099 {
5100         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5101         int vector = exit_qualification & 0xff;
5102
5103         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5104         kvm_apic_set_eoi_accelerated(vcpu, vector);
5105         return 1;
5106 }
5107
5108 static int handle_apic_write(struct kvm_vcpu *vcpu)
5109 {
5110         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5111         u32 offset = exit_qualification & 0xfff;
5112
5113         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5114         kvm_apic_write_nodecode(vcpu, offset);
5115         return 1;
5116 }
5117
5118 static int handle_task_switch(struct kvm_vcpu *vcpu)
5119 {
5120         struct vcpu_vmx *vmx = to_vmx(vcpu);
5121         unsigned long exit_qualification;
5122         bool has_error_code = false;
5123         u32 error_code = 0;
5124         u16 tss_selector;
5125         int reason, type, idt_v, idt_index;
5126
5127         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5128         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5129         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5130
5131         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5132
5133         reason = (u32)exit_qualification >> 30;
5134         if (reason == TASK_SWITCH_GATE && idt_v) {
5135                 switch (type) {
5136                 case INTR_TYPE_NMI_INTR:
5137                         vcpu->arch.nmi_injected = false;
5138                         vmx_set_nmi_mask(vcpu, true);
5139                         break;
5140                 case INTR_TYPE_EXT_INTR:
5141                 case INTR_TYPE_SOFT_INTR:
5142                         kvm_clear_interrupt_queue(vcpu);
5143                         break;
5144                 case INTR_TYPE_HARD_EXCEPTION:
5145                         if (vmx->idt_vectoring_info &
5146                             VECTORING_INFO_DELIVER_CODE_MASK) {
5147                                 has_error_code = true;
5148                                 error_code =
5149                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5150                         }
5151                         /* fall through */
5152                 case INTR_TYPE_SOFT_EXCEPTION:
5153                         kvm_clear_exception_queue(vcpu);
5154                         break;
5155                 default:
5156                         break;
5157                 }
5158         }
5159         tss_selector = exit_qualification;
5160
5161         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5162                        type != INTR_TYPE_EXT_INTR &&
5163                        type != INTR_TYPE_NMI_INTR))
5164                 WARN_ON(!skip_emulated_instruction(vcpu));
5165
5166         /*
5167          * TODO: What about debug traps on tss switch?
5168          *       Are we supposed to inject them and update dr6?
5169          */
5170         return kvm_task_switch(vcpu, tss_selector,
5171                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5172                                reason, has_error_code, error_code);
5173 }
5174
5175 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5176 {
5177         unsigned long exit_qualification;
5178         gpa_t gpa;
5179         u64 error_code;
5180
5181         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5182
5183         /*
5184          * EPT violation happened while executing iret from NMI,
5185          * "blocked by NMI" bit has to be set before next VM entry.
5186          * There are errata that may cause this bit to not be set:
5187          * AAK134, BY25.
5188          */
5189         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5190                         enable_vnmi &&
5191                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5192                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5193
5194         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5195         trace_kvm_page_fault(gpa, exit_qualification);
5196
5197         /* Is it a read fault? */
5198         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5199                      ? PFERR_USER_MASK : 0;
5200         /* Is it a write fault? */
5201         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5202                       ? PFERR_WRITE_MASK : 0;
5203         /* Is it a fetch fault? */
5204         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5205                       ? PFERR_FETCH_MASK : 0;
5206         /* ept page table entry is present? */
5207         error_code |= (exit_qualification &
5208                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5209                         EPT_VIOLATION_EXECUTABLE))
5210                       ? PFERR_PRESENT_MASK : 0;
5211
5212         error_code |= (exit_qualification & 0x100) != 0 ?
5213                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5214
5215         vcpu->arch.exit_qualification = exit_qualification;
5216         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5217 }
5218
5219 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5220 {
5221         gpa_t gpa;
5222
5223         /*
5224          * A nested guest cannot optimize MMIO vmexits, because we have an
5225          * nGPA here instead of the required GPA.
5226          */
5227         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5228         if (!is_guest_mode(vcpu) &&
5229             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5230                 trace_kvm_fast_mmio(gpa);
5231                 return kvm_skip_emulated_instruction(vcpu);
5232         }
5233
5234         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5235 }
5236
5237 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5238 {
5239         WARN_ON_ONCE(!enable_vnmi);
5240         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5241         ++vcpu->stat.nmi_window_exits;
5242         kvm_make_request(KVM_REQ_EVENT, vcpu);
5243
5244         return 1;
5245 }
5246
5247 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5248 {
5249         struct vcpu_vmx *vmx = to_vmx(vcpu);
5250         bool intr_window_requested;
5251         unsigned count = 130;
5252
5253         /*
5254          * We should never reach the point where we are emulating L2
5255          * due to invalid guest state as that means we incorrectly
5256          * allowed a nested VMEntry with an invalid vmcs12.
5257          */
5258         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5259
5260         intr_window_requested = exec_controls_get(vmx) &
5261                                 CPU_BASED_INTR_WINDOW_EXITING;
5262
5263         while (vmx->emulation_required && count-- != 0) {
5264                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5265                         return handle_interrupt_window(&vmx->vcpu);
5266
5267                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5268                         return 1;
5269
5270                 if (!kvm_emulate_instruction(vcpu, 0))
5271                         return 0;
5272
5273                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5274                     vcpu->arch.exception.pending) {
5275                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5276                         vcpu->run->internal.suberror =
5277                                                 KVM_INTERNAL_ERROR_EMULATION;
5278                         vcpu->run->internal.ndata = 0;
5279                         return 0;
5280                 }
5281
5282                 if (vcpu->arch.halt_request) {
5283                         vcpu->arch.halt_request = 0;
5284                         return kvm_vcpu_halt(vcpu);
5285                 }
5286
5287                 /*
5288                  * Note, return 1 and not 0, vcpu_run() is responsible for
5289                  * morphing the pending signal into the proper return code.
5290                  */
5291                 if (signal_pending(current))
5292                         return 1;
5293
5294                 if (need_resched())
5295                         schedule();
5296         }
5297
5298         return 1;
5299 }
5300
5301 static void grow_ple_window(struct kvm_vcpu *vcpu)
5302 {
5303         struct vcpu_vmx *vmx = to_vmx(vcpu);
5304         unsigned int old = vmx->ple_window;
5305
5306         vmx->ple_window = __grow_ple_window(old, ple_window,
5307                                             ple_window_grow,
5308                                             ple_window_max);
5309
5310         if (vmx->ple_window != old) {
5311                 vmx->ple_window_dirty = true;
5312                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5313                                             vmx->ple_window, old);
5314         }
5315 }
5316
5317 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5318 {
5319         struct vcpu_vmx *vmx = to_vmx(vcpu);
5320         unsigned int old = vmx->ple_window;
5321
5322         vmx->ple_window = __shrink_ple_window(old, ple_window,
5323                                               ple_window_shrink,
5324                                               ple_window);
5325
5326         if (vmx->ple_window != old) {
5327                 vmx->ple_window_dirty = true;
5328                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5329                                             vmx->ple_window, old);
5330         }
5331 }
5332
5333 /*
5334  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5335  */
5336 static void wakeup_handler(void)
5337 {
5338         struct kvm_vcpu *vcpu;
5339         int cpu = smp_processor_id();
5340
5341         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5342         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5343                         blocked_vcpu_list) {
5344                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5345
5346                 if (pi_test_on(pi_desc) == 1)
5347                         kvm_vcpu_kick(vcpu);
5348         }
5349         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5350 }
5351
5352 static void vmx_enable_tdp(void)
5353 {
5354         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5355                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5356                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5357                 0ull, VMX_EPT_EXECUTABLE_MASK,
5358                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5359                 VMX_EPT_RWX_MASK, 0ull);
5360
5361         ept_set_mmio_spte_mask();
5362 }
5363
5364 /*
5365  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5366  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5367  */
5368 static int handle_pause(struct kvm_vcpu *vcpu)
5369 {
5370         if (!kvm_pause_in_guest(vcpu->kvm))
5371                 grow_ple_window(vcpu);
5372
5373         /*
5374          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5375          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5376          * never set PAUSE_EXITING and just set PLE if supported,
5377          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5378          */
5379         kvm_vcpu_on_spin(vcpu, true);
5380         return kvm_skip_emulated_instruction(vcpu);
5381 }
5382
5383 static int handle_nop(struct kvm_vcpu *vcpu)
5384 {
5385         return kvm_skip_emulated_instruction(vcpu);
5386 }
5387
5388 static int handle_mwait(struct kvm_vcpu *vcpu)
5389 {
5390         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5391         return handle_nop(vcpu);
5392 }
5393
5394 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5395 {
5396         kvm_queue_exception(vcpu, UD_VECTOR);
5397         return 1;
5398 }
5399
5400 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5401 {
5402         return 1;
5403 }
5404
5405 static int handle_monitor(struct kvm_vcpu *vcpu)
5406 {
5407         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5408         return handle_nop(vcpu);
5409 }
5410
5411 static int handle_invpcid(struct kvm_vcpu *vcpu)
5412 {
5413         u32 vmx_instruction_info;
5414         unsigned long type;
5415         bool pcid_enabled;
5416         gva_t gva;
5417         struct x86_exception e;
5418         unsigned i;
5419         unsigned long roots_to_free = 0;
5420         struct {
5421                 u64 pcid;
5422                 u64 gla;
5423         } operand;
5424
5425         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5426                 kvm_queue_exception(vcpu, UD_VECTOR);
5427                 return 1;
5428         }
5429
5430         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5431         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5432
5433         if (type > 3) {
5434                 kvm_inject_gp(vcpu, 0);
5435                 return 1;
5436         }
5437
5438         /* According to the Intel instruction reference, the memory operand
5439          * is read even if it isn't needed (e.g., for type==all)
5440          */
5441         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5442                                 vmx_instruction_info, false,
5443                                 sizeof(operand), &gva))
5444                 return 1;
5445
5446         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5447                 kvm_inject_emulated_page_fault(vcpu, &e);
5448                 return 1;
5449         }
5450
5451         if (operand.pcid >> 12 != 0) {
5452                 kvm_inject_gp(vcpu, 0);
5453                 return 1;
5454         }
5455
5456         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5457
5458         switch (type) {
5459         case INVPCID_TYPE_INDIV_ADDR:
5460                 if ((!pcid_enabled && (operand.pcid != 0)) ||
5461                     is_noncanonical_address(operand.gla, vcpu)) {
5462                         kvm_inject_gp(vcpu, 0);
5463                         return 1;
5464                 }
5465                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5466                 return kvm_skip_emulated_instruction(vcpu);
5467
5468         case INVPCID_TYPE_SINGLE_CTXT:
5469                 if (!pcid_enabled && (operand.pcid != 0)) {
5470                         kvm_inject_gp(vcpu, 0);
5471                         return 1;
5472                 }
5473
5474                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5475                         kvm_mmu_sync_roots(vcpu);
5476                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
5477                 }
5478
5479                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5480                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
5481                             == operand.pcid)
5482                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5483
5484                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5485                 /*
5486                  * If neither the current cr3 nor any of the prev_roots use the
5487                  * given PCID, then nothing needs to be done here because a
5488                  * resync will happen anyway before switching to any other CR3.
5489                  */
5490
5491                 return kvm_skip_emulated_instruction(vcpu);
5492
5493         case INVPCID_TYPE_ALL_NON_GLOBAL:
5494                 /*
5495                  * Currently, KVM doesn't mark global entries in the shadow
5496                  * page tables, so a non-global flush just degenerates to a
5497                  * global flush. If needed, we could optimize this later by
5498                  * keeping track of global entries in shadow page tables.
5499                  */
5500
5501                 /* fall-through */
5502         case INVPCID_TYPE_ALL_INCL_GLOBAL:
5503                 kvm_mmu_unload(vcpu);
5504                 return kvm_skip_emulated_instruction(vcpu);
5505
5506         default:
5507                 BUG(); /* We have already checked above that type <= 3 */
5508         }
5509 }
5510
5511 static int handle_pml_full(struct kvm_vcpu *vcpu)
5512 {
5513         unsigned long exit_qualification;
5514
5515         trace_kvm_pml_full(vcpu->vcpu_id);
5516
5517         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5518
5519         /*
5520          * PML buffer FULL happened while executing iret from NMI,
5521          * "blocked by NMI" bit has to be set before next VM entry.
5522          */
5523         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5524                         enable_vnmi &&
5525                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5526                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5527                                 GUEST_INTR_STATE_NMI);
5528
5529         /*
5530          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5531          * here.., and there's no userspace involvement needed for PML.
5532          */
5533         return 1;
5534 }
5535
5536 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5537 {
5538         struct vcpu_vmx *vmx = to_vmx(vcpu);
5539
5540         if (!vmx->req_immediate_exit &&
5541             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5542                 kvm_lapic_expired_hv_timer(vcpu);
5543
5544         return 1;
5545 }
5546
5547 /*
5548  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5549  * are overwritten by nested_vmx_setup() when nested=1.
5550  */
5551 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5552 {
5553         kvm_queue_exception(vcpu, UD_VECTOR);
5554         return 1;
5555 }
5556
5557 static int handle_encls(struct kvm_vcpu *vcpu)
5558 {
5559         /*
5560          * SGX virtualization is not yet supported.  There is no software
5561          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5562          * to prevent the guest from executing ENCLS.
5563          */
5564         kvm_queue_exception(vcpu, UD_VECTOR);
5565         return 1;
5566 }
5567
5568 /*
5569  * The exit handlers return 1 if the exit was handled fully and guest execution
5570  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5571  * to be done to userspace and return 0.
5572  */
5573 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5574         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5575         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5576         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5577         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5578         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5579         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5580         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5581         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5582         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5583         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5584         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5585         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5586         [EXIT_REASON_INVD]                    = handle_invd,
5587         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5588         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5589         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5590         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5591         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5592         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5593         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5594         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5595         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5596         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5597         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5598         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5599         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5600         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5601         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5602         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5603         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5604         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5605         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5606         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5607         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5608         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5609         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5610         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5611         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5612         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
5613         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5614         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
5615         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5616         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5617         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
5618         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
5619         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5620         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5621         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5622         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5623         [EXIT_REASON_ENCLS]                   = handle_encls,
5624 };
5625
5626 static const int kvm_vmx_max_exit_handlers =
5627         ARRAY_SIZE(kvm_vmx_exit_handlers);
5628
5629 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5630 {
5631         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5632         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5633 }
5634
5635 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5636 {
5637         if (vmx->pml_pg) {
5638                 __free_page(vmx->pml_pg);
5639                 vmx->pml_pg = NULL;
5640         }
5641 }
5642
5643 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5644 {
5645         struct vcpu_vmx *vmx = to_vmx(vcpu);
5646         u64 *pml_buf;
5647         u16 pml_idx;
5648
5649         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5650
5651         /* Do nothing if PML buffer is empty */
5652         if (pml_idx == (PML_ENTITY_NUM - 1))
5653                 return;
5654
5655         /* PML index always points to next available PML buffer entity */
5656         if (pml_idx >= PML_ENTITY_NUM)
5657                 pml_idx = 0;
5658         else
5659                 pml_idx++;
5660
5661         pml_buf = page_address(vmx->pml_pg);
5662         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5663                 u64 gpa;
5664
5665                 gpa = pml_buf[pml_idx];
5666                 WARN_ON(gpa & (PAGE_SIZE - 1));
5667                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5668         }
5669
5670         /* reset PML index */
5671         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5672 }
5673
5674 /*
5675  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5676  * Called before reporting dirty_bitmap to userspace.
5677  */
5678 static void kvm_flush_pml_buffers(struct kvm *kvm)
5679 {
5680         int i;
5681         struct kvm_vcpu *vcpu;
5682         /*
5683          * We only need to kick vcpu out of guest mode here, as PML buffer
5684          * is flushed at beginning of all VMEXITs, and it's obvious that only
5685          * vcpus running in guest are possible to have unflushed GPAs in PML
5686          * buffer.
5687          */
5688         kvm_for_each_vcpu(i, vcpu, kvm)
5689                 kvm_vcpu_kick(vcpu);
5690 }
5691
5692 static void vmx_dump_sel(char *name, uint32_t sel)
5693 {
5694         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5695                name, vmcs_read16(sel),
5696                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5697                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5698                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5699 }
5700
5701 static void vmx_dump_dtsel(char *name, uint32_t limit)
5702 {
5703         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5704                name, vmcs_read32(limit),
5705                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5706 }
5707
5708 void dump_vmcs(void)
5709 {
5710         u32 vmentry_ctl, vmexit_ctl;
5711         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5712         unsigned long cr4;
5713         u64 efer;
5714         int i, n;
5715
5716         if (!dump_invalid_vmcs) {
5717                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5718                 return;
5719         }
5720
5721         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5722         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5723         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5724         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5725         cr4 = vmcs_readl(GUEST_CR4);
5726         efer = vmcs_read64(GUEST_IA32_EFER);
5727         secondary_exec_control = 0;
5728         if (cpu_has_secondary_exec_ctrls())
5729                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5730
5731         pr_err("*** Guest State ***\n");
5732         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5733                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5734                vmcs_readl(CR0_GUEST_HOST_MASK));
5735         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5736                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5737         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5738         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5739             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5740         {
5741                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5742                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5743                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5744                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5745         }
5746         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5747                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5748         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5749                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5750         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5751                vmcs_readl(GUEST_SYSENTER_ESP),
5752                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5753         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5754         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5755         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5756         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5757         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5758         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5759         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5760         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5761         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5762         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5763         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5764             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5765                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
5766                        efer, vmcs_read64(GUEST_IA32_PAT));
5767         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5768                vmcs_read64(GUEST_IA32_DEBUGCTL),
5769                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5770         if (cpu_has_load_perf_global_ctrl() &&
5771             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5772                 pr_err("PerfGlobCtl = 0x%016llx\n",
5773                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5774         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5775                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5776         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5777                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5778                vmcs_read32(GUEST_ACTIVITY_STATE));
5779         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5780                 pr_err("InterruptStatus = %04x\n",
5781                        vmcs_read16(GUEST_INTR_STATUS));
5782
5783         pr_err("*** Host State ***\n");
5784         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5785                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5786         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5787                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5788                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5789                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5790                vmcs_read16(HOST_TR_SELECTOR));
5791         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5792                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5793                vmcs_readl(HOST_TR_BASE));
5794         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5795                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5796         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5797                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5798                vmcs_readl(HOST_CR4));
5799         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5800                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5801                vmcs_read32(HOST_IA32_SYSENTER_CS),
5802                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5803         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5804                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
5805                        vmcs_read64(HOST_IA32_EFER),
5806                        vmcs_read64(HOST_IA32_PAT));
5807         if (cpu_has_load_perf_global_ctrl() &&
5808             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5809                 pr_err("PerfGlobCtl = 0x%016llx\n",
5810                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5811
5812         pr_err("*** Control State ***\n");
5813         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5814                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5815         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5816         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5817                vmcs_read32(EXCEPTION_BITMAP),
5818                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5819                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5820         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5821                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5822                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5823                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5824         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5825                vmcs_read32(VM_EXIT_INTR_INFO),
5826                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5827                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5828         pr_err("        reason=%08x qualification=%016lx\n",
5829                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5830         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5831                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5832                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5833         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5834         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5835                 pr_err("TSC Multiplier = 0x%016llx\n",
5836                        vmcs_read64(TSC_MULTIPLIER));
5837         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5838                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5839                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5840                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5841                 }
5842                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5843                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5844                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5845                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5846         }
5847         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5848                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5849         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5850                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5851         n = vmcs_read32(CR3_TARGET_COUNT);
5852         for (i = 0; i + 1 < n; i += 4)
5853                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5854                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5855                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5856         if (i < n)
5857                 pr_err("CR3 target%u=%016lx\n",
5858                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5859         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5860                 pr_err("PLE Gap=%08x Window=%08x\n",
5861                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5862         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5863                 pr_err("Virtual processor ID = 0x%04x\n",
5864                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5865 }
5866
5867 /*
5868  * The guest has exited.  See if we can fix it or if we need userspace
5869  * assistance.
5870  */
5871 static int vmx_handle_exit(struct kvm_vcpu *vcpu,
5872         enum exit_fastpath_completion exit_fastpath)
5873 {
5874         struct vcpu_vmx *vmx = to_vmx(vcpu);
5875         u32 exit_reason = vmx->exit_reason;
5876         u32 vectoring_info = vmx->idt_vectoring_info;
5877
5878         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5879
5880         /*
5881          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5882          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5883          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5884          * mode as if vcpus is in root mode, the PML buffer must has been
5885          * flushed already.
5886          */
5887         if (enable_pml)
5888                 vmx_flush_pml_buffer(vcpu);
5889
5890         /* If guest state is invalid, start emulating */
5891         if (vmx->emulation_required)
5892                 return handle_invalid_guest_state(vcpu);
5893
5894         if (is_guest_mode(vcpu)) {
5895                 /*
5896                  * The host physical addresses of some pages of guest memory
5897                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5898                  * Page). The CPU may write to these pages via their host
5899                  * physical address while L2 is running, bypassing any
5900                  * address-translation-based dirty tracking (e.g. EPT write
5901                  * protection).
5902                  *
5903                  * Mark them dirty on every exit from L2 to prevent them from
5904                  * getting out of sync with dirty tracking.
5905                  */
5906                 nested_mark_vmcs12_pages_dirty(vcpu);
5907
5908                 if (nested_vmx_reflect_vmexit(vcpu))
5909                         return 1;
5910         }
5911
5912         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5913                 dump_vmcs();
5914                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5915                 vcpu->run->fail_entry.hardware_entry_failure_reason
5916                         = exit_reason;
5917                 return 0;
5918         }
5919
5920         if (unlikely(vmx->fail)) {
5921                 dump_vmcs();
5922                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5923                 vcpu->run->fail_entry.hardware_entry_failure_reason
5924                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5925                 return 0;
5926         }
5927
5928         /*
5929          * Note:
5930          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5931          * delivery event since it indicates guest is accessing MMIO.
5932          * The vm-exit can be triggered again after return to guest that
5933          * will cause infinite loop.
5934          */
5935         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5936                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5937                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5938                         exit_reason != EXIT_REASON_PML_FULL &&
5939                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
5940                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5941                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5942                 vcpu->run->internal.ndata = 3;
5943                 vcpu->run->internal.data[0] = vectoring_info;
5944                 vcpu->run->internal.data[1] = exit_reason;
5945                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5946                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5947                         vcpu->run->internal.ndata++;
5948                         vcpu->run->internal.data[3] =
5949                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5950                 }
5951                 return 0;
5952         }
5953
5954         if (unlikely(!enable_vnmi &&
5955                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5956                 if (vmx_interrupt_allowed(vcpu)) {
5957                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5958                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5959                            vcpu->arch.nmi_pending) {
5960                         /*
5961                          * This CPU don't support us in finding the end of an
5962                          * NMI-blocked window if the guest runs with IRQs
5963                          * disabled. So we pull the trigger after 1 s of
5964                          * futile waiting, but inform the user about this.
5965                          */
5966                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5967                                "state on VCPU %d after 1 s timeout\n",
5968                                __func__, vcpu->vcpu_id);
5969                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5970                 }
5971         }
5972
5973         if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5974                 kvm_skip_emulated_instruction(vcpu);
5975                 return 1;
5976         }
5977
5978         if (exit_reason >= kvm_vmx_max_exit_handlers)
5979                 goto unexpected_vmexit;
5980 #ifdef CONFIG_RETPOLINE
5981         if (exit_reason == EXIT_REASON_MSR_WRITE)
5982                 return kvm_emulate_wrmsr(vcpu);
5983         else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5984                 return handle_preemption_timer(vcpu);
5985         else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
5986                 return handle_interrupt_window(vcpu);
5987         else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5988                 return handle_external_interrupt(vcpu);
5989         else if (exit_reason == EXIT_REASON_HLT)
5990                 return kvm_emulate_halt(vcpu);
5991         else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5992                 return handle_ept_misconfig(vcpu);
5993 #endif
5994
5995         exit_reason = array_index_nospec(exit_reason,
5996                                          kvm_vmx_max_exit_handlers);
5997         if (!kvm_vmx_exit_handlers[exit_reason])
5998                 goto unexpected_vmexit;
5999
6000         return kvm_vmx_exit_handlers[exit_reason](vcpu);
6001
6002 unexpected_vmexit:
6003         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
6004         dump_vmcs();
6005         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6006         vcpu->run->internal.suberror =
6007                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6008         vcpu->run->internal.ndata = 1;
6009         vcpu->run->internal.data[0] = exit_reason;
6010         return 0;
6011 }
6012
6013 /*
6014  * Software based L1D cache flush which is used when microcode providing
6015  * the cache control MSR is not loaded.
6016  *
6017  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6018  * flush it is required to read in 64 KiB because the replacement algorithm
6019  * is not exactly LRU. This could be sized at runtime via topology
6020  * information but as all relevant affected CPUs have 32KiB L1D cache size
6021  * there is no point in doing so.
6022  */
6023 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6024 {
6025         int size = PAGE_SIZE << L1D_CACHE_ORDER;
6026
6027         /*
6028          * This code is only executed when the the flush mode is 'cond' or
6029          * 'always'
6030          */
6031         if (static_branch_likely(&vmx_l1d_flush_cond)) {
6032                 bool flush_l1d;
6033
6034                 /*
6035                  * Clear the per-vcpu flush bit, it gets set again
6036                  * either from vcpu_run() or from one of the unsafe
6037                  * VMEXIT handlers.
6038                  */
6039                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6040                 vcpu->arch.l1tf_flush_l1d = false;
6041
6042                 /*
6043                  * Clear the per-cpu flush bit, it gets set again from
6044                  * the interrupt handlers.
6045                  */
6046                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6047                 kvm_clear_cpu_l1tf_flush_l1d();
6048
6049                 if (!flush_l1d)
6050                         return;
6051         }
6052
6053         vcpu->stat.l1d_flush++;
6054
6055         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6056                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6057                 return;
6058         }
6059
6060         asm volatile(
6061                 /* First ensure the pages are in the TLB */
6062                 "xorl   %%eax, %%eax\n"
6063                 ".Lpopulate_tlb:\n\t"
6064                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6065                 "addl   $4096, %%eax\n\t"
6066                 "cmpl   %%eax, %[size]\n\t"
6067                 "jne    .Lpopulate_tlb\n\t"
6068                 "xorl   %%eax, %%eax\n\t"
6069                 "cpuid\n\t"
6070                 /* Now fill the cache */
6071                 "xorl   %%eax, %%eax\n"
6072                 ".Lfill_cache:\n"
6073                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6074                 "addl   $64, %%eax\n\t"
6075                 "cmpl   %%eax, %[size]\n\t"
6076                 "jne    .Lfill_cache\n\t"
6077                 "lfence\n"
6078                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6079                     [size] "r" (size)
6080                 : "eax", "ebx", "ecx", "edx");
6081 }
6082
6083 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6084 {
6085         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6086         int tpr_threshold;
6087
6088         if (is_guest_mode(vcpu) &&
6089                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6090                 return;
6091
6092         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6093         if (is_guest_mode(vcpu))
6094                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6095         else
6096                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6097 }
6098
6099 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6100 {
6101         struct vcpu_vmx *vmx = to_vmx(vcpu);
6102         u32 sec_exec_control;
6103
6104         if (!lapic_in_kernel(vcpu))
6105                 return;
6106
6107         if (!flexpriority_enabled &&
6108             !cpu_has_vmx_virtualize_x2apic_mode())
6109                 return;
6110
6111         /* Postpone execution until vmcs01 is the current VMCS. */
6112         if (is_guest_mode(vcpu)) {
6113                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6114                 return;
6115         }
6116
6117         sec_exec_control = secondary_exec_controls_get(vmx);
6118         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6119                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6120
6121         switch (kvm_get_apic_mode(vcpu)) {
6122         case LAPIC_MODE_INVALID:
6123                 WARN_ONCE(true, "Invalid local APIC state");
6124         case LAPIC_MODE_DISABLED:
6125                 break;
6126         case LAPIC_MODE_XAPIC:
6127                 if (flexpriority_enabled) {
6128                         sec_exec_control |=
6129                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6130                         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6131
6132                         /*
6133                          * Flush the TLB, reloading the APIC access page will
6134                          * only do so if its physical address has changed, but
6135                          * the guest may have inserted a non-APIC mapping into
6136                          * the TLB while the APIC access page was disabled.
6137                          */
6138                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6139                 }
6140                 break;
6141         case LAPIC_MODE_X2APIC:
6142                 if (cpu_has_vmx_virtualize_x2apic_mode())
6143                         sec_exec_control |=
6144                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6145                 break;
6146         }
6147         secondary_exec_controls_set(vmx, sec_exec_control);
6148
6149         vmx_update_msr_bitmap(vcpu);
6150 }
6151
6152 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6153 {
6154         struct page *page;
6155
6156         /* Defer reload until vmcs01 is the current VMCS. */
6157         if (is_guest_mode(vcpu)) {
6158                 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6159                 return;
6160         }
6161
6162         if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6163             SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6164                 return;
6165
6166         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6167         if (is_error_page(page))
6168                 return;
6169
6170         vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6171         vmx_flush_tlb_current(vcpu);
6172
6173         /*
6174          * Do not pin apic access page in memory, the MMU notifier
6175          * will call us again if it is migrated or swapped out.
6176          */
6177         put_page(page);
6178 }
6179
6180 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6181 {
6182         u16 status;
6183         u8 old;
6184
6185         if (max_isr == -1)
6186                 max_isr = 0;
6187
6188         status = vmcs_read16(GUEST_INTR_STATUS);
6189         old = status >> 8;
6190         if (max_isr != old) {
6191                 status &= 0xff;
6192                 status |= max_isr << 8;
6193                 vmcs_write16(GUEST_INTR_STATUS, status);
6194         }
6195 }
6196
6197 static void vmx_set_rvi(int vector)
6198 {
6199         u16 status;
6200         u8 old;
6201
6202         if (vector == -1)
6203                 vector = 0;
6204
6205         status = vmcs_read16(GUEST_INTR_STATUS);
6206         old = (u8)status & 0xff;
6207         if ((u8)vector != old) {
6208                 status &= ~0xff;
6209                 status |= (u8)vector;
6210                 vmcs_write16(GUEST_INTR_STATUS, status);
6211         }
6212 }
6213
6214 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6215 {
6216         /*
6217          * When running L2, updating RVI is only relevant when
6218          * vmcs12 virtual-interrupt-delivery enabled.
6219          * However, it can be enabled only when L1 also
6220          * intercepts external-interrupts and in that case
6221          * we should not update vmcs02 RVI but instead intercept
6222          * interrupt. Therefore, do nothing when running L2.
6223          */
6224         if (!is_guest_mode(vcpu))
6225                 vmx_set_rvi(max_irr);
6226 }
6227
6228 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6229 {
6230         struct vcpu_vmx *vmx = to_vmx(vcpu);
6231         int max_irr;
6232         bool max_irr_updated;
6233
6234         WARN_ON(!vcpu->arch.apicv_active);
6235         if (pi_test_on(&vmx->pi_desc)) {
6236                 pi_clear_on(&vmx->pi_desc);
6237                 /*
6238                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6239                  * But on x86 this is just a compiler barrier anyway.
6240                  */
6241                 smp_mb__after_atomic();
6242                 max_irr_updated =
6243                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6244
6245                 /*
6246                  * If we are running L2 and L1 has a new pending interrupt
6247                  * which can be injected, we should re-evaluate
6248                  * what should be done with this new L1 interrupt.
6249                  * If L1 intercepts external-interrupts, we should
6250                  * exit from L2 to L1. Otherwise, interrupt should be
6251                  * delivered directly to L2.
6252                  */
6253                 if (is_guest_mode(vcpu) && max_irr_updated) {
6254                         if (nested_exit_on_intr(vcpu))
6255                                 kvm_vcpu_exiting_guest_mode(vcpu);
6256                         else
6257                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6258                 }
6259         } else {
6260                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6261         }
6262         vmx_hwapic_irr_update(vcpu, max_irr);
6263         return max_irr;
6264 }
6265
6266 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6267 {
6268         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6269
6270         return pi_test_on(pi_desc) ||
6271                 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6272 }
6273
6274 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6275 {
6276         if (!kvm_vcpu_apicv_active(vcpu))
6277                 return;
6278
6279         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6280         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6281         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6282         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6283 }
6284
6285 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6286 {
6287         struct vcpu_vmx *vmx = to_vmx(vcpu);
6288
6289         pi_clear_on(&vmx->pi_desc);
6290         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6291 }
6292
6293 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6294 {
6295         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6296
6297         /* if exit due to PF check for async PF */
6298         if (is_page_fault(vmx->exit_intr_info)) {
6299                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6300         /* Handle machine checks before interrupts are enabled */
6301         } else if (is_machine_check(vmx->exit_intr_info)) {
6302                 kvm_machine_check();
6303         /* We need to handle NMIs before interrupts are enabled */
6304         } else if (is_nmi(vmx->exit_intr_info)) {
6305                 kvm_before_interrupt(&vmx->vcpu);
6306                 asm("int $2");
6307                 kvm_after_interrupt(&vmx->vcpu);
6308         }
6309 }
6310
6311 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6312 {
6313         unsigned int vector;
6314         unsigned long entry;
6315 #ifdef CONFIG_X86_64
6316         unsigned long tmp;
6317 #endif
6318         gate_desc *desc;
6319         u32 intr_info;
6320
6321         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6322         if (WARN_ONCE(!is_external_intr(intr_info),
6323             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6324                 return;
6325
6326         vector = intr_info & INTR_INFO_VECTOR_MASK;
6327         desc = (gate_desc *)host_idt_base + vector;
6328         entry = gate_offset(desc);
6329
6330         kvm_before_interrupt(vcpu);
6331
6332         asm volatile(
6333 #ifdef CONFIG_X86_64
6334                 "mov %%" _ASM_SP ", %[sp]\n\t"
6335                 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6336                 "push $%c[ss]\n\t"
6337                 "push %[sp]\n\t"
6338 #endif
6339                 "pushf\n\t"
6340                 __ASM_SIZE(push) " $%c[cs]\n\t"
6341                 CALL_NOSPEC
6342                 :
6343 #ifdef CONFIG_X86_64
6344                 [sp]"=&r"(tmp),
6345 #endif
6346                 ASM_CALL_CONSTRAINT
6347                 :
6348                 [thunk_target]"r"(entry),
6349                 [ss]"i"(__KERNEL_DS),
6350                 [cs]"i"(__KERNEL_CS)
6351         );
6352
6353         kvm_after_interrupt(vcpu);
6354 }
6355 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6356
6357 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6358         enum exit_fastpath_completion *exit_fastpath)
6359 {
6360         struct vcpu_vmx *vmx = to_vmx(vcpu);
6361
6362         if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6363                 handle_external_interrupt_irqoff(vcpu);
6364         else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6365                 handle_exception_nmi_irqoff(vmx);
6366         else if (!is_guest_mode(vcpu) &&
6367                 vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6368                 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
6369 }
6370
6371 static bool vmx_has_emulated_msr(int index)
6372 {
6373         switch (index) {
6374         case MSR_IA32_SMBASE:
6375                 /*
6376                  * We cannot do SMM unless we can run the guest in big
6377                  * real mode.
6378                  */
6379                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6380         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6381                 return nested;
6382         case MSR_AMD64_VIRT_SPEC_CTRL:
6383                 /* This is AMD only.  */
6384                 return false;
6385         default:
6386                 return true;
6387         }
6388 }
6389
6390 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6391 {
6392         u32 exit_intr_info;
6393         bool unblock_nmi;
6394         u8 vector;
6395         bool idtv_info_valid;
6396
6397         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6398
6399         if (enable_vnmi) {
6400                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6401                         return;
6402                 /*
6403                  * Can't use vmx->exit_intr_info since we're not sure what
6404                  * the exit reason is.
6405                  */
6406                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6407                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6408                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6409                 /*
6410                  * SDM 3: 27.7.1.2 (September 2008)
6411                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6412                  * a guest IRET fault.
6413                  * SDM 3: 23.2.2 (September 2008)
6414                  * Bit 12 is undefined in any of the following cases:
6415                  *  If the VM exit sets the valid bit in the IDT-vectoring
6416                  *   information field.
6417                  *  If the VM exit is due to a double fault.
6418                  */
6419                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6420                     vector != DF_VECTOR && !idtv_info_valid)
6421                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6422                                       GUEST_INTR_STATE_NMI);
6423                 else
6424                         vmx->loaded_vmcs->nmi_known_unmasked =
6425                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6426                                   & GUEST_INTR_STATE_NMI);
6427         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6428                 vmx->loaded_vmcs->vnmi_blocked_time +=
6429                         ktime_to_ns(ktime_sub(ktime_get(),
6430                                               vmx->loaded_vmcs->entry_time));
6431 }
6432
6433 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6434                                       u32 idt_vectoring_info,
6435                                       int instr_len_field,
6436                                       int error_code_field)
6437 {
6438         u8 vector;
6439         int type;
6440         bool idtv_info_valid;
6441
6442         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6443
6444         vcpu->arch.nmi_injected = false;
6445         kvm_clear_exception_queue(vcpu);
6446         kvm_clear_interrupt_queue(vcpu);
6447
6448         if (!idtv_info_valid)
6449                 return;
6450
6451         kvm_make_request(KVM_REQ_EVENT, vcpu);
6452
6453         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6454         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6455
6456         switch (type) {
6457         case INTR_TYPE_NMI_INTR:
6458                 vcpu->arch.nmi_injected = true;
6459                 /*
6460                  * SDM 3: 27.7.1.2 (September 2008)
6461                  * Clear bit "block by NMI" before VM entry if a NMI
6462                  * delivery faulted.
6463                  */
6464                 vmx_set_nmi_mask(vcpu, false);
6465                 break;
6466         case INTR_TYPE_SOFT_EXCEPTION:
6467                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6468                 /* fall through */
6469         case INTR_TYPE_HARD_EXCEPTION:
6470                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6471                         u32 err = vmcs_read32(error_code_field);
6472                         kvm_requeue_exception_e(vcpu, vector, err);
6473                 } else
6474                         kvm_requeue_exception(vcpu, vector);
6475                 break;
6476         case INTR_TYPE_SOFT_INTR:
6477                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6478                 /* fall through */
6479         case INTR_TYPE_EXT_INTR:
6480                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6481                 break;
6482         default:
6483                 break;
6484         }
6485 }
6486
6487 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6488 {
6489         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6490                                   VM_EXIT_INSTRUCTION_LEN,
6491                                   IDT_VECTORING_ERROR_CODE);
6492 }
6493
6494 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6495 {
6496         __vmx_complete_interrupts(vcpu,
6497                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6498                                   VM_ENTRY_INSTRUCTION_LEN,
6499                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6500
6501         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6502 }
6503
6504 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6505 {
6506         int i, nr_msrs;
6507         struct perf_guest_switch_msr *msrs;
6508
6509         msrs = perf_guest_get_msrs(&nr_msrs);
6510
6511         if (!msrs)
6512                 return;
6513
6514         for (i = 0; i < nr_msrs; i++)
6515                 if (msrs[i].host == msrs[i].guest)
6516                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6517                 else
6518                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6519                                         msrs[i].host, false);
6520 }
6521
6522 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6523 {
6524         u32 host_umwait_control;
6525
6526         if (!vmx_has_waitpkg(vmx))
6527                 return;
6528
6529         host_umwait_control = get_umwait_control_msr();
6530
6531         if (vmx->msr_ia32_umwait_control != host_umwait_control)
6532                 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6533                         vmx->msr_ia32_umwait_control,
6534                         host_umwait_control, false);
6535         else
6536                 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6537 }
6538
6539 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6540 {
6541         struct vcpu_vmx *vmx = to_vmx(vcpu);
6542         u64 tscl;
6543         u32 delta_tsc;
6544
6545         if (vmx->req_immediate_exit) {
6546                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6547                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6548         } else if (vmx->hv_deadline_tsc != -1) {
6549                 tscl = rdtsc();
6550                 if (vmx->hv_deadline_tsc > tscl)
6551                         /* set_hv_timer ensures the delta fits in 32-bits */
6552                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6553                                 cpu_preemption_timer_multi);
6554                 else
6555                         delta_tsc = 0;
6556
6557                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6558                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6559         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6560                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6561                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6562         }
6563 }
6564
6565 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6566 {
6567         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6568                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6569                 vmcs_writel(HOST_RSP, host_rsp);
6570         }
6571 }
6572
6573 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6574
6575 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6576 {
6577         struct vcpu_vmx *vmx = to_vmx(vcpu);
6578         unsigned long cr3, cr4;
6579
6580         /* Record the guest's net vcpu time for enforced NMI injections. */
6581         if (unlikely(!enable_vnmi &&
6582                      vmx->loaded_vmcs->soft_vnmi_blocked))
6583                 vmx->loaded_vmcs->entry_time = ktime_get();
6584
6585         /* Don't enter VMX if guest state is invalid, let the exit handler
6586            start emulation until we arrive back to a valid state */
6587         if (vmx->emulation_required)
6588                 return;
6589
6590         if (vmx->ple_window_dirty) {
6591                 vmx->ple_window_dirty = false;
6592                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6593         }
6594
6595         /*
6596          * We did this in prepare_switch_to_guest, because it needs to
6597          * be within srcu_read_lock.
6598          */
6599         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6600
6601         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6602                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6603         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6604                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6605
6606         cr3 = __get_current_cr3_fast();
6607         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6608                 vmcs_writel(HOST_CR3, cr3);
6609                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6610         }
6611
6612         cr4 = cr4_read_shadow();
6613         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6614                 vmcs_writel(HOST_CR4, cr4);
6615                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6616         }
6617
6618         /* When single-stepping over STI and MOV SS, we must clear the
6619          * corresponding interruptibility bits in the guest state. Otherwise
6620          * vmentry fails as it then expects bit 14 (BS) in pending debug
6621          * exceptions being set, but that's not correct for the guest debugging
6622          * case. */
6623         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6624                 vmx_set_interrupt_shadow(vcpu, 0);
6625
6626         kvm_load_guest_xsave_state(vcpu);
6627
6628         if (static_cpu_has(X86_FEATURE_PKU) &&
6629             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6630             vcpu->arch.pkru != vmx->host_pkru)
6631                 __write_pkru(vcpu->arch.pkru);
6632
6633         pt_guest_enter(vmx);
6634
6635         if (vcpu_to_pmu(vcpu)->version)
6636                 atomic_switch_perf_msrs(vmx);
6637         atomic_switch_umwait_control_msr(vmx);
6638
6639         if (enable_preemption_timer)
6640                 vmx_update_hv_timer(vcpu);
6641
6642         if (lapic_in_kernel(vcpu) &&
6643                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6644                 kvm_wait_lapic_expire(vcpu);
6645
6646         /*
6647          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6648          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6649          * is no need to worry about the conditional branch over the wrmsr
6650          * being speculatively taken.
6651          */
6652         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6653
6654         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6655         if (static_branch_unlikely(&vmx_l1d_should_flush))
6656                 vmx_l1d_flush(vcpu);
6657         else if (static_branch_unlikely(&mds_user_clear))
6658                 mds_clear_cpu_buffers();
6659
6660         if (vcpu->arch.cr2 != read_cr2())
6661                 write_cr2(vcpu->arch.cr2);
6662
6663         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6664                                    vmx->loaded_vmcs->launched);
6665
6666         vcpu->arch.cr2 = read_cr2();
6667
6668         /*
6669          * We do not use IBRS in the kernel. If this vCPU has used the
6670          * SPEC_CTRL MSR it may have left it on; save the value and
6671          * turn it off. This is much more efficient than blindly adding
6672          * it to the atomic save/restore list. Especially as the former
6673          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6674          *
6675          * For non-nested case:
6676          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6677          * save it.
6678          *
6679          * For nested case:
6680          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6681          * save it.
6682          */
6683         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6684                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6685
6686         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6687
6688         /* All fields are clean at this point */
6689         if (static_branch_unlikely(&enable_evmcs))
6690                 current_evmcs->hv_clean_fields |=
6691                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6692
6693         if (static_branch_unlikely(&enable_evmcs))
6694                 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6695
6696         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6697         if (vmx->host_debugctlmsr)
6698                 update_debugctlmsr(vmx->host_debugctlmsr);
6699
6700 #ifndef CONFIG_X86_64
6701         /*
6702          * The sysexit path does not restore ds/es, so we must set them to
6703          * a reasonable value ourselves.
6704          *
6705          * We can't defer this to vmx_prepare_switch_to_host() since that
6706          * function may be executed in interrupt context, which saves and
6707          * restore segments around it, nullifying its effect.
6708          */
6709         loadsegment(ds, __USER_DS);
6710         loadsegment(es, __USER_DS);
6711 #endif
6712
6713         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6714                                   | (1 << VCPU_EXREG_RFLAGS)
6715                                   | (1 << VCPU_EXREG_PDPTR)
6716                                   | (1 << VCPU_EXREG_SEGMENTS)
6717                                   | (1 << VCPU_EXREG_CR3));
6718         vcpu->arch.regs_dirty = 0;
6719
6720         pt_guest_exit(vmx);
6721
6722         /*
6723          * eager fpu is enabled if PKEY is supported and CR4 is switched
6724          * back on host, so it is safe to read guest PKRU from current
6725          * XSAVE.
6726          */
6727         if (static_cpu_has(X86_FEATURE_PKU) &&
6728             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6729                 vcpu->arch.pkru = rdpkru();
6730                 if (vcpu->arch.pkru != vmx->host_pkru)
6731                         __write_pkru(vmx->host_pkru);
6732         }
6733
6734         kvm_load_host_xsave_state(vcpu);
6735
6736         vmx->nested.nested_run_pending = 0;
6737         vmx->idt_vectoring_info = 0;
6738
6739         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6740         if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6741                 kvm_machine_check();
6742
6743         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6744                 return;
6745
6746         vmx->loaded_vmcs->launched = 1;
6747         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6748
6749         vmx_recover_nmi_blocking(vmx);
6750         vmx_complete_interrupts(vmx);
6751 }
6752
6753 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6754 {
6755         struct vcpu_vmx *vmx = to_vmx(vcpu);
6756
6757         if (enable_pml)
6758                 vmx_destroy_pml_buffer(vmx);
6759         free_vpid(vmx->vpid);
6760         nested_vmx_free_vcpu(vcpu);
6761         free_loaded_vmcs(vmx->loaded_vmcs);
6762 }
6763
6764 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6765 {
6766         struct vcpu_vmx *vmx;
6767         unsigned long *msr_bitmap;
6768         int i, cpu, err;
6769
6770         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6771         vmx = to_vmx(vcpu);
6772
6773         err = -ENOMEM;
6774
6775         vmx->vpid = allocate_vpid();
6776
6777         /*
6778          * If PML is turned on, failure on enabling PML just results in failure
6779          * of creating the vcpu, therefore we can simplify PML logic (by
6780          * avoiding dealing with cases, such as enabling PML partially on vcpus
6781          * for the guest), etc.
6782          */
6783         if (enable_pml) {
6784                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6785                 if (!vmx->pml_pg)
6786                         goto free_vpid;
6787         }
6788
6789         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
6790
6791         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6792                 u32 index = vmx_msr_index[i];
6793                 u32 data_low, data_high;
6794                 int j = vmx->nmsrs;
6795
6796                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6797                         continue;
6798                 if (wrmsr_safe(index, data_low, data_high) < 0)
6799                         continue;
6800
6801                 vmx->guest_msrs[j].index = i;
6802                 vmx->guest_msrs[j].data = 0;
6803                 switch (index) {
6804                 case MSR_IA32_TSX_CTRL:
6805                         /*
6806                          * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6807                          * let's avoid changing CPUID bits under the host
6808                          * kernel's feet.
6809                          */
6810                         vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6811                         break;
6812                 default:
6813                         vmx->guest_msrs[j].mask = -1ull;
6814                         break;
6815                 }
6816                 ++vmx->nmsrs;
6817         }
6818
6819         err = alloc_loaded_vmcs(&vmx->vmcs01);
6820         if (err < 0)
6821                 goto free_pml;
6822
6823         msr_bitmap = vmx->vmcs01.msr_bitmap;
6824         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6825         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6826         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6827         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6828         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6829         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6830         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6831         if (kvm_cstate_in_guest(vcpu->kvm)) {
6832                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6833                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6834                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6835                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6836         }
6837         vmx->msr_bitmap_mode = 0;
6838
6839         vmx->loaded_vmcs = &vmx->vmcs01;
6840         cpu = get_cpu();
6841         vmx_vcpu_load(vcpu, cpu);
6842         vcpu->cpu = cpu;
6843         init_vmcs(vmx);
6844         vmx_vcpu_put(vcpu);
6845         put_cpu();
6846         if (cpu_need_virtualize_apic_accesses(vcpu)) {
6847                 err = alloc_apic_access_page(vcpu->kvm);
6848                 if (err)
6849                         goto free_vmcs;
6850         }
6851
6852         if (enable_ept && !enable_unrestricted_guest) {
6853                 err = init_rmode_identity_map(vcpu->kvm);
6854                 if (err)
6855                         goto free_vmcs;
6856         }
6857
6858         if (nested)
6859                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6860                                            vmx_capability.ept);
6861         else
6862                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6863
6864         vmx->nested.posted_intr_nv = -1;
6865         vmx->nested.current_vmptr = -1ull;
6866
6867         vcpu->arch.microcode_version = 0x100000000ULL;
6868         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6869
6870         /*
6871          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6872          * or POSTED_INTR_WAKEUP_VECTOR.
6873          */
6874         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6875         vmx->pi_desc.sn = 1;
6876
6877         vmx->ept_pointer = INVALID_PAGE;
6878
6879         return 0;
6880
6881 free_vmcs:
6882         free_loaded_vmcs(vmx->loaded_vmcs);
6883 free_pml:
6884         vmx_destroy_pml_buffer(vmx);
6885 free_vpid:
6886         free_vpid(vmx->vpid);
6887         return err;
6888 }
6889
6890 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6891 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6892
6893 static int vmx_vm_init(struct kvm *kvm)
6894 {
6895         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6896
6897         if (!ple_gap)
6898                 kvm->arch.pause_in_guest = true;
6899
6900         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6901                 switch (l1tf_mitigation) {
6902                 case L1TF_MITIGATION_OFF:
6903                 case L1TF_MITIGATION_FLUSH_NOWARN:
6904                         /* 'I explicitly don't care' is set */
6905                         break;
6906                 case L1TF_MITIGATION_FLUSH:
6907                 case L1TF_MITIGATION_FLUSH_NOSMT:
6908                 case L1TF_MITIGATION_FULL:
6909                         /*
6910                          * Warn upon starting the first VM in a potentially
6911                          * insecure environment.
6912                          */
6913                         if (sched_smt_active())
6914                                 pr_warn_once(L1TF_MSG_SMT);
6915                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6916                                 pr_warn_once(L1TF_MSG_L1D);
6917                         break;
6918                 case L1TF_MITIGATION_FULL_FORCE:
6919                         /* Flush is enforced */
6920                         break;
6921                 }
6922         }
6923         kvm_apicv_init(kvm, enable_apicv);
6924         return 0;
6925 }
6926
6927 static int __init vmx_check_processor_compat(void)
6928 {
6929         struct vmcs_config vmcs_conf;
6930         struct vmx_capability vmx_cap;
6931
6932         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6933             !this_cpu_has(X86_FEATURE_VMX)) {
6934                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6935                 return -EIO;
6936         }
6937
6938         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6939                 return -EIO;
6940         if (nested)
6941                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6942         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6943                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6944                                 smp_processor_id());
6945                 return -EIO;
6946         }
6947         return 0;
6948 }
6949
6950 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6951 {
6952         u8 cache;
6953         u64 ipat = 0;
6954
6955         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6956          * memory aliases with conflicting memory types and sometimes MCEs.
6957          * We have to be careful as to what are honored and when.
6958          *
6959          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
6960          * UC.  The effective memory type is UC or WC depending on guest PAT.
6961          * This was historically the source of MCEs and we want to be
6962          * conservative.
6963          *
6964          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6965          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
6966          * EPT memory type is set to WB.  The effective memory type is forced
6967          * WB.
6968          *
6969          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
6970          * EPT memory type is used to emulate guest CD/MTRR.
6971          */
6972
6973         if (is_mmio) {
6974                 cache = MTRR_TYPE_UNCACHABLE;
6975                 goto exit;
6976         }
6977
6978         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6979                 ipat = VMX_EPT_IPAT_BIT;
6980                 cache = MTRR_TYPE_WRBACK;
6981                 goto exit;
6982         }
6983
6984         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6985                 ipat = VMX_EPT_IPAT_BIT;
6986                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6987                         cache = MTRR_TYPE_WRBACK;
6988                 else
6989                         cache = MTRR_TYPE_UNCACHABLE;
6990                 goto exit;
6991         }
6992
6993         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6994
6995 exit:
6996         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6997 }
6998
6999 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
7000 {
7001         /*
7002          * These bits in the secondary execution controls field
7003          * are dynamic, the others are mostly based on the hypervisor
7004          * architecture and the guest's CPUID.  Do not touch the
7005          * dynamic bits.
7006          */
7007         u32 mask =
7008                 SECONDARY_EXEC_SHADOW_VMCS |
7009                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7010                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7011                 SECONDARY_EXEC_DESC;
7012
7013         u32 new_ctl = vmx->secondary_exec_control;
7014         u32 cur_ctl = secondary_exec_controls_get(vmx);
7015
7016         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7017 }
7018
7019 /*
7020  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7021  * (indicating "allowed-1") if they are supported in the guest's CPUID.
7022  */
7023 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7024 {
7025         struct vcpu_vmx *vmx = to_vmx(vcpu);
7026         struct kvm_cpuid_entry2 *entry;
7027
7028         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7029         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7030
7031 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
7032         if (entry && (entry->_reg & (_cpuid_mask)))                     \
7033                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
7034 } while (0)
7035
7036         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7037         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
7038         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
7039         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
7040         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
7041         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
7042         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
7043         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
7044         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
7045         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
7046         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7047         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
7048         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
7049         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
7050         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
7051
7052         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7053         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
7054         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
7055         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
7056         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
7057         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
7058         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
7059
7060 #undef cr4_fixed1_update
7061 }
7062
7063 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7064 {
7065         struct vcpu_vmx *vmx = to_vmx(vcpu);
7066
7067         if (kvm_mpx_supported()) {
7068                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7069
7070                 if (mpx_enabled) {
7071                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7072                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7073                 } else {
7074                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7075                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7076                 }
7077         }
7078 }
7079
7080 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7081 {
7082         struct vcpu_vmx *vmx = to_vmx(vcpu);
7083         struct kvm_cpuid_entry2 *best = NULL;
7084         int i;
7085
7086         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7087                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7088                 if (!best)
7089                         return;
7090                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7091                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7092                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7093                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7094         }
7095
7096         /* Get the number of configurable Address Ranges for filtering */
7097         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7098                                                 PT_CAP_num_address_ranges);
7099
7100         /* Initialize and clear the no dependency bits */
7101         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7102                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7103
7104         /*
7105          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7106          * will inject an #GP
7107          */
7108         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7109                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7110
7111         /*
7112          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7113          * PSBFreq can be set
7114          */
7115         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7116                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7117                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7118
7119         /*
7120          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7121          * MTCFreq can be set
7122          */
7123         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7124                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7125                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7126
7127         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7128         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7129                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7130                                                         RTIT_CTL_PTW_EN);
7131
7132         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7133         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7134                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7135
7136         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7137         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7138                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7139
7140         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7141         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7142                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7143
7144         /* unmask address range configure area */
7145         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7146                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7147 }
7148
7149 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7150 {
7151         struct vcpu_vmx *vmx = to_vmx(vcpu);
7152
7153         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7154         vcpu->arch.xsaves_enabled = false;
7155
7156         if (cpu_has_secondary_exec_ctrls()) {
7157                 vmx_compute_secondary_exec_control(vmx);
7158                 vmcs_set_secondary_exec_control(vmx);
7159         }
7160
7161         if (nested_vmx_allowed(vcpu))
7162                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7163                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7164                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7165         else
7166                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7167                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7168                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7169
7170         if (nested_vmx_allowed(vcpu)) {
7171                 nested_vmx_cr_fixed1_bits_update(vcpu);
7172                 nested_vmx_entry_exit_ctls_update(vcpu);
7173         }
7174
7175         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7176                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7177                 update_intel_pt_cfg(vcpu);
7178
7179         if (boot_cpu_has(X86_FEATURE_RTM)) {
7180                 struct shared_msr_entry *msr;
7181                 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7182                 if (msr) {
7183                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7184                         vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7185                 }
7186         }
7187 }
7188
7189 static __init void vmx_set_cpu_caps(void)
7190 {
7191         kvm_set_cpu_caps();
7192
7193         /* CPUID 0x1 */
7194         if (nested)
7195                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7196
7197         /* CPUID 0x7 */
7198         if (kvm_mpx_supported())
7199                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7200         if (cpu_has_vmx_invpcid())
7201                 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
7202         if (vmx_pt_mode_is_host_guest())
7203                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7204
7205         /* PKU is not yet implemented for shadow paging. */
7206         if (enable_ept && boot_cpu_has(X86_FEATURE_OSPKE))
7207                 kvm_cpu_cap_check_and_set(X86_FEATURE_PKU);
7208
7209         if (vmx_umip_emulated())
7210                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7211
7212         /* CPUID 0xD.1 */
7213         supported_xss = 0;
7214         if (!vmx_xsaves_supported())
7215                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7216
7217         /* CPUID 0x80000001 */
7218         if (!cpu_has_vmx_rdtscp())
7219                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7220 }
7221
7222 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7223 {
7224         to_vmx(vcpu)->req_immediate_exit = true;
7225 }
7226
7227 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7228                                   struct x86_instruction_info *info)
7229 {
7230         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7231         unsigned short port;
7232         bool intercept;
7233         int size;
7234
7235         if (info->intercept == x86_intercept_in ||
7236             info->intercept == x86_intercept_ins) {
7237                 port = info->src_val;
7238                 size = info->dst_bytes;
7239         } else {
7240                 port = info->dst_val;
7241                 size = info->src_bytes;
7242         }
7243
7244         /*
7245          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7246          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7247          * control.
7248          *
7249          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7250          */
7251         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7252                 intercept = nested_cpu_has(vmcs12,
7253                                            CPU_BASED_UNCOND_IO_EXITING);
7254         else
7255                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7256
7257         /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7258         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7259 }
7260
7261 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7262                                struct x86_instruction_info *info,
7263                                enum x86_intercept_stage stage,
7264                                struct x86_exception *exception)
7265 {
7266         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7267
7268         switch (info->intercept) {
7269         /*
7270          * RDPID causes #UD if disabled through secondary execution controls.
7271          * Because it is marked as EmulateOnUD, we need to intercept it here.
7272          */
7273         case x86_intercept_rdtscp:
7274                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7275                         exception->vector = UD_VECTOR;
7276                         exception->error_code_valid = false;
7277                         return X86EMUL_PROPAGATE_FAULT;
7278                 }
7279                 break;
7280
7281         case x86_intercept_in:
7282         case x86_intercept_ins:
7283         case x86_intercept_out:
7284         case x86_intercept_outs:
7285                 return vmx_check_intercept_io(vcpu, info);
7286
7287         case x86_intercept_lgdt:
7288         case x86_intercept_lidt:
7289         case x86_intercept_lldt:
7290         case x86_intercept_ltr:
7291         case x86_intercept_sgdt:
7292         case x86_intercept_sidt:
7293         case x86_intercept_sldt:
7294         case x86_intercept_str:
7295                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7296                         return X86EMUL_CONTINUE;
7297
7298                 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7299                 break;
7300
7301         /* TODO: check more intercepts... */
7302         default:
7303                 break;
7304         }
7305
7306         return X86EMUL_UNHANDLEABLE;
7307 }
7308
7309 #ifdef CONFIG_X86_64
7310 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7311 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7312                                   u64 divisor, u64 *result)
7313 {
7314         u64 low = a << shift, high = a >> (64 - shift);
7315
7316         /* To avoid the overflow on divq */
7317         if (high >= divisor)
7318                 return 1;
7319
7320         /* Low hold the result, high hold rem which is discarded */
7321         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7322             "rm" (divisor), "0" (low), "1" (high));
7323         *result = low;
7324
7325         return 0;
7326 }
7327
7328 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7329                             bool *expired)
7330 {
7331         struct vcpu_vmx *vmx;
7332         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7333         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7334
7335         if (kvm_mwait_in_guest(vcpu->kvm) ||
7336                 kvm_can_post_timer_interrupt(vcpu))
7337                 return -EOPNOTSUPP;
7338
7339         vmx = to_vmx(vcpu);
7340         tscl = rdtsc();
7341         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7342         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7343         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7344                                                     ktimer->timer_advance_ns);
7345
7346         if (delta_tsc > lapic_timer_advance_cycles)
7347                 delta_tsc -= lapic_timer_advance_cycles;
7348         else
7349                 delta_tsc = 0;
7350
7351         /* Convert to host delta tsc if tsc scaling is enabled */
7352         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7353             delta_tsc && u64_shl_div_u64(delta_tsc,
7354                                 kvm_tsc_scaling_ratio_frac_bits,
7355                                 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7356                 return -ERANGE;
7357
7358         /*
7359          * If the delta tsc can't fit in the 32 bit after the multi shift,
7360          * we can't use the preemption timer.
7361          * It's possible that it fits on later vmentries, but checking
7362          * on every vmentry is costly so we just use an hrtimer.
7363          */
7364         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7365                 return -ERANGE;
7366
7367         vmx->hv_deadline_tsc = tscl + delta_tsc;
7368         *expired = !delta_tsc;
7369         return 0;
7370 }
7371
7372 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7373 {
7374         to_vmx(vcpu)->hv_deadline_tsc = -1;
7375 }
7376 #endif
7377
7378 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7379 {
7380         if (!kvm_pause_in_guest(vcpu->kvm))
7381                 shrink_ple_window(vcpu);
7382 }
7383
7384 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7385                                      struct kvm_memory_slot *slot)
7386 {
7387         if (!kvm_dirty_log_manual_protect_and_init_set(kvm))
7388                 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7389         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7390 }
7391
7392 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7393                                        struct kvm_memory_slot *slot)
7394 {
7395         kvm_mmu_slot_set_dirty(kvm, slot);
7396 }
7397
7398 static void vmx_flush_log_dirty(struct kvm *kvm)
7399 {
7400         kvm_flush_pml_buffers(kvm);
7401 }
7402
7403 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7404 {
7405         struct vmcs12 *vmcs12;
7406         struct vcpu_vmx *vmx = to_vmx(vcpu);
7407         gpa_t gpa, dst;
7408
7409         if (is_guest_mode(vcpu)) {
7410                 WARN_ON_ONCE(vmx->nested.pml_full);
7411
7412                 /*
7413                  * Check if PML is enabled for the nested guest.
7414                  * Whether eptp bit 6 is set is already checked
7415                  * as part of A/D emulation.
7416                  */
7417                 vmcs12 = get_vmcs12(vcpu);
7418                 if (!nested_cpu_has_pml(vmcs12))
7419                         return 0;
7420
7421                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7422                         vmx->nested.pml_full = true;
7423                         return 1;
7424                 }
7425
7426                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7427                 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7428
7429                 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7430                                          offset_in_page(dst), sizeof(gpa)))
7431                         return 0;
7432
7433                 vmcs12->guest_pml_index--;
7434         }
7435
7436         return 0;
7437 }
7438
7439 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7440                                            struct kvm_memory_slot *memslot,
7441                                            gfn_t offset, unsigned long mask)
7442 {
7443         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7444 }
7445
7446 static void __pi_post_block(struct kvm_vcpu *vcpu)
7447 {
7448         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7449         struct pi_desc old, new;
7450         unsigned int dest;
7451
7452         do {
7453                 old.control = new.control = pi_desc->control;
7454                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7455                      "Wakeup handler not enabled while the VCPU is blocked\n");
7456
7457                 dest = cpu_physical_id(vcpu->cpu);
7458
7459                 if (x2apic_enabled())
7460                         new.ndst = dest;
7461                 else
7462                         new.ndst = (dest << 8) & 0xFF00;
7463
7464                 /* set 'NV' to 'notification vector' */
7465                 new.nv = POSTED_INTR_VECTOR;
7466         } while (cmpxchg64(&pi_desc->control, old.control,
7467                            new.control) != old.control);
7468
7469         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7470                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7471                 list_del(&vcpu->blocked_vcpu_list);
7472                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7473                 vcpu->pre_pcpu = -1;
7474         }
7475 }
7476
7477 /*
7478  * This routine does the following things for vCPU which is going
7479  * to be blocked if VT-d PI is enabled.
7480  * - Store the vCPU to the wakeup list, so when interrupts happen
7481  *   we can find the right vCPU to wake up.
7482  * - Change the Posted-interrupt descriptor as below:
7483  *      'NDST' <-- vcpu->pre_pcpu
7484  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7485  * - If 'ON' is set during this process, which means at least one
7486  *   interrupt is posted for this vCPU, we cannot block it, in
7487  *   this case, return 1, otherwise, return 0.
7488  *
7489  */
7490 static int pi_pre_block(struct kvm_vcpu *vcpu)
7491 {
7492         unsigned int dest;
7493         struct pi_desc old, new;
7494         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7495
7496         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7497                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
7498                 !kvm_vcpu_apicv_active(vcpu))
7499                 return 0;
7500
7501         WARN_ON(irqs_disabled());
7502         local_irq_disable();
7503         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7504                 vcpu->pre_pcpu = vcpu->cpu;
7505                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7506                 list_add_tail(&vcpu->blocked_vcpu_list,
7507                               &per_cpu(blocked_vcpu_on_cpu,
7508                                        vcpu->pre_pcpu));
7509                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7510         }
7511
7512         do {
7513                 old.control = new.control = pi_desc->control;
7514
7515                 WARN((pi_desc->sn == 1),
7516                      "Warning: SN field of posted-interrupts "
7517                      "is set before blocking\n");
7518
7519                 /*
7520                  * Since vCPU can be preempted during this process,
7521                  * vcpu->cpu could be different with pre_pcpu, we
7522                  * need to set pre_pcpu as the destination of wakeup
7523                  * notification event, then we can find the right vCPU
7524                  * to wakeup in wakeup handler if interrupts happen
7525                  * when the vCPU is in blocked state.
7526                  */
7527                 dest = cpu_physical_id(vcpu->pre_pcpu);
7528
7529                 if (x2apic_enabled())
7530                         new.ndst = dest;
7531                 else
7532                         new.ndst = (dest << 8) & 0xFF00;
7533
7534                 /* set 'NV' to 'wakeup vector' */
7535                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7536         } while (cmpxchg64(&pi_desc->control, old.control,
7537                            new.control) != old.control);
7538
7539         /* We should not block the vCPU if an interrupt is posted for it.  */
7540         if (pi_test_on(pi_desc) == 1)
7541                 __pi_post_block(vcpu);
7542
7543         local_irq_enable();
7544         return (vcpu->pre_pcpu == -1);
7545 }
7546
7547 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7548 {
7549         if (pi_pre_block(vcpu))
7550                 return 1;
7551
7552         if (kvm_lapic_hv_timer_in_use(vcpu))
7553                 kvm_lapic_switch_to_sw_timer(vcpu);
7554
7555         return 0;
7556 }
7557
7558 static void pi_post_block(struct kvm_vcpu *vcpu)
7559 {
7560         if (vcpu->pre_pcpu == -1)
7561                 return;
7562
7563         WARN_ON(irqs_disabled());
7564         local_irq_disable();
7565         __pi_post_block(vcpu);
7566         local_irq_enable();
7567 }
7568
7569 static void vmx_post_block(struct kvm_vcpu *vcpu)
7570 {
7571         if (kvm_x86_ops.set_hv_timer)
7572                 kvm_lapic_switch_to_hv_timer(vcpu);
7573
7574         pi_post_block(vcpu);
7575 }
7576
7577 /*
7578  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7579  *
7580  * @kvm: kvm
7581  * @host_irq: host irq of the interrupt
7582  * @guest_irq: gsi of the interrupt
7583  * @set: set or unset PI
7584  * returns 0 on success, < 0 on failure
7585  */
7586 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7587                               uint32_t guest_irq, bool set)
7588 {
7589         struct kvm_kernel_irq_routing_entry *e;
7590         struct kvm_irq_routing_table *irq_rt;
7591         struct kvm_lapic_irq irq;
7592         struct kvm_vcpu *vcpu;
7593         struct vcpu_data vcpu_info;
7594         int idx, ret = 0;
7595
7596         if (!kvm_arch_has_assigned_device(kvm) ||
7597                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7598                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7599                 return 0;
7600
7601         idx = srcu_read_lock(&kvm->irq_srcu);
7602         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7603         if (guest_irq >= irq_rt->nr_rt_entries ||
7604             hlist_empty(&irq_rt->map[guest_irq])) {
7605                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7606                              guest_irq, irq_rt->nr_rt_entries);
7607                 goto out;
7608         }
7609
7610         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7611                 if (e->type != KVM_IRQ_ROUTING_MSI)
7612                         continue;
7613                 /*
7614                  * VT-d PI cannot support posting multicast/broadcast
7615                  * interrupts to a vCPU, we still use interrupt remapping
7616                  * for these kind of interrupts.
7617                  *
7618                  * For lowest-priority interrupts, we only support
7619                  * those with single CPU as the destination, e.g. user
7620                  * configures the interrupts via /proc/irq or uses
7621                  * irqbalance to make the interrupts single-CPU.
7622                  *
7623                  * We will support full lowest-priority interrupt later.
7624                  *
7625                  * In addition, we can only inject generic interrupts using
7626                  * the PI mechanism, refuse to route others through it.
7627                  */
7628
7629                 kvm_set_msi_irq(kvm, e, &irq);
7630                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7631                     !kvm_irq_is_postable(&irq)) {
7632                         /*
7633                          * Make sure the IRTE is in remapped mode if
7634                          * we don't handle it in posted mode.
7635                          */
7636                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7637                         if (ret < 0) {
7638                                 printk(KERN_INFO
7639                                    "failed to back to remapped mode, irq: %u\n",
7640                                    host_irq);
7641                                 goto out;
7642                         }
7643
7644                         continue;
7645                 }
7646
7647                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7648                 vcpu_info.vector = irq.vector;
7649
7650                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7651                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7652
7653                 if (set)
7654                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7655                 else
7656                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7657
7658                 if (ret < 0) {
7659                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
7660                                         __func__);
7661                         goto out;
7662                 }
7663         }
7664
7665         ret = 0;
7666 out:
7667         srcu_read_unlock(&kvm->irq_srcu, idx);
7668         return ret;
7669 }
7670
7671 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7672 {
7673         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7674                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7675                         FEAT_CTL_LMCE_ENABLED;
7676         else
7677                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7678                         ~FEAT_CTL_LMCE_ENABLED;
7679 }
7680
7681 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7682 {
7683         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7684         if (to_vmx(vcpu)->nested.nested_run_pending)
7685                 return 0;
7686         return 1;
7687 }
7688
7689 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7690 {
7691         struct vcpu_vmx *vmx = to_vmx(vcpu);
7692
7693         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7694         if (vmx->nested.smm.guest_mode)
7695                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7696
7697         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7698         vmx->nested.vmxon = false;
7699         vmx_clear_hlt(vcpu);
7700         return 0;
7701 }
7702
7703 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7704 {
7705         struct vcpu_vmx *vmx = to_vmx(vcpu);
7706         int ret;
7707
7708         if (vmx->nested.smm.vmxon) {
7709                 vmx->nested.vmxon = true;
7710                 vmx->nested.smm.vmxon = false;
7711         }
7712
7713         if (vmx->nested.smm.guest_mode) {
7714                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7715                 if (ret)
7716                         return ret;
7717
7718                 vmx->nested.smm.guest_mode = false;
7719         }
7720         return 0;
7721 }
7722
7723 static int enable_smi_window(struct kvm_vcpu *vcpu)
7724 {
7725         return 0;
7726 }
7727
7728 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7729 {
7730         return false;
7731 }
7732
7733 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7734 {
7735         return to_vmx(vcpu)->nested.vmxon;
7736 }
7737
7738 static void hardware_unsetup(void)
7739 {
7740         if (nested)
7741                 nested_vmx_hardware_unsetup();
7742
7743         free_kvm_area();
7744 }
7745
7746 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7747 {
7748         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7749                           BIT(APICV_INHIBIT_REASON_HYPERV);
7750
7751         return supported & BIT(bit);
7752 }
7753
7754 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7755         .hardware_unsetup = hardware_unsetup,
7756
7757         .hardware_enable = hardware_enable,
7758         .hardware_disable = hardware_disable,
7759         .cpu_has_accelerated_tpr = report_flexpriority,
7760         .has_emulated_msr = vmx_has_emulated_msr,
7761
7762         .vm_size = sizeof(struct kvm_vmx),
7763         .vm_init = vmx_vm_init,
7764
7765         .vcpu_create = vmx_create_vcpu,
7766         .vcpu_free = vmx_free_vcpu,
7767         .vcpu_reset = vmx_vcpu_reset,
7768
7769         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7770         .vcpu_load = vmx_vcpu_load,
7771         .vcpu_put = vmx_vcpu_put,
7772
7773         .update_bp_intercept = update_exception_bitmap,
7774         .get_msr_feature = vmx_get_msr_feature,
7775         .get_msr = vmx_get_msr,
7776         .set_msr = vmx_set_msr,
7777         .get_segment_base = vmx_get_segment_base,
7778         .get_segment = vmx_get_segment,
7779         .set_segment = vmx_set_segment,
7780         .get_cpl = vmx_get_cpl,
7781         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7782         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7783         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7784         .set_cr0 = vmx_set_cr0,
7785         .set_cr4 = vmx_set_cr4,
7786         .set_efer = vmx_set_efer,
7787         .get_idt = vmx_get_idt,
7788         .set_idt = vmx_set_idt,
7789         .get_gdt = vmx_get_gdt,
7790         .set_gdt = vmx_set_gdt,
7791         .get_dr6 = vmx_get_dr6,
7792         .set_dr6 = vmx_set_dr6,
7793         .set_dr7 = vmx_set_dr7,
7794         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7795         .cache_reg = vmx_cache_reg,
7796         .get_rflags = vmx_get_rflags,
7797         .set_rflags = vmx_set_rflags,
7798
7799         .tlb_flush_all = vmx_flush_tlb_all,
7800         .tlb_flush_current = vmx_flush_tlb_current,
7801         .tlb_flush_gva = vmx_flush_tlb_gva,
7802         .tlb_flush_guest = vmx_flush_tlb_guest,
7803
7804         .run = vmx_vcpu_run,
7805         .handle_exit = vmx_handle_exit,
7806         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7807         .update_emulated_instruction = vmx_update_emulated_instruction,
7808         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7809         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7810         .patch_hypercall = vmx_patch_hypercall,
7811         .set_irq = vmx_inject_irq,
7812         .set_nmi = vmx_inject_nmi,
7813         .queue_exception = vmx_queue_exception,
7814         .cancel_injection = vmx_cancel_injection,
7815         .interrupt_allowed = vmx_interrupt_allowed,
7816         .nmi_allowed = vmx_nmi_allowed,
7817         .get_nmi_mask = vmx_get_nmi_mask,
7818         .set_nmi_mask = vmx_set_nmi_mask,
7819         .enable_nmi_window = enable_nmi_window,
7820         .enable_irq_window = enable_irq_window,
7821         .update_cr8_intercept = update_cr8_intercept,
7822         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7823         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7824         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7825         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7826         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7827         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7828         .hwapic_irr_update = vmx_hwapic_irr_update,
7829         .hwapic_isr_update = vmx_hwapic_isr_update,
7830         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7831         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7832         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7833         .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7834
7835         .set_tss_addr = vmx_set_tss_addr,
7836         .set_identity_map_addr = vmx_set_identity_map_addr,
7837         .get_tdp_level = get_ept_level,
7838         .get_mt_mask = vmx_get_mt_mask,
7839
7840         .get_exit_info = vmx_get_exit_info,
7841
7842         .cpuid_update = vmx_cpuid_update,
7843
7844         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7845
7846         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7847         .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7848
7849         .load_mmu_pgd = vmx_load_mmu_pgd,
7850
7851         .check_intercept = vmx_check_intercept,
7852         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7853
7854         .request_immediate_exit = vmx_request_immediate_exit,
7855
7856         .sched_in = vmx_sched_in,
7857
7858         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7859         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7860         .flush_log_dirty = vmx_flush_log_dirty,
7861         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7862         .write_log_dirty = vmx_write_pml_buffer,
7863
7864         .pre_block = vmx_pre_block,
7865         .post_block = vmx_post_block,
7866
7867         .pmu_ops = &intel_pmu_ops,
7868
7869         .update_pi_irte = vmx_update_pi_irte,
7870
7871 #ifdef CONFIG_X86_64
7872         .set_hv_timer = vmx_set_hv_timer,
7873         .cancel_hv_timer = vmx_cancel_hv_timer,
7874 #endif
7875
7876         .setup_mce = vmx_setup_mce,
7877
7878         .smi_allowed = vmx_smi_allowed,
7879         .pre_enter_smm = vmx_pre_enter_smm,
7880         .pre_leave_smm = vmx_pre_leave_smm,
7881         .enable_smi_window = enable_smi_window,
7882
7883         .check_nested_events = NULL,
7884         .get_nested_state = NULL,
7885         .set_nested_state = NULL,
7886         .get_vmcs12_pages = NULL,
7887         .nested_enable_evmcs = NULL,
7888         .nested_get_evmcs_version = NULL,
7889         .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7890         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7891 };
7892
7893 static __init int hardware_setup(void)
7894 {
7895         unsigned long host_bndcfgs;
7896         struct desc_ptr dt;
7897         int r, i, ept_lpage_level;
7898
7899         store_idt(&dt);
7900         host_idt_base = dt.address;
7901
7902         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7903                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7904
7905         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7906                 return -EIO;
7907
7908         if (boot_cpu_has(X86_FEATURE_NX))
7909                 kvm_enable_efer_bits(EFER_NX);
7910
7911         if (boot_cpu_has(X86_FEATURE_MPX)) {
7912                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7913                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7914         }
7915
7916         if (!cpu_has_vmx_mpx())
7917                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7918                                     XFEATURE_MASK_BNDCSR);
7919
7920         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7921             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7922                 enable_vpid = 0;
7923
7924         if (!cpu_has_vmx_ept() ||
7925             !cpu_has_vmx_ept_4levels() ||
7926             !cpu_has_vmx_ept_mt_wb() ||
7927             !cpu_has_vmx_invept_global())
7928                 enable_ept = 0;
7929
7930         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7931                 enable_ept_ad_bits = 0;
7932
7933         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7934                 enable_unrestricted_guest = 0;
7935
7936         if (!cpu_has_vmx_flexpriority())
7937                 flexpriority_enabled = 0;
7938
7939         if (!cpu_has_virtual_nmis())
7940                 enable_vnmi = 0;
7941
7942         /*
7943          * set_apic_access_page_addr() is used to reload apic access
7944          * page upon invalidation.  No need to do anything if not
7945          * using the APIC_ACCESS_ADDR VMCS field.
7946          */
7947         if (!flexpriority_enabled)
7948                 vmx_x86_ops.set_apic_access_page_addr = NULL;
7949
7950         if (!cpu_has_vmx_tpr_shadow())
7951                 vmx_x86_ops.update_cr8_intercept = NULL;
7952
7953 #if IS_ENABLED(CONFIG_HYPERV)
7954         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7955             && enable_ept) {
7956                 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7957                 vmx_x86_ops.tlb_remote_flush_with_range =
7958                                 hv_remote_flush_tlb_with_range;
7959         }
7960 #endif
7961
7962         if (!cpu_has_vmx_ple()) {
7963                 ple_gap = 0;
7964                 ple_window = 0;
7965                 ple_window_grow = 0;
7966                 ple_window_max = 0;
7967                 ple_window_shrink = 0;
7968         }
7969
7970         if (!cpu_has_vmx_apicv()) {
7971                 enable_apicv = 0;
7972                 vmx_x86_ops.sync_pir_to_irr = NULL;
7973         }
7974
7975         if (cpu_has_vmx_tsc_scaling()) {
7976                 kvm_has_tsc_control = true;
7977                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7978                 kvm_tsc_scaling_ratio_frac_bits = 48;
7979         }
7980
7981         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7982
7983         if (enable_ept)
7984                 vmx_enable_tdp();
7985
7986         if (!enable_ept)
7987                 ept_lpage_level = 0;
7988         else if (cpu_has_vmx_ept_1g_page())
7989                 ept_lpage_level = PT_PDPE_LEVEL;
7990         else if (cpu_has_vmx_ept_2m_page())
7991                 ept_lpage_level = PT_DIRECTORY_LEVEL;
7992         else
7993                 ept_lpage_level = PT_PAGE_TABLE_LEVEL;
7994         kvm_configure_mmu(enable_ept, ept_lpage_level);
7995
7996         /*
7997          * Only enable PML when hardware supports PML feature, and both EPT
7998          * and EPT A/D bit features are enabled -- PML depends on them to work.
7999          */
8000         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
8001                 enable_pml = 0;
8002
8003         if (!enable_pml) {
8004                 vmx_x86_ops.slot_enable_log_dirty = NULL;
8005                 vmx_x86_ops.slot_disable_log_dirty = NULL;
8006                 vmx_x86_ops.flush_log_dirty = NULL;
8007                 vmx_x86_ops.enable_log_dirty_pt_masked = NULL;
8008         }
8009
8010         if (!cpu_has_vmx_preemption_timer())
8011                 enable_preemption_timer = false;
8012
8013         if (enable_preemption_timer) {
8014                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
8015                 u64 vmx_msr;
8016
8017                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
8018                 cpu_preemption_timer_multi =
8019                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
8020
8021                 if (tsc_khz)
8022                         use_timer_freq = (u64)tsc_khz * 1000;
8023                 use_timer_freq >>= cpu_preemption_timer_multi;
8024
8025                 /*
8026                  * KVM "disables" the preemption timer by setting it to its max
8027                  * value.  Don't use the timer if it might cause spurious exits
8028                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
8029                  */
8030                 if (use_timer_freq > 0xffffffffu / 10)
8031                         enable_preemption_timer = false;
8032         }
8033
8034         if (!enable_preemption_timer) {
8035                 vmx_x86_ops.set_hv_timer = NULL;
8036                 vmx_x86_ops.cancel_hv_timer = NULL;
8037                 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
8038         }
8039
8040         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
8041
8042         kvm_mce_cap_supported |= MCG_LMCE_P;
8043
8044         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
8045                 return -EINVAL;
8046         if (!enable_ept || !cpu_has_vmx_intel_pt())
8047                 pt_mode = PT_MODE_SYSTEM;
8048
8049         if (nested) {
8050                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
8051                                            vmx_capability.ept);
8052
8053                 r = nested_vmx_hardware_setup(&vmx_x86_ops,
8054                                               kvm_vmx_exit_handlers);
8055                 if (r)
8056                         return r;
8057         }
8058
8059         vmx_set_cpu_caps();
8060
8061         r = alloc_kvm_area();
8062         if (r)
8063                 nested_vmx_hardware_unsetup();
8064         return r;
8065 }
8066
8067 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
8068         .cpu_has_kvm_support = cpu_has_kvm_support,
8069         .disabled_by_bios = vmx_disabled_by_bios,
8070         .check_processor_compatibility = vmx_check_processor_compat,
8071         .hardware_setup = hardware_setup,
8072
8073         .runtime_ops = &vmx_x86_ops,
8074 };
8075
8076 static void vmx_cleanup_l1d_flush(void)
8077 {
8078         if (vmx_l1d_flush_pages) {
8079                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
8080                 vmx_l1d_flush_pages = NULL;
8081         }
8082         /* Restore state so sysfs ignores VMX */
8083         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
8084 }
8085
8086 static void vmx_exit(void)
8087 {
8088 #ifdef CONFIG_KEXEC_CORE
8089         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8090         synchronize_rcu();
8091 #endif
8092
8093         kvm_exit();
8094
8095 #if IS_ENABLED(CONFIG_HYPERV)
8096         if (static_branch_unlikely(&enable_evmcs)) {
8097                 int cpu;
8098                 struct hv_vp_assist_page *vp_ap;
8099                 /*
8100                  * Reset everything to support using non-enlightened VMCS
8101                  * access later (e.g. when we reload the module with
8102                  * enlightened_vmcs=0)
8103                  */
8104                 for_each_online_cpu(cpu) {
8105                         vp_ap = hv_get_vp_assist_page(cpu);
8106
8107                         if (!vp_ap)
8108                                 continue;
8109
8110                         vp_ap->nested_control.features.directhypercall = 0;
8111                         vp_ap->current_nested_vmcs = 0;
8112                         vp_ap->enlighten_vmentry = 0;
8113                 }
8114
8115                 static_branch_disable(&enable_evmcs);
8116         }
8117 #endif
8118         vmx_cleanup_l1d_flush();
8119 }
8120 module_exit(vmx_exit);
8121
8122 static int __init vmx_init(void)
8123 {
8124         int r, cpu;
8125
8126 #if IS_ENABLED(CONFIG_HYPERV)
8127         /*
8128          * Enlightened VMCS usage should be recommended and the host needs
8129          * to support eVMCS v1 or above. We can also disable eVMCS support
8130          * with module parameter.
8131          */
8132         if (enlightened_vmcs &&
8133             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8134             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8135             KVM_EVMCS_VERSION) {
8136                 int cpu;
8137
8138                 /* Check that we have assist pages on all online CPUs */
8139                 for_each_online_cpu(cpu) {
8140                         if (!hv_get_vp_assist_page(cpu)) {
8141                                 enlightened_vmcs = false;
8142                                 break;
8143                         }
8144                 }
8145
8146                 if (enlightened_vmcs) {
8147                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8148                         static_branch_enable(&enable_evmcs);
8149                 }
8150
8151                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8152                         vmx_x86_ops.enable_direct_tlbflush
8153                                 = hv_enable_direct_tlbflush;
8154
8155         } else {
8156                 enlightened_vmcs = false;
8157         }
8158 #endif
8159
8160         r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
8161                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8162         if (r)
8163                 return r;
8164
8165         /*
8166          * Must be called after kvm_init() so enable_ept is properly set
8167          * up. Hand the parameter mitigation value in which was stored in
8168          * the pre module init parser. If no parameter was given, it will
8169          * contain 'auto' which will be turned into the default 'cond'
8170          * mitigation mode.
8171          */
8172         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8173         if (r) {
8174                 vmx_exit();
8175                 return r;
8176         }
8177
8178         for_each_possible_cpu(cpu) {
8179                 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8180                 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
8181                 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8182         }
8183
8184 #ifdef CONFIG_KEXEC_CORE
8185         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8186                            crash_vmclear_local_loaded_vmcss);
8187 #endif
8188         vmx_check_vmcs12_offsets();
8189
8190         return 0;
8191 }
8192 module_init(vmx_init);