arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/frame.h>
  17 #include <linux/highmem.h>
  18 #include <linux/hrtimer.h>
  19 #include <linux/kernel.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/mm.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30
  31 #include <asm/apic.h>
  32 #include <asm/asm.h>
  33 #include <asm/cpu.h>
  34 #include <asm/cpu_device_id.h>
  35 #include <asm/debugreg.h>
  36 #include <asm/desc.h>
  37 #include <asm/fpu/internal.h>
  38 #include <asm/io.h>
  39 #include <asm/irq_remapping.h>
  40 #include <asm/kexec.h>
  41 #include <asm/perf_event.h>
  42 #include <asm/mce.h>
  43 #include <asm/mmu_context.h>
  44 #include <asm/mshyperv.h>
  45 #include <asm/mwait.h>
  46 #include <asm/spec-ctrl.h>
  47 #include <asm/virtext.h>
  48 #include <asm/vmx.h>
  49
  50 #include "capabilities.h"
  51 #include "cpuid.h"
  52 #include "evmcs.h"
  53 #include "irq.h"
  54 #include "kvm_cache_regs.h"
  55 #include "lapic.h"
  56 #include "mmu.h"
  57 #include "nested.h"
  58 #include "ops.h"
  59 #include "pmu.h"
  60 #include "trace.h"
  61 #include "vmcs.h"
  62 #include "vmcs12.h"
  63 #include "vmx.h"
  64 #include "x86.h"
  65
  66 MODULE_AUTHOR("Qumranet");
  67 MODULE_LICENSE("GPL");
  68
  69 #ifdef MODULE
  70 static const struct x86_cpu_id vmx_cpu_id[] = {
  71         X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
  72         {}
  73 };
  74 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  75 #endif
  76
  77 bool __read_mostly enable_vpid = 1;
  78 module_param_named(vpid, enable_vpid, bool, 0444);
  79
  80 static bool __read_mostly enable_vnmi = 1;
  81 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  82
  83 bool __read_mostly flexpriority_enabled = 1;
  84 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  85
  86 bool __read_mostly enable_ept = 1;
  87 module_param_named(ept, enable_ept, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_unrestricted_guest = 1;
  90 module_param_named(unrestricted_guest,
  91                         enable_unrestricted_guest, bool, S_IRUGO);
  92
  93 bool __read_mostly enable_ept_ad_bits = 1;
  94 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  95
  96 static bool __read_mostly emulate_invalid_guest_state = true;
  97 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  98
  99 static bool __read_mostly fasteoi = 1;
 100 module_param(fasteoi, bool, S_IRUGO);
 101
 102 bool __read_mostly enable_apicv = 1;
 103 module_param(enable_apicv, bool, S_IRUGO);
 104
 105 /*
 106  * If nested=1, nested virtualization is supported, i.e., guests may use
 107  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 108  * use VMX instructions.
 109  */
 110 static bool __read_mostly nested = 1;
 111 module_param(nested, bool, S_IRUGO);
 112
 113 bool __read_mostly enable_pml = 1;
 114 module_param_named(pml, enable_pml, bool, S_IRUGO);
 115
 116 static bool __read_mostly dump_invalid_vmcs = 0;
 117 module_param(dump_invalid_vmcs, bool, 0644);
 118
 119 #define MSR_BITMAP_MODE_X2APIC          1
 120 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 121
 122 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 123
 124 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 125 static int __read_mostly cpu_preemption_timer_multi;
 126 static bool __read_mostly enable_preemption_timer = 1;
 127 #ifdef CONFIG_X86_64
 128 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 129 #endif
 130
 131 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 132 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 133 #define KVM_VM_CR0_ALWAYS_ON                            \
 134         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 135          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 136 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 137         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 138          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 139
 140 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 141 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 142 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 143
 144 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 145
 146 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 147         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 148         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 149         RTIT_STATUS_BYTECNT))
 150
 151 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
 152         (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
 153
 154 /*
 155  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 156  * ple_gap:    upper bound on the amount of time between two successive
 157  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 158  *             According to test, this time is usually smaller than 128 cycles.
 159  * ple_window: upper bound on the amount of time a guest is allowed to execute
 160  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 161  *             less than 2^12 cycles
 162  * Time is measured based on a counter that runs at the same rate as the TSC,
 163  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 164  */
 165 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 166 module_param(ple_gap, uint, 0444);
 167
 168 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 169 module_param(ple_window, uint, 0444);
 170
 171 /* Default doubles per-vcpu window every exit. */
 172 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 173 module_param(ple_window_grow, uint, 0444);
 174
 175 /* Default resets per-vcpu window every exit to ple_window. */
 176 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 177 module_param(ple_window_shrink, uint, 0444);
 178
 179 /* Default is to compute the maximum so we can never overflow. */
 180 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 181 module_param(ple_window_max, uint, 0444);
 182
 183 /* Default is SYSTEM mode, 1 for host-guest mode */
 184 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 185 module_param(pt_mode, int, S_IRUGO);
 186
 187 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 188 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 189 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 190
 191 /* Storage for pre module init parameter parsing */
 192 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 193
 194 static const struct {
 195         const char *option;
 196         bool for_parse;
 197 } vmentry_l1d_param[] = {
 198         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 199         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 200         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 201         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 202         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 203         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 204 };
 205
 206 #define L1D_CACHE_ORDER 4
 207 static void *vmx_l1d_flush_pages;
 208
 209 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 210 {
 211         struct page *page;
 212         unsigned int i;
 213
 214         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 215                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 216                 return 0;
 217         }
 218
 219         if (!enable_ept) {
 220                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 221                 return 0;
 222         }
 223
 224         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 225                 u64 msr;
 226
 227                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 228                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 229                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 230                         return 0;
 231                 }
 232         }
 233
 234         /* If set to auto use the default l1tf mitigation method */
 235         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 236                 switch (l1tf_mitigation) {
 237                 case L1TF_MITIGATION_OFF:
 238                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 239                         break;
 240                 case L1TF_MITIGATION_FLUSH_NOWARN:
 241                 case L1TF_MITIGATION_FLUSH:
 242                 case L1TF_MITIGATION_FLUSH_NOSMT:
 243                         l1tf = VMENTER_L1D_FLUSH_COND;
 244                         break;
 245                 case L1TF_MITIGATION_FULL:
 246                 case L1TF_MITIGATION_FULL_FORCE:
 247                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 248                         break;
 249                 }
 250         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 251                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 252         }
 253
 254         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 255             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 256                 /*
 257                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 258                  * lifetime and so should not be charged to a memcg.
 259                  */
 260                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 261                 if (!page)
 262                         return -ENOMEM;
 263                 vmx_l1d_flush_pages = page_address(page);
 264
 265                 /*
 266                  * Initialize each page with a different pattern in
 267                  * order to protect against KSM in the nested
 268                  * virtualization case.
 269                  */
 270                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 271                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 272                                PAGE_SIZE);
 273                 }
 274         }
 275
 276         l1tf_vmx_mitigation = l1tf;
 277
 278         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 279                 static_branch_enable(&vmx_l1d_should_flush);
 280         else
 281                 static_branch_disable(&vmx_l1d_should_flush);
 282
 283         if (l1tf == VMENTER_L1D_FLUSH_COND)
 284                 static_branch_enable(&vmx_l1d_flush_cond);
 285         else
 286                 static_branch_disable(&vmx_l1d_flush_cond);
 287         return 0;
 288 }
 289
 290 static int vmentry_l1d_flush_parse(const char *s)
 291 {
 292         unsigned int i;
 293
 294         if (s) {
 295                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 296                         if (vmentry_l1d_param[i].for_parse &&
 297                             sysfs_streq(s, vmentry_l1d_param[i].option))
 298                                 return i;
 299                 }
 300         }
 301         return -EINVAL;
 302 }
 303
 304 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 305 {
 306         int l1tf, ret;
 307
 308         l1tf = vmentry_l1d_flush_parse(s);
 309         if (l1tf < 0)
 310                 return l1tf;
 311
 312         if (!boot_cpu_has(X86_BUG_L1TF))
 313                 return 0;
 314
 315         /*
 316          * Has vmx_init() run already? If not then this is the pre init
 317          * parameter parsing. In that case just store the value and let
 318          * vmx_init() do the proper setup after enable_ept has been
 319          * established.
 320          */
 321         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 322                 vmentry_l1d_flush_param = l1tf;
 323                 return 0;
 324         }
 325
 326         mutex_lock(&vmx_l1d_flush_mutex);
 327         ret = vmx_setup_l1d_flush(l1tf);
 328         mutex_unlock(&vmx_l1d_flush_mutex);
 329         return ret;
 330 }
 331
 332 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 333 {
 334         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 335                 return sprintf(s, "???\n");
 336
 337         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 338 }
 339
 340 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 341         .set = vmentry_l1d_flush_set,
 342         .get = vmentry_l1d_flush_get,
 343 };
 344 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 345
 346 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 347 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 348 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 349                                                           u32 msr, int type);
 350
 351 void vmx_vmexit(void);
 352
 353 #define vmx_insn_failed(fmt...)         \
 354 do {                                    \
 355         WARN_ONCE(1, fmt);              \
 356         pr_warn_ratelimited(fmt);       \
 357 } while (0)
 358
 359 asmlinkage void vmread_error(unsigned long field, bool fault)
 360 {
 361         if (fault)
 362                 kvm_spurious_fault();
 363         else
 364                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 365 }
 366
 367 noinline void vmwrite_error(unsigned long field, unsigned long value)
 368 {
 369         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 370                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 371 }
 372
 373 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 374 {
 375         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 376 }
 377
 378 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 379 {
 380         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 381 }
 382
 383 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 384 {
 385         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 386                         ext, vpid, gva);
 387 }
 388
 389 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 390 {
 391         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 392                         ext, eptp, gpa);
 393 }
 394
 395 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 396 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 397 /*
 398  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 399  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 400  */
 401 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 402
 403 /*
 404  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 405  * can find which vCPU should be waken up.
 406  */
 407 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 408 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 409
 410 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 411 static DEFINE_SPINLOCK(vmx_vpid_lock);
 412
 413 struct vmcs_config vmcs_config;
 414 struct vmx_capability vmx_capability;
 415
 416 #define VMX_SEGMENT_FIELD(seg)                                  \
 417         [VCPU_SREG_##seg] = {                                   \
 418                 .selector = GUEST_##seg##_SELECTOR,             \
 419                 .base = GUEST_##seg##_BASE,                     \
 420                 .limit = GUEST_##seg##_LIMIT,                   \
 421                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 422         }
 423
 424 static const struct kvm_vmx_segment_field {
 425         unsigned selector;
 426         unsigned base;
 427         unsigned limit;
 428         unsigned ar_bytes;
 429 } kvm_vmx_segment_fields[] = {
 430         VMX_SEGMENT_FIELD(CS),
 431         VMX_SEGMENT_FIELD(DS),
 432         VMX_SEGMENT_FIELD(ES),
 433         VMX_SEGMENT_FIELD(FS),
 434         VMX_SEGMENT_FIELD(GS),
 435         VMX_SEGMENT_FIELD(SS),
 436         VMX_SEGMENT_FIELD(TR),
 437         VMX_SEGMENT_FIELD(LDTR),
 438 };
 439
 440 static unsigned long host_idt_base;
 441
 442 /*
 443  * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
 444  * will emulate SYSCALL in legacy mode if the vendor string in guest
 445  * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
 446  * support this emulation, IA32_STAR must always be included in
 447  * vmx_msr_index[], even in i386 builds.
 448  */
 449 const u32 vmx_msr_index[] = {
 450 #ifdef CONFIG_X86_64
 451         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 452 #endif
 453         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 454         MSR_IA32_TSX_CTRL,
 455 };
 456
 457 #if IS_ENABLED(CONFIG_HYPERV)
 458 static bool __read_mostly enlightened_vmcs = true;
 459 module_param(enlightened_vmcs, bool, 0444);
 460
 461 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
 462 static void check_ept_pointer_match(struct kvm *kvm)
 463 {
 464         struct kvm_vcpu *vcpu;
 465         u64 tmp_eptp = INVALID_PAGE;
 466         int i;
 467
 468         kvm_for_each_vcpu(i, vcpu, kvm) {
 469                 if (!VALID_PAGE(tmp_eptp)) {
 470                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
 471                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
 472                         to_kvm_vmx(kvm)->ept_pointers_match
 473                                 = EPT_POINTERS_MISMATCH;
 474                         return;
 475                 }
 476         }
 477
 478         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
 479 }
 480
 481 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
 482                 void *data)
 483 {
 484         struct kvm_tlb_range *range = data;
 485
 486         return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
 487                         range->pages);
 488 }
 489
 490 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
 491                 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
 492 {
 493         u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
 494
 495         /*
 496          * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
 497          * of the base of EPT PML4 table, strip off EPT configuration
 498          * information.
 499          */
 500         if (range)
 501                 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
 502                                 kvm_fill_hv_flush_list_func, (void *)range);
 503         else
 504                 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
 505 }
 506
 507 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
 508                 struct kvm_tlb_range *range)
 509 {
 510         struct kvm_vcpu *vcpu;
 511         int ret = 0, i;
 512
 513         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 514
 515         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
 516                 check_ept_pointer_match(kvm);
 517
 518         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
 519                 kvm_for_each_vcpu(i, vcpu, kvm) {
 520                         /* If ept_pointer is invalid pointer, bypass flush request. */
 521                         if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
 522                                 ret |= __hv_remote_flush_tlb_with_range(
 523                                         kvm, vcpu, range);
 524                 }
 525         } else {
 526                 ret = __hv_remote_flush_tlb_with_range(kvm,
 527                                 kvm_get_vcpu(kvm, 0), range);
 528         }
 529
 530         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 531         return ret;
 532 }
 533 static int hv_remote_flush_tlb(struct kvm *kvm)
 534 {
 535         return hv_remote_flush_tlb_with_range(kvm, NULL);
 536 }
 537
 538 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 539 {
 540         struct hv_enlightened_vmcs *evmcs;
 541         struct hv_partition_assist_pg **p_hv_pa_pg =
 542                         &vcpu->kvm->arch.hyperv.hv_pa_pg;
 543         /*
 544          * Synthetic VM-Exit is not enabled in current code and so All
 545          * evmcs in singe VM shares same assist page.
 546          */
 547         if (!*p_hv_pa_pg)
 548                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
 549
 550         if (!*p_hv_pa_pg)
 551                 return -ENOMEM;
 552
 553         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 554
 555         evmcs->partition_assist_page =
 556                 __pa(*p_hv_pa_pg);
 557         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 558         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 559
 560         return 0;
 561 }
 562
 563 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 564
 565 /*
 566  * Comment's format: document - errata name - stepping - processor name.
 567  * Refer from
 568  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 569  */
 570 static u32 vmx_preemption_cpu_tfms[] = {
 571 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 572 0x000206E6,
 573 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 574 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 575 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 576 0x00020652,
 577 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 578 0x00020655,
 579 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 580 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 581 /*
 582  * 320767.pdf - AAP86  - B1 -
 583  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 584  */
 585 0x000106E5,
 586 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 587 0x000106A0,
 588 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 589 0x000106A1,
 590 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 591 0x000106A4,
 592  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 593  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 594  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 595 0x000106A5,
 596  /* Xeon E3-1220 V2 */
 597 0x000306A8,
 598 };
 599
 600 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 601 {
 602         u32 eax = cpuid_eax(0x00000001), i;
 603
 604         /* Clear the reserved bits */
 605         eax &= ~(0x3U << 14 | 0xfU << 28);
 606         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 607                 if (eax == vmx_preemption_cpu_tfms[i])
 608                         return true;
 609
 610         return false;
 611 }
 612
 613 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 614 {
 615         return flexpriority_enabled && lapic_in_kernel(vcpu);
 616 }
 617
 618 static inline bool report_flexpriority(void)
 619 {
 620         return flexpriority_enabled;
 621 }
 622
 623 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 624 {
 625         int i;
 626
 627         for (i = 0; i < vmx->nmsrs; ++i)
 628                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 629                         return i;
 630         return -1;
 631 }
 632
 633 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 634 {
 635         int i;
 636
 637         i = __find_msr_index(vmx, msr);
 638         if (i >= 0)
 639                 return &vmx->guest_msrs[i];
 640         return NULL;
 641 }
 642
 643 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
 644 {
 645         int ret = 0;
 646
 647         u64 old_msr_data = msr->data;
 648         msr->data = data;
 649         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
 650                 preempt_disable();
 651                 ret = kvm_set_shared_msr(msr->index, msr->data,
 652                                          msr->mask);
 653                 preempt_enable();
 654                 if (ret)
 655                         msr->data = old_msr_data;
 656         }
 657         return ret;
 658 }
 659
 660 #ifdef CONFIG_KEXEC_CORE
 661 static void crash_vmclear_local_loaded_vmcss(void)
 662 {
 663         int cpu = raw_smp_processor_id();
 664         struct loaded_vmcs *v;
 665
 666         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 667                             loaded_vmcss_on_cpu_link)
 668                 vmcs_clear(v->vmcs);
 669 }
 670 #endif /* CONFIG_KEXEC_CORE */
 671
 672 static void __loaded_vmcs_clear(void *arg)
 673 {
 674         struct loaded_vmcs *loaded_vmcs = arg;
 675         int cpu = raw_smp_processor_id();
 676
 677         if (loaded_vmcs->cpu != cpu)
 678                 return; /* vcpu migration can race with cpu offline */
 679         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 680                 per_cpu(current_vmcs, cpu) = NULL;
 681
 682         vmcs_clear(loaded_vmcs->vmcs);
 683         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 684                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 685
 686         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 687
 688         /*
 689          * Ensure all writes to loaded_vmcs, including deleting it from its
 690          * current percpu list, complete before setting loaded_vmcs->vcpu to
 691          * -1, otherwise a different cpu can see vcpu == -1 first and add
 692          * loaded_vmcs to its percpu list before it's deleted from this cpu's
 693          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
 694          */
 695         smp_wmb();
 696
 697         loaded_vmcs->cpu = -1;
 698         loaded_vmcs->launched = 0;
 699 }
 700
 701 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 702 {
 703         int cpu = loaded_vmcs->cpu;
 704
 705         if (cpu != -1)
 706                 smp_call_function_single(cpu,
 707                          __loaded_vmcs_clear, loaded_vmcs, 1);
 708 }
 709
 710 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 711                                        unsigned field)
 712 {
 713         bool ret;
 714         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 715
 716         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
 717                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
 718                 vmx->segment_cache.bitmask = 0;
 719         }
 720         ret = vmx->segment_cache.bitmask & mask;
 721         vmx->segment_cache.bitmask |= mask;
 722         return ret;
 723 }
 724
 725 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 726 {
 727         u16 *p = &vmx->segment_cache.seg[seg].selector;
 728
 729         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 730                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 731         return *p;
 732 }
 733
 734 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 735 {
 736         ulong *p = &vmx->segment_cache.seg[seg].base;
 737
 738         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 739                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 740         return *p;
 741 }
 742
 743 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 744 {
 745         u32 *p = &vmx->segment_cache.seg[seg].limit;
 746
 747         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 748                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 749         return *p;
 750 }
 751
 752 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 753 {
 754         u32 *p = &vmx->segment_cache.seg[seg].ar;
 755
 756         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 757                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 758         return *p;
 759 }
 760
 761 void update_exception_bitmap(struct kvm_vcpu *vcpu)
 762 {
 763         u32 eb;
 764
 765         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 766              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 767         /*
 768          * Guest access to VMware backdoor ports could legitimately
 769          * trigger #GP because of TSS I/O permission bitmap.
 770          * We intercept those #GP and allow access to them anyway
 771          * as VMware does.
 772          */
 773         if (enable_vmware_backdoor)
 774                 eb |= (1u << GP_VECTOR);
 775         if ((vcpu->guest_debug &
 776              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 777             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 778                 eb |= 1u << BP_VECTOR;
 779         if (to_vmx(vcpu)->rmode.vm86_active)
 780                 eb = ~0;
 781         if (enable_ept)
 782                 eb &= ~(1u << PF_VECTOR);
 783
 784         /* When we are running a nested L2 guest and L1 specified for it a
 785          * certain exception bitmap, we must trap the same exceptions and pass
 786          * them to L1. When running L2, we will only handle the exceptions
 787          * specified above if L1 did not want them.
 788          */
 789         if (is_guest_mode(vcpu))
 790                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 791
 792         vmcs_write32(EXCEPTION_BITMAP, eb);
 793 }
 794
 795 /*
 796  * Check if MSR is intercepted for currently loaded MSR bitmap.
 797  */
 798 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 799 {
 800         unsigned long *msr_bitmap;
 801         int f = sizeof(unsigned long);
 802
 803         if (!cpu_has_vmx_msr_bitmap())
 804                 return true;
 805
 806         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 807
 808         if (msr <= 0x1fff) {
 809                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 810         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 811                 msr &= 0x1fff;
 812                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 813         }
 814
 815         return true;
 816 }
 817
 818 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 819                 unsigned long entry, unsigned long exit)
 820 {
 821         vm_entry_controls_clearbit(vmx, entry);
 822         vm_exit_controls_clearbit(vmx, exit);
 823 }
 824
 825 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
 826 {
 827         unsigned int i;
 828
 829         for (i = 0; i < m->nr; ++i) {
 830                 if (m->val[i].index == msr)
 831                         return i;
 832         }
 833         return -ENOENT;
 834 }
 835
 836 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 837 {
 838         int i;
 839         struct msr_autoload *m = &vmx->msr_autoload;
 840
 841         switch (msr) {
 842         case MSR_EFER:
 843                 if (cpu_has_load_ia32_efer()) {
 844                         clear_atomic_switch_msr_special(vmx,
 845                                         VM_ENTRY_LOAD_IA32_EFER,
 846                                         VM_EXIT_LOAD_IA32_EFER);
 847                         return;
 848                 }
 849                 break;
 850         case MSR_CORE_PERF_GLOBAL_CTRL:
 851                 if (cpu_has_load_perf_global_ctrl()) {
 852                         clear_atomic_switch_msr_special(vmx,
 853                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 854                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 855                         return;
 856                 }
 857                 break;
 858         }
 859         i = vmx_find_msr_index(&m->guest, msr);
 860         if (i < 0)
 861                 goto skip_guest;
 862         --m->guest.nr;
 863         m->guest.val[i] = m->guest.val[m->guest.nr];
 864         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 865
 866 skip_guest:
 867         i = vmx_find_msr_index(&m->host, msr);
 868         if (i < 0)
 869                 return;
 870
 871         --m->host.nr;
 872         m->host.val[i] = m->host.val[m->host.nr];
 873         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 874 }
 875
 876 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 877                 unsigned long entry, unsigned long exit,
 878                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 879                 u64 guest_val, u64 host_val)
 880 {
 881         vmcs_write64(guest_val_vmcs, guest_val);
 882         if (host_val_vmcs != HOST_IA32_EFER)
 883                 vmcs_write64(host_val_vmcs, host_val);
 884         vm_entry_controls_setbit(vmx, entry);
 885         vm_exit_controls_setbit(vmx, exit);
 886 }
 887
 888 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 889                                   u64 guest_val, u64 host_val, bool entry_only)
 890 {
 891         int i, j = 0;
 892         struct msr_autoload *m = &vmx->msr_autoload;
 893
 894         switch (msr) {
 895         case MSR_EFER:
 896                 if (cpu_has_load_ia32_efer()) {
 897                         add_atomic_switch_msr_special(vmx,
 898                                         VM_ENTRY_LOAD_IA32_EFER,
 899                                         VM_EXIT_LOAD_IA32_EFER,
 900                                         GUEST_IA32_EFER,
 901                                         HOST_IA32_EFER,
 902                                         guest_val, host_val);
 903                         return;
 904                 }
 905                 break;
 906         case MSR_CORE_PERF_GLOBAL_CTRL:
 907                 if (cpu_has_load_perf_global_ctrl()) {
 908                         add_atomic_switch_msr_special(vmx,
 909                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 910                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 911                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 912                                         HOST_IA32_PERF_GLOBAL_CTRL,
 913                                         guest_val, host_val);
 914                         return;
 915                 }
 916                 break;
 917         case MSR_IA32_PEBS_ENABLE:
 918                 /* PEBS needs a quiescent period after being disabled (to write
 919                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 920                  * provide that period, so a CPU could write host's record into
 921                  * guest's memory.
 922                  */
 923                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 924         }
 925
 926         i = vmx_find_msr_index(&m->guest, msr);
 927         if (!entry_only)
 928                 j = vmx_find_msr_index(&m->host, msr);
 929
 930         if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
 931                 (j < 0 &&  m->host.nr == NR_LOADSTORE_MSRS)) {
 932                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 933                                 "Can't add msr %x\n", msr);
 934                 return;
 935         }
 936         if (i < 0) {
 937                 i = m->guest.nr++;
 938                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 939         }
 940         m->guest.val[i].index = msr;
 941         m->guest.val[i].value = guest_val;
 942
 943         if (entry_only)
 944                 return;
 945
 946         if (j < 0) {
 947                 j = m->host.nr++;
 948                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 949         }
 950         m->host.val[j].index = msr;
 951         m->host.val[j].value = host_val;
 952 }
 953
 954 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 955 {
 956         u64 guest_efer = vmx->vcpu.arch.efer;
 957         u64 ignore_bits = 0;
 958
 959         /* Shadow paging assumes NX to be available.  */
 960         if (!enable_ept)
 961                 guest_efer |= EFER_NX;
 962
 963         /*
 964          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 965          */
 966         ignore_bits |= EFER_SCE;
 967 #ifdef CONFIG_X86_64
 968         ignore_bits |= EFER_LMA | EFER_LME;
 969         /* SCE is meaningful only in long mode on Intel */
 970         if (guest_efer & EFER_LMA)
 971                 ignore_bits &= ~(u64)EFER_SCE;
 972 #endif
 973
 974         /*
 975          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 976          * On CPUs that support "load IA32_EFER", always switch EFER
 977          * atomically, since it's faster than switching it manually.
 978          */
 979         if (cpu_has_load_ia32_efer() ||
 980             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 981                 if (!(guest_efer & EFER_LMA))
 982                         guest_efer &= ~EFER_LME;
 983                 if (guest_efer != host_efer)
 984                         add_atomic_switch_msr(vmx, MSR_EFER,
 985                                               guest_efer, host_efer, false);
 986                 else
 987                         clear_atomic_switch_msr(vmx, MSR_EFER);
 988                 return false;
 989         } else {
 990                 clear_atomic_switch_msr(vmx, MSR_EFER);
 991
 992                 guest_efer &= ~ignore_bits;
 993                 guest_efer |= host_efer & ignore_bits;
 994
 995                 vmx->guest_msrs[efer_offset].data = guest_efer;
 996                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 997
 998                 return true;
 999         }
1000 }
1001
1002 #ifdef CONFIG_X86_32
1003 /*
1004  * On 32-bit kernels, VM exits still load the FS and GS bases from the
1005  * VMCS rather than the segment table.  KVM uses this helper to figure
1006  * out the current bases to poke them into the VMCS before entry.
1007  */
1008 static unsigned long segment_base(u16 selector)
1009 {
1010         struct desc_struct *table;
1011         unsigned long v;
1012
1013         if (!(selector & ~SEGMENT_RPL_MASK))
1014                 return 0;
1015
1016         table = get_current_gdt_ro();
1017
1018         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1019                 u16 ldt_selector = kvm_read_ldt();
1020
1021                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1022                         return 0;
1023
1024                 table = (struct desc_struct *)segment_base(ldt_selector);
1025         }
1026         v = get_desc_base(&table[selector >> 3]);
1027         return v;
1028 }
1029 #endif
1030
1031 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1032 {
1033         return vmx_pt_mode_is_host_guest() &&
1034                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1035 }
1036
1037 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1038 {
1039         u32 i;
1040
1041         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1042         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1043         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1044         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1045         for (i = 0; i < addr_range; i++) {
1046                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1047                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1048         }
1049 }
1050
1051 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1052 {
1053         u32 i;
1054
1055         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1056         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1057         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1058         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1059         for (i = 0; i < addr_range; i++) {
1060                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1061                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1062         }
1063 }
1064
1065 static void pt_guest_enter(struct vcpu_vmx *vmx)
1066 {
1067         if (vmx_pt_mode_is_system())
1068                 return;
1069
1070         /*
1071          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1072          * Save host state before VM entry.
1073          */
1074         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1075         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1076                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1077                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1078                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1079         }
1080 }
1081
1082 static void pt_guest_exit(struct vcpu_vmx *vmx)
1083 {
1084         if (vmx_pt_mode_is_system())
1085                 return;
1086
1087         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1088                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1089                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1090         }
1091
1092         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1093         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1094 }
1095
1096 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1097                         unsigned long fs_base, unsigned long gs_base)
1098 {
1099         if (unlikely(fs_sel != host->fs_sel)) {
1100                 if (!(fs_sel & 7))
1101                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1102                 else
1103                         vmcs_write16(HOST_FS_SELECTOR, 0);
1104                 host->fs_sel = fs_sel;
1105         }
1106         if (unlikely(gs_sel != host->gs_sel)) {
1107                 if (!(gs_sel & 7))
1108                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1109                 else
1110                         vmcs_write16(HOST_GS_SELECTOR, 0);
1111                 host->gs_sel = gs_sel;
1112         }
1113         if (unlikely(fs_base != host->fs_base)) {
1114                 vmcs_writel(HOST_FS_BASE, fs_base);
1115                 host->fs_base = fs_base;
1116         }
1117         if (unlikely(gs_base != host->gs_base)) {
1118                 vmcs_writel(HOST_GS_BASE, gs_base);
1119                 host->gs_base = gs_base;
1120         }
1121 }
1122
1123 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1124 {
1125         struct vcpu_vmx *vmx = to_vmx(vcpu);
1126         struct vmcs_host_state *host_state;
1127 #ifdef CONFIG_X86_64
1128         int cpu = raw_smp_processor_id();
1129 #endif
1130         unsigned long fs_base, gs_base;
1131         u16 fs_sel, gs_sel;
1132         int i;
1133
1134         vmx->req_immediate_exit = false;
1135
1136         /*
1137          * Note that guest MSRs to be saved/restored can also be changed
1138          * when guest state is loaded. This happens when guest transitions
1139          * to/from long-mode by setting MSR_EFER.LMA.
1140          */
1141         if (!vmx->guest_msrs_ready) {
1142                 vmx->guest_msrs_ready = true;
1143                 for (i = 0; i < vmx->save_nmsrs; ++i)
1144                         kvm_set_shared_msr(vmx->guest_msrs[i].index,
1145                                            vmx->guest_msrs[i].data,
1146                                            vmx->guest_msrs[i].mask);
1147
1148         }
1149
1150         if (vmx->nested.need_vmcs12_to_shadow_sync)
1151                 nested_sync_vmcs12_to_shadow(vcpu);
1152
1153         if (vmx->guest_state_loaded)
1154                 return;
1155
1156         host_state = &vmx->loaded_vmcs->host_state;
1157
1158         /*
1159          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1160          * allow segment selectors with cpl > 0 or ti == 1.
1161          */
1162         host_state->ldt_sel = kvm_read_ldt();
1163
1164 #ifdef CONFIG_X86_64
1165         savesegment(ds, host_state->ds_sel);
1166         savesegment(es, host_state->es_sel);
1167
1168         gs_base = cpu_kernelmode_gs_base(cpu);
1169         if (likely(is_64bit_mm(current->mm))) {
1170                 save_fsgs_for_kvm();
1171                 fs_sel = current->thread.fsindex;
1172                 gs_sel = current->thread.gsindex;
1173                 fs_base = current->thread.fsbase;
1174                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1175         } else {
1176                 savesegment(fs, fs_sel);
1177                 savesegment(gs, gs_sel);
1178                 fs_base = read_msr(MSR_FS_BASE);
1179                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1180         }
1181
1182         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1183 #else
1184         savesegment(fs, fs_sel);
1185         savesegment(gs, gs_sel);
1186         fs_base = segment_base(fs_sel);
1187         gs_base = segment_base(gs_sel);
1188 #endif
1189
1190         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1191         vmx->guest_state_loaded = true;
1192 }
1193
1194 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1195 {
1196         struct vmcs_host_state *host_state;
1197
1198         if (!vmx->guest_state_loaded)
1199                 return;
1200
1201         host_state = &vmx->loaded_vmcs->host_state;
1202
1203         ++vmx->vcpu.stat.host_state_reload;
1204
1205 #ifdef CONFIG_X86_64
1206         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1207 #endif
1208         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1209                 kvm_load_ldt(host_state->ldt_sel);
1210 #ifdef CONFIG_X86_64
1211                 load_gs_index(host_state->gs_sel);
1212 #else
1213                 loadsegment(gs, host_state->gs_sel);
1214 #endif
1215         }
1216         if (host_state->fs_sel & 7)
1217                 loadsegment(fs, host_state->fs_sel);
1218 #ifdef CONFIG_X86_64
1219         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1220                 loadsegment(ds, host_state->ds_sel);
1221                 loadsegment(es, host_state->es_sel);
1222         }
1223 #endif
1224         invalidate_tss_limit();
1225 #ifdef CONFIG_X86_64
1226         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1227 #endif
1228         load_fixmap_gdt(raw_smp_processor_id());
1229         vmx->guest_state_loaded = false;
1230         vmx->guest_msrs_ready = false;
1231 }
1232
1233 #ifdef CONFIG_X86_64
1234 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1235 {
1236         preempt_disable();
1237         if (vmx->guest_state_loaded)
1238                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1239         preempt_enable();
1240         return vmx->msr_guest_kernel_gs_base;
1241 }
1242
1243 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1244 {
1245         preempt_disable();
1246         if (vmx->guest_state_loaded)
1247                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1248         preempt_enable();
1249         vmx->msr_guest_kernel_gs_base = data;
1250 }
1251 #endif
1252
1253 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1254 {
1255         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1256         struct pi_desc old, new;
1257         unsigned int dest;
1258
1259         /*
1260          * In case of hot-plug or hot-unplug, we may have to undo
1261          * vmx_vcpu_pi_put even if there is no assigned device.  And we
1262          * always keep PI.NDST up to date for simplicity: it makes the
1263          * code easier, and CPU migration is not a fast path.
1264          */
1265         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1266                 return;
1267
1268         /*
1269          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1270          * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1271          * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1272          * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1273          * correctly.
1274          */
1275         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1276                 pi_clear_sn(pi_desc);
1277                 goto after_clear_sn;
1278         }
1279
1280         /* The full case.  */
1281         do {
1282                 old.control = new.control = pi_desc->control;
1283
1284                 dest = cpu_physical_id(cpu);
1285
1286                 if (x2apic_enabled())
1287                         new.ndst = dest;
1288                 else
1289                         new.ndst = (dest << 8) & 0xFF00;
1290
1291                 new.sn = 0;
1292         } while (cmpxchg64(&pi_desc->control, old.control,
1293                            new.control) != old.control);
1294
1295 after_clear_sn:
1296
1297         /*
1298          * Clear SN before reading the bitmap.  The VT-d firmware
1299          * writes the bitmap and reads SN atomically (5.2.3 in the
1300          * spec), so it doesn't really have a memory barrier that
1301          * pairs with this, but we cannot do that and we need one.
1302          */
1303         smp_mb__after_atomic();
1304
1305         if (!pi_is_pir_empty(pi_desc))
1306                 pi_set_on(pi_desc);
1307 }
1308
1309 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1310 {
1311         struct vcpu_vmx *vmx = to_vmx(vcpu);
1312         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1313
1314         if (!already_loaded) {
1315                 loaded_vmcs_clear(vmx->loaded_vmcs);
1316                 local_irq_disable();
1317
1318                 /*
1319                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1320                  * this cpu's percpu list, otherwise it may not yet be deleted
1321                  * from its previous cpu's percpu list.  Pairs with the
1322                  * smb_wmb() in __loaded_vmcs_clear().
1323                  */
1324                 smp_rmb();
1325
1326                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1327                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1328                 local_irq_enable();
1329         }
1330
1331         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1332                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1333                 vmcs_load(vmx->loaded_vmcs->vmcs);
1334                 indirect_branch_prediction_barrier();
1335         }
1336
1337         if (!already_loaded) {
1338                 void *gdt = get_current_gdt_ro();
1339                 unsigned long sysenter_esp;
1340
1341                 /*
1342                  * Flush all EPTP/VPID contexts, the new pCPU may have stale
1343                  * TLB entries from its previous association with the vCPU.
1344                  */
1345                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1346
1347                 /*
1348                  * Linux uses per-cpu TSS and GDT, so set these when switching
1349                  * processors.  See 22.2.4.
1350                  */
1351                 vmcs_writel(HOST_TR_BASE,
1352                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1353                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1354
1355                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1356                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1357
1358                 vmx->loaded_vmcs->cpu = cpu;
1359         }
1360
1361         /* Setup TSC multiplier */
1362         if (kvm_has_tsc_control &&
1363             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1364                 decache_tsc_multiplier(vmx);
1365 }
1366
1367 /*
1368  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1369  * vcpu mutex is already taken.
1370  */
1371 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1372 {
1373         struct vcpu_vmx *vmx = to_vmx(vcpu);
1374
1375         vmx_vcpu_load_vmcs(vcpu, cpu);
1376
1377         vmx_vcpu_pi_load(vcpu, cpu);
1378
1379         vmx->host_pkru = read_pkru();
1380         vmx->host_debugctlmsr = get_debugctlmsr();
1381 }
1382
1383 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1384 {
1385         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1386
1387         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1388                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
1389                 !kvm_vcpu_apicv_active(vcpu))
1390                 return;
1391
1392         /* Set SN when the vCPU is preempted */
1393         if (vcpu->preempted)
1394                 pi_set_sn(pi_desc);
1395 }
1396
1397 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1398 {
1399         vmx_vcpu_pi_put(vcpu);
1400
1401         vmx_prepare_switch_to_host(to_vmx(vcpu));
1402 }
1403
1404 static bool emulation_required(struct kvm_vcpu *vcpu)
1405 {
1406         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1407 }
1408
1409 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1410 {
1411         struct vcpu_vmx *vmx = to_vmx(vcpu);
1412         unsigned long rflags, save_rflags;
1413
1414         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1415                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1416                 rflags = vmcs_readl(GUEST_RFLAGS);
1417                 if (vmx->rmode.vm86_active) {
1418                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1419                         save_rflags = vmx->rmode.save_rflags;
1420                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1421                 }
1422                 vmx->rflags = rflags;
1423         }
1424         return vmx->rflags;
1425 }
1426
1427 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1428 {
1429         struct vcpu_vmx *vmx = to_vmx(vcpu);
1430         unsigned long old_rflags;
1431
1432         if (enable_unrestricted_guest) {
1433                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1434                 vmx->rflags = rflags;
1435                 vmcs_writel(GUEST_RFLAGS, rflags);
1436                 return;
1437         }
1438
1439         old_rflags = vmx_get_rflags(vcpu);
1440         vmx->rflags = rflags;
1441         if (vmx->rmode.vm86_active) {
1442                 vmx->rmode.save_rflags = rflags;
1443                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1444         }
1445         vmcs_writel(GUEST_RFLAGS, rflags);
1446
1447         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1448                 vmx->emulation_required = emulation_required(vcpu);
1449 }
1450
1451 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1452 {
1453         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1454         int ret = 0;
1455
1456         if (interruptibility & GUEST_INTR_STATE_STI)
1457                 ret |= KVM_X86_SHADOW_INT_STI;
1458         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1459                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1460
1461         return ret;
1462 }
1463
1464 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1465 {
1466         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1467         u32 interruptibility = interruptibility_old;
1468
1469         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1470
1471         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1472                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1473         else if (mask & KVM_X86_SHADOW_INT_STI)
1474                 interruptibility |= GUEST_INTR_STATE_STI;
1475
1476         if ((interruptibility != interruptibility_old))
1477                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1478 }
1479
1480 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1481 {
1482         struct vcpu_vmx *vmx = to_vmx(vcpu);
1483         unsigned long value;
1484
1485         /*
1486          * Any MSR write that attempts to change bits marked reserved will
1487          * case a #GP fault.
1488          */
1489         if (data & vmx->pt_desc.ctl_bitmask)
1490                 return 1;
1491
1492         /*
1493          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1494          * result in a #GP unless the same write also clears TraceEn.
1495          */
1496         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1497                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1498                 return 1;
1499
1500         /*
1501          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1502          * and FabricEn would cause #GP, if
1503          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1504          */
1505         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1506                 !(data & RTIT_CTL_FABRIC_EN) &&
1507                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1508                                         PT_CAP_single_range_output))
1509                 return 1;
1510
1511         /*
1512          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1513          * utilize encodings marked reserved will casue a #GP fault.
1514          */
1515         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1516         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1517                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1518                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1519                 return 1;
1520         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1521                                                 PT_CAP_cycle_thresholds);
1522         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1523                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1524                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1525                 return 1;
1526         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1527         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1528                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1529                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1530                 return 1;
1531
1532         /*
1533          * If ADDRx_CFG is reserved or the encodings is >2 will
1534          * cause a #GP fault.
1535          */
1536         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1537         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1538                 return 1;
1539         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1540         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1541                 return 1;
1542         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1543         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1544                 return 1;
1545         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1546         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1547                 return 1;
1548
1549         return 0;
1550 }
1551
1552 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1553 {
1554         unsigned long rip;
1555
1556         /*
1557          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1558          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1559          * set when EPT misconfig occurs.  In practice, real hardware updates
1560          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1561          * (namely Hyper-V) don't set it due to it being undefined behavior,
1562          * i.e. we end up advancing IP with some random value.
1563          */
1564         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1565             to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1566                 rip = kvm_rip_read(vcpu);
1567                 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1568                 kvm_rip_write(vcpu, rip);
1569         } else {
1570                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1571                         return 0;
1572         }
1573
1574         /* skipping an emulated instruction also counts */
1575         vmx_set_interrupt_shadow(vcpu, 0);
1576
1577         return 1;
1578 }
1579
1580
1581 /*
1582  * Recognizes a pending MTF VM-exit and records the nested state for later
1583  * delivery.
1584  */
1585 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1586 {
1587         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1588         struct vcpu_vmx *vmx = to_vmx(vcpu);
1589
1590         if (!is_guest_mode(vcpu))
1591                 return;
1592
1593         /*
1594          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1595          * T-bit traps. As instruction emulation is completed (i.e. at the
1596          * instruction boundary), any #DB exception pending delivery must be a
1597          * debug-trap. Record the pending MTF state to be delivered in
1598          * vmx_check_nested_events().
1599          */
1600         if (nested_cpu_has_mtf(vmcs12) &&
1601             (!vcpu->arch.exception.pending ||
1602              vcpu->arch.exception.nr == DB_VECTOR))
1603                 vmx->nested.mtf_pending = true;
1604         else
1605                 vmx->nested.mtf_pending = false;
1606 }
1607
1608 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1609 {
1610         vmx_update_emulated_instruction(vcpu);
1611         return skip_emulated_instruction(vcpu);
1612 }
1613
1614 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1615 {
1616         /*
1617          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1618          * explicitly skip the instruction because if the HLT state is set,
1619          * then the instruction is already executing and RIP has already been
1620          * advanced.
1621          */
1622         if (kvm_hlt_in_guest(vcpu->kvm) &&
1623                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1624                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1625 }
1626
1627 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1628 {
1629         struct vcpu_vmx *vmx = to_vmx(vcpu);
1630         unsigned nr = vcpu->arch.exception.nr;
1631         bool has_error_code = vcpu->arch.exception.has_error_code;
1632         u32 error_code = vcpu->arch.exception.error_code;
1633         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1634
1635         kvm_deliver_exception_payload(vcpu);
1636
1637         if (has_error_code) {
1638                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1639                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1640         }
1641
1642         if (vmx->rmode.vm86_active) {
1643                 int inc_eip = 0;
1644                 if (kvm_exception_is_soft(nr))
1645                         inc_eip = vcpu->arch.event_exit_inst_len;
1646                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1647                 return;
1648         }
1649
1650         WARN_ON_ONCE(vmx->emulation_required);
1651
1652         if (kvm_exception_is_soft(nr)) {
1653                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1654                              vmx->vcpu.arch.event_exit_inst_len);
1655                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1656         } else
1657                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1658
1659         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1660
1661         vmx_clear_hlt(vcpu);
1662 }
1663
1664 /*
1665  * Swap MSR entry in host/guest MSR entry array.
1666  */
1667 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1668 {
1669         struct shared_msr_entry tmp;
1670
1671         tmp = vmx->guest_msrs[to];
1672         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1673         vmx->guest_msrs[from] = tmp;
1674 }
1675
1676 /*
1677  * Set up the vmcs to automatically save and restore system
1678  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1679  * mode, as fiddling with msrs is very expensive.
1680  */
1681 static void setup_msrs(struct vcpu_vmx *vmx)
1682 {
1683         int save_nmsrs, index;
1684
1685         save_nmsrs = 0;
1686 #ifdef CONFIG_X86_64
1687         /*
1688          * The SYSCALL MSRs are only needed on long mode guests, and only
1689          * when EFER.SCE is set.
1690          */
1691         if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1692                 index = __find_msr_index(vmx, MSR_STAR);
1693                 if (index >= 0)
1694                         move_msr_up(vmx, index, save_nmsrs++);
1695                 index = __find_msr_index(vmx, MSR_LSTAR);
1696                 if (index >= 0)
1697                         move_msr_up(vmx, index, save_nmsrs++);
1698                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1699                 if (index >= 0)
1700                         move_msr_up(vmx, index, save_nmsrs++);
1701         }
1702 #endif
1703         index = __find_msr_index(vmx, MSR_EFER);
1704         if (index >= 0 && update_transition_efer(vmx, index))
1705                 move_msr_up(vmx, index, save_nmsrs++);
1706         index = __find_msr_index(vmx, MSR_TSC_AUX);
1707         if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1708                 move_msr_up(vmx, index, save_nmsrs++);
1709         index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1710         if (index >= 0)
1711                 move_msr_up(vmx, index, save_nmsrs++);
1712
1713         vmx->save_nmsrs = save_nmsrs;
1714         vmx->guest_msrs_ready = false;
1715
1716         if (cpu_has_vmx_msr_bitmap())
1717                 vmx_update_msr_bitmap(&vmx->vcpu);
1718 }
1719
1720 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1721 {
1722         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1723
1724         if (is_guest_mode(vcpu) &&
1725             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1726                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1727
1728         return vcpu->arch.tsc_offset;
1729 }
1730
1731 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1732 {
1733         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1734         u64 g_tsc_offset = 0;
1735
1736         /*
1737          * We're here if L1 chose not to trap WRMSR to TSC. According
1738          * to the spec, this should set L1's TSC; The offset that L1
1739          * set for L2 remains unchanged, and still needs to be added
1740          * to the newly set TSC to get L2's TSC.
1741          */
1742         if (is_guest_mode(vcpu) &&
1743             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1744                 g_tsc_offset = vmcs12->tsc_offset;
1745
1746         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1747                                    vcpu->arch.tsc_offset - g_tsc_offset,
1748                                    offset);
1749         vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1750         return offset + g_tsc_offset;
1751 }
1752
1753 /*
1754  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1755  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1756  * all guests if the "nested" module option is off, and can also be disabled
1757  * for a single guest by disabling its VMX cpuid bit.
1758  */
1759 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1760 {
1761         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1762 }
1763
1764 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1765                                                  uint64_t val)
1766 {
1767         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1768
1769         return !(val & ~valid_bits);
1770 }
1771
1772 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1773 {
1774         switch (msr->index) {
1775         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1776                 if (!nested)
1777                         return 1;
1778                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1779         default:
1780                 return 1;
1781         }
1782 }
1783
1784 /*
1785  * Reads an msr value (of 'msr_index') into 'pdata'.
1786  * Returns 0 on success, non-0 otherwise.
1787  * Assumes vcpu_load() was already called.
1788  */
1789 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1790 {
1791         struct vcpu_vmx *vmx = to_vmx(vcpu);
1792         struct shared_msr_entry *msr;
1793         u32 index;
1794
1795         switch (msr_info->index) {
1796 #ifdef CONFIG_X86_64
1797         case MSR_FS_BASE:
1798                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1799                 break;
1800         case MSR_GS_BASE:
1801                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1802                 break;
1803         case MSR_KERNEL_GS_BASE:
1804                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1805                 break;
1806 #endif
1807         case MSR_EFER:
1808                 return kvm_get_msr_common(vcpu, msr_info);
1809         case MSR_IA32_TSX_CTRL:
1810                 if (!msr_info->host_initiated &&
1811                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1812                         return 1;
1813                 goto find_shared_msr;
1814         case MSR_IA32_UMWAIT_CONTROL:
1815                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1816                         return 1;
1817
1818                 msr_info->data = vmx->msr_ia32_umwait_control;
1819                 break;
1820         case MSR_IA32_SPEC_CTRL:
1821                 if (!msr_info->host_initiated &&
1822                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1823                         return 1;
1824
1825                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1826                 break;
1827         case MSR_IA32_SYSENTER_CS:
1828                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1829                 break;
1830         case MSR_IA32_SYSENTER_EIP:
1831                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1832                 break;
1833         case MSR_IA32_SYSENTER_ESP:
1834                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1835                 break;
1836         case MSR_IA32_BNDCFGS:
1837                 if (!kvm_mpx_supported() ||
1838                     (!msr_info->host_initiated &&
1839                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1840                         return 1;
1841                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1842                 break;
1843         case MSR_IA32_MCG_EXT_CTL:
1844                 if (!msr_info->host_initiated &&
1845                     !(vmx->msr_ia32_feature_control &
1846                       FEAT_CTL_LMCE_ENABLED))
1847                         return 1;
1848                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1849                 break;
1850         case MSR_IA32_FEAT_CTL:
1851                 msr_info->data = vmx->msr_ia32_feature_control;
1852                 break;
1853         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1854                 if (!nested_vmx_allowed(vcpu))
1855                         return 1;
1856                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1857                                     &msr_info->data))
1858                         return 1;
1859                 /*
1860                  * Enlightened VMCS v1 doesn't have certain fields, but buggy
1861                  * Hyper-V versions are still trying to use corresponding
1862                  * features when they are exposed. Filter out the essential
1863                  * minimum.
1864                  */
1865                 if (!msr_info->host_initiated &&
1866                     vmx->nested.enlightened_vmcs_enabled)
1867                         nested_evmcs_filter_control_msr(msr_info->index,
1868                                                         &msr_info->data);
1869                 break;
1870         case MSR_IA32_RTIT_CTL:
1871                 if (!vmx_pt_mode_is_host_guest())
1872                         return 1;
1873                 msr_info->data = vmx->pt_desc.guest.ctl;
1874                 break;
1875         case MSR_IA32_RTIT_STATUS:
1876                 if (!vmx_pt_mode_is_host_guest())
1877                         return 1;
1878                 msr_info->data = vmx->pt_desc.guest.status;
1879                 break;
1880         case MSR_IA32_RTIT_CR3_MATCH:
1881                 if (!vmx_pt_mode_is_host_guest() ||
1882                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1883                                                 PT_CAP_cr3_filtering))
1884                         return 1;
1885                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1886                 break;
1887         case MSR_IA32_RTIT_OUTPUT_BASE:
1888                 if (!vmx_pt_mode_is_host_guest() ||
1889                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1890                                         PT_CAP_topa_output) &&
1891                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1892                                         PT_CAP_single_range_output)))
1893                         return 1;
1894                 msr_info->data = vmx->pt_desc.guest.output_base;
1895                 break;
1896         case MSR_IA32_RTIT_OUTPUT_MASK:
1897                 if (!vmx_pt_mode_is_host_guest() ||
1898                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1899                                         PT_CAP_topa_output) &&
1900                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1901                                         PT_CAP_single_range_output)))
1902                         return 1;
1903                 msr_info->data = vmx->pt_desc.guest.output_mask;
1904                 break;
1905         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1906                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1907                 if (!vmx_pt_mode_is_host_guest() ||
1908                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1909                                         PT_CAP_num_address_ranges)))
1910                         return 1;
1911                 if (index % 2)
1912                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1913                 else
1914                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1915                 break;
1916         case MSR_TSC_AUX:
1917                 if (!msr_info->host_initiated &&
1918                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1919                         return 1;
1920                 goto find_shared_msr;
1921         default:
1922         find_shared_msr:
1923                 msr = find_msr_entry(vmx, msr_info->index);
1924                 if (msr) {
1925                         msr_info->data = msr->data;
1926                         break;
1927                 }
1928                 return kvm_get_msr_common(vcpu, msr_info);
1929         }
1930
1931         return 0;
1932 }
1933
1934 /*
1935  * Writes msr value into the appropriate "register".
1936  * Returns 0 on success, non-0 otherwise.
1937  * Assumes vcpu_load() was already called.
1938  */
1939 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1940 {
1941         struct vcpu_vmx *vmx = to_vmx(vcpu);
1942         struct shared_msr_entry *msr;
1943         int ret = 0;
1944         u32 msr_index = msr_info->index;
1945         u64 data = msr_info->data;
1946         u32 index;
1947
1948         switch (msr_index) {
1949         case MSR_EFER:
1950                 ret = kvm_set_msr_common(vcpu, msr_info);
1951                 break;
1952 #ifdef CONFIG_X86_64
1953         case MSR_FS_BASE:
1954                 vmx_segment_cache_clear(vmx);
1955                 vmcs_writel(GUEST_FS_BASE, data);
1956                 break;
1957         case MSR_GS_BASE:
1958                 vmx_segment_cache_clear(vmx);
1959                 vmcs_writel(GUEST_GS_BASE, data);
1960                 break;
1961         case MSR_KERNEL_GS_BASE:
1962                 vmx_write_guest_kernel_gs_base(vmx, data);
1963                 break;
1964 #endif
1965         case MSR_IA32_SYSENTER_CS:
1966                 if (is_guest_mode(vcpu))
1967                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1968                 vmcs_write32(GUEST_SYSENTER_CS, data);
1969                 break;
1970         case MSR_IA32_SYSENTER_EIP:
1971                 if (is_guest_mode(vcpu))
1972                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1973                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1974                 break;
1975         case MSR_IA32_SYSENTER_ESP:
1976                 if (is_guest_mode(vcpu))
1977                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1978                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1979                 break;
1980         case MSR_IA32_DEBUGCTLMSR:
1981                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1982                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
1983                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1984
1985                 ret = kvm_set_msr_common(vcpu, msr_info);
1986                 break;
1987
1988         case MSR_IA32_BNDCFGS:
1989                 if (!kvm_mpx_supported() ||
1990                     (!msr_info->host_initiated &&
1991                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1992                         return 1;
1993                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1994                     (data & MSR_IA32_BNDCFGS_RSVD))
1995                         return 1;
1996                 vmcs_write64(GUEST_BNDCFGS, data);
1997                 break;
1998         case MSR_IA32_UMWAIT_CONTROL:
1999                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2000                         return 1;
2001
2002                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2003                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2004                         return 1;
2005
2006                 vmx->msr_ia32_umwait_control = data;
2007                 break;
2008         case MSR_IA32_SPEC_CTRL:
2009                 if (!msr_info->host_initiated &&
2010                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2011                         return 1;
2012
2013                 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
2014                         return 1;
2015
2016                 vmx->spec_ctrl = data;
2017                 if (!data)
2018                         break;
2019
2020                 /*
2021                  * For non-nested:
2022                  * When it's written (to non-zero) for the first time, pass
2023                  * it through.
2024                  *
2025                  * For nested:
2026                  * The handling of the MSR bitmap for L2 guests is done in
2027                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2028                  * vmcs02.msr_bitmap here since it gets completely overwritten
2029                  * in the merging. We update the vmcs01 here for L1 as well
2030                  * since it will end up touching the MSR anyway now.
2031                  */
2032                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2033                                               MSR_IA32_SPEC_CTRL,
2034                                               MSR_TYPE_RW);
2035                 break;
2036         case MSR_IA32_TSX_CTRL:
2037                 if (!msr_info->host_initiated &&
2038                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2039                         return 1;
2040                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2041                         return 1;
2042                 goto find_shared_msr;
2043         case MSR_IA32_PRED_CMD:
2044                 if (!msr_info->host_initiated &&
2045                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2046                         return 1;
2047
2048                 if (data & ~PRED_CMD_IBPB)
2049                         return 1;
2050                 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2051                         return 1;
2052                 if (!data)
2053                         break;
2054
2055                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2056
2057                 /*
2058                  * For non-nested:
2059                  * When it's written (to non-zero) for the first time, pass
2060                  * it through.
2061                  *
2062                  * For nested:
2063                  * The handling of the MSR bitmap for L2 guests is done in
2064                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2065                  * vmcs02.msr_bitmap here since it gets completely overwritten
2066                  * in the merging.
2067                  */
2068                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2069                                               MSR_TYPE_W);
2070                 break;
2071         case MSR_IA32_CR_PAT:
2072                 if (!kvm_pat_valid(data))
2073                         return 1;
2074
2075                 if (is_guest_mode(vcpu) &&
2076                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2077                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2078
2079                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2080                         vmcs_write64(GUEST_IA32_PAT, data);
2081                         vcpu->arch.pat = data;
2082                         break;
2083                 }
2084                 ret = kvm_set_msr_common(vcpu, msr_info);
2085                 break;
2086         case MSR_IA32_TSC_ADJUST:
2087                 ret = kvm_set_msr_common(vcpu, msr_info);
2088                 break;
2089         case MSR_IA32_MCG_EXT_CTL:
2090                 if ((!msr_info->host_initiated &&
2091                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2092                        FEAT_CTL_LMCE_ENABLED)) ||
2093                     (data & ~MCG_EXT_CTL_LMCE_EN))
2094                         return 1;
2095                 vcpu->arch.mcg_ext_ctl = data;
2096                 break;
2097         case MSR_IA32_FEAT_CTL:
2098                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2099                     (to_vmx(vcpu)->msr_ia32_feature_control &
2100                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2101                         return 1;
2102                 vmx->msr_ia32_feature_control = data;
2103                 if (msr_info->host_initiated && data == 0)
2104                         vmx_leave_nested(vcpu);
2105                 break;
2106         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2107                 if (!msr_info->host_initiated)
2108                         return 1; /* they are read-only */
2109                 if (!nested_vmx_allowed(vcpu))
2110                         return 1;
2111                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2112         case MSR_IA32_RTIT_CTL:
2113                 if (!vmx_pt_mode_is_host_guest() ||
2114                         vmx_rtit_ctl_check(vcpu, data) ||
2115                         vmx->nested.vmxon)
2116                         return 1;
2117                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2118                 vmx->pt_desc.guest.ctl = data;
2119                 pt_update_intercept_for_msr(vmx);
2120                 break;
2121         case MSR_IA32_RTIT_STATUS:
2122                 if (!pt_can_write_msr(vmx))
2123                         return 1;
2124                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2125                         return 1;
2126                 vmx->pt_desc.guest.status = data;
2127                 break;
2128         case MSR_IA32_RTIT_CR3_MATCH:
2129                 if (!pt_can_write_msr(vmx))
2130                         return 1;
2131                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2132                                            PT_CAP_cr3_filtering))
2133                         return 1;
2134                 vmx->pt_desc.guest.cr3_match = data;
2135                 break;
2136         case MSR_IA32_RTIT_OUTPUT_BASE:
2137                 if (!pt_can_write_msr(vmx))
2138                         return 1;
2139                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2140                                            PT_CAP_topa_output) &&
2141                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2142                                            PT_CAP_single_range_output))
2143                         return 1;
2144                 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
2145                         return 1;
2146                 vmx->pt_desc.guest.output_base = data;
2147                 break;
2148         case MSR_IA32_RTIT_OUTPUT_MASK:
2149                 if (!pt_can_write_msr(vmx))
2150                         return 1;
2151                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2152                                            PT_CAP_topa_output) &&
2153                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2154                                            PT_CAP_single_range_output))
2155                         return 1;
2156                 vmx->pt_desc.guest.output_mask = data;
2157                 break;
2158         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2159                 if (!pt_can_write_msr(vmx))
2160                         return 1;
2161                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2162                 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2163                                                        PT_CAP_num_address_ranges))
2164                         return 1;
2165                 if (is_noncanonical_address(data, vcpu))
2166                         return 1;
2167                 if (index % 2)
2168                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2169                 else
2170                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2171                 break;
2172         case MSR_TSC_AUX:
2173                 if (!msr_info->host_initiated &&
2174                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2175                         return 1;
2176                 /* Check reserved bit, higher 32 bits should be zero */
2177                 if ((data >> 32) != 0)
2178                         return 1;
2179                 goto find_shared_msr;
2180
2181         default:
2182         find_shared_msr:
2183                 msr = find_msr_entry(vmx, msr_index);
2184                 if (msr)
2185                         ret = vmx_set_guest_msr(vmx, msr, data);
2186                 else
2187                         ret = kvm_set_msr_common(vcpu, msr_info);
2188         }
2189
2190         return ret;
2191 }
2192
2193 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2194 {
2195         kvm_register_mark_available(vcpu, reg);
2196
2197         switch (reg) {
2198         case VCPU_REGS_RSP:
2199                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2200                 break;
2201         case VCPU_REGS_RIP:
2202                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2203                 break;
2204         case VCPU_EXREG_PDPTR:
2205                 if (enable_ept)
2206                         ept_save_pdptrs(vcpu);
2207                 break;
2208         case VCPU_EXREG_CR3:
2209                 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2210                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2211                 break;
2212         default:
2213                 WARN_ON_ONCE(1);
2214                 break;
2215         }
2216 }
2217
2218 static __init int cpu_has_kvm_support(void)
2219 {
2220         return cpu_has_vmx();
2221 }
2222
2223 static __init int vmx_disabled_by_bios(void)
2224 {
2225         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2226                !boot_cpu_has(X86_FEATURE_VMX);
2227 }
2228
2229 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2230 {
2231         u64 msr;
2232
2233         cr4_set_bits(X86_CR4_VMXE);
2234         intel_pt_handle_vmx(1);
2235
2236         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2237                           _ASM_EXTABLE(1b, %l[fault])
2238                           : : [vmxon_pointer] "m"(vmxon_pointer)
2239                           : : fault);
2240         return 0;
2241
2242 fault:
2243         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2244                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2245         intel_pt_handle_vmx(0);
2246         cr4_clear_bits(X86_CR4_VMXE);
2247
2248         return -EFAULT;
2249 }
2250
2251 static int hardware_enable(void)
2252 {
2253         int cpu = raw_smp_processor_id();
2254         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2255         int r;
2256
2257         if (cr4_read_shadow() & X86_CR4_VMXE)
2258                 return -EBUSY;
2259
2260         /*
2261          * This can happen if we hot-added a CPU but failed to allocate
2262          * VP assist page for it.
2263          */
2264         if (static_branch_unlikely(&enable_evmcs) &&
2265             !hv_get_vp_assist_page(cpu))
2266                 return -EFAULT;
2267
2268         r = kvm_cpu_vmxon(phys_addr);
2269         if (r)
2270                 return r;
2271
2272         if (enable_ept)
2273                 ept_sync_global();
2274
2275         return 0;
2276 }
2277
2278 static void vmclear_local_loaded_vmcss(void)
2279 {
2280         int cpu = raw_smp_processor_id();
2281         struct loaded_vmcs *v, *n;
2282
2283         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2284                                  loaded_vmcss_on_cpu_link)
2285                 __loaded_vmcs_clear(v);
2286 }
2287
2288
2289 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2290  * tricks.
2291  */
2292 static void kvm_cpu_vmxoff(void)
2293 {
2294         asm volatile (__ex("vmxoff"));
2295
2296         intel_pt_handle_vmx(0);
2297         cr4_clear_bits(X86_CR4_VMXE);
2298 }
2299
2300 static void hardware_disable(void)
2301 {
2302         vmclear_local_loaded_vmcss();
2303         kvm_cpu_vmxoff();
2304 }
2305
2306 /*
2307  * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2308  * directly instead of going through cpu_has(), to ensure KVM is trapping
2309  * ENCLS whenever it's supported in hardware.  It does not matter whether
2310  * the host OS supports or has enabled SGX.
2311  */
2312 static bool cpu_has_sgx(void)
2313 {
2314         return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2315 }
2316
2317 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2318                                       u32 msr, u32 *result)
2319 {
2320         u32 vmx_msr_low, vmx_msr_high;
2321         u32 ctl = ctl_min | ctl_opt;
2322
2323         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2324
2325         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2326         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2327
2328         /* Ensure minimum (required) set of control bits are supported. */
2329         if (ctl_min & ~ctl)
2330                 return -EIO;
2331
2332         *result = ctl;
2333         return 0;
2334 }
2335
2336 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2337                                     struct vmx_capability *vmx_cap)
2338 {
2339         u32 vmx_msr_low, vmx_msr_high;
2340         u32 min, opt, min2, opt2;
2341         u32 _pin_based_exec_control = 0;
2342         u32 _cpu_based_exec_control = 0;
2343         u32 _cpu_based_2nd_exec_control = 0;
2344         u32 _vmexit_control = 0;
2345         u32 _vmentry_control = 0;
2346
2347         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2348         min = CPU_BASED_HLT_EXITING |
2349 #ifdef CONFIG_X86_64
2350               CPU_BASED_CR8_LOAD_EXITING |
2351               CPU_BASED_CR8_STORE_EXITING |
2352 #endif
2353               CPU_BASED_CR3_LOAD_EXITING |
2354               CPU_BASED_CR3_STORE_EXITING |
2355               CPU_BASED_UNCOND_IO_EXITING |
2356               CPU_BASED_MOV_DR_EXITING |
2357               CPU_BASED_USE_TSC_OFFSETTING |
2358               CPU_BASED_MWAIT_EXITING |
2359               CPU_BASED_MONITOR_EXITING |
2360               CPU_BASED_INVLPG_EXITING |
2361               CPU_BASED_RDPMC_EXITING;
2362
2363         opt = CPU_BASED_TPR_SHADOW |
2364               CPU_BASED_USE_MSR_BITMAPS |
2365               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2366         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2367                                 &_cpu_based_exec_control) < 0)
2368                 return -EIO;
2369 #ifdef CONFIG_X86_64
2370         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2371                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2372                                            ~CPU_BASED_CR8_STORE_EXITING;
2373 #endif
2374         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2375                 min2 = 0;
2376                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2377                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2378                         SECONDARY_EXEC_WBINVD_EXITING |
2379                         SECONDARY_EXEC_ENABLE_VPID |
2380                         SECONDARY_EXEC_ENABLE_EPT |
2381                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2382                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2383                         SECONDARY_EXEC_DESC |
2384                         SECONDARY_EXEC_RDTSCP |
2385                         SECONDARY_EXEC_ENABLE_INVPCID |
2386                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2387                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2388                         SECONDARY_EXEC_SHADOW_VMCS |
2389                         SECONDARY_EXEC_XSAVES |
2390                         SECONDARY_EXEC_RDSEED_EXITING |
2391                         SECONDARY_EXEC_RDRAND_EXITING |
2392                         SECONDARY_EXEC_ENABLE_PML |
2393                         SECONDARY_EXEC_TSC_SCALING |
2394                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2395                         SECONDARY_EXEC_PT_USE_GPA |
2396                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2397                         SECONDARY_EXEC_ENABLE_VMFUNC;
2398                 if (cpu_has_sgx())
2399                         opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2400                 if (adjust_vmx_controls(min2, opt2,
2401                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2402                                         &_cpu_based_2nd_exec_control) < 0)
2403                         return -EIO;
2404         }
2405 #ifndef CONFIG_X86_64
2406         if (!(_cpu_based_2nd_exec_control &
2407                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2408                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2409 #endif
2410
2411         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2412                 _cpu_based_2nd_exec_control &= ~(
2413                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2414                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2415                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2416
2417         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2418                 &vmx_cap->ept, &vmx_cap->vpid);
2419
2420         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2421                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2422                    enabled */
2423                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2424                                              CPU_BASED_CR3_STORE_EXITING |
2425                                              CPU_BASED_INVLPG_EXITING);
2426         } else if (vmx_cap->ept) {
2427                 vmx_cap->ept = 0;
2428                 pr_warn_once("EPT CAP should not exist if not support "
2429                                 "1-setting enable EPT VM-execution control\n");
2430         }
2431         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2432                 vmx_cap->vpid) {
2433                 vmx_cap->vpid = 0;
2434                 pr_warn_once("VPID CAP should not exist if not support "
2435                                 "1-setting enable VPID VM-execution control\n");
2436         }
2437
2438         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2439 #ifdef CONFIG_X86_64
2440         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2441 #endif
2442         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2443               VM_EXIT_LOAD_IA32_PAT |
2444               VM_EXIT_LOAD_IA32_EFER |
2445               VM_EXIT_CLEAR_BNDCFGS |
2446               VM_EXIT_PT_CONCEAL_PIP |
2447               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2448         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2449                                 &_vmexit_control) < 0)
2450                 return -EIO;
2451
2452         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2453         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2454                  PIN_BASED_VMX_PREEMPTION_TIMER;
2455         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2456                                 &_pin_based_exec_control) < 0)
2457                 return -EIO;
2458
2459         if (cpu_has_broken_vmx_preemption_timer())
2460                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2461         if (!(_cpu_based_2nd_exec_control &
2462                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2463                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2464
2465         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2466         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2467               VM_ENTRY_LOAD_IA32_PAT |
2468               VM_ENTRY_LOAD_IA32_EFER |
2469               VM_ENTRY_LOAD_BNDCFGS |
2470               VM_ENTRY_PT_CONCEAL_PIP |
2471               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2472         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2473                                 &_vmentry_control) < 0)
2474                 return -EIO;
2475
2476         /*
2477          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2478          * can't be used due to an errata where VM Exit may incorrectly clear
2479          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2480          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2481          */
2482         if (boot_cpu_data.x86 == 0x6) {
2483                 switch (boot_cpu_data.x86_model) {
2484                 case 26: /* AAK155 */
2485                 case 30: /* AAP115 */
2486                 case 37: /* AAT100 */
2487                 case 44: /* BC86,AAY89,BD102 */
2488                 case 46: /* BA97 */
2489                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2490                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2491                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2492                                         "does not work properly. Using workaround\n");
2493                         break;
2494                 default:
2495                         break;
2496                 }
2497         }
2498
2499
2500         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2501
2502         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2503         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2504                 return -EIO;
2505
2506 #ifdef CONFIG_X86_64
2507         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2508         if (vmx_msr_high & (1u<<16))
2509                 return -EIO;
2510 #endif
2511
2512         /* Require Write-Back (WB) memory type for VMCS accesses. */
2513         if (((vmx_msr_high >> 18) & 15) != 6)
2514                 return -EIO;
2515
2516         vmcs_conf->size = vmx_msr_high & 0x1fff;
2517         vmcs_conf->order = get_order(vmcs_conf->size);
2518         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2519
2520         vmcs_conf->revision_id = vmx_msr_low;
2521
2522         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2523         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2524         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2525         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2526         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2527
2528         if (static_branch_unlikely(&enable_evmcs))
2529                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2530
2531         return 0;
2532 }
2533
2534 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2535 {
2536         int node = cpu_to_node(cpu);
2537         struct page *pages;
2538         struct vmcs *vmcs;
2539
2540         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2541         if (!pages)
2542                 return NULL;
2543         vmcs = page_address(pages);
2544         memset(vmcs, 0, vmcs_config.size);
2545
2546         /* KVM supports Enlightened VMCS v1 only */
2547         if (static_branch_unlikely(&enable_evmcs))
2548                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2549         else
2550                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2551
2552         if (shadow)
2553                 vmcs->hdr.shadow_vmcs = 1;
2554         return vmcs;
2555 }
2556
2557 void free_vmcs(struct vmcs *vmcs)
2558 {
2559         free_pages((unsigned long)vmcs, vmcs_config.order);
2560 }
2561
2562 /*
2563  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2564  */
2565 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2566 {
2567         if (!loaded_vmcs->vmcs)
2568                 return;
2569         loaded_vmcs_clear(loaded_vmcs);
2570         free_vmcs(loaded_vmcs->vmcs);
2571         loaded_vmcs->vmcs = NULL;
2572         if (loaded_vmcs->msr_bitmap)
2573                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2574         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2575 }
2576
2577 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2578 {
2579         loaded_vmcs->vmcs = alloc_vmcs(false);
2580         if (!loaded_vmcs->vmcs)
2581                 return -ENOMEM;
2582
2583         vmcs_clear(loaded_vmcs->vmcs);
2584
2585         loaded_vmcs->shadow_vmcs = NULL;
2586         loaded_vmcs->hv_timer_soft_disabled = false;
2587         loaded_vmcs->cpu = -1;
2588         loaded_vmcs->launched = 0;
2589
2590         if (cpu_has_vmx_msr_bitmap()) {
2591                 loaded_vmcs->msr_bitmap = (unsigned long *)
2592                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2593                 if (!loaded_vmcs->msr_bitmap)
2594                         goto out_vmcs;
2595                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2596
2597                 if (IS_ENABLED(CONFIG_HYPERV) &&
2598                     static_branch_unlikely(&enable_evmcs) &&
2599                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2600                         struct hv_enlightened_vmcs *evmcs =
2601                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2602
2603                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2604                 }
2605         }
2606
2607         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2608         memset(&loaded_vmcs->controls_shadow, 0,
2609                 sizeof(struct vmcs_controls_shadow));
2610
2611         return 0;
2612
2613 out_vmcs:
2614         free_loaded_vmcs(loaded_vmcs);
2615         return -ENOMEM;
2616 }
2617
2618 static void free_kvm_area(void)
2619 {
2620         int cpu;
2621
2622         for_each_possible_cpu(cpu) {
2623                 free_vmcs(per_cpu(vmxarea, cpu));
2624                 per_cpu(vmxarea, cpu) = NULL;
2625         }
2626 }
2627
2628 static __init int alloc_kvm_area(void)
2629 {
2630         int cpu;
2631
2632         for_each_possible_cpu(cpu) {
2633                 struct vmcs *vmcs;
2634
2635                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2636                 if (!vmcs) {
2637                         free_kvm_area();
2638                         return -ENOMEM;
2639                 }
2640
2641                 /*
2642                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2643                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2644                  * revision_id reported by MSR_IA32_VMX_BASIC.
2645                  *
2646                  * However, even though not explicitly documented by
2647                  * TLFS, VMXArea passed as VMXON argument should
2648                  * still be marked with revision_id reported by
2649                  * physical CPU.
2650                  */
2651                 if (static_branch_unlikely(&enable_evmcs))
2652                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2653
2654                 per_cpu(vmxarea, cpu) = vmcs;
2655         }
2656         return 0;
2657 }
2658
2659 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2660                 struct kvm_segment *save)
2661 {
2662         if (!emulate_invalid_guest_state) {
2663                 /*
2664                  * CS and SS RPL should be equal during guest entry according
2665                  * to VMX spec, but in reality it is not always so. Since vcpu
2666                  * is in the middle of the transition from real mode to
2667                  * protected mode it is safe to assume that RPL 0 is a good
2668                  * default value.
2669                  */
2670                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2671                         save->selector &= ~SEGMENT_RPL_MASK;
2672                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2673                 save->s = 1;
2674         }
2675         vmx_set_segment(vcpu, save, seg);
2676 }
2677
2678 static void enter_pmode(struct kvm_vcpu *vcpu)
2679 {
2680         unsigned long flags;
2681         struct vcpu_vmx *vmx = to_vmx(vcpu);
2682
2683         /*
2684          * Update real mode segment cache. It may be not up-to-date if sement
2685          * register was written while vcpu was in a guest mode.
2686          */
2687         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2688         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2689         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2690         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2691         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2692         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2693
2694         vmx->rmode.vm86_active = 0;
2695
2696         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2697
2698         flags = vmcs_readl(GUEST_RFLAGS);
2699         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2700         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2701         vmcs_writel(GUEST_RFLAGS, flags);
2702
2703         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2704                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2705
2706         update_exception_bitmap(vcpu);
2707
2708         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2709         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2710         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2711         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2712         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2713         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2714 }
2715
2716 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2717 {
2718         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2719         struct kvm_segment var = *save;
2720
2721         var.dpl = 0x3;
2722         if (seg == VCPU_SREG_CS)
2723                 var.type = 0x3;
2724
2725         if (!emulate_invalid_guest_state) {
2726                 var.selector = var.base >> 4;
2727                 var.base = var.base & 0xffff0;
2728                 var.limit = 0xffff;
2729                 var.g = 0;
2730                 var.db = 0;
2731                 var.present = 1;
2732                 var.s = 1;
2733                 var.l = 0;
2734                 var.unusable = 0;
2735                 var.type = 0x3;
2736                 var.avl = 0;
2737                 if (save->base & 0xf)
2738                         printk_once(KERN_WARNING "kvm: segment base is not "
2739                                         "paragraph aligned when entering "
2740                                         "protected mode (seg=%d)", seg);
2741         }
2742
2743         vmcs_write16(sf->selector, var.selector);
2744         vmcs_writel(sf->base, var.base);
2745         vmcs_write32(sf->limit, var.limit);
2746         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2747 }
2748
2749 static void enter_rmode(struct kvm_vcpu *vcpu)
2750 {
2751         unsigned long flags;
2752         struct vcpu_vmx *vmx = to_vmx(vcpu);
2753         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2754
2755         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2756         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2757         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2758         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2759         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2760         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2761         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2762
2763         vmx->rmode.vm86_active = 1;
2764
2765         /*
2766          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2767          * vcpu. Warn the user that an update is overdue.
2768          */
2769         if (!kvm_vmx->tss_addr)
2770                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2771                              "called before entering vcpu\n");
2772
2773         vmx_segment_cache_clear(vmx);
2774
2775         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2776         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2777         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2778
2779         flags = vmcs_readl(GUEST_RFLAGS);
2780         vmx->rmode.save_rflags = flags;
2781
2782         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2783
2784         vmcs_writel(GUEST_RFLAGS, flags);
2785         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2786         update_exception_bitmap(vcpu);
2787
2788         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2789         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2790         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2791         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2792         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2793         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2794
2795         kvm_mmu_reset_context(vcpu);
2796 }
2797
2798 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2799 {
2800         struct vcpu_vmx *vmx = to_vmx(vcpu);
2801         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2802
2803         if (!msr)
2804                 return;
2805
2806         vcpu->arch.efer = efer;
2807         if (efer & EFER_LMA) {
2808                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2809                 msr->data = efer;
2810         } else {
2811                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2812
2813                 msr->data = efer & ~EFER_LME;
2814         }
2815         setup_msrs(vmx);
2816 }
2817
2818 #ifdef CONFIG_X86_64
2819
2820 static void enter_lmode(struct kvm_vcpu *vcpu)
2821 {
2822         u32 guest_tr_ar;
2823
2824         vmx_segment_cache_clear(to_vmx(vcpu));
2825
2826         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2827         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2828                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2829                                      __func__);
2830                 vmcs_write32(GUEST_TR_AR_BYTES,
2831                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2832                              | VMX_AR_TYPE_BUSY_64_TSS);
2833         }
2834         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2835 }
2836
2837 static void exit_lmode(struct kvm_vcpu *vcpu)
2838 {
2839         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2840         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2841 }
2842
2843 #endif
2844
2845 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2846 {
2847         struct vcpu_vmx *vmx = to_vmx(vcpu);
2848
2849         /*
2850          * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2851          * the CPU is not required to invalidate guest-physical mappings on
2852          * VM-Entry, even if VPID is disabled.  Guest-physical mappings are
2853          * associated with the root EPT structure and not any particular VPID
2854          * (INVVPID also isn't required to invalidate guest-physical mappings).
2855          */
2856         if (enable_ept) {
2857                 ept_sync_global();
2858         } else if (enable_vpid) {
2859                 if (cpu_has_vmx_invvpid_global()) {
2860                         vpid_sync_vcpu_global();
2861                 } else {
2862                         vpid_sync_vcpu_single(vmx->vpid);
2863                         vpid_sync_vcpu_single(vmx->nested.vpid02);
2864                 }
2865         }
2866 }
2867
2868 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2869 {
2870         u64 root_hpa = vcpu->arch.mmu->root_hpa;
2871
2872         /* No flush required if the current context is invalid. */
2873         if (!VALID_PAGE(root_hpa))
2874                 return;
2875
2876         if (enable_ept)
2877                 ept_sync_context(construct_eptp(vcpu, root_hpa));
2878         else if (!is_guest_mode(vcpu))
2879                 vpid_sync_context(to_vmx(vcpu)->vpid);
2880         else
2881                 vpid_sync_context(nested_get_vpid02(vcpu));
2882 }
2883
2884 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2885 {
2886         /*
2887          * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2888          * vmx_flush_tlb_guest() for an explanation of why this is ok.
2889          */
2890         vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2891 }
2892
2893 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2894 {
2895         /*
2896          * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2897          * or a vpid couldn't be allocated for this vCPU.  VM-Enter and VM-Exit
2898          * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2899          * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2900          * i.e. no explicit INVVPID is necessary.
2901          */
2902         vpid_sync_context(to_vmx(vcpu)->vpid);
2903 }
2904
2905 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2906 {
2907         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2908
2909         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2910         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2911 }
2912
2913 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2914 {
2915         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2916
2917         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2918         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2919 }
2920
2921 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2922 {
2923         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2924
2925         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2926                 return;
2927
2928         if (is_pae_paging(vcpu)) {
2929                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2930                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2931                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2932                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2933         }
2934 }
2935
2936 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2937 {
2938         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2939
2940         if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2941                 return;
2942
2943         mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2944         mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2945         mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2946         mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2947
2948         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2949 }
2950
2951 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2952                                         unsigned long cr0,
2953                                         struct kvm_vcpu *vcpu)
2954 {
2955         struct vcpu_vmx *vmx = to_vmx(vcpu);
2956
2957         if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2958                 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2959         if (!(cr0 & X86_CR0_PG)) {
2960                 /* From paging/starting to nonpaging */
2961                 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2962                                           CPU_BASED_CR3_STORE_EXITING);
2963                 vcpu->arch.cr0 = cr0;
2964                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2965         } else if (!is_paging(vcpu)) {
2966                 /* From nonpaging to paging */
2967                 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2968                                             CPU_BASED_CR3_STORE_EXITING);
2969                 vcpu->arch.cr0 = cr0;
2970                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2971         }
2972
2973         if (!(cr0 & X86_CR0_WP))
2974                 *hw_cr0 &= ~X86_CR0_WP;
2975 }
2976
2977 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2978 {
2979         struct vcpu_vmx *vmx = to_vmx(vcpu);
2980         unsigned long hw_cr0;
2981
2982         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2983         if (enable_unrestricted_guest)
2984                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2985         else {
2986                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2987
2988                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2989                         enter_pmode(vcpu);
2990
2991                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2992                         enter_rmode(vcpu);
2993         }
2994
2995 #ifdef CONFIG_X86_64
2996         if (vcpu->arch.efer & EFER_LME) {
2997                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2998                         enter_lmode(vcpu);
2999                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3000                         exit_lmode(vcpu);
3001         }
3002 #endif
3003
3004         if (enable_ept && !enable_unrestricted_guest)
3005                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3006
3007         vmcs_writel(CR0_READ_SHADOW, cr0);
3008         vmcs_writel(GUEST_CR0, hw_cr0);
3009         vcpu->arch.cr0 = cr0;
3010
3011         /* depends on vcpu->arch.cr0 to be set to a new value */
3012         vmx->emulation_required = emulation_required(vcpu);
3013 }
3014
3015 static int get_ept_level(struct kvm_vcpu *vcpu)
3016 {
3017         if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu)))
3018                 return vmx_eptp_page_walk_level(nested_ept_get_eptp(vcpu));
3019         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
3020                 return 5;
3021         return 4;
3022 }
3023
3024 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
3025 {
3026         u64 eptp = VMX_EPTP_MT_WB;
3027
3028         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3029
3030         if (enable_ept_ad_bits &&
3031             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3032                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3033         eptp |= (root_hpa & PAGE_MASK);
3034
3035         return eptp;
3036 }
3037
3038 void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long pgd)
3039 {
3040         struct kvm *kvm = vcpu->kvm;
3041         bool update_guest_cr3 = true;
3042         unsigned long guest_cr3;
3043         u64 eptp;
3044
3045         if (enable_ept) {
3046                 eptp = construct_eptp(vcpu, pgd);
3047                 vmcs_write64(EPT_POINTER, eptp);
3048
3049                 if (kvm_x86_ops.tlb_remote_flush) {
3050                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3051                         to_vmx(vcpu)->ept_pointer = eptp;
3052                         to_kvm_vmx(kvm)->ept_pointers_match
3053                                 = EPT_POINTERS_CHECK;
3054                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3055                 }
3056
3057                 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3058                 if (is_guest_mode(vcpu))
3059                         update_guest_cr3 = false;
3060                 else if (!enable_unrestricted_guest && !is_paging(vcpu))
3061                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3062                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3063                         guest_cr3 = vcpu->arch.cr3;
3064                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3065                         update_guest_cr3 = false;
3066                 ept_load_pdptrs(vcpu);
3067         } else {
3068                 guest_cr3 = pgd;
3069         }
3070
3071         if (update_guest_cr3)
3072                 vmcs_writel(GUEST_CR3, guest_cr3);
3073 }
3074
3075 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3076 {
3077         struct vcpu_vmx *vmx = to_vmx(vcpu);
3078         /*
3079          * Pass through host's Machine Check Enable value to hw_cr4, which
3080          * is in force while we are in guest mode.  Do not let guests control
3081          * this bit, even if host CR4.MCE == 0.
3082          */
3083         unsigned long hw_cr4;
3084
3085         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3086         if (enable_unrestricted_guest)
3087                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3088         else if (vmx->rmode.vm86_active)
3089                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3090         else
3091                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3092
3093         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3094                 if (cr4 & X86_CR4_UMIP) {
3095                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3096                         hw_cr4 &= ~X86_CR4_UMIP;
3097                 } else if (!is_guest_mode(vcpu) ||
3098                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3099                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3100                 }
3101         }
3102
3103         if (cr4 & X86_CR4_VMXE) {
3104                 /*
3105                  * To use VMXON (and later other VMX instructions), a guest
3106                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3107                  * So basically the check on whether to allow nested VMX
3108                  * is here.  We operate under the default treatment of SMM,
3109                  * so VMX cannot be enabled under SMM.
3110                  */
3111                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3112                         return 1;
3113         }
3114
3115         if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3116                 return 1;
3117
3118         vcpu->arch.cr4 = cr4;
3119
3120         if (!enable_unrestricted_guest) {
3121                 if (enable_ept) {
3122                         if (!is_paging(vcpu)) {
3123                                 hw_cr4 &= ~X86_CR4_PAE;
3124                                 hw_cr4 |= X86_CR4_PSE;
3125                         } else if (!(cr4 & X86_CR4_PAE)) {
3126                                 hw_cr4 &= ~X86_CR4_PAE;
3127                         }
3128                 }
3129
3130                 /*
3131                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3132                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3133                  * to be manually disabled when guest switches to non-paging
3134                  * mode.
3135                  *
3136                  * If !enable_unrestricted_guest, the CPU is always running
3137                  * with CR0.PG=1 and CR4 needs to be modified.
3138                  * If enable_unrestricted_guest, the CPU automatically
3139                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3140                  */
3141                 if (!is_paging(vcpu))
3142                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3143         }
3144
3145         vmcs_writel(CR4_READ_SHADOW, cr4);
3146         vmcs_writel(GUEST_CR4, hw_cr4);
3147         return 0;
3148 }
3149
3150 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3151 {
3152         struct vcpu_vmx *vmx = to_vmx(vcpu);
3153         u32 ar;
3154
3155         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3156                 *var = vmx->rmode.segs[seg];
3157                 if (seg == VCPU_SREG_TR
3158                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3159                         return;
3160                 var->base = vmx_read_guest_seg_base(vmx, seg);
3161                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3162                 return;
3163         }
3164         var->base = vmx_read_guest_seg_base(vmx, seg);
3165         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3166         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3167         ar = vmx_read_guest_seg_ar(vmx, seg);
3168         var->unusable = (ar >> 16) & 1;
3169         var->type = ar & 15;
3170         var->s = (ar >> 4) & 1;
3171         var->dpl = (ar >> 5) & 3;
3172         /*
3173          * Some userspaces do not preserve unusable property. Since usable
3174          * segment has to be present according to VMX spec we can use present
3175          * property to amend userspace bug by making unusable segment always
3176          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3177          * segment as unusable.
3178          */
3179         var->present = !var->unusable;
3180         var->avl = (ar >> 12) & 1;
3181         var->l = (ar >> 13) & 1;
3182         var->db = (ar >> 14) & 1;
3183         var->g = (ar >> 15) & 1;
3184 }
3185
3186 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3187 {
3188         struct kvm_segment s;
3189
3190         if (to_vmx(vcpu)->rmode.vm86_active) {
3191                 vmx_get_segment(vcpu, &s, seg);
3192                 return s.base;
3193         }
3194         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3195 }
3196
3197 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3198 {
3199         struct vcpu_vmx *vmx = to_vmx(vcpu);
3200
3201         if (unlikely(vmx->rmode.vm86_active))
3202                 return 0;
3203         else {
3204                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3205                 return VMX_AR_DPL(ar);
3206         }
3207 }
3208
3209 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3210 {
3211         u32 ar;
3212
3213         if (var->unusable || !var->present)
3214                 ar = 1 << 16;
3215         else {
3216                 ar = var->type & 15;
3217                 ar |= (var->s & 1) << 4;
3218                 ar |= (var->dpl & 3) << 5;
3219                 ar |= (var->present & 1) << 7;
3220                 ar |= (var->avl & 1) << 12;
3221                 ar |= (var->l & 1) << 13;
3222                 ar |= (var->db & 1) << 14;
3223                 ar |= (var->g & 1) << 15;
3224         }
3225
3226         return ar;
3227 }
3228
3229 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3230 {
3231         struct vcpu_vmx *vmx = to_vmx(vcpu);
3232         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3233
3234         vmx_segment_cache_clear(vmx);
3235
3236         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3237                 vmx->rmode.segs[seg] = *var;
3238                 if (seg == VCPU_SREG_TR)
3239                         vmcs_write16(sf->selector, var->selector);
3240                 else if (var->s)
3241                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3242                 goto out;
3243         }
3244
3245         vmcs_writel(sf->base, var->base);
3246         vmcs_write32(sf->limit, var->limit);
3247         vmcs_write16(sf->selector, var->selector);
3248
3249         /*
3250          *   Fix the "Accessed" bit in AR field of segment registers for older
3251          * qemu binaries.
3252          *   IA32 arch specifies that at the time of processor reset the
3253          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3254          * is setting it to 0 in the userland code. This causes invalid guest
3255          * state vmexit when "unrestricted guest" mode is turned on.
3256          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3257          * tree. Newer qemu binaries with that qemu fix would not need this
3258          * kvm hack.
3259          */
3260         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3261                 var->type |= 0x1; /* Accessed */
3262
3263         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3264
3265 out:
3266         vmx->emulation_required = emulation_required(vcpu);
3267 }
3268
3269 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3270 {
3271         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3272
3273         *db = (ar >> 14) & 1;
3274         *l = (ar >> 13) & 1;
3275 }
3276
3277 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3278 {
3279         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3280         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3281 }
3282
3283 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3284 {
3285         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3286         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3287 }
3288
3289 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3290 {
3291         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3292         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3293 }
3294
3295 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3296 {
3297         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3298         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3299 }
3300
3301 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3302 {
3303         struct kvm_segment var;
3304         u32 ar;
3305
3306         vmx_get_segment(vcpu, &var, seg);
3307         var.dpl = 0x3;
3308         if (seg == VCPU_SREG_CS)
3309                 var.type = 0x3;
3310         ar = vmx_segment_access_rights(&var);
3311
3312         if (var.base != (var.selector << 4))
3313                 return false;
3314         if (var.limit != 0xffff)
3315                 return false;
3316         if (ar != 0xf3)
3317                 return false;
3318
3319         return true;
3320 }
3321
3322 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3323 {
3324         struct kvm_segment cs;
3325         unsigned int cs_rpl;
3326
3327         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3328         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3329
3330         if (cs.unusable)
3331                 return false;
3332         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3333                 return false;
3334         if (!cs.s)
3335                 return false;
3336         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3337                 if (cs.dpl > cs_rpl)
3338                         return false;
3339         } else {
3340                 if (cs.dpl != cs_rpl)
3341                         return false;
3342         }
3343         if (!cs.present)
3344                 return false;
3345
3346         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3347         return true;
3348 }
3349
3350 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3351 {
3352         struct kvm_segment ss;
3353         unsigned int ss_rpl;
3354
3355         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3356         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3357
3358         if (ss.unusable)
3359                 return true;
3360         if (ss.type != 3 && ss.type != 7)
3361                 return false;
3362         if (!ss.s)
3363                 return false;
3364         if (ss.dpl != ss_rpl) /* DPL != RPL */
3365                 return false;
3366         if (!ss.present)
3367                 return false;
3368
3369         return true;
3370 }
3371
3372 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3373 {
3374         struct kvm_segment var;
3375         unsigned int rpl;
3376
3377         vmx_get_segment(vcpu, &var, seg);
3378         rpl = var.selector & SEGMENT_RPL_MASK;
3379
3380         if (var.unusable)
3381                 return true;
3382         if (!var.s)
3383                 return false;
3384         if (!var.present)
3385                 return false;
3386         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3387                 if (var.dpl < rpl) /* DPL < RPL */
3388                         return false;
3389         }
3390
3391         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3392          * rights flags
3393          */
3394         return true;
3395 }
3396
3397 static bool tr_valid(struct kvm_vcpu *vcpu)
3398 {
3399         struct kvm_segment tr;
3400
3401         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3402
3403         if (tr.unusable)
3404                 return false;
3405         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3406                 return false;
3407         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3408                 return false;
3409         if (!tr.present)
3410                 return false;
3411
3412         return true;
3413 }
3414
3415 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3416 {
3417         struct kvm_segment ldtr;
3418
3419         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3420
3421         if (ldtr.unusable)
3422                 return true;
3423         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3424                 return false;
3425         if (ldtr.type != 2)
3426                 return false;
3427         if (!ldtr.present)
3428                 return false;
3429
3430         return true;
3431 }
3432
3433 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3434 {
3435         struct kvm_segment cs, ss;
3436
3437         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3438         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3439
3440         return ((cs.selector & SEGMENT_RPL_MASK) ==
3441                  (ss.selector & SEGMENT_RPL_MASK));
3442 }
3443
3444 /*
3445  * Check if guest state is valid. Returns true if valid, false if
3446  * not.
3447  * We assume that registers are always usable
3448  */
3449 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3450 {
3451         if (enable_unrestricted_guest)
3452                 return true;
3453
3454         /* real mode guest state checks */
3455         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3456                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3457                         return false;
3458                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3459                         return false;
3460                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3461                         return false;
3462                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3463                         return false;
3464                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3465                         return false;
3466                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3467                         return false;
3468         } else {
3469         /* protected mode guest state checks */
3470                 if (!cs_ss_rpl_check(vcpu))
3471                         return false;
3472                 if (!code_segment_valid(vcpu))
3473                         return false;
3474                 if (!stack_segment_valid(vcpu))
3475                         return false;
3476                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3477                         return false;
3478                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3479                         return false;
3480                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3481                         return false;
3482                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3483                         return false;
3484                 if (!tr_valid(vcpu))
3485                         return false;
3486                 if (!ldtr_valid(vcpu))
3487                         return false;
3488         }
3489         /* TODO:
3490          * - Add checks on RIP
3491          * - Add checks on RFLAGS
3492          */
3493
3494         return true;
3495 }
3496
3497 static int init_rmode_tss(struct kvm *kvm)
3498 {
3499         gfn_t fn;
3500         u16 data = 0;
3501         int idx, r;
3502
3503         idx = srcu_read_lock(&kvm->srcu);
3504         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3505         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3506         if (r < 0)
3507                 goto out;
3508         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3509         r = kvm_write_guest_page(kvm, fn++, &data,
3510                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3511         if (r < 0)
3512                 goto out;
3513         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3514         if (r < 0)
3515                 goto out;
3516         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3517         if (r < 0)
3518                 goto out;
3519         data = ~0;
3520         r = kvm_write_guest_page(kvm, fn, &data,
3521                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3522                                  sizeof(u8));
3523 out:
3524         srcu_read_unlock(&kvm->srcu, idx);
3525         return r;
3526 }
3527
3528 static int init_rmode_identity_map(struct kvm *kvm)
3529 {
3530         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3531         int i, r = 0;
3532         kvm_pfn_t identity_map_pfn;
3533         u32 tmp;
3534
3535         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3536         mutex_lock(&kvm->slots_lock);
3537
3538         if (likely(kvm_vmx->ept_identity_pagetable_done))
3539                 goto out;
3540
3541         if (!kvm_vmx->ept_identity_map_addr)
3542                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3543         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3544
3545         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3546                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3547         if (r < 0)
3548                 goto out;
3549
3550         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3551         if (r < 0)
3552                 goto out;
3553         /* Set up identity-mapping pagetable for EPT in real mode */
3554         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3555                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3556                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3557                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3558                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3559                 if (r < 0)
3560                         goto out;
3561         }
3562         kvm_vmx->ept_identity_pagetable_done = true;
3563
3564 out:
3565         mutex_unlock(&kvm->slots_lock);
3566         return r;
3567 }
3568
3569 static void seg_setup(int seg)
3570 {
3571         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3572         unsigned int ar;
3573
3574         vmcs_write16(sf->selector, 0);
3575         vmcs_writel(sf->base, 0);
3576         vmcs_write32(sf->limit, 0xffff);
3577         ar = 0x93;
3578         if (seg == VCPU_SREG_CS)
3579                 ar |= 0x08; /* code segment */
3580
3581         vmcs_write32(sf->ar_bytes, ar);
3582 }
3583
3584 static int alloc_apic_access_page(struct kvm *kvm)
3585 {
3586         struct page *page;
3587         int r = 0;
3588
3589         mutex_lock(&kvm->slots_lock);
3590         if (kvm->arch.apic_access_page_done)
3591                 goto out;
3592         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3593                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3594         if (r)
3595                 goto out;
3596
3597         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3598         if (is_error_page(page)) {
3599                 r = -EFAULT;
3600                 goto out;
3601         }
3602
3603         /*
3604          * Do not pin the page in memory, so that memory hot-unplug
3605          * is able to migrate it.
3606          */
3607         put_page(page);
3608         kvm->arch.apic_access_page_done = true;
3609 out:
3610         mutex_unlock(&kvm->slots_lock);
3611         return r;
3612 }
3613
3614 int allocate_vpid(void)
3615 {
3616         int vpid;
3617
3618         if (!enable_vpid)
3619                 return 0;
3620         spin_lock(&vmx_vpid_lock);
3621         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3622         if (vpid < VMX_NR_VPIDS)
3623                 __set_bit(vpid, vmx_vpid_bitmap);
3624         else
3625                 vpid = 0;
3626         spin_unlock(&vmx_vpid_lock);
3627         return vpid;
3628 }
3629
3630 void free_vpid(int vpid)
3631 {
3632         if (!enable_vpid || vpid == 0)
3633                 return;
3634         spin_lock(&vmx_vpid_lock);
3635         __clear_bit(vpid, vmx_vpid_bitmap);
3636         spin_unlock(&vmx_vpid_lock);
3637 }
3638
3639 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3640                                                           u32 msr, int type)
3641 {
3642         int f = sizeof(unsigned long);
3643
3644         if (!cpu_has_vmx_msr_bitmap())
3645                 return;
3646
3647         if (static_branch_unlikely(&enable_evmcs))
3648                 evmcs_touch_msr_bitmap();
3649
3650         /*
3651          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3652          * have the write-low and read-high bitmap offsets the wrong way round.
3653          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3654          */
3655         if (msr <= 0x1fff) {
3656                 if (type & MSR_TYPE_R)
3657                         /* read-low */
3658                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3659
3660                 if (type & MSR_TYPE_W)
3661                         /* write-low */
3662                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3663
3664         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3665                 msr &= 0x1fff;
3666                 if (type & MSR_TYPE_R)
3667                         /* read-high */
3668                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3669
3670                 if (type & MSR_TYPE_W)
3671                         /* write-high */
3672                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3673
3674         }
3675 }
3676
3677 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3678                                                          u32 msr, int type)
3679 {
3680         int f = sizeof(unsigned long);
3681
3682         if (!cpu_has_vmx_msr_bitmap())
3683                 return;
3684
3685         if (static_branch_unlikely(&enable_evmcs))
3686                 evmcs_touch_msr_bitmap();
3687
3688         /*
3689          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3690          * have the write-low and read-high bitmap offsets the wrong way round.
3691          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3692          */
3693         if (msr <= 0x1fff) {
3694                 if (type & MSR_TYPE_R)
3695                         /* read-low */
3696                         __set_bit(msr, msr_bitmap + 0x000 / f);
3697
3698                 if (type & MSR_TYPE_W)
3699                         /* write-low */
3700                         __set_bit(msr, msr_bitmap + 0x800 / f);
3701
3702         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3703                 msr &= 0x1fff;
3704                 if (type & MSR_TYPE_R)
3705                         /* read-high */
3706                         __set_bit(msr, msr_bitmap + 0x400 / f);
3707
3708                 if (type & MSR_TYPE_W)
3709                         /* write-high */
3710                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3711
3712         }
3713 }
3714
3715 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3716                                                       u32 msr, int type, bool value)
3717 {
3718         if (value)
3719                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3720         else
3721                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3722 }
3723
3724 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3725 {
3726         u8 mode = 0;
3727
3728         if (cpu_has_secondary_exec_ctrls() &&
3729             (secondary_exec_controls_get(to_vmx(vcpu)) &
3730              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3731                 mode |= MSR_BITMAP_MODE_X2APIC;
3732                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3733                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3734         }
3735
3736         return mode;
3737 }
3738
3739 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3740                                          u8 mode)
3741 {
3742         int msr;
3743
3744         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3745                 unsigned word = msr / BITS_PER_LONG;
3746                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3747                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3748         }
3749
3750         if (mode & MSR_BITMAP_MODE_X2APIC) {
3751                 /*
3752                  * TPR reads and writes can be virtualized even if virtual interrupt
3753                  * delivery is not in use.
3754                  */
3755                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3756                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3757                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3758                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3759                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3760                 }
3761         }
3762 }
3763
3764 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3765 {
3766         struct vcpu_vmx *vmx = to_vmx(vcpu);
3767         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3768         u8 mode = vmx_msr_bitmap_mode(vcpu);
3769         u8 changed = mode ^ vmx->msr_bitmap_mode;
3770
3771         if (!changed)
3772                 return;
3773
3774         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3775                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3776
3777         vmx->msr_bitmap_mode = mode;
3778 }
3779
3780 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3781 {
3782         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3783         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3784         u32 i;
3785
3786         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3787                                                         MSR_TYPE_RW, flag);
3788         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3789                                                         MSR_TYPE_RW, flag);
3790         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3791                                                         MSR_TYPE_RW, flag);
3792         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3793                                                         MSR_TYPE_RW, flag);
3794         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3795                 vmx_set_intercept_for_msr(msr_bitmap,
3796                         MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3797                 vmx_set_intercept_for_msr(msr_bitmap,
3798                         MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3799         }
3800 }
3801
3802 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3803 {
3804         struct vcpu_vmx *vmx = to_vmx(vcpu);
3805         void *vapic_page;
3806         u32 vppr;
3807         int rvi;
3808
3809         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3810                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3811                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3812                 return false;
3813
3814         rvi = vmx_get_rvi();
3815
3816         vapic_page = vmx->nested.virtual_apic_map.hva;
3817         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3818
3819         return ((rvi & 0xf0) > (vppr & 0xf0));
3820 }
3821
3822 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3823                                                      bool nested)
3824 {
3825 #ifdef CONFIG_SMP
3826         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3827
3828         if (vcpu->mode == IN_GUEST_MODE) {
3829                 /*
3830                  * The vector of interrupt to be delivered to vcpu had
3831                  * been set in PIR before this function.
3832                  *
3833                  * Following cases will be reached in this block, and
3834                  * we always send a notification event in all cases as
3835                  * explained below.
3836                  *
3837                  * Case 1: vcpu keeps in non-root mode. Sending a
3838                  * notification event posts the interrupt to vcpu.
3839                  *
3840                  * Case 2: vcpu exits to root mode and is still
3841                  * runnable. PIR will be synced to vIRR before the
3842                  * next vcpu entry. Sending a notification event in
3843                  * this case has no effect, as vcpu is not in root
3844                  * mode.
3845                  *
3846                  * Case 3: vcpu exits to root mode and is blocked.
3847                  * vcpu_block() has already synced PIR to vIRR and
3848                  * never blocks vcpu if vIRR is not cleared. Therefore,
3849                  * a blocked vcpu here does not wait for any requested
3850                  * interrupts in PIR, and sending a notification event
3851                  * which has no effect is safe here.
3852                  */
3853
3854                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3855                 return true;
3856         }
3857 #endif
3858         return false;
3859 }
3860
3861 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3862                                                 int vector)
3863 {
3864         struct vcpu_vmx *vmx = to_vmx(vcpu);
3865
3866         if (is_guest_mode(vcpu) &&
3867             vector == vmx->nested.posted_intr_nv) {
3868                 /*
3869                  * If a posted intr is not recognized by hardware,
3870                  * we will accomplish it in the next vmentry.
3871                  */
3872                 vmx->nested.pi_pending = true;
3873                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3874                 /* the PIR and ON have been set by L1. */
3875                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3876                         kvm_vcpu_kick(vcpu);
3877                 return 0;
3878         }
3879         return -1;
3880 }
3881 /*
3882  * Send interrupt to vcpu via posted interrupt way.
3883  * 1. If target vcpu is running(non-root mode), send posted interrupt
3884  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3885  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3886  * interrupt from PIR in next vmentry.
3887  */
3888 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3889 {
3890         struct vcpu_vmx *vmx = to_vmx(vcpu);
3891         int r;
3892
3893         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3894         if (!r)
3895                 return 0;
3896
3897         if (!vcpu->arch.apicv_active)
3898                 return -1;
3899
3900         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3901                 return 0;
3902
3903         /* If a previous notification has sent the IPI, nothing to do.  */
3904         if (pi_test_and_set_on(&vmx->pi_desc))
3905                 return 0;
3906
3907         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3908                 kvm_vcpu_kick(vcpu);
3909
3910         return 0;
3911 }
3912
3913 /*
3914  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3915  * will not change in the lifetime of the guest.
3916  * Note that host-state that does change is set elsewhere. E.g., host-state
3917  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3918  */
3919 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3920 {
3921         u32 low32, high32;
3922         unsigned long tmpl;
3923         unsigned long cr0, cr3, cr4;
3924
3925         cr0 = read_cr0();
3926         WARN_ON(cr0 & X86_CR0_TS);
3927         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3928
3929         /*
3930          * Save the most likely value for this task's CR3 in the VMCS.
3931          * We can't use __get_current_cr3_fast() because we're not atomic.
3932          */
3933         cr3 = __read_cr3();
3934         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
3935         vmx->loaded_vmcs->host_state.cr3 = cr3;
3936
3937         /* Save the most likely value for this task's CR4 in the VMCS. */
3938         cr4 = cr4_read_shadow();
3939         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
3940         vmx->loaded_vmcs->host_state.cr4 = cr4;
3941
3942         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3943 #ifdef CONFIG_X86_64
3944         /*
3945          * Load null selectors, so we can avoid reloading them in
3946          * vmx_prepare_switch_to_host(), in case userspace uses
3947          * the null selectors too (the expected case).
3948          */
3949         vmcs_write16(HOST_DS_SELECTOR, 0);
3950         vmcs_write16(HOST_ES_SELECTOR, 0);
3951 #else
3952         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3953         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3954 #endif
3955         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3956         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3957
3958         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
3959
3960         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3961
3962         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3963         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3964         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3965         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3966
3967         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3968                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3969                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3970         }
3971
3972         if (cpu_has_load_ia32_efer())
3973                 vmcs_write64(HOST_IA32_EFER, host_efer);
3974 }
3975
3976 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3977 {
3978         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3979         if (enable_ept)
3980                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3981         if (is_guest_mode(&vmx->vcpu))
3982                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3983                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3984         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3985 }
3986
3987 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3988 {
3989         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3990
3991         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3992                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3993
3994         if (!enable_vnmi)
3995                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3996
3997         if (!enable_preemption_timer)
3998                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3999
4000         return pin_based_exec_ctrl;
4001 }
4002
4003 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4004 {
4005         struct vcpu_vmx *vmx = to_vmx(vcpu);
4006
4007         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4008         if (cpu_has_secondary_exec_ctrls()) {
4009                 if (kvm_vcpu_apicv_active(vcpu))
4010                         secondary_exec_controls_setbit(vmx,
4011                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4012                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4013                 else
4014                         secondary_exec_controls_clearbit(vmx,
4015                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4016                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4017         }
4018
4019         if (cpu_has_vmx_msr_bitmap())
4020                 vmx_update_msr_bitmap(vcpu);
4021 }
4022
4023 u32 vmx_exec_control(struct vcpu_vmx *vmx)
4024 {
4025         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4026
4027         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4028                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4029
4030         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4031                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4032 #ifdef CONFIG_X86_64
4033                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4034                                 CPU_BASED_CR8_LOAD_EXITING;
4035 #endif
4036         }
4037         if (!enable_ept)
4038                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4039                                 CPU_BASED_CR3_LOAD_EXITING  |
4040                                 CPU_BASED_INVLPG_EXITING;
4041         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4042                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4043                                 CPU_BASED_MONITOR_EXITING);
4044         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4045                 exec_control &= ~CPU_BASED_HLT_EXITING;
4046         return exec_control;
4047 }
4048
4049
4050 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4051 {
4052         struct kvm_vcpu *vcpu = &vmx->vcpu;
4053
4054         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4055
4056         if (vmx_pt_mode_is_system())
4057                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4058         if (!cpu_need_virtualize_apic_accesses(vcpu))
4059                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4060         if (vmx->vpid == 0)
4061                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4062         if (!enable_ept) {
4063                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4064                 enable_unrestricted_guest = 0;
4065         }
4066         if (!enable_unrestricted_guest)
4067                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4068         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4069                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4070         if (!kvm_vcpu_apicv_active(vcpu))
4071                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4072                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4073         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4074
4075         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4076          * in vmx_set_cr4.  */
4077         exec_control &= ~SECONDARY_EXEC_DESC;
4078
4079         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4080            (handle_vmptrld).
4081            We can NOT enable shadow_vmcs here because we don't have yet
4082            a current VMCS12
4083         */
4084         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4085
4086         if (!enable_pml)
4087                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4088
4089         if (vmx_xsaves_supported()) {
4090                 /* Exposing XSAVES only when XSAVE is exposed */
4091                 bool xsaves_enabled =
4092                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4093                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4094                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4095
4096                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4097
4098                 if (!xsaves_enabled)
4099                         exec_control &= ~SECONDARY_EXEC_XSAVES;
4100
4101                 if (nested) {
4102                         if (xsaves_enabled)
4103                                 vmx->nested.msrs.secondary_ctls_high |=
4104                                         SECONDARY_EXEC_XSAVES;
4105                         else
4106                                 vmx->nested.msrs.secondary_ctls_high &=
4107                                         ~SECONDARY_EXEC_XSAVES;
4108                 }
4109         }
4110
4111         if (cpu_has_vmx_rdtscp()) {
4112                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4113                 if (!rdtscp_enabled)
4114                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
4115
4116                 if (nested) {
4117                         if (rdtscp_enabled)
4118                                 vmx->nested.msrs.secondary_ctls_high |=
4119                                         SECONDARY_EXEC_RDTSCP;
4120                         else
4121                                 vmx->nested.msrs.secondary_ctls_high &=
4122                                         ~SECONDARY_EXEC_RDTSCP;
4123                 }
4124         }
4125
4126         if (cpu_has_vmx_invpcid()) {
4127                 /* Exposing INVPCID only when PCID is exposed */
4128                 bool invpcid_enabled =
4129                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4130                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4131
4132                 if (!invpcid_enabled) {
4133                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4134                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4135                 }
4136
4137                 if (nested) {
4138                         if (invpcid_enabled)
4139                                 vmx->nested.msrs.secondary_ctls_high |=
4140                                         SECONDARY_EXEC_ENABLE_INVPCID;
4141                         else
4142                                 vmx->nested.msrs.secondary_ctls_high &=
4143                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
4144                 }
4145         }
4146
4147         if (vmx_rdrand_supported()) {
4148                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4149                 if (rdrand_enabled)
4150                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4151
4152                 if (nested) {
4153                         if (rdrand_enabled)
4154                                 vmx->nested.msrs.secondary_ctls_high |=
4155                                         SECONDARY_EXEC_RDRAND_EXITING;
4156                         else
4157                                 vmx->nested.msrs.secondary_ctls_high &=
4158                                         ~SECONDARY_EXEC_RDRAND_EXITING;
4159                 }
4160         }
4161
4162         if (vmx_rdseed_supported()) {
4163                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4164                 if (rdseed_enabled)
4165                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4166
4167                 if (nested) {
4168                         if (rdseed_enabled)
4169                                 vmx->nested.msrs.secondary_ctls_high |=
4170                                         SECONDARY_EXEC_RDSEED_EXITING;
4171                         else
4172                                 vmx->nested.msrs.secondary_ctls_high &=
4173                                         ~SECONDARY_EXEC_RDSEED_EXITING;
4174                 }
4175         }
4176
4177         if (vmx_waitpkg_supported()) {
4178                 bool waitpkg_enabled =
4179                         guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4180
4181                 if (!waitpkg_enabled)
4182                         exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4183
4184                 if (nested) {
4185                         if (waitpkg_enabled)
4186                                 vmx->nested.msrs.secondary_ctls_high |=
4187                                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4188                         else
4189                                 vmx->nested.msrs.secondary_ctls_high &=
4190                                         ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4191                 }
4192         }
4193
4194         vmx->secondary_exec_control = exec_control;
4195 }
4196
4197 static void ept_set_mmio_spte_mask(void)
4198 {
4199         /*
4200          * EPT Misconfigurations can be generated if the value of bits 2:0
4201          * of an EPT paging-structure entry is 110b (write/execute).
4202          */
4203         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4204                                    VMX_EPT_MISCONFIG_WX_VALUE, 0);
4205 }
4206
4207 #define VMX_XSS_EXIT_BITMAP 0
4208
4209 /*
4210  * Noting that the initialization of Guest-state Area of VMCS is in
4211  * vmx_vcpu_reset().
4212  */
4213 static void init_vmcs(struct vcpu_vmx *vmx)
4214 {
4215         if (nested)
4216                 nested_vmx_set_vmcs_shadowing_bitmap();
4217
4218         if (cpu_has_vmx_msr_bitmap())
4219                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4220
4221         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4222
4223         /* Control */
4224         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4225
4226         exec_controls_set(vmx, vmx_exec_control(vmx));
4227
4228         if (cpu_has_secondary_exec_ctrls()) {
4229                 vmx_compute_secondary_exec_control(vmx);
4230                 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4231         }
4232
4233         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4234                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4235                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4236                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4237                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4238
4239                 vmcs_write16(GUEST_INTR_STATUS, 0);
4240
4241                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4242                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4243         }
4244
4245         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4246                 vmcs_write32(PLE_GAP, ple_gap);
4247                 vmx->ple_window = ple_window;
4248                 vmx->ple_window_dirty = true;
4249         }
4250
4251         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4252         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4253         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4254
4255         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4256         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4257         vmx_set_constant_host_state(vmx);
4258         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4259         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4260
4261         if (cpu_has_vmx_vmfunc())
4262                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4263
4264         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4265         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4266         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4267         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4268         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4269
4270         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4271                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4272
4273         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4274
4275         /* 22.2.1, 20.8.1 */
4276         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4277
4278         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4279         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4280
4281         set_cr4_guest_host_mask(vmx);
4282
4283         if (vmx->vpid != 0)
4284                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4285
4286         if (vmx_xsaves_supported())
4287                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4288
4289         if (enable_pml) {
4290                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4291                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4292         }
4293
4294         if (cpu_has_vmx_encls_vmexit())
4295                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4296
4297         if (vmx_pt_mode_is_host_guest()) {
4298                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4299                 /* Bit[6~0] are forced to 1, writes are ignored. */
4300                 vmx->pt_desc.guest.output_mask = 0x7F;
4301                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4302         }
4303 }
4304
4305 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4306 {
4307         struct vcpu_vmx *vmx = to_vmx(vcpu);
4308         struct msr_data apic_base_msr;
4309         u64 cr0;
4310
4311         vmx->rmode.vm86_active = 0;
4312         vmx->spec_ctrl = 0;
4313
4314         vmx->msr_ia32_umwait_control = 0;
4315
4316         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4317         vmx->hv_deadline_tsc = -1;
4318         kvm_set_cr8(vcpu, 0);
4319
4320         if (!init_event) {
4321                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4322                                      MSR_IA32_APICBASE_ENABLE;
4323                 if (kvm_vcpu_is_reset_bsp(vcpu))
4324                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4325                 apic_base_msr.host_initiated = true;
4326                 kvm_set_apic_base(vcpu, &apic_base_msr);
4327         }
4328
4329         vmx_segment_cache_clear(vmx);
4330
4331         seg_setup(VCPU_SREG_CS);
4332         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4333         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4334
4335         seg_setup(VCPU_SREG_DS);
4336         seg_setup(VCPU_SREG_ES);
4337         seg_setup(VCPU_SREG_FS);
4338         seg_setup(VCPU_SREG_GS);
4339         seg_setup(VCPU_SREG_SS);
4340
4341         vmcs_write16(GUEST_TR_SELECTOR, 0);
4342         vmcs_writel(GUEST_TR_BASE, 0);
4343         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4344         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4345
4346         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4347         vmcs_writel(GUEST_LDTR_BASE, 0);
4348         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4349         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4350
4351         if (!init_event) {
4352                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4353                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4354                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4355                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4356         }
4357
4358         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4359         kvm_rip_write(vcpu, 0xfff0);
4360
4361         vmcs_writel(GUEST_GDTR_BASE, 0);
4362         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4363
4364         vmcs_writel(GUEST_IDTR_BASE, 0);
4365         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4366
4367         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4368         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4369         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4370         if (kvm_mpx_supported())
4371                 vmcs_write64(GUEST_BNDCFGS, 0);
4372
4373         setup_msrs(vmx);
4374
4375         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4376
4377         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4378                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4379                 if (cpu_need_tpr_shadow(vcpu))
4380                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4381                                      __pa(vcpu->arch.apic->regs));
4382                 vmcs_write32(TPR_THRESHOLD, 0);
4383         }
4384
4385         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4386
4387         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4388         vmx->vcpu.arch.cr0 = cr0;
4389         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4390         vmx_set_cr4(vcpu, 0);
4391         vmx_set_efer(vcpu, 0);
4392
4393         update_exception_bitmap(vcpu);
4394
4395         vpid_sync_context(vmx->vpid);
4396         if (init_event)
4397                 vmx_clear_hlt(vcpu);
4398 }
4399
4400 static void enable_irq_window(struct kvm_vcpu *vcpu)
4401 {
4402         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4403 }
4404
4405 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4406 {
4407         if (!enable_vnmi ||
4408             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4409                 enable_irq_window(vcpu);
4410                 return;
4411         }
4412
4413         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4414 }
4415
4416 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4417 {
4418         struct vcpu_vmx *vmx = to_vmx(vcpu);
4419         uint32_t intr;
4420         int irq = vcpu->arch.interrupt.nr;
4421
4422         trace_kvm_inj_virq(irq);
4423
4424         ++vcpu->stat.irq_injections;
4425         if (vmx->rmode.vm86_active) {
4426                 int inc_eip = 0;
4427                 if (vcpu->arch.interrupt.soft)
4428                         inc_eip = vcpu->arch.event_exit_inst_len;
4429                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4430                 return;
4431         }
4432         intr = irq | INTR_INFO_VALID_MASK;
4433         if (vcpu->arch.interrupt.soft) {
4434                 intr |= INTR_TYPE_SOFT_INTR;
4435                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4436                              vmx->vcpu.arch.event_exit_inst_len);
4437         } else
4438                 intr |= INTR_TYPE_EXT_INTR;
4439         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4440
4441         vmx_clear_hlt(vcpu);
4442 }
4443
4444 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4445 {
4446         struct vcpu_vmx *vmx = to_vmx(vcpu);
4447
4448         if (!enable_vnmi) {
4449                 /*
4450                  * Tracking the NMI-blocked state in software is built upon
4451                  * finding the next open IRQ window. This, in turn, depends on
4452                  * well-behaving guests: They have to keep IRQs disabled at
4453                  * least as long as the NMI handler runs. Otherwise we may
4454                  * cause NMI nesting, maybe breaking the guest. But as this is
4455                  * highly unlikely, we can live with the residual risk.
4456                  */
4457                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4458                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4459         }
4460
4461         ++vcpu->stat.nmi_injections;
4462         vmx->loaded_vmcs->nmi_known_unmasked = false;
4463
4464         if (vmx->rmode.vm86_active) {
4465                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4466                 return;
4467         }
4468
4469         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4470                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4471
4472         vmx_clear_hlt(vcpu);
4473 }
4474
4475 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4476 {
4477         struct vcpu_vmx *vmx = to_vmx(vcpu);
4478         bool masked;
4479
4480         if (!enable_vnmi)
4481                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4482         if (vmx->loaded_vmcs->nmi_known_unmasked)
4483                 return false;
4484         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4485         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4486         return masked;
4487 }
4488
4489 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4490 {
4491         struct vcpu_vmx *vmx = to_vmx(vcpu);
4492
4493         if (!enable_vnmi) {
4494                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4495                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4496                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4497                 }
4498         } else {
4499                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4500                 if (masked)
4501                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4502                                       GUEST_INTR_STATE_NMI);
4503                 else
4504                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4505                                         GUEST_INTR_STATE_NMI);
4506         }
4507 }
4508
4509 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4510 {
4511         if (to_vmx(vcpu)->nested.nested_run_pending)
4512                 return 0;
4513
4514         if (!enable_vnmi &&
4515             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4516                 return 0;
4517
4518         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4519                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4520                    | GUEST_INTR_STATE_NMI));
4521 }
4522
4523 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4524 {
4525         if (to_vmx(vcpu)->nested.nested_run_pending)
4526                 return false;
4527
4528         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4529                 return true;
4530
4531         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4532                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4533                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4534 }
4535
4536 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4537 {
4538         int ret;
4539
4540         if (enable_unrestricted_guest)
4541                 return 0;
4542
4543         mutex_lock(&kvm->slots_lock);
4544         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4545                                       PAGE_SIZE * 3);
4546         mutex_unlock(&kvm->slots_lock);
4547
4548         if (ret)
4549                 return ret;
4550         to_kvm_vmx(kvm)->tss_addr = addr;
4551         return init_rmode_tss(kvm);
4552 }
4553
4554 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4555 {
4556         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4557         return 0;
4558 }
4559
4560 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4561 {
4562         switch (vec) {
4563         case BP_VECTOR:
4564                 /*
4565                  * Update instruction length as we may reinject the exception
4566                  * from user space while in guest debugging mode.
4567                  */
4568                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4569                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4570                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4571                         return false;
4572                 /* fall through */
4573         case DB_VECTOR:
4574                 if (vcpu->guest_debug &
4575                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4576                         return false;
4577                 /* fall through */
4578         case DE_VECTOR:
4579         case OF_VECTOR:
4580         case BR_VECTOR:
4581         case UD_VECTOR:
4582         case DF_VECTOR:
4583         case SS_VECTOR:
4584         case GP_VECTOR:
4585         case MF_VECTOR:
4586                 return true;
4587         }
4588         return false;
4589 }
4590
4591 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4592                                   int vec, u32 err_code)
4593 {
4594         /*
4595          * Instruction with address size override prefix opcode 0x67
4596          * Cause the #SS fault with 0 error code in VM86 mode.
4597          */
4598         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4599                 if (kvm_emulate_instruction(vcpu, 0)) {
4600                         if (vcpu->arch.halt_request) {
4601                                 vcpu->arch.halt_request = 0;
4602                                 return kvm_vcpu_halt(vcpu);
4603                         }
4604                         return 1;
4605                 }
4606                 return 0;
4607         }
4608
4609         /*
4610          * Forward all other exceptions that are valid in real mode.
4611          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4612          *        the required debugging infrastructure rework.
4613          */
4614         kvm_queue_exception(vcpu, vec);
4615         return 1;
4616 }
4617
4618 /*
4619  * Trigger machine check on the host. We assume all the MSRs are already set up
4620  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4621  * We pass a fake environment to the machine check handler because we want
4622  * the guest to be always treated like user space, no matter what context
4623  * it used internally.
4624  */
4625 static void kvm_machine_check(void)
4626 {
4627 #if defined(CONFIG_X86_MCE)
4628         struct pt_regs regs = {
4629                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4630                 .flags = X86_EFLAGS_IF,
4631         };
4632
4633         do_machine_check(&regs, 0);
4634 #endif
4635 }
4636
4637 static int handle_machine_check(struct kvm_vcpu *vcpu)
4638 {
4639         /* handled by vmx_vcpu_run() */
4640         return 1;
4641 }
4642
4643 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4644 {
4645         struct vcpu_vmx *vmx = to_vmx(vcpu);
4646         struct kvm_run *kvm_run = vcpu->run;
4647         u32 intr_info, ex_no, error_code;
4648         unsigned long cr2, rip, dr6;
4649         u32 vect_info;
4650
4651         vect_info = vmx->idt_vectoring_info;
4652         intr_info = vmx->exit_intr_info;
4653
4654         if (is_machine_check(intr_info) || is_nmi(intr_info))
4655                 return 1; /* handled by handle_exception_nmi_irqoff() */
4656
4657         if (is_invalid_opcode(intr_info))
4658                 return handle_ud(vcpu);
4659
4660         error_code = 0;
4661         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4662                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4663
4664         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4665                 WARN_ON_ONCE(!enable_vmware_backdoor);
4666
4667                 /*
4668                  * VMware backdoor emulation on #GP interception only handles
4669                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4670                  * error code on #GP.
4671                  */
4672                 if (error_code) {
4673                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4674                         return 1;
4675                 }
4676                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4677         }
4678
4679         /*
4680          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4681          * MMIO, it is better to report an internal error.
4682          * See the comments in vmx_handle_exit.
4683          */
4684         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4685             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4686                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4687                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4688                 vcpu->run->internal.ndata = 3;
4689                 vcpu->run->internal.data[0] = vect_info;
4690                 vcpu->run->internal.data[1] = intr_info;
4691                 vcpu->run->internal.data[2] = error_code;
4692                 return 0;
4693         }
4694
4695         if (is_page_fault(intr_info)) {
4696                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4697                 /* EPT won't cause page fault directly */
4698                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4699                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4700         }
4701
4702         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4703
4704         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4705                 return handle_rmode_exception(vcpu, ex_no, error_code);
4706
4707         switch (ex_no) {
4708         case AC_VECTOR:
4709                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4710                 return 1;
4711         case DB_VECTOR:
4712                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4713                 if (!(vcpu->guest_debug &
4714                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4715                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4716                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4717                         if (is_icebp(intr_info))
4718                                 WARN_ON(!skip_emulated_instruction(vcpu));
4719
4720                         kvm_queue_exception(vcpu, DB_VECTOR);
4721                         return 1;
4722                 }
4723                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4724                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4725                 /* fall through */
4726         case BP_VECTOR:
4727                 /*
4728                  * Update instruction length as we may reinject #BP from
4729                  * user space while in guest debugging mode. Reading it for
4730                  * #DB as well causes no harm, it is not used in that case.
4731                  */
4732                 vmx->vcpu.arch.event_exit_inst_len =
4733                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4734                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4735                 rip = kvm_rip_read(vcpu);
4736                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4737                 kvm_run->debug.arch.exception = ex_no;
4738                 break;
4739         default:
4740                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4741                 kvm_run->ex.exception = ex_no;
4742                 kvm_run->ex.error_code = error_code;
4743                 break;
4744         }
4745         return 0;
4746 }
4747
4748 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4749 {
4750         ++vcpu->stat.irq_exits;
4751         return 1;
4752 }
4753
4754 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4755 {
4756         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4757         vcpu->mmio_needed = 0;
4758         return 0;
4759 }
4760
4761 static int handle_io(struct kvm_vcpu *vcpu)
4762 {
4763         unsigned long exit_qualification;
4764         int size, in, string;
4765         unsigned port;
4766
4767         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4768         string = (exit_qualification & 16) != 0;
4769
4770         ++vcpu->stat.io_exits;
4771
4772         if (string)
4773                 return kvm_emulate_instruction(vcpu, 0);
4774
4775         port = exit_qualification >> 16;
4776         size = (exit_qualification & 7) + 1;
4777         in = (exit_qualification & 8) != 0;
4778
4779         return kvm_fast_pio(vcpu, size, port, in);
4780 }
4781
4782 static void
4783 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4784 {
4785         /*
4786          * Patch in the VMCALL instruction:
4787          */
4788         hypercall[0] = 0x0f;
4789         hypercall[1] = 0x01;
4790         hypercall[2] = 0xc1;
4791 }
4792
4793 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4794 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4795 {
4796         if (is_guest_mode(vcpu)) {
4797                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4798                 unsigned long orig_val = val;
4799
4800                 /*
4801                  * We get here when L2 changed cr0 in a way that did not change
4802                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4803                  * but did change L0 shadowed bits. So we first calculate the
4804                  * effective cr0 value that L1 would like to write into the
4805                  * hardware. It consists of the L2-owned bits from the new
4806                  * value combined with the L1-owned bits from L1's guest_cr0.
4807                  */
4808                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4809                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4810
4811                 if (!nested_guest_cr0_valid(vcpu, val))
4812                         return 1;
4813
4814                 if (kvm_set_cr0(vcpu, val))
4815                         return 1;
4816                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4817                 return 0;
4818         } else {
4819                 if (to_vmx(vcpu)->nested.vmxon &&
4820                     !nested_host_cr0_valid(vcpu, val))
4821                         return 1;
4822
4823                 return kvm_set_cr0(vcpu, val);
4824         }
4825 }
4826
4827 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4828 {
4829         if (is_guest_mode(vcpu)) {
4830                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4831                 unsigned long orig_val = val;
4832
4833                 /* analogously to handle_set_cr0 */
4834                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4835                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4836                 if (kvm_set_cr4(vcpu, val))
4837                         return 1;
4838                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4839                 return 0;
4840         } else
4841                 return kvm_set_cr4(vcpu, val);
4842 }
4843
4844 static int handle_desc(struct kvm_vcpu *vcpu)
4845 {
4846         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4847         return kvm_emulate_instruction(vcpu, 0);
4848 }
4849
4850 static int handle_cr(struct kvm_vcpu *vcpu)
4851 {
4852         unsigned long exit_qualification, val;
4853         int cr;
4854         int reg;
4855         int err;
4856         int ret;
4857
4858         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4859         cr = exit_qualification & 15;
4860         reg = (exit_qualification >> 8) & 15;
4861         switch ((exit_qualification >> 4) & 3) {
4862         case 0: /* mov to cr */
4863                 val = kvm_register_readl(vcpu, reg);
4864                 trace_kvm_cr_write(cr, val);
4865                 switch (cr) {
4866                 case 0:
4867                         err = handle_set_cr0(vcpu, val);
4868                         return kvm_complete_insn_gp(vcpu, err);
4869                 case 3:
4870                         WARN_ON_ONCE(enable_unrestricted_guest);
4871                         err = kvm_set_cr3(vcpu, val);
4872                         return kvm_complete_insn_gp(vcpu, err);
4873                 case 4:
4874                         err = handle_set_cr4(vcpu, val);
4875                         return kvm_complete_insn_gp(vcpu, err);
4876                 case 8: {
4877                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4878                                 u8 cr8 = (u8)val;
4879                                 err = kvm_set_cr8(vcpu, cr8);
4880                                 ret = kvm_complete_insn_gp(vcpu, err);
4881                                 if (lapic_in_kernel(vcpu))
4882                                         return ret;
4883                                 if (cr8_prev <= cr8)
4884                                         return ret;
4885                                 /*
4886                                  * TODO: we might be squashing a
4887                                  * KVM_GUESTDBG_SINGLESTEP-triggered
4888                                  * KVM_EXIT_DEBUG here.
4889                                  */
4890                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4891                                 return 0;
4892                         }
4893                 }
4894                 break;
4895         case 2: /* clts */
4896                 WARN_ONCE(1, "Guest should always own CR0.TS");
4897                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4898                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4899                 return kvm_skip_emulated_instruction(vcpu);
4900         case 1: /*mov from cr*/
4901                 switch (cr) {
4902                 case 3:
4903                         WARN_ON_ONCE(enable_unrestricted_guest);
4904                         val = kvm_read_cr3(vcpu);
4905                         kvm_register_write(vcpu, reg, val);
4906                         trace_kvm_cr_read(cr, val);
4907                         return kvm_skip_emulated_instruction(vcpu);
4908                 case 8:
4909                         val = kvm_get_cr8(vcpu);
4910                         kvm_register_write(vcpu, reg, val);
4911                         trace_kvm_cr_read(cr, val);
4912                         return kvm_skip_emulated_instruction(vcpu);
4913                 }
4914                 break;
4915         case 3: /* lmsw */
4916                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4917                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4918                 kvm_lmsw(vcpu, val);
4919
4920                 return kvm_skip_emulated_instruction(vcpu);
4921         default:
4922                 break;
4923         }
4924         vcpu->run->exit_reason = 0;
4925         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4926                (int)(exit_qualification >> 4) & 3, cr);
4927         return 0;
4928 }
4929
4930 static int handle_dr(struct kvm_vcpu *vcpu)
4931 {
4932         unsigned long exit_qualification;
4933         int dr, dr7, reg;
4934
4935         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4936         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4937
4938         /* First, if DR does not exist, trigger UD */
4939         if (!kvm_require_dr(vcpu, dr))
4940                 return 1;
4941
4942         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4943         if (!kvm_require_cpl(vcpu, 0))
4944                 return 1;
4945         dr7 = vmcs_readl(GUEST_DR7);
4946         if (dr7 & DR7_GD) {
4947                 /*
4948                  * As the vm-exit takes precedence over the debug trap, we
4949                  * need to emulate the latter, either for the host or the
4950                  * guest debugging itself.
4951                  */
4952                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4953                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4954                         vcpu->run->debug.arch.dr7 = dr7;
4955                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4956                         vcpu->run->debug.arch.exception = DB_VECTOR;
4957                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4958                         return 0;
4959                 } else {
4960                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4961                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4962                         kvm_queue_exception(vcpu, DB_VECTOR);
4963                         return 1;
4964                 }
4965         }
4966
4967         if (vcpu->guest_debug == 0) {
4968                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4969
4970                 /*
4971                  * No more DR vmexits; force a reload of the debug registers
4972                  * and reenter on this instruction.  The next vmexit will
4973                  * retrieve the full state of the debug registers.
4974                  */
4975                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4976                 return 1;
4977         }
4978
4979         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4980         if (exit_qualification & TYPE_MOV_FROM_DR) {
4981                 unsigned long val;
4982
4983                 if (kvm_get_dr(vcpu, dr, &val))
4984                         return 1;
4985                 kvm_register_write(vcpu, reg, val);
4986         } else
4987                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4988                         return 1;
4989
4990         return kvm_skip_emulated_instruction(vcpu);
4991 }
4992
4993 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4994 {
4995         return vcpu->arch.dr6;
4996 }
4997
4998 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4999 {
5000 }
5001
5002 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5003 {
5004         get_debugreg(vcpu->arch.db[0], 0);
5005         get_debugreg(vcpu->arch.db[1], 1);
5006         get_debugreg(vcpu->arch.db[2], 2);
5007         get_debugreg(vcpu->arch.db[3], 3);
5008         get_debugreg(vcpu->arch.dr6, 6);
5009         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5010
5011         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5012         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5013 }
5014
5015 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5016 {
5017         vmcs_writel(GUEST_DR7, val);
5018 }
5019
5020 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5021 {
5022         kvm_apic_update_ppr(vcpu);
5023         return 1;
5024 }
5025
5026 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5027 {
5028         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5029
5030         kvm_make_request(KVM_REQ_EVENT, vcpu);
5031
5032         ++vcpu->stat.irq_window_exits;
5033         return 1;
5034 }
5035
5036 static int handle_vmcall(struct kvm_vcpu *vcpu)
5037 {
5038         return kvm_emulate_hypercall(vcpu);
5039 }
5040
5041 static int handle_invd(struct kvm_vcpu *vcpu)
5042 {
5043         return kvm_emulate_instruction(vcpu, 0);
5044 }
5045
5046 static int handle_invlpg(struct kvm_vcpu *vcpu)
5047 {
5048         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5049
5050         kvm_mmu_invlpg(vcpu, exit_qualification);
5051         return kvm_skip_emulated_instruction(vcpu);
5052 }
5053
5054 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5055 {
5056         int err;
5057
5058         err = kvm_rdpmc(vcpu);
5059         return kvm_complete_insn_gp(vcpu, err);
5060 }
5061
5062 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5063 {
5064         return kvm_emulate_wbinvd(vcpu);
5065 }
5066
5067 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5068 {
5069         u64 new_bv = kvm_read_edx_eax(vcpu);
5070         u32 index = kvm_rcx_read(vcpu);
5071
5072         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5073                 return kvm_skip_emulated_instruction(vcpu);
5074         return 1;
5075 }
5076
5077 static int handle_apic_access(struct kvm_vcpu *vcpu)
5078 {
5079         if (likely(fasteoi)) {
5080                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5081                 int access_type, offset;
5082
5083                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5084                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5085                 /*
5086                  * Sane guest uses MOV to write EOI, with written value
5087                  * not cared. So make a short-circuit here by avoiding
5088                  * heavy instruction emulation.
5089                  */
5090                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5091                     (offset == APIC_EOI)) {
5092                         kvm_lapic_set_eoi(vcpu);
5093                         return kvm_skip_emulated_instruction(vcpu);
5094                 }
5095         }
5096         return kvm_emulate_instruction(vcpu, 0);
5097 }
5098
5099 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5100 {
5101         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5102         int vector = exit_qualification & 0xff;
5103
5104         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5105         kvm_apic_set_eoi_accelerated(vcpu, vector);
5106         return 1;
5107 }
5108
5109 static int handle_apic_write(struct kvm_vcpu *vcpu)
5110 {
5111         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5112         u32 offset = exit_qualification & 0xfff;
5113
5114         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5115         kvm_apic_write_nodecode(vcpu, offset);
5116         return 1;
5117 }
5118
5119 static int handle_task_switch(struct kvm_vcpu *vcpu)
5120 {
5121         struct vcpu_vmx *vmx = to_vmx(vcpu);
5122         unsigned long exit_qualification;
5123         bool has_error_code = false;
5124         u32 error_code = 0;
5125         u16 tss_selector;
5126         int reason, type, idt_v, idt_index;
5127
5128         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5129         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5130         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5131
5132         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5133
5134         reason = (u32)exit_qualification >> 30;
5135         if (reason == TASK_SWITCH_GATE && idt_v) {
5136                 switch (type) {
5137                 case INTR_TYPE_NMI_INTR:
5138                         vcpu->arch.nmi_injected = false;
5139                         vmx_set_nmi_mask(vcpu, true);
5140                         break;
5141                 case INTR_TYPE_EXT_INTR:
5142                 case INTR_TYPE_SOFT_INTR:
5143                         kvm_clear_interrupt_queue(vcpu);
5144                         break;
5145                 case INTR_TYPE_HARD_EXCEPTION:
5146                         if (vmx->idt_vectoring_info &
5147                             VECTORING_INFO_DELIVER_CODE_MASK) {
5148                                 has_error_code = true;
5149                                 error_code =
5150                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5151                         }
5152                         /* fall through */
5153                 case INTR_TYPE_SOFT_EXCEPTION:
5154                         kvm_clear_exception_queue(vcpu);
5155                         break;
5156                 default:
5157                         break;
5158                 }
5159         }
5160         tss_selector = exit_qualification;
5161
5162         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5163                        type != INTR_TYPE_EXT_INTR &&
5164                        type != INTR_TYPE_NMI_INTR))
5165                 WARN_ON(!skip_emulated_instruction(vcpu));
5166
5167         /*
5168          * TODO: What about debug traps on tss switch?
5169          *       Are we supposed to inject them and update dr6?
5170          */
5171         return kvm_task_switch(vcpu, tss_selector,
5172                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5173                                reason, has_error_code, error_code);
5174 }
5175
5176 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5177 {
5178         unsigned long exit_qualification;
5179         gpa_t gpa;
5180         u64 error_code;
5181
5182         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5183
5184         /*
5185          * EPT violation happened while executing iret from NMI,
5186          * "blocked by NMI" bit has to be set before next VM entry.
5187          * There are errata that may cause this bit to not be set:
5188          * AAK134, BY25.
5189          */
5190         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5191                         enable_vnmi &&
5192                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5193                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5194
5195         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5196         trace_kvm_page_fault(gpa, exit_qualification);
5197
5198         /* Is it a read fault? */
5199         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5200                      ? PFERR_USER_MASK : 0;
5201         /* Is it a write fault? */
5202         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5203                       ? PFERR_WRITE_MASK : 0;
5204         /* Is it a fetch fault? */
5205         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5206                       ? PFERR_FETCH_MASK : 0;
5207         /* ept page table entry is present? */
5208         error_code |= (exit_qualification &
5209                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5210                         EPT_VIOLATION_EXECUTABLE))
5211                       ? PFERR_PRESENT_MASK : 0;
5212
5213         error_code |= (exit_qualification & 0x100) != 0 ?
5214                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5215
5216         vcpu->arch.exit_qualification = exit_qualification;
5217         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5218 }
5219
5220 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5221 {
5222         gpa_t gpa;
5223
5224         /*
5225          * A nested guest cannot optimize MMIO vmexits, because we have an
5226          * nGPA here instead of the required GPA.
5227          */
5228         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5229         if (!is_guest_mode(vcpu) &&
5230             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5231                 trace_kvm_fast_mmio(gpa);
5232                 return kvm_skip_emulated_instruction(vcpu);
5233         }
5234
5235         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5236 }
5237
5238 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5239 {
5240         WARN_ON_ONCE(!enable_vnmi);
5241         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5242         ++vcpu->stat.nmi_window_exits;
5243         kvm_make_request(KVM_REQ_EVENT, vcpu);
5244
5245         return 1;
5246 }
5247
5248 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5249 {
5250         struct vcpu_vmx *vmx = to_vmx(vcpu);
5251         bool intr_window_requested;
5252         unsigned count = 130;
5253
5254         /*
5255          * We should never reach the point where we are emulating L2
5256          * due to invalid guest state as that means we incorrectly
5257          * allowed a nested VMEntry with an invalid vmcs12.
5258          */
5259         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5260
5261         intr_window_requested = exec_controls_get(vmx) &
5262                                 CPU_BASED_INTR_WINDOW_EXITING;
5263
5264         while (vmx->emulation_required && count-- != 0) {
5265                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5266                         return handle_interrupt_window(&vmx->vcpu);
5267
5268                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5269                         return 1;
5270
5271                 if (!kvm_emulate_instruction(vcpu, 0))
5272                         return 0;
5273
5274                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5275                     vcpu->arch.exception.pending) {
5276                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5277                         vcpu->run->internal.suberror =
5278                                                 KVM_INTERNAL_ERROR_EMULATION;
5279                         vcpu->run->internal.ndata = 0;
5280                         return 0;
5281                 }
5282
5283                 if (vcpu->arch.halt_request) {
5284                         vcpu->arch.halt_request = 0;
5285                         return kvm_vcpu_halt(vcpu);
5286                 }
5287
5288                 /*
5289                  * Note, return 1 and not 0, vcpu_run() is responsible for
5290                  * morphing the pending signal into the proper return code.
5291                  */
5292                 if (signal_pending(current))
5293                         return 1;
5294
5295                 if (need_resched())
5296                         schedule();
5297         }
5298
5299         return 1;
5300 }
5301
5302 static void grow_ple_window(struct kvm_vcpu *vcpu)
5303 {
5304         struct vcpu_vmx *vmx = to_vmx(vcpu);
5305         unsigned int old = vmx->ple_window;
5306
5307         vmx->ple_window = __grow_ple_window(old, ple_window,
5308                                             ple_window_grow,
5309                                             ple_window_max);
5310
5311         if (vmx->ple_window != old) {
5312                 vmx->ple_window_dirty = true;
5313                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5314                                             vmx->ple_window, old);
5315         }
5316 }
5317
5318 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5319 {
5320         struct vcpu_vmx *vmx = to_vmx(vcpu);
5321         unsigned int old = vmx->ple_window;
5322
5323         vmx->ple_window = __shrink_ple_window(old, ple_window,
5324                                               ple_window_shrink,
5325                                               ple_window);
5326
5327         if (vmx->ple_window != old) {
5328                 vmx->ple_window_dirty = true;
5329                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5330                                             vmx->ple_window, old);
5331         }
5332 }
5333
5334 /*
5335  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5336  */
5337 static void wakeup_handler(void)
5338 {
5339         struct kvm_vcpu *vcpu;
5340         int cpu = smp_processor_id();
5341
5342         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5343         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5344                         blocked_vcpu_list) {
5345                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5346
5347                 if (pi_test_on(pi_desc) == 1)
5348                         kvm_vcpu_kick(vcpu);
5349         }
5350         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5351 }
5352
5353 static void vmx_enable_tdp(void)
5354 {
5355         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5356                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5357                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5358                 0ull, VMX_EPT_EXECUTABLE_MASK,
5359                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5360                 VMX_EPT_RWX_MASK, 0ull);
5361
5362         ept_set_mmio_spte_mask();
5363 }
5364
5365 /*
5366  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5367  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5368  */
5369 static int handle_pause(struct kvm_vcpu *vcpu)
5370 {
5371         if (!kvm_pause_in_guest(vcpu->kvm))
5372                 grow_ple_window(vcpu);
5373
5374         /*
5375          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5376          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5377          * never set PAUSE_EXITING and just set PLE if supported,
5378          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5379          */
5380         kvm_vcpu_on_spin(vcpu, true);
5381         return kvm_skip_emulated_instruction(vcpu);
5382 }
5383
5384 static int handle_nop(struct kvm_vcpu *vcpu)
5385 {
5386         return kvm_skip_emulated_instruction(vcpu);
5387 }
5388
5389 static int handle_mwait(struct kvm_vcpu *vcpu)
5390 {
5391         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5392         return handle_nop(vcpu);
5393 }
5394
5395 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5396 {
5397         kvm_queue_exception(vcpu, UD_VECTOR);
5398         return 1;
5399 }
5400
5401 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5402 {
5403         return 1;
5404 }
5405
5406 static int handle_monitor(struct kvm_vcpu *vcpu)
5407 {
5408         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5409         return handle_nop(vcpu);
5410 }
5411
5412 static int handle_invpcid(struct kvm_vcpu *vcpu)
5413 {
5414         u32 vmx_instruction_info;
5415         unsigned long type;
5416         bool pcid_enabled;
5417         gva_t gva;
5418         struct x86_exception e;
5419         unsigned i;
5420         unsigned long roots_to_free = 0;
5421         struct {
5422                 u64 pcid;
5423                 u64 gla;
5424         } operand;
5425
5426         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5427                 kvm_queue_exception(vcpu, UD_VECTOR);
5428                 return 1;
5429         }
5430
5431         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5432         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5433
5434         if (type > 3) {
5435                 kvm_inject_gp(vcpu, 0);
5436                 return 1;
5437         }
5438
5439         /* According to the Intel instruction reference, the memory operand
5440          * is read even if it isn't needed (e.g., for type==all)
5441          */
5442         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5443                                 vmx_instruction_info, false,
5444                                 sizeof(operand), &gva))
5445                 return 1;
5446
5447         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5448                 kvm_inject_emulated_page_fault(vcpu, &e);
5449                 return 1;
5450         }
5451
5452         if (operand.pcid >> 12 != 0) {
5453                 kvm_inject_gp(vcpu, 0);
5454                 return 1;
5455         }
5456
5457         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5458
5459         switch (type) {
5460         case INVPCID_TYPE_INDIV_ADDR:
5461                 if ((!pcid_enabled && (operand.pcid != 0)) ||
5462                     is_noncanonical_address(operand.gla, vcpu)) {
5463                         kvm_inject_gp(vcpu, 0);
5464                         return 1;
5465                 }
5466                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5467                 return kvm_skip_emulated_instruction(vcpu);
5468
5469         case INVPCID_TYPE_SINGLE_CTXT:
5470                 if (!pcid_enabled && (operand.pcid != 0)) {
5471                         kvm_inject_gp(vcpu, 0);
5472                         return 1;
5473                 }
5474
5475                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5476                         kvm_mmu_sync_roots(vcpu);
5477                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
5478                 }
5479
5480                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5481                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
5482                             == operand.pcid)
5483                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5484
5485                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5486                 /*
5487                  * If neither the current cr3 nor any of the prev_roots use the
5488                  * given PCID, then nothing needs to be done here because a
5489                  * resync will happen anyway before switching to any other CR3.
5490                  */
5491
5492                 return kvm_skip_emulated_instruction(vcpu);
5493
5494         case INVPCID_TYPE_ALL_NON_GLOBAL:
5495                 /*
5496                  * Currently, KVM doesn't mark global entries in the shadow
5497                  * page tables, so a non-global flush just degenerates to a
5498                  * global flush. If needed, we could optimize this later by
5499                  * keeping track of global entries in shadow page tables.
5500                  */
5501
5502                 /* fall-through */
5503         case INVPCID_TYPE_ALL_INCL_GLOBAL:
5504                 kvm_mmu_unload(vcpu);
5505                 return kvm_skip_emulated_instruction(vcpu);
5506
5507         default:
5508                 BUG(); /* We have already checked above that type <= 3 */
5509         }
5510 }
5511
5512 static int handle_pml_full(struct kvm_vcpu *vcpu)
5513 {
5514         unsigned long exit_qualification;
5515
5516         trace_kvm_pml_full(vcpu->vcpu_id);
5517
5518         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5519
5520         /*
5521          * PML buffer FULL happened while executing iret from NMI,
5522          * "blocked by NMI" bit has to be set before next VM entry.
5523          */
5524         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5525                         enable_vnmi &&
5526                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5527                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5528                                 GUEST_INTR_STATE_NMI);
5529
5530         /*
5531          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5532          * here.., and there's no userspace involvement needed for PML.
5533          */
5534         return 1;
5535 }
5536
5537 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5538 {
5539         struct vcpu_vmx *vmx = to_vmx(vcpu);
5540
5541         if (!vmx->req_immediate_exit &&
5542             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5543                 kvm_lapic_expired_hv_timer(vcpu);
5544
5545         return 1;
5546 }
5547
5548 /*
5549  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5550  * are overwritten by nested_vmx_setup() when nested=1.
5551  */
5552 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5553 {
5554         kvm_queue_exception(vcpu, UD_VECTOR);
5555         return 1;
5556 }
5557
5558 static int handle_encls(struct kvm_vcpu *vcpu)
5559 {
5560         /*
5561          * SGX virtualization is not yet supported.  There is no software
5562          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5563          * to prevent the guest from executing ENCLS.
5564          */
5565         kvm_queue_exception(vcpu, UD_VECTOR);
5566         return 1;
5567 }
5568
5569 /*
5570  * The exit handlers return 1 if the exit was handled fully and guest execution
5571  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5572  * to be done to userspace and return 0.
5573  */
5574 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5575         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5576         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5577         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5578         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5579         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5580         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5581         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5582         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5583         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5584         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5585         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5586         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5587         [EXIT_REASON_INVD]                    = handle_invd,
5588         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5589         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5590         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5591         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5592         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5593         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5594         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5595         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5596         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5597         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5598         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5599         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5600         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5601         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5602         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5603         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5604         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5605         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5606         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5607         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5608         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5609         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5610         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5611         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5612         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5613         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
5614         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5615         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
5616         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5617         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5618         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
5619         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
5620         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5621         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5622         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5623         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5624         [EXIT_REASON_ENCLS]                   = handle_encls,
5625 };
5626
5627 static const int kvm_vmx_max_exit_handlers =
5628         ARRAY_SIZE(kvm_vmx_exit_handlers);
5629
5630 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5631 {
5632         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5633         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5634 }
5635
5636 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5637 {
5638         if (vmx->pml_pg) {
5639                 __free_page(vmx->pml_pg);
5640                 vmx->pml_pg = NULL;
5641         }
5642 }
5643
5644 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5645 {
5646         struct vcpu_vmx *vmx = to_vmx(vcpu);
5647         u64 *pml_buf;
5648         u16 pml_idx;
5649
5650         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5651
5652         /* Do nothing if PML buffer is empty */
5653         if (pml_idx == (PML_ENTITY_NUM - 1))
5654                 return;
5655
5656         /* PML index always points to next available PML buffer entity */
5657         if (pml_idx >= PML_ENTITY_NUM)
5658                 pml_idx = 0;
5659         else
5660                 pml_idx++;
5661
5662         pml_buf = page_address(vmx->pml_pg);
5663         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5664                 u64 gpa;
5665
5666                 gpa = pml_buf[pml_idx];
5667                 WARN_ON(gpa & (PAGE_SIZE - 1));
5668                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5669         }
5670
5671         /* reset PML index */
5672         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5673 }
5674
5675 /*
5676  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5677  * Called before reporting dirty_bitmap to userspace.
5678  */
5679 static void kvm_flush_pml_buffers(struct kvm *kvm)
5680 {
5681         int i;
5682         struct kvm_vcpu *vcpu;
5683         /*
5684          * We only need to kick vcpu out of guest mode here, as PML buffer
5685          * is flushed at beginning of all VMEXITs, and it's obvious that only
5686          * vcpus running in guest are possible to have unflushed GPAs in PML
5687          * buffer.
5688          */
5689         kvm_for_each_vcpu(i, vcpu, kvm)
5690                 kvm_vcpu_kick(vcpu);
5691 }
5692
5693 static void vmx_dump_sel(char *name, uint32_t sel)
5694 {
5695         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5696                name, vmcs_read16(sel),
5697                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5698                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5699                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5700 }
5701
5702 static void vmx_dump_dtsel(char *name, uint32_t limit)
5703 {
5704         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5705                name, vmcs_read32(limit),
5706                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5707 }
5708
5709 void dump_vmcs(void)
5710 {
5711         u32 vmentry_ctl, vmexit_ctl;
5712         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5713         unsigned long cr4;
5714         u64 efer;
5715         int i, n;
5716
5717         if (!dump_invalid_vmcs) {
5718                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5719                 return;
5720         }
5721
5722         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5723         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5724         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5725         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5726         cr4 = vmcs_readl(GUEST_CR4);
5727         efer = vmcs_read64(GUEST_IA32_EFER);
5728         secondary_exec_control = 0;
5729         if (cpu_has_secondary_exec_ctrls())
5730                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5731
5732         pr_err("*** Guest State ***\n");
5733         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5734                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5735                vmcs_readl(CR0_GUEST_HOST_MASK));
5736         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5737                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5738         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5739         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5740             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5741         {
5742                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5743                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5744                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5745                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5746         }
5747         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5748                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5749         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5750                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5751         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5752                vmcs_readl(GUEST_SYSENTER_ESP),
5753                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5754         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5755         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5756         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5757         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5758         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5759         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5760         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5761         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5762         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5763         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5764         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5765             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5766                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
5767                        efer, vmcs_read64(GUEST_IA32_PAT));
5768         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5769                vmcs_read64(GUEST_IA32_DEBUGCTL),
5770                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5771         if (cpu_has_load_perf_global_ctrl() &&
5772             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5773                 pr_err("PerfGlobCtl = 0x%016llx\n",
5774                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5775         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5776                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5777         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5778                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5779                vmcs_read32(GUEST_ACTIVITY_STATE));
5780         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5781                 pr_err("InterruptStatus = %04x\n",
5782                        vmcs_read16(GUEST_INTR_STATUS));
5783
5784         pr_err("*** Host State ***\n");
5785         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5786                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5787         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5788                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5789                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5790                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5791                vmcs_read16(HOST_TR_SELECTOR));
5792         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5793                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5794                vmcs_readl(HOST_TR_BASE));
5795         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5796                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5797         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5798                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5799                vmcs_readl(HOST_CR4));
5800         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5801                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5802                vmcs_read32(HOST_IA32_SYSENTER_CS),
5803                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5804         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5805                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
5806                        vmcs_read64(HOST_IA32_EFER),
5807                        vmcs_read64(HOST_IA32_PAT));
5808         if (cpu_has_load_perf_global_ctrl() &&
5809             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5810                 pr_err("PerfGlobCtl = 0x%016llx\n",
5811                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5812
5813         pr_err("*** Control State ***\n");
5814         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5815                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5816         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5817         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5818                vmcs_read32(EXCEPTION_BITMAP),
5819                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5820                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5821         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5822                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5823                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5824                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5825         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5826                vmcs_read32(VM_EXIT_INTR_INFO),
5827                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5828                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5829         pr_err("        reason=%08x qualification=%016lx\n",
5830                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5831         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5832                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5833                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5834         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5835         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5836                 pr_err("TSC Multiplier = 0x%016llx\n",
5837                        vmcs_read64(TSC_MULTIPLIER));
5838         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5839                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5840                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5841                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5842                 }
5843                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5844                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5845                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5846                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5847         }
5848         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5849                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5850         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5851                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5852         n = vmcs_read32(CR3_TARGET_COUNT);
5853         for (i = 0; i + 1 < n; i += 4)
5854                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5855                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5856                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5857         if (i < n)
5858                 pr_err("CR3 target%u=%016lx\n",
5859                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5860         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5861                 pr_err("PLE Gap=%08x Window=%08x\n",
5862                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5863         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5864                 pr_err("Virtual processor ID = 0x%04x\n",
5865                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5866 }
5867
5868 /*
5869  * The guest has exited.  See if we can fix it or if we need userspace
5870  * assistance.
5871  */
5872 static int vmx_handle_exit(struct kvm_vcpu *vcpu,
5873         enum exit_fastpath_completion exit_fastpath)
5874 {
5875         struct vcpu_vmx *vmx = to_vmx(vcpu);
5876         u32 exit_reason = vmx->exit_reason;
5877         u32 vectoring_info = vmx->idt_vectoring_info;
5878
5879         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5880
5881         /*
5882          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5883          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5884          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5885          * mode as if vcpus is in root mode, the PML buffer must has been
5886          * flushed already.
5887          */
5888         if (enable_pml)
5889                 vmx_flush_pml_buffer(vcpu);
5890
5891         /* If guest state is invalid, start emulating */
5892         if (vmx->emulation_required)
5893                 return handle_invalid_guest_state(vcpu);
5894
5895         if (is_guest_mode(vcpu)) {
5896                 /*
5897                  * The host physical addresses of some pages of guest memory
5898                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5899                  * Page). The CPU may write to these pages via their host
5900                  * physical address while L2 is running, bypassing any
5901                  * address-translation-based dirty tracking (e.g. EPT write
5902                  * protection).
5903                  *
5904                  * Mark them dirty on every exit from L2 to prevent them from
5905                  * getting out of sync with dirty tracking.
5906                  */
5907                 nested_mark_vmcs12_pages_dirty(vcpu);
5908
5909                 if (nested_vmx_reflect_vmexit(vcpu))
5910                         return 1;
5911         }
5912
5913         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5914                 dump_vmcs();
5915                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5916                 vcpu->run->fail_entry.hardware_entry_failure_reason
5917                         = exit_reason;
5918                 return 0;
5919         }
5920
5921         if (unlikely(vmx->fail)) {
5922                 dump_vmcs();
5923                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5924                 vcpu->run->fail_entry.hardware_entry_failure_reason
5925                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5926                 return 0;
5927         }
5928
5929         /*
5930          * Note:
5931          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5932          * delivery event since it indicates guest is accessing MMIO.
5933          * The vm-exit can be triggered again after return to guest that
5934          * will cause infinite loop.
5935          */
5936         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5937                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5938                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5939                         exit_reason != EXIT_REASON_PML_FULL &&
5940                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
5941                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5942                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5943                 vcpu->run->internal.ndata = 3;
5944                 vcpu->run->internal.data[0] = vectoring_info;
5945                 vcpu->run->internal.data[1] = exit_reason;
5946                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5947                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5948                         vcpu->run->internal.ndata++;
5949                         vcpu->run->internal.data[3] =
5950                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5951                 }
5952                 return 0;
5953         }
5954
5955         if (unlikely(!enable_vnmi &&
5956                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5957                 if (vmx_interrupt_allowed(vcpu)) {
5958                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5959                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5960                            vcpu->arch.nmi_pending) {
5961                         /*
5962                          * This CPU don't support us in finding the end of an
5963                          * NMI-blocked window if the guest runs with IRQs
5964                          * disabled. So we pull the trigger after 1 s of
5965                          * futile waiting, but inform the user about this.
5966                          */
5967                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5968                                "state on VCPU %d after 1 s timeout\n",
5969                                __func__, vcpu->vcpu_id);
5970                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5971                 }
5972         }
5973
5974         if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5975                 kvm_skip_emulated_instruction(vcpu);
5976                 return 1;
5977         }
5978
5979         if (exit_reason >= kvm_vmx_max_exit_handlers)
5980                 goto unexpected_vmexit;
5981 #ifdef CONFIG_RETPOLINE
5982         if (exit_reason == EXIT_REASON_MSR_WRITE)
5983                 return kvm_emulate_wrmsr(vcpu);
5984         else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5985                 return handle_preemption_timer(vcpu);
5986         else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
5987                 return handle_interrupt_window(vcpu);
5988         else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5989                 return handle_external_interrupt(vcpu);
5990         else if (exit_reason == EXIT_REASON_HLT)
5991                 return kvm_emulate_halt(vcpu);
5992         else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5993                 return handle_ept_misconfig(vcpu);
5994 #endif
5995
5996         exit_reason = array_index_nospec(exit_reason,
5997                                          kvm_vmx_max_exit_handlers);
5998         if (!kvm_vmx_exit_handlers[exit_reason])
5999                 goto unexpected_vmexit;
6000
6001         return kvm_vmx_exit_handlers[exit_reason](vcpu);
6002
6003 unexpected_vmexit:
6004         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
6005         dump_vmcs();
6006         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6007         vcpu->run->internal.suberror =
6008                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6009         vcpu->run->internal.ndata = 1;
6010         vcpu->run->internal.data[0] = exit_reason;
6011         return 0;
6012 }
6013
6014 /*
6015  * Software based L1D cache flush which is used when microcode providing
6016  * the cache control MSR is not loaded.
6017  *
6018  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6019  * flush it is required to read in 64 KiB because the replacement algorithm
6020  * is not exactly LRU. This could be sized at runtime via topology
6021  * information but as all relevant affected CPUs have 32KiB L1D cache size
6022  * there is no point in doing so.
6023  */
6024 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6025 {
6026         int size = PAGE_SIZE << L1D_CACHE_ORDER;
6027
6028         /*
6029          * This code is only executed when the the flush mode is 'cond' or
6030          * 'always'
6031          */
6032         if (static_branch_likely(&vmx_l1d_flush_cond)) {
6033                 bool flush_l1d;
6034
6035                 /*
6036                  * Clear the per-vcpu flush bit, it gets set again
6037                  * either from vcpu_run() or from one of the unsafe
6038                  * VMEXIT handlers.
6039                  */
6040                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6041                 vcpu->arch.l1tf_flush_l1d = false;
6042
6043                 /*
6044                  * Clear the per-cpu flush bit, it gets set again from
6045                  * the interrupt handlers.
6046                  */
6047                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6048                 kvm_clear_cpu_l1tf_flush_l1d();
6049
6050                 if (!flush_l1d)
6051                         return;
6052         }
6053
6054         vcpu->stat.l1d_flush++;
6055
6056         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6057                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6058                 return;
6059         }
6060
6061         asm volatile(
6062                 /* First ensure the pages are in the TLB */
6063                 "xorl   %%eax, %%eax\n"
6064                 ".Lpopulate_tlb:\n\t"
6065                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6066                 "addl   $4096, %%eax\n\t"
6067                 "cmpl   %%eax, %[size]\n\t"
6068                 "jne    .Lpopulate_tlb\n\t"
6069                 "xorl   %%eax, %%eax\n\t"
6070                 "cpuid\n\t"
6071                 /* Now fill the cache */
6072                 "xorl   %%eax, %%eax\n"
6073                 ".Lfill_cache:\n"
6074                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6075                 "addl   $64, %%eax\n\t"
6076                 "cmpl   %%eax, %[size]\n\t"
6077                 "jne    .Lfill_cache\n\t"
6078                 "lfence\n"
6079                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6080                     [size] "r" (size)
6081                 : "eax", "ebx", "ecx", "edx");
6082 }
6083
6084 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6085 {
6086         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6087         int tpr_threshold;
6088
6089         if (is_guest_mode(vcpu) &&
6090                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6091                 return;
6092
6093         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6094         if (is_guest_mode(vcpu))
6095                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6096         else
6097                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6098 }
6099
6100 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6101 {
6102         struct vcpu_vmx *vmx = to_vmx(vcpu);
6103         u32 sec_exec_control;
6104
6105         if (!lapic_in_kernel(vcpu))
6106                 return;
6107
6108         if (!flexpriority_enabled &&
6109             !cpu_has_vmx_virtualize_x2apic_mode())
6110                 return;
6111
6112         /* Postpone execution until vmcs01 is the current VMCS. */
6113         if (is_guest_mode(vcpu)) {
6114                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6115                 return;
6116         }
6117
6118         sec_exec_control = secondary_exec_controls_get(vmx);
6119         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6120                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6121
6122         switch (kvm_get_apic_mode(vcpu)) {
6123         case LAPIC_MODE_INVALID:
6124                 WARN_ONCE(true, "Invalid local APIC state");
6125         case LAPIC_MODE_DISABLED:
6126                 break;
6127         case LAPIC_MODE_XAPIC:
6128                 if (flexpriority_enabled) {
6129                         sec_exec_control |=
6130                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6131                         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6132
6133                         /*
6134                          * Flush the TLB, reloading the APIC access page will
6135                          * only do so if its physical address has changed, but
6136                          * the guest may have inserted a non-APIC mapping into
6137                          * the TLB while the APIC access page was disabled.
6138                          */
6139                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6140                 }
6141                 break;
6142         case LAPIC_MODE_X2APIC:
6143                 if (cpu_has_vmx_virtualize_x2apic_mode())
6144                         sec_exec_control |=
6145                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6146                 break;
6147         }
6148         secondary_exec_controls_set(vmx, sec_exec_control);
6149
6150         vmx_update_msr_bitmap(vcpu);
6151 }
6152
6153 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6154 {
6155         struct page *page;
6156
6157         /* Defer reload until vmcs01 is the current VMCS. */
6158         if (is_guest_mode(vcpu)) {
6159                 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6160                 return;
6161         }
6162
6163         if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6164             SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6165                 return;
6166
6167         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6168         if (is_error_page(page))
6169                 return;
6170
6171         vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6172         vmx_flush_tlb_current(vcpu);
6173
6174         /*
6175          * Do not pin apic access page in memory, the MMU notifier
6176          * will call us again if it is migrated or swapped out.
6177          */
6178         put_page(page);
6179 }
6180
6181 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6182 {
6183         u16 status;
6184         u8 old;
6185
6186         if (max_isr == -1)
6187                 max_isr = 0;
6188
6189         status = vmcs_read16(GUEST_INTR_STATUS);
6190         old = status >> 8;
6191         if (max_isr != old) {
6192                 status &= 0xff;
6193                 status |= max_isr << 8;
6194                 vmcs_write16(GUEST_INTR_STATUS, status);
6195         }
6196 }
6197
6198 static void vmx_set_rvi(int vector)
6199 {
6200         u16 status;
6201         u8 old;
6202
6203         if (vector == -1)
6204                 vector = 0;
6205
6206         status = vmcs_read16(GUEST_INTR_STATUS);
6207         old = (u8)status & 0xff;
6208         if ((u8)vector != old) {
6209                 status &= ~0xff;
6210                 status |= (u8)vector;
6211                 vmcs_write16(GUEST_INTR_STATUS, status);
6212         }
6213 }
6214
6215 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6216 {
6217         /*
6218          * When running L2, updating RVI is only relevant when
6219          * vmcs12 virtual-interrupt-delivery enabled.
6220          * However, it can be enabled only when L1 also
6221          * intercepts external-interrupts and in that case
6222          * we should not update vmcs02 RVI but instead intercept
6223          * interrupt. Therefore, do nothing when running L2.
6224          */
6225         if (!is_guest_mode(vcpu))
6226                 vmx_set_rvi(max_irr);
6227 }
6228
6229 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6230 {
6231         struct vcpu_vmx *vmx = to_vmx(vcpu);
6232         int max_irr;
6233         bool max_irr_updated;
6234
6235         WARN_ON(!vcpu->arch.apicv_active);
6236         if (pi_test_on(&vmx->pi_desc)) {
6237                 pi_clear_on(&vmx->pi_desc);
6238                 /*
6239                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6240                  * But on x86 this is just a compiler barrier anyway.
6241                  */
6242                 smp_mb__after_atomic();
6243                 max_irr_updated =
6244                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6245
6246                 /*
6247                  * If we are running L2 and L1 has a new pending interrupt
6248                  * which can be injected, we should re-evaluate
6249                  * what should be done with this new L1 interrupt.
6250                  * If L1 intercepts external-interrupts, we should
6251                  * exit from L2 to L1. Otherwise, interrupt should be
6252                  * delivered directly to L2.
6253                  */
6254                 if (is_guest_mode(vcpu) && max_irr_updated) {
6255                         if (nested_exit_on_intr(vcpu))
6256                                 kvm_vcpu_exiting_guest_mode(vcpu);
6257                         else
6258                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6259                 }
6260         } else {
6261                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6262         }
6263         vmx_hwapic_irr_update(vcpu, max_irr);
6264         return max_irr;
6265 }
6266
6267 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6268 {
6269         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6270
6271         return pi_test_on(pi_desc) ||
6272                 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6273 }
6274
6275 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6276 {
6277         if (!kvm_vcpu_apicv_active(vcpu))
6278                 return;
6279
6280         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6281         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6282         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6283         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6284 }
6285
6286 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6287 {
6288         struct vcpu_vmx *vmx = to_vmx(vcpu);
6289
6290         pi_clear_on(&vmx->pi_desc);
6291         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6292 }
6293
6294 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6295 {
6296         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6297
6298         /* if exit due to PF check for async PF */
6299         if (is_page_fault(vmx->exit_intr_info)) {
6300                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6301         /* Handle machine checks before interrupts are enabled */
6302         } else if (is_machine_check(vmx->exit_intr_info)) {
6303                 kvm_machine_check();
6304         /* We need to handle NMIs before interrupts are enabled */
6305         } else if (is_nmi(vmx->exit_intr_info)) {
6306                 kvm_before_interrupt(&vmx->vcpu);
6307                 asm("int $2");
6308                 kvm_after_interrupt(&vmx->vcpu);
6309         }
6310 }
6311
6312 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6313 {
6314         unsigned int vector;
6315         unsigned long entry;
6316 #ifdef CONFIG_X86_64
6317         unsigned long tmp;
6318 #endif
6319         gate_desc *desc;
6320         u32 intr_info;
6321
6322         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6323         if (WARN_ONCE(!is_external_intr(intr_info),
6324             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6325                 return;
6326
6327         vector = intr_info & INTR_INFO_VECTOR_MASK;
6328         desc = (gate_desc *)host_idt_base + vector;
6329         entry = gate_offset(desc);
6330
6331         kvm_before_interrupt(vcpu);
6332
6333         asm volatile(
6334 #ifdef CONFIG_X86_64
6335                 "mov %%" _ASM_SP ", %[sp]\n\t"
6336                 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6337                 "push $%c[ss]\n\t"
6338                 "push %[sp]\n\t"
6339 #endif
6340                 "pushf\n\t"
6341                 __ASM_SIZE(push) " $%c[cs]\n\t"
6342                 CALL_NOSPEC
6343                 :
6344 #ifdef CONFIG_X86_64
6345                 [sp]"=&r"(tmp),
6346 #endif
6347                 ASM_CALL_CONSTRAINT
6348                 :
6349                 [thunk_target]"r"(entry),
6350                 [ss]"i"(__KERNEL_DS),
6351                 [cs]"i"(__KERNEL_CS)
6352         );
6353
6354         kvm_after_interrupt(vcpu);
6355 }
6356 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6357
6358 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6359         enum exit_fastpath_completion *exit_fastpath)
6360 {
6361         struct vcpu_vmx *vmx = to_vmx(vcpu);
6362
6363         if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6364                 handle_external_interrupt_irqoff(vcpu);
6365         else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6366                 handle_exception_nmi_irqoff(vmx);
6367         else if (!is_guest_mode(vcpu) &&
6368                 vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6369                 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
6370 }
6371
6372 static bool vmx_has_emulated_msr(int index)
6373 {
6374         switch (index) {
6375         case MSR_IA32_SMBASE:
6376                 /*
6377                  * We cannot do SMM unless we can run the guest in big
6378                  * real mode.
6379                  */
6380                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6381         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6382                 return nested;
6383         case MSR_AMD64_VIRT_SPEC_CTRL:
6384                 /* This is AMD only.  */
6385                 return false;
6386         default:
6387                 return true;
6388         }
6389 }
6390
6391 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6392 {
6393         u32 exit_intr_info;
6394         bool unblock_nmi;
6395         u8 vector;
6396         bool idtv_info_valid;
6397
6398         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6399
6400         if (enable_vnmi) {
6401                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6402                         return;
6403                 /*
6404                  * Can't use vmx->exit_intr_info since we're not sure what
6405                  * the exit reason is.
6406                  */
6407                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6408                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6409                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6410                 /*
6411                  * SDM 3: 27.7.1.2 (September 2008)
6412                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6413                  * a guest IRET fault.
6414                  * SDM 3: 23.2.2 (September 2008)
6415                  * Bit 12 is undefined in any of the following cases:
6416                  *  If the VM exit sets the valid bit in the IDT-vectoring
6417                  *   information field.
6418                  *  If the VM exit is due to a double fault.
6419                  */
6420                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6421                     vector != DF_VECTOR && !idtv_info_valid)
6422                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6423                                       GUEST_INTR_STATE_NMI);
6424                 else
6425                         vmx->loaded_vmcs->nmi_known_unmasked =
6426                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6427                                   & GUEST_INTR_STATE_NMI);
6428         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6429                 vmx->loaded_vmcs->vnmi_blocked_time +=
6430                         ktime_to_ns(ktime_sub(ktime_get(),
6431                                               vmx->loaded_vmcs->entry_time));
6432 }
6433
6434 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6435                                       u32 idt_vectoring_info,
6436                                       int instr_len_field,
6437                                       int error_code_field)
6438 {
6439         u8 vector;
6440         int type;
6441         bool idtv_info_valid;
6442
6443         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6444
6445         vcpu->arch.nmi_injected = false;
6446         kvm_clear_exception_queue(vcpu);
6447         kvm_clear_interrupt_queue(vcpu);
6448
6449         if (!idtv_info_valid)
6450                 return;
6451
6452         kvm_make_request(KVM_REQ_EVENT, vcpu);
6453
6454         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6455         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6456
6457         switch (type) {
6458         case INTR_TYPE_NMI_INTR:
6459                 vcpu->arch.nmi_injected = true;
6460                 /*
6461                  * SDM 3: 27.7.1.2 (September 2008)
6462                  * Clear bit "block by NMI" before VM entry if a NMI
6463                  * delivery faulted.
6464                  */
6465                 vmx_set_nmi_mask(vcpu, false);
6466                 break;
6467         case INTR_TYPE_SOFT_EXCEPTION:
6468                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6469                 /* fall through */
6470         case INTR_TYPE_HARD_EXCEPTION:
6471                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6472                         u32 err = vmcs_read32(error_code_field);
6473                         kvm_requeue_exception_e(vcpu, vector, err);
6474                 } else
6475                         kvm_requeue_exception(vcpu, vector);
6476                 break;
6477         case INTR_TYPE_SOFT_INTR:
6478                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6479                 /* fall through */
6480         case INTR_TYPE_EXT_INTR:
6481                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6482                 break;
6483         default:
6484                 break;
6485         }
6486 }
6487
6488 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6489 {
6490         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6491                                   VM_EXIT_INSTRUCTION_LEN,
6492                                   IDT_VECTORING_ERROR_CODE);
6493 }
6494
6495 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6496 {
6497         __vmx_complete_interrupts(vcpu,
6498                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6499                                   VM_ENTRY_INSTRUCTION_LEN,
6500                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6501
6502         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6503 }
6504
6505 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6506 {
6507         int i, nr_msrs;
6508         struct perf_guest_switch_msr *msrs;
6509
6510         msrs = perf_guest_get_msrs(&nr_msrs);
6511
6512         if (!msrs)
6513                 return;
6514
6515         for (i = 0; i < nr_msrs; i++)
6516                 if (msrs[i].host == msrs[i].guest)
6517                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6518                 else
6519                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6520                                         msrs[i].host, false);
6521 }
6522
6523 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6524 {
6525         u32 host_umwait_control;
6526
6527         if (!vmx_has_waitpkg(vmx))
6528                 return;
6529
6530         host_umwait_control = get_umwait_control_msr();
6531
6532         if (vmx->msr_ia32_umwait_control != host_umwait_control)
6533                 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6534                         vmx->msr_ia32_umwait_control,
6535                         host_umwait_control, false);
6536         else
6537                 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6538 }
6539
6540 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6541 {
6542         struct vcpu_vmx *vmx = to_vmx(vcpu);
6543         u64 tscl;
6544         u32 delta_tsc;
6545
6546         if (vmx->req_immediate_exit) {
6547                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6548                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6549         } else if (vmx->hv_deadline_tsc != -1) {
6550                 tscl = rdtsc();
6551                 if (vmx->hv_deadline_tsc > tscl)
6552                         /* set_hv_timer ensures the delta fits in 32-bits */
6553                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6554                                 cpu_preemption_timer_multi);
6555                 else
6556                         delta_tsc = 0;
6557
6558                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6559                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6560         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6561                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6562                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6563         }
6564 }
6565
6566 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6567 {
6568         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6569                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6570                 vmcs_writel(HOST_RSP, host_rsp);
6571         }
6572 }
6573
6574 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6575
6576 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6577 {
6578         struct vcpu_vmx *vmx = to_vmx(vcpu);
6579         unsigned long cr3, cr4;
6580
6581         /* Record the guest's net vcpu time for enforced NMI injections. */
6582         if (unlikely(!enable_vnmi &&
6583                      vmx->loaded_vmcs->soft_vnmi_blocked))
6584                 vmx->loaded_vmcs->entry_time = ktime_get();
6585
6586         /* Don't enter VMX if guest state is invalid, let the exit handler
6587            start emulation until we arrive back to a valid state */
6588         if (vmx->emulation_required)
6589                 return;
6590
6591         if (vmx->ple_window_dirty) {
6592                 vmx->ple_window_dirty = false;
6593                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6594         }
6595
6596         /*
6597          * We did this in prepare_switch_to_guest, because it needs to
6598          * be within srcu_read_lock.
6599          */
6600         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6601
6602         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6603                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6604         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6605                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6606
6607         cr3 = __get_current_cr3_fast();
6608         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6609                 vmcs_writel(HOST_CR3, cr3);
6610                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6611         }
6612
6613         cr4 = cr4_read_shadow();
6614         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6615                 vmcs_writel(HOST_CR4, cr4);
6616                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6617         }
6618
6619         /* When single-stepping over STI and MOV SS, we must clear the
6620          * corresponding interruptibility bits in the guest state. Otherwise
6621          * vmentry fails as it then expects bit 14 (BS) in pending debug
6622          * exceptions being set, but that's not correct for the guest debugging
6623          * case. */
6624         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6625                 vmx_set_interrupt_shadow(vcpu, 0);
6626
6627         kvm_load_guest_xsave_state(vcpu);
6628
6629         if (static_cpu_has(X86_FEATURE_PKU) &&
6630             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6631             vcpu->arch.pkru != vmx->host_pkru)
6632                 __write_pkru(vcpu->arch.pkru);
6633
6634         pt_guest_enter(vmx);
6635
6636         if (vcpu_to_pmu(vcpu)->version)
6637                 atomic_switch_perf_msrs(vmx);
6638         atomic_switch_umwait_control_msr(vmx);
6639
6640         if (enable_preemption_timer)
6641                 vmx_update_hv_timer(vcpu);
6642
6643         if (lapic_in_kernel(vcpu) &&
6644                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6645                 kvm_wait_lapic_expire(vcpu);
6646
6647         /*
6648          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6649          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6650          * is no need to worry about the conditional branch over the wrmsr
6651          * being speculatively taken.
6652          */
6653         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6654
6655         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6656         if (static_branch_unlikely(&vmx_l1d_should_flush))
6657                 vmx_l1d_flush(vcpu);
6658         else if (static_branch_unlikely(&mds_user_clear))
6659                 mds_clear_cpu_buffers();
6660
6661         if (vcpu->arch.cr2 != read_cr2())
6662                 write_cr2(vcpu->arch.cr2);
6663
6664         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6665                                    vmx->loaded_vmcs->launched);
6666
6667         vcpu->arch.cr2 = read_cr2();
6668
6669         /*
6670          * We do not use IBRS in the kernel. If this vCPU has used the
6671          * SPEC_CTRL MSR it may have left it on; save the value and
6672          * turn it off. This is much more efficient than blindly adding
6673          * it to the atomic save/restore list. Especially as the former
6674          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6675          *
6676          * For non-nested case:
6677          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6678          * save it.
6679          *
6680          * For nested case:
6681          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6682          * save it.
6683          */
6684         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6685                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6686
6687         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6688
6689         /* All fields are clean at this point */
6690         if (static_branch_unlikely(&enable_evmcs))
6691                 current_evmcs->hv_clean_fields |=
6692                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6693
6694         if (static_branch_unlikely(&enable_evmcs))
6695                 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6696
6697         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6698         if (vmx->host_debugctlmsr)
6699                 update_debugctlmsr(vmx->host_debugctlmsr);
6700
6701 #ifndef CONFIG_X86_64
6702         /*
6703          * The sysexit path does not restore ds/es, so we must set them to
6704          * a reasonable value ourselves.
6705          *
6706          * We can't defer this to vmx_prepare_switch_to_host() since that
6707          * function may be executed in interrupt context, which saves and
6708          * restore segments around it, nullifying its effect.
6709          */
6710         loadsegment(ds, __USER_DS);
6711         loadsegment(es, __USER_DS);
6712 #endif
6713
6714         vmx_register_cache_reset(vcpu);
6715
6716         pt_guest_exit(vmx);
6717
6718         /*
6719          * eager fpu is enabled if PKEY is supported and CR4 is switched
6720          * back on host, so it is safe to read guest PKRU from current
6721          * XSAVE.
6722          */
6723         if (static_cpu_has(X86_FEATURE_PKU) &&
6724             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6725                 vcpu->arch.pkru = rdpkru();
6726                 if (vcpu->arch.pkru != vmx->host_pkru)
6727                         __write_pkru(vmx->host_pkru);
6728         }
6729
6730         kvm_load_host_xsave_state(vcpu);
6731
6732         vmx->nested.nested_run_pending = 0;
6733         vmx->idt_vectoring_info = 0;
6734
6735         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6736         if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6737                 kvm_machine_check();
6738
6739         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6740                 return;
6741
6742         vmx->loaded_vmcs->launched = 1;
6743         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6744
6745         vmx_recover_nmi_blocking(vmx);
6746         vmx_complete_interrupts(vmx);
6747 }
6748
6749 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6750 {
6751         struct vcpu_vmx *vmx = to_vmx(vcpu);
6752
6753         if (enable_pml)
6754                 vmx_destroy_pml_buffer(vmx);
6755         free_vpid(vmx->vpid);
6756         nested_vmx_free_vcpu(vcpu);
6757         free_loaded_vmcs(vmx->loaded_vmcs);
6758 }
6759
6760 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6761 {
6762         struct vcpu_vmx *vmx;
6763         unsigned long *msr_bitmap;
6764         int i, cpu, err;
6765
6766         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6767         vmx = to_vmx(vcpu);
6768
6769         err = -ENOMEM;
6770
6771         vmx->vpid = allocate_vpid();
6772
6773         /*
6774          * If PML is turned on, failure on enabling PML just results in failure
6775          * of creating the vcpu, therefore we can simplify PML logic (by
6776          * avoiding dealing with cases, such as enabling PML partially on vcpus
6777          * for the guest), etc.
6778          */
6779         if (enable_pml) {
6780                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6781                 if (!vmx->pml_pg)
6782                         goto free_vpid;
6783         }
6784
6785         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
6786
6787         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6788                 u32 index = vmx_msr_index[i];
6789                 u32 data_low, data_high;
6790                 int j = vmx->nmsrs;
6791
6792                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6793                         continue;
6794                 if (wrmsr_safe(index, data_low, data_high) < 0)
6795                         continue;
6796
6797                 vmx->guest_msrs[j].index = i;
6798                 vmx->guest_msrs[j].data = 0;
6799                 switch (index) {
6800                 case MSR_IA32_TSX_CTRL:
6801                         /*
6802                          * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6803                          * let's avoid changing CPUID bits under the host
6804                          * kernel's feet.
6805                          */
6806                         vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6807                         break;
6808                 default:
6809                         vmx->guest_msrs[j].mask = -1ull;
6810                         break;
6811                 }
6812                 ++vmx->nmsrs;
6813         }
6814
6815         err = alloc_loaded_vmcs(&vmx->vmcs01);
6816         if (err < 0)
6817                 goto free_pml;
6818
6819         msr_bitmap = vmx->vmcs01.msr_bitmap;
6820         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6821         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6822         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6823         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6824         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6825         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6826         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6827         if (kvm_cstate_in_guest(vcpu->kvm)) {
6828                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6829                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6830                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6831                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6832         }
6833         vmx->msr_bitmap_mode = 0;
6834
6835         vmx->loaded_vmcs = &vmx->vmcs01;
6836         cpu = get_cpu();
6837         vmx_vcpu_load(vcpu, cpu);
6838         vcpu->cpu = cpu;
6839         init_vmcs(vmx);
6840         vmx_vcpu_put(vcpu);
6841         put_cpu();
6842         if (cpu_need_virtualize_apic_accesses(vcpu)) {
6843                 err = alloc_apic_access_page(vcpu->kvm);
6844                 if (err)
6845                         goto free_vmcs;
6846         }
6847
6848         if (enable_ept && !enable_unrestricted_guest) {
6849                 err = init_rmode_identity_map(vcpu->kvm);
6850                 if (err)
6851                         goto free_vmcs;
6852         }
6853
6854         if (nested)
6855                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6856                                            vmx_capability.ept);
6857         else
6858                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6859
6860         vmx->nested.posted_intr_nv = -1;
6861         vmx->nested.current_vmptr = -1ull;
6862
6863         vcpu->arch.microcode_version = 0x100000000ULL;
6864         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6865
6866         /*
6867          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6868          * or POSTED_INTR_WAKEUP_VECTOR.
6869          */
6870         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6871         vmx->pi_desc.sn = 1;
6872
6873         vmx->ept_pointer = INVALID_PAGE;
6874
6875         return 0;
6876
6877 free_vmcs:
6878         free_loaded_vmcs(vmx->loaded_vmcs);
6879 free_pml:
6880         vmx_destroy_pml_buffer(vmx);
6881 free_vpid:
6882         free_vpid(vmx->vpid);
6883         return err;
6884 }
6885
6886 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6887 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6888
6889 static int vmx_vm_init(struct kvm *kvm)
6890 {
6891         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6892
6893         if (!ple_gap)
6894                 kvm->arch.pause_in_guest = true;
6895
6896         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6897                 switch (l1tf_mitigation) {
6898                 case L1TF_MITIGATION_OFF:
6899                 case L1TF_MITIGATION_FLUSH_NOWARN:
6900                         /* 'I explicitly don't care' is set */
6901                         break;
6902                 case L1TF_MITIGATION_FLUSH:
6903                 case L1TF_MITIGATION_FLUSH_NOSMT:
6904                 case L1TF_MITIGATION_FULL:
6905                         /*
6906                          * Warn upon starting the first VM in a potentially
6907                          * insecure environment.
6908                          */
6909                         if (sched_smt_active())
6910                                 pr_warn_once(L1TF_MSG_SMT);
6911                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6912                                 pr_warn_once(L1TF_MSG_L1D);
6913                         break;
6914                 case L1TF_MITIGATION_FULL_FORCE:
6915                         /* Flush is enforced */
6916                         break;
6917                 }
6918         }
6919         kvm_apicv_init(kvm, enable_apicv);
6920         return 0;
6921 }
6922
6923 static int __init vmx_check_processor_compat(void)
6924 {
6925         struct vmcs_config vmcs_conf;
6926         struct vmx_capability vmx_cap;
6927
6928         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6929             !this_cpu_has(X86_FEATURE_VMX)) {
6930                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6931                 return -EIO;
6932         }
6933
6934         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6935                 return -EIO;
6936         if (nested)
6937                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6938         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6939                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6940                                 smp_processor_id());
6941                 return -EIO;
6942         }
6943         return 0;
6944 }
6945
6946 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6947 {
6948         u8 cache;
6949         u64 ipat = 0;
6950
6951         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6952          * memory aliases with conflicting memory types and sometimes MCEs.
6953          * We have to be careful as to what are honored and when.
6954          *
6955          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
6956          * UC.  The effective memory type is UC or WC depending on guest PAT.
6957          * This was historically the source of MCEs and we want to be
6958          * conservative.
6959          *
6960          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6961          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
6962          * EPT memory type is set to WB.  The effective memory type is forced
6963          * WB.
6964          *
6965          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
6966          * EPT memory type is used to emulate guest CD/MTRR.
6967          */
6968
6969         if (is_mmio) {
6970                 cache = MTRR_TYPE_UNCACHABLE;
6971                 goto exit;
6972         }
6973
6974         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6975                 ipat = VMX_EPT_IPAT_BIT;
6976                 cache = MTRR_TYPE_WRBACK;
6977                 goto exit;
6978         }
6979
6980         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6981                 ipat = VMX_EPT_IPAT_BIT;
6982                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6983                         cache = MTRR_TYPE_WRBACK;
6984                 else
6985                         cache = MTRR_TYPE_UNCACHABLE;
6986                 goto exit;
6987         }
6988
6989         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6990
6991 exit:
6992         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6993 }
6994
6995 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6996 {
6997         /*
6998          * These bits in the secondary execution controls field
6999          * are dynamic, the others are mostly based on the hypervisor
7000          * architecture and the guest's CPUID.  Do not touch the
7001          * dynamic bits.
7002          */
7003         u32 mask =
7004                 SECONDARY_EXEC_SHADOW_VMCS |
7005                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7006                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7007                 SECONDARY_EXEC_DESC;
7008
7009         u32 new_ctl = vmx->secondary_exec_control;
7010         u32 cur_ctl = secondary_exec_controls_get(vmx);
7011
7012         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7013 }
7014
7015 /*
7016  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7017  * (indicating "allowed-1") if they are supported in the guest's CPUID.
7018  */
7019 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7020 {
7021         struct vcpu_vmx *vmx = to_vmx(vcpu);
7022         struct kvm_cpuid_entry2 *entry;
7023
7024         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7025         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7026
7027 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
7028         if (entry && (entry->_reg & (_cpuid_mask)))                     \
7029                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
7030 } while (0)
7031
7032         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7033         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
7034         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
7035         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
7036         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
7037         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
7038         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
7039         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
7040         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
7041         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
7042         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7043         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
7044         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
7045         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
7046         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
7047
7048         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7049         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
7050         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
7051         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
7052         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
7053         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
7054         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
7055
7056 #undef cr4_fixed1_update
7057 }
7058
7059 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7060 {
7061         struct vcpu_vmx *vmx = to_vmx(vcpu);
7062
7063         if (kvm_mpx_supported()) {
7064                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7065
7066                 if (mpx_enabled) {
7067                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7068                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7069                 } else {
7070                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7071                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7072                 }
7073         }
7074 }
7075
7076 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7077 {
7078         struct vcpu_vmx *vmx = to_vmx(vcpu);
7079         struct kvm_cpuid_entry2 *best = NULL;
7080         int i;
7081
7082         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7083                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7084                 if (!best)
7085                         return;
7086                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7087                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7088                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7089                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7090         }
7091
7092         /* Get the number of configurable Address Ranges for filtering */
7093         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7094                                                 PT_CAP_num_address_ranges);
7095
7096         /* Initialize and clear the no dependency bits */
7097         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7098                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7099
7100         /*
7101          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7102          * will inject an #GP
7103          */
7104         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7105                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7106
7107         /*
7108          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7109          * PSBFreq can be set
7110          */
7111         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7112                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7113                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7114
7115         /*
7116          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7117          * MTCFreq can be set
7118          */
7119         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7120                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7121                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7122
7123         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7124         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7125                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7126                                                         RTIT_CTL_PTW_EN);
7127
7128         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7129         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7130                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7131
7132         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7133         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7134                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7135
7136         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7137         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7138                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7139
7140         /* unmask address range configure area */
7141         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7142                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7143 }
7144
7145 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7146 {
7147         struct vcpu_vmx *vmx = to_vmx(vcpu);
7148
7149         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7150         vcpu->arch.xsaves_enabled = false;
7151
7152         if (cpu_has_secondary_exec_ctrls()) {
7153                 vmx_compute_secondary_exec_control(vmx);
7154                 vmcs_set_secondary_exec_control(vmx);
7155         }
7156
7157         if (nested_vmx_allowed(vcpu))
7158                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7159                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7160                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7161         else
7162                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7163                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7164                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7165
7166         if (nested_vmx_allowed(vcpu)) {
7167                 nested_vmx_cr_fixed1_bits_update(vcpu);
7168                 nested_vmx_entry_exit_ctls_update(vcpu);
7169         }
7170
7171         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7172                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7173                 update_intel_pt_cfg(vcpu);
7174
7175         if (boot_cpu_has(X86_FEATURE_RTM)) {
7176                 struct shared_msr_entry *msr;
7177                 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7178                 if (msr) {
7179                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7180                         vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7181                 }
7182         }
7183 }
7184
7185 static __init void vmx_set_cpu_caps(void)
7186 {
7187         kvm_set_cpu_caps();
7188
7189         /* CPUID 0x1 */
7190         if (nested)
7191                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7192
7193         /* CPUID 0x7 */
7194         if (kvm_mpx_supported())
7195                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7196         if (cpu_has_vmx_invpcid())
7197                 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
7198         if (vmx_pt_mode_is_host_guest())
7199                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7200
7201         /* PKU is not yet implemented for shadow paging. */
7202         if (enable_ept && boot_cpu_has(X86_FEATURE_OSPKE))
7203                 kvm_cpu_cap_check_and_set(X86_FEATURE_PKU);
7204
7205         if (vmx_umip_emulated())
7206                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7207
7208         /* CPUID 0xD.1 */
7209         supported_xss = 0;
7210         if (!vmx_xsaves_supported())
7211                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7212
7213         /* CPUID 0x80000001 */
7214         if (!cpu_has_vmx_rdtscp())
7215                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7216 }
7217
7218 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7219 {
7220         to_vmx(vcpu)->req_immediate_exit = true;
7221 }
7222
7223 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7224                                   struct x86_instruction_info *info)
7225 {
7226         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7227         unsigned short port;
7228         bool intercept;
7229         int size;
7230
7231         if (info->intercept == x86_intercept_in ||
7232             info->intercept == x86_intercept_ins) {
7233                 port = info->src_val;
7234                 size = info->dst_bytes;
7235         } else {
7236                 port = info->dst_val;
7237                 size = info->src_bytes;
7238         }
7239
7240         /*
7241          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7242          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7243          * control.
7244          *
7245          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7246          */
7247         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7248                 intercept = nested_cpu_has(vmcs12,
7249                                            CPU_BASED_UNCOND_IO_EXITING);
7250         else
7251                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7252
7253         /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7254         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7255 }
7256
7257 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7258                                struct x86_instruction_info *info,
7259                                enum x86_intercept_stage stage,
7260                                struct x86_exception *exception)
7261 {
7262         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7263
7264         switch (info->intercept) {
7265         /*
7266          * RDPID causes #UD if disabled through secondary execution controls.
7267          * Because it is marked as EmulateOnUD, we need to intercept it here.
7268          */
7269         case x86_intercept_rdtscp:
7270                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7271                         exception->vector = UD_VECTOR;
7272                         exception->error_code_valid = false;
7273                         return X86EMUL_PROPAGATE_FAULT;
7274                 }
7275                 break;
7276
7277         case x86_intercept_in:
7278         case x86_intercept_ins:
7279         case x86_intercept_out:
7280         case x86_intercept_outs:
7281                 return vmx_check_intercept_io(vcpu, info);
7282
7283         case x86_intercept_lgdt:
7284         case x86_intercept_lidt:
7285         case x86_intercept_lldt:
7286         case x86_intercept_ltr:
7287         case x86_intercept_sgdt:
7288         case x86_intercept_sidt:
7289         case x86_intercept_sldt:
7290         case x86_intercept_str:
7291                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7292                         return X86EMUL_CONTINUE;
7293
7294                 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7295                 break;
7296
7297         /* TODO: check more intercepts... */
7298         default:
7299                 break;
7300         }
7301
7302         return X86EMUL_UNHANDLEABLE;
7303 }
7304
7305 #ifdef CONFIG_X86_64
7306 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7307 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7308                                   u64 divisor, u64 *result)
7309 {
7310         u64 low = a << shift, high = a >> (64 - shift);
7311
7312         /* To avoid the overflow on divq */
7313         if (high >= divisor)
7314                 return 1;
7315
7316         /* Low hold the result, high hold rem which is discarded */
7317         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7318             "rm" (divisor), "0" (low), "1" (high));
7319         *result = low;
7320
7321         return 0;
7322 }
7323
7324 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7325                             bool *expired)
7326 {
7327         struct vcpu_vmx *vmx;
7328         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7329         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7330
7331         if (kvm_mwait_in_guest(vcpu->kvm) ||
7332                 kvm_can_post_timer_interrupt(vcpu))
7333                 return -EOPNOTSUPP;
7334
7335         vmx = to_vmx(vcpu);
7336         tscl = rdtsc();
7337         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7338         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7339         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7340                                                     ktimer->timer_advance_ns);
7341
7342         if (delta_tsc > lapic_timer_advance_cycles)
7343                 delta_tsc -= lapic_timer_advance_cycles;
7344         else
7345                 delta_tsc = 0;
7346
7347         /* Convert to host delta tsc if tsc scaling is enabled */
7348         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7349             delta_tsc && u64_shl_div_u64(delta_tsc,
7350                                 kvm_tsc_scaling_ratio_frac_bits,
7351                                 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7352                 return -ERANGE;
7353
7354         /*
7355          * If the delta tsc can't fit in the 32 bit after the multi shift,
7356          * we can't use the preemption timer.
7357          * It's possible that it fits on later vmentries, but checking
7358          * on every vmentry is costly so we just use an hrtimer.
7359          */
7360         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7361                 return -ERANGE;
7362
7363         vmx->hv_deadline_tsc = tscl + delta_tsc;
7364         *expired = !delta_tsc;
7365         return 0;
7366 }
7367
7368 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7369 {
7370         to_vmx(vcpu)->hv_deadline_tsc = -1;
7371 }
7372 #endif
7373
7374 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7375 {
7376         if (!kvm_pause_in_guest(vcpu->kvm))
7377                 shrink_ple_window(vcpu);
7378 }
7379
7380 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7381                                      struct kvm_memory_slot *slot)
7382 {
7383         if (!kvm_dirty_log_manual_protect_and_init_set(kvm))
7384                 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7385         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7386 }
7387
7388 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7389                                        struct kvm_memory_slot *slot)
7390 {
7391         kvm_mmu_slot_set_dirty(kvm, slot);
7392 }
7393
7394 static void vmx_flush_log_dirty(struct kvm *kvm)
7395 {
7396         kvm_flush_pml_buffers(kvm);
7397 }
7398
7399 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7400 {
7401         struct vmcs12 *vmcs12;
7402         struct vcpu_vmx *vmx = to_vmx(vcpu);
7403         gpa_t gpa, dst;
7404
7405         if (is_guest_mode(vcpu)) {
7406                 WARN_ON_ONCE(vmx->nested.pml_full);
7407
7408                 /*
7409                  * Check if PML is enabled for the nested guest.
7410                  * Whether eptp bit 6 is set is already checked
7411                  * as part of A/D emulation.
7412                  */
7413                 vmcs12 = get_vmcs12(vcpu);
7414                 if (!nested_cpu_has_pml(vmcs12))
7415                         return 0;
7416
7417                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7418                         vmx->nested.pml_full = true;
7419                         return 1;
7420                 }
7421
7422                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7423                 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7424
7425                 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7426                                          offset_in_page(dst), sizeof(gpa)))
7427                         return 0;
7428
7429                 vmcs12->guest_pml_index--;
7430         }
7431
7432         return 0;
7433 }
7434
7435 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7436                                            struct kvm_memory_slot *memslot,
7437                                            gfn_t offset, unsigned long mask)
7438 {
7439         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7440 }
7441
7442 static void __pi_post_block(struct kvm_vcpu *vcpu)
7443 {
7444         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7445         struct pi_desc old, new;
7446         unsigned int dest;
7447
7448         do {
7449                 old.control = new.control = pi_desc->control;
7450                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7451                      "Wakeup handler not enabled while the VCPU is blocked\n");
7452
7453                 dest = cpu_physical_id(vcpu->cpu);
7454
7455                 if (x2apic_enabled())
7456                         new.ndst = dest;
7457                 else
7458                         new.ndst = (dest << 8) & 0xFF00;
7459
7460                 /* set 'NV' to 'notification vector' */
7461                 new.nv = POSTED_INTR_VECTOR;
7462         } while (cmpxchg64(&pi_desc->control, old.control,
7463                            new.control) != old.control);
7464
7465         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7466                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7467                 list_del(&vcpu->blocked_vcpu_list);
7468                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7469                 vcpu->pre_pcpu = -1;
7470         }
7471 }
7472
7473 /*
7474  * This routine does the following things for vCPU which is going
7475  * to be blocked if VT-d PI is enabled.
7476  * - Store the vCPU to the wakeup list, so when interrupts happen
7477  *   we can find the right vCPU to wake up.
7478  * - Change the Posted-interrupt descriptor as below:
7479  *      'NDST' <-- vcpu->pre_pcpu
7480  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7481  * - If 'ON' is set during this process, which means at least one
7482  *   interrupt is posted for this vCPU, we cannot block it, in
7483  *   this case, return 1, otherwise, return 0.
7484  *
7485  */
7486 static int pi_pre_block(struct kvm_vcpu *vcpu)
7487 {
7488         unsigned int dest;
7489         struct pi_desc old, new;
7490         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7491
7492         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7493                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
7494                 !kvm_vcpu_apicv_active(vcpu))
7495                 return 0;
7496
7497         WARN_ON(irqs_disabled());
7498         local_irq_disable();
7499         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7500                 vcpu->pre_pcpu = vcpu->cpu;
7501                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7502                 list_add_tail(&vcpu->blocked_vcpu_list,
7503                               &per_cpu(blocked_vcpu_on_cpu,
7504                                        vcpu->pre_pcpu));
7505                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7506         }
7507
7508         do {
7509                 old.control = new.control = pi_desc->control;
7510
7511                 WARN((pi_desc->sn == 1),
7512                      "Warning: SN field of posted-interrupts "
7513                      "is set before blocking\n");
7514
7515                 /*
7516                  * Since vCPU can be preempted during this process,
7517                  * vcpu->cpu could be different with pre_pcpu, we
7518                  * need to set pre_pcpu as the destination of wakeup
7519                  * notification event, then we can find the right vCPU
7520                  * to wakeup in wakeup handler if interrupts happen
7521                  * when the vCPU is in blocked state.
7522                  */
7523                 dest = cpu_physical_id(vcpu->pre_pcpu);
7524
7525                 if (x2apic_enabled())
7526                         new.ndst = dest;
7527                 else
7528                         new.ndst = (dest << 8) & 0xFF00;
7529
7530                 /* set 'NV' to 'wakeup vector' */
7531                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7532         } while (cmpxchg64(&pi_desc->control, old.control,
7533                            new.control) != old.control);
7534
7535         /* We should not block the vCPU if an interrupt is posted for it.  */
7536         if (pi_test_on(pi_desc) == 1)
7537                 __pi_post_block(vcpu);
7538
7539         local_irq_enable();
7540         return (vcpu->pre_pcpu == -1);
7541 }
7542
7543 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7544 {
7545         if (pi_pre_block(vcpu))
7546                 return 1;
7547
7548         if (kvm_lapic_hv_timer_in_use(vcpu))
7549                 kvm_lapic_switch_to_sw_timer(vcpu);
7550
7551         return 0;
7552 }
7553
7554 static void pi_post_block(struct kvm_vcpu *vcpu)
7555 {
7556         if (vcpu->pre_pcpu == -1)
7557                 return;
7558
7559         WARN_ON(irqs_disabled());
7560         local_irq_disable();
7561         __pi_post_block(vcpu);
7562         local_irq_enable();
7563 }
7564
7565 static void vmx_post_block(struct kvm_vcpu *vcpu)
7566 {
7567         if (kvm_x86_ops.set_hv_timer)
7568                 kvm_lapic_switch_to_hv_timer(vcpu);
7569
7570         pi_post_block(vcpu);
7571 }
7572
7573 /*
7574  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7575  *
7576  * @kvm: kvm
7577  * @host_irq: host irq of the interrupt
7578  * @guest_irq: gsi of the interrupt
7579  * @set: set or unset PI
7580  * returns 0 on success, < 0 on failure
7581  */
7582 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7583                               uint32_t guest_irq, bool set)
7584 {
7585         struct kvm_kernel_irq_routing_entry *e;
7586         struct kvm_irq_routing_table *irq_rt;
7587         struct kvm_lapic_irq irq;
7588         struct kvm_vcpu *vcpu;
7589         struct vcpu_data vcpu_info;
7590         int idx, ret = 0;
7591
7592         if (!kvm_arch_has_assigned_device(kvm) ||
7593                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7594                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7595                 return 0;
7596
7597         idx = srcu_read_lock(&kvm->irq_srcu);
7598         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7599         if (guest_irq >= irq_rt->nr_rt_entries ||
7600             hlist_empty(&irq_rt->map[guest_irq])) {
7601                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7602                              guest_irq, irq_rt->nr_rt_entries);
7603                 goto out;
7604         }
7605
7606         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7607                 if (e->type != KVM_IRQ_ROUTING_MSI)
7608                         continue;
7609                 /*
7610                  * VT-d PI cannot support posting multicast/broadcast
7611                  * interrupts to a vCPU, we still use interrupt remapping
7612                  * for these kind of interrupts.
7613                  *
7614                  * For lowest-priority interrupts, we only support
7615                  * those with single CPU as the destination, e.g. user
7616                  * configures the interrupts via /proc/irq or uses
7617                  * irqbalance to make the interrupts single-CPU.
7618                  *
7619                  * We will support full lowest-priority interrupt later.
7620                  *
7621                  * In addition, we can only inject generic interrupts using
7622                  * the PI mechanism, refuse to route others through it.
7623                  */
7624
7625                 kvm_set_msi_irq(kvm, e, &irq);
7626                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7627                     !kvm_irq_is_postable(&irq)) {
7628                         /*
7629                          * Make sure the IRTE is in remapped mode if
7630                          * we don't handle it in posted mode.
7631                          */
7632                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7633                         if (ret < 0) {
7634                                 printk(KERN_INFO
7635                                    "failed to back to remapped mode, irq: %u\n",
7636                                    host_irq);
7637                                 goto out;
7638                         }
7639
7640                         continue;
7641                 }
7642
7643                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7644                 vcpu_info.vector = irq.vector;
7645
7646                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7647                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7648
7649                 if (set)
7650                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7651                 else
7652                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7653
7654                 if (ret < 0) {
7655                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
7656                                         __func__);
7657                         goto out;
7658                 }
7659         }
7660
7661         ret = 0;
7662 out:
7663         srcu_read_unlock(&kvm->irq_srcu, idx);
7664         return ret;
7665 }
7666
7667 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7668 {
7669         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7670                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7671                         FEAT_CTL_LMCE_ENABLED;
7672         else
7673                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7674                         ~FEAT_CTL_LMCE_ENABLED;
7675 }
7676
7677 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7678 {
7679         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7680         if (to_vmx(vcpu)->nested.nested_run_pending)
7681                 return 0;
7682         return 1;
7683 }
7684
7685 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7686 {
7687         struct vcpu_vmx *vmx = to_vmx(vcpu);
7688
7689         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7690         if (vmx->nested.smm.guest_mode)
7691                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7692
7693         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7694         vmx->nested.vmxon = false;
7695         vmx_clear_hlt(vcpu);
7696         return 0;
7697 }
7698
7699 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7700 {
7701         struct vcpu_vmx *vmx = to_vmx(vcpu);
7702         int ret;
7703
7704         if (vmx->nested.smm.vmxon) {
7705                 vmx->nested.vmxon = true;
7706                 vmx->nested.smm.vmxon = false;
7707         }
7708
7709         if (vmx->nested.smm.guest_mode) {
7710                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7711                 if (ret)
7712                         return ret;
7713
7714                 vmx->nested.smm.guest_mode = false;
7715         }
7716         return 0;
7717 }
7718
7719 static int enable_smi_window(struct kvm_vcpu *vcpu)
7720 {
7721         return 0;
7722 }
7723
7724 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7725 {
7726         return false;
7727 }
7728
7729 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7730 {
7731         return to_vmx(vcpu)->nested.vmxon;
7732 }
7733
7734 static void hardware_unsetup(void)
7735 {
7736         if (nested)
7737                 nested_vmx_hardware_unsetup();
7738
7739         free_kvm_area();
7740 }
7741
7742 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7743 {
7744         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7745                           BIT(APICV_INHIBIT_REASON_HYPERV);
7746
7747         return supported & BIT(bit);
7748 }
7749
7750 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7751         .hardware_unsetup = hardware_unsetup,
7752
7753         .hardware_enable = hardware_enable,
7754         .hardware_disable = hardware_disable,
7755         .cpu_has_accelerated_tpr = report_flexpriority,
7756         .has_emulated_msr = vmx_has_emulated_msr,
7757
7758         .vm_size = sizeof(struct kvm_vmx),
7759         .vm_init = vmx_vm_init,
7760
7761         .vcpu_create = vmx_create_vcpu,
7762         .vcpu_free = vmx_free_vcpu,
7763         .vcpu_reset = vmx_vcpu_reset,
7764
7765         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7766         .vcpu_load = vmx_vcpu_load,
7767         .vcpu_put = vmx_vcpu_put,
7768
7769         .update_bp_intercept = update_exception_bitmap,
7770         .get_msr_feature = vmx_get_msr_feature,
7771         .get_msr = vmx_get_msr,
7772         .set_msr = vmx_set_msr,
7773         .get_segment_base = vmx_get_segment_base,
7774         .get_segment = vmx_get_segment,
7775         .set_segment = vmx_set_segment,
7776         .get_cpl = vmx_get_cpl,
7777         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7778         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7779         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7780         .set_cr0 = vmx_set_cr0,
7781         .set_cr4 = vmx_set_cr4,
7782         .set_efer = vmx_set_efer,
7783         .get_idt = vmx_get_idt,
7784         .set_idt = vmx_set_idt,
7785         .get_gdt = vmx_get_gdt,
7786         .set_gdt = vmx_set_gdt,
7787         .get_dr6 = vmx_get_dr6,
7788         .set_dr6 = vmx_set_dr6,
7789         .set_dr7 = vmx_set_dr7,
7790         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7791         .cache_reg = vmx_cache_reg,
7792         .get_rflags = vmx_get_rflags,
7793         .set_rflags = vmx_set_rflags,
7794
7795         .tlb_flush_all = vmx_flush_tlb_all,
7796         .tlb_flush_current = vmx_flush_tlb_current,
7797         .tlb_flush_gva = vmx_flush_tlb_gva,
7798         .tlb_flush_guest = vmx_flush_tlb_guest,
7799
7800         .run = vmx_vcpu_run,
7801         .handle_exit = vmx_handle_exit,
7802         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7803         .update_emulated_instruction = vmx_update_emulated_instruction,
7804         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7805         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7806         .patch_hypercall = vmx_patch_hypercall,
7807         .set_irq = vmx_inject_irq,
7808         .set_nmi = vmx_inject_nmi,
7809         .queue_exception = vmx_queue_exception,
7810         .cancel_injection = vmx_cancel_injection,
7811         .interrupt_allowed = vmx_interrupt_allowed,
7812         .nmi_allowed = vmx_nmi_allowed,
7813         .get_nmi_mask = vmx_get_nmi_mask,
7814         .set_nmi_mask = vmx_set_nmi_mask,
7815         .enable_nmi_window = enable_nmi_window,
7816         .enable_irq_window = enable_irq_window,
7817         .update_cr8_intercept = update_cr8_intercept,
7818         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7819         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7820         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7821         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7822         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7823         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7824         .hwapic_irr_update = vmx_hwapic_irr_update,
7825         .hwapic_isr_update = vmx_hwapic_isr_update,
7826         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7827         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7828         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7829         .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7830
7831         .set_tss_addr = vmx_set_tss_addr,
7832         .set_identity_map_addr = vmx_set_identity_map_addr,
7833         .get_tdp_level = get_ept_level,
7834         .get_mt_mask = vmx_get_mt_mask,
7835
7836         .get_exit_info = vmx_get_exit_info,
7837
7838         .cpuid_update = vmx_cpuid_update,
7839
7840         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7841
7842         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7843         .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7844
7845         .load_mmu_pgd = vmx_load_mmu_pgd,
7846
7847         .check_intercept = vmx_check_intercept,
7848         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7849
7850         .request_immediate_exit = vmx_request_immediate_exit,
7851
7852         .sched_in = vmx_sched_in,
7853
7854         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7855         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7856         .flush_log_dirty = vmx_flush_log_dirty,
7857         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7858         .write_log_dirty = vmx_write_pml_buffer,
7859
7860         .pre_block = vmx_pre_block,
7861         .post_block = vmx_post_block,
7862
7863         .pmu_ops = &intel_pmu_ops,
7864
7865         .update_pi_irte = vmx_update_pi_irte,
7866
7867 #ifdef CONFIG_X86_64
7868         .set_hv_timer = vmx_set_hv_timer,
7869         .cancel_hv_timer = vmx_cancel_hv_timer,
7870 #endif
7871
7872         .setup_mce = vmx_setup_mce,
7873
7874         .smi_allowed = vmx_smi_allowed,
7875         .pre_enter_smm = vmx_pre_enter_smm,
7876         .pre_leave_smm = vmx_pre_leave_smm,
7877         .enable_smi_window = enable_smi_window,
7878
7879         .check_nested_events = NULL,
7880         .get_nested_state = NULL,
7881         .set_nested_state = NULL,
7882         .get_vmcs12_pages = NULL,
7883         .nested_enable_evmcs = NULL,
7884         .nested_get_evmcs_version = NULL,
7885         .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7886         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7887 };
7888
7889 static __init int hardware_setup(void)
7890 {
7891         unsigned long host_bndcfgs;
7892         struct desc_ptr dt;
7893         int r, i, ept_lpage_level;
7894
7895         store_idt(&dt);
7896         host_idt_base = dt.address;
7897
7898         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7899                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7900
7901         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7902                 return -EIO;
7903
7904         if (boot_cpu_has(X86_FEATURE_NX))
7905                 kvm_enable_efer_bits(EFER_NX);
7906
7907         if (boot_cpu_has(X86_FEATURE_MPX)) {
7908                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7909                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7910         }
7911
7912         if (!cpu_has_vmx_mpx())
7913                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7914                                     XFEATURE_MASK_BNDCSR);
7915
7916         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7917             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7918                 enable_vpid = 0;
7919
7920         if (!cpu_has_vmx_ept() ||
7921             !cpu_has_vmx_ept_4levels() ||
7922             !cpu_has_vmx_ept_mt_wb() ||
7923             !cpu_has_vmx_invept_global())
7924                 enable_ept = 0;
7925
7926         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7927                 enable_ept_ad_bits = 0;
7928
7929         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7930                 enable_unrestricted_guest = 0;
7931
7932         if (!cpu_has_vmx_flexpriority())
7933                 flexpriority_enabled = 0;
7934
7935         if (!cpu_has_virtual_nmis())
7936                 enable_vnmi = 0;
7937
7938         /*
7939          * set_apic_access_page_addr() is used to reload apic access
7940          * page upon invalidation.  No need to do anything if not
7941          * using the APIC_ACCESS_ADDR VMCS field.
7942          */
7943         if (!flexpriority_enabled)
7944                 vmx_x86_ops.set_apic_access_page_addr = NULL;
7945
7946         if (!cpu_has_vmx_tpr_shadow())
7947                 vmx_x86_ops.update_cr8_intercept = NULL;
7948
7949 #if IS_ENABLED(CONFIG_HYPERV)
7950         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7951             && enable_ept) {
7952                 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7953                 vmx_x86_ops.tlb_remote_flush_with_range =
7954                                 hv_remote_flush_tlb_with_range;
7955         }
7956 #endif
7957
7958         if (!cpu_has_vmx_ple()) {
7959                 ple_gap = 0;
7960                 ple_window = 0;
7961                 ple_window_grow = 0;
7962                 ple_window_max = 0;
7963                 ple_window_shrink = 0;
7964         }
7965
7966         if (!cpu_has_vmx_apicv()) {
7967                 enable_apicv = 0;
7968                 vmx_x86_ops.sync_pir_to_irr = NULL;
7969         }
7970
7971         if (cpu_has_vmx_tsc_scaling()) {
7972                 kvm_has_tsc_control = true;
7973                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7974                 kvm_tsc_scaling_ratio_frac_bits = 48;
7975         }
7976
7977         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7978
7979         if (enable_ept)
7980                 vmx_enable_tdp();
7981
7982         if (!enable_ept)
7983                 ept_lpage_level = 0;
7984         else if (cpu_has_vmx_ept_1g_page())
7985                 ept_lpage_level = PT_PDPE_LEVEL;
7986         else if (cpu_has_vmx_ept_2m_page())
7987                 ept_lpage_level = PT_DIRECTORY_LEVEL;
7988         else
7989                 ept_lpage_level = PT_PAGE_TABLE_LEVEL;
7990         kvm_configure_mmu(enable_ept, ept_lpage_level);
7991
7992         /*
7993          * Only enable PML when hardware supports PML feature, and both EPT
7994          * and EPT A/D bit features are enabled -- PML depends on them to work.
7995          */
7996         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7997                 enable_pml = 0;
7998
7999         if (!enable_pml) {
8000                 vmx_x86_ops.slot_enable_log_dirty = NULL;
8001                 vmx_x86_ops.slot_disable_log_dirty = NULL;
8002                 vmx_x86_ops.flush_log_dirty = NULL;
8003                 vmx_x86_ops.enable_log_dirty_pt_masked = NULL;
8004         }
8005
8006         if (!cpu_has_vmx_preemption_timer())
8007                 enable_preemption_timer = false;
8008
8009         if (enable_preemption_timer) {
8010                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
8011                 u64 vmx_msr;
8012
8013                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
8014                 cpu_preemption_timer_multi =
8015                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
8016
8017                 if (tsc_khz)
8018                         use_timer_freq = (u64)tsc_khz * 1000;
8019                 use_timer_freq >>= cpu_preemption_timer_multi;
8020
8021                 /*
8022                  * KVM "disables" the preemption timer by setting it to its max
8023                  * value.  Don't use the timer if it might cause spurious exits
8024                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
8025                  */
8026                 if (use_timer_freq > 0xffffffffu / 10)
8027                         enable_preemption_timer = false;
8028         }
8029
8030         if (!enable_preemption_timer) {
8031                 vmx_x86_ops.set_hv_timer = NULL;
8032                 vmx_x86_ops.cancel_hv_timer = NULL;
8033                 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
8034         }
8035
8036         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
8037
8038         kvm_mce_cap_supported |= MCG_LMCE_P;
8039
8040         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
8041                 return -EINVAL;
8042         if (!enable_ept || !cpu_has_vmx_intel_pt())
8043                 pt_mode = PT_MODE_SYSTEM;
8044
8045         if (nested) {
8046                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
8047                                            vmx_capability.ept);
8048
8049                 r = nested_vmx_hardware_setup(&vmx_x86_ops,
8050                                               kvm_vmx_exit_handlers);
8051                 if (r)
8052                         return r;
8053         }
8054
8055         vmx_set_cpu_caps();
8056
8057         r = alloc_kvm_area();
8058         if (r)
8059                 nested_vmx_hardware_unsetup();
8060         return r;
8061 }
8062
8063 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
8064         .cpu_has_kvm_support = cpu_has_kvm_support,
8065         .disabled_by_bios = vmx_disabled_by_bios,
8066         .check_processor_compatibility = vmx_check_processor_compat,
8067         .hardware_setup = hardware_setup,
8068
8069         .runtime_ops = &vmx_x86_ops,
8070 };
8071
8072 static void vmx_cleanup_l1d_flush(void)
8073 {
8074         if (vmx_l1d_flush_pages) {
8075                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
8076                 vmx_l1d_flush_pages = NULL;
8077         }
8078         /* Restore state so sysfs ignores VMX */
8079         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
8080 }
8081
8082 static void vmx_exit(void)
8083 {
8084 #ifdef CONFIG_KEXEC_CORE
8085         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8086         synchronize_rcu();
8087 #endif
8088
8089         kvm_exit();
8090
8091 #if IS_ENABLED(CONFIG_HYPERV)
8092         if (static_branch_unlikely(&enable_evmcs)) {
8093                 int cpu;
8094                 struct hv_vp_assist_page *vp_ap;
8095                 /*
8096                  * Reset everything to support using non-enlightened VMCS
8097                  * access later (e.g. when we reload the module with
8098                  * enlightened_vmcs=0)
8099                  */
8100                 for_each_online_cpu(cpu) {
8101                         vp_ap = hv_get_vp_assist_page(cpu);
8102
8103                         if (!vp_ap)
8104                                 continue;
8105
8106                         vp_ap->nested_control.features.directhypercall = 0;
8107                         vp_ap->current_nested_vmcs = 0;
8108                         vp_ap->enlighten_vmentry = 0;
8109                 }
8110
8111                 static_branch_disable(&enable_evmcs);
8112         }
8113 #endif
8114         vmx_cleanup_l1d_flush();
8115 }
8116 module_exit(vmx_exit);
8117
8118 static int __init vmx_init(void)
8119 {
8120         int r, cpu;
8121
8122 #if IS_ENABLED(CONFIG_HYPERV)
8123         /*
8124          * Enlightened VMCS usage should be recommended and the host needs
8125          * to support eVMCS v1 or above. We can also disable eVMCS support
8126          * with module parameter.
8127          */
8128         if (enlightened_vmcs &&
8129             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8130             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8131             KVM_EVMCS_VERSION) {
8132                 int cpu;
8133
8134                 /* Check that we have assist pages on all online CPUs */
8135                 for_each_online_cpu(cpu) {
8136                         if (!hv_get_vp_assist_page(cpu)) {
8137                                 enlightened_vmcs = false;
8138                                 break;
8139                         }
8140                 }
8141
8142                 if (enlightened_vmcs) {
8143                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8144                         static_branch_enable(&enable_evmcs);
8145                 }
8146
8147                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8148                         vmx_x86_ops.enable_direct_tlbflush
8149                                 = hv_enable_direct_tlbflush;
8150
8151         } else {
8152                 enlightened_vmcs = false;
8153         }
8154 #endif
8155
8156         r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
8157                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8158         if (r)
8159                 return r;
8160
8161         /*
8162          * Must be called after kvm_init() so enable_ept is properly set
8163          * up. Hand the parameter mitigation value in which was stored in
8164          * the pre module init parser. If no parameter was given, it will
8165          * contain 'auto' which will be turned into the default 'cond'
8166          * mitigation mode.
8167          */
8168         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8169         if (r) {
8170                 vmx_exit();
8171                 return r;
8172         }
8173
8174         for_each_possible_cpu(cpu) {
8175                 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8176                 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
8177                 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8178         }
8179
8180 #ifdef CONFIG_KEXEC_CORE
8181         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8182                            crash_vmclear_local_loaded_vmcss);
8183 #endif
8184         vmx_check_vmcs12_offsets();
8185
8186         return 0;
8187 }
8188 module_init(vmx_init);