arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/frame.h>
  17 #include <linux/highmem.h>
  18 #include <linux/hrtimer.h>
  19 #include <linux/kernel.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/mm.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30
  31 #include <asm/apic.h>
  32 #include <asm/asm.h>
  33 #include <asm/cpu.h>
  34 #include <asm/cpu_device_id.h>
  35 #include <asm/debugreg.h>
  36 #include <asm/desc.h>
  37 #include <asm/fpu/internal.h>
  38 #include <asm/io.h>
  39 #include <asm/irq_remapping.h>
  40 #include <asm/kexec.h>
  41 #include <asm/perf_event.h>
  42 #include <asm/mce.h>
  43 #include <asm/mmu_context.h>
  44 #include <asm/mshyperv.h>
  45 #include <asm/mwait.h>
  46 #include <asm/spec-ctrl.h>
  47 #include <asm/virtext.h>
  48 #include <asm/vmx.h>
  49
  50 #include "capabilities.h"
  51 #include "cpuid.h"
  52 #include "evmcs.h"
  53 #include "irq.h"
  54 #include "kvm_cache_regs.h"
  55 #include "lapic.h"
  56 #include "mmu.h"
  57 #include "nested.h"
  58 #include "ops.h"
  59 #include "pmu.h"
  60 #include "trace.h"
  61 #include "vmcs.h"
  62 #include "vmcs12.h"
  63 #include "vmx.h"
  64 #include "x86.h"
  65
  66 MODULE_AUTHOR("Qumranet");
  67 MODULE_LICENSE("GPL");
  68
  69 #ifdef MODULE
  70 static const struct x86_cpu_id vmx_cpu_id[] = {
  71         X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
  72         {}
  73 };
  74 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  75 #endif
  76
  77 bool __read_mostly enable_vpid = 1;
  78 module_param_named(vpid, enable_vpid, bool, 0444);
  79
  80 static bool __read_mostly enable_vnmi = 1;
  81 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  82
  83 bool __read_mostly flexpriority_enabled = 1;
  84 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  85
  86 bool __read_mostly enable_ept = 1;
  87 module_param_named(ept, enable_ept, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_unrestricted_guest = 1;
  90 module_param_named(unrestricted_guest,
  91                         enable_unrestricted_guest, bool, S_IRUGO);
  92
  93 bool __read_mostly enable_ept_ad_bits = 1;
  94 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  95
  96 static bool __read_mostly emulate_invalid_guest_state = true;
  97 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  98
  99 static bool __read_mostly fasteoi = 1;
 100 module_param(fasteoi, bool, S_IRUGO);
 101
 102 bool __read_mostly enable_apicv = 1;
 103 module_param(enable_apicv, bool, S_IRUGO);
 104
 105 /*
 106  * If nested=1, nested virtualization is supported, i.e., guests may use
 107  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 108  * use VMX instructions.
 109  */
 110 static bool __read_mostly nested = 1;
 111 module_param(nested, bool, S_IRUGO);
 112
 113 bool __read_mostly enable_pml = 1;
 114 module_param_named(pml, enable_pml, bool, S_IRUGO);
 115
 116 static bool __read_mostly dump_invalid_vmcs = 0;
 117 module_param(dump_invalid_vmcs, bool, 0644);
 118
 119 #define MSR_BITMAP_MODE_X2APIC          1
 120 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 121
 122 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 123
 124 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 125 static int __read_mostly cpu_preemption_timer_multi;
 126 static bool __read_mostly enable_preemption_timer = 1;
 127 #ifdef CONFIG_X86_64
 128 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 129 #endif
 130
 131 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 132 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 133 #define KVM_VM_CR0_ALWAYS_ON                            \
 134         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 135          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 136 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 137         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 138          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 139
 140 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 141 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 142 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 143
 144 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 145
 146 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 147         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 148         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 149         RTIT_STATUS_BYTECNT))
 150
 151 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
 152         (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
 153
 154 /*
 155  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 156  * ple_gap:    upper bound on the amount of time between two successive
 157  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 158  *             According to test, this time is usually smaller than 128 cycles.
 159  * ple_window: upper bound on the amount of time a guest is allowed to execute
 160  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 161  *             less than 2^12 cycles
 162  * Time is measured based on a counter that runs at the same rate as the TSC,
 163  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 164  */
 165 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 166 module_param(ple_gap, uint, 0444);
 167
 168 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 169 module_param(ple_window, uint, 0444);
 170
 171 /* Default doubles per-vcpu window every exit. */
 172 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 173 module_param(ple_window_grow, uint, 0444);
 174
 175 /* Default resets per-vcpu window every exit to ple_window. */
 176 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 177 module_param(ple_window_shrink, uint, 0444);
 178
 179 /* Default is to compute the maximum so we can never overflow. */
 180 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 181 module_param(ple_window_max, uint, 0444);
 182
 183 /* Default is SYSTEM mode, 1 for host-guest mode */
 184 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 185 module_param(pt_mode, int, S_IRUGO);
 186
 187 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 188 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 189 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 190
 191 /* Storage for pre module init parameter parsing */
 192 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 193
 194 static const struct {
 195         const char *option;
 196         bool for_parse;
 197 } vmentry_l1d_param[] = {
 198         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 199         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 200         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 201         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 202         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 203         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 204 };
 205
 206 #define L1D_CACHE_ORDER 4
 207 static void *vmx_l1d_flush_pages;
 208
 209 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 210 {
 211         struct page *page;
 212         unsigned int i;
 213
 214         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 215                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 216                 return 0;
 217         }
 218
 219         if (!enable_ept) {
 220                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 221                 return 0;
 222         }
 223
 224         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 225                 u64 msr;
 226
 227                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 228                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 229                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 230                         return 0;
 231                 }
 232         }
 233
 234         /* If set to auto use the default l1tf mitigation method */
 235         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 236                 switch (l1tf_mitigation) {
 237                 case L1TF_MITIGATION_OFF:
 238                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 239                         break;
 240                 case L1TF_MITIGATION_FLUSH_NOWARN:
 241                 case L1TF_MITIGATION_FLUSH:
 242                 case L1TF_MITIGATION_FLUSH_NOSMT:
 243                         l1tf = VMENTER_L1D_FLUSH_COND;
 244                         break;
 245                 case L1TF_MITIGATION_FULL:
 246                 case L1TF_MITIGATION_FULL_FORCE:
 247                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 248                         break;
 249                 }
 250         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 251                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 252         }
 253
 254         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 255             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 256                 /*
 257                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 258                  * lifetime and so should not be charged to a memcg.
 259                  */
 260                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 261                 if (!page)
 262                         return -ENOMEM;
 263                 vmx_l1d_flush_pages = page_address(page);
 264
 265                 /*
 266                  * Initialize each page with a different pattern in
 267                  * order to protect against KSM in the nested
 268                  * virtualization case.
 269                  */
 270                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 271                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 272                                PAGE_SIZE);
 273                 }
 274         }
 275
 276         l1tf_vmx_mitigation = l1tf;
 277
 278         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 279                 static_branch_enable(&vmx_l1d_should_flush);
 280         else
 281                 static_branch_disable(&vmx_l1d_should_flush);
 282
 283         if (l1tf == VMENTER_L1D_FLUSH_COND)
 284                 static_branch_enable(&vmx_l1d_flush_cond);
 285         else
 286                 static_branch_disable(&vmx_l1d_flush_cond);
 287         return 0;
 288 }
 289
 290 static int vmentry_l1d_flush_parse(const char *s)
 291 {
 292         unsigned int i;
 293
 294         if (s) {
 295                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 296                         if (vmentry_l1d_param[i].for_parse &&
 297                             sysfs_streq(s, vmentry_l1d_param[i].option))
 298                                 return i;
 299                 }
 300         }
 301         return -EINVAL;
 302 }
 303
 304 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 305 {
 306         int l1tf, ret;
 307
 308         l1tf = vmentry_l1d_flush_parse(s);
 309         if (l1tf < 0)
 310                 return l1tf;
 311
 312         if (!boot_cpu_has(X86_BUG_L1TF))
 313                 return 0;
 314
 315         /*
 316          * Has vmx_init() run already? If not then this is the pre init
 317          * parameter parsing. In that case just store the value and let
 318          * vmx_init() do the proper setup after enable_ept has been
 319          * established.
 320          */
 321         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 322                 vmentry_l1d_flush_param = l1tf;
 323                 return 0;
 324         }
 325
 326         mutex_lock(&vmx_l1d_flush_mutex);
 327         ret = vmx_setup_l1d_flush(l1tf);
 328         mutex_unlock(&vmx_l1d_flush_mutex);
 329         return ret;
 330 }
 331
 332 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 333 {
 334         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 335                 return sprintf(s, "???\n");
 336
 337         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 338 }
 339
 340 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 341         .set = vmentry_l1d_flush_set,
 342         .get = vmentry_l1d_flush_get,
 343 };
 344 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 345
 346 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 347 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 348 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 349                                                           u32 msr, int type);
 350
 351 void vmx_vmexit(void);
 352
 353 #define vmx_insn_failed(fmt...)         \
 354 do {                                    \
 355         WARN_ONCE(1, fmt);              \
 356         pr_warn_ratelimited(fmt);       \
 357 } while (0)
 358
 359 asmlinkage void vmread_error(unsigned long field, bool fault)
 360 {
 361         if (fault)
 362                 kvm_spurious_fault();
 363         else
 364                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 365 }
 366
 367 noinline void vmwrite_error(unsigned long field, unsigned long value)
 368 {
 369         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 370                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 371 }
 372
 373 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 374 {
 375         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 376 }
 377
 378 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 379 {
 380         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 381 }
 382
 383 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 384 {
 385         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 386                         ext, vpid, gva);
 387 }
 388
 389 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 390 {
 391         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 392                         ext, eptp, gpa);
 393 }
 394
 395 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 396 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 397 /*
 398  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 399  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 400  */
 401 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 402
 403 /*
 404  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 405  * can find which vCPU should be waken up.
 406  */
 407 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 408 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 409
 410 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 411 static DEFINE_SPINLOCK(vmx_vpid_lock);
 412
 413 struct vmcs_config vmcs_config;
 414 struct vmx_capability vmx_capability;
 415
 416 #define VMX_SEGMENT_FIELD(seg)                                  \
 417         [VCPU_SREG_##seg] = {                                   \
 418                 .selector = GUEST_##seg##_SELECTOR,             \
 419                 .base = GUEST_##seg##_BASE,                     \
 420                 .limit = GUEST_##seg##_LIMIT,                   \
 421                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 422         }
 423
 424 static const struct kvm_vmx_segment_field {
 425         unsigned selector;
 426         unsigned base;
 427         unsigned limit;
 428         unsigned ar_bytes;
 429 } kvm_vmx_segment_fields[] = {
 430         VMX_SEGMENT_FIELD(CS),
 431         VMX_SEGMENT_FIELD(DS),
 432         VMX_SEGMENT_FIELD(ES),
 433         VMX_SEGMENT_FIELD(FS),
 434         VMX_SEGMENT_FIELD(GS),
 435         VMX_SEGMENT_FIELD(SS),
 436         VMX_SEGMENT_FIELD(TR),
 437         VMX_SEGMENT_FIELD(LDTR),
 438 };
 439
 440 static unsigned long host_idt_base;
 441
 442 /*
 443  * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
 444  * will emulate SYSCALL in legacy mode if the vendor string in guest
 445  * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
 446  * support this emulation, IA32_STAR must always be included in
 447  * vmx_msr_index[], even in i386 builds.
 448  */
 449 const u32 vmx_msr_index[] = {
 450 #ifdef CONFIG_X86_64
 451         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 452 #endif
 453         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 454         MSR_IA32_TSX_CTRL,
 455 };
 456
 457 #if IS_ENABLED(CONFIG_HYPERV)
 458 static bool __read_mostly enlightened_vmcs = true;
 459 module_param(enlightened_vmcs, bool, 0444);
 460
 461 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
 462 static void check_ept_pointer_match(struct kvm *kvm)
 463 {
 464         struct kvm_vcpu *vcpu;
 465         u64 tmp_eptp = INVALID_PAGE;
 466         int i;
 467
 468         kvm_for_each_vcpu(i, vcpu, kvm) {
 469                 if (!VALID_PAGE(tmp_eptp)) {
 470                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
 471                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
 472                         to_kvm_vmx(kvm)->ept_pointers_match
 473                                 = EPT_POINTERS_MISMATCH;
 474                         return;
 475                 }
 476         }
 477
 478         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
 479 }
 480
 481 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
 482                 void *data)
 483 {
 484         struct kvm_tlb_range *range = data;
 485
 486         return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
 487                         range->pages);
 488 }
 489
 490 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
 491                 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
 492 {
 493         u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
 494
 495         /*
 496          * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
 497          * of the base of EPT PML4 table, strip off EPT configuration
 498          * information.
 499          */
 500         if (range)
 501                 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
 502                                 kvm_fill_hv_flush_list_func, (void *)range);
 503         else
 504                 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
 505 }
 506
 507 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
 508                 struct kvm_tlb_range *range)
 509 {
 510         struct kvm_vcpu *vcpu;
 511         int ret = 0, i;
 512
 513         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 514
 515         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
 516                 check_ept_pointer_match(kvm);
 517
 518         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
 519                 kvm_for_each_vcpu(i, vcpu, kvm) {
 520                         /* If ept_pointer is invalid pointer, bypass flush request. */
 521                         if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
 522                                 ret |= __hv_remote_flush_tlb_with_range(
 523                                         kvm, vcpu, range);
 524                 }
 525         } else {
 526                 ret = __hv_remote_flush_tlb_with_range(kvm,
 527                                 kvm_get_vcpu(kvm, 0), range);
 528         }
 529
 530         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 531         return ret;
 532 }
 533 static int hv_remote_flush_tlb(struct kvm *kvm)
 534 {
 535         return hv_remote_flush_tlb_with_range(kvm, NULL);
 536 }
 537
 538 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 539 {
 540         struct hv_enlightened_vmcs *evmcs;
 541         struct hv_partition_assist_pg **p_hv_pa_pg =
 542                         &vcpu->kvm->arch.hyperv.hv_pa_pg;
 543         /*
 544          * Synthetic VM-Exit is not enabled in current code and so All
 545          * evmcs in singe VM shares same assist page.
 546          */
 547         if (!*p_hv_pa_pg)
 548                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
 549
 550         if (!*p_hv_pa_pg)
 551                 return -ENOMEM;
 552
 553         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 554
 555         evmcs->partition_assist_page =
 556                 __pa(*p_hv_pa_pg);
 557         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 558         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 559
 560         return 0;
 561 }
 562
 563 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 564
 565 /*
 566  * Comment's format: document - errata name - stepping - processor name.
 567  * Refer from
 568  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 569  */
 570 static u32 vmx_preemption_cpu_tfms[] = {
 571 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 572 0x000206E6,
 573 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 574 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 575 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 576 0x00020652,
 577 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 578 0x00020655,
 579 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 580 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 581 /*
 582  * 320767.pdf - AAP86  - B1 -
 583  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 584  */
 585 0x000106E5,
 586 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 587 0x000106A0,
 588 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 589 0x000106A1,
 590 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 591 0x000106A4,
 592  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 593  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 594  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 595 0x000106A5,
 596  /* Xeon E3-1220 V2 */
 597 0x000306A8,
 598 };
 599
 600 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 601 {
 602         u32 eax = cpuid_eax(0x00000001), i;
 603
 604         /* Clear the reserved bits */
 605         eax &= ~(0x3U << 14 | 0xfU << 28);
 606         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 607                 if (eax == vmx_preemption_cpu_tfms[i])
 608                         return true;
 609
 610         return false;
 611 }
 612
 613 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 614 {
 615         return flexpriority_enabled && lapic_in_kernel(vcpu);
 616 }
 617
 618 static inline bool report_flexpriority(void)
 619 {
 620         return flexpriority_enabled;
 621 }
 622
 623 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 624 {
 625         int i;
 626
 627         for (i = 0; i < vmx->nmsrs; ++i)
 628                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 629                         return i;
 630         return -1;
 631 }
 632
 633 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 634 {
 635         int i;
 636
 637         i = __find_msr_index(vmx, msr);
 638         if (i >= 0)
 639                 return &vmx->guest_msrs[i];
 640         return NULL;
 641 }
 642
 643 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
 644 {
 645         int ret = 0;
 646
 647         u64 old_msr_data = msr->data;
 648         msr->data = data;
 649         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
 650                 preempt_disable();
 651                 ret = kvm_set_shared_msr(msr->index, msr->data,
 652                                          msr->mask);
 653                 preempt_enable();
 654                 if (ret)
 655                         msr->data = old_msr_data;
 656         }
 657         return ret;
 658 }
 659
 660 #ifdef CONFIG_KEXEC_CORE
 661 static void crash_vmclear_local_loaded_vmcss(void)
 662 {
 663         int cpu = raw_smp_processor_id();
 664         struct loaded_vmcs *v;
 665
 666         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 667                             loaded_vmcss_on_cpu_link)
 668                 vmcs_clear(v->vmcs);
 669 }
 670 #endif /* CONFIG_KEXEC_CORE */
 671
 672 static void __loaded_vmcs_clear(void *arg)
 673 {
 674         struct loaded_vmcs *loaded_vmcs = arg;
 675         int cpu = raw_smp_processor_id();
 676
 677         if (loaded_vmcs->cpu != cpu)
 678                 return; /* vcpu migration can race with cpu offline */
 679         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 680                 per_cpu(current_vmcs, cpu) = NULL;
 681
 682         vmcs_clear(loaded_vmcs->vmcs);
 683         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 684                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 685
 686         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 687
 688         /*
 689          * Ensure all writes to loaded_vmcs, including deleting it from its
 690          * current percpu list, complete before setting loaded_vmcs->vcpu to
 691          * -1, otherwise a different cpu can see vcpu == -1 first and add
 692          * loaded_vmcs to its percpu list before it's deleted from this cpu's
 693          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
 694          */
 695         smp_wmb();
 696
 697         loaded_vmcs->cpu = -1;
 698         loaded_vmcs->launched = 0;
 699 }
 700
 701 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 702 {
 703         int cpu = loaded_vmcs->cpu;
 704
 705         if (cpu != -1)
 706                 smp_call_function_single(cpu,
 707                          __loaded_vmcs_clear, loaded_vmcs, 1);
 708 }
 709
 710 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 711                                        unsigned field)
 712 {
 713         bool ret;
 714         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 715
 716         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
 717                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
 718                 vmx->segment_cache.bitmask = 0;
 719         }
 720         ret = vmx->segment_cache.bitmask & mask;
 721         vmx->segment_cache.bitmask |= mask;
 722         return ret;
 723 }
 724
 725 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 726 {
 727         u16 *p = &vmx->segment_cache.seg[seg].selector;
 728
 729         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 730                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 731         return *p;
 732 }
 733
 734 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 735 {
 736         ulong *p = &vmx->segment_cache.seg[seg].base;
 737
 738         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 739                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 740         return *p;
 741 }
 742
 743 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 744 {
 745         u32 *p = &vmx->segment_cache.seg[seg].limit;
 746
 747         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 748                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 749         return *p;
 750 }
 751
 752 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 753 {
 754         u32 *p = &vmx->segment_cache.seg[seg].ar;
 755
 756         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 757                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 758         return *p;
 759 }
 760
 761 void update_exception_bitmap(struct kvm_vcpu *vcpu)
 762 {
 763         u32 eb;
 764
 765         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 766              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 767         /*
 768          * Guest access to VMware backdoor ports could legitimately
 769          * trigger #GP because of TSS I/O permission bitmap.
 770          * We intercept those #GP and allow access to them anyway
 771          * as VMware does.
 772          */
 773         if (enable_vmware_backdoor)
 774                 eb |= (1u << GP_VECTOR);
 775         if ((vcpu->guest_debug &
 776              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 777             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 778                 eb |= 1u << BP_VECTOR;
 779         if (to_vmx(vcpu)->rmode.vm86_active)
 780                 eb = ~0;
 781         if (enable_ept)
 782                 eb &= ~(1u << PF_VECTOR);
 783
 784         /* When we are running a nested L2 guest and L1 specified for it a
 785          * certain exception bitmap, we must trap the same exceptions and pass
 786          * them to L1. When running L2, we will only handle the exceptions
 787          * specified above if L1 did not want them.
 788          */
 789         if (is_guest_mode(vcpu))
 790                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 791
 792         vmcs_write32(EXCEPTION_BITMAP, eb);
 793 }
 794
 795 /*
 796  * Check if MSR is intercepted for currently loaded MSR bitmap.
 797  */
 798 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 799 {
 800         unsigned long *msr_bitmap;
 801         int f = sizeof(unsigned long);
 802
 803         if (!cpu_has_vmx_msr_bitmap())
 804                 return true;
 805
 806         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 807
 808         if (msr <= 0x1fff) {
 809                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 810         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 811                 msr &= 0x1fff;
 812                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 813         }
 814
 815         return true;
 816 }
 817
 818 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 819                 unsigned long entry, unsigned long exit)
 820 {
 821         vm_entry_controls_clearbit(vmx, entry);
 822         vm_exit_controls_clearbit(vmx, exit);
 823 }
 824
 825 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
 826 {
 827         unsigned int i;
 828
 829         for (i = 0; i < m->nr; ++i) {
 830                 if (m->val[i].index == msr)
 831                         return i;
 832         }
 833         return -ENOENT;
 834 }
 835
 836 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 837 {
 838         int i;
 839         struct msr_autoload *m = &vmx->msr_autoload;
 840
 841         switch (msr) {
 842         case MSR_EFER:
 843                 if (cpu_has_load_ia32_efer()) {
 844                         clear_atomic_switch_msr_special(vmx,
 845                                         VM_ENTRY_LOAD_IA32_EFER,
 846                                         VM_EXIT_LOAD_IA32_EFER);
 847                         return;
 848                 }
 849                 break;
 850         case MSR_CORE_PERF_GLOBAL_CTRL:
 851                 if (cpu_has_load_perf_global_ctrl()) {
 852                         clear_atomic_switch_msr_special(vmx,
 853                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 854                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 855                         return;
 856                 }
 857                 break;
 858         }
 859         i = vmx_find_msr_index(&m->guest, msr);
 860         if (i < 0)
 861                 goto skip_guest;
 862         --m->guest.nr;
 863         m->guest.val[i] = m->guest.val[m->guest.nr];
 864         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 865
 866 skip_guest:
 867         i = vmx_find_msr_index(&m->host, msr);
 868         if (i < 0)
 869                 return;
 870
 871         --m->host.nr;
 872         m->host.val[i] = m->host.val[m->host.nr];
 873         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 874 }
 875
 876 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 877                 unsigned long entry, unsigned long exit,
 878                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 879                 u64 guest_val, u64 host_val)
 880 {
 881         vmcs_write64(guest_val_vmcs, guest_val);
 882         if (host_val_vmcs != HOST_IA32_EFER)
 883                 vmcs_write64(host_val_vmcs, host_val);
 884         vm_entry_controls_setbit(vmx, entry);
 885         vm_exit_controls_setbit(vmx, exit);
 886 }
 887
 888 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 889                                   u64 guest_val, u64 host_val, bool entry_only)
 890 {
 891         int i, j = 0;
 892         struct msr_autoload *m = &vmx->msr_autoload;
 893
 894         switch (msr) {
 895         case MSR_EFER:
 896                 if (cpu_has_load_ia32_efer()) {
 897                         add_atomic_switch_msr_special(vmx,
 898                                         VM_ENTRY_LOAD_IA32_EFER,
 899                                         VM_EXIT_LOAD_IA32_EFER,
 900                                         GUEST_IA32_EFER,
 901                                         HOST_IA32_EFER,
 902                                         guest_val, host_val);
 903                         return;
 904                 }
 905                 break;
 906         case MSR_CORE_PERF_GLOBAL_CTRL:
 907                 if (cpu_has_load_perf_global_ctrl()) {
 908                         add_atomic_switch_msr_special(vmx,
 909                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 910                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 911                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 912                                         HOST_IA32_PERF_GLOBAL_CTRL,
 913                                         guest_val, host_val);
 914                         return;
 915                 }
 916                 break;
 917         case MSR_IA32_PEBS_ENABLE:
 918                 /* PEBS needs a quiescent period after being disabled (to write
 919                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 920                  * provide that period, so a CPU could write host's record into
 921                  * guest's memory.
 922                  */
 923                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 924         }
 925
 926         i = vmx_find_msr_index(&m->guest, msr);
 927         if (!entry_only)
 928                 j = vmx_find_msr_index(&m->host, msr);
 929
 930         if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
 931                 (j < 0 &&  m->host.nr == NR_LOADSTORE_MSRS)) {
 932                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 933                                 "Can't add msr %x\n", msr);
 934                 return;
 935         }
 936         if (i < 0) {
 937                 i = m->guest.nr++;
 938                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 939         }
 940         m->guest.val[i].index = msr;
 941         m->guest.val[i].value = guest_val;
 942
 943         if (entry_only)
 944                 return;
 945
 946         if (j < 0) {
 947                 j = m->host.nr++;
 948                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 949         }
 950         m->host.val[j].index = msr;
 951         m->host.val[j].value = host_val;
 952 }
 953
 954 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 955 {
 956         u64 guest_efer = vmx->vcpu.arch.efer;
 957         u64 ignore_bits = 0;
 958
 959         /* Shadow paging assumes NX to be available.  */
 960         if (!enable_ept)
 961                 guest_efer |= EFER_NX;
 962
 963         /*
 964          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 965          */
 966         ignore_bits |= EFER_SCE;
 967 #ifdef CONFIG_X86_64
 968         ignore_bits |= EFER_LMA | EFER_LME;
 969         /* SCE is meaningful only in long mode on Intel */
 970         if (guest_efer & EFER_LMA)
 971                 ignore_bits &= ~(u64)EFER_SCE;
 972 #endif
 973
 974         /*
 975          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 976          * On CPUs that support "load IA32_EFER", always switch EFER
 977          * atomically, since it's faster than switching it manually.
 978          */
 979         if (cpu_has_load_ia32_efer() ||
 980             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 981                 if (!(guest_efer & EFER_LMA))
 982                         guest_efer &= ~EFER_LME;
 983                 if (guest_efer != host_efer)
 984                         add_atomic_switch_msr(vmx, MSR_EFER,
 985                                               guest_efer, host_efer, false);
 986                 else
 987                         clear_atomic_switch_msr(vmx, MSR_EFER);
 988                 return false;
 989         } else {
 990                 clear_atomic_switch_msr(vmx, MSR_EFER);
 991
 992                 guest_efer &= ~ignore_bits;
 993                 guest_efer |= host_efer & ignore_bits;
 994
 995                 vmx->guest_msrs[efer_offset].data = guest_efer;
 996                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 997
 998                 return true;
 999         }
1000 }
1001
1002 #ifdef CONFIG_X86_32
1003 /*
1004  * On 32-bit kernels, VM exits still load the FS and GS bases from the
1005  * VMCS rather than the segment table.  KVM uses this helper to figure
1006  * out the current bases to poke them into the VMCS before entry.
1007  */
1008 static unsigned long segment_base(u16 selector)
1009 {
1010         struct desc_struct *table;
1011         unsigned long v;
1012
1013         if (!(selector & ~SEGMENT_RPL_MASK))
1014                 return 0;
1015
1016         table = get_current_gdt_ro();
1017
1018         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1019                 u16 ldt_selector = kvm_read_ldt();
1020
1021                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1022                         return 0;
1023
1024                 table = (struct desc_struct *)segment_base(ldt_selector);
1025         }
1026         v = get_desc_base(&table[selector >> 3]);
1027         return v;
1028 }
1029 #endif
1030
1031 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1032 {
1033         return vmx_pt_mode_is_host_guest() &&
1034                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1035 }
1036
1037 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1038 {
1039         u32 i;
1040
1041         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1042         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1043         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1044         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1045         for (i = 0; i < addr_range; i++) {
1046                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1047                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1048         }
1049 }
1050
1051 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1052 {
1053         u32 i;
1054
1055         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1056         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1057         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1058         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1059         for (i = 0; i < addr_range; i++) {
1060                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1061                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1062         }
1063 }
1064
1065 static void pt_guest_enter(struct vcpu_vmx *vmx)
1066 {
1067         if (vmx_pt_mode_is_system())
1068                 return;
1069
1070         /*
1071          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1072          * Save host state before VM entry.
1073          */
1074         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1075         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1076                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1077                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1078                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1079         }
1080 }
1081
1082 static void pt_guest_exit(struct vcpu_vmx *vmx)
1083 {
1084         if (vmx_pt_mode_is_system())
1085                 return;
1086
1087         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1088                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1089                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1090         }
1091
1092         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1093         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1094 }
1095
1096 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1097                         unsigned long fs_base, unsigned long gs_base)
1098 {
1099         if (unlikely(fs_sel != host->fs_sel)) {
1100                 if (!(fs_sel & 7))
1101                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1102                 else
1103                         vmcs_write16(HOST_FS_SELECTOR, 0);
1104                 host->fs_sel = fs_sel;
1105         }
1106         if (unlikely(gs_sel != host->gs_sel)) {
1107                 if (!(gs_sel & 7))
1108                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1109                 else
1110                         vmcs_write16(HOST_GS_SELECTOR, 0);
1111                 host->gs_sel = gs_sel;
1112         }
1113         if (unlikely(fs_base != host->fs_base)) {
1114                 vmcs_writel(HOST_FS_BASE, fs_base);
1115                 host->fs_base = fs_base;
1116         }
1117         if (unlikely(gs_base != host->gs_base)) {
1118                 vmcs_writel(HOST_GS_BASE, gs_base);
1119                 host->gs_base = gs_base;
1120         }
1121 }
1122
1123 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1124 {
1125         struct vcpu_vmx *vmx = to_vmx(vcpu);
1126         struct vmcs_host_state *host_state;
1127 #ifdef CONFIG_X86_64
1128         int cpu = raw_smp_processor_id();
1129 #endif
1130         unsigned long fs_base, gs_base;
1131         u16 fs_sel, gs_sel;
1132         int i;
1133
1134         vmx->req_immediate_exit = false;
1135
1136         /*
1137          * Note that guest MSRs to be saved/restored can also be changed
1138          * when guest state is loaded. This happens when guest transitions
1139          * to/from long-mode by setting MSR_EFER.LMA.
1140          */
1141         if (!vmx->guest_msrs_ready) {
1142                 vmx->guest_msrs_ready = true;
1143                 for (i = 0; i < vmx->save_nmsrs; ++i)
1144                         kvm_set_shared_msr(vmx->guest_msrs[i].index,
1145                                            vmx->guest_msrs[i].data,
1146                                            vmx->guest_msrs[i].mask);
1147
1148         }
1149
1150         if (vmx->nested.need_vmcs12_to_shadow_sync)
1151                 nested_sync_vmcs12_to_shadow(vcpu);
1152
1153         if (vmx->guest_state_loaded)
1154                 return;
1155
1156         host_state = &vmx->loaded_vmcs->host_state;
1157
1158         /*
1159          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1160          * allow segment selectors with cpl > 0 or ti == 1.
1161          */
1162         host_state->ldt_sel = kvm_read_ldt();
1163
1164 #ifdef CONFIG_X86_64
1165         savesegment(ds, host_state->ds_sel);
1166         savesegment(es, host_state->es_sel);
1167
1168         gs_base = cpu_kernelmode_gs_base(cpu);
1169         if (likely(is_64bit_mm(current->mm))) {
1170                 save_fsgs_for_kvm();
1171                 fs_sel = current->thread.fsindex;
1172                 gs_sel = current->thread.gsindex;
1173                 fs_base = current->thread.fsbase;
1174                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1175         } else {
1176                 savesegment(fs, fs_sel);
1177                 savesegment(gs, gs_sel);
1178                 fs_base = read_msr(MSR_FS_BASE);
1179                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1180         }
1181
1182         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1183 #else
1184         savesegment(fs, fs_sel);
1185         savesegment(gs, gs_sel);
1186         fs_base = segment_base(fs_sel);
1187         gs_base = segment_base(gs_sel);
1188 #endif
1189
1190         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1191         vmx->guest_state_loaded = true;
1192 }
1193
1194 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1195 {
1196         struct vmcs_host_state *host_state;
1197
1198         if (!vmx->guest_state_loaded)
1199                 return;
1200
1201         host_state = &vmx->loaded_vmcs->host_state;
1202
1203         ++vmx->vcpu.stat.host_state_reload;
1204
1205 #ifdef CONFIG_X86_64
1206         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1207 #endif
1208         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1209                 kvm_load_ldt(host_state->ldt_sel);
1210 #ifdef CONFIG_X86_64
1211                 load_gs_index(host_state->gs_sel);
1212 #else
1213                 loadsegment(gs, host_state->gs_sel);
1214 #endif
1215         }
1216         if (host_state->fs_sel & 7)
1217                 loadsegment(fs, host_state->fs_sel);
1218 #ifdef CONFIG_X86_64
1219         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1220                 loadsegment(ds, host_state->ds_sel);
1221                 loadsegment(es, host_state->es_sel);
1222         }
1223 #endif
1224         invalidate_tss_limit();
1225 #ifdef CONFIG_X86_64
1226         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1227 #endif
1228         load_fixmap_gdt(raw_smp_processor_id());
1229         vmx->guest_state_loaded = false;
1230         vmx->guest_msrs_ready = false;
1231 }
1232
1233 #ifdef CONFIG_X86_64
1234 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1235 {
1236         preempt_disable();
1237         if (vmx->guest_state_loaded)
1238                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1239         preempt_enable();
1240         return vmx->msr_guest_kernel_gs_base;
1241 }
1242
1243 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1244 {
1245         preempt_disable();
1246         if (vmx->guest_state_loaded)
1247                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1248         preempt_enable();
1249         vmx->msr_guest_kernel_gs_base = data;
1250 }
1251 #endif
1252
1253 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1254 {
1255         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1256         struct pi_desc old, new;
1257         unsigned int dest;
1258
1259         /*
1260          * In case of hot-plug or hot-unplug, we may have to undo
1261          * vmx_vcpu_pi_put even if there is no assigned device.  And we
1262          * always keep PI.NDST up to date for simplicity: it makes the
1263          * code easier, and CPU migration is not a fast path.
1264          */
1265         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1266                 return;
1267
1268         /*
1269          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1270          * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1271          * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1272          * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1273          * correctly.
1274          */
1275         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1276                 pi_clear_sn(pi_desc);
1277                 goto after_clear_sn;
1278         }
1279
1280         /* The full case.  */
1281         do {
1282                 old.control = new.control = pi_desc->control;
1283
1284                 dest = cpu_physical_id(cpu);
1285
1286                 if (x2apic_enabled())
1287                         new.ndst = dest;
1288                 else
1289                         new.ndst = (dest << 8) & 0xFF00;
1290
1291                 new.sn = 0;
1292         } while (cmpxchg64(&pi_desc->control, old.control,
1293                            new.control) != old.control);
1294
1295 after_clear_sn:
1296
1297         /*
1298          * Clear SN before reading the bitmap.  The VT-d firmware
1299          * writes the bitmap and reads SN atomically (5.2.3 in the
1300          * spec), so it doesn't really have a memory barrier that
1301          * pairs with this, but we cannot do that and we need one.
1302          */
1303         smp_mb__after_atomic();
1304
1305         if (!pi_is_pir_empty(pi_desc))
1306                 pi_set_on(pi_desc);
1307 }
1308
1309 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1310 {
1311         struct vcpu_vmx *vmx = to_vmx(vcpu);
1312         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1313
1314         if (!already_loaded) {
1315                 loaded_vmcs_clear(vmx->loaded_vmcs);
1316                 local_irq_disable();
1317
1318                 /*
1319                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1320                  * this cpu's percpu list, otherwise it may not yet be deleted
1321                  * from its previous cpu's percpu list.  Pairs with the
1322                  * smb_wmb() in __loaded_vmcs_clear().
1323                  */
1324                 smp_rmb();
1325
1326                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1327                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1328                 local_irq_enable();
1329         }
1330
1331         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1332                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1333                 vmcs_load(vmx->loaded_vmcs->vmcs);
1334                 indirect_branch_prediction_barrier();
1335         }
1336
1337         if (!already_loaded) {
1338                 void *gdt = get_current_gdt_ro();
1339                 unsigned long sysenter_esp;
1340
1341                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1342
1343                 /*
1344                  * Linux uses per-cpu TSS and GDT, so set these when switching
1345                  * processors.  See 22.2.4.
1346                  */
1347                 vmcs_writel(HOST_TR_BASE,
1348                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1349                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1350
1351                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1352                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1353
1354                 vmx->loaded_vmcs->cpu = cpu;
1355         }
1356
1357         /* Setup TSC multiplier */
1358         if (kvm_has_tsc_control &&
1359             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1360                 decache_tsc_multiplier(vmx);
1361 }
1362
1363 /*
1364  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1365  * vcpu mutex is already taken.
1366  */
1367 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1368 {
1369         struct vcpu_vmx *vmx = to_vmx(vcpu);
1370
1371         vmx_vcpu_load_vmcs(vcpu, cpu);
1372
1373         vmx_vcpu_pi_load(vcpu, cpu);
1374
1375         vmx->host_pkru = read_pkru();
1376         vmx->host_debugctlmsr = get_debugctlmsr();
1377 }
1378
1379 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1380 {
1381         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1382
1383         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1384                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
1385                 !kvm_vcpu_apicv_active(vcpu))
1386                 return;
1387
1388         /* Set SN when the vCPU is preempted */
1389         if (vcpu->preempted)
1390                 pi_set_sn(pi_desc);
1391 }
1392
1393 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1394 {
1395         vmx_vcpu_pi_put(vcpu);
1396
1397         vmx_prepare_switch_to_host(to_vmx(vcpu));
1398 }
1399
1400 static bool emulation_required(struct kvm_vcpu *vcpu)
1401 {
1402         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1403 }
1404
1405 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1406 {
1407         struct vcpu_vmx *vmx = to_vmx(vcpu);
1408         unsigned long rflags, save_rflags;
1409
1410         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1411                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1412                 rflags = vmcs_readl(GUEST_RFLAGS);
1413                 if (vmx->rmode.vm86_active) {
1414                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1415                         save_rflags = vmx->rmode.save_rflags;
1416                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1417                 }
1418                 vmx->rflags = rflags;
1419         }
1420         return vmx->rflags;
1421 }
1422
1423 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1424 {
1425         struct vcpu_vmx *vmx = to_vmx(vcpu);
1426         unsigned long old_rflags;
1427
1428         if (enable_unrestricted_guest) {
1429                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1430                 vmx->rflags = rflags;
1431                 vmcs_writel(GUEST_RFLAGS, rflags);
1432                 return;
1433         }
1434
1435         old_rflags = vmx_get_rflags(vcpu);
1436         vmx->rflags = rflags;
1437         if (vmx->rmode.vm86_active) {
1438                 vmx->rmode.save_rflags = rflags;
1439                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1440         }
1441         vmcs_writel(GUEST_RFLAGS, rflags);
1442
1443         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1444                 vmx->emulation_required = emulation_required(vcpu);
1445 }
1446
1447 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1448 {
1449         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1450         int ret = 0;
1451
1452         if (interruptibility & GUEST_INTR_STATE_STI)
1453                 ret |= KVM_X86_SHADOW_INT_STI;
1454         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1455                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1456
1457         return ret;
1458 }
1459
1460 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1461 {
1462         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1463         u32 interruptibility = interruptibility_old;
1464
1465         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1466
1467         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1468                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1469         else if (mask & KVM_X86_SHADOW_INT_STI)
1470                 interruptibility |= GUEST_INTR_STATE_STI;
1471
1472         if ((interruptibility != interruptibility_old))
1473                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1474 }
1475
1476 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1477 {
1478         struct vcpu_vmx *vmx = to_vmx(vcpu);
1479         unsigned long value;
1480
1481         /*
1482          * Any MSR write that attempts to change bits marked reserved will
1483          * case a #GP fault.
1484          */
1485         if (data & vmx->pt_desc.ctl_bitmask)
1486                 return 1;
1487
1488         /*
1489          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1490          * result in a #GP unless the same write also clears TraceEn.
1491          */
1492         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1493                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1494                 return 1;
1495
1496         /*
1497          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1498          * and FabricEn would cause #GP, if
1499          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1500          */
1501         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1502                 !(data & RTIT_CTL_FABRIC_EN) &&
1503                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1504                                         PT_CAP_single_range_output))
1505                 return 1;
1506
1507         /*
1508          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1509          * utilize encodings marked reserved will casue a #GP fault.
1510          */
1511         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1512         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1513                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1514                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1515                 return 1;
1516         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1517                                                 PT_CAP_cycle_thresholds);
1518         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1519                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1520                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1521                 return 1;
1522         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1523         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1524                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1525                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1526                 return 1;
1527
1528         /*
1529          * If ADDRx_CFG is reserved or the encodings is >2 will
1530          * cause a #GP fault.
1531          */
1532         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1533         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1534                 return 1;
1535         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1536         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1537                 return 1;
1538         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1539         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1540                 return 1;
1541         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1542         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1543                 return 1;
1544
1545         return 0;
1546 }
1547
1548 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1549 {
1550         unsigned long rip;
1551
1552         /*
1553          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1554          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1555          * set when EPT misconfig occurs.  In practice, real hardware updates
1556          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1557          * (namely Hyper-V) don't set it due to it being undefined behavior,
1558          * i.e. we end up advancing IP with some random value.
1559          */
1560         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1561             to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1562                 rip = kvm_rip_read(vcpu);
1563                 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1564                 kvm_rip_write(vcpu, rip);
1565         } else {
1566                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1567                         return 0;
1568         }
1569
1570         /* skipping an emulated instruction also counts */
1571         vmx_set_interrupt_shadow(vcpu, 0);
1572
1573         return 1;
1574 }
1575
1576
1577 /*
1578  * Recognizes a pending MTF VM-exit and records the nested state for later
1579  * delivery.
1580  */
1581 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1582 {
1583         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1584         struct vcpu_vmx *vmx = to_vmx(vcpu);
1585
1586         if (!is_guest_mode(vcpu))
1587                 return;
1588
1589         /*
1590          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1591          * T-bit traps. As instruction emulation is completed (i.e. at the
1592          * instruction boundary), any #DB exception pending delivery must be a
1593          * debug-trap. Record the pending MTF state to be delivered in
1594          * vmx_check_nested_events().
1595          */
1596         if (nested_cpu_has_mtf(vmcs12) &&
1597             (!vcpu->arch.exception.pending ||
1598              vcpu->arch.exception.nr == DB_VECTOR))
1599                 vmx->nested.mtf_pending = true;
1600         else
1601                 vmx->nested.mtf_pending = false;
1602 }
1603
1604 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1605 {
1606         vmx_update_emulated_instruction(vcpu);
1607         return skip_emulated_instruction(vcpu);
1608 }
1609
1610 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1611 {
1612         /*
1613          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1614          * explicitly skip the instruction because if the HLT state is set,
1615          * then the instruction is already executing and RIP has already been
1616          * advanced.
1617          */
1618         if (kvm_hlt_in_guest(vcpu->kvm) &&
1619                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1620                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1621 }
1622
1623 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1624 {
1625         struct vcpu_vmx *vmx = to_vmx(vcpu);
1626         unsigned nr = vcpu->arch.exception.nr;
1627         bool has_error_code = vcpu->arch.exception.has_error_code;
1628         u32 error_code = vcpu->arch.exception.error_code;
1629         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1630
1631         kvm_deliver_exception_payload(vcpu);
1632
1633         if (has_error_code) {
1634                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1635                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1636         }
1637
1638         if (vmx->rmode.vm86_active) {
1639                 int inc_eip = 0;
1640                 if (kvm_exception_is_soft(nr))
1641                         inc_eip = vcpu->arch.event_exit_inst_len;
1642                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1643                 return;
1644         }
1645
1646         WARN_ON_ONCE(vmx->emulation_required);
1647
1648         if (kvm_exception_is_soft(nr)) {
1649                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1650                              vmx->vcpu.arch.event_exit_inst_len);
1651                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1652         } else
1653                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1654
1655         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1656
1657         vmx_clear_hlt(vcpu);
1658 }
1659
1660 /*
1661  * Swap MSR entry in host/guest MSR entry array.
1662  */
1663 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1664 {
1665         struct shared_msr_entry tmp;
1666
1667         tmp = vmx->guest_msrs[to];
1668         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1669         vmx->guest_msrs[from] = tmp;
1670 }
1671
1672 /*
1673  * Set up the vmcs to automatically save and restore system
1674  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1675  * mode, as fiddling with msrs is very expensive.
1676  */
1677 static void setup_msrs(struct vcpu_vmx *vmx)
1678 {
1679         int save_nmsrs, index;
1680
1681         save_nmsrs = 0;
1682 #ifdef CONFIG_X86_64
1683         /*
1684          * The SYSCALL MSRs are only needed on long mode guests, and only
1685          * when EFER.SCE is set.
1686          */
1687         if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1688                 index = __find_msr_index(vmx, MSR_STAR);
1689                 if (index >= 0)
1690                         move_msr_up(vmx, index, save_nmsrs++);
1691                 index = __find_msr_index(vmx, MSR_LSTAR);
1692                 if (index >= 0)
1693                         move_msr_up(vmx, index, save_nmsrs++);
1694                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1695                 if (index >= 0)
1696                         move_msr_up(vmx, index, save_nmsrs++);
1697         }
1698 #endif
1699         index = __find_msr_index(vmx, MSR_EFER);
1700         if (index >= 0 && update_transition_efer(vmx, index))
1701                 move_msr_up(vmx, index, save_nmsrs++);
1702         index = __find_msr_index(vmx, MSR_TSC_AUX);
1703         if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1704                 move_msr_up(vmx, index, save_nmsrs++);
1705         index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1706         if (index >= 0)
1707                 move_msr_up(vmx, index, save_nmsrs++);
1708
1709         vmx->save_nmsrs = save_nmsrs;
1710         vmx->guest_msrs_ready = false;
1711
1712         if (cpu_has_vmx_msr_bitmap())
1713                 vmx_update_msr_bitmap(&vmx->vcpu);
1714 }
1715
1716 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1717 {
1718         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1719
1720         if (is_guest_mode(vcpu) &&
1721             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1722                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1723
1724         return vcpu->arch.tsc_offset;
1725 }
1726
1727 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1728 {
1729         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1730         u64 g_tsc_offset = 0;
1731
1732         /*
1733          * We're here if L1 chose not to trap WRMSR to TSC. According
1734          * to the spec, this should set L1's TSC; The offset that L1
1735          * set for L2 remains unchanged, and still needs to be added
1736          * to the newly set TSC to get L2's TSC.
1737          */
1738         if (is_guest_mode(vcpu) &&
1739             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1740                 g_tsc_offset = vmcs12->tsc_offset;
1741
1742         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1743                                    vcpu->arch.tsc_offset - g_tsc_offset,
1744                                    offset);
1745         vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1746         return offset + g_tsc_offset;
1747 }
1748
1749 /*
1750  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1751  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1752  * all guests if the "nested" module option is off, and can also be disabled
1753  * for a single guest by disabling its VMX cpuid bit.
1754  */
1755 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1756 {
1757         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1758 }
1759
1760 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1761                                                  uint64_t val)
1762 {
1763         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1764
1765         return !(val & ~valid_bits);
1766 }
1767
1768 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1769 {
1770         switch (msr->index) {
1771         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1772                 if (!nested)
1773                         return 1;
1774                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1775         default:
1776                 return 1;
1777         }
1778 }
1779
1780 /*
1781  * Reads an msr value (of 'msr_index') into 'pdata'.
1782  * Returns 0 on success, non-0 otherwise.
1783  * Assumes vcpu_load() was already called.
1784  */
1785 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1786 {
1787         struct vcpu_vmx *vmx = to_vmx(vcpu);
1788         struct shared_msr_entry *msr;
1789         u32 index;
1790
1791         switch (msr_info->index) {
1792 #ifdef CONFIG_X86_64
1793         case MSR_FS_BASE:
1794                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1795                 break;
1796         case MSR_GS_BASE:
1797                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1798                 break;
1799         case MSR_KERNEL_GS_BASE:
1800                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1801                 break;
1802 #endif
1803         case MSR_EFER:
1804                 return kvm_get_msr_common(vcpu, msr_info);
1805         case MSR_IA32_TSX_CTRL:
1806                 if (!msr_info->host_initiated &&
1807                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1808                         return 1;
1809                 goto find_shared_msr;
1810         case MSR_IA32_UMWAIT_CONTROL:
1811                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1812                         return 1;
1813
1814                 msr_info->data = vmx->msr_ia32_umwait_control;
1815                 break;
1816         case MSR_IA32_SPEC_CTRL:
1817                 if (!msr_info->host_initiated &&
1818                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1819                         return 1;
1820
1821                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1822                 break;
1823         case MSR_IA32_SYSENTER_CS:
1824                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1825                 break;
1826         case MSR_IA32_SYSENTER_EIP:
1827                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1828                 break;
1829         case MSR_IA32_SYSENTER_ESP:
1830                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1831                 break;
1832         case MSR_IA32_BNDCFGS:
1833                 if (!kvm_mpx_supported() ||
1834                     (!msr_info->host_initiated &&
1835                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1836                         return 1;
1837                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1838                 break;
1839         case MSR_IA32_MCG_EXT_CTL:
1840                 if (!msr_info->host_initiated &&
1841                     !(vmx->msr_ia32_feature_control &
1842                       FEAT_CTL_LMCE_ENABLED))
1843                         return 1;
1844                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1845                 break;
1846         case MSR_IA32_FEAT_CTL:
1847                 msr_info->data = vmx->msr_ia32_feature_control;
1848                 break;
1849         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1850                 if (!nested_vmx_allowed(vcpu))
1851                         return 1;
1852                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1853                                     &msr_info->data))
1854                         return 1;
1855                 /*
1856                  * Enlightened VMCS v1 doesn't have certain fields, but buggy
1857                  * Hyper-V versions are still trying to use corresponding
1858                  * features when they are exposed. Filter out the essential
1859                  * minimum.
1860                  */
1861                 if (!msr_info->host_initiated &&
1862                     vmx->nested.enlightened_vmcs_enabled)
1863                         nested_evmcs_filter_control_msr(msr_info->index,
1864                                                         &msr_info->data);
1865                 break;
1866         case MSR_IA32_RTIT_CTL:
1867                 if (!vmx_pt_mode_is_host_guest())
1868                         return 1;
1869                 msr_info->data = vmx->pt_desc.guest.ctl;
1870                 break;
1871         case MSR_IA32_RTIT_STATUS:
1872                 if (!vmx_pt_mode_is_host_guest())
1873                         return 1;
1874                 msr_info->data = vmx->pt_desc.guest.status;
1875                 break;
1876         case MSR_IA32_RTIT_CR3_MATCH:
1877                 if (!vmx_pt_mode_is_host_guest() ||
1878                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1879                                                 PT_CAP_cr3_filtering))
1880                         return 1;
1881                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1882                 break;
1883         case MSR_IA32_RTIT_OUTPUT_BASE:
1884                 if (!vmx_pt_mode_is_host_guest() ||
1885                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1886                                         PT_CAP_topa_output) &&
1887                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1888                                         PT_CAP_single_range_output)))
1889                         return 1;
1890                 msr_info->data = vmx->pt_desc.guest.output_base;
1891                 break;
1892         case MSR_IA32_RTIT_OUTPUT_MASK:
1893                 if (!vmx_pt_mode_is_host_guest() ||
1894                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1895                                         PT_CAP_topa_output) &&
1896                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1897                                         PT_CAP_single_range_output)))
1898                         return 1;
1899                 msr_info->data = vmx->pt_desc.guest.output_mask;
1900                 break;
1901         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1902                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1903                 if (!vmx_pt_mode_is_host_guest() ||
1904                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1905                                         PT_CAP_num_address_ranges)))
1906                         return 1;
1907                 if (index % 2)
1908                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1909                 else
1910                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1911                 break;
1912         case MSR_TSC_AUX:
1913                 if (!msr_info->host_initiated &&
1914                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1915                         return 1;
1916                 goto find_shared_msr;
1917         default:
1918         find_shared_msr:
1919                 msr = find_msr_entry(vmx, msr_info->index);
1920                 if (msr) {
1921                         msr_info->data = msr->data;
1922                         break;
1923                 }
1924                 return kvm_get_msr_common(vcpu, msr_info);
1925         }
1926
1927         return 0;
1928 }
1929
1930 /*
1931  * Writes msr value into the appropriate "register".
1932  * Returns 0 on success, non-0 otherwise.
1933  * Assumes vcpu_load() was already called.
1934  */
1935 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1936 {
1937         struct vcpu_vmx *vmx = to_vmx(vcpu);
1938         struct shared_msr_entry *msr;
1939         int ret = 0;
1940         u32 msr_index = msr_info->index;
1941         u64 data = msr_info->data;
1942         u32 index;
1943
1944         switch (msr_index) {
1945         case MSR_EFER:
1946                 ret = kvm_set_msr_common(vcpu, msr_info);
1947                 break;
1948 #ifdef CONFIG_X86_64
1949         case MSR_FS_BASE:
1950                 vmx_segment_cache_clear(vmx);
1951                 vmcs_writel(GUEST_FS_BASE, data);
1952                 break;
1953         case MSR_GS_BASE:
1954                 vmx_segment_cache_clear(vmx);
1955                 vmcs_writel(GUEST_GS_BASE, data);
1956                 break;
1957         case MSR_KERNEL_GS_BASE:
1958                 vmx_write_guest_kernel_gs_base(vmx, data);
1959                 break;
1960 #endif
1961         case MSR_IA32_SYSENTER_CS:
1962                 if (is_guest_mode(vcpu))
1963                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1964                 vmcs_write32(GUEST_SYSENTER_CS, data);
1965                 break;
1966         case MSR_IA32_SYSENTER_EIP:
1967                 if (is_guest_mode(vcpu))
1968                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1969                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1970                 break;
1971         case MSR_IA32_SYSENTER_ESP:
1972                 if (is_guest_mode(vcpu))
1973                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1974                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1975                 break;
1976         case MSR_IA32_DEBUGCTLMSR:
1977                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1978                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
1979                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1980
1981                 ret = kvm_set_msr_common(vcpu, msr_info);
1982                 break;
1983
1984         case MSR_IA32_BNDCFGS:
1985                 if (!kvm_mpx_supported() ||
1986                     (!msr_info->host_initiated &&
1987                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1988                         return 1;
1989                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1990                     (data & MSR_IA32_BNDCFGS_RSVD))
1991                         return 1;
1992                 vmcs_write64(GUEST_BNDCFGS, data);
1993                 break;
1994         case MSR_IA32_UMWAIT_CONTROL:
1995                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1996                         return 1;
1997
1998                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
1999                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2000                         return 1;
2001
2002                 vmx->msr_ia32_umwait_control = data;
2003                 break;
2004         case MSR_IA32_SPEC_CTRL:
2005                 if (!msr_info->host_initiated &&
2006                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2007                         return 1;
2008
2009                 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
2010                         return 1;
2011
2012                 vmx->spec_ctrl = data;
2013                 if (!data)
2014                         break;
2015
2016                 /*
2017                  * For non-nested:
2018                  * When it's written (to non-zero) for the first time, pass
2019                  * it through.
2020                  *
2021                  * For nested:
2022                  * The handling of the MSR bitmap for L2 guests is done in
2023                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2024                  * vmcs02.msr_bitmap here since it gets completely overwritten
2025                  * in the merging. We update the vmcs01 here for L1 as well
2026                  * since it will end up touching the MSR anyway now.
2027                  */
2028                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2029                                               MSR_IA32_SPEC_CTRL,
2030                                               MSR_TYPE_RW);
2031                 break;
2032         case MSR_IA32_TSX_CTRL:
2033                 if (!msr_info->host_initiated &&
2034                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2035                         return 1;
2036                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2037                         return 1;
2038                 goto find_shared_msr;
2039         case MSR_IA32_PRED_CMD:
2040                 if (!msr_info->host_initiated &&
2041                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2042                         return 1;
2043
2044                 if (data & ~PRED_CMD_IBPB)
2045                         return 1;
2046                 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2047                         return 1;
2048                 if (!data)
2049                         break;
2050
2051                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2052
2053                 /*
2054                  * For non-nested:
2055                  * When it's written (to non-zero) for the first time, pass
2056                  * it through.
2057                  *
2058                  * For nested:
2059                  * The handling of the MSR bitmap for L2 guests is done in
2060                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2061                  * vmcs02.msr_bitmap here since it gets completely overwritten
2062                  * in the merging.
2063                  */
2064                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2065                                               MSR_TYPE_W);
2066                 break;
2067         case MSR_IA32_CR_PAT:
2068                 if (!kvm_pat_valid(data))
2069                         return 1;
2070
2071                 if (is_guest_mode(vcpu) &&
2072                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2073                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2074
2075                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2076                         vmcs_write64(GUEST_IA32_PAT, data);
2077                         vcpu->arch.pat = data;
2078                         break;
2079                 }
2080                 ret = kvm_set_msr_common(vcpu, msr_info);
2081                 break;
2082         case MSR_IA32_TSC_ADJUST:
2083                 ret = kvm_set_msr_common(vcpu, msr_info);
2084                 break;
2085         case MSR_IA32_MCG_EXT_CTL:
2086                 if ((!msr_info->host_initiated &&
2087                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2088                        FEAT_CTL_LMCE_ENABLED)) ||
2089                     (data & ~MCG_EXT_CTL_LMCE_EN))
2090                         return 1;
2091                 vcpu->arch.mcg_ext_ctl = data;
2092                 break;
2093         case MSR_IA32_FEAT_CTL:
2094                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2095                     (to_vmx(vcpu)->msr_ia32_feature_control &
2096                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2097                         return 1;
2098                 vmx->msr_ia32_feature_control = data;
2099                 if (msr_info->host_initiated && data == 0)
2100                         vmx_leave_nested(vcpu);
2101                 break;
2102         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2103                 if (!msr_info->host_initiated)
2104                         return 1; /* they are read-only */
2105                 if (!nested_vmx_allowed(vcpu))
2106                         return 1;
2107                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2108         case MSR_IA32_RTIT_CTL:
2109                 if (!vmx_pt_mode_is_host_guest() ||
2110                         vmx_rtit_ctl_check(vcpu, data) ||
2111                         vmx->nested.vmxon)
2112                         return 1;
2113                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2114                 vmx->pt_desc.guest.ctl = data;
2115                 pt_update_intercept_for_msr(vmx);
2116                 break;
2117         case MSR_IA32_RTIT_STATUS:
2118                 if (!pt_can_write_msr(vmx))
2119                         return 1;
2120                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2121                         return 1;
2122                 vmx->pt_desc.guest.status = data;
2123                 break;
2124         case MSR_IA32_RTIT_CR3_MATCH:
2125                 if (!pt_can_write_msr(vmx))
2126                         return 1;
2127                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2128                                            PT_CAP_cr3_filtering))
2129                         return 1;
2130                 vmx->pt_desc.guest.cr3_match = data;
2131                 break;
2132         case MSR_IA32_RTIT_OUTPUT_BASE:
2133                 if (!pt_can_write_msr(vmx))
2134                         return 1;
2135                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2136                                            PT_CAP_topa_output) &&
2137                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2138                                            PT_CAP_single_range_output))
2139                         return 1;
2140                 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
2141                         return 1;
2142                 vmx->pt_desc.guest.output_base = data;
2143                 break;
2144         case MSR_IA32_RTIT_OUTPUT_MASK:
2145                 if (!pt_can_write_msr(vmx))
2146                         return 1;
2147                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2148                                            PT_CAP_topa_output) &&
2149                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2150                                            PT_CAP_single_range_output))
2151                         return 1;
2152                 vmx->pt_desc.guest.output_mask = data;
2153                 break;
2154         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2155                 if (!pt_can_write_msr(vmx))
2156                         return 1;
2157                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2158                 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2159                                                        PT_CAP_num_address_ranges))
2160                         return 1;
2161                 if (is_noncanonical_address(data, vcpu))
2162                         return 1;
2163                 if (index % 2)
2164                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2165                 else
2166                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2167                 break;
2168         case MSR_TSC_AUX:
2169                 if (!msr_info->host_initiated &&
2170                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2171                         return 1;
2172                 /* Check reserved bit, higher 32 bits should be zero */
2173                 if ((data >> 32) != 0)
2174                         return 1;
2175                 goto find_shared_msr;
2176
2177         default:
2178         find_shared_msr:
2179                 msr = find_msr_entry(vmx, msr_index);
2180                 if (msr)
2181                         ret = vmx_set_guest_msr(vmx, msr, data);
2182                 else
2183                         ret = kvm_set_msr_common(vcpu, msr_info);
2184         }
2185
2186         return ret;
2187 }
2188
2189 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2190 {
2191         kvm_register_mark_available(vcpu, reg);
2192
2193         switch (reg) {
2194         case VCPU_REGS_RSP:
2195                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2196                 break;
2197         case VCPU_REGS_RIP:
2198                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2199                 break;
2200         case VCPU_EXREG_PDPTR:
2201                 if (enable_ept)
2202                         ept_save_pdptrs(vcpu);
2203                 break;
2204         case VCPU_EXREG_CR3:
2205                 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2206                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2207                 break;
2208         default:
2209                 WARN_ON_ONCE(1);
2210                 break;
2211         }
2212 }
2213
2214 static __init int cpu_has_kvm_support(void)
2215 {
2216         return cpu_has_vmx();
2217 }
2218
2219 static __init int vmx_disabled_by_bios(void)
2220 {
2221         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2222                !boot_cpu_has(X86_FEATURE_VMX);
2223 }
2224
2225 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2226 {
2227         u64 msr;
2228
2229         cr4_set_bits(X86_CR4_VMXE);
2230         intel_pt_handle_vmx(1);
2231
2232         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2233                           _ASM_EXTABLE(1b, %l[fault])
2234                           : : [vmxon_pointer] "m"(vmxon_pointer)
2235                           : : fault);
2236         return 0;
2237
2238 fault:
2239         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2240                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2241         intel_pt_handle_vmx(0);
2242         cr4_clear_bits(X86_CR4_VMXE);
2243
2244         return -EFAULT;
2245 }
2246
2247 static int hardware_enable(void)
2248 {
2249         int cpu = raw_smp_processor_id();
2250         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2251         int r;
2252
2253         if (cr4_read_shadow() & X86_CR4_VMXE)
2254                 return -EBUSY;
2255
2256         /*
2257          * This can happen if we hot-added a CPU but failed to allocate
2258          * VP assist page for it.
2259          */
2260         if (static_branch_unlikely(&enable_evmcs) &&
2261             !hv_get_vp_assist_page(cpu))
2262                 return -EFAULT;
2263
2264         r = kvm_cpu_vmxon(phys_addr);
2265         if (r)
2266                 return r;
2267
2268         if (enable_ept)
2269                 ept_sync_global();
2270
2271         return 0;
2272 }
2273
2274 static void vmclear_local_loaded_vmcss(void)
2275 {
2276         int cpu = raw_smp_processor_id();
2277         struct loaded_vmcs *v, *n;
2278
2279         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2280                                  loaded_vmcss_on_cpu_link)
2281                 __loaded_vmcs_clear(v);
2282 }
2283
2284
2285 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2286  * tricks.
2287  */
2288 static void kvm_cpu_vmxoff(void)
2289 {
2290         asm volatile (__ex("vmxoff"));
2291
2292         intel_pt_handle_vmx(0);
2293         cr4_clear_bits(X86_CR4_VMXE);
2294 }
2295
2296 static void hardware_disable(void)
2297 {
2298         vmclear_local_loaded_vmcss();
2299         kvm_cpu_vmxoff();
2300 }
2301
2302 /*
2303  * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2304  * directly instead of going through cpu_has(), to ensure KVM is trapping
2305  * ENCLS whenever it's supported in hardware.  It does not matter whether
2306  * the host OS supports or has enabled SGX.
2307  */
2308 static bool cpu_has_sgx(void)
2309 {
2310         return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2311 }
2312
2313 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2314                                       u32 msr, u32 *result)
2315 {
2316         u32 vmx_msr_low, vmx_msr_high;
2317         u32 ctl = ctl_min | ctl_opt;
2318
2319         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2320
2321         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2322         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2323
2324         /* Ensure minimum (required) set of control bits are supported. */
2325         if (ctl_min & ~ctl)
2326                 return -EIO;
2327
2328         *result = ctl;
2329         return 0;
2330 }
2331
2332 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2333                                     struct vmx_capability *vmx_cap)
2334 {
2335         u32 vmx_msr_low, vmx_msr_high;
2336         u32 min, opt, min2, opt2;
2337         u32 _pin_based_exec_control = 0;
2338         u32 _cpu_based_exec_control = 0;
2339         u32 _cpu_based_2nd_exec_control = 0;
2340         u32 _vmexit_control = 0;
2341         u32 _vmentry_control = 0;
2342
2343         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2344         min = CPU_BASED_HLT_EXITING |
2345 #ifdef CONFIG_X86_64
2346               CPU_BASED_CR8_LOAD_EXITING |
2347               CPU_BASED_CR8_STORE_EXITING |
2348 #endif
2349               CPU_BASED_CR3_LOAD_EXITING |
2350               CPU_BASED_CR3_STORE_EXITING |
2351               CPU_BASED_UNCOND_IO_EXITING |
2352               CPU_BASED_MOV_DR_EXITING |
2353               CPU_BASED_USE_TSC_OFFSETTING |
2354               CPU_BASED_MWAIT_EXITING |
2355               CPU_BASED_MONITOR_EXITING |
2356               CPU_BASED_INVLPG_EXITING |
2357               CPU_BASED_RDPMC_EXITING;
2358
2359         opt = CPU_BASED_TPR_SHADOW |
2360               CPU_BASED_USE_MSR_BITMAPS |
2361               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2362         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2363                                 &_cpu_based_exec_control) < 0)
2364                 return -EIO;
2365 #ifdef CONFIG_X86_64
2366         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2367                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2368                                            ~CPU_BASED_CR8_STORE_EXITING;
2369 #endif
2370         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2371                 min2 = 0;
2372                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2373                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2374                         SECONDARY_EXEC_WBINVD_EXITING |
2375                         SECONDARY_EXEC_ENABLE_VPID |
2376                         SECONDARY_EXEC_ENABLE_EPT |
2377                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2378                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2379                         SECONDARY_EXEC_DESC |
2380                         SECONDARY_EXEC_RDTSCP |
2381                         SECONDARY_EXEC_ENABLE_INVPCID |
2382                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2383                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2384                         SECONDARY_EXEC_SHADOW_VMCS |
2385                         SECONDARY_EXEC_XSAVES |
2386                         SECONDARY_EXEC_RDSEED_EXITING |
2387                         SECONDARY_EXEC_RDRAND_EXITING |
2388                         SECONDARY_EXEC_ENABLE_PML |
2389                         SECONDARY_EXEC_TSC_SCALING |
2390                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2391                         SECONDARY_EXEC_PT_USE_GPA |
2392                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2393                         SECONDARY_EXEC_ENABLE_VMFUNC;
2394                 if (cpu_has_sgx())
2395                         opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2396                 if (adjust_vmx_controls(min2, opt2,
2397                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2398                                         &_cpu_based_2nd_exec_control) < 0)
2399                         return -EIO;
2400         }
2401 #ifndef CONFIG_X86_64
2402         if (!(_cpu_based_2nd_exec_control &
2403                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2404                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2405 #endif
2406
2407         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2408                 _cpu_based_2nd_exec_control &= ~(
2409                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2410                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2411                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2412
2413         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2414                 &vmx_cap->ept, &vmx_cap->vpid);
2415
2416         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2417                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2418                    enabled */
2419                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2420                                              CPU_BASED_CR3_STORE_EXITING |
2421                                              CPU_BASED_INVLPG_EXITING);
2422         } else if (vmx_cap->ept) {
2423                 vmx_cap->ept = 0;
2424                 pr_warn_once("EPT CAP should not exist if not support "
2425                                 "1-setting enable EPT VM-execution control\n");
2426         }
2427         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2428                 vmx_cap->vpid) {
2429                 vmx_cap->vpid = 0;
2430                 pr_warn_once("VPID CAP should not exist if not support "
2431                                 "1-setting enable VPID VM-execution control\n");
2432         }
2433
2434         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2435 #ifdef CONFIG_X86_64
2436         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2437 #endif
2438         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2439               VM_EXIT_LOAD_IA32_PAT |
2440               VM_EXIT_LOAD_IA32_EFER |
2441               VM_EXIT_CLEAR_BNDCFGS |
2442               VM_EXIT_PT_CONCEAL_PIP |
2443               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2444         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2445                                 &_vmexit_control) < 0)
2446                 return -EIO;
2447
2448         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2449         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2450                  PIN_BASED_VMX_PREEMPTION_TIMER;
2451         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2452                                 &_pin_based_exec_control) < 0)
2453                 return -EIO;
2454
2455         if (cpu_has_broken_vmx_preemption_timer())
2456                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2457         if (!(_cpu_based_2nd_exec_control &
2458                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2459                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2460
2461         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2462         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2463               VM_ENTRY_LOAD_IA32_PAT |
2464               VM_ENTRY_LOAD_IA32_EFER |
2465               VM_ENTRY_LOAD_BNDCFGS |
2466               VM_ENTRY_PT_CONCEAL_PIP |
2467               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2468         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2469                                 &_vmentry_control) < 0)
2470                 return -EIO;
2471
2472         /*
2473          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2474          * can't be used due to an errata where VM Exit may incorrectly clear
2475          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2476          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2477          */
2478         if (boot_cpu_data.x86 == 0x6) {
2479                 switch (boot_cpu_data.x86_model) {
2480                 case 26: /* AAK155 */
2481                 case 30: /* AAP115 */
2482                 case 37: /* AAT100 */
2483                 case 44: /* BC86,AAY89,BD102 */
2484                 case 46: /* BA97 */
2485                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2486                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2487                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2488                                         "does not work properly. Using workaround\n");
2489                         break;
2490                 default:
2491                         break;
2492                 }
2493         }
2494
2495
2496         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2497
2498         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2499         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2500                 return -EIO;
2501
2502 #ifdef CONFIG_X86_64
2503         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2504         if (vmx_msr_high & (1u<<16))
2505                 return -EIO;
2506 #endif
2507
2508         /* Require Write-Back (WB) memory type for VMCS accesses. */
2509         if (((vmx_msr_high >> 18) & 15) != 6)
2510                 return -EIO;
2511
2512         vmcs_conf->size = vmx_msr_high & 0x1fff;
2513         vmcs_conf->order = get_order(vmcs_conf->size);
2514         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2515
2516         vmcs_conf->revision_id = vmx_msr_low;
2517
2518         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2519         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2520         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2521         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2522         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2523
2524         if (static_branch_unlikely(&enable_evmcs))
2525                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2526
2527         return 0;
2528 }
2529
2530 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2531 {
2532         int node = cpu_to_node(cpu);
2533         struct page *pages;
2534         struct vmcs *vmcs;
2535
2536         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2537         if (!pages)
2538                 return NULL;
2539         vmcs = page_address(pages);
2540         memset(vmcs, 0, vmcs_config.size);
2541
2542         /* KVM supports Enlightened VMCS v1 only */
2543         if (static_branch_unlikely(&enable_evmcs))
2544                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2545         else
2546                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2547
2548         if (shadow)
2549                 vmcs->hdr.shadow_vmcs = 1;
2550         return vmcs;
2551 }
2552
2553 void free_vmcs(struct vmcs *vmcs)
2554 {
2555         free_pages((unsigned long)vmcs, vmcs_config.order);
2556 }
2557
2558 /*
2559  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2560  */
2561 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2562 {
2563         if (!loaded_vmcs->vmcs)
2564                 return;
2565         loaded_vmcs_clear(loaded_vmcs);
2566         free_vmcs(loaded_vmcs->vmcs);
2567         loaded_vmcs->vmcs = NULL;
2568         if (loaded_vmcs->msr_bitmap)
2569                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2570         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2571 }
2572
2573 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2574 {
2575         loaded_vmcs->vmcs = alloc_vmcs(false);
2576         if (!loaded_vmcs->vmcs)
2577                 return -ENOMEM;
2578
2579         vmcs_clear(loaded_vmcs->vmcs);
2580
2581         loaded_vmcs->shadow_vmcs = NULL;
2582         loaded_vmcs->hv_timer_soft_disabled = false;
2583         loaded_vmcs->cpu = -1;
2584         loaded_vmcs->launched = 0;
2585
2586         if (cpu_has_vmx_msr_bitmap()) {
2587                 loaded_vmcs->msr_bitmap = (unsigned long *)
2588                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2589                 if (!loaded_vmcs->msr_bitmap)
2590                         goto out_vmcs;
2591                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2592
2593                 if (IS_ENABLED(CONFIG_HYPERV) &&
2594                     static_branch_unlikely(&enable_evmcs) &&
2595                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2596                         struct hv_enlightened_vmcs *evmcs =
2597                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2598
2599                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2600                 }
2601         }
2602
2603         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2604         memset(&loaded_vmcs->controls_shadow, 0,
2605                 sizeof(struct vmcs_controls_shadow));
2606
2607         return 0;
2608
2609 out_vmcs:
2610         free_loaded_vmcs(loaded_vmcs);
2611         return -ENOMEM;
2612 }
2613
2614 static void free_kvm_area(void)
2615 {
2616         int cpu;
2617
2618         for_each_possible_cpu(cpu) {
2619                 free_vmcs(per_cpu(vmxarea, cpu));
2620                 per_cpu(vmxarea, cpu) = NULL;
2621         }
2622 }
2623
2624 static __init int alloc_kvm_area(void)
2625 {
2626         int cpu;
2627
2628         for_each_possible_cpu(cpu) {
2629                 struct vmcs *vmcs;
2630
2631                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2632                 if (!vmcs) {
2633                         free_kvm_area();
2634                         return -ENOMEM;
2635                 }
2636
2637                 /*
2638                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2639                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2640                  * revision_id reported by MSR_IA32_VMX_BASIC.
2641                  *
2642                  * However, even though not explicitly documented by
2643                  * TLFS, VMXArea passed as VMXON argument should
2644                  * still be marked with revision_id reported by
2645                  * physical CPU.
2646                  */
2647                 if (static_branch_unlikely(&enable_evmcs))
2648                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2649
2650                 per_cpu(vmxarea, cpu) = vmcs;
2651         }
2652         return 0;
2653 }
2654
2655 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2656                 struct kvm_segment *save)
2657 {
2658         if (!emulate_invalid_guest_state) {
2659                 /*
2660                  * CS and SS RPL should be equal during guest entry according
2661                  * to VMX spec, but in reality it is not always so. Since vcpu
2662                  * is in the middle of the transition from real mode to
2663                  * protected mode it is safe to assume that RPL 0 is a good
2664                  * default value.
2665                  */
2666                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2667                         save->selector &= ~SEGMENT_RPL_MASK;
2668                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2669                 save->s = 1;
2670         }
2671         vmx_set_segment(vcpu, save, seg);
2672 }
2673
2674 static void enter_pmode(struct kvm_vcpu *vcpu)
2675 {
2676         unsigned long flags;
2677         struct vcpu_vmx *vmx = to_vmx(vcpu);
2678
2679         /*
2680          * Update real mode segment cache. It may be not up-to-date if sement
2681          * register was written while vcpu was in a guest mode.
2682          */
2683         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2684         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2685         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2686         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2687         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2688         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2689
2690         vmx->rmode.vm86_active = 0;
2691
2692         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2693
2694         flags = vmcs_readl(GUEST_RFLAGS);
2695         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2696         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2697         vmcs_writel(GUEST_RFLAGS, flags);
2698
2699         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2700                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2701
2702         update_exception_bitmap(vcpu);
2703
2704         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2705         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2706         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2707         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2708         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2709         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2710 }
2711
2712 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2713 {
2714         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2715         struct kvm_segment var = *save;
2716
2717         var.dpl = 0x3;
2718         if (seg == VCPU_SREG_CS)
2719                 var.type = 0x3;
2720
2721         if (!emulate_invalid_guest_state) {
2722                 var.selector = var.base >> 4;
2723                 var.base = var.base & 0xffff0;
2724                 var.limit = 0xffff;
2725                 var.g = 0;
2726                 var.db = 0;
2727                 var.present = 1;
2728                 var.s = 1;
2729                 var.l = 0;
2730                 var.unusable = 0;
2731                 var.type = 0x3;
2732                 var.avl = 0;
2733                 if (save->base & 0xf)
2734                         printk_once(KERN_WARNING "kvm: segment base is not "
2735                                         "paragraph aligned when entering "
2736                                         "protected mode (seg=%d)", seg);
2737         }
2738
2739         vmcs_write16(sf->selector, var.selector);
2740         vmcs_writel(sf->base, var.base);
2741         vmcs_write32(sf->limit, var.limit);
2742         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2743 }
2744
2745 static void enter_rmode(struct kvm_vcpu *vcpu)
2746 {
2747         unsigned long flags;
2748         struct vcpu_vmx *vmx = to_vmx(vcpu);
2749         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2750
2751         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2752         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2753         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2754         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2755         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2756         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2757         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2758
2759         vmx->rmode.vm86_active = 1;
2760
2761         /*
2762          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2763          * vcpu. Warn the user that an update is overdue.
2764          */
2765         if (!kvm_vmx->tss_addr)
2766                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2767                              "called before entering vcpu\n");
2768
2769         vmx_segment_cache_clear(vmx);
2770
2771         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2772         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2773         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2774
2775         flags = vmcs_readl(GUEST_RFLAGS);
2776         vmx->rmode.save_rflags = flags;
2777
2778         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2779
2780         vmcs_writel(GUEST_RFLAGS, flags);
2781         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2782         update_exception_bitmap(vcpu);
2783
2784         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2785         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2786         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2787         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2788         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2789         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2790
2791         kvm_mmu_reset_context(vcpu);
2792 }
2793
2794 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2795 {
2796         struct vcpu_vmx *vmx = to_vmx(vcpu);
2797         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2798
2799         if (!msr)
2800                 return;
2801
2802         vcpu->arch.efer = efer;
2803         if (efer & EFER_LMA) {
2804                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2805                 msr->data = efer;
2806         } else {
2807                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2808
2809                 msr->data = efer & ~EFER_LME;
2810         }
2811         setup_msrs(vmx);
2812 }
2813
2814 #ifdef CONFIG_X86_64
2815
2816 static void enter_lmode(struct kvm_vcpu *vcpu)
2817 {
2818         u32 guest_tr_ar;
2819
2820         vmx_segment_cache_clear(to_vmx(vcpu));
2821
2822         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2823         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2824                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2825                                      __func__);
2826                 vmcs_write32(GUEST_TR_AR_BYTES,
2827                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2828                              | VMX_AR_TYPE_BUSY_64_TSS);
2829         }
2830         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2831 }
2832
2833 static void exit_lmode(struct kvm_vcpu *vcpu)
2834 {
2835         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2836         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2837 }
2838
2839 #endif
2840
2841 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2842 {
2843         int vpid = to_vmx(vcpu)->vpid;
2844
2845         if (!vpid_sync_vcpu_addr(vpid, addr))
2846                 vpid_sync_context(vpid);
2847
2848         /*
2849          * If VPIDs are not supported or enabled, then the above is a no-op.
2850          * But we don't really need a TLB flush in that case anyway, because
2851          * each VM entry/exit includes an implicit flush when VPID is 0.
2852          */
2853 }
2854
2855 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2856 {
2857         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2858
2859         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2860         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2861 }
2862
2863 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2864 {
2865         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2866
2867         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2868         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2869 }
2870
2871 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2872 {
2873         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2874
2875         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2876                 return;
2877
2878         if (is_pae_paging(vcpu)) {
2879                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2880                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2881                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2882                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2883         }
2884 }
2885
2886 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2887 {
2888         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2889
2890         if (is_pae_paging(vcpu)) {
2891                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2892                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2893                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2894                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2895         }
2896
2897         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2898 }
2899
2900 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2901                                         unsigned long cr0,
2902                                         struct kvm_vcpu *vcpu)
2903 {
2904         struct vcpu_vmx *vmx = to_vmx(vcpu);
2905
2906         if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2907                 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2908         if (!(cr0 & X86_CR0_PG)) {
2909                 /* From paging/starting to nonpaging */
2910                 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2911                                           CPU_BASED_CR3_STORE_EXITING);
2912                 vcpu->arch.cr0 = cr0;
2913                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2914         } else if (!is_paging(vcpu)) {
2915                 /* From nonpaging to paging */
2916                 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2917                                             CPU_BASED_CR3_STORE_EXITING);
2918                 vcpu->arch.cr0 = cr0;
2919                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2920         }
2921
2922         if (!(cr0 & X86_CR0_WP))
2923                 *hw_cr0 &= ~X86_CR0_WP;
2924 }
2925
2926 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2927 {
2928         struct vcpu_vmx *vmx = to_vmx(vcpu);
2929         unsigned long hw_cr0;
2930
2931         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2932         if (enable_unrestricted_guest)
2933                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2934         else {
2935                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2936
2937                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2938                         enter_pmode(vcpu);
2939
2940                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2941                         enter_rmode(vcpu);
2942         }
2943
2944 #ifdef CONFIG_X86_64
2945         if (vcpu->arch.efer & EFER_LME) {
2946                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2947                         enter_lmode(vcpu);
2948                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2949                         exit_lmode(vcpu);
2950         }
2951 #endif
2952
2953         if (enable_ept && !enable_unrestricted_guest)
2954                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2955
2956         vmcs_writel(CR0_READ_SHADOW, cr0);
2957         vmcs_writel(GUEST_CR0, hw_cr0);
2958         vcpu->arch.cr0 = cr0;
2959
2960         /* depends on vcpu->arch.cr0 to be set to a new value */
2961         vmx->emulation_required = emulation_required(vcpu);
2962 }
2963
2964 static int get_ept_level(struct kvm_vcpu *vcpu)
2965 {
2966         if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu)))
2967                 return vmx_eptp_page_walk_level(nested_ept_get_eptp(vcpu));
2968         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2969                 return 5;
2970         return 4;
2971 }
2972
2973 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2974 {
2975         u64 eptp = VMX_EPTP_MT_WB;
2976
2977         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2978
2979         if (enable_ept_ad_bits &&
2980             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2981                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2982         eptp |= (root_hpa & PAGE_MASK);
2983
2984         return eptp;
2985 }
2986
2987 void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long cr3)
2988 {
2989         struct kvm *kvm = vcpu->kvm;
2990         bool update_guest_cr3 = true;
2991         unsigned long guest_cr3;
2992         u64 eptp;
2993
2994         guest_cr3 = cr3;
2995         if (enable_ept) {
2996                 eptp = construct_eptp(vcpu, cr3);
2997                 vmcs_write64(EPT_POINTER, eptp);
2998
2999                 if (kvm_x86_ops.tlb_remote_flush) {
3000                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3001                         to_vmx(vcpu)->ept_pointer = eptp;
3002                         to_kvm_vmx(kvm)->ept_pointers_match
3003                                 = EPT_POINTERS_CHECK;
3004                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3005                 }
3006
3007                 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3008                 if (is_guest_mode(vcpu))
3009                         update_guest_cr3 = false;
3010                 else if (!enable_unrestricted_guest && !is_paging(vcpu))
3011                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3012                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3013                         guest_cr3 = vcpu->arch.cr3;
3014                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3015                         update_guest_cr3 = false;
3016                 ept_load_pdptrs(vcpu);
3017         }
3018
3019         if (update_guest_cr3)
3020                 vmcs_writel(GUEST_CR3, guest_cr3);
3021 }
3022
3023 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3024 {
3025         struct vcpu_vmx *vmx = to_vmx(vcpu);
3026         /*
3027          * Pass through host's Machine Check Enable value to hw_cr4, which
3028          * is in force while we are in guest mode.  Do not let guests control
3029          * this bit, even if host CR4.MCE == 0.
3030          */
3031         unsigned long hw_cr4;
3032
3033         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3034         if (enable_unrestricted_guest)
3035                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3036         else if (vmx->rmode.vm86_active)
3037                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3038         else
3039                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3040
3041         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3042                 if (cr4 & X86_CR4_UMIP) {
3043                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3044                         hw_cr4 &= ~X86_CR4_UMIP;
3045                 } else if (!is_guest_mode(vcpu) ||
3046                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3047                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3048                 }
3049         }
3050
3051         if (cr4 & X86_CR4_VMXE) {
3052                 /*
3053                  * To use VMXON (and later other VMX instructions), a guest
3054                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3055                  * So basically the check on whether to allow nested VMX
3056                  * is here.  We operate under the default treatment of SMM,
3057                  * so VMX cannot be enabled under SMM.
3058                  */
3059                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3060                         return 1;
3061         }
3062
3063         if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3064                 return 1;
3065
3066         vcpu->arch.cr4 = cr4;
3067
3068         if (!enable_unrestricted_guest) {
3069                 if (enable_ept) {
3070                         if (!is_paging(vcpu)) {
3071                                 hw_cr4 &= ~X86_CR4_PAE;
3072                                 hw_cr4 |= X86_CR4_PSE;
3073                         } else if (!(cr4 & X86_CR4_PAE)) {
3074                                 hw_cr4 &= ~X86_CR4_PAE;
3075                         }
3076                 }
3077
3078                 /*
3079                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3080                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3081                  * to be manually disabled when guest switches to non-paging
3082                  * mode.
3083                  *
3084                  * If !enable_unrestricted_guest, the CPU is always running
3085                  * with CR0.PG=1 and CR4 needs to be modified.
3086                  * If enable_unrestricted_guest, the CPU automatically
3087                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3088                  */
3089                 if (!is_paging(vcpu))
3090                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3091         }
3092
3093         vmcs_writel(CR4_READ_SHADOW, cr4);
3094         vmcs_writel(GUEST_CR4, hw_cr4);
3095         return 0;
3096 }
3097
3098 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3099 {
3100         struct vcpu_vmx *vmx = to_vmx(vcpu);
3101         u32 ar;
3102
3103         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3104                 *var = vmx->rmode.segs[seg];
3105                 if (seg == VCPU_SREG_TR
3106                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3107                         return;
3108                 var->base = vmx_read_guest_seg_base(vmx, seg);
3109                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3110                 return;
3111         }
3112         var->base = vmx_read_guest_seg_base(vmx, seg);
3113         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3114         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3115         ar = vmx_read_guest_seg_ar(vmx, seg);
3116         var->unusable = (ar >> 16) & 1;
3117         var->type = ar & 15;
3118         var->s = (ar >> 4) & 1;
3119         var->dpl = (ar >> 5) & 3;
3120         /*
3121          * Some userspaces do not preserve unusable property. Since usable
3122          * segment has to be present according to VMX spec we can use present
3123          * property to amend userspace bug by making unusable segment always
3124          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3125          * segment as unusable.
3126          */
3127         var->present = !var->unusable;
3128         var->avl = (ar >> 12) & 1;
3129         var->l = (ar >> 13) & 1;
3130         var->db = (ar >> 14) & 1;
3131         var->g = (ar >> 15) & 1;
3132 }
3133
3134 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3135 {
3136         struct kvm_segment s;
3137
3138         if (to_vmx(vcpu)->rmode.vm86_active) {
3139                 vmx_get_segment(vcpu, &s, seg);
3140                 return s.base;
3141         }
3142         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3143 }
3144
3145 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3146 {
3147         struct vcpu_vmx *vmx = to_vmx(vcpu);
3148
3149         if (unlikely(vmx->rmode.vm86_active))
3150                 return 0;
3151         else {
3152                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3153                 return VMX_AR_DPL(ar);
3154         }
3155 }
3156
3157 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3158 {
3159         u32 ar;
3160
3161         if (var->unusable || !var->present)
3162                 ar = 1 << 16;
3163         else {
3164                 ar = var->type & 15;
3165                 ar |= (var->s & 1) << 4;
3166                 ar |= (var->dpl & 3) << 5;
3167                 ar |= (var->present & 1) << 7;
3168                 ar |= (var->avl & 1) << 12;
3169                 ar |= (var->l & 1) << 13;
3170                 ar |= (var->db & 1) << 14;
3171                 ar |= (var->g & 1) << 15;
3172         }
3173
3174         return ar;
3175 }
3176
3177 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3178 {
3179         struct vcpu_vmx *vmx = to_vmx(vcpu);
3180         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3181
3182         vmx_segment_cache_clear(vmx);
3183
3184         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3185                 vmx->rmode.segs[seg] = *var;
3186                 if (seg == VCPU_SREG_TR)
3187                         vmcs_write16(sf->selector, var->selector);
3188                 else if (var->s)
3189                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3190                 goto out;
3191         }
3192
3193         vmcs_writel(sf->base, var->base);
3194         vmcs_write32(sf->limit, var->limit);
3195         vmcs_write16(sf->selector, var->selector);
3196
3197         /*
3198          *   Fix the "Accessed" bit in AR field of segment registers for older
3199          * qemu binaries.
3200          *   IA32 arch specifies that at the time of processor reset the
3201          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3202          * is setting it to 0 in the userland code. This causes invalid guest
3203          * state vmexit when "unrestricted guest" mode is turned on.
3204          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3205          * tree. Newer qemu binaries with that qemu fix would not need this
3206          * kvm hack.
3207          */
3208         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3209                 var->type |= 0x1; /* Accessed */
3210
3211         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3212
3213 out:
3214         vmx->emulation_required = emulation_required(vcpu);
3215 }
3216
3217 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3218 {
3219         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3220
3221         *db = (ar >> 14) & 1;
3222         *l = (ar >> 13) & 1;
3223 }
3224
3225 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3226 {
3227         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3228         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3229 }
3230
3231 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3232 {
3233         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3234         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3235 }
3236
3237 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3238 {
3239         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3240         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3241 }
3242
3243 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3244 {
3245         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3246         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3247 }
3248
3249 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3250 {
3251         struct kvm_segment var;
3252         u32 ar;
3253
3254         vmx_get_segment(vcpu, &var, seg);
3255         var.dpl = 0x3;
3256         if (seg == VCPU_SREG_CS)
3257                 var.type = 0x3;
3258         ar = vmx_segment_access_rights(&var);
3259
3260         if (var.base != (var.selector << 4))
3261                 return false;
3262         if (var.limit != 0xffff)
3263                 return false;
3264         if (ar != 0xf3)
3265                 return false;
3266
3267         return true;
3268 }
3269
3270 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3271 {
3272         struct kvm_segment cs;
3273         unsigned int cs_rpl;
3274
3275         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3276         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3277
3278         if (cs.unusable)
3279                 return false;
3280         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3281                 return false;
3282         if (!cs.s)
3283                 return false;
3284         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3285                 if (cs.dpl > cs_rpl)
3286                         return false;
3287         } else {
3288                 if (cs.dpl != cs_rpl)
3289                         return false;
3290         }
3291         if (!cs.present)
3292                 return false;
3293
3294         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3295         return true;
3296 }
3297
3298 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3299 {
3300         struct kvm_segment ss;
3301         unsigned int ss_rpl;
3302
3303         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3304         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3305
3306         if (ss.unusable)
3307                 return true;
3308         if (ss.type != 3 && ss.type != 7)
3309                 return false;
3310         if (!ss.s)
3311                 return false;
3312         if (ss.dpl != ss_rpl) /* DPL != RPL */
3313                 return false;
3314         if (!ss.present)
3315                 return false;
3316
3317         return true;
3318 }
3319
3320 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3321 {
3322         struct kvm_segment var;
3323         unsigned int rpl;
3324
3325         vmx_get_segment(vcpu, &var, seg);
3326         rpl = var.selector & SEGMENT_RPL_MASK;
3327
3328         if (var.unusable)
3329                 return true;
3330         if (!var.s)
3331                 return false;
3332         if (!var.present)
3333                 return false;
3334         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3335                 if (var.dpl < rpl) /* DPL < RPL */
3336                         return false;
3337         }
3338
3339         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3340          * rights flags
3341          */
3342         return true;
3343 }
3344
3345 static bool tr_valid(struct kvm_vcpu *vcpu)
3346 {
3347         struct kvm_segment tr;
3348
3349         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3350
3351         if (tr.unusable)
3352                 return false;
3353         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3354                 return false;
3355         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3356                 return false;
3357         if (!tr.present)
3358                 return false;
3359
3360         return true;
3361 }
3362
3363 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3364 {
3365         struct kvm_segment ldtr;
3366
3367         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3368
3369         if (ldtr.unusable)
3370                 return true;
3371         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3372                 return false;
3373         if (ldtr.type != 2)
3374                 return false;
3375         if (!ldtr.present)
3376                 return false;
3377
3378         return true;
3379 }
3380
3381 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3382 {
3383         struct kvm_segment cs, ss;
3384
3385         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3386         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3387
3388         return ((cs.selector & SEGMENT_RPL_MASK) ==
3389                  (ss.selector & SEGMENT_RPL_MASK));
3390 }
3391
3392 /*
3393  * Check if guest state is valid. Returns true if valid, false if
3394  * not.
3395  * We assume that registers are always usable
3396  */
3397 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3398 {
3399         if (enable_unrestricted_guest)
3400                 return true;
3401
3402         /* real mode guest state checks */
3403         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3404                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3405                         return false;
3406                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3407                         return false;
3408                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3409                         return false;
3410                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3411                         return false;
3412                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3413                         return false;
3414                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3415                         return false;
3416         } else {
3417         /* protected mode guest state checks */
3418                 if (!cs_ss_rpl_check(vcpu))
3419                         return false;
3420                 if (!code_segment_valid(vcpu))
3421                         return false;
3422                 if (!stack_segment_valid(vcpu))
3423                         return false;
3424                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3425                         return false;
3426                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3427                         return false;
3428                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3429                         return false;
3430                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3431                         return false;
3432                 if (!tr_valid(vcpu))
3433                         return false;
3434                 if (!ldtr_valid(vcpu))
3435                         return false;
3436         }
3437         /* TODO:
3438          * - Add checks on RIP
3439          * - Add checks on RFLAGS
3440          */
3441
3442         return true;
3443 }
3444
3445 static int init_rmode_tss(struct kvm *kvm)
3446 {
3447         gfn_t fn;
3448         u16 data = 0;
3449         int idx, r;
3450
3451         idx = srcu_read_lock(&kvm->srcu);
3452         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3453         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3454         if (r < 0)
3455                 goto out;
3456         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3457         r = kvm_write_guest_page(kvm, fn++, &data,
3458                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3459         if (r < 0)
3460                 goto out;
3461         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3462         if (r < 0)
3463                 goto out;
3464         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3465         if (r < 0)
3466                 goto out;
3467         data = ~0;
3468         r = kvm_write_guest_page(kvm, fn, &data,
3469                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3470                                  sizeof(u8));
3471 out:
3472         srcu_read_unlock(&kvm->srcu, idx);
3473         return r;
3474 }
3475
3476 static int init_rmode_identity_map(struct kvm *kvm)
3477 {
3478         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3479         int i, r = 0;
3480         kvm_pfn_t identity_map_pfn;
3481         u32 tmp;
3482
3483         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3484         mutex_lock(&kvm->slots_lock);
3485
3486         if (likely(kvm_vmx->ept_identity_pagetable_done))
3487                 goto out;
3488
3489         if (!kvm_vmx->ept_identity_map_addr)
3490                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3491         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3492
3493         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3494                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3495         if (r < 0)
3496                 goto out;
3497
3498         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3499         if (r < 0)
3500                 goto out;
3501         /* Set up identity-mapping pagetable for EPT in real mode */
3502         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3503                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3504                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3505                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3506                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3507                 if (r < 0)
3508                         goto out;
3509         }
3510         kvm_vmx->ept_identity_pagetable_done = true;
3511
3512 out:
3513         mutex_unlock(&kvm->slots_lock);
3514         return r;
3515 }
3516
3517 static void seg_setup(int seg)
3518 {
3519         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3520         unsigned int ar;
3521
3522         vmcs_write16(sf->selector, 0);
3523         vmcs_writel(sf->base, 0);
3524         vmcs_write32(sf->limit, 0xffff);
3525         ar = 0x93;
3526         if (seg == VCPU_SREG_CS)
3527                 ar |= 0x08; /* code segment */
3528
3529         vmcs_write32(sf->ar_bytes, ar);
3530 }
3531
3532 static int alloc_apic_access_page(struct kvm *kvm)
3533 {
3534         struct page *page;
3535         int r = 0;
3536
3537         mutex_lock(&kvm->slots_lock);
3538         if (kvm->arch.apic_access_page_done)
3539                 goto out;
3540         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3541                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3542         if (r)
3543                 goto out;
3544
3545         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3546         if (is_error_page(page)) {
3547                 r = -EFAULT;
3548                 goto out;
3549         }
3550
3551         /*
3552          * Do not pin the page in memory, so that memory hot-unplug
3553          * is able to migrate it.
3554          */
3555         put_page(page);
3556         kvm->arch.apic_access_page_done = true;
3557 out:
3558         mutex_unlock(&kvm->slots_lock);
3559         return r;
3560 }
3561
3562 int allocate_vpid(void)
3563 {
3564         int vpid;
3565
3566         if (!enable_vpid)
3567                 return 0;
3568         spin_lock(&vmx_vpid_lock);
3569         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3570         if (vpid < VMX_NR_VPIDS)
3571                 __set_bit(vpid, vmx_vpid_bitmap);
3572         else
3573                 vpid = 0;
3574         spin_unlock(&vmx_vpid_lock);
3575         return vpid;
3576 }
3577
3578 void free_vpid(int vpid)
3579 {
3580         if (!enable_vpid || vpid == 0)
3581                 return;
3582         spin_lock(&vmx_vpid_lock);
3583         __clear_bit(vpid, vmx_vpid_bitmap);
3584         spin_unlock(&vmx_vpid_lock);
3585 }
3586
3587 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3588                                                           u32 msr, int type)
3589 {
3590         int f = sizeof(unsigned long);
3591
3592         if (!cpu_has_vmx_msr_bitmap())
3593                 return;
3594
3595         if (static_branch_unlikely(&enable_evmcs))
3596                 evmcs_touch_msr_bitmap();
3597
3598         /*
3599          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3600          * have the write-low and read-high bitmap offsets the wrong way round.
3601          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3602          */
3603         if (msr <= 0x1fff) {
3604                 if (type & MSR_TYPE_R)
3605                         /* read-low */
3606                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3607
3608                 if (type & MSR_TYPE_W)
3609                         /* write-low */
3610                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3611
3612         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3613                 msr &= 0x1fff;
3614                 if (type & MSR_TYPE_R)
3615                         /* read-high */
3616                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3617
3618                 if (type & MSR_TYPE_W)
3619                         /* write-high */
3620                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3621
3622         }
3623 }
3624
3625 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3626                                                          u32 msr, int type)
3627 {
3628         int f = sizeof(unsigned long);
3629
3630         if (!cpu_has_vmx_msr_bitmap())
3631                 return;
3632
3633         if (static_branch_unlikely(&enable_evmcs))
3634                 evmcs_touch_msr_bitmap();
3635
3636         /*
3637          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3638          * have the write-low and read-high bitmap offsets the wrong way round.
3639          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3640          */
3641         if (msr <= 0x1fff) {
3642                 if (type & MSR_TYPE_R)
3643                         /* read-low */
3644                         __set_bit(msr, msr_bitmap + 0x000 / f);
3645
3646                 if (type & MSR_TYPE_W)
3647                         /* write-low */
3648                         __set_bit(msr, msr_bitmap + 0x800 / f);
3649
3650         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3651                 msr &= 0x1fff;
3652                 if (type & MSR_TYPE_R)
3653                         /* read-high */
3654                         __set_bit(msr, msr_bitmap + 0x400 / f);
3655
3656                 if (type & MSR_TYPE_W)
3657                         /* write-high */
3658                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3659
3660         }
3661 }
3662
3663 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3664                                                       u32 msr, int type, bool value)
3665 {
3666         if (value)
3667                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3668         else
3669                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3670 }
3671
3672 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3673 {
3674         u8 mode = 0;
3675
3676         if (cpu_has_secondary_exec_ctrls() &&
3677             (secondary_exec_controls_get(to_vmx(vcpu)) &
3678              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3679                 mode |= MSR_BITMAP_MODE_X2APIC;
3680                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3681                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3682         }
3683
3684         return mode;
3685 }
3686
3687 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3688                                          u8 mode)
3689 {
3690         int msr;
3691
3692         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3693                 unsigned word = msr / BITS_PER_LONG;
3694                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3695                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3696         }
3697
3698         if (mode & MSR_BITMAP_MODE_X2APIC) {
3699                 /*
3700                  * TPR reads and writes can be virtualized even if virtual interrupt
3701                  * delivery is not in use.
3702                  */
3703                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3704                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3705                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3706                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3707                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3708                 }
3709         }
3710 }
3711
3712 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3713 {
3714         struct vcpu_vmx *vmx = to_vmx(vcpu);
3715         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3716         u8 mode = vmx_msr_bitmap_mode(vcpu);
3717         u8 changed = mode ^ vmx->msr_bitmap_mode;
3718
3719         if (!changed)
3720                 return;
3721
3722         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3723                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3724
3725         vmx->msr_bitmap_mode = mode;
3726 }
3727
3728 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3729 {
3730         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3731         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3732         u32 i;
3733
3734         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3735                                                         MSR_TYPE_RW, flag);
3736         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3737                                                         MSR_TYPE_RW, flag);
3738         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3739                                                         MSR_TYPE_RW, flag);
3740         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3741                                                         MSR_TYPE_RW, flag);
3742         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3743                 vmx_set_intercept_for_msr(msr_bitmap,
3744                         MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3745                 vmx_set_intercept_for_msr(msr_bitmap,
3746                         MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3747         }
3748 }
3749
3750 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3751 {
3752         struct vcpu_vmx *vmx = to_vmx(vcpu);
3753         void *vapic_page;
3754         u32 vppr;
3755         int rvi;
3756
3757         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3758                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3759                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3760                 return false;
3761
3762         rvi = vmx_get_rvi();
3763
3764         vapic_page = vmx->nested.virtual_apic_map.hva;
3765         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3766
3767         return ((rvi & 0xf0) > (vppr & 0xf0));
3768 }
3769
3770 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3771                                                      bool nested)
3772 {
3773 #ifdef CONFIG_SMP
3774         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3775
3776         if (vcpu->mode == IN_GUEST_MODE) {
3777                 /*
3778                  * The vector of interrupt to be delivered to vcpu had
3779                  * been set in PIR before this function.
3780                  *
3781                  * Following cases will be reached in this block, and
3782                  * we always send a notification event in all cases as
3783                  * explained below.
3784                  *
3785                  * Case 1: vcpu keeps in non-root mode. Sending a
3786                  * notification event posts the interrupt to vcpu.
3787                  *
3788                  * Case 2: vcpu exits to root mode and is still
3789                  * runnable. PIR will be synced to vIRR before the
3790                  * next vcpu entry. Sending a notification event in
3791                  * this case has no effect, as vcpu is not in root
3792                  * mode.
3793                  *
3794                  * Case 3: vcpu exits to root mode and is blocked.
3795                  * vcpu_block() has already synced PIR to vIRR and
3796                  * never blocks vcpu if vIRR is not cleared. Therefore,
3797                  * a blocked vcpu here does not wait for any requested
3798                  * interrupts in PIR, and sending a notification event
3799                  * which has no effect is safe here.
3800                  */
3801
3802                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3803                 return true;
3804         }
3805 #endif
3806         return false;
3807 }
3808
3809 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3810                                                 int vector)
3811 {
3812         struct vcpu_vmx *vmx = to_vmx(vcpu);
3813
3814         if (is_guest_mode(vcpu) &&
3815             vector == vmx->nested.posted_intr_nv) {
3816                 /*
3817                  * If a posted intr is not recognized by hardware,
3818                  * we will accomplish it in the next vmentry.
3819                  */
3820                 vmx->nested.pi_pending = true;
3821                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3822                 /* the PIR and ON have been set by L1. */
3823                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3824                         kvm_vcpu_kick(vcpu);
3825                 return 0;
3826         }
3827         return -1;
3828 }
3829 /*
3830  * Send interrupt to vcpu via posted interrupt way.
3831  * 1. If target vcpu is running(non-root mode), send posted interrupt
3832  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3833  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3834  * interrupt from PIR in next vmentry.
3835  */
3836 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3837 {
3838         struct vcpu_vmx *vmx = to_vmx(vcpu);
3839         int r;
3840
3841         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3842         if (!r)
3843                 return 0;
3844
3845         if (!vcpu->arch.apicv_active)
3846                 return -1;
3847
3848         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3849                 return 0;
3850
3851         /* If a previous notification has sent the IPI, nothing to do.  */
3852         if (pi_test_and_set_on(&vmx->pi_desc))
3853                 return 0;
3854
3855         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3856                 kvm_vcpu_kick(vcpu);
3857
3858         return 0;
3859 }
3860
3861 /*
3862  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3863  * will not change in the lifetime of the guest.
3864  * Note that host-state that does change is set elsewhere. E.g., host-state
3865  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3866  */
3867 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3868 {
3869         u32 low32, high32;
3870         unsigned long tmpl;
3871         unsigned long cr0, cr3, cr4;
3872
3873         cr0 = read_cr0();
3874         WARN_ON(cr0 & X86_CR0_TS);
3875         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3876
3877         /*
3878          * Save the most likely value for this task's CR3 in the VMCS.
3879          * We can't use __get_current_cr3_fast() because we're not atomic.
3880          */
3881         cr3 = __read_cr3();
3882         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
3883         vmx->loaded_vmcs->host_state.cr3 = cr3;
3884
3885         /* Save the most likely value for this task's CR4 in the VMCS. */
3886         cr4 = cr4_read_shadow();
3887         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
3888         vmx->loaded_vmcs->host_state.cr4 = cr4;
3889
3890         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3891 #ifdef CONFIG_X86_64
3892         /*
3893          * Load null selectors, so we can avoid reloading them in
3894          * vmx_prepare_switch_to_host(), in case userspace uses
3895          * the null selectors too (the expected case).
3896          */
3897         vmcs_write16(HOST_DS_SELECTOR, 0);
3898         vmcs_write16(HOST_ES_SELECTOR, 0);
3899 #else
3900         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3901         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3902 #endif
3903         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3904         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3905
3906         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
3907
3908         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3909
3910         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3911         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3912         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3913         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3914
3915         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3916                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3917                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3918         }
3919
3920         if (cpu_has_load_ia32_efer())
3921                 vmcs_write64(HOST_IA32_EFER, host_efer);
3922 }
3923
3924 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3925 {
3926         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3927         if (enable_ept)
3928                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3929         if (is_guest_mode(&vmx->vcpu))
3930                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3931                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3932         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3933 }
3934
3935 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3936 {
3937         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3938
3939         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3940                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3941
3942         if (!enable_vnmi)
3943                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3944
3945         if (!enable_preemption_timer)
3946                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3947
3948         return pin_based_exec_ctrl;
3949 }
3950
3951 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3952 {
3953         struct vcpu_vmx *vmx = to_vmx(vcpu);
3954
3955         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3956         if (cpu_has_secondary_exec_ctrls()) {
3957                 if (kvm_vcpu_apicv_active(vcpu))
3958                         secondary_exec_controls_setbit(vmx,
3959                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
3960                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3961                 else
3962                         secondary_exec_controls_clearbit(vmx,
3963                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3964                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3965         }
3966
3967         if (cpu_has_vmx_msr_bitmap())
3968                 vmx_update_msr_bitmap(vcpu);
3969 }
3970
3971 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3972 {
3973         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3974
3975         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3976                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3977
3978         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3979                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3980 #ifdef CONFIG_X86_64
3981                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3982                                 CPU_BASED_CR8_LOAD_EXITING;
3983 #endif
3984         }
3985         if (!enable_ept)
3986                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3987                                 CPU_BASED_CR3_LOAD_EXITING  |
3988                                 CPU_BASED_INVLPG_EXITING;
3989         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3990                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3991                                 CPU_BASED_MONITOR_EXITING);
3992         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3993                 exec_control &= ~CPU_BASED_HLT_EXITING;
3994         return exec_control;
3995 }
3996
3997
3998 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
3999 {
4000         struct kvm_vcpu *vcpu = &vmx->vcpu;
4001
4002         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4003
4004         if (vmx_pt_mode_is_system())
4005                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4006         if (!cpu_need_virtualize_apic_accesses(vcpu))
4007                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4008         if (vmx->vpid == 0)
4009                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4010         if (!enable_ept) {
4011                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4012                 enable_unrestricted_guest = 0;
4013         }
4014         if (!enable_unrestricted_guest)
4015                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4016         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4017                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4018         if (!kvm_vcpu_apicv_active(vcpu))
4019                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4020                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4021         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4022
4023         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4024          * in vmx_set_cr4.  */
4025         exec_control &= ~SECONDARY_EXEC_DESC;
4026
4027         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4028            (handle_vmptrld).
4029            We can NOT enable shadow_vmcs here because we don't have yet
4030            a current VMCS12
4031         */
4032         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4033
4034         if (!enable_pml)
4035                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4036
4037         if (vmx_xsaves_supported()) {
4038                 /* Exposing XSAVES only when XSAVE is exposed */
4039                 bool xsaves_enabled =
4040                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4041                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4042                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4043
4044                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4045
4046                 if (!xsaves_enabled)
4047                         exec_control &= ~SECONDARY_EXEC_XSAVES;
4048
4049                 if (nested) {
4050                         if (xsaves_enabled)
4051                                 vmx->nested.msrs.secondary_ctls_high |=
4052                                         SECONDARY_EXEC_XSAVES;
4053                         else
4054                                 vmx->nested.msrs.secondary_ctls_high &=
4055                                         ~SECONDARY_EXEC_XSAVES;
4056                 }
4057         }
4058
4059         if (cpu_has_vmx_rdtscp()) {
4060                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4061                 if (!rdtscp_enabled)
4062                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
4063
4064                 if (nested) {
4065                         if (rdtscp_enabled)
4066                                 vmx->nested.msrs.secondary_ctls_high |=
4067                                         SECONDARY_EXEC_RDTSCP;
4068                         else
4069                                 vmx->nested.msrs.secondary_ctls_high &=
4070                                         ~SECONDARY_EXEC_RDTSCP;
4071                 }
4072         }
4073
4074         if (cpu_has_vmx_invpcid()) {
4075                 /* Exposing INVPCID only when PCID is exposed */
4076                 bool invpcid_enabled =
4077                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4078                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4079
4080                 if (!invpcid_enabled) {
4081                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4082                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4083                 }
4084
4085                 if (nested) {
4086                         if (invpcid_enabled)
4087                                 vmx->nested.msrs.secondary_ctls_high |=
4088                                         SECONDARY_EXEC_ENABLE_INVPCID;
4089                         else
4090                                 vmx->nested.msrs.secondary_ctls_high &=
4091                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
4092                 }
4093         }
4094
4095         if (vmx_rdrand_supported()) {
4096                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4097                 if (rdrand_enabled)
4098                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4099
4100                 if (nested) {
4101                         if (rdrand_enabled)
4102                                 vmx->nested.msrs.secondary_ctls_high |=
4103                                         SECONDARY_EXEC_RDRAND_EXITING;
4104                         else
4105                                 vmx->nested.msrs.secondary_ctls_high &=
4106                                         ~SECONDARY_EXEC_RDRAND_EXITING;
4107                 }
4108         }
4109
4110         if (vmx_rdseed_supported()) {
4111                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4112                 if (rdseed_enabled)
4113                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4114
4115                 if (nested) {
4116                         if (rdseed_enabled)
4117                                 vmx->nested.msrs.secondary_ctls_high |=
4118                                         SECONDARY_EXEC_RDSEED_EXITING;
4119                         else
4120                                 vmx->nested.msrs.secondary_ctls_high &=
4121                                         ~SECONDARY_EXEC_RDSEED_EXITING;
4122                 }
4123         }
4124
4125         if (vmx_waitpkg_supported()) {
4126                 bool waitpkg_enabled =
4127                         guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4128
4129                 if (!waitpkg_enabled)
4130                         exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4131
4132                 if (nested) {
4133                         if (waitpkg_enabled)
4134                                 vmx->nested.msrs.secondary_ctls_high |=
4135                                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4136                         else
4137                                 vmx->nested.msrs.secondary_ctls_high &=
4138                                         ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4139                 }
4140         }
4141
4142         vmx->secondary_exec_control = exec_control;
4143 }
4144
4145 static void ept_set_mmio_spte_mask(void)
4146 {
4147         /*
4148          * EPT Misconfigurations can be generated if the value of bits 2:0
4149          * of an EPT paging-structure entry is 110b (write/execute).
4150          */
4151         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4152                                    VMX_EPT_MISCONFIG_WX_VALUE, 0);
4153 }
4154
4155 #define VMX_XSS_EXIT_BITMAP 0
4156
4157 /*
4158  * Noting that the initialization of Guest-state Area of VMCS is in
4159  * vmx_vcpu_reset().
4160  */
4161 static void init_vmcs(struct vcpu_vmx *vmx)
4162 {
4163         if (nested)
4164                 nested_vmx_set_vmcs_shadowing_bitmap();
4165
4166         if (cpu_has_vmx_msr_bitmap())
4167                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4168
4169         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4170
4171         /* Control */
4172         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4173
4174         exec_controls_set(vmx, vmx_exec_control(vmx));
4175
4176         if (cpu_has_secondary_exec_ctrls()) {
4177                 vmx_compute_secondary_exec_control(vmx);
4178                 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4179         }
4180
4181         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4182                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4183                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4184                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4185                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4186
4187                 vmcs_write16(GUEST_INTR_STATUS, 0);
4188
4189                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4190                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4191         }
4192
4193         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4194                 vmcs_write32(PLE_GAP, ple_gap);
4195                 vmx->ple_window = ple_window;
4196                 vmx->ple_window_dirty = true;
4197         }
4198
4199         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4200         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4201         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4202
4203         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4204         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4205         vmx_set_constant_host_state(vmx);
4206         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4207         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4208
4209         if (cpu_has_vmx_vmfunc())
4210                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4211
4212         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4213         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4214         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4215         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4216         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4217
4218         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4219                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4220
4221         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4222
4223         /* 22.2.1, 20.8.1 */
4224         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4225
4226         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4227         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4228
4229         set_cr4_guest_host_mask(vmx);
4230
4231         if (vmx->vpid != 0)
4232                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4233
4234         if (vmx_xsaves_supported())
4235                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4236
4237         if (enable_pml) {
4238                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4239                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4240         }
4241
4242         if (cpu_has_vmx_encls_vmexit())
4243                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4244
4245         if (vmx_pt_mode_is_host_guest()) {
4246                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4247                 /* Bit[6~0] are forced to 1, writes are ignored. */
4248                 vmx->pt_desc.guest.output_mask = 0x7F;
4249                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4250         }
4251 }
4252
4253 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4254 {
4255         struct vcpu_vmx *vmx = to_vmx(vcpu);
4256         struct msr_data apic_base_msr;
4257         u64 cr0;
4258
4259         vmx->rmode.vm86_active = 0;
4260         vmx->spec_ctrl = 0;
4261
4262         vmx->msr_ia32_umwait_control = 0;
4263
4264         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4265         vmx->hv_deadline_tsc = -1;
4266         kvm_set_cr8(vcpu, 0);
4267
4268         if (!init_event) {
4269                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4270                                      MSR_IA32_APICBASE_ENABLE;
4271                 if (kvm_vcpu_is_reset_bsp(vcpu))
4272                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4273                 apic_base_msr.host_initiated = true;
4274                 kvm_set_apic_base(vcpu, &apic_base_msr);
4275         }
4276
4277         vmx_segment_cache_clear(vmx);
4278
4279         seg_setup(VCPU_SREG_CS);
4280         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4281         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4282
4283         seg_setup(VCPU_SREG_DS);
4284         seg_setup(VCPU_SREG_ES);
4285         seg_setup(VCPU_SREG_FS);
4286         seg_setup(VCPU_SREG_GS);
4287         seg_setup(VCPU_SREG_SS);
4288
4289         vmcs_write16(GUEST_TR_SELECTOR, 0);
4290         vmcs_writel(GUEST_TR_BASE, 0);
4291         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4292         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4293
4294         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4295         vmcs_writel(GUEST_LDTR_BASE, 0);
4296         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4297         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4298
4299         if (!init_event) {
4300                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4301                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4302                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4303                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4304         }
4305
4306         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4307         kvm_rip_write(vcpu, 0xfff0);
4308
4309         vmcs_writel(GUEST_GDTR_BASE, 0);
4310         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4311
4312         vmcs_writel(GUEST_IDTR_BASE, 0);
4313         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4314
4315         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4316         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4317         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4318         if (kvm_mpx_supported())
4319                 vmcs_write64(GUEST_BNDCFGS, 0);
4320
4321         setup_msrs(vmx);
4322
4323         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4324
4325         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4326                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4327                 if (cpu_need_tpr_shadow(vcpu))
4328                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4329                                      __pa(vcpu->arch.apic->regs));
4330                 vmcs_write32(TPR_THRESHOLD, 0);
4331         }
4332
4333         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4334
4335         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4336         vmx->vcpu.arch.cr0 = cr0;
4337         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4338         vmx_set_cr4(vcpu, 0);
4339         vmx_set_efer(vcpu, 0);
4340
4341         update_exception_bitmap(vcpu);
4342
4343         vpid_sync_context(vmx->vpid);
4344         if (init_event)
4345                 vmx_clear_hlt(vcpu);
4346 }
4347
4348 static void enable_irq_window(struct kvm_vcpu *vcpu)
4349 {
4350         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4351 }
4352
4353 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4354 {
4355         if (!enable_vnmi ||
4356             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4357                 enable_irq_window(vcpu);
4358                 return;
4359         }
4360
4361         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4362 }
4363
4364 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4365 {
4366         struct vcpu_vmx *vmx = to_vmx(vcpu);
4367         uint32_t intr;
4368         int irq = vcpu->arch.interrupt.nr;
4369
4370         trace_kvm_inj_virq(irq);
4371
4372         ++vcpu->stat.irq_injections;
4373         if (vmx->rmode.vm86_active) {
4374                 int inc_eip = 0;
4375                 if (vcpu->arch.interrupt.soft)
4376                         inc_eip = vcpu->arch.event_exit_inst_len;
4377                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4378                 return;
4379         }
4380         intr = irq | INTR_INFO_VALID_MASK;
4381         if (vcpu->arch.interrupt.soft) {
4382                 intr |= INTR_TYPE_SOFT_INTR;
4383                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4384                              vmx->vcpu.arch.event_exit_inst_len);
4385         } else
4386                 intr |= INTR_TYPE_EXT_INTR;
4387         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4388
4389         vmx_clear_hlt(vcpu);
4390 }
4391
4392 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4393 {
4394         struct vcpu_vmx *vmx = to_vmx(vcpu);
4395
4396         if (!enable_vnmi) {
4397                 /*
4398                  * Tracking the NMI-blocked state in software is built upon
4399                  * finding the next open IRQ window. This, in turn, depends on
4400                  * well-behaving guests: They have to keep IRQs disabled at
4401                  * least as long as the NMI handler runs. Otherwise we may
4402                  * cause NMI nesting, maybe breaking the guest. But as this is
4403                  * highly unlikely, we can live with the residual risk.
4404                  */
4405                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4406                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4407         }
4408
4409         ++vcpu->stat.nmi_injections;
4410         vmx->loaded_vmcs->nmi_known_unmasked = false;
4411
4412         if (vmx->rmode.vm86_active) {
4413                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4414                 return;
4415         }
4416
4417         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4418                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4419
4420         vmx_clear_hlt(vcpu);
4421 }
4422
4423 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4424 {
4425         struct vcpu_vmx *vmx = to_vmx(vcpu);
4426         bool masked;
4427
4428         if (!enable_vnmi)
4429                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4430         if (vmx->loaded_vmcs->nmi_known_unmasked)
4431                 return false;
4432         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4433         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4434         return masked;
4435 }
4436
4437 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4438 {
4439         struct vcpu_vmx *vmx = to_vmx(vcpu);
4440
4441         if (!enable_vnmi) {
4442                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4443                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4444                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4445                 }
4446         } else {
4447                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4448                 if (masked)
4449                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4450                                       GUEST_INTR_STATE_NMI);
4451                 else
4452                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4453                                         GUEST_INTR_STATE_NMI);
4454         }
4455 }
4456
4457 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4458 {
4459         if (to_vmx(vcpu)->nested.nested_run_pending)
4460                 return 0;
4461
4462         if (!enable_vnmi &&
4463             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4464                 return 0;
4465
4466         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4467                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4468                    | GUEST_INTR_STATE_NMI));
4469 }
4470
4471 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4472 {
4473         if (to_vmx(vcpu)->nested.nested_run_pending)
4474                 return false;
4475
4476         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4477                 return true;
4478
4479         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4480                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4481                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4482 }
4483
4484 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4485 {
4486         int ret;
4487
4488         if (enable_unrestricted_guest)
4489                 return 0;
4490
4491         mutex_lock(&kvm->slots_lock);
4492         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4493                                       PAGE_SIZE * 3);
4494         mutex_unlock(&kvm->slots_lock);
4495
4496         if (ret)
4497                 return ret;
4498         to_kvm_vmx(kvm)->tss_addr = addr;
4499         return init_rmode_tss(kvm);
4500 }
4501
4502 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4503 {
4504         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4505         return 0;
4506 }
4507
4508 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4509 {
4510         switch (vec) {
4511         case BP_VECTOR:
4512                 /*
4513                  * Update instruction length as we may reinject the exception
4514                  * from user space while in guest debugging mode.
4515                  */
4516                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4517                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4518                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4519                         return false;
4520                 /* fall through */
4521         case DB_VECTOR:
4522                 if (vcpu->guest_debug &
4523                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4524                         return false;
4525                 /* fall through */
4526         case DE_VECTOR:
4527         case OF_VECTOR:
4528         case BR_VECTOR:
4529         case UD_VECTOR:
4530         case DF_VECTOR:
4531         case SS_VECTOR:
4532         case GP_VECTOR:
4533         case MF_VECTOR:
4534                 return true;
4535         }
4536         return false;
4537 }
4538
4539 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4540                                   int vec, u32 err_code)
4541 {
4542         /*
4543          * Instruction with address size override prefix opcode 0x67
4544          * Cause the #SS fault with 0 error code in VM86 mode.
4545          */
4546         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4547                 if (kvm_emulate_instruction(vcpu, 0)) {
4548                         if (vcpu->arch.halt_request) {
4549                                 vcpu->arch.halt_request = 0;
4550                                 return kvm_vcpu_halt(vcpu);
4551                         }
4552                         return 1;
4553                 }
4554                 return 0;
4555         }
4556
4557         /*
4558          * Forward all other exceptions that are valid in real mode.
4559          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4560          *        the required debugging infrastructure rework.
4561          */
4562         kvm_queue_exception(vcpu, vec);
4563         return 1;
4564 }
4565
4566 /*
4567  * Trigger machine check on the host. We assume all the MSRs are already set up
4568  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4569  * We pass a fake environment to the machine check handler because we want
4570  * the guest to be always treated like user space, no matter what context
4571  * it used internally.
4572  */
4573 static void kvm_machine_check(void)
4574 {
4575 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4576         struct pt_regs regs = {
4577                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4578                 .flags = X86_EFLAGS_IF,
4579         };
4580
4581         do_machine_check(&regs, 0);
4582 #endif
4583 }
4584
4585 static int handle_machine_check(struct kvm_vcpu *vcpu)
4586 {
4587         /* handled by vmx_vcpu_run() */
4588         return 1;
4589 }
4590
4591 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4592 {
4593         struct vcpu_vmx *vmx = to_vmx(vcpu);
4594         struct kvm_run *kvm_run = vcpu->run;
4595         u32 intr_info, ex_no, error_code;
4596         unsigned long cr2, rip, dr6;
4597         u32 vect_info;
4598
4599         vect_info = vmx->idt_vectoring_info;
4600         intr_info = vmx->exit_intr_info;
4601
4602         if (is_machine_check(intr_info) || is_nmi(intr_info))
4603                 return 1; /* handled by handle_exception_nmi_irqoff() */
4604
4605         if (is_invalid_opcode(intr_info))
4606                 return handle_ud(vcpu);
4607
4608         error_code = 0;
4609         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4610                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4611
4612         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4613                 WARN_ON_ONCE(!enable_vmware_backdoor);
4614
4615                 /*
4616                  * VMware backdoor emulation on #GP interception only handles
4617                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4618                  * error code on #GP.
4619                  */
4620                 if (error_code) {
4621                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4622                         return 1;
4623                 }
4624                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4625         }
4626
4627         /*
4628          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4629          * MMIO, it is better to report an internal error.
4630          * See the comments in vmx_handle_exit.
4631          */
4632         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4633             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4634                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4635                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4636                 vcpu->run->internal.ndata = 3;
4637                 vcpu->run->internal.data[0] = vect_info;
4638                 vcpu->run->internal.data[1] = intr_info;
4639                 vcpu->run->internal.data[2] = error_code;
4640                 return 0;
4641         }
4642
4643         if (is_page_fault(intr_info)) {
4644                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4645                 /* EPT won't cause page fault directly */
4646                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4647                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4648         }
4649
4650         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4651
4652         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4653                 return handle_rmode_exception(vcpu, ex_no, error_code);
4654
4655         switch (ex_no) {
4656         case AC_VECTOR:
4657                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4658                 return 1;
4659         case DB_VECTOR:
4660                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4661                 if (!(vcpu->guest_debug &
4662                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4663                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4664                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4665                         if (is_icebp(intr_info))
4666                                 WARN_ON(!skip_emulated_instruction(vcpu));
4667
4668                         kvm_queue_exception(vcpu, DB_VECTOR);
4669                         return 1;
4670                 }
4671                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4672                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4673                 /* fall through */
4674         case BP_VECTOR:
4675                 /*
4676                  * Update instruction length as we may reinject #BP from
4677                  * user space while in guest debugging mode. Reading it for
4678                  * #DB as well causes no harm, it is not used in that case.
4679                  */
4680                 vmx->vcpu.arch.event_exit_inst_len =
4681                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4682                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4683                 rip = kvm_rip_read(vcpu);
4684                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4685                 kvm_run->debug.arch.exception = ex_no;
4686                 break;
4687         default:
4688                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4689                 kvm_run->ex.exception = ex_no;
4690                 kvm_run->ex.error_code = error_code;
4691                 break;
4692         }
4693         return 0;
4694 }
4695
4696 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4697 {
4698         ++vcpu->stat.irq_exits;
4699         return 1;
4700 }
4701
4702 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4703 {
4704         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4705         vcpu->mmio_needed = 0;
4706         return 0;
4707 }
4708
4709 static int handle_io(struct kvm_vcpu *vcpu)
4710 {
4711         unsigned long exit_qualification;
4712         int size, in, string;
4713         unsigned port;
4714
4715         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4716         string = (exit_qualification & 16) != 0;
4717
4718         ++vcpu->stat.io_exits;
4719
4720         if (string)
4721                 return kvm_emulate_instruction(vcpu, 0);
4722
4723         port = exit_qualification >> 16;
4724         size = (exit_qualification & 7) + 1;
4725         in = (exit_qualification & 8) != 0;
4726
4727         return kvm_fast_pio(vcpu, size, port, in);
4728 }
4729
4730 static void
4731 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4732 {
4733         /*
4734          * Patch in the VMCALL instruction:
4735          */
4736         hypercall[0] = 0x0f;
4737         hypercall[1] = 0x01;
4738         hypercall[2] = 0xc1;
4739 }
4740
4741 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4742 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4743 {
4744         if (is_guest_mode(vcpu)) {
4745                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4746                 unsigned long orig_val = val;
4747
4748                 /*
4749                  * We get here when L2 changed cr0 in a way that did not change
4750                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4751                  * but did change L0 shadowed bits. So we first calculate the
4752                  * effective cr0 value that L1 would like to write into the
4753                  * hardware. It consists of the L2-owned bits from the new
4754                  * value combined with the L1-owned bits from L1's guest_cr0.
4755                  */
4756                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4757                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4758
4759                 if (!nested_guest_cr0_valid(vcpu, val))
4760                         return 1;
4761
4762                 if (kvm_set_cr0(vcpu, val))
4763                         return 1;
4764                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4765                 return 0;
4766         } else {
4767                 if (to_vmx(vcpu)->nested.vmxon &&
4768                     !nested_host_cr0_valid(vcpu, val))
4769                         return 1;
4770
4771                 return kvm_set_cr0(vcpu, val);
4772         }
4773 }
4774
4775 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4776 {
4777         if (is_guest_mode(vcpu)) {
4778                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4779                 unsigned long orig_val = val;
4780
4781                 /* analogously to handle_set_cr0 */
4782                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4783                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4784                 if (kvm_set_cr4(vcpu, val))
4785                         return 1;
4786                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4787                 return 0;
4788         } else
4789                 return kvm_set_cr4(vcpu, val);
4790 }
4791
4792 static int handle_desc(struct kvm_vcpu *vcpu)
4793 {
4794         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4795         return kvm_emulate_instruction(vcpu, 0);
4796 }
4797
4798 static int handle_cr(struct kvm_vcpu *vcpu)
4799 {
4800         unsigned long exit_qualification, val;
4801         int cr;
4802         int reg;
4803         int err;
4804         int ret;
4805
4806         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4807         cr = exit_qualification & 15;
4808         reg = (exit_qualification >> 8) & 15;
4809         switch ((exit_qualification >> 4) & 3) {
4810         case 0: /* mov to cr */
4811                 val = kvm_register_readl(vcpu, reg);
4812                 trace_kvm_cr_write(cr, val);
4813                 switch (cr) {
4814                 case 0:
4815                         err = handle_set_cr0(vcpu, val);
4816                         return kvm_complete_insn_gp(vcpu, err);
4817                 case 3:
4818                         WARN_ON_ONCE(enable_unrestricted_guest);
4819                         err = kvm_set_cr3(vcpu, val);
4820                         return kvm_complete_insn_gp(vcpu, err);
4821                 case 4:
4822                         err = handle_set_cr4(vcpu, val);
4823                         return kvm_complete_insn_gp(vcpu, err);
4824                 case 8: {
4825                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4826                                 u8 cr8 = (u8)val;
4827                                 err = kvm_set_cr8(vcpu, cr8);
4828                                 ret = kvm_complete_insn_gp(vcpu, err);
4829                                 if (lapic_in_kernel(vcpu))
4830                                         return ret;
4831                                 if (cr8_prev <= cr8)
4832                                         return ret;
4833                                 /*
4834                                  * TODO: we might be squashing a
4835                                  * KVM_GUESTDBG_SINGLESTEP-triggered
4836                                  * KVM_EXIT_DEBUG here.
4837                                  */
4838                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4839                                 return 0;
4840                         }
4841                 }
4842                 break;
4843         case 2: /* clts */
4844                 WARN_ONCE(1, "Guest should always own CR0.TS");
4845                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4846                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4847                 return kvm_skip_emulated_instruction(vcpu);
4848         case 1: /*mov from cr*/
4849                 switch (cr) {
4850                 case 3:
4851                         WARN_ON_ONCE(enable_unrestricted_guest);
4852                         val = kvm_read_cr3(vcpu);
4853                         kvm_register_write(vcpu, reg, val);
4854                         trace_kvm_cr_read(cr, val);
4855                         return kvm_skip_emulated_instruction(vcpu);
4856                 case 8:
4857                         val = kvm_get_cr8(vcpu);
4858                         kvm_register_write(vcpu, reg, val);
4859                         trace_kvm_cr_read(cr, val);
4860                         return kvm_skip_emulated_instruction(vcpu);
4861                 }
4862                 break;
4863         case 3: /* lmsw */
4864                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4865                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4866                 kvm_lmsw(vcpu, val);
4867
4868                 return kvm_skip_emulated_instruction(vcpu);
4869         default:
4870                 break;
4871         }
4872         vcpu->run->exit_reason = 0;
4873         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4874                (int)(exit_qualification >> 4) & 3, cr);
4875         return 0;
4876 }
4877
4878 static int handle_dr(struct kvm_vcpu *vcpu)
4879 {
4880         unsigned long exit_qualification;
4881         int dr, dr7, reg;
4882
4883         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4884         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4885
4886         /* First, if DR does not exist, trigger UD */
4887         if (!kvm_require_dr(vcpu, dr))
4888                 return 1;
4889
4890         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4891         if (!kvm_require_cpl(vcpu, 0))
4892                 return 1;
4893         dr7 = vmcs_readl(GUEST_DR7);
4894         if (dr7 & DR7_GD) {
4895                 /*
4896                  * As the vm-exit takes precedence over the debug trap, we
4897                  * need to emulate the latter, either for the host or the
4898                  * guest debugging itself.
4899                  */
4900                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4901                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4902                         vcpu->run->debug.arch.dr7 = dr7;
4903                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4904                         vcpu->run->debug.arch.exception = DB_VECTOR;
4905                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4906                         return 0;
4907                 } else {
4908                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4909                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4910                         kvm_queue_exception(vcpu, DB_VECTOR);
4911                         return 1;
4912                 }
4913         }
4914
4915         if (vcpu->guest_debug == 0) {
4916                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4917
4918                 /*
4919                  * No more DR vmexits; force a reload of the debug registers
4920                  * and reenter on this instruction.  The next vmexit will
4921                  * retrieve the full state of the debug registers.
4922                  */
4923                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4924                 return 1;
4925         }
4926
4927         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4928         if (exit_qualification & TYPE_MOV_FROM_DR) {
4929                 unsigned long val;
4930
4931                 if (kvm_get_dr(vcpu, dr, &val))
4932                         return 1;
4933                 kvm_register_write(vcpu, reg, val);
4934         } else
4935                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4936                         return 1;
4937
4938         return kvm_skip_emulated_instruction(vcpu);
4939 }
4940
4941 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4942 {
4943         return vcpu->arch.dr6;
4944 }
4945
4946 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4947 {
4948 }
4949
4950 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4951 {
4952         get_debugreg(vcpu->arch.db[0], 0);
4953         get_debugreg(vcpu->arch.db[1], 1);
4954         get_debugreg(vcpu->arch.db[2], 2);
4955         get_debugreg(vcpu->arch.db[3], 3);
4956         get_debugreg(vcpu->arch.dr6, 6);
4957         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4958
4959         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4960         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4961 }
4962
4963 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4964 {
4965         vmcs_writel(GUEST_DR7, val);
4966 }
4967
4968 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4969 {
4970         kvm_apic_update_ppr(vcpu);
4971         return 1;
4972 }
4973
4974 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4975 {
4976         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4977
4978         kvm_make_request(KVM_REQ_EVENT, vcpu);
4979
4980         ++vcpu->stat.irq_window_exits;
4981         return 1;
4982 }
4983
4984 static int handle_vmcall(struct kvm_vcpu *vcpu)
4985 {
4986         return kvm_emulate_hypercall(vcpu);
4987 }
4988
4989 static int handle_invd(struct kvm_vcpu *vcpu)
4990 {
4991         return kvm_emulate_instruction(vcpu, 0);
4992 }
4993
4994 static int handle_invlpg(struct kvm_vcpu *vcpu)
4995 {
4996         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4997
4998         kvm_mmu_invlpg(vcpu, exit_qualification);
4999         return kvm_skip_emulated_instruction(vcpu);
5000 }
5001
5002 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5003 {
5004         int err;
5005
5006         err = kvm_rdpmc(vcpu);
5007         return kvm_complete_insn_gp(vcpu, err);
5008 }
5009
5010 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5011 {
5012         return kvm_emulate_wbinvd(vcpu);
5013 }
5014
5015 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5016 {
5017         u64 new_bv = kvm_read_edx_eax(vcpu);
5018         u32 index = kvm_rcx_read(vcpu);
5019
5020         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5021                 return kvm_skip_emulated_instruction(vcpu);
5022         return 1;
5023 }
5024
5025 static int handle_apic_access(struct kvm_vcpu *vcpu)
5026 {
5027         if (likely(fasteoi)) {
5028                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5029                 int access_type, offset;
5030
5031                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5032                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5033                 /*
5034                  * Sane guest uses MOV to write EOI, with written value
5035                  * not cared. So make a short-circuit here by avoiding
5036                  * heavy instruction emulation.
5037                  */
5038                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5039                     (offset == APIC_EOI)) {
5040                         kvm_lapic_set_eoi(vcpu);
5041                         return kvm_skip_emulated_instruction(vcpu);
5042                 }
5043         }
5044         return kvm_emulate_instruction(vcpu, 0);
5045 }
5046
5047 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5048 {
5049         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5050         int vector = exit_qualification & 0xff;
5051
5052         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5053         kvm_apic_set_eoi_accelerated(vcpu, vector);
5054         return 1;
5055 }
5056
5057 static int handle_apic_write(struct kvm_vcpu *vcpu)
5058 {
5059         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5060         u32 offset = exit_qualification & 0xfff;
5061
5062         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5063         kvm_apic_write_nodecode(vcpu, offset);
5064         return 1;
5065 }
5066
5067 static int handle_task_switch(struct kvm_vcpu *vcpu)
5068 {
5069         struct vcpu_vmx *vmx = to_vmx(vcpu);
5070         unsigned long exit_qualification;
5071         bool has_error_code = false;
5072         u32 error_code = 0;
5073         u16 tss_selector;
5074         int reason, type, idt_v, idt_index;
5075
5076         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5077         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5078         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5079
5080         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5081
5082         reason = (u32)exit_qualification >> 30;
5083         if (reason == TASK_SWITCH_GATE && idt_v) {
5084                 switch (type) {
5085                 case INTR_TYPE_NMI_INTR:
5086                         vcpu->arch.nmi_injected = false;
5087                         vmx_set_nmi_mask(vcpu, true);
5088                         break;
5089                 case INTR_TYPE_EXT_INTR:
5090                 case INTR_TYPE_SOFT_INTR:
5091                         kvm_clear_interrupt_queue(vcpu);
5092                         break;
5093                 case INTR_TYPE_HARD_EXCEPTION:
5094                         if (vmx->idt_vectoring_info &
5095                             VECTORING_INFO_DELIVER_CODE_MASK) {
5096                                 has_error_code = true;
5097                                 error_code =
5098                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5099                         }
5100                         /* fall through */
5101                 case INTR_TYPE_SOFT_EXCEPTION:
5102                         kvm_clear_exception_queue(vcpu);
5103                         break;
5104                 default:
5105                         break;
5106                 }
5107         }
5108         tss_selector = exit_qualification;
5109
5110         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5111                        type != INTR_TYPE_EXT_INTR &&
5112                        type != INTR_TYPE_NMI_INTR))
5113                 WARN_ON(!skip_emulated_instruction(vcpu));
5114
5115         /*
5116          * TODO: What about debug traps on tss switch?
5117          *       Are we supposed to inject them and update dr6?
5118          */
5119         return kvm_task_switch(vcpu, tss_selector,
5120                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5121                                reason, has_error_code, error_code);
5122 }
5123
5124 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5125 {
5126         unsigned long exit_qualification;
5127         gpa_t gpa;
5128         u64 error_code;
5129
5130         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5131
5132         /*
5133          * EPT violation happened while executing iret from NMI,
5134          * "blocked by NMI" bit has to be set before next VM entry.
5135          * There are errata that may cause this bit to not be set:
5136          * AAK134, BY25.
5137          */
5138         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5139                         enable_vnmi &&
5140                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5141                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5142
5143         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5144         trace_kvm_page_fault(gpa, exit_qualification);
5145
5146         /* Is it a read fault? */
5147         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5148                      ? PFERR_USER_MASK : 0;
5149         /* Is it a write fault? */
5150         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5151                       ? PFERR_WRITE_MASK : 0;
5152         /* Is it a fetch fault? */
5153         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5154                       ? PFERR_FETCH_MASK : 0;
5155         /* ept page table entry is present? */
5156         error_code |= (exit_qualification &
5157                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5158                         EPT_VIOLATION_EXECUTABLE))
5159                       ? PFERR_PRESENT_MASK : 0;
5160
5161         error_code |= (exit_qualification & 0x100) != 0 ?
5162                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5163
5164         vcpu->arch.exit_qualification = exit_qualification;
5165         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5166 }
5167
5168 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5169 {
5170         gpa_t gpa;
5171
5172         /*
5173          * A nested guest cannot optimize MMIO vmexits, because we have an
5174          * nGPA here instead of the required GPA.
5175          */
5176         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5177         if (!is_guest_mode(vcpu) &&
5178             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5179                 trace_kvm_fast_mmio(gpa);
5180                 return kvm_skip_emulated_instruction(vcpu);
5181         }
5182
5183         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5184 }
5185
5186 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5187 {
5188         WARN_ON_ONCE(!enable_vnmi);
5189         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5190         ++vcpu->stat.nmi_window_exits;
5191         kvm_make_request(KVM_REQ_EVENT, vcpu);
5192
5193         return 1;
5194 }
5195
5196 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5197 {
5198         struct vcpu_vmx *vmx = to_vmx(vcpu);
5199         bool intr_window_requested;
5200         unsigned count = 130;
5201
5202         /*
5203          * We should never reach the point where we are emulating L2
5204          * due to invalid guest state as that means we incorrectly
5205          * allowed a nested VMEntry with an invalid vmcs12.
5206          */
5207         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5208
5209         intr_window_requested = exec_controls_get(vmx) &
5210                                 CPU_BASED_INTR_WINDOW_EXITING;
5211
5212         while (vmx->emulation_required && count-- != 0) {
5213                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5214                         return handle_interrupt_window(&vmx->vcpu);
5215
5216                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5217                         return 1;
5218
5219                 if (!kvm_emulate_instruction(vcpu, 0))
5220                         return 0;
5221
5222                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5223                     vcpu->arch.exception.pending) {
5224                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5225                         vcpu->run->internal.suberror =
5226                                                 KVM_INTERNAL_ERROR_EMULATION;
5227                         vcpu->run->internal.ndata = 0;
5228                         return 0;
5229                 }
5230
5231                 if (vcpu->arch.halt_request) {
5232                         vcpu->arch.halt_request = 0;
5233                         return kvm_vcpu_halt(vcpu);
5234                 }
5235
5236                 /*
5237                  * Note, return 1 and not 0, vcpu_run() is responsible for
5238                  * morphing the pending signal into the proper return code.
5239                  */
5240                 if (signal_pending(current))
5241                         return 1;
5242
5243                 if (need_resched())
5244                         schedule();
5245         }
5246
5247         return 1;
5248 }
5249
5250 static void grow_ple_window(struct kvm_vcpu *vcpu)
5251 {
5252         struct vcpu_vmx *vmx = to_vmx(vcpu);
5253         unsigned int old = vmx->ple_window;
5254
5255         vmx->ple_window = __grow_ple_window(old, ple_window,
5256                                             ple_window_grow,
5257                                             ple_window_max);
5258
5259         if (vmx->ple_window != old) {
5260                 vmx->ple_window_dirty = true;
5261                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5262                                             vmx->ple_window, old);
5263         }
5264 }
5265
5266 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5267 {
5268         struct vcpu_vmx *vmx = to_vmx(vcpu);
5269         unsigned int old = vmx->ple_window;
5270
5271         vmx->ple_window = __shrink_ple_window(old, ple_window,
5272                                               ple_window_shrink,
5273                                               ple_window);
5274
5275         if (vmx->ple_window != old) {
5276                 vmx->ple_window_dirty = true;
5277                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5278                                             vmx->ple_window, old);
5279         }
5280 }
5281
5282 /*
5283  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5284  */
5285 static void wakeup_handler(void)
5286 {
5287         struct kvm_vcpu *vcpu;
5288         int cpu = smp_processor_id();
5289
5290         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5291         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5292                         blocked_vcpu_list) {
5293                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5294
5295                 if (pi_test_on(pi_desc) == 1)
5296                         kvm_vcpu_kick(vcpu);
5297         }
5298         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5299 }
5300
5301 static void vmx_enable_tdp(void)
5302 {
5303         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5304                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5305                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5306                 0ull, VMX_EPT_EXECUTABLE_MASK,
5307                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5308                 VMX_EPT_RWX_MASK, 0ull);
5309
5310         ept_set_mmio_spte_mask();
5311 }
5312
5313 /*
5314  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5315  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5316  */
5317 static int handle_pause(struct kvm_vcpu *vcpu)
5318 {
5319         if (!kvm_pause_in_guest(vcpu->kvm))
5320                 grow_ple_window(vcpu);
5321
5322         /*
5323          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5324          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5325          * never set PAUSE_EXITING and just set PLE if supported,
5326          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5327          */
5328         kvm_vcpu_on_spin(vcpu, true);
5329         return kvm_skip_emulated_instruction(vcpu);
5330 }
5331
5332 static int handle_nop(struct kvm_vcpu *vcpu)
5333 {
5334         return kvm_skip_emulated_instruction(vcpu);
5335 }
5336
5337 static int handle_mwait(struct kvm_vcpu *vcpu)
5338 {
5339         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5340         return handle_nop(vcpu);
5341 }
5342
5343 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5344 {
5345         kvm_queue_exception(vcpu, UD_VECTOR);
5346         return 1;
5347 }
5348
5349 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5350 {
5351         return 1;
5352 }
5353
5354 static int handle_monitor(struct kvm_vcpu *vcpu)
5355 {
5356         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5357         return handle_nop(vcpu);
5358 }
5359
5360 static int handle_invpcid(struct kvm_vcpu *vcpu)
5361 {
5362         u32 vmx_instruction_info;
5363         unsigned long type;
5364         bool pcid_enabled;
5365         gva_t gva;
5366         struct x86_exception e;
5367         unsigned i;
5368         unsigned long roots_to_free = 0;
5369         struct {
5370                 u64 pcid;
5371                 u64 gla;
5372         } operand;
5373
5374         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5375                 kvm_queue_exception(vcpu, UD_VECTOR);
5376                 return 1;
5377         }
5378
5379         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5380         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5381
5382         if (type > 3) {
5383                 kvm_inject_gp(vcpu, 0);
5384                 return 1;
5385         }
5386
5387         /* According to the Intel instruction reference, the memory operand
5388          * is read even if it isn't needed (e.g., for type==all)
5389          */
5390         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5391                                 vmx_instruction_info, false,
5392                                 sizeof(operand), &gva))
5393                 return 1;
5394
5395         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5396                 kvm_inject_page_fault(vcpu, &e);
5397                 return 1;
5398         }
5399
5400         if (operand.pcid >> 12 != 0) {
5401                 kvm_inject_gp(vcpu, 0);
5402                 return 1;
5403         }
5404
5405         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5406
5407         switch (type) {
5408         case INVPCID_TYPE_INDIV_ADDR:
5409                 if ((!pcid_enabled && (operand.pcid != 0)) ||
5410                     is_noncanonical_address(operand.gla, vcpu)) {
5411                         kvm_inject_gp(vcpu, 0);
5412                         return 1;
5413                 }
5414                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5415                 return kvm_skip_emulated_instruction(vcpu);
5416
5417         case INVPCID_TYPE_SINGLE_CTXT:
5418                 if (!pcid_enabled && (operand.pcid != 0)) {
5419                         kvm_inject_gp(vcpu, 0);
5420                         return 1;
5421                 }
5422
5423                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5424                         kvm_mmu_sync_roots(vcpu);
5425                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5426                 }
5427
5428                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5429                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5430                             == operand.pcid)
5431                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5432
5433                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5434                 /*
5435                  * If neither the current cr3 nor any of the prev_roots use the
5436                  * given PCID, then nothing needs to be done here because a
5437                  * resync will happen anyway before switching to any other CR3.
5438                  */
5439
5440                 return kvm_skip_emulated_instruction(vcpu);
5441
5442         case INVPCID_TYPE_ALL_NON_GLOBAL:
5443                 /*
5444                  * Currently, KVM doesn't mark global entries in the shadow
5445                  * page tables, so a non-global flush just degenerates to a
5446                  * global flush. If needed, we could optimize this later by
5447                  * keeping track of global entries in shadow page tables.
5448                  */
5449
5450                 /* fall-through */
5451         case INVPCID_TYPE_ALL_INCL_GLOBAL:
5452                 kvm_mmu_unload(vcpu);
5453                 return kvm_skip_emulated_instruction(vcpu);
5454
5455         default:
5456                 BUG(); /* We have already checked above that type <= 3 */
5457         }
5458 }
5459
5460 static int handle_pml_full(struct kvm_vcpu *vcpu)
5461 {
5462         unsigned long exit_qualification;
5463
5464         trace_kvm_pml_full(vcpu->vcpu_id);
5465
5466         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5467
5468         /*
5469          * PML buffer FULL happened while executing iret from NMI,
5470          * "blocked by NMI" bit has to be set before next VM entry.
5471          */
5472         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5473                         enable_vnmi &&
5474                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5475                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5476                                 GUEST_INTR_STATE_NMI);
5477
5478         /*
5479          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5480          * here.., and there's no userspace involvement needed for PML.
5481          */
5482         return 1;
5483 }
5484
5485 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5486 {
5487         struct vcpu_vmx *vmx = to_vmx(vcpu);
5488
5489         if (!vmx->req_immediate_exit &&
5490             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5491                 kvm_lapic_expired_hv_timer(vcpu);
5492
5493         return 1;
5494 }
5495
5496 /*
5497  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5498  * are overwritten by nested_vmx_setup() when nested=1.
5499  */
5500 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5501 {
5502         kvm_queue_exception(vcpu, UD_VECTOR);
5503         return 1;
5504 }
5505
5506 static int handle_encls(struct kvm_vcpu *vcpu)
5507 {
5508         /*
5509          * SGX virtualization is not yet supported.  There is no software
5510          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5511          * to prevent the guest from executing ENCLS.
5512          */
5513         kvm_queue_exception(vcpu, UD_VECTOR);
5514         return 1;
5515 }
5516
5517 /*
5518  * The exit handlers return 1 if the exit was handled fully and guest execution
5519  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5520  * to be done to userspace and return 0.
5521  */
5522 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5523         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5524         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5525         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5526         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5527         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5528         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5529         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5530         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5531         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5532         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5533         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5534         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5535         [EXIT_REASON_INVD]                    = handle_invd,
5536         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5537         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5538         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5539         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5540         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5541         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5542         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5543         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5544         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5545         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5546         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5547         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5548         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5549         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5550         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5551         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5552         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5553         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5554         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5555         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5556         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5557         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5558         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5559         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5560         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5561         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
5562         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5563         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
5564         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5565         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5566         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
5567         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
5568         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5569         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5570         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5571         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5572         [EXIT_REASON_ENCLS]                   = handle_encls,
5573 };
5574
5575 static const int kvm_vmx_max_exit_handlers =
5576         ARRAY_SIZE(kvm_vmx_exit_handlers);
5577
5578 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5579 {
5580         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5581         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5582 }
5583
5584 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5585 {
5586         if (vmx->pml_pg) {
5587                 __free_page(vmx->pml_pg);
5588                 vmx->pml_pg = NULL;
5589         }
5590 }
5591
5592 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5593 {
5594         struct vcpu_vmx *vmx = to_vmx(vcpu);
5595         u64 *pml_buf;
5596         u16 pml_idx;
5597
5598         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5599
5600         /* Do nothing if PML buffer is empty */
5601         if (pml_idx == (PML_ENTITY_NUM - 1))
5602                 return;
5603
5604         /* PML index always points to next available PML buffer entity */
5605         if (pml_idx >= PML_ENTITY_NUM)
5606                 pml_idx = 0;
5607         else
5608                 pml_idx++;
5609
5610         pml_buf = page_address(vmx->pml_pg);
5611         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5612                 u64 gpa;
5613
5614                 gpa = pml_buf[pml_idx];
5615                 WARN_ON(gpa & (PAGE_SIZE - 1));
5616                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5617         }
5618
5619         /* reset PML index */
5620         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5621 }
5622
5623 /*
5624  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5625  * Called before reporting dirty_bitmap to userspace.
5626  */
5627 static void kvm_flush_pml_buffers(struct kvm *kvm)
5628 {
5629         int i;
5630         struct kvm_vcpu *vcpu;
5631         /*
5632          * We only need to kick vcpu out of guest mode here, as PML buffer
5633          * is flushed at beginning of all VMEXITs, and it's obvious that only
5634          * vcpus running in guest are possible to have unflushed GPAs in PML
5635          * buffer.
5636          */
5637         kvm_for_each_vcpu(i, vcpu, kvm)
5638                 kvm_vcpu_kick(vcpu);
5639 }
5640
5641 static void vmx_dump_sel(char *name, uint32_t sel)
5642 {
5643         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5644                name, vmcs_read16(sel),
5645                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5646                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5647                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5648 }
5649
5650 static void vmx_dump_dtsel(char *name, uint32_t limit)
5651 {
5652         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5653                name, vmcs_read32(limit),
5654                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5655 }
5656
5657 void dump_vmcs(void)
5658 {
5659         u32 vmentry_ctl, vmexit_ctl;
5660         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5661         unsigned long cr4;
5662         u64 efer;
5663         int i, n;
5664
5665         if (!dump_invalid_vmcs) {
5666                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5667                 return;
5668         }
5669
5670         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5671         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5672         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5673         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5674         cr4 = vmcs_readl(GUEST_CR4);
5675         efer = vmcs_read64(GUEST_IA32_EFER);
5676         secondary_exec_control = 0;
5677         if (cpu_has_secondary_exec_ctrls())
5678                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5679
5680         pr_err("*** Guest State ***\n");
5681         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5682                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5683                vmcs_readl(CR0_GUEST_HOST_MASK));
5684         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5685                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5686         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5687         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5688             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5689         {
5690                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5691                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5692                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5693                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5694         }
5695         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5696                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5697         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5698                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5699         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5700                vmcs_readl(GUEST_SYSENTER_ESP),
5701                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5702         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5703         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5704         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5705         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5706         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5707         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5708         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5709         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5710         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5711         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5712         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5713             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5714                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
5715                        efer, vmcs_read64(GUEST_IA32_PAT));
5716         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5717                vmcs_read64(GUEST_IA32_DEBUGCTL),
5718                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5719         if (cpu_has_load_perf_global_ctrl() &&
5720             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5721                 pr_err("PerfGlobCtl = 0x%016llx\n",
5722                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5723         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5724                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5725         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5726                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5727                vmcs_read32(GUEST_ACTIVITY_STATE));
5728         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5729                 pr_err("InterruptStatus = %04x\n",
5730                        vmcs_read16(GUEST_INTR_STATUS));
5731
5732         pr_err("*** Host State ***\n");
5733         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5734                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5735         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5736                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5737                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5738                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5739                vmcs_read16(HOST_TR_SELECTOR));
5740         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5741                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5742                vmcs_readl(HOST_TR_BASE));
5743         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5744                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5745         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5746                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5747                vmcs_readl(HOST_CR4));
5748         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5749                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5750                vmcs_read32(HOST_IA32_SYSENTER_CS),
5751                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5752         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5753                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
5754                        vmcs_read64(HOST_IA32_EFER),
5755                        vmcs_read64(HOST_IA32_PAT));
5756         if (cpu_has_load_perf_global_ctrl() &&
5757             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5758                 pr_err("PerfGlobCtl = 0x%016llx\n",
5759                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5760
5761         pr_err("*** Control State ***\n");
5762         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5763                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5764         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5765         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5766                vmcs_read32(EXCEPTION_BITMAP),
5767                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5768                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5769         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5770                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5771                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5772                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5773         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5774                vmcs_read32(VM_EXIT_INTR_INFO),
5775                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5776                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5777         pr_err("        reason=%08x qualification=%016lx\n",
5778                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5779         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5780                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5781                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5782         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5783         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5784                 pr_err("TSC Multiplier = 0x%016llx\n",
5785                        vmcs_read64(TSC_MULTIPLIER));
5786         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5787                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5788                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5789                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5790                 }
5791                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5792                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5793                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5794                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5795         }
5796         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5797                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5798         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5799                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5800         n = vmcs_read32(CR3_TARGET_COUNT);
5801         for (i = 0; i + 1 < n; i += 4)
5802                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5803                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5804                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5805         if (i < n)
5806                 pr_err("CR3 target%u=%016lx\n",
5807                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5808         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5809                 pr_err("PLE Gap=%08x Window=%08x\n",
5810                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5811         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5812                 pr_err("Virtual processor ID = 0x%04x\n",
5813                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5814 }
5815
5816 /*
5817  * The guest has exited.  See if we can fix it or if we need userspace
5818  * assistance.
5819  */
5820 static int vmx_handle_exit(struct kvm_vcpu *vcpu,
5821         enum exit_fastpath_completion exit_fastpath)
5822 {
5823         struct vcpu_vmx *vmx = to_vmx(vcpu);
5824         u32 exit_reason = vmx->exit_reason;
5825         u32 vectoring_info = vmx->idt_vectoring_info;
5826
5827         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5828
5829         /*
5830          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5831          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5832          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5833          * mode as if vcpus is in root mode, the PML buffer must has been
5834          * flushed already.
5835          */
5836         if (enable_pml)
5837                 vmx_flush_pml_buffer(vcpu);
5838
5839         /* If guest state is invalid, start emulating */
5840         if (vmx->emulation_required)
5841                 return handle_invalid_guest_state(vcpu);
5842
5843         if (is_guest_mode(vcpu)) {
5844                 /*
5845                  * The host physical addresses of some pages of guest memory
5846                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5847                  * Page). The CPU may write to these pages via their host
5848                  * physical address while L2 is running, bypassing any
5849                  * address-translation-based dirty tracking (e.g. EPT write
5850                  * protection).
5851                  *
5852                  * Mark them dirty on every exit from L2 to prevent them from
5853                  * getting out of sync with dirty tracking.
5854                  */
5855                 nested_mark_vmcs12_pages_dirty(vcpu);
5856
5857                 if (nested_vmx_exit_reflected(vcpu, exit_reason))
5858                         return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5859         }
5860
5861         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5862                 dump_vmcs();
5863                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5864                 vcpu->run->fail_entry.hardware_entry_failure_reason
5865                         = exit_reason;
5866                 return 0;
5867         }
5868
5869         if (unlikely(vmx->fail)) {
5870                 dump_vmcs();
5871                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5872                 vcpu->run->fail_entry.hardware_entry_failure_reason
5873                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5874                 return 0;
5875         }
5876
5877         /*
5878          * Note:
5879          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5880          * delivery event since it indicates guest is accessing MMIO.
5881          * The vm-exit can be triggered again after return to guest that
5882          * will cause infinite loop.
5883          */
5884         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5885                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5886                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5887                         exit_reason != EXIT_REASON_PML_FULL &&
5888                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
5889                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5890                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5891                 vcpu->run->internal.ndata = 3;
5892                 vcpu->run->internal.data[0] = vectoring_info;
5893                 vcpu->run->internal.data[1] = exit_reason;
5894                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5895                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5896                         vcpu->run->internal.ndata++;
5897                         vcpu->run->internal.data[3] =
5898                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5899                 }
5900                 return 0;
5901         }
5902
5903         if (unlikely(!enable_vnmi &&
5904                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5905                 if (vmx_interrupt_allowed(vcpu)) {
5906                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5907                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5908                            vcpu->arch.nmi_pending) {
5909                         /*
5910                          * This CPU don't support us in finding the end of an
5911                          * NMI-blocked window if the guest runs with IRQs
5912                          * disabled. So we pull the trigger after 1 s of
5913                          * futile waiting, but inform the user about this.
5914                          */
5915                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5916                                "state on VCPU %d after 1 s timeout\n",
5917                                __func__, vcpu->vcpu_id);
5918                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5919                 }
5920         }
5921
5922         if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5923                 kvm_skip_emulated_instruction(vcpu);
5924                 return 1;
5925         }
5926
5927         if (exit_reason >= kvm_vmx_max_exit_handlers)
5928                 goto unexpected_vmexit;
5929 #ifdef CONFIG_RETPOLINE
5930         if (exit_reason == EXIT_REASON_MSR_WRITE)
5931                 return kvm_emulate_wrmsr(vcpu);
5932         else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5933                 return handle_preemption_timer(vcpu);
5934         else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
5935                 return handle_interrupt_window(vcpu);
5936         else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5937                 return handle_external_interrupt(vcpu);
5938         else if (exit_reason == EXIT_REASON_HLT)
5939                 return kvm_emulate_halt(vcpu);
5940         else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5941                 return handle_ept_misconfig(vcpu);
5942 #endif
5943
5944         exit_reason = array_index_nospec(exit_reason,
5945                                          kvm_vmx_max_exit_handlers);
5946         if (!kvm_vmx_exit_handlers[exit_reason])
5947                 goto unexpected_vmexit;
5948
5949         return kvm_vmx_exit_handlers[exit_reason](vcpu);
5950
5951 unexpected_vmexit:
5952         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
5953         dump_vmcs();
5954         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5955         vcpu->run->internal.suberror =
5956                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5957         vcpu->run->internal.ndata = 1;
5958         vcpu->run->internal.data[0] = exit_reason;
5959         return 0;
5960 }
5961
5962 /*
5963  * Software based L1D cache flush which is used when microcode providing
5964  * the cache control MSR is not loaded.
5965  *
5966  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5967  * flush it is required to read in 64 KiB because the replacement algorithm
5968  * is not exactly LRU. This could be sized at runtime via topology
5969  * information but as all relevant affected CPUs have 32KiB L1D cache size
5970  * there is no point in doing so.
5971  */
5972 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5973 {
5974         int size = PAGE_SIZE << L1D_CACHE_ORDER;
5975
5976         /*
5977          * This code is only executed when the the flush mode is 'cond' or
5978          * 'always'
5979          */
5980         if (static_branch_likely(&vmx_l1d_flush_cond)) {
5981                 bool flush_l1d;
5982
5983                 /*
5984                  * Clear the per-vcpu flush bit, it gets set again
5985                  * either from vcpu_run() or from one of the unsafe
5986                  * VMEXIT handlers.
5987                  */
5988                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5989                 vcpu->arch.l1tf_flush_l1d = false;
5990
5991                 /*
5992                  * Clear the per-cpu flush bit, it gets set again from
5993                  * the interrupt handlers.
5994                  */
5995                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5996                 kvm_clear_cpu_l1tf_flush_l1d();
5997
5998                 if (!flush_l1d)
5999                         return;
6000         }
6001
6002         vcpu->stat.l1d_flush++;
6003
6004         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6005                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6006                 return;
6007         }
6008
6009         asm volatile(
6010                 /* First ensure the pages are in the TLB */
6011                 "xorl   %%eax, %%eax\n"
6012                 ".Lpopulate_tlb:\n\t"
6013                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6014                 "addl   $4096, %%eax\n\t"
6015                 "cmpl   %%eax, %[size]\n\t"
6016                 "jne    .Lpopulate_tlb\n\t"
6017                 "xorl   %%eax, %%eax\n\t"
6018                 "cpuid\n\t"
6019                 /* Now fill the cache */
6020                 "xorl   %%eax, %%eax\n"
6021                 ".Lfill_cache:\n"
6022                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6023                 "addl   $64, %%eax\n\t"
6024                 "cmpl   %%eax, %[size]\n\t"
6025                 "jne    .Lfill_cache\n\t"
6026                 "lfence\n"
6027                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6028                     [size] "r" (size)
6029                 : "eax", "ebx", "ecx", "edx");
6030 }
6031
6032 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6033 {
6034         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6035         int tpr_threshold;
6036
6037         if (is_guest_mode(vcpu) &&
6038                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6039                 return;
6040
6041         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6042         if (is_guest_mode(vcpu))
6043                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6044         else
6045                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6046 }
6047
6048 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6049 {
6050         struct vcpu_vmx *vmx = to_vmx(vcpu);
6051         u32 sec_exec_control;
6052
6053         if (!lapic_in_kernel(vcpu))
6054                 return;
6055
6056         if (!flexpriority_enabled &&
6057             !cpu_has_vmx_virtualize_x2apic_mode())
6058                 return;
6059
6060         /* Postpone execution until vmcs01 is the current VMCS. */
6061         if (is_guest_mode(vcpu)) {
6062                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6063                 return;
6064         }
6065
6066         sec_exec_control = secondary_exec_controls_get(vmx);
6067         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6068                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6069
6070         switch (kvm_get_apic_mode(vcpu)) {
6071         case LAPIC_MODE_INVALID:
6072                 WARN_ONCE(true, "Invalid local APIC state");
6073         case LAPIC_MODE_DISABLED:
6074                 break;
6075         case LAPIC_MODE_XAPIC:
6076                 if (flexpriority_enabled) {
6077                         sec_exec_control |=
6078                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6079                         vmx_flush_tlb(vcpu, true);
6080                 }
6081                 break;
6082         case LAPIC_MODE_X2APIC:
6083                 if (cpu_has_vmx_virtualize_x2apic_mode())
6084                         sec_exec_control |=
6085                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6086                 break;
6087         }
6088         secondary_exec_controls_set(vmx, sec_exec_control);
6089
6090         vmx_update_msr_bitmap(vcpu);
6091 }
6092
6093 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6094 {
6095         if (!is_guest_mode(vcpu)) {
6096                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6097                 vmx_flush_tlb(vcpu, true);
6098         }
6099 }
6100
6101 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6102 {
6103         u16 status;
6104         u8 old;
6105
6106         if (max_isr == -1)
6107                 max_isr = 0;
6108
6109         status = vmcs_read16(GUEST_INTR_STATUS);
6110         old = status >> 8;
6111         if (max_isr != old) {
6112                 status &= 0xff;
6113                 status |= max_isr << 8;
6114                 vmcs_write16(GUEST_INTR_STATUS, status);
6115         }
6116 }
6117
6118 static void vmx_set_rvi(int vector)
6119 {
6120         u16 status;
6121         u8 old;
6122
6123         if (vector == -1)
6124                 vector = 0;
6125
6126         status = vmcs_read16(GUEST_INTR_STATUS);
6127         old = (u8)status & 0xff;
6128         if ((u8)vector != old) {
6129                 status &= ~0xff;
6130                 status |= (u8)vector;
6131                 vmcs_write16(GUEST_INTR_STATUS, status);
6132         }
6133 }
6134
6135 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6136 {
6137         /*
6138          * When running L2, updating RVI is only relevant when
6139          * vmcs12 virtual-interrupt-delivery enabled.
6140          * However, it can be enabled only when L1 also
6141          * intercepts external-interrupts and in that case
6142          * we should not update vmcs02 RVI but instead intercept
6143          * interrupt. Therefore, do nothing when running L2.
6144          */
6145         if (!is_guest_mode(vcpu))
6146                 vmx_set_rvi(max_irr);
6147 }
6148
6149 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6150 {
6151         struct vcpu_vmx *vmx = to_vmx(vcpu);
6152         int max_irr;
6153         bool max_irr_updated;
6154
6155         WARN_ON(!vcpu->arch.apicv_active);
6156         if (pi_test_on(&vmx->pi_desc)) {
6157                 pi_clear_on(&vmx->pi_desc);
6158                 /*
6159                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6160                  * But on x86 this is just a compiler barrier anyway.
6161                  */
6162                 smp_mb__after_atomic();
6163                 max_irr_updated =
6164                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6165
6166                 /*
6167                  * If we are running L2 and L1 has a new pending interrupt
6168                  * which can be injected, we should re-evaluate
6169                  * what should be done with this new L1 interrupt.
6170                  * If L1 intercepts external-interrupts, we should
6171                  * exit from L2 to L1. Otherwise, interrupt should be
6172                  * delivered directly to L2.
6173                  */
6174                 if (is_guest_mode(vcpu) && max_irr_updated) {
6175                         if (nested_exit_on_intr(vcpu))
6176                                 kvm_vcpu_exiting_guest_mode(vcpu);
6177                         else
6178                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6179                 }
6180         } else {
6181                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6182         }
6183         vmx_hwapic_irr_update(vcpu, max_irr);
6184         return max_irr;
6185 }
6186
6187 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6188 {
6189         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6190
6191         return pi_test_on(pi_desc) ||
6192                 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6193 }
6194
6195 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6196 {
6197         if (!kvm_vcpu_apicv_active(vcpu))
6198                 return;
6199
6200         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6201         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6202         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6203         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6204 }
6205
6206 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6207 {
6208         struct vcpu_vmx *vmx = to_vmx(vcpu);
6209
6210         pi_clear_on(&vmx->pi_desc);
6211         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6212 }
6213
6214 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6215 {
6216         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6217
6218         /* if exit due to PF check for async PF */
6219         if (is_page_fault(vmx->exit_intr_info)) {
6220                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6221         /* Handle machine checks before interrupts are enabled */
6222         } else if (is_machine_check(vmx->exit_intr_info)) {
6223                 kvm_machine_check();
6224         /* We need to handle NMIs before interrupts are enabled */
6225         } else if (is_nmi(vmx->exit_intr_info)) {
6226                 kvm_before_interrupt(&vmx->vcpu);
6227                 asm("int $2");
6228                 kvm_after_interrupt(&vmx->vcpu);
6229         }
6230 }
6231
6232 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6233 {
6234         unsigned int vector;
6235         unsigned long entry;
6236 #ifdef CONFIG_X86_64
6237         unsigned long tmp;
6238 #endif
6239         gate_desc *desc;
6240         u32 intr_info;
6241
6242         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6243         if (WARN_ONCE(!is_external_intr(intr_info),
6244             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6245                 return;
6246
6247         vector = intr_info & INTR_INFO_VECTOR_MASK;
6248         desc = (gate_desc *)host_idt_base + vector;
6249         entry = gate_offset(desc);
6250
6251         kvm_before_interrupt(vcpu);
6252
6253         asm volatile(
6254 #ifdef CONFIG_X86_64
6255                 "mov %%" _ASM_SP ", %[sp]\n\t"
6256                 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6257                 "push $%c[ss]\n\t"
6258                 "push %[sp]\n\t"
6259 #endif
6260                 "pushf\n\t"
6261                 __ASM_SIZE(push) " $%c[cs]\n\t"
6262                 CALL_NOSPEC
6263                 :
6264 #ifdef CONFIG_X86_64
6265                 [sp]"=&r"(tmp),
6266 #endif
6267                 ASM_CALL_CONSTRAINT
6268                 :
6269                 [thunk_target]"r"(entry),
6270                 [ss]"i"(__KERNEL_DS),
6271                 [cs]"i"(__KERNEL_CS)
6272         );
6273
6274         kvm_after_interrupt(vcpu);
6275 }
6276 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6277
6278 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6279         enum exit_fastpath_completion *exit_fastpath)
6280 {
6281         struct vcpu_vmx *vmx = to_vmx(vcpu);
6282
6283         if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6284                 handle_external_interrupt_irqoff(vcpu);
6285         else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6286                 handle_exception_nmi_irqoff(vmx);
6287         else if (!is_guest_mode(vcpu) &&
6288                 vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6289                 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
6290 }
6291
6292 static bool vmx_has_emulated_msr(int index)
6293 {
6294         switch (index) {
6295         case MSR_IA32_SMBASE:
6296                 /*
6297                  * We cannot do SMM unless we can run the guest in big
6298                  * real mode.
6299                  */
6300                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6301         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6302                 return nested;
6303         case MSR_AMD64_VIRT_SPEC_CTRL:
6304                 /* This is AMD only.  */
6305                 return false;
6306         default:
6307                 return true;
6308         }
6309 }
6310
6311 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6312 {
6313         u32 exit_intr_info;
6314         bool unblock_nmi;
6315         u8 vector;
6316         bool idtv_info_valid;
6317
6318         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6319
6320         if (enable_vnmi) {
6321                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6322                         return;
6323                 /*
6324                  * Can't use vmx->exit_intr_info since we're not sure what
6325                  * the exit reason is.
6326                  */
6327                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6328                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6329                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6330                 /*
6331                  * SDM 3: 27.7.1.2 (September 2008)
6332                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6333                  * a guest IRET fault.
6334                  * SDM 3: 23.2.2 (September 2008)
6335                  * Bit 12 is undefined in any of the following cases:
6336                  *  If the VM exit sets the valid bit in the IDT-vectoring
6337                  *   information field.
6338                  *  If the VM exit is due to a double fault.
6339                  */
6340                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6341                     vector != DF_VECTOR && !idtv_info_valid)
6342                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6343                                       GUEST_INTR_STATE_NMI);
6344                 else
6345                         vmx->loaded_vmcs->nmi_known_unmasked =
6346                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6347                                   & GUEST_INTR_STATE_NMI);
6348         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6349                 vmx->loaded_vmcs->vnmi_blocked_time +=
6350                         ktime_to_ns(ktime_sub(ktime_get(),
6351                                               vmx->loaded_vmcs->entry_time));
6352 }
6353
6354 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6355                                       u32 idt_vectoring_info,
6356                                       int instr_len_field,
6357                                       int error_code_field)
6358 {
6359         u8 vector;
6360         int type;
6361         bool idtv_info_valid;
6362
6363         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6364
6365         vcpu->arch.nmi_injected = false;
6366         kvm_clear_exception_queue(vcpu);
6367         kvm_clear_interrupt_queue(vcpu);
6368
6369         if (!idtv_info_valid)
6370                 return;
6371
6372         kvm_make_request(KVM_REQ_EVENT, vcpu);
6373
6374         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6375         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6376
6377         switch (type) {
6378         case INTR_TYPE_NMI_INTR:
6379                 vcpu->arch.nmi_injected = true;
6380                 /*
6381                  * SDM 3: 27.7.1.2 (September 2008)
6382                  * Clear bit "block by NMI" before VM entry if a NMI
6383                  * delivery faulted.
6384                  */
6385                 vmx_set_nmi_mask(vcpu, false);
6386                 break;
6387         case INTR_TYPE_SOFT_EXCEPTION:
6388                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6389                 /* fall through */
6390         case INTR_TYPE_HARD_EXCEPTION:
6391                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6392                         u32 err = vmcs_read32(error_code_field);
6393                         kvm_requeue_exception_e(vcpu, vector, err);
6394                 } else
6395                         kvm_requeue_exception(vcpu, vector);
6396                 break;
6397         case INTR_TYPE_SOFT_INTR:
6398                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6399                 /* fall through */
6400         case INTR_TYPE_EXT_INTR:
6401                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6402                 break;
6403         default:
6404                 break;
6405         }
6406 }
6407
6408 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6409 {
6410         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6411                                   VM_EXIT_INSTRUCTION_LEN,
6412                                   IDT_VECTORING_ERROR_CODE);
6413 }
6414
6415 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6416 {
6417         __vmx_complete_interrupts(vcpu,
6418                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6419                                   VM_ENTRY_INSTRUCTION_LEN,
6420                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6421
6422         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6423 }
6424
6425 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6426 {
6427         int i, nr_msrs;
6428         struct perf_guest_switch_msr *msrs;
6429
6430         msrs = perf_guest_get_msrs(&nr_msrs);
6431
6432         if (!msrs)
6433                 return;
6434
6435         for (i = 0; i < nr_msrs; i++)
6436                 if (msrs[i].host == msrs[i].guest)
6437                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6438                 else
6439                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6440                                         msrs[i].host, false);
6441 }
6442
6443 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6444 {
6445         u32 host_umwait_control;
6446
6447         if (!vmx_has_waitpkg(vmx))
6448                 return;
6449
6450         host_umwait_control = get_umwait_control_msr();
6451
6452         if (vmx->msr_ia32_umwait_control != host_umwait_control)
6453                 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6454                         vmx->msr_ia32_umwait_control,
6455                         host_umwait_control, false);
6456         else
6457                 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6458 }
6459
6460 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6461 {
6462         struct vcpu_vmx *vmx = to_vmx(vcpu);
6463         u64 tscl;
6464         u32 delta_tsc;
6465
6466         if (vmx->req_immediate_exit) {
6467                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6468                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6469         } else if (vmx->hv_deadline_tsc != -1) {
6470                 tscl = rdtsc();
6471                 if (vmx->hv_deadline_tsc > tscl)
6472                         /* set_hv_timer ensures the delta fits in 32-bits */
6473                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6474                                 cpu_preemption_timer_multi);
6475                 else
6476                         delta_tsc = 0;
6477
6478                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6479                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6480         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6481                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6482                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6483         }
6484 }
6485
6486 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6487 {
6488         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6489                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6490                 vmcs_writel(HOST_RSP, host_rsp);
6491         }
6492 }
6493
6494 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6495
6496 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6497 {
6498         struct vcpu_vmx *vmx = to_vmx(vcpu);
6499         unsigned long cr3, cr4;
6500
6501         /* Record the guest's net vcpu time for enforced NMI injections. */
6502         if (unlikely(!enable_vnmi &&
6503                      vmx->loaded_vmcs->soft_vnmi_blocked))
6504                 vmx->loaded_vmcs->entry_time = ktime_get();
6505
6506         /* Don't enter VMX if guest state is invalid, let the exit handler
6507            start emulation until we arrive back to a valid state */
6508         if (vmx->emulation_required)
6509                 return;
6510
6511         if (vmx->ple_window_dirty) {
6512                 vmx->ple_window_dirty = false;
6513                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6514         }
6515
6516         /*
6517          * We did this in prepare_switch_to_guest, because it needs to
6518          * be within srcu_read_lock.
6519          */
6520         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6521
6522         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6523                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6524         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6525                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6526
6527         cr3 = __get_current_cr3_fast();
6528         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6529                 vmcs_writel(HOST_CR3, cr3);
6530                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6531         }
6532
6533         cr4 = cr4_read_shadow();
6534         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6535                 vmcs_writel(HOST_CR4, cr4);
6536                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6537         }
6538
6539         /* When single-stepping over STI and MOV SS, we must clear the
6540          * corresponding interruptibility bits in the guest state. Otherwise
6541          * vmentry fails as it then expects bit 14 (BS) in pending debug
6542          * exceptions being set, but that's not correct for the guest debugging
6543          * case. */
6544         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6545                 vmx_set_interrupt_shadow(vcpu, 0);
6546
6547         kvm_load_guest_xsave_state(vcpu);
6548
6549         if (static_cpu_has(X86_FEATURE_PKU) &&
6550             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6551             vcpu->arch.pkru != vmx->host_pkru)
6552                 __write_pkru(vcpu->arch.pkru);
6553
6554         pt_guest_enter(vmx);
6555
6556         if (vcpu_to_pmu(vcpu)->version)
6557                 atomic_switch_perf_msrs(vmx);
6558         atomic_switch_umwait_control_msr(vmx);
6559
6560         if (enable_preemption_timer)
6561                 vmx_update_hv_timer(vcpu);
6562
6563         if (lapic_in_kernel(vcpu) &&
6564                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6565                 kvm_wait_lapic_expire(vcpu);
6566
6567         /*
6568          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6569          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6570          * is no need to worry about the conditional branch over the wrmsr
6571          * being speculatively taken.
6572          */
6573         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6574
6575         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6576         if (static_branch_unlikely(&vmx_l1d_should_flush))
6577                 vmx_l1d_flush(vcpu);
6578         else if (static_branch_unlikely(&mds_user_clear))
6579                 mds_clear_cpu_buffers();
6580
6581         if (vcpu->arch.cr2 != read_cr2())
6582                 write_cr2(vcpu->arch.cr2);
6583
6584         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6585                                    vmx->loaded_vmcs->launched);
6586
6587         vcpu->arch.cr2 = read_cr2();
6588
6589         /*
6590          * We do not use IBRS in the kernel. If this vCPU has used the
6591          * SPEC_CTRL MSR it may have left it on; save the value and
6592          * turn it off. This is much more efficient than blindly adding
6593          * it to the atomic save/restore list. Especially as the former
6594          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6595          *
6596          * For non-nested case:
6597          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6598          * save it.
6599          *
6600          * For nested case:
6601          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6602          * save it.
6603          */
6604         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6605                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6606
6607         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6608
6609         /* All fields are clean at this point */
6610         if (static_branch_unlikely(&enable_evmcs))
6611                 current_evmcs->hv_clean_fields |=
6612                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6613
6614         if (static_branch_unlikely(&enable_evmcs))
6615                 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6616
6617         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6618         if (vmx->host_debugctlmsr)
6619                 update_debugctlmsr(vmx->host_debugctlmsr);
6620
6621 #ifndef CONFIG_X86_64
6622         /*
6623          * The sysexit path does not restore ds/es, so we must set them to
6624          * a reasonable value ourselves.
6625          *
6626          * We can't defer this to vmx_prepare_switch_to_host() since that
6627          * function may be executed in interrupt context, which saves and
6628          * restore segments around it, nullifying its effect.
6629          */
6630         loadsegment(ds, __USER_DS);
6631         loadsegment(es, __USER_DS);
6632 #endif
6633
6634         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6635                                   | (1 << VCPU_EXREG_RFLAGS)
6636                                   | (1 << VCPU_EXREG_PDPTR)
6637                                   | (1 << VCPU_EXREG_SEGMENTS)
6638                                   | (1 << VCPU_EXREG_CR3));
6639         vcpu->arch.regs_dirty = 0;
6640
6641         pt_guest_exit(vmx);
6642
6643         /*
6644          * eager fpu is enabled if PKEY is supported and CR4 is switched
6645          * back on host, so it is safe to read guest PKRU from current
6646          * XSAVE.
6647          */
6648         if (static_cpu_has(X86_FEATURE_PKU) &&
6649             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6650                 vcpu->arch.pkru = rdpkru();
6651                 if (vcpu->arch.pkru != vmx->host_pkru)
6652                         __write_pkru(vmx->host_pkru);
6653         }
6654
6655         kvm_load_host_xsave_state(vcpu);
6656
6657         vmx->nested.nested_run_pending = 0;
6658         vmx->idt_vectoring_info = 0;
6659
6660         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6661         if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6662                 kvm_machine_check();
6663
6664         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6665                 return;
6666
6667         vmx->loaded_vmcs->launched = 1;
6668         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6669
6670         vmx_recover_nmi_blocking(vmx);
6671         vmx_complete_interrupts(vmx);
6672 }
6673
6674 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6675 {
6676         struct vcpu_vmx *vmx = to_vmx(vcpu);
6677
6678         if (enable_pml)
6679                 vmx_destroy_pml_buffer(vmx);
6680         free_vpid(vmx->vpid);
6681         nested_vmx_free_vcpu(vcpu);
6682         free_loaded_vmcs(vmx->loaded_vmcs);
6683 }
6684
6685 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6686 {
6687         struct vcpu_vmx *vmx;
6688         unsigned long *msr_bitmap;
6689         int i, cpu, err;
6690
6691         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6692         vmx = to_vmx(vcpu);
6693
6694         err = -ENOMEM;
6695
6696         vmx->vpid = allocate_vpid();
6697
6698         /*
6699          * If PML is turned on, failure on enabling PML just results in failure
6700          * of creating the vcpu, therefore we can simplify PML logic (by
6701          * avoiding dealing with cases, such as enabling PML partially on vcpus
6702          * for the guest), etc.
6703          */
6704         if (enable_pml) {
6705                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6706                 if (!vmx->pml_pg)
6707                         goto free_vpid;
6708         }
6709
6710         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
6711
6712         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6713                 u32 index = vmx_msr_index[i];
6714                 u32 data_low, data_high;
6715                 int j = vmx->nmsrs;
6716
6717                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6718                         continue;
6719                 if (wrmsr_safe(index, data_low, data_high) < 0)
6720                         continue;
6721
6722                 vmx->guest_msrs[j].index = i;
6723                 vmx->guest_msrs[j].data = 0;
6724                 switch (index) {
6725                 case MSR_IA32_TSX_CTRL:
6726                         /*
6727                          * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6728                          * let's avoid changing CPUID bits under the host
6729                          * kernel's feet.
6730                          */
6731                         vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6732                         break;
6733                 default:
6734                         vmx->guest_msrs[j].mask = -1ull;
6735                         break;
6736                 }
6737                 ++vmx->nmsrs;
6738         }
6739
6740         err = alloc_loaded_vmcs(&vmx->vmcs01);
6741         if (err < 0)
6742                 goto free_pml;
6743
6744         msr_bitmap = vmx->vmcs01.msr_bitmap;
6745         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6746         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6747         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6748         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6749         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6750         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6751         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6752         if (kvm_cstate_in_guest(vcpu->kvm)) {
6753                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6754                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6755                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6756                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6757         }
6758         vmx->msr_bitmap_mode = 0;
6759
6760         vmx->loaded_vmcs = &vmx->vmcs01;
6761         cpu = get_cpu();
6762         vmx_vcpu_load(vcpu, cpu);
6763         vcpu->cpu = cpu;
6764         init_vmcs(vmx);
6765         vmx_vcpu_put(vcpu);
6766         put_cpu();
6767         if (cpu_need_virtualize_apic_accesses(vcpu)) {
6768                 err = alloc_apic_access_page(vcpu->kvm);
6769                 if (err)
6770                         goto free_vmcs;
6771         }
6772
6773         if (enable_ept && !enable_unrestricted_guest) {
6774                 err = init_rmode_identity_map(vcpu->kvm);
6775                 if (err)
6776                         goto free_vmcs;
6777         }
6778
6779         if (nested)
6780                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6781                                            vmx_capability.ept);
6782         else
6783                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6784
6785         vmx->nested.posted_intr_nv = -1;
6786         vmx->nested.current_vmptr = -1ull;
6787
6788         vcpu->arch.microcode_version = 0x100000000ULL;
6789         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6790
6791         /*
6792          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6793          * or POSTED_INTR_WAKEUP_VECTOR.
6794          */
6795         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6796         vmx->pi_desc.sn = 1;
6797
6798         vmx->ept_pointer = INVALID_PAGE;
6799
6800         return 0;
6801
6802 free_vmcs:
6803         free_loaded_vmcs(vmx->loaded_vmcs);
6804 free_pml:
6805         vmx_destroy_pml_buffer(vmx);
6806 free_vpid:
6807         free_vpid(vmx->vpid);
6808         return err;
6809 }
6810
6811 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6812 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6813
6814 static int vmx_vm_init(struct kvm *kvm)
6815 {
6816         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6817
6818         if (!ple_gap)
6819                 kvm->arch.pause_in_guest = true;
6820
6821         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6822                 switch (l1tf_mitigation) {
6823                 case L1TF_MITIGATION_OFF:
6824                 case L1TF_MITIGATION_FLUSH_NOWARN:
6825                         /* 'I explicitly don't care' is set */
6826                         break;
6827                 case L1TF_MITIGATION_FLUSH:
6828                 case L1TF_MITIGATION_FLUSH_NOSMT:
6829                 case L1TF_MITIGATION_FULL:
6830                         /*
6831                          * Warn upon starting the first VM in a potentially
6832                          * insecure environment.
6833                          */
6834                         if (sched_smt_active())
6835                                 pr_warn_once(L1TF_MSG_SMT);
6836                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6837                                 pr_warn_once(L1TF_MSG_L1D);
6838                         break;
6839                 case L1TF_MITIGATION_FULL_FORCE:
6840                         /* Flush is enforced */
6841                         break;
6842                 }
6843         }
6844         kvm_apicv_init(kvm, enable_apicv);
6845         return 0;
6846 }
6847
6848 static int __init vmx_check_processor_compat(void)
6849 {
6850         struct vmcs_config vmcs_conf;
6851         struct vmx_capability vmx_cap;
6852
6853         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6854             !this_cpu_has(X86_FEATURE_VMX)) {
6855                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6856                 return -EIO;
6857         }
6858
6859         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6860                 return -EIO;
6861         if (nested)
6862                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6863         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6864                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6865                                 smp_processor_id());
6866                 return -EIO;
6867         }
6868         return 0;
6869 }
6870
6871 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6872 {
6873         u8 cache;
6874         u64 ipat = 0;
6875
6876         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6877          * memory aliases with conflicting memory types and sometimes MCEs.
6878          * We have to be careful as to what are honored and when.
6879          *
6880          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
6881          * UC.  The effective memory type is UC or WC depending on guest PAT.
6882          * This was historically the source of MCEs and we want to be
6883          * conservative.
6884          *
6885          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6886          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
6887          * EPT memory type is set to WB.  The effective memory type is forced
6888          * WB.
6889          *
6890          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
6891          * EPT memory type is used to emulate guest CD/MTRR.
6892          */
6893
6894         if (is_mmio) {
6895                 cache = MTRR_TYPE_UNCACHABLE;
6896                 goto exit;
6897         }
6898
6899         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6900                 ipat = VMX_EPT_IPAT_BIT;
6901                 cache = MTRR_TYPE_WRBACK;
6902                 goto exit;
6903         }
6904
6905         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6906                 ipat = VMX_EPT_IPAT_BIT;
6907                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6908                         cache = MTRR_TYPE_WRBACK;
6909                 else
6910                         cache = MTRR_TYPE_UNCACHABLE;
6911                 goto exit;
6912         }
6913
6914         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6915
6916 exit:
6917         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6918 }
6919
6920 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6921 {
6922         /*
6923          * These bits in the secondary execution controls field
6924          * are dynamic, the others are mostly based on the hypervisor
6925          * architecture and the guest's CPUID.  Do not touch the
6926          * dynamic bits.
6927          */
6928         u32 mask =
6929                 SECONDARY_EXEC_SHADOW_VMCS |
6930                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6931                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6932                 SECONDARY_EXEC_DESC;
6933
6934         u32 new_ctl = vmx->secondary_exec_control;
6935         u32 cur_ctl = secondary_exec_controls_get(vmx);
6936
6937         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6938 }
6939
6940 /*
6941  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6942  * (indicating "allowed-1") if they are supported in the guest's CPUID.
6943  */
6944 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6945 {
6946         struct vcpu_vmx *vmx = to_vmx(vcpu);
6947         struct kvm_cpuid_entry2 *entry;
6948
6949         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6950         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6951
6952 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
6953         if (entry && (entry->_reg & (_cpuid_mask)))                     \
6954                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
6955 } while (0)
6956
6957         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6958         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
6959         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
6960         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
6961         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
6962         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
6963         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
6964         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
6965         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
6966         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
6967         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
6968         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
6969         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
6970         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
6971         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
6972
6973         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6974         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
6975         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
6976         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
6977         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
6978         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
6979         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
6980
6981 #undef cr4_fixed1_update
6982 }
6983
6984 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6985 {
6986         struct vcpu_vmx *vmx = to_vmx(vcpu);
6987
6988         if (kvm_mpx_supported()) {
6989                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
6990
6991                 if (mpx_enabled) {
6992                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6993                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6994                 } else {
6995                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6996                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6997                 }
6998         }
6999 }
7000
7001 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7002 {
7003         struct vcpu_vmx *vmx = to_vmx(vcpu);
7004         struct kvm_cpuid_entry2 *best = NULL;
7005         int i;
7006
7007         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7008                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7009                 if (!best)
7010                         return;
7011                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7012                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7013                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7014                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7015         }
7016
7017         /* Get the number of configurable Address Ranges for filtering */
7018         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7019                                                 PT_CAP_num_address_ranges);
7020
7021         /* Initialize and clear the no dependency bits */
7022         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7023                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7024
7025         /*
7026          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7027          * will inject an #GP
7028          */
7029         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7030                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7031
7032         /*
7033          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7034          * PSBFreq can be set
7035          */
7036         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7037                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7038                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7039
7040         /*
7041          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7042          * MTCFreq can be set
7043          */
7044         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7045                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7046                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7047
7048         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7049         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7050                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7051                                                         RTIT_CTL_PTW_EN);
7052
7053         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7054         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7055                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7056
7057         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7058         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7059                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7060
7061         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7062         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7063                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7064
7065         /* unmask address range configure area */
7066         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7067                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7068 }
7069
7070 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7071 {
7072         struct vcpu_vmx *vmx = to_vmx(vcpu);
7073
7074         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7075         vcpu->arch.xsaves_enabled = false;
7076
7077         if (cpu_has_secondary_exec_ctrls()) {
7078                 vmx_compute_secondary_exec_control(vmx);
7079                 vmcs_set_secondary_exec_control(vmx);
7080         }
7081
7082         if (nested_vmx_allowed(vcpu))
7083                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7084                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7085                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7086         else
7087                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7088                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7089                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7090
7091         if (nested_vmx_allowed(vcpu)) {
7092                 nested_vmx_cr_fixed1_bits_update(vcpu);
7093                 nested_vmx_entry_exit_ctls_update(vcpu);
7094         }
7095
7096         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7097                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7098                 update_intel_pt_cfg(vcpu);
7099
7100         if (boot_cpu_has(X86_FEATURE_RTM)) {
7101                 struct shared_msr_entry *msr;
7102                 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7103                 if (msr) {
7104                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7105                         vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7106                 }
7107         }
7108 }
7109
7110 static __init void vmx_set_cpu_caps(void)
7111 {
7112         kvm_set_cpu_caps();
7113
7114         /* CPUID 0x1 */
7115         if (nested)
7116                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7117
7118         /* CPUID 0x7 */
7119         if (kvm_mpx_supported())
7120                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7121         if (cpu_has_vmx_invpcid())
7122                 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
7123         if (vmx_pt_mode_is_host_guest())
7124                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7125
7126         /* PKU is not yet implemented for shadow paging. */
7127         if (enable_ept && boot_cpu_has(X86_FEATURE_OSPKE))
7128                 kvm_cpu_cap_check_and_set(X86_FEATURE_PKU);
7129
7130         if (vmx_umip_emulated())
7131                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7132
7133         /* CPUID 0xD.1 */
7134         supported_xss = 0;
7135         if (!vmx_xsaves_supported())
7136                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7137
7138         /* CPUID 0x80000001 */
7139         if (!cpu_has_vmx_rdtscp())
7140                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7141 }
7142
7143 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7144 {
7145         to_vmx(vcpu)->req_immediate_exit = true;
7146 }
7147
7148 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7149                                   struct x86_instruction_info *info)
7150 {
7151         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7152         unsigned short port;
7153         bool intercept;
7154         int size;
7155
7156         if (info->intercept == x86_intercept_in ||
7157             info->intercept == x86_intercept_ins) {
7158                 port = info->src_val;
7159                 size = info->dst_bytes;
7160         } else {
7161                 port = info->dst_val;
7162                 size = info->src_bytes;
7163         }
7164
7165         /*
7166          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7167          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7168          * control.
7169          *
7170          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7171          */
7172         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7173                 intercept = nested_cpu_has(vmcs12,
7174                                            CPU_BASED_UNCOND_IO_EXITING);
7175         else
7176                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7177
7178         /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7179         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7180 }
7181
7182 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7183                                struct x86_instruction_info *info,
7184                                enum x86_intercept_stage stage,
7185                                struct x86_exception *exception)
7186 {
7187         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7188
7189         switch (info->intercept) {
7190         /*
7191          * RDPID causes #UD if disabled through secondary execution controls.
7192          * Because it is marked as EmulateOnUD, we need to intercept it here.
7193          */
7194         case x86_intercept_rdtscp:
7195                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7196                         exception->vector = UD_VECTOR;
7197                         exception->error_code_valid = false;
7198                         return X86EMUL_PROPAGATE_FAULT;
7199                 }
7200                 break;
7201
7202         case x86_intercept_in:
7203         case x86_intercept_ins:
7204         case x86_intercept_out:
7205         case x86_intercept_outs:
7206                 return vmx_check_intercept_io(vcpu, info);
7207
7208         case x86_intercept_lgdt:
7209         case x86_intercept_lidt:
7210         case x86_intercept_lldt:
7211         case x86_intercept_ltr:
7212         case x86_intercept_sgdt:
7213         case x86_intercept_sidt:
7214         case x86_intercept_sldt:
7215         case x86_intercept_str:
7216                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7217                         return X86EMUL_CONTINUE;
7218
7219                 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7220                 break;
7221
7222         /* TODO: check more intercepts... */
7223         default:
7224                 break;
7225         }
7226
7227         return X86EMUL_UNHANDLEABLE;
7228 }
7229
7230 #ifdef CONFIG_X86_64
7231 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7232 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7233                                   u64 divisor, u64 *result)
7234 {
7235         u64 low = a << shift, high = a >> (64 - shift);
7236
7237         /* To avoid the overflow on divq */
7238         if (high >= divisor)
7239                 return 1;
7240
7241         /* Low hold the result, high hold rem which is discarded */
7242         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7243             "rm" (divisor), "0" (low), "1" (high));
7244         *result = low;
7245
7246         return 0;
7247 }
7248
7249 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7250                             bool *expired)
7251 {
7252         struct vcpu_vmx *vmx;
7253         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7254         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7255
7256         if (kvm_mwait_in_guest(vcpu->kvm) ||
7257                 kvm_can_post_timer_interrupt(vcpu))
7258                 return -EOPNOTSUPP;
7259
7260         vmx = to_vmx(vcpu);
7261         tscl = rdtsc();
7262         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7263         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7264         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7265                                                     ktimer->timer_advance_ns);
7266
7267         if (delta_tsc > lapic_timer_advance_cycles)
7268                 delta_tsc -= lapic_timer_advance_cycles;
7269         else
7270                 delta_tsc = 0;
7271
7272         /* Convert to host delta tsc if tsc scaling is enabled */
7273         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7274             delta_tsc && u64_shl_div_u64(delta_tsc,
7275                                 kvm_tsc_scaling_ratio_frac_bits,
7276                                 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7277                 return -ERANGE;
7278
7279         /*
7280          * If the delta tsc can't fit in the 32 bit after the multi shift,
7281          * we can't use the preemption timer.
7282          * It's possible that it fits on later vmentries, but checking
7283          * on every vmentry is costly so we just use an hrtimer.
7284          */
7285         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7286                 return -ERANGE;
7287
7288         vmx->hv_deadline_tsc = tscl + delta_tsc;
7289         *expired = !delta_tsc;
7290         return 0;
7291 }
7292
7293 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7294 {
7295         to_vmx(vcpu)->hv_deadline_tsc = -1;
7296 }
7297 #endif
7298
7299 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7300 {
7301         if (!kvm_pause_in_guest(vcpu->kvm))
7302                 shrink_ple_window(vcpu);
7303 }
7304
7305 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7306                                      struct kvm_memory_slot *slot)
7307 {
7308         if (!kvm_dirty_log_manual_protect_and_init_set(kvm))
7309                 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7310         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7311 }
7312
7313 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7314                                        struct kvm_memory_slot *slot)
7315 {
7316         kvm_mmu_slot_set_dirty(kvm, slot);
7317 }
7318
7319 static void vmx_flush_log_dirty(struct kvm *kvm)
7320 {
7321         kvm_flush_pml_buffers(kvm);
7322 }
7323
7324 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7325 {
7326         struct vmcs12 *vmcs12;
7327         struct vcpu_vmx *vmx = to_vmx(vcpu);
7328         gpa_t gpa, dst;
7329
7330         if (is_guest_mode(vcpu)) {
7331                 WARN_ON_ONCE(vmx->nested.pml_full);
7332
7333                 /*
7334                  * Check if PML is enabled for the nested guest.
7335                  * Whether eptp bit 6 is set is already checked
7336                  * as part of A/D emulation.
7337                  */
7338                 vmcs12 = get_vmcs12(vcpu);
7339                 if (!nested_cpu_has_pml(vmcs12))
7340                         return 0;
7341
7342                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7343                         vmx->nested.pml_full = true;
7344                         return 1;
7345                 }
7346
7347                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7348                 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7349
7350                 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7351                                          offset_in_page(dst), sizeof(gpa)))
7352                         return 0;
7353
7354                 vmcs12->guest_pml_index--;
7355         }
7356
7357         return 0;
7358 }
7359
7360 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7361                                            struct kvm_memory_slot *memslot,
7362                                            gfn_t offset, unsigned long mask)
7363 {
7364         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7365 }
7366
7367 static void __pi_post_block(struct kvm_vcpu *vcpu)
7368 {
7369         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7370         struct pi_desc old, new;
7371         unsigned int dest;
7372
7373         do {
7374                 old.control = new.control = pi_desc->control;
7375                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7376                      "Wakeup handler not enabled while the VCPU is blocked\n");
7377
7378                 dest = cpu_physical_id(vcpu->cpu);
7379
7380                 if (x2apic_enabled())
7381                         new.ndst = dest;
7382                 else
7383                         new.ndst = (dest << 8) & 0xFF00;
7384
7385                 /* set 'NV' to 'notification vector' */
7386                 new.nv = POSTED_INTR_VECTOR;
7387         } while (cmpxchg64(&pi_desc->control, old.control,
7388                            new.control) != old.control);
7389
7390         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7391                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7392                 list_del(&vcpu->blocked_vcpu_list);
7393                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7394                 vcpu->pre_pcpu = -1;
7395         }
7396 }
7397
7398 /*
7399  * This routine does the following things for vCPU which is going
7400  * to be blocked if VT-d PI is enabled.
7401  * - Store the vCPU to the wakeup list, so when interrupts happen
7402  *   we can find the right vCPU to wake up.
7403  * - Change the Posted-interrupt descriptor as below:
7404  *      'NDST' <-- vcpu->pre_pcpu
7405  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7406  * - If 'ON' is set during this process, which means at least one
7407  *   interrupt is posted for this vCPU, we cannot block it, in
7408  *   this case, return 1, otherwise, return 0.
7409  *
7410  */
7411 static int pi_pre_block(struct kvm_vcpu *vcpu)
7412 {
7413         unsigned int dest;
7414         struct pi_desc old, new;
7415         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7416
7417         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7418                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
7419                 !kvm_vcpu_apicv_active(vcpu))
7420                 return 0;
7421
7422         WARN_ON(irqs_disabled());
7423         local_irq_disable();
7424         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7425                 vcpu->pre_pcpu = vcpu->cpu;
7426                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7427                 list_add_tail(&vcpu->blocked_vcpu_list,
7428                               &per_cpu(blocked_vcpu_on_cpu,
7429                                        vcpu->pre_pcpu));
7430                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7431         }
7432
7433         do {
7434                 old.control = new.control = pi_desc->control;
7435
7436                 WARN((pi_desc->sn == 1),
7437                      "Warning: SN field of posted-interrupts "
7438                      "is set before blocking\n");
7439
7440                 /*
7441                  * Since vCPU can be preempted during this process,
7442                  * vcpu->cpu could be different with pre_pcpu, we
7443                  * need to set pre_pcpu as the destination of wakeup
7444                  * notification event, then we can find the right vCPU
7445                  * to wakeup in wakeup handler if interrupts happen
7446                  * when the vCPU is in blocked state.
7447                  */
7448                 dest = cpu_physical_id(vcpu->pre_pcpu);
7449
7450                 if (x2apic_enabled())
7451                         new.ndst = dest;
7452                 else
7453                         new.ndst = (dest << 8) & 0xFF00;
7454
7455                 /* set 'NV' to 'wakeup vector' */
7456                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7457         } while (cmpxchg64(&pi_desc->control, old.control,
7458                            new.control) != old.control);
7459
7460         /* We should not block the vCPU if an interrupt is posted for it.  */
7461         if (pi_test_on(pi_desc) == 1)
7462                 __pi_post_block(vcpu);
7463
7464         local_irq_enable();
7465         return (vcpu->pre_pcpu == -1);
7466 }
7467
7468 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7469 {
7470         if (pi_pre_block(vcpu))
7471                 return 1;
7472
7473         if (kvm_lapic_hv_timer_in_use(vcpu))
7474                 kvm_lapic_switch_to_sw_timer(vcpu);
7475
7476         return 0;
7477 }
7478
7479 static void pi_post_block(struct kvm_vcpu *vcpu)
7480 {
7481         if (vcpu->pre_pcpu == -1)
7482                 return;
7483
7484         WARN_ON(irqs_disabled());
7485         local_irq_disable();
7486         __pi_post_block(vcpu);
7487         local_irq_enable();
7488 }
7489
7490 static void vmx_post_block(struct kvm_vcpu *vcpu)
7491 {
7492         if (kvm_x86_ops.set_hv_timer)
7493                 kvm_lapic_switch_to_hv_timer(vcpu);
7494
7495         pi_post_block(vcpu);
7496 }
7497
7498 /*
7499  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7500  *
7501  * @kvm: kvm
7502  * @host_irq: host irq of the interrupt
7503  * @guest_irq: gsi of the interrupt
7504  * @set: set or unset PI
7505  * returns 0 on success, < 0 on failure
7506  */
7507 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7508                               uint32_t guest_irq, bool set)
7509 {
7510         struct kvm_kernel_irq_routing_entry *e;
7511         struct kvm_irq_routing_table *irq_rt;
7512         struct kvm_lapic_irq irq;
7513         struct kvm_vcpu *vcpu;
7514         struct vcpu_data vcpu_info;
7515         int idx, ret = 0;
7516
7517         if (!kvm_arch_has_assigned_device(kvm) ||
7518                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7519                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7520                 return 0;
7521
7522         idx = srcu_read_lock(&kvm->irq_srcu);
7523         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7524         if (guest_irq >= irq_rt->nr_rt_entries ||
7525             hlist_empty(&irq_rt->map[guest_irq])) {
7526                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7527                              guest_irq, irq_rt->nr_rt_entries);
7528                 goto out;
7529         }
7530
7531         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7532                 if (e->type != KVM_IRQ_ROUTING_MSI)
7533                         continue;
7534                 /*
7535                  * VT-d PI cannot support posting multicast/broadcast
7536                  * interrupts to a vCPU, we still use interrupt remapping
7537                  * for these kind of interrupts.
7538                  *
7539                  * For lowest-priority interrupts, we only support
7540                  * those with single CPU as the destination, e.g. user
7541                  * configures the interrupts via /proc/irq or uses
7542                  * irqbalance to make the interrupts single-CPU.
7543                  *
7544                  * We will support full lowest-priority interrupt later.
7545                  *
7546                  * In addition, we can only inject generic interrupts using
7547                  * the PI mechanism, refuse to route others through it.
7548                  */
7549
7550                 kvm_set_msi_irq(kvm, e, &irq);
7551                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7552                     !kvm_irq_is_postable(&irq)) {
7553                         /*
7554                          * Make sure the IRTE is in remapped mode if
7555                          * we don't handle it in posted mode.
7556                          */
7557                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7558                         if (ret < 0) {
7559                                 printk(KERN_INFO
7560                                    "failed to back to remapped mode, irq: %u\n",
7561                                    host_irq);
7562                                 goto out;
7563                         }
7564
7565                         continue;
7566                 }
7567
7568                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7569                 vcpu_info.vector = irq.vector;
7570
7571                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7572                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7573
7574                 if (set)
7575                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7576                 else
7577                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7578
7579                 if (ret < 0) {
7580                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
7581                                         __func__);
7582                         goto out;
7583                 }
7584         }
7585
7586         ret = 0;
7587 out:
7588         srcu_read_unlock(&kvm->irq_srcu, idx);
7589         return ret;
7590 }
7591
7592 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7593 {
7594         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7595                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7596                         FEAT_CTL_LMCE_ENABLED;
7597         else
7598                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7599                         ~FEAT_CTL_LMCE_ENABLED;
7600 }
7601
7602 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7603 {
7604         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7605         if (to_vmx(vcpu)->nested.nested_run_pending)
7606                 return 0;
7607         return 1;
7608 }
7609
7610 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7611 {
7612         struct vcpu_vmx *vmx = to_vmx(vcpu);
7613
7614         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7615         if (vmx->nested.smm.guest_mode)
7616                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7617
7618         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7619         vmx->nested.vmxon = false;
7620         vmx_clear_hlt(vcpu);
7621         return 0;
7622 }
7623
7624 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7625 {
7626         struct vcpu_vmx *vmx = to_vmx(vcpu);
7627         int ret;
7628
7629         if (vmx->nested.smm.vmxon) {
7630                 vmx->nested.vmxon = true;
7631                 vmx->nested.smm.vmxon = false;
7632         }
7633
7634         if (vmx->nested.smm.guest_mode) {
7635                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7636                 if (ret)
7637                         return ret;
7638
7639                 vmx->nested.smm.guest_mode = false;
7640         }
7641         return 0;
7642 }
7643
7644 static int enable_smi_window(struct kvm_vcpu *vcpu)
7645 {
7646         return 0;
7647 }
7648
7649 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7650 {
7651         return false;
7652 }
7653
7654 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7655 {
7656         return to_vmx(vcpu)->nested.vmxon;
7657 }
7658
7659 static void hardware_unsetup(void)
7660 {
7661         if (nested)
7662                 nested_vmx_hardware_unsetup();
7663
7664         free_kvm_area();
7665 }
7666
7667 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7668 {
7669         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7670                           BIT(APICV_INHIBIT_REASON_HYPERV);
7671
7672         return supported & BIT(bit);
7673 }
7674
7675 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7676         .hardware_unsetup = hardware_unsetup,
7677
7678         .hardware_enable = hardware_enable,
7679         .hardware_disable = hardware_disable,
7680         .cpu_has_accelerated_tpr = report_flexpriority,
7681         .has_emulated_msr = vmx_has_emulated_msr,
7682
7683         .vm_size = sizeof(struct kvm_vmx),
7684         .vm_init = vmx_vm_init,
7685
7686         .vcpu_create = vmx_create_vcpu,
7687         .vcpu_free = vmx_free_vcpu,
7688         .vcpu_reset = vmx_vcpu_reset,
7689
7690         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7691         .vcpu_load = vmx_vcpu_load,
7692         .vcpu_put = vmx_vcpu_put,
7693
7694         .update_bp_intercept = update_exception_bitmap,
7695         .get_msr_feature = vmx_get_msr_feature,
7696         .get_msr = vmx_get_msr,
7697         .set_msr = vmx_set_msr,
7698         .get_segment_base = vmx_get_segment_base,
7699         .get_segment = vmx_get_segment,
7700         .set_segment = vmx_set_segment,
7701         .get_cpl = vmx_get_cpl,
7702         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7703         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7704         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7705         .set_cr0 = vmx_set_cr0,
7706         .set_cr4 = vmx_set_cr4,
7707         .set_efer = vmx_set_efer,
7708         .get_idt = vmx_get_idt,
7709         .set_idt = vmx_set_idt,
7710         .get_gdt = vmx_get_gdt,
7711         .set_gdt = vmx_set_gdt,
7712         .get_dr6 = vmx_get_dr6,
7713         .set_dr6 = vmx_set_dr6,
7714         .set_dr7 = vmx_set_dr7,
7715         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7716         .cache_reg = vmx_cache_reg,
7717         .get_rflags = vmx_get_rflags,
7718         .set_rflags = vmx_set_rflags,
7719
7720         .tlb_flush = vmx_flush_tlb,
7721         .tlb_flush_gva = vmx_flush_tlb_gva,
7722
7723         .run = vmx_vcpu_run,
7724         .handle_exit = vmx_handle_exit,
7725         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7726         .update_emulated_instruction = vmx_update_emulated_instruction,
7727         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7728         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7729         .patch_hypercall = vmx_patch_hypercall,
7730         .set_irq = vmx_inject_irq,
7731         .set_nmi = vmx_inject_nmi,
7732         .queue_exception = vmx_queue_exception,
7733         .cancel_injection = vmx_cancel_injection,
7734         .interrupt_allowed = vmx_interrupt_allowed,
7735         .nmi_allowed = vmx_nmi_allowed,
7736         .get_nmi_mask = vmx_get_nmi_mask,
7737         .set_nmi_mask = vmx_set_nmi_mask,
7738         .enable_nmi_window = enable_nmi_window,
7739         .enable_irq_window = enable_irq_window,
7740         .update_cr8_intercept = update_cr8_intercept,
7741         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7742         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7743         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7744         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7745         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7746         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7747         .hwapic_irr_update = vmx_hwapic_irr_update,
7748         .hwapic_isr_update = vmx_hwapic_isr_update,
7749         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7750         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7751         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7752         .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7753
7754         .set_tss_addr = vmx_set_tss_addr,
7755         .set_identity_map_addr = vmx_set_identity_map_addr,
7756         .get_tdp_level = get_ept_level,
7757         .get_mt_mask = vmx_get_mt_mask,
7758
7759         .get_exit_info = vmx_get_exit_info,
7760
7761         .cpuid_update = vmx_cpuid_update,
7762
7763         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7764
7765         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7766         .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7767
7768         .load_mmu_pgd = vmx_load_mmu_pgd,
7769
7770         .check_intercept = vmx_check_intercept,
7771         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7772
7773         .request_immediate_exit = vmx_request_immediate_exit,
7774
7775         .sched_in = vmx_sched_in,
7776
7777         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7778         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7779         .flush_log_dirty = vmx_flush_log_dirty,
7780         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7781         .write_log_dirty = vmx_write_pml_buffer,
7782
7783         .pre_block = vmx_pre_block,
7784         .post_block = vmx_post_block,
7785
7786         .pmu_ops = &intel_pmu_ops,
7787
7788         .update_pi_irte = vmx_update_pi_irte,
7789
7790 #ifdef CONFIG_X86_64
7791         .set_hv_timer = vmx_set_hv_timer,
7792         .cancel_hv_timer = vmx_cancel_hv_timer,
7793 #endif
7794
7795         .setup_mce = vmx_setup_mce,
7796
7797         .smi_allowed = vmx_smi_allowed,
7798         .pre_enter_smm = vmx_pre_enter_smm,
7799         .pre_leave_smm = vmx_pre_leave_smm,
7800         .enable_smi_window = enable_smi_window,
7801
7802         .check_nested_events = NULL,
7803         .get_nested_state = NULL,
7804         .set_nested_state = NULL,
7805         .get_vmcs12_pages = NULL,
7806         .nested_enable_evmcs = NULL,
7807         .nested_get_evmcs_version = NULL,
7808         .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7809         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7810 };
7811
7812 static __init int hardware_setup(void)
7813 {
7814         unsigned long host_bndcfgs;
7815         struct desc_ptr dt;
7816         int r, i, ept_lpage_level;
7817
7818         store_idt(&dt);
7819         host_idt_base = dt.address;
7820
7821         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7822                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7823
7824         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7825                 return -EIO;
7826
7827         if (boot_cpu_has(X86_FEATURE_NX))
7828                 kvm_enable_efer_bits(EFER_NX);
7829
7830         if (boot_cpu_has(X86_FEATURE_MPX)) {
7831                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7832                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7833         }
7834
7835         if (!cpu_has_vmx_mpx())
7836                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7837                                     XFEATURE_MASK_BNDCSR);
7838
7839         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7840             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7841                 enable_vpid = 0;
7842
7843         if (!cpu_has_vmx_ept() ||
7844             !cpu_has_vmx_ept_4levels() ||
7845             !cpu_has_vmx_ept_mt_wb() ||
7846             !cpu_has_vmx_invept_global())
7847                 enable_ept = 0;
7848
7849         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7850                 enable_ept_ad_bits = 0;
7851
7852         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7853                 enable_unrestricted_guest = 0;
7854
7855         if (!cpu_has_vmx_flexpriority())
7856                 flexpriority_enabled = 0;
7857
7858         if (!cpu_has_virtual_nmis())
7859                 enable_vnmi = 0;
7860
7861         /*
7862          * set_apic_access_page_addr() is used to reload apic access
7863          * page upon invalidation.  No need to do anything if not
7864          * using the APIC_ACCESS_ADDR VMCS field.
7865          */
7866         if (!flexpriority_enabled)
7867                 vmx_x86_ops.set_apic_access_page_addr = NULL;
7868
7869         if (!cpu_has_vmx_tpr_shadow())
7870                 vmx_x86_ops.update_cr8_intercept = NULL;
7871
7872 #if IS_ENABLED(CONFIG_HYPERV)
7873         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7874             && enable_ept) {
7875                 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7876                 vmx_x86_ops.tlb_remote_flush_with_range =
7877                                 hv_remote_flush_tlb_with_range;
7878         }
7879 #endif
7880
7881         if (!cpu_has_vmx_ple()) {
7882                 ple_gap = 0;
7883                 ple_window = 0;
7884                 ple_window_grow = 0;
7885                 ple_window_max = 0;
7886                 ple_window_shrink = 0;
7887         }
7888
7889         if (!cpu_has_vmx_apicv()) {
7890                 enable_apicv = 0;
7891                 vmx_x86_ops.sync_pir_to_irr = NULL;
7892         }
7893
7894         if (cpu_has_vmx_tsc_scaling()) {
7895                 kvm_has_tsc_control = true;
7896                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7897                 kvm_tsc_scaling_ratio_frac_bits = 48;
7898         }
7899
7900         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7901
7902         if (enable_ept)
7903                 vmx_enable_tdp();
7904
7905         if (!enable_ept)
7906                 ept_lpage_level = 0;
7907         else if (cpu_has_vmx_ept_1g_page())
7908                 ept_lpage_level = PT_PDPE_LEVEL;
7909         else if (cpu_has_vmx_ept_2m_page())
7910                 ept_lpage_level = PT_DIRECTORY_LEVEL;
7911         else
7912                 ept_lpage_level = PT_PAGE_TABLE_LEVEL;
7913         kvm_configure_mmu(enable_ept, ept_lpage_level);
7914
7915         /*
7916          * Only enable PML when hardware supports PML feature, and both EPT
7917          * and EPT A/D bit features are enabled -- PML depends on them to work.
7918          */
7919         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7920                 enable_pml = 0;
7921
7922         if (!enable_pml) {
7923                 vmx_x86_ops.slot_enable_log_dirty = NULL;
7924                 vmx_x86_ops.slot_disable_log_dirty = NULL;
7925                 vmx_x86_ops.flush_log_dirty = NULL;
7926                 vmx_x86_ops.enable_log_dirty_pt_masked = NULL;
7927         }
7928
7929         if (!cpu_has_vmx_preemption_timer())
7930                 enable_preemption_timer = false;
7931
7932         if (enable_preemption_timer) {
7933                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7934                 u64 vmx_msr;
7935
7936                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7937                 cpu_preemption_timer_multi =
7938                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7939
7940                 if (tsc_khz)
7941                         use_timer_freq = (u64)tsc_khz * 1000;
7942                 use_timer_freq >>= cpu_preemption_timer_multi;
7943
7944                 /*
7945                  * KVM "disables" the preemption timer by setting it to its max
7946                  * value.  Don't use the timer if it might cause spurious exits
7947                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7948                  */
7949                 if (use_timer_freq > 0xffffffffu / 10)
7950                         enable_preemption_timer = false;
7951         }
7952
7953         if (!enable_preemption_timer) {
7954                 vmx_x86_ops.set_hv_timer = NULL;
7955                 vmx_x86_ops.cancel_hv_timer = NULL;
7956                 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
7957         }
7958
7959         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7960
7961         kvm_mce_cap_supported |= MCG_LMCE_P;
7962
7963         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7964                 return -EINVAL;
7965         if (!enable_ept || !cpu_has_vmx_intel_pt())
7966                 pt_mode = PT_MODE_SYSTEM;
7967
7968         if (nested) {
7969                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7970                                            vmx_capability.ept);
7971
7972                 r = nested_vmx_hardware_setup(&vmx_x86_ops,
7973                                               kvm_vmx_exit_handlers);
7974                 if (r)
7975                         return r;
7976         }
7977
7978         vmx_set_cpu_caps();
7979
7980         r = alloc_kvm_area();
7981         if (r)
7982                 nested_vmx_hardware_unsetup();
7983         return r;
7984 }
7985
7986 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
7987         .cpu_has_kvm_support = cpu_has_kvm_support,
7988         .disabled_by_bios = vmx_disabled_by_bios,
7989         .check_processor_compatibility = vmx_check_processor_compat,
7990         .hardware_setup = hardware_setup,
7991
7992         .runtime_ops = &vmx_x86_ops,
7993 };
7994
7995 static void vmx_cleanup_l1d_flush(void)
7996 {
7997         if (vmx_l1d_flush_pages) {
7998                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7999                 vmx_l1d_flush_pages = NULL;
8000         }
8001         /* Restore state so sysfs ignores VMX */
8002         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
8003 }
8004
8005 static void vmx_exit(void)
8006 {
8007 #ifdef CONFIG_KEXEC_CORE
8008         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8009         synchronize_rcu();
8010 #endif
8011
8012         kvm_exit();
8013
8014 #if IS_ENABLED(CONFIG_HYPERV)
8015         if (static_branch_unlikely(&enable_evmcs)) {
8016                 int cpu;
8017                 struct hv_vp_assist_page *vp_ap;
8018                 /*
8019                  * Reset everything to support using non-enlightened VMCS
8020                  * access later (e.g. when we reload the module with
8021                  * enlightened_vmcs=0)
8022                  */
8023                 for_each_online_cpu(cpu) {
8024                         vp_ap = hv_get_vp_assist_page(cpu);
8025
8026                         if (!vp_ap)
8027                                 continue;
8028
8029                         vp_ap->nested_control.features.directhypercall = 0;
8030                         vp_ap->current_nested_vmcs = 0;
8031                         vp_ap->enlighten_vmentry = 0;
8032                 }
8033
8034                 static_branch_disable(&enable_evmcs);
8035         }
8036 #endif
8037         vmx_cleanup_l1d_flush();
8038 }
8039 module_exit(vmx_exit);
8040
8041 static int __init vmx_init(void)
8042 {
8043         int r, cpu;
8044
8045 #if IS_ENABLED(CONFIG_HYPERV)
8046         /*
8047          * Enlightened VMCS usage should be recommended and the host needs
8048          * to support eVMCS v1 or above. We can also disable eVMCS support
8049          * with module parameter.
8050          */
8051         if (enlightened_vmcs &&
8052             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8053             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8054             KVM_EVMCS_VERSION) {
8055                 int cpu;
8056
8057                 /* Check that we have assist pages on all online CPUs */
8058                 for_each_online_cpu(cpu) {
8059                         if (!hv_get_vp_assist_page(cpu)) {
8060                                 enlightened_vmcs = false;
8061                                 break;
8062                         }
8063                 }
8064
8065                 if (enlightened_vmcs) {
8066                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8067                         static_branch_enable(&enable_evmcs);
8068                 }
8069
8070                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8071                         vmx_x86_ops.enable_direct_tlbflush
8072                                 = hv_enable_direct_tlbflush;
8073
8074         } else {
8075                 enlightened_vmcs = false;
8076         }
8077 #endif
8078
8079         r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
8080                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8081         if (r)
8082                 return r;
8083
8084         /*
8085          * Must be called after kvm_init() so enable_ept is properly set
8086          * up. Hand the parameter mitigation value in which was stored in
8087          * the pre module init parser. If no parameter was given, it will
8088          * contain 'auto' which will be turned into the default 'cond'
8089          * mitigation mode.
8090          */
8091         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8092         if (r) {
8093                 vmx_exit();
8094                 return r;
8095         }
8096
8097         for_each_possible_cpu(cpu) {
8098                 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8099                 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
8100                 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8101         }
8102
8103 #ifdef CONFIG_KEXEC_CORE
8104         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8105                            crash_vmclear_local_loaded_vmcss);
8106 #endif
8107         vmx_check_vmcs12_offsets();
8108
8109         return 0;
8110 }
8111 module_init(vmx_init);