arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/frame.h>
  17 #include <linux/highmem.h>
  18 #include <linux/hrtimer.h>
  19 #include <linux/kernel.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/mm.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30
  31 #include <asm/apic.h>
  32 #include <asm/asm.h>
  33 #include <asm/cpu.h>
  34 #include <asm/cpu_device_id.h>
  35 #include <asm/debugreg.h>
  36 #include <asm/desc.h>
  37 #include <asm/fpu/internal.h>
  38 #include <asm/io.h>
  39 #include <asm/irq_remapping.h>
  40 #include <asm/kexec.h>
  41 #include <asm/perf_event.h>
  42 #include <asm/mce.h>
  43 #include <asm/mmu_context.h>
  44 #include <asm/mshyperv.h>
  45 #include <asm/mwait.h>
  46 #include <asm/spec-ctrl.h>
  47 #include <asm/virtext.h>
  48 #include <asm/vmx.h>
  49
  50 #include "capabilities.h"
  51 #include "cpuid.h"
  52 #include "evmcs.h"
  53 #include "irq.h"
  54 #include "kvm_cache_regs.h"
  55 #include "lapic.h"
  56 #include "mmu.h"
  57 #include "nested.h"
  58 #include "ops.h"
  59 #include "pmu.h"
  60 #include "trace.h"
  61 #include "vmcs.h"
  62 #include "vmcs12.h"
  63 #include "vmx.h"
  64 #include "x86.h"
  65
  66 MODULE_AUTHOR("Qumranet");
  67 MODULE_LICENSE("GPL");
  68
  69 #ifdef MODULE
  70 static const struct x86_cpu_id vmx_cpu_id[] = {
  71         X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
  72         {}
  73 };
  74 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  75 #endif
  76
  77 bool __read_mostly enable_vpid = 1;
  78 module_param_named(vpid, enable_vpid, bool, 0444);
  79
  80 static bool __read_mostly enable_vnmi = 1;
  81 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  82
  83 bool __read_mostly flexpriority_enabled = 1;
  84 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  85
  86 bool __read_mostly enable_ept = 1;
  87 module_param_named(ept, enable_ept, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_unrestricted_guest = 1;
  90 module_param_named(unrestricted_guest,
  91                         enable_unrestricted_guest, bool, S_IRUGO);
  92
  93 bool __read_mostly enable_ept_ad_bits = 1;
  94 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  95
  96 static bool __read_mostly emulate_invalid_guest_state = true;
  97 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  98
  99 static bool __read_mostly fasteoi = 1;
 100 module_param(fasteoi, bool, S_IRUGO);
 101
 102 bool __read_mostly enable_apicv = 1;
 103 module_param(enable_apicv, bool, S_IRUGO);
 104
 105 /*
 106  * If nested=1, nested virtualization is supported, i.e., guests may use
 107  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 108  * use VMX instructions.
 109  */
 110 static bool __read_mostly nested = 1;
 111 module_param(nested, bool, S_IRUGO);
 112
 113 bool __read_mostly enable_pml = 1;
 114 module_param_named(pml, enable_pml, bool, S_IRUGO);
 115
 116 static bool __read_mostly dump_invalid_vmcs = 0;
 117 module_param(dump_invalid_vmcs, bool, 0644);
 118
 119 #define MSR_BITMAP_MODE_X2APIC          1
 120 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 121
 122 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 123
 124 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 125 static int __read_mostly cpu_preemption_timer_multi;
 126 static bool __read_mostly enable_preemption_timer = 1;
 127 #ifdef CONFIG_X86_64
 128 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 129 #endif
 130
 131 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 132 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 133 #define KVM_VM_CR0_ALWAYS_ON                            \
 134         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 135          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 136 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 137         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 138          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 139
 140 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 141 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 142 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 143
 144 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 145
 146 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 147         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 148         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 149         RTIT_STATUS_BYTECNT))
 150
 151 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
 152         (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
 153
 154 /*
 155  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 156  * ple_gap:    upper bound on the amount of time between two successive
 157  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 158  *             According to test, this time is usually smaller than 128 cycles.
 159  * ple_window: upper bound on the amount of time a guest is allowed to execute
 160  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 161  *             less than 2^12 cycles
 162  * Time is measured based on a counter that runs at the same rate as the TSC,
 163  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 164  */
 165 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 166 module_param(ple_gap, uint, 0444);
 167
 168 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 169 module_param(ple_window, uint, 0444);
 170
 171 /* Default doubles per-vcpu window every exit. */
 172 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 173 module_param(ple_window_grow, uint, 0444);
 174
 175 /* Default resets per-vcpu window every exit to ple_window. */
 176 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 177 module_param(ple_window_shrink, uint, 0444);
 178
 179 /* Default is to compute the maximum so we can never overflow. */
 180 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 181 module_param(ple_window_max, uint, 0444);
 182
 183 /* Default is SYSTEM mode, 1 for host-guest mode */
 184 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 185 module_param(pt_mode, int, S_IRUGO);
 186
 187 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 188 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 189 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 190
 191 /* Storage for pre module init parameter parsing */
 192 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 193
 194 static const struct {
 195         const char *option;
 196         bool for_parse;
 197 } vmentry_l1d_param[] = {
 198         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 199         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 200         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 201         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 202         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 203         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 204 };
 205
 206 #define L1D_CACHE_ORDER 4
 207 static void *vmx_l1d_flush_pages;
 208
 209 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 210 {
 211         struct page *page;
 212         unsigned int i;
 213
 214         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 215                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 216                 return 0;
 217         }
 218
 219         if (!enable_ept) {
 220                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 221                 return 0;
 222         }
 223
 224         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 225                 u64 msr;
 226
 227                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 228                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 229                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 230                         return 0;
 231                 }
 232         }
 233
 234         /* If set to auto use the default l1tf mitigation method */
 235         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 236                 switch (l1tf_mitigation) {
 237                 case L1TF_MITIGATION_OFF:
 238                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 239                         break;
 240                 case L1TF_MITIGATION_FLUSH_NOWARN:
 241                 case L1TF_MITIGATION_FLUSH:
 242                 case L1TF_MITIGATION_FLUSH_NOSMT:
 243                         l1tf = VMENTER_L1D_FLUSH_COND;
 244                         break;
 245                 case L1TF_MITIGATION_FULL:
 246                 case L1TF_MITIGATION_FULL_FORCE:
 247                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 248                         break;
 249                 }
 250         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 251                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 252         }
 253
 254         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 255             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 256                 /*
 257                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 258                  * lifetime and so should not be charged to a memcg.
 259                  */
 260                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 261                 if (!page)
 262                         return -ENOMEM;
 263                 vmx_l1d_flush_pages = page_address(page);
 264
 265                 /*
 266                  * Initialize each page with a different pattern in
 267                  * order to protect against KSM in the nested
 268                  * virtualization case.
 269                  */
 270                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 271                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 272                                PAGE_SIZE);
 273                 }
 274         }
 275
 276         l1tf_vmx_mitigation = l1tf;
 277
 278         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 279                 static_branch_enable(&vmx_l1d_should_flush);
 280         else
 281                 static_branch_disable(&vmx_l1d_should_flush);
 282
 283         if (l1tf == VMENTER_L1D_FLUSH_COND)
 284                 static_branch_enable(&vmx_l1d_flush_cond);
 285         else
 286                 static_branch_disable(&vmx_l1d_flush_cond);
 287         return 0;
 288 }
 289
 290 static int vmentry_l1d_flush_parse(const char *s)
 291 {
 292         unsigned int i;
 293
 294         if (s) {
 295                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 296                         if (vmentry_l1d_param[i].for_parse &&
 297                             sysfs_streq(s, vmentry_l1d_param[i].option))
 298                                 return i;
 299                 }
 300         }
 301         return -EINVAL;
 302 }
 303
 304 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 305 {
 306         int l1tf, ret;
 307
 308         l1tf = vmentry_l1d_flush_parse(s);
 309         if (l1tf < 0)
 310                 return l1tf;
 311
 312         if (!boot_cpu_has(X86_BUG_L1TF))
 313                 return 0;
 314
 315         /*
 316          * Has vmx_init() run already? If not then this is the pre init
 317          * parameter parsing. In that case just store the value and let
 318          * vmx_init() do the proper setup after enable_ept has been
 319          * established.
 320          */
 321         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 322                 vmentry_l1d_flush_param = l1tf;
 323                 return 0;
 324         }
 325
 326         mutex_lock(&vmx_l1d_flush_mutex);
 327         ret = vmx_setup_l1d_flush(l1tf);
 328         mutex_unlock(&vmx_l1d_flush_mutex);
 329         return ret;
 330 }
 331
 332 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 333 {
 334         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 335                 return sprintf(s, "???\n");
 336
 337         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 338 }
 339
 340 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 341         .set = vmentry_l1d_flush_set,
 342         .get = vmentry_l1d_flush_get,
 343 };
 344 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 345
 346 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 347 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 348 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 349                                                           u32 msr, int type);
 350
 351 void vmx_vmexit(void);
 352
 353 #define vmx_insn_failed(fmt...)         \
 354 do {                                    \
 355         WARN_ONCE(1, fmt);              \
 356         pr_warn_ratelimited(fmt);       \
 357 } while (0)
 358
 359 asmlinkage void vmread_error(unsigned long field, bool fault)
 360 {
 361         if (fault)
 362                 kvm_spurious_fault();
 363         else
 364                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 365 }
 366
 367 noinline void vmwrite_error(unsigned long field, unsigned long value)
 368 {
 369         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 370                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 371 }
 372
 373 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 374 {
 375         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 376 }
 377
 378 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 379 {
 380         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 381 }
 382
 383 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 384 {
 385         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 386                         ext, vpid, gva);
 387 }
 388
 389 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 390 {
 391         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 392                         ext, eptp, gpa);
 393 }
 394
 395 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 396 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 397 /*
 398  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 399  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 400  */
 401 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 402
 403 /*
 404  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 405  * can find which vCPU should be waken up.
 406  */
 407 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 408 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 409
 410 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 411 static DEFINE_SPINLOCK(vmx_vpid_lock);
 412
 413 struct vmcs_config vmcs_config;
 414 struct vmx_capability vmx_capability;
 415
 416 #define VMX_SEGMENT_FIELD(seg)                                  \
 417         [VCPU_SREG_##seg] = {                                   \
 418                 .selector = GUEST_##seg##_SELECTOR,             \
 419                 .base = GUEST_##seg##_BASE,                     \
 420                 .limit = GUEST_##seg##_LIMIT,                   \
 421                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 422         }
 423
 424 static const struct kvm_vmx_segment_field {
 425         unsigned selector;
 426         unsigned base;
 427         unsigned limit;
 428         unsigned ar_bytes;
 429 } kvm_vmx_segment_fields[] = {
 430         VMX_SEGMENT_FIELD(CS),
 431         VMX_SEGMENT_FIELD(DS),
 432         VMX_SEGMENT_FIELD(ES),
 433         VMX_SEGMENT_FIELD(FS),
 434         VMX_SEGMENT_FIELD(GS),
 435         VMX_SEGMENT_FIELD(SS),
 436         VMX_SEGMENT_FIELD(TR),
 437         VMX_SEGMENT_FIELD(LDTR),
 438 };
 439
 440 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
 441 {
 442         vmx->segment_cache.bitmask = 0;
 443 }
 444
 445 static unsigned long host_idt_base;
 446
 447 /*
 448  * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
 449  * will emulate SYSCALL in legacy mode if the vendor string in guest
 450  * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
 451  * support this emulation, IA32_STAR must always be included in
 452  * vmx_msr_index[], even in i386 builds.
 453  */
 454 const u32 vmx_msr_index[] = {
 455 #ifdef CONFIG_X86_64
 456         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 457 #endif
 458         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 459         MSR_IA32_TSX_CTRL,
 460 };
 461
 462 #if IS_ENABLED(CONFIG_HYPERV)
 463 static bool __read_mostly enlightened_vmcs = true;
 464 module_param(enlightened_vmcs, bool, 0444);
 465
 466 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
 467 static void check_ept_pointer_match(struct kvm *kvm)
 468 {
 469         struct kvm_vcpu *vcpu;
 470         u64 tmp_eptp = INVALID_PAGE;
 471         int i;
 472
 473         kvm_for_each_vcpu(i, vcpu, kvm) {
 474                 if (!VALID_PAGE(tmp_eptp)) {
 475                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
 476                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
 477                         to_kvm_vmx(kvm)->ept_pointers_match
 478                                 = EPT_POINTERS_MISMATCH;
 479                         return;
 480                 }
 481         }
 482
 483         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
 484 }
 485
 486 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
 487                 void *data)
 488 {
 489         struct kvm_tlb_range *range = data;
 490
 491         return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
 492                         range->pages);
 493 }
 494
 495 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
 496                 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
 497 {
 498         u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
 499
 500         /*
 501          * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
 502          * of the base of EPT PML4 table, strip off EPT configuration
 503          * information.
 504          */
 505         if (range)
 506                 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
 507                                 kvm_fill_hv_flush_list_func, (void *)range);
 508         else
 509                 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
 510 }
 511
 512 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
 513                 struct kvm_tlb_range *range)
 514 {
 515         struct kvm_vcpu *vcpu;
 516         int ret = 0, i;
 517
 518         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 519
 520         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
 521                 check_ept_pointer_match(kvm);
 522
 523         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
 524                 kvm_for_each_vcpu(i, vcpu, kvm) {
 525                         /* If ept_pointer is invalid pointer, bypass flush request. */
 526                         if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
 527                                 ret |= __hv_remote_flush_tlb_with_range(
 528                                         kvm, vcpu, range);
 529                 }
 530         } else {
 531                 ret = __hv_remote_flush_tlb_with_range(kvm,
 532                                 kvm_get_vcpu(kvm, 0), range);
 533         }
 534
 535         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 536         return ret;
 537 }
 538 static int hv_remote_flush_tlb(struct kvm *kvm)
 539 {
 540         return hv_remote_flush_tlb_with_range(kvm, NULL);
 541 }
 542
 543 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 544 {
 545         struct hv_enlightened_vmcs *evmcs;
 546         struct hv_partition_assist_pg **p_hv_pa_pg =
 547                         &vcpu->kvm->arch.hyperv.hv_pa_pg;
 548         /*
 549          * Synthetic VM-Exit is not enabled in current code and so All
 550          * evmcs in singe VM shares same assist page.
 551          */
 552         if (!*p_hv_pa_pg)
 553                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
 554
 555         if (!*p_hv_pa_pg)
 556                 return -ENOMEM;
 557
 558         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 559
 560         evmcs->partition_assist_page =
 561                 __pa(*p_hv_pa_pg);
 562         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 563         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 564
 565         return 0;
 566 }
 567
 568 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 569
 570 /*
 571  * Comment's format: document - errata name - stepping - processor name.
 572  * Refer from
 573  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 574  */
 575 static u32 vmx_preemption_cpu_tfms[] = {
 576 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 577 0x000206E6,
 578 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 579 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 580 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 581 0x00020652,
 582 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 583 0x00020655,
 584 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 585 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 586 /*
 587  * 320767.pdf - AAP86  - B1 -
 588  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 589  */
 590 0x000106E5,
 591 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 592 0x000106A0,
 593 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 594 0x000106A1,
 595 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 596 0x000106A4,
 597  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 598  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 599  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 600 0x000106A5,
 601  /* Xeon E3-1220 V2 */
 602 0x000306A8,
 603 };
 604
 605 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 606 {
 607         u32 eax = cpuid_eax(0x00000001), i;
 608
 609         /* Clear the reserved bits */
 610         eax &= ~(0x3U << 14 | 0xfU << 28);
 611         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 612                 if (eax == vmx_preemption_cpu_tfms[i])
 613                         return true;
 614
 615         return false;
 616 }
 617
 618 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 619 {
 620         return flexpriority_enabled && lapic_in_kernel(vcpu);
 621 }
 622
 623 static inline bool report_flexpriority(void)
 624 {
 625         return flexpriority_enabled;
 626 }
 627
 628 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 629 {
 630         int i;
 631
 632         for (i = 0; i < vmx->nmsrs; ++i)
 633                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 634                         return i;
 635         return -1;
 636 }
 637
 638 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 639 {
 640         int i;
 641
 642         i = __find_msr_index(vmx, msr);
 643         if (i >= 0)
 644                 return &vmx->guest_msrs[i];
 645         return NULL;
 646 }
 647
 648 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
 649 {
 650         int ret = 0;
 651
 652         u64 old_msr_data = msr->data;
 653         msr->data = data;
 654         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
 655                 preempt_disable();
 656                 ret = kvm_set_shared_msr(msr->index, msr->data,
 657                                          msr->mask);
 658                 preempt_enable();
 659                 if (ret)
 660                         msr->data = old_msr_data;
 661         }
 662         return ret;
 663 }
 664
 665 #ifdef CONFIG_KEXEC_CORE
 666 static void crash_vmclear_local_loaded_vmcss(void)
 667 {
 668         int cpu = raw_smp_processor_id();
 669         struct loaded_vmcs *v;
 670
 671         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 672                             loaded_vmcss_on_cpu_link)
 673                 vmcs_clear(v->vmcs);
 674 }
 675 #endif /* CONFIG_KEXEC_CORE */
 676
 677 static void __loaded_vmcs_clear(void *arg)
 678 {
 679         struct loaded_vmcs *loaded_vmcs = arg;
 680         int cpu = raw_smp_processor_id();
 681
 682         if (loaded_vmcs->cpu != cpu)
 683                 return; /* vcpu migration can race with cpu offline */
 684         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 685                 per_cpu(current_vmcs, cpu) = NULL;
 686
 687         vmcs_clear(loaded_vmcs->vmcs);
 688         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 689                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 690
 691         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 692
 693         /*
 694          * Ensure all writes to loaded_vmcs, including deleting it from its
 695          * current percpu list, complete before setting loaded_vmcs->vcpu to
 696          * -1, otherwise a different cpu can see vcpu == -1 first and add
 697          * loaded_vmcs to its percpu list before it's deleted from this cpu's
 698          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
 699          */
 700         smp_wmb();
 701
 702         loaded_vmcs->cpu = -1;
 703         loaded_vmcs->launched = 0;
 704 }
 705
 706 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 707 {
 708         int cpu = loaded_vmcs->cpu;
 709
 710         if (cpu != -1)
 711                 smp_call_function_single(cpu,
 712                          __loaded_vmcs_clear, loaded_vmcs, 1);
 713 }
 714
 715 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 716                                        unsigned field)
 717 {
 718         bool ret;
 719         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 720
 721         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
 722                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
 723                 vmx->segment_cache.bitmask = 0;
 724         }
 725         ret = vmx->segment_cache.bitmask & mask;
 726         vmx->segment_cache.bitmask |= mask;
 727         return ret;
 728 }
 729
 730 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 731 {
 732         u16 *p = &vmx->segment_cache.seg[seg].selector;
 733
 734         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 735                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 736         return *p;
 737 }
 738
 739 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 740 {
 741         ulong *p = &vmx->segment_cache.seg[seg].base;
 742
 743         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 744                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 745         return *p;
 746 }
 747
 748 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 749 {
 750         u32 *p = &vmx->segment_cache.seg[seg].limit;
 751
 752         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 753                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 754         return *p;
 755 }
 756
 757 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 758 {
 759         u32 *p = &vmx->segment_cache.seg[seg].ar;
 760
 761         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 762                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 763         return *p;
 764 }
 765
 766 void update_exception_bitmap(struct kvm_vcpu *vcpu)
 767 {
 768         u32 eb;
 769
 770         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 771              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 772         /*
 773          * Guest access to VMware backdoor ports could legitimately
 774          * trigger #GP because of TSS I/O permission bitmap.
 775          * We intercept those #GP and allow access to them anyway
 776          * as VMware does.
 777          */
 778         if (enable_vmware_backdoor)
 779                 eb |= (1u << GP_VECTOR);
 780         if ((vcpu->guest_debug &
 781              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 782             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 783                 eb |= 1u << BP_VECTOR;
 784         if (to_vmx(vcpu)->rmode.vm86_active)
 785                 eb = ~0;
 786         if (enable_ept)
 787                 eb &= ~(1u << PF_VECTOR);
 788
 789         /* When we are running a nested L2 guest and L1 specified for it a
 790          * certain exception bitmap, we must trap the same exceptions and pass
 791          * them to L1. When running L2, we will only handle the exceptions
 792          * specified above if L1 did not want them.
 793          */
 794         if (is_guest_mode(vcpu))
 795                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 796
 797         vmcs_write32(EXCEPTION_BITMAP, eb);
 798 }
 799
 800 /*
 801  * Check if MSR is intercepted for currently loaded MSR bitmap.
 802  */
 803 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 804 {
 805         unsigned long *msr_bitmap;
 806         int f = sizeof(unsigned long);
 807
 808         if (!cpu_has_vmx_msr_bitmap())
 809                 return true;
 810
 811         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 812
 813         if (msr <= 0x1fff) {
 814                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 815         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 816                 msr &= 0x1fff;
 817                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 818         }
 819
 820         return true;
 821 }
 822
 823 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 824                 unsigned long entry, unsigned long exit)
 825 {
 826         vm_entry_controls_clearbit(vmx, entry);
 827         vm_exit_controls_clearbit(vmx, exit);
 828 }
 829
 830 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
 831 {
 832         unsigned int i;
 833
 834         for (i = 0; i < m->nr; ++i) {
 835                 if (m->val[i].index == msr)
 836                         return i;
 837         }
 838         return -ENOENT;
 839 }
 840
 841 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 842 {
 843         int i;
 844         struct msr_autoload *m = &vmx->msr_autoload;
 845
 846         switch (msr) {
 847         case MSR_EFER:
 848                 if (cpu_has_load_ia32_efer()) {
 849                         clear_atomic_switch_msr_special(vmx,
 850                                         VM_ENTRY_LOAD_IA32_EFER,
 851                                         VM_EXIT_LOAD_IA32_EFER);
 852                         return;
 853                 }
 854                 break;
 855         case MSR_CORE_PERF_GLOBAL_CTRL:
 856                 if (cpu_has_load_perf_global_ctrl()) {
 857                         clear_atomic_switch_msr_special(vmx,
 858                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 859                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 860                         return;
 861                 }
 862                 break;
 863         }
 864         i = vmx_find_msr_index(&m->guest, msr);
 865         if (i < 0)
 866                 goto skip_guest;
 867         --m->guest.nr;
 868         m->guest.val[i] = m->guest.val[m->guest.nr];
 869         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 870
 871 skip_guest:
 872         i = vmx_find_msr_index(&m->host, msr);
 873         if (i < 0)
 874                 return;
 875
 876         --m->host.nr;
 877         m->host.val[i] = m->host.val[m->host.nr];
 878         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 879 }
 880
 881 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 882                 unsigned long entry, unsigned long exit,
 883                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 884                 u64 guest_val, u64 host_val)
 885 {
 886         vmcs_write64(guest_val_vmcs, guest_val);
 887         if (host_val_vmcs != HOST_IA32_EFER)
 888                 vmcs_write64(host_val_vmcs, host_val);
 889         vm_entry_controls_setbit(vmx, entry);
 890         vm_exit_controls_setbit(vmx, exit);
 891 }
 892
 893 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 894                                   u64 guest_val, u64 host_val, bool entry_only)
 895 {
 896         int i, j = 0;
 897         struct msr_autoload *m = &vmx->msr_autoload;
 898
 899         switch (msr) {
 900         case MSR_EFER:
 901                 if (cpu_has_load_ia32_efer()) {
 902                         add_atomic_switch_msr_special(vmx,
 903                                         VM_ENTRY_LOAD_IA32_EFER,
 904                                         VM_EXIT_LOAD_IA32_EFER,
 905                                         GUEST_IA32_EFER,
 906                                         HOST_IA32_EFER,
 907                                         guest_val, host_val);
 908                         return;
 909                 }
 910                 break;
 911         case MSR_CORE_PERF_GLOBAL_CTRL:
 912                 if (cpu_has_load_perf_global_ctrl()) {
 913                         add_atomic_switch_msr_special(vmx,
 914                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 915                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 916                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 917                                         HOST_IA32_PERF_GLOBAL_CTRL,
 918                                         guest_val, host_val);
 919                         return;
 920                 }
 921                 break;
 922         case MSR_IA32_PEBS_ENABLE:
 923                 /* PEBS needs a quiescent period after being disabled (to write
 924                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 925                  * provide that period, so a CPU could write host's record into
 926                  * guest's memory.
 927                  */
 928                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 929         }
 930
 931         i = vmx_find_msr_index(&m->guest, msr);
 932         if (!entry_only)
 933                 j = vmx_find_msr_index(&m->host, msr);
 934
 935         if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
 936                 (j < 0 &&  m->host.nr == NR_LOADSTORE_MSRS)) {
 937                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 938                                 "Can't add msr %x\n", msr);
 939                 return;
 940         }
 941         if (i < 0) {
 942                 i = m->guest.nr++;
 943                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 944         }
 945         m->guest.val[i].index = msr;
 946         m->guest.val[i].value = guest_val;
 947
 948         if (entry_only)
 949                 return;
 950
 951         if (j < 0) {
 952                 j = m->host.nr++;
 953                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 954         }
 955         m->host.val[j].index = msr;
 956         m->host.val[j].value = host_val;
 957 }
 958
 959 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 960 {
 961         u64 guest_efer = vmx->vcpu.arch.efer;
 962         u64 ignore_bits = 0;
 963
 964         /* Shadow paging assumes NX to be available.  */
 965         if (!enable_ept)
 966                 guest_efer |= EFER_NX;
 967
 968         /*
 969          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 970          */
 971         ignore_bits |= EFER_SCE;
 972 #ifdef CONFIG_X86_64
 973         ignore_bits |= EFER_LMA | EFER_LME;
 974         /* SCE is meaningful only in long mode on Intel */
 975         if (guest_efer & EFER_LMA)
 976                 ignore_bits &= ~(u64)EFER_SCE;
 977 #endif
 978
 979         /*
 980          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 981          * On CPUs that support "load IA32_EFER", always switch EFER
 982          * atomically, since it's faster than switching it manually.
 983          */
 984         if (cpu_has_load_ia32_efer() ||
 985             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 986                 if (!(guest_efer & EFER_LMA))
 987                         guest_efer &= ~EFER_LME;
 988                 if (guest_efer != host_efer)
 989                         add_atomic_switch_msr(vmx, MSR_EFER,
 990                                               guest_efer, host_efer, false);
 991                 else
 992                         clear_atomic_switch_msr(vmx, MSR_EFER);
 993                 return false;
 994         } else {
 995                 clear_atomic_switch_msr(vmx, MSR_EFER);
 996
 997                 guest_efer &= ~ignore_bits;
 998                 guest_efer |= host_efer & ignore_bits;
 999
1000                 vmx->guest_msrs[efer_offset].data = guest_efer;
1001                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1002
1003                 return true;
1004         }
1005 }
1006
1007 #ifdef CONFIG_X86_32
1008 /*
1009  * On 32-bit kernels, VM exits still load the FS and GS bases from the
1010  * VMCS rather than the segment table.  KVM uses this helper to figure
1011  * out the current bases to poke them into the VMCS before entry.
1012  */
1013 static unsigned long segment_base(u16 selector)
1014 {
1015         struct desc_struct *table;
1016         unsigned long v;
1017
1018         if (!(selector & ~SEGMENT_RPL_MASK))
1019                 return 0;
1020
1021         table = get_current_gdt_ro();
1022
1023         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1024                 u16 ldt_selector = kvm_read_ldt();
1025
1026                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1027                         return 0;
1028
1029                 table = (struct desc_struct *)segment_base(ldt_selector);
1030         }
1031         v = get_desc_base(&table[selector >> 3]);
1032         return v;
1033 }
1034 #endif
1035
1036 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1037 {
1038         return vmx_pt_mode_is_host_guest() &&
1039                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1040 }
1041
1042 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1043 {
1044         u32 i;
1045
1046         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1047         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1048         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1049         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1050         for (i = 0; i < addr_range; i++) {
1051                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1052                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1053         }
1054 }
1055
1056 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1057 {
1058         u32 i;
1059
1060         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1061         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1062         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1063         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1064         for (i = 0; i < addr_range; i++) {
1065                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1066                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1067         }
1068 }
1069
1070 static void pt_guest_enter(struct vcpu_vmx *vmx)
1071 {
1072         if (vmx_pt_mode_is_system())
1073                 return;
1074
1075         /*
1076          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1077          * Save host state before VM entry.
1078          */
1079         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1080         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1081                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1082                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1083                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1084         }
1085 }
1086
1087 static void pt_guest_exit(struct vcpu_vmx *vmx)
1088 {
1089         if (vmx_pt_mode_is_system())
1090                 return;
1091
1092         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1093                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1094                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1095         }
1096
1097         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1098         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1099 }
1100
1101 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1102                         unsigned long fs_base, unsigned long gs_base)
1103 {
1104         if (unlikely(fs_sel != host->fs_sel)) {
1105                 if (!(fs_sel & 7))
1106                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1107                 else
1108                         vmcs_write16(HOST_FS_SELECTOR, 0);
1109                 host->fs_sel = fs_sel;
1110         }
1111         if (unlikely(gs_sel != host->gs_sel)) {
1112                 if (!(gs_sel & 7))
1113                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1114                 else
1115                         vmcs_write16(HOST_GS_SELECTOR, 0);
1116                 host->gs_sel = gs_sel;
1117         }
1118         if (unlikely(fs_base != host->fs_base)) {
1119                 vmcs_writel(HOST_FS_BASE, fs_base);
1120                 host->fs_base = fs_base;
1121         }
1122         if (unlikely(gs_base != host->gs_base)) {
1123                 vmcs_writel(HOST_GS_BASE, gs_base);
1124                 host->gs_base = gs_base;
1125         }
1126 }
1127
1128 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1129 {
1130         struct vcpu_vmx *vmx = to_vmx(vcpu);
1131         struct vmcs_host_state *host_state;
1132 #ifdef CONFIG_X86_64
1133         int cpu = raw_smp_processor_id();
1134 #endif
1135         unsigned long fs_base, gs_base;
1136         u16 fs_sel, gs_sel;
1137         int i;
1138
1139         vmx->req_immediate_exit = false;
1140
1141         /*
1142          * Note that guest MSRs to be saved/restored can also be changed
1143          * when guest state is loaded. This happens when guest transitions
1144          * to/from long-mode by setting MSR_EFER.LMA.
1145          */
1146         if (!vmx->guest_msrs_ready) {
1147                 vmx->guest_msrs_ready = true;
1148                 for (i = 0; i < vmx->save_nmsrs; ++i)
1149                         kvm_set_shared_msr(vmx->guest_msrs[i].index,
1150                                            vmx->guest_msrs[i].data,
1151                                            vmx->guest_msrs[i].mask);
1152
1153         }
1154
1155         if (vmx->nested.need_vmcs12_to_shadow_sync)
1156                 nested_sync_vmcs12_to_shadow(vcpu);
1157
1158         if (vmx->guest_state_loaded)
1159                 return;
1160
1161         host_state = &vmx->loaded_vmcs->host_state;
1162
1163         /*
1164          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1165          * allow segment selectors with cpl > 0 or ti == 1.
1166          */
1167         host_state->ldt_sel = kvm_read_ldt();
1168
1169 #ifdef CONFIG_X86_64
1170         savesegment(ds, host_state->ds_sel);
1171         savesegment(es, host_state->es_sel);
1172
1173         gs_base = cpu_kernelmode_gs_base(cpu);
1174         if (likely(is_64bit_mm(current->mm))) {
1175                 save_fsgs_for_kvm();
1176                 fs_sel = current->thread.fsindex;
1177                 gs_sel = current->thread.gsindex;
1178                 fs_base = current->thread.fsbase;
1179                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1180         } else {
1181                 savesegment(fs, fs_sel);
1182                 savesegment(gs, gs_sel);
1183                 fs_base = read_msr(MSR_FS_BASE);
1184                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1185         }
1186
1187         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1188 #else
1189         savesegment(fs, fs_sel);
1190         savesegment(gs, gs_sel);
1191         fs_base = segment_base(fs_sel);
1192         gs_base = segment_base(gs_sel);
1193 #endif
1194
1195         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1196         vmx->guest_state_loaded = true;
1197 }
1198
1199 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1200 {
1201         struct vmcs_host_state *host_state;
1202
1203         if (!vmx->guest_state_loaded)
1204                 return;
1205
1206         host_state = &vmx->loaded_vmcs->host_state;
1207
1208         ++vmx->vcpu.stat.host_state_reload;
1209
1210 #ifdef CONFIG_X86_64
1211         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1212 #endif
1213         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1214                 kvm_load_ldt(host_state->ldt_sel);
1215 #ifdef CONFIG_X86_64
1216                 load_gs_index(host_state->gs_sel);
1217 #else
1218                 loadsegment(gs, host_state->gs_sel);
1219 #endif
1220         }
1221         if (host_state->fs_sel & 7)
1222                 loadsegment(fs, host_state->fs_sel);
1223 #ifdef CONFIG_X86_64
1224         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1225                 loadsegment(ds, host_state->ds_sel);
1226                 loadsegment(es, host_state->es_sel);
1227         }
1228 #endif
1229         invalidate_tss_limit();
1230 #ifdef CONFIG_X86_64
1231         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1232 #endif
1233         load_fixmap_gdt(raw_smp_processor_id());
1234         vmx->guest_state_loaded = false;
1235         vmx->guest_msrs_ready = false;
1236 }
1237
1238 #ifdef CONFIG_X86_64
1239 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1240 {
1241         preempt_disable();
1242         if (vmx->guest_state_loaded)
1243                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1244         preempt_enable();
1245         return vmx->msr_guest_kernel_gs_base;
1246 }
1247
1248 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1249 {
1250         preempt_disable();
1251         if (vmx->guest_state_loaded)
1252                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1253         preempt_enable();
1254         vmx->msr_guest_kernel_gs_base = data;
1255 }
1256 #endif
1257
1258 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1259 {
1260         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1261         struct pi_desc old, new;
1262         unsigned int dest;
1263
1264         /*
1265          * In case of hot-plug or hot-unplug, we may have to undo
1266          * vmx_vcpu_pi_put even if there is no assigned device.  And we
1267          * always keep PI.NDST up to date for simplicity: it makes the
1268          * code easier, and CPU migration is not a fast path.
1269          */
1270         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1271                 return;
1272
1273         /*
1274          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1275          * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1276          * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1277          * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1278          * correctly.
1279          */
1280         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1281                 pi_clear_sn(pi_desc);
1282                 goto after_clear_sn;
1283         }
1284
1285         /* The full case.  */
1286         do {
1287                 old.control = new.control = pi_desc->control;
1288
1289                 dest = cpu_physical_id(cpu);
1290
1291                 if (x2apic_enabled())
1292                         new.ndst = dest;
1293                 else
1294                         new.ndst = (dest << 8) & 0xFF00;
1295
1296                 new.sn = 0;
1297         } while (cmpxchg64(&pi_desc->control, old.control,
1298                            new.control) != old.control);
1299
1300 after_clear_sn:
1301
1302         /*
1303          * Clear SN before reading the bitmap.  The VT-d firmware
1304          * writes the bitmap and reads SN atomically (5.2.3 in the
1305          * spec), so it doesn't really have a memory barrier that
1306          * pairs with this, but we cannot do that and we need one.
1307          */
1308         smp_mb__after_atomic();
1309
1310         if (!pi_is_pir_empty(pi_desc))
1311                 pi_set_on(pi_desc);
1312 }
1313
1314 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1315 {
1316         struct vcpu_vmx *vmx = to_vmx(vcpu);
1317         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1318
1319         if (!already_loaded) {
1320                 loaded_vmcs_clear(vmx->loaded_vmcs);
1321                 local_irq_disable();
1322
1323                 /*
1324                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1325                  * this cpu's percpu list, otherwise it may not yet be deleted
1326                  * from its previous cpu's percpu list.  Pairs with the
1327                  * smb_wmb() in __loaded_vmcs_clear().
1328                  */
1329                 smp_rmb();
1330
1331                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1332                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1333                 local_irq_enable();
1334         }
1335
1336         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1337                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1338                 vmcs_load(vmx->loaded_vmcs->vmcs);
1339                 indirect_branch_prediction_barrier();
1340         }
1341
1342         if (!already_loaded) {
1343                 void *gdt = get_current_gdt_ro();
1344                 unsigned long sysenter_esp;
1345
1346                 /*
1347                  * Flush all EPTP/VPID contexts, the new pCPU may have stale
1348                  * TLB entries from its previous association with the vCPU.
1349                  */
1350                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1351
1352                 /*
1353                  * Linux uses per-cpu TSS and GDT, so set these when switching
1354                  * processors.  See 22.2.4.
1355                  */
1356                 vmcs_writel(HOST_TR_BASE,
1357                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1358                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1359
1360                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1361                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1362
1363                 vmx->loaded_vmcs->cpu = cpu;
1364         }
1365
1366         /* Setup TSC multiplier */
1367         if (kvm_has_tsc_control &&
1368             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1369                 decache_tsc_multiplier(vmx);
1370 }
1371
1372 /*
1373  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1374  * vcpu mutex is already taken.
1375  */
1376 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1377 {
1378         struct vcpu_vmx *vmx = to_vmx(vcpu);
1379
1380         vmx_vcpu_load_vmcs(vcpu, cpu);
1381
1382         vmx_vcpu_pi_load(vcpu, cpu);
1383
1384         vmx->host_pkru = read_pkru();
1385         vmx->host_debugctlmsr = get_debugctlmsr();
1386 }
1387
1388 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1389 {
1390         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1391
1392         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1393                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
1394                 !kvm_vcpu_apicv_active(vcpu))
1395                 return;
1396
1397         /* Set SN when the vCPU is preempted */
1398         if (vcpu->preempted)
1399                 pi_set_sn(pi_desc);
1400 }
1401
1402 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1403 {
1404         vmx_vcpu_pi_put(vcpu);
1405
1406         vmx_prepare_switch_to_host(to_vmx(vcpu));
1407 }
1408
1409 static bool emulation_required(struct kvm_vcpu *vcpu)
1410 {
1411         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1412 }
1413
1414 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1415 {
1416         struct vcpu_vmx *vmx = to_vmx(vcpu);
1417         unsigned long rflags, save_rflags;
1418
1419         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1420                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1421                 rflags = vmcs_readl(GUEST_RFLAGS);
1422                 if (vmx->rmode.vm86_active) {
1423                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1424                         save_rflags = vmx->rmode.save_rflags;
1425                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1426                 }
1427                 vmx->rflags = rflags;
1428         }
1429         return vmx->rflags;
1430 }
1431
1432 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1433 {
1434         struct vcpu_vmx *vmx = to_vmx(vcpu);
1435         unsigned long old_rflags;
1436
1437         if (enable_unrestricted_guest) {
1438                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1439                 vmx->rflags = rflags;
1440                 vmcs_writel(GUEST_RFLAGS, rflags);
1441                 return;
1442         }
1443
1444         old_rflags = vmx_get_rflags(vcpu);
1445         vmx->rflags = rflags;
1446         if (vmx->rmode.vm86_active) {
1447                 vmx->rmode.save_rflags = rflags;
1448                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1449         }
1450         vmcs_writel(GUEST_RFLAGS, rflags);
1451
1452         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1453                 vmx->emulation_required = emulation_required(vcpu);
1454 }
1455
1456 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1457 {
1458         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1459         int ret = 0;
1460
1461         if (interruptibility & GUEST_INTR_STATE_STI)
1462                 ret |= KVM_X86_SHADOW_INT_STI;
1463         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1464                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1465
1466         return ret;
1467 }
1468
1469 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1470 {
1471         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1472         u32 interruptibility = interruptibility_old;
1473
1474         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1475
1476         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1477                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1478         else if (mask & KVM_X86_SHADOW_INT_STI)
1479                 interruptibility |= GUEST_INTR_STATE_STI;
1480
1481         if ((interruptibility != interruptibility_old))
1482                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1483 }
1484
1485 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1486 {
1487         struct vcpu_vmx *vmx = to_vmx(vcpu);
1488         unsigned long value;
1489
1490         /*
1491          * Any MSR write that attempts to change bits marked reserved will
1492          * case a #GP fault.
1493          */
1494         if (data & vmx->pt_desc.ctl_bitmask)
1495                 return 1;
1496
1497         /*
1498          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1499          * result in a #GP unless the same write also clears TraceEn.
1500          */
1501         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1502                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1503                 return 1;
1504
1505         /*
1506          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1507          * and FabricEn would cause #GP, if
1508          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1509          */
1510         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1511                 !(data & RTIT_CTL_FABRIC_EN) &&
1512                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1513                                         PT_CAP_single_range_output))
1514                 return 1;
1515
1516         /*
1517          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1518          * utilize encodings marked reserved will casue a #GP fault.
1519          */
1520         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1521         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1522                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1523                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1524                 return 1;
1525         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1526                                                 PT_CAP_cycle_thresholds);
1527         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1528                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1529                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1530                 return 1;
1531         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1532         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1533                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1534                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1535                 return 1;
1536
1537         /*
1538          * If ADDRx_CFG is reserved or the encodings is >2 will
1539          * cause a #GP fault.
1540          */
1541         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1542         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1543                 return 1;
1544         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1545         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1546                 return 1;
1547         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1548         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1549                 return 1;
1550         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1551         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1552                 return 1;
1553
1554         return 0;
1555 }
1556
1557 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1558 {
1559         unsigned long rip;
1560
1561         /*
1562          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1563          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1564          * set when EPT misconfig occurs.  In practice, real hardware updates
1565          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1566          * (namely Hyper-V) don't set it due to it being undefined behavior,
1567          * i.e. we end up advancing IP with some random value.
1568          */
1569         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1570             to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1571                 rip = kvm_rip_read(vcpu);
1572                 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1573                 kvm_rip_write(vcpu, rip);
1574         } else {
1575                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1576                         return 0;
1577         }
1578
1579         /* skipping an emulated instruction also counts */
1580         vmx_set_interrupt_shadow(vcpu, 0);
1581
1582         return 1;
1583 }
1584
1585
1586 /*
1587  * Recognizes a pending MTF VM-exit and records the nested state for later
1588  * delivery.
1589  */
1590 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1591 {
1592         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1593         struct vcpu_vmx *vmx = to_vmx(vcpu);
1594
1595         if (!is_guest_mode(vcpu))
1596                 return;
1597
1598         /*
1599          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1600          * T-bit traps. As instruction emulation is completed (i.e. at the
1601          * instruction boundary), any #DB exception pending delivery must be a
1602          * debug-trap. Record the pending MTF state to be delivered in
1603          * vmx_check_nested_events().
1604          */
1605         if (nested_cpu_has_mtf(vmcs12) &&
1606             (!vcpu->arch.exception.pending ||
1607              vcpu->arch.exception.nr == DB_VECTOR))
1608                 vmx->nested.mtf_pending = true;
1609         else
1610                 vmx->nested.mtf_pending = false;
1611 }
1612
1613 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1614 {
1615         vmx_update_emulated_instruction(vcpu);
1616         return skip_emulated_instruction(vcpu);
1617 }
1618
1619 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1620 {
1621         /*
1622          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1623          * explicitly skip the instruction because if the HLT state is set,
1624          * then the instruction is already executing and RIP has already been
1625          * advanced.
1626          */
1627         if (kvm_hlt_in_guest(vcpu->kvm) &&
1628                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1629                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1630 }
1631
1632 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1633 {
1634         struct vcpu_vmx *vmx = to_vmx(vcpu);
1635         unsigned nr = vcpu->arch.exception.nr;
1636         bool has_error_code = vcpu->arch.exception.has_error_code;
1637         u32 error_code = vcpu->arch.exception.error_code;
1638         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1639
1640         kvm_deliver_exception_payload(vcpu);
1641
1642         if (has_error_code) {
1643                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1644                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1645         }
1646
1647         if (vmx->rmode.vm86_active) {
1648                 int inc_eip = 0;
1649                 if (kvm_exception_is_soft(nr))
1650                         inc_eip = vcpu->arch.event_exit_inst_len;
1651                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1652                 return;
1653         }
1654
1655         WARN_ON_ONCE(vmx->emulation_required);
1656
1657         if (kvm_exception_is_soft(nr)) {
1658                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1659                              vmx->vcpu.arch.event_exit_inst_len);
1660                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1661         } else
1662                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1663
1664         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1665
1666         vmx_clear_hlt(vcpu);
1667 }
1668
1669 /*
1670  * Swap MSR entry in host/guest MSR entry array.
1671  */
1672 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1673 {
1674         struct shared_msr_entry tmp;
1675
1676         tmp = vmx->guest_msrs[to];
1677         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1678         vmx->guest_msrs[from] = tmp;
1679 }
1680
1681 /*
1682  * Set up the vmcs to automatically save and restore system
1683  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1684  * mode, as fiddling with msrs is very expensive.
1685  */
1686 static void setup_msrs(struct vcpu_vmx *vmx)
1687 {
1688         int save_nmsrs, index;
1689
1690         save_nmsrs = 0;
1691 #ifdef CONFIG_X86_64
1692         /*
1693          * The SYSCALL MSRs are only needed on long mode guests, and only
1694          * when EFER.SCE is set.
1695          */
1696         if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1697                 index = __find_msr_index(vmx, MSR_STAR);
1698                 if (index >= 0)
1699                         move_msr_up(vmx, index, save_nmsrs++);
1700                 index = __find_msr_index(vmx, MSR_LSTAR);
1701                 if (index >= 0)
1702                         move_msr_up(vmx, index, save_nmsrs++);
1703                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1704                 if (index >= 0)
1705                         move_msr_up(vmx, index, save_nmsrs++);
1706         }
1707 #endif
1708         index = __find_msr_index(vmx, MSR_EFER);
1709         if (index >= 0 && update_transition_efer(vmx, index))
1710                 move_msr_up(vmx, index, save_nmsrs++);
1711         index = __find_msr_index(vmx, MSR_TSC_AUX);
1712         if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1713                 move_msr_up(vmx, index, save_nmsrs++);
1714         index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1715         if (index >= 0)
1716                 move_msr_up(vmx, index, save_nmsrs++);
1717
1718         vmx->save_nmsrs = save_nmsrs;
1719         vmx->guest_msrs_ready = false;
1720
1721         if (cpu_has_vmx_msr_bitmap())
1722                 vmx_update_msr_bitmap(&vmx->vcpu);
1723 }
1724
1725 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1726 {
1727         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1728
1729         if (is_guest_mode(vcpu) &&
1730             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1731                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1732
1733         return vcpu->arch.tsc_offset;
1734 }
1735
1736 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1737 {
1738         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1739         u64 g_tsc_offset = 0;
1740
1741         /*
1742          * We're here if L1 chose not to trap WRMSR to TSC. According
1743          * to the spec, this should set L1's TSC; The offset that L1
1744          * set for L2 remains unchanged, and still needs to be added
1745          * to the newly set TSC to get L2's TSC.
1746          */
1747         if (is_guest_mode(vcpu) &&
1748             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1749                 g_tsc_offset = vmcs12->tsc_offset;
1750
1751         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1752                                    vcpu->arch.tsc_offset - g_tsc_offset,
1753                                    offset);
1754         vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1755         return offset + g_tsc_offset;
1756 }
1757
1758 /*
1759  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1760  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1761  * all guests if the "nested" module option is off, and can also be disabled
1762  * for a single guest by disabling its VMX cpuid bit.
1763  */
1764 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1765 {
1766         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1767 }
1768
1769 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1770                                                  uint64_t val)
1771 {
1772         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1773
1774         return !(val & ~valid_bits);
1775 }
1776
1777 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1778 {
1779         switch (msr->index) {
1780         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1781                 if (!nested)
1782                         return 1;
1783                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1784         default:
1785                 return 1;
1786         }
1787 }
1788
1789 /*
1790  * Reads an msr value (of 'msr_index') into 'pdata'.
1791  * Returns 0 on success, non-0 otherwise.
1792  * Assumes vcpu_load() was already called.
1793  */
1794 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1795 {
1796         struct vcpu_vmx *vmx = to_vmx(vcpu);
1797         struct shared_msr_entry *msr;
1798         u32 index;
1799
1800         switch (msr_info->index) {
1801 #ifdef CONFIG_X86_64
1802         case MSR_FS_BASE:
1803                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1804                 break;
1805         case MSR_GS_BASE:
1806                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1807                 break;
1808         case MSR_KERNEL_GS_BASE:
1809                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1810                 break;
1811 #endif
1812         case MSR_EFER:
1813                 return kvm_get_msr_common(vcpu, msr_info);
1814         case MSR_IA32_TSX_CTRL:
1815                 if (!msr_info->host_initiated &&
1816                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1817                         return 1;
1818                 goto find_shared_msr;
1819         case MSR_IA32_UMWAIT_CONTROL:
1820                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1821                         return 1;
1822
1823                 msr_info->data = vmx->msr_ia32_umwait_control;
1824                 break;
1825         case MSR_IA32_SPEC_CTRL:
1826                 if (!msr_info->host_initiated &&
1827                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1828                         return 1;
1829
1830                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1831                 break;
1832         case MSR_IA32_SYSENTER_CS:
1833                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1834                 break;
1835         case MSR_IA32_SYSENTER_EIP:
1836                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1837                 break;
1838         case MSR_IA32_SYSENTER_ESP:
1839                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1840                 break;
1841         case MSR_IA32_BNDCFGS:
1842                 if (!kvm_mpx_supported() ||
1843                     (!msr_info->host_initiated &&
1844                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1845                         return 1;
1846                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1847                 break;
1848         case MSR_IA32_MCG_EXT_CTL:
1849                 if (!msr_info->host_initiated &&
1850                     !(vmx->msr_ia32_feature_control &
1851                       FEAT_CTL_LMCE_ENABLED))
1852                         return 1;
1853                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1854                 break;
1855         case MSR_IA32_FEAT_CTL:
1856                 msr_info->data = vmx->msr_ia32_feature_control;
1857                 break;
1858         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1859                 if (!nested_vmx_allowed(vcpu))
1860                         return 1;
1861                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1862                                     &msr_info->data))
1863                         return 1;
1864                 /*
1865                  * Enlightened VMCS v1 doesn't have certain fields, but buggy
1866                  * Hyper-V versions are still trying to use corresponding
1867                  * features when they are exposed. Filter out the essential
1868                  * minimum.
1869                  */
1870                 if (!msr_info->host_initiated &&
1871                     vmx->nested.enlightened_vmcs_enabled)
1872                         nested_evmcs_filter_control_msr(msr_info->index,
1873                                                         &msr_info->data);
1874                 break;
1875         case MSR_IA32_RTIT_CTL:
1876                 if (!vmx_pt_mode_is_host_guest())
1877                         return 1;
1878                 msr_info->data = vmx->pt_desc.guest.ctl;
1879                 break;
1880         case MSR_IA32_RTIT_STATUS:
1881                 if (!vmx_pt_mode_is_host_guest())
1882                         return 1;
1883                 msr_info->data = vmx->pt_desc.guest.status;
1884                 break;
1885         case MSR_IA32_RTIT_CR3_MATCH:
1886                 if (!vmx_pt_mode_is_host_guest() ||
1887                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1888                                                 PT_CAP_cr3_filtering))
1889                         return 1;
1890                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1891                 break;
1892         case MSR_IA32_RTIT_OUTPUT_BASE:
1893                 if (!vmx_pt_mode_is_host_guest() ||
1894                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1895                                         PT_CAP_topa_output) &&
1896                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1897                                         PT_CAP_single_range_output)))
1898                         return 1;
1899                 msr_info->data = vmx->pt_desc.guest.output_base;
1900                 break;
1901         case MSR_IA32_RTIT_OUTPUT_MASK:
1902                 if (!vmx_pt_mode_is_host_guest() ||
1903                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1904                                         PT_CAP_topa_output) &&
1905                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1906                                         PT_CAP_single_range_output)))
1907                         return 1;
1908                 msr_info->data = vmx->pt_desc.guest.output_mask;
1909                 break;
1910         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1911                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1912                 if (!vmx_pt_mode_is_host_guest() ||
1913                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1914                                         PT_CAP_num_address_ranges)))
1915                         return 1;
1916                 if (index % 2)
1917                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1918                 else
1919                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1920                 break;
1921         case MSR_TSC_AUX:
1922                 if (!msr_info->host_initiated &&
1923                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1924                         return 1;
1925                 goto find_shared_msr;
1926         default:
1927         find_shared_msr:
1928                 msr = find_msr_entry(vmx, msr_info->index);
1929                 if (msr) {
1930                         msr_info->data = msr->data;
1931                         break;
1932                 }
1933                 return kvm_get_msr_common(vcpu, msr_info);
1934         }
1935
1936         return 0;
1937 }
1938
1939 /*
1940  * Writes msr value into the appropriate "register".
1941  * Returns 0 on success, non-0 otherwise.
1942  * Assumes vcpu_load() was already called.
1943  */
1944 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1945 {
1946         struct vcpu_vmx *vmx = to_vmx(vcpu);
1947         struct shared_msr_entry *msr;
1948         int ret = 0;
1949         u32 msr_index = msr_info->index;
1950         u64 data = msr_info->data;
1951         u32 index;
1952
1953         switch (msr_index) {
1954         case MSR_EFER:
1955                 ret = kvm_set_msr_common(vcpu, msr_info);
1956                 break;
1957 #ifdef CONFIG_X86_64
1958         case MSR_FS_BASE:
1959                 vmx_segment_cache_clear(vmx);
1960                 vmcs_writel(GUEST_FS_BASE, data);
1961                 break;
1962         case MSR_GS_BASE:
1963                 vmx_segment_cache_clear(vmx);
1964                 vmcs_writel(GUEST_GS_BASE, data);
1965                 break;
1966         case MSR_KERNEL_GS_BASE:
1967                 vmx_write_guest_kernel_gs_base(vmx, data);
1968                 break;
1969 #endif
1970         case MSR_IA32_SYSENTER_CS:
1971                 if (is_guest_mode(vcpu))
1972                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1973                 vmcs_write32(GUEST_SYSENTER_CS, data);
1974                 break;
1975         case MSR_IA32_SYSENTER_EIP:
1976                 if (is_guest_mode(vcpu))
1977                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1978                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1979                 break;
1980         case MSR_IA32_SYSENTER_ESP:
1981                 if (is_guest_mode(vcpu))
1982                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1983                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1984                 break;
1985         case MSR_IA32_DEBUGCTLMSR:
1986                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1987                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
1988                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1989
1990                 ret = kvm_set_msr_common(vcpu, msr_info);
1991                 break;
1992
1993         case MSR_IA32_BNDCFGS:
1994                 if (!kvm_mpx_supported() ||
1995                     (!msr_info->host_initiated &&
1996                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1997                         return 1;
1998                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1999                     (data & MSR_IA32_BNDCFGS_RSVD))
2000                         return 1;
2001                 vmcs_write64(GUEST_BNDCFGS, data);
2002                 break;
2003         case MSR_IA32_UMWAIT_CONTROL:
2004                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2005                         return 1;
2006
2007                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2008                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2009                         return 1;
2010
2011                 vmx->msr_ia32_umwait_control = data;
2012                 break;
2013         case MSR_IA32_SPEC_CTRL:
2014                 if (!msr_info->host_initiated &&
2015                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2016                         return 1;
2017
2018                 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
2019                         return 1;
2020
2021                 vmx->spec_ctrl = data;
2022                 if (!data)
2023                         break;
2024
2025                 /*
2026                  * For non-nested:
2027                  * When it's written (to non-zero) for the first time, pass
2028                  * it through.
2029                  *
2030                  * For nested:
2031                  * The handling of the MSR bitmap for L2 guests is done in
2032                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2033                  * vmcs02.msr_bitmap here since it gets completely overwritten
2034                  * in the merging. We update the vmcs01 here for L1 as well
2035                  * since it will end up touching the MSR anyway now.
2036                  */
2037                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2038                                               MSR_IA32_SPEC_CTRL,
2039                                               MSR_TYPE_RW);
2040                 break;
2041         case MSR_IA32_TSX_CTRL:
2042                 if (!msr_info->host_initiated &&
2043                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2044                         return 1;
2045                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2046                         return 1;
2047                 goto find_shared_msr;
2048         case MSR_IA32_PRED_CMD:
2049                 if (!msr_info->host_initiated &&
2050                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2051                         return 1;
2052
2053                 if (data & ~PRED_CMD_IBPB)
2054                         return 1;
2055                 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2056                         return 1;
2057                 if (!data)
2058                         break;
2059
2060                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2061
2062                 /*
2063                  * For non-nested:
2064                  * When it's written (to non-zero) for the first time, pass
2065                  * it through.
2066                  *
2067                  * For nested:
2068                  * The handling of the MSR bitmap for L2 guests is done in
2069                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2070                  * vmcs02.msr_bitmap here since it gets completely overwritten
2071                  * in the merging.
2072                  */
2073                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2074                                               MSR_TYPE_W);
2075                 break;
2076         case MSR_IA32_CR_PAT:
2077                 if (!kvm_pat_valid(data))
2078                         return 1;
2079
2080                 if (is_guest_mode(vcpu) &&
2081                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2082                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2083
2084                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2085                         vmcs_write64(GUEST_IA32_PAT, data);
2086                         vcpu->arch.pat = data;
2087                         break;
2088                 }
2089                 ret = kvm_set_msr_common(vcpu, msr_info);
2090                 break;
2091         case MSR_IA32_TSC_ADJUST:
2092                 ret = kvm_set_msr_common(vcpu, msr_info);
2093                 break;
2094         case MSR_IA32_MCG_EXT_CTL:
2095                 if ((!msr_info->host_initiated &&
2096                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2097                        FEAT_CTL_LMCE_ENABLED)) ||
2098                     (data & ~MCG_EXT_CTL_LMCE_EN))
2099                         return 1;
2100                 vcpu->arch.mcg_ext_ctl = data;
2101                 break;
2102         case MSR_IA32_FEAT_CTL:
2103                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2104                     (to_vmx(vcpu)->msr_ia32_feature_control &
2105                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2106                         return 1;
2107                 vmx->msr_ia32_feature_control = data;
2108                 if (msr_info->host_initiated && data == 0)
2109                         vmx_leave_nested(vcpu);
2110                 break;
2111         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2112                 if (!msr_info->host_initiated)
2113                         return 1; /* they are read-only */
2114                 if (!nested_vmx_allowed(vcpu))
2115                         return 1;
2116                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2117         case MSR_IA32_RTIT_CTL:
2118                 if (!vmx_pt_mode_is_host_guest() ||
2119                         vmx_rtit_ctl_check(vcpu, data) ||
2120                         vmx->nested.vmxon)
2121                         return 1;
2122                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2123                 vmx->pt_desc.guest.ctl = data;
2124                 pt_update_intercept_for_msr(vmx);
2125                 break;
2126         case MSR_IA32_RTIT_STATUS:
2127                 if (!pt_can_write_msr(vmx))
2128                         return 1;
2129                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2130                         return 1;
2131                 vmx->pt_desc.guest.status = data;
2132                 break;
2133         case MSR_IA32_RTIT_CR3_MATCH:
2134                 if (!pt_can_write_msr(vmx))
2135                         return 1;
2136                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2137                                            PT_CAP_cr3_filtering))
2138                         return 1;
2139                 vmx->pt_desc.guest.cr3_match = data;
2140                 break;
2141         case MSR_IA32_RTIT_OUTPUT_BASE:
2142                 if (!pt_can_write_msr(vmx))
2143                         return 1;
2144                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2145                                            PT_CAP_topa_output) &&
2146                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2147                                            PT_CAP_single_range_output))
2148                         return 1;
2149                 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
2150                         return 1;
2151                 vmx->pt_desc.guest.output_base = data;
2152                 break;
2153         case MSR_IA32_RTIT_OUTPUT_MASK:
2154                 if (!pt_can_write_msr(vmx))
2155                         return 1;
2156                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2157                                            PT_CAP_topa_output) &&
2158                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2159                                            PT_CAP_single_range_output))
2160                         return 1;
2161                 vmx->pt_desc.guest.output_mask = data;
2162                 break;
2163         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2164                 if (!pt_can_write_msr(vmx))
2165                         return 1;
2166                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2167                 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2168                                                        PT_CAP_num_address_ranges))
2169                         return 1;
2170                 if (is_noncanonical_address(data, vcpu))
2171                         return 1;
2172                 if (index % 2)
2173                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2174                 else
2175                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2176                 break;
2177         case MSR_TSC_AUX:
2178                 if (!msr_info->host_initiated &&
2179                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2180                         return 1;
2181                 /* Check reserved bit, higher 32 bits should be zero */
2182                 if ((data >> 32) != 0)
2183                         return 1;
2184                 goto find_shared_msr;
2185
2186         default:
2187         find_shared_msr:
2188                 msr = find_msr_entry(vmx, msr_index);
2189                 if (msr)
2190                         ret = vmx_set_guest_msr(vmx, msr, data);
2191                 else
2192                         ret = kvm_set_msr_common(vcpu, msr_info);
2193         }
2194
2195         return ret;
2196 }
2197
2198 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2199 {
2200         kvm_register_mark_available(vcpu, reg);
2201
2202         switch (reg) {
2203         case VCPU_REGS_RSP:
2204                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2205                 break;
2206         case VCPU_REGS_RIP:
2207                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2208                 break;
2209         case VCPU_EXREG_PDPTR:
2210                 if (enable_ept)
2211                         ept_save_pdptrs(vcpu);
2212                 break;
2213         case VCPU_EXREG_CR3:
2214                 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2215                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2216                 break;
2217         default:
2218                 WARN_ON_ONCE(1);
2219                 break;
2220         }
2221 }
2222
2223 static __init int cpu_has_kvm_support(void)
2224 {
2225         return cpu_has_vmx();
2226 }
2227
2228 static __init int vmx_disabled_by_bios(void)
2229 {
2230         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2231                !boot_cpu_has(X86_FEATURE_VMX);
2232 }
2233
2234 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2235 {
2236         u64 msr;
2237
2238         cr4_set_bits(X86_CR4_VMXE);
2239         intel_pt_handle_vmx(1);
2240
2241         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2242                           _ASM_EXTABLE(1b, %l[fault])
2243                           : : [vmxon_pointer] "m"(vmxon_pointer)
2244                           : : fault);
2245         return 0;
2246
2247 fault:
2248         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2249                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2250         intel_pt_handle_vmx(0);
2251         cr4_clear_bits(X86_CR4_VMXE);
2252
2253         return -EFAULT;
2254 }
2255
2256 static int hardware_enable(void)
2257 {
2258         int cpu = raw_smp_processor_id();
2259         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2260         int r;
2261
2262         if (cr4_read_shadow() & X86_CR4_VMXE)
2263                 return -EBUSY;
2264
2265         /*
2266          * This can happen if we hot-added a CPU but failed to allocate
2267          * VP assist page for it.
2268          */
2269         if (static_branch_unlikely(&enable_evmcs) &&
2270             !hv_get_vp_assist_page(cpu))
2271                 return -EFAULT;
2272
2273         r = kvm_cpu_vmxon(phys_addr);
2274         if (r)
2275                 return r;
2276
2277         if (enable_ept)
2278                 ept_sync_global();
2279
2280         return 0;
2281 }
2282
2283 static void vmclear_local_loaded_vmcss(void)
2284 {
2285         int cpu = raw_smp_processor_id();
2286         struct loaded_vmcs *v, *n;
2287
2288         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2289                                  loaded_vmcss_on_cpu_link)
2290                 __loaded_vmcs_clear(v);
2291 }
2292
2293
2294 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2295  * tricks.
2296  */
2297 static void kvm_cpu_vmxoff(void)
2298 {
2299         asm volatile (__ex("vmxoff"));
2300
2301         intel_pt_handle_vmx(0);
2302         cr4_clear_bits(X86_CR4_VMXE);
2303 }
2304
2305 static void hardware_disable(void)
2306 {
2307         vmclear_local_loaded_vmcss();
2308         kvm_cpu_vmxoff();
2309 }
2310
2311 /*
2312  * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2313  * directly instead of going through cpu_has(), to ensure KVM is trapping
2314  * ENCLS whenever it's supported in hardware.  It does not matter whether
2315  * the host OS supports or has enabled SGX.
2316  */
2317 static bool cpu_has_sgx(void)
2318 {
2319         return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2320 }
2321
2322 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2323                                       u32 msr, u32 *result)
2324 {
2325         u32 vmx_msr_low, vmx_msr_high;
2326         u32 ctl = ctl_min | ctl_opt;
2327
2328         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2329
2330         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2331         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2332
2333         /* Ensure minimum (required) set of control bits are supported. */
2334         if (ctl_min & ~ctl)
2335                 return -EIO;
2336
2337         *result = ctl;
2338         return 0;
2339 }
2340
2341 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2342                                     struct vmx_capability *vmx_cap)
2343 {
2344         u32 vmx_msr_low, vmx_msr_high;
2345         u32 min, opt, min2, opt2;
2346         u32 _pin_based_exec_control = 0;
2347         u32 _cpu_based_exec_control = 0;
2348         u32 _cpu_based_2nd_exec_control = 0;
2349         u32 _vmexit_control = 0;
2350         u32 _vmentry_control = 0;
2351
2352         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2353         min = CPU_BASED_HLT_EXITING |
2354 #ifdef CONFIG_X86_64
2355               CPU_BASED_CR8_LOAD_EXITING |
2356               CPU_BASED_CR8_STORE_EXITING |
2357 #endif
2358               CPU_BASED_CR3_LOAD_EXITING |
2359               CPU_BASED_CR3_STORE_EXITING |
2360               CPU_BASED_UNCOND_IO_EXITING |
2361               CPU_BASED_MOV_DR_EXITING |
2362               CPU_BASED_USE_TSC_OFFSETTING |
2363               CPU_BASED_MWAIT_EXITING |
2364               CPU_BASED_MONITOR_EXITING |
2365               CPU_BASED_INVLPG_EXITING |
2366               CPU_BASED_RDPMC_EXITING;
2367
2368         opt = CPU_BASED_TPR_SHADOW |
2369               CPU_BASED_USE_MSR_BITMAPS |
2370               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2371         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2372                                 &_cpu_based_exec_control) < 0)
2373                 return -EIO;
2374 #ifdef CONFIG_X86_64
2375         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2376                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2377                                            ~CPU_BASED_CR8_STORE_EXITING;
2378 #endif
2379         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2380                 min2 = 0;
2381                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2382                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2383                         SECONDARY_EXEC_WBINVD_EXITING |
2384                         SECONDARY_EXEC_ENABLE_VPID |
2385                         SECONDARY_EXEC_ENABLE_EPT |
2386                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2387                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2388                         SECONDARY_EXEC_DESC |
2389                         SECONDARY_EXEC_RDTSCP |
2390                         SECONDARY_EXEC_ENABLE_INVPCID |
2391                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2392                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2393                         SECONDARY_EXEC_SHADOW_VMCS |
2394                         SECONDARY_EXEC_XSAVES |
2395                         SECONDARY_EXEC_RDSEED_EXITING |
2396                         SECONDARY_EXEC_RDRAND_EXITING |
2397                         SECONDARY_EXEC_ENABLE_PML |
2398                         SECONDARY_EXEC_TSC_SCALING |
2399                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2400                         SECONDARY_EXEC_PT_USE_GPA |
2401                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2402                         SECONDARY_EXEC_ENABLE_VMFUNC;
2403                 if (cpu_has_sgx())
2404                         opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2405                 if (adjust_vmx_controls(min2, opt2,
2406                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2407                                         &_cpu_based_2nd_exec_control) < 0)
2408                         return -EIO;
2409         }
2410 #ifndef CONFIG_X86_64
2411         if (!(_cpu_based_2nd_exec_control &
2412                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2413                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2414 #endif
2415
2416         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2417                 _cpu_based_2nd_exec_control &= ~(
2418                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2419                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2420                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2421
2422         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2423                 &vmx_cap->ept, &vmx_cap->vpid);
2424
2425         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2426                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2427                    enabled */
2428                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2429                                              CPU_BASED_CR3_STORE_EXITING |
2430                                              CPU_BASED_INVLPG_EXITING);
2431         } else if (vmx_cap->ept) {
2432                 vmx_cap->ept = 0;
2433                 pr_warn_once("EPT CAP should not exist if not support "
2434                                 "1-setting enable EPT VM-execution control\n");
2435         }
2436         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2437                 vmx_cap->vpid) {
2438                 vmx_cap->vpid = 0;
2439                 pr_warn_once("VPID CAP should not exist if not support "
2440                                 "1-setting enable VPID VM-execution control\n");
2441         }
2442
2443         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2444 #ifdef CONFIG_X86_64
2445         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2446 #endif
2447         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2448               VM_EXIT_LOAD_IA32_PAT |
2449               VM_EXIT_LOAD_IA32_EFER |
2450               VM_EXIT_CLEAR_BNDCFGS |
2451               VM_EXIT_PT_CONCEAL_PIP |
2452               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2453         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2454                                 &_vmexit_control) < 0)
2455                 return -EIO;
2456
2457         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2458         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2459                  PIN_BASED_VMX_PREEMPTION_TIMER;
2460         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2461                                 &_pin_based_exec_control) < 0)
2462                 return -EIO;
2463
2464         if (cpu_has_broken_vmx_preemption_timer())
2465                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2466         if (!(_cpu_based_2nd_exec_control &
2467                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2468                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2469
2470         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2471         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2472               VM_ENTRY_LOAD_IA32_PAT |
2473               VM_ENTRY_LOAD_IA32_EFER |
2474               VM_ENTRY_LOAD_BNDCFGS |
2475               VM_ENTRY_PT_CONCEAL_PIP |
2476               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2477         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2478                                 &_vmentry_control) < 0)
2479                 return -EIO;
2480
2481         /*
2482          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2483          * can't be used due to an errata where VM Exit may incorrectly clear
2484          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2485          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2486          */
2487         if (boot_cpu_data.x86 == 0x6) {
2488                 switch (boot_cpu_data.x86_model) {
2489                 case 26: /* AAK155 */
2490                 case 30: /* AAP115 */
2491                 case 37: /* AAT100 */
2492                 case 44: /* BC86,AAY89,BD102 */
2493                 case 46: /* BA97 */
2494                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2495                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2496                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2497                                         "does not work properly. Using workaround\n");
2498                         break;
2499                 default:
2500                         break;
2501                 }
2502         }
2503
2504
2505         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2506
2507         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2508         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2509                 return -EIO;
2510
2511 #ifdef CONFIG_X86_64
2512         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2513         if (vmx_msr_high & (1u<<16))
2514                 return -EIO;
2515 #endif
2516
2517         /* Require Write-Back (WB) memory type for VMCS accesses. */
2518         if (((vmx_msr_high >> 18) & 15) != 6)
2519                 return -EIO;
2520
2521         vmcs_conf->size = vmx_msr_high & 0x1fff;
2522         vmcs_conf->order = get_order(vmcs_conf->size);
2523         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2524
2525         vmcs_conf->revision_id = vmx_msr_low;
2526
2527         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2528         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2529         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2530         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2531         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2532
2533         if (static_branch_unlikely(&enable_evmcs))
2534                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2535
2536         return 0;
2537 }
2538
2539 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2540 {
2541         int node = cpu_to_node(cpu);
2542         struct page *pages;
2543         struct vmcs *vmcs;
2544
2545         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2546         if (!pages)
2547                 return NULL;
2548         vmcs = page_address(pages);
2549         memset(vmcs, 0, vmcs_config.size);
2550
2551         /* KVM supports Enlightened VMCS v1 only */
2552         if (static_branch_unlikely(&enable_evmcs))
2553                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2554         else
2555                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2556
2557         if (shadow)
2558                 vmcs->hdr.shadow_vmcs = 1;
2559         return vmcs;
2560 }
2561
2562 void free_vmcs(struct vmcs *vmcs)
2563 {
2564         free_pages((unsigned long)vmcs, vmcs_config.order);
2565 }
2566
2567 /*
2568  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2569  */
2570 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2571 {
2572         if (!loaded_vmcs->vmcs)
2573                 return;
2574         loaded_vmcs_clear(loaded_vmcs);
2575         free_vmcs(loaded_vmcs->vmcs);
2576         loaded_vmcs->vmcs = NULL;
2577         if (loaded_vmcs->msr_bitmap)
2578                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2579         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2580 }
2581
2582 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2583 {
2584         loaded_vmcs->vmcs = alloc_vmcs(false);
2585         if (!loaded_vmcs->vmcs)
2586                 return -ENOMEM;
2587
2588         vmcs_clear(loaded_vmcs->vmcs);
2589
2590         loaded_vmcs->shadow_vmcs = NULL;
2591         loaded_vmcs->hv_timer_soft_disabled = false;
2592         loaded_vmcs->cpu = -1;
2593         loaded_vmcs->launched = 0;
2594
2595         if (cpu_has_vmx_msr_bitmap()) {
2596                 loaded_vmcs->msr_bitmap = (unsigned long *)
2597                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2598                 if (!loaded_vmcs->msr_bitmap)
2599                         goto out_vmcs;
2600                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2601
2602                 if (IS_ENABLED(CONFIG_HYPERV) &&
2603                     static_branch_unlikely(&enable_evmcs) &&
2604                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2605                         struct hv_enlightened_vmcs *evmcs =
2606                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2607
2608                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2609                 }
2610         }
2611
2612         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2613         memset(&loaded_vmcs->controls_shadow, 0,
2614                 sizeof(struct vmcs_controls_shadow));
2615
2616         return 0;
2617
2618 out_vmcs:
2619         free_loaded_vmcs(loaded_vmcs);
2620         return -ENOMEM;
2621 }
2622
2623 static void free_kvm_area(void)
2624 {
2625         int cpu;
2626
2627         for_each_possible_cpu(cpu) {
2628                 free_vmcs(per_cpu(vmxarea, cpu));
2629                 per_cpu(vmxarea, cpu) = NULL;
2630         }
2631 }
2632
2633 static __init int alloc_kvm_area(void)
2634 {
2635         int cpu;
2636
2637         for_each_possible_cpu(cpu) {
2638                 struct vmcs *vmcs;
2639
2640                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2641                 if (!vmcs) {
2642                         free_kvm_area();
2643                         return -ENOMEM;
2644                 }
2645
2646                 /*
2647                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2648                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2649                  * revision_id reported by MSR_IA32_VMX_BASIC.
2650                  *
2651                  * However, even though not explicitly documented by
2652                  * TLFS, VMXArea passed as VMXON argument should
2653                  * still be marked with revision_id reported by
2654                  * physical CPU.
2655                  */
2656                 if (static_branch_unlikely(&enable_evmcs))
2657                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2658
2659                 per_cpu(vmxarea, cpu) = vmcs;
2660         }
2661         return 0;
2662 }
2663
2664 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2665                 struct kvm_segment *save)
2666 {
2667         if (!emulate_invalid_guest_state) {
2668                 /*
2669                  * CS and SS RPL should be equal during guest entry according
2670                  * to VMX spec, but in reality it is not always so. Since vcpu
2671                  * is in the middle of the transition from real mode to
2672                  * protected mode it is safe to assume that RPL 0 is a good
2673                  * default value.
2674                  */
2675                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2676                         save->selector &= ~SEGMENT_RPL_MASK;
2677                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2678                 save->s = 1;
2679         }
2680         vmx_set_segment(vcpu, save, seg);
2681 }
2682
2683 static void enter_pmode(struct kvm_vcpu *vcpu)
2684 {
2685         unsigned long flags;
2686         struct vcpu_vmx *vmx = to_vmx(vcpu);
2687
2688         /*
2689          * Update real mode segment cache. It may be not up-to-date if sement
2690          * register was written while vcpu was in a guest mode.
2691          */
2692         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2693         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2694         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2695         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2696         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2697         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2698
2699         vmx->rmode.vm86_active = 0;
2700
2701         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2702
2703         flags = vmcs_readl(GUEST_RFLAGS);
2704         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2705         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2706         vmcs_writel(GUEST_RFLAGS, flags);
2707
2708         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2709                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2710
2711         update_exception_bitmap(vcpu);
2712
2713         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2714         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2715         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2716         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2717         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2718         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2719 }
2720
2721 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2722 {
2723         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2724         struct kvm_segment var = *save;
2725
2726         var.dpl = 0x3;
2727         if (seg == VCPU_SREG_CS)
2728                 var.type = 0x3;
2729
2730         if (!emulate_invalid_guest_state) {
2731                 var.selector = var.base >> 4;
2732                 var.base = var.base & 0xffff0;
2733                 var.limit = 0xffff;
2734                 var.g = 0;
2735                 var.db = 0;
2736                 var.present = 1;
2737                 var.s = 1;
2738                 var.l = 0;
2739                 var.unusable = 0;
2740                 var.type = 0x3;
2741                 var.avl = 0;
2742                 if (save->base & 0xf)
2743                         printk_once(KERN_WARNING "kvm: segment base is not "
2744                                         "paragraph aligned when entering "
2745                                         "protected mode (seg=%d)", seg);
2746         }
2747
2748         vmcs_write16(sf->selector, var.selector);
2749         vmcs_writel(sf->base, var.base);
2750         vmcs_write32(sf->limit, var.limit);
2751         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2752 }
2753
2754 static void enter_rmode(struct kvm_vcpu *vcpu)
2755 {
2756         unsigned long flags;
2757         struct vcpu_vmx *vmx = to_vmx(vcpu);
2758         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2759
2760         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2761         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2762         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2763         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2764         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2765         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2766         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2767
2768         vmx->rmode.vm86_active = 1;
2769
2770         /*
2771          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2772          * vcpu. Warn the user that an update is overdue.
2773          */
2774         if (!kvm_vmx->tss_addr)
2775                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2776                              "called before entering vcpu\n");
2777
2778         vmx_segment_cache_clear(vmx);
2779
2780         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2781         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2782         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2783
2784         flags = vmcs_readl(GUEST_RFLAGS);
2785         vmx->rmode.save_rflags = flags;
2786
2787         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2788
2789         vmcs_writel(GUEST_RFLAGS, flags);
2790         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2791         update_exception_bitmap(vcpu);
2792
2793         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2794         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2795         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2796         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2797         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2798         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2799
2800         kvm_mmu_reset_context(vcpu);
2801 }
2802
2803 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2804 {
2805         struct vcpu_vmx *vmx = to_vmx(vcpu);
2806         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2807
2808         if (!msr)
2809                 return;
2810
2811         vcpu->arch.efer = efer;
2812         if (efer & EFER_LMA) {
2813                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2814                 msr->data = efer;
2815         } else {
2816                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2817
2818                 msr->data = efer & ~EFER_LME;
2819         }
2820         setup_msrs(vmx);
2821 }
2822
2823 #ifdef CONFIG_X86_64
2824
2825 static void enter_lmode(struct kvm_vcpu *vcpu)
2826 {
2827         u32 guest_tr_ar;
2828
2829         vmx_segment_cache_clear(to_vmx(vcpu));
2830
2831         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2832         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2833                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2834                                      __func__);
2835                 vmcs_write32(GUEST_TR_AR_BYTES,
2836                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2837                              | VMX_AR_TYPE_BUSY_64_TSS);
2838         }
2839         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2840 }
2841
2842 static void exit_lmode(struct kvm_vcpu *vcpu)
2843 {
2844         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2845         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2846 }
2847
2848 #endif
2849
2850 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2851 {
2852         struct vcpu_vmx *vmx = to_vmx(vcpu);
2853
2854         /*
2855          * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2856          * the CPU is not required to invalidate guest-physical mappings on
2857          * VM-Entry, even if VPID is disabled.  Guest-physical mappings are
2858          * associated with the root EPT structure and not any particular VPID
2859          * (INVVPID also isn't required to invalidate guest-physical mappings).
2860          */
2861         if (enable_ept) {
2862                 ept_sync_global();
2863         } else if (enable_vpid) {
2864                 if (cpu_has_vmx_invvpid_global()) {
2865                         vpid_sync_vcpu_global();
2866                 } else {
2867                         vpid_sync_vcpu_single(vmx->vpid);
2868                         vpid_sync_vcpu_single(vmx->nested.vpid02);
2869                 }
2870         }
2871 }
2872
2873 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2874 {
2875         u64 root_hpa = vcpu->arch.mmu->root_hpa;
2876
2877         /* No flush required if the current context is invalid. */
2878         if (!VALID_PAGE(root_hpa))
2879                 return;
2880
2881         if (enable_ept)
2882                 ept_sync_context(construct_eptp(vcpu, root_hpa));
2883         else if (!is_guest_mode(vcpu))
2884                 vpid_sync_context(to_vmx(vcpu)->vpid);
2885         else
2886                 vpid_sync_context(nested_get_vpid02(vcpu));
2887 }
2888
2889 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2890 {
2891         /*
2892          * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2893          * vmx_flush_tlb_guest() for an explanation of why this is ok.
2894          */
2895         vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2896 }
2897
2898 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2899 {
2900         /*
2901          * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2902          * or a vpid couldn't be allocated for this vCPU.  VM-Enter and VM-Exit
2903          * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2904          * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2905          * i.e. no explicit INVVPID is necessary.
2906          */
2907         vpid_sync_context(to_vmx(vcpu)->vpid);
2908 }
2909
2910 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2911 {
2912         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2913
2914         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2915         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2916 }
2917
2918 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2919 {
2920         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2921
2922         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2923         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2924 }
2925
2926 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2927 {
2928         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2929
2930         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2931                 return;
2932
2933         if (is_pae_paging(vcpu)) {
2934                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2935                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2936                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2937                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2938         }
2939 }
2940
2941 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2942 {
2943         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2944
2945         if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2946                 return;
2947
2948         mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2949         mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2950         mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2951         mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2952
2953         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2954 }
2955
2956 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2957                                         unsigned long cr0,
2958                                         struct kvm_vcpu *vcpu)
2959 {
2960         struct vcpu_vmx *vmx = to_vmx(vcpu);
2961
2962         if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2963                 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2964         if (!(cr0 & X86_CR0_PG)) {
2965                 /* From paging/starting to nonpaging */
2966                 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2967                                           CPU_BASED_CR3_STORE_EXITING);
2968                 vcpu->arch.cr0 = cr0;
2969                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2970         } else if (!is_paging(vcpu)) {
2971                 /* From nonpaging to paging */
2972                 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2973                                             CPU_BASED_CR3_STORE_EXITING);
2974                 vcpu->arch.cr0 = cr0;
2975                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2976         }
2977
2978         if (!(cr0 & X86_CR0_WP))
2979                 *hw_cr0 &= ~X86_CR0_WP;
2980 }
2981
2982 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2983 {
2984         struct vcpu_vmx *vmx = to_vmx(vcpu);
2985         unsigned long hw_cr0;
2986
2987         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2988         if (enable_unrestricted_guest)
2989                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2990         else {
2991                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2992
2993                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2994                         enter_pmode(vcpu);
2995
2996                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2997                         enter_rmode(vcpu);
2998         }
2999
3000 #ifdef CONFIG_X86_64
3001         if (vcpu->arch.efer & EFER_LME) {
3002                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3003                         enter_lmode(vcpu);
3004                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3005                         exit_lmode(vcpu);
3006         }
3007 #endif
3008
3009         if (enable_ept && !enable_unrestricted_guest)
3010                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3011
3012         vmcs_writel(CR0_READ_SHADOW, cr0);
3013         vmcs_writel(GUEST_CR0, hw_cr0);
3014         vcpu->arch.cr0 = cr0;
3015
3016         /* depends on vcpu->arch.cr0 to be set to a new value */
3017         vmx->emulation_required = emulation_required(vcpu);
3018 }
3019
3020 static int get_ept_level(struct kvm_vcpu *vcpu)
3021 {
3022         if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu)))
3023                 return vmx_eptp_page_walk_level(nested_ept_get_eptp(vcpu));
3024         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
3025                 return 5;
3026         return 4;
3027 }
3028
3029 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
3030 {
3031         u64 eptp = VMX_EPTP_MT_WB;
3032
3033         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3034
3035         if (enable_ept_ad_bits &&
3036             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3037                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3038         eptp |= (root_hpa & PAGE_MASK);
3039
3040         return eptp;
3041 }
3042
3043 void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long pgd)
3044 {
3045         struct kvm *kvm = vcpu->kvm;
3046         bool update_guest_cr3 = true;
3047         unsigned long guest_cr3;
3048         u64 eptp;
3049
3050         if (enable_ept) {
3051                 eptp = construct_eptp(vcpu, pgd);
3052                 vmcs_write64(EPT_POINTER, eptp);
3053
3054                 if (kvm_x86_ops.tlb_remote_flush) {
3055                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3056                         to_vmx(vcpu)->ept_pointer = eptp;
3057                         to_kvm_vmx(kvm)->ept_pointers_match
3058                                 = EPT_POINTERS_CHECK;
3059                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3060                 }
3061
3062                 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */
3063                 if (is_guest_mode(vcpu))
3064                         update_guest_cr3 = false;
3065                 else if (!enable_unrestricted_guest && !is_paging(vcpu))
3066                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3067                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3068                         guest_cr3 = vcpu->arch.cr3;
3069                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3070                         update_guest_cr3 = false;
3071                 ept_load_pdptrs(vcpu);
3072         } else {
3073                 guest_cr3 = pgd;
3074         }
3075
3076         if (update_guest_cr3)
3077                 vmcs_writel(GUEST_CR3, guest_cr3);
3078 }
3079
3080 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3081 {
3082         struct vcpu_vmx *vmx = to_vmx(vcpu);
3083         /*
3084          * Pass through host's Machine Check Enable value to hw_cr4, which
3085          * is in force while we are in guest mode.  Do not let guests control
3086          * this bit, even if host CR4.MCE == 0.
3087          */
3088         unsigned long hw_cr4;
3089
3090         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3091         if (enable_unrestricted_guest)
3092                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3093         else if (vmx->rmode.vm86_active)
3094                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3095         else
3096                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3097
3098         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3099                 if (cr4 & X86_CR4_UMIP) {
3100                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3101                         hw_cr4 &= ~X86_CR4_UMIP;
3102                 } else if (!is_guest_mode(vcpu) ||
3103                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3104                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3105                 }
3106         }
3107
3108         if (cr4 & X86_CR4_VMXE) {
3109                 /*
3110                  * To use VMXON (and later other VMX instructions), a guest
3111                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3112                  * So basically the check on whether to allow nested VMX
3113                  * is here.  We operate under the default treatment of SMM,
3114                  * so VMX cannot be enabled under SMM.
3115                  */
3116                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3117                         return 1;
3118         }
3119
3120         if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3121                 return 1;
3122
3123         vcpu->arch.cr4 = cr4;
3124
3125         if (!enable_unrestricted_guest) {
3126                 if (enable_ept) {
3127                         if (!is_paging(vcpu)) {
3128                                 hw_cr4 &= ~X86_CR4_PAE;
3129                                 hw_cr4 |= X86_CR4_PSE;
3130                         } else if (!(cr4 & X86_CR4_PAE)) {
3131                                 hw_cr4 &= ~X86_CR4_PAE;
3132                         }
3133                 }
3134
3135                 /*
3136                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3137                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3138                  * to be manually disabled when guest switches to non-paging
3139                  * mode.
3140                  *
3141                  * If !enable_unrestricted_guest, the CPU is always running
3142                  * with CR0.PG=1 and CR4 needs to be modified.
3143                  * If enable_unrestricted_guest, the CPU automatically
3144                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3145                  */
3146                 if (!is_paging(vcpu))
3147                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3148         }
3149
3150         vmcs_writel(CR4_READ_SHADOW, cr4);
3151         vmcs_writel(GUEST_CR4, hw_cr4);
3152         return 0;
3153 }
3154
3155 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3156 {
3157         struct vcpu_vmx *vmx = to_vmx(vcpu);
3158         u32 ar;
3159
3160         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3161                 *var = vmx->rmode.segs[seg];
3162                 if (seg == VCPU_SREG_TR
3163                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3164                         return;
3165                 var->base = vmx_read_guest_seg_base(vmx, seg);
3166                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3167                 return;
3168         }
3169         var->base = vmx_read_guest_seg_base(vmx, seg);
3170         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3171         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3172         ar = vmx_read_guest_seg_ar(vmx, seg);
3173         var->unusable = (ar >> 16) & 1;
3174         var->type = ar & 15;
3175         var->s = (ar >> 4) & 1;
3176         var->dpl = (ar >> 5) & 3;
3177         /*
3178          * Some userspaces do not preserve unusable property. Since usable
3179          * segment has to be present according to VMX spec we can use present
3180          * property to amend userspace bug by making unusable segment always
3181          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3182          * segment as unusable.
3183          */
3184         var->present = !var->unusable;
3185         var->avl = (ar >> 12) & 1;
3186         var->l = (ar >> 13) & 1;
3187         var->db = (ar >> 14) & 1;
3188         var->g = (ar >> 15) & 1;
3189 }
3190
3191 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3192 {
3193         struct kvm_segment s;
3194
3195         if (to_vmx(vcpu)->rmode.vm86_active) {
3196                 vmx_get_segment(vcpu, &s, seg);
3197                 return s.base;
3198         }
3199         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3200 }
3201
3202 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3203 {
3204         struct vcpu_vmx *vmx = to_vmx(vcpu);
3205
3206         if (unlikely(vmx->rmode.vm86_active))
3207                 return 0;
3208         else {
3209                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3210                 return VMX_AR_DPL(ar);
3211         }
3212 }
3213
3214 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3215 {
3216         u32 ar;
3217
3218         if (var->unusable || !var->present)
3219                 ar = 1 << 16;
3220         else {
3221                 ar = var->type & 15;
3222                 ar |= (var->s & 1) << 4;
3223                 ar |= (var->dpl & 3) << 5;
3224                 ar |= (var->present & 1) << 7;
3225                 ar |= (var->avl & 1) << 12;
3226                 ar |= (var->l & 1) << 13;
3227                 ar |= (var->db & 1) << 14;
3228                 ar |= (var->g & 1) << 15;
3229         }
3230
3231         return ar;
3232 }
3233
3234 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3235 {
3236         struct vcpu_vmx *vmx = to_vmx(vcpu);
3237         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3238
3239         vmx_segment_cache_clear(vmx);
3240
3241         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3242                 vmx->rmode.segs[seg] = *var;
3243                 if (seg == VCPU_SREG_TR)
3244                         vmcs_write16(sf->selector, var->selector);
3245                 else if (var->s)
3246                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3247                 goto out;
3248         }
3249
3250         vmcs_writel(sf->base, var->base);
3251         vmcs_write32(sf->limit, var->limit);
3252         vmcs_write16(sf->selector, var->selector);
3253
3254         /*
3255          *   Fix the "Accessed" bit in AR field of segment registers for older
3256          * qemu binaries.
3257          *   IA32 arch specifies that at the time of processor reset the
3258          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3259          * is setting it to 0 in the userland code. This causes invalid guest
3260          * state vmexit when "unrestricted guest" mode is turned on.
3261          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3262          * tree. Newer qemu binaries with that qemu fix would not need this
3263          * kvm hack.
3264          */
3265         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3266                 var->type |= 0x1; /* Accessed */
3267
3268         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3269
3270 out:
3271         vmx->emulation_required = emulation_required(vcpu);
3272 }
3273
3274 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3275 {
3276         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3277
3278         *db = (ar >> 14) & 1;
3279         *l = (ar >> 13) & 1;
3280 }
3281
3282 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3283 {
3284         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3285         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3286 }
3287
3288 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3289 {
3290         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3291         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3292 }
3293
3294 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3295 {
3296         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3297         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3298 }
3299
3300 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3301 {
3302         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3303         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3304 }
3305
3306 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3307 {
3308         struct kvm_segment var;
3309         u32 ar;
3310
3311         vmx_get_segment(vcpu, &var, seg);
3312         var.dpl = 0x3;
3313         if (seg == VCPU_SREG_CS)
3314                 var.type = 0x3;
3315         ar = vmx_segment_access_rights(&var);
3316
3317         if (var.base != (var.selector << 4))
3318                 return false;
3319         if (var.limit != 0xffff)
3320                 return false;
3321         if (ar != 0xf3)
3322                 return false;
3323
3324         return true;
3325 }
3326
3327 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3328 {
3329         struct kvm_segment cs;
3330         unsigned int cs_rpl;
3331
3332         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3333         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3334
3335         if (cs.unusable)
3336                 return false;
3337         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3338                 return false;
3339         if (!cs.s)
3340                 return false;
3341         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3342                 if (cs.dpl > cs_rpl)
3343                         return false;
3344         } else {
3345                 if (cs.dpl != cs_rpl)
3346                         return false;
3347         }
3348         if (!cs.present)
3349                 return false;
3350
3351         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3352         return true;
3353 }
3354
3355 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3356 {
3357         struct kvm_segment ss;
3358         unsigned int ss_rpl;
3359
3360         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3361         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3362
3363         if (ss.unusable)
3364                 return true;
3365         if (ss.type != 3 && ss.type != 7)
3366                 return false;
3367         if (!ss.s)
3368                 return false;
3369         if (ss.dpl != ss_rpl) /* DPL != RPL */
3370                 return false;
3371         if (!ss.present)
3372                 return false;
3373
3374         return true;
3375 }
3376
3377 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3378 {
3379         struct kvm_segment var;
3380         unsigned int rpl;
3381
3382         vmx_get_segment(vcpu, &var, seg);
3383         rpl = var.selector & SEGMENT_RPL_MASK;
3384
3385         if (var.unusable)
3386                 return true;
3387         if (!var.s)
3388                 return false;
3389         if (!var.present)
3390                 return false;
3391         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3392                 if (var.dpl < rpl) /* DPL < RPL */
3393                         return false;
3394         }
3395
3396         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3397          * rights flags
3398          */
3399         return true;
3400 }
3401
3402 static bool tr_valid(struct kvm_vcpu *vcpu)
3403 {
3404         struct kvm_segment tr;
3405
3406         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3407
3408         if (tr.unusable)
3409                 return false;
3410         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3411                 return false;
3412         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3413                 return false;
3414         if (!tr.present)
3415                 return false;
3416
3417         return true;
3418 }
3419
3420 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3421 {
3422         struct kvm_segment ldtr;
3423
3424         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3425
3426         if (ldtr.unusable)
3427                 return true;
3428         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3429                 return false;
3430         if (ldtr.type != 2)
3431                 return false;
3432         if (!ldtr.present)
3433                 return false;
3434
3435         return true;
3436 }
3437
3438 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3439 {
3440         struct kvm_segment cs, ss;
3441
3442         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3443         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3444
3445         return ((cs.selector & SEGMENT_RPL_MASK) ==
3446                  (ss.selector & SEGMENT_RPL_MASK));
3447 }
3448
3449 /*
3450  * Check if guest state is valid. Returns true if valid, false if
3451  * not.
3452  * We assume that registers are always usable
3453  */
3454 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3455 {
3456         if (enable_unrestricted_guest)
3457                 return true;
3458
3459         /* real mode guest state checks */
3460         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3461                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3462                         return false;
3463                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3464                         return false;
3465                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3466                         return false;
3467                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3468                         return false;
3469                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3470                         return false;
3471                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3472                         return false;
3473         } else {
3474         /* protected mode guest state checks */
3475                 if (!cs_ss_rpl_check(vcpu))
3476                         return false;
3477                 if (!code_segment_valid(vcpu))
3478                         return false;
3479                 if (!stack_segment_valid(vcpu))
3480                         return false;
3481                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3482                         return false;
3483                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3484                         return false;
3485                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3486                         return false;
3487                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3488                         return false;
3489                 if (!tr_valid(vcpu))
3490                         return false;
3491                 if (!ldtr_valid(vcpu))
3492                         return false;
3493         }
3494         /* TODO:
3495          * - Add checks on RIP
3496          * - Add checks on RFLAGS
3497          */
3498
3499         return true;
3500 }
3501
3502 static int init_rmode_tss(struct kvm *kvm)
3503 {
3504         gfn_t fn;
3505         u16 data = 0;
3506         int idx, r;
3507
3508         idx = srcu_read_lock(&kvm->srcu);
3509         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3510         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3511         if (r < 0)
3512                 goto out;
3513         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3514         r = kvm_write_guest_page(kvm, fn++, &data,
3515                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3516         if (r < 0)
3517                 goto out;
3518         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3519         if (r < 0)
3520                 goto out;
3521         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3522         if (r < 0)
3523                 goto out;
3524         data = ~0;
3525         r = kvm_write_guest_page(kvm, fn, &data,
3526                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3527                                  sizeof(u8));
3528 out:
3529         srcu_read_unlock(&kvm->srcu, idx);
3530         return r;
3531 }
3532
3533 static int init_rmode_identity_map(struct kvm *kvm)
3534 {
3535         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3536         int i, r = 0;
3537         kvm_pfn_t identity_map_pfn;
3538         u32 tmp;
3539
3540         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3541         mutex_lock(&kvm->slots_lock);
3542
3543         if (likely(kvm_vmx->ept_identity_pagetable_done))
3544                 goto out;
3545
3546         if (!kvm_vmx->ept_identity_map_addr)
3547                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3548         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3549
3550         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3551                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3552         if (r < 0)
3553                 goto out;
3554
3555         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3556         if (r < 0)
3557                 goto out;
3558         /* Set up identity-mapping pagetable for EPT in real mode */
3559         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3560                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3561                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3562                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3563                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3564                 if (r < 0)
3565                         goto out;
3566         }
3567         kvm_vmx->ept_identity_pagetable_done = true;
3568
3569 out:
3570         mutex_unlock(&kvm->slots_lock);
3571         return r;
3572 }
3573
3574 static void seg_setup(int seg)
3575 {
3576         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3577         unsigned int ar;
3578
3579         vmcs_write16(sf->selector, 0);
3580         vmcs_writel(sf->base, 0);
3581         vmcs_write32(sf->limit, 0xffff);
3582         ar = 0x93;
3583         if (seg == VCPU_SREG_CS)
3584                 ar |= 0x08; /* code segment */
3585
3586         vmcs_write32(sf->ar_bytes, ar);
3587 }
3588
3589 static int alloc_apic_access_page(struct kvm *kvm)
3590 {
3591         struct page *page;
3592         int r = 0;
3593
3594         mutex_lock(&kvm->slots_lock);
3595         if (kvm->arch.apic_access_page_done)
3596                 goto out;
3597         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3598                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3599         if (r)
3600                 goto out;
3601
3602         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3603         if (is_error_page(page)) {
3604                 r = -EFAULT;
3605                 goto out;
3606         }
3607
3608         /*
3609          * Do not pin the page in memory, so that memory hot-unplug
3610          * is able to migrate it.
3611          */
3612         put_page(page);
3613         kvm->arch.apic_access_page_done = true;
3614 out:
3615         mutex_unlock(&kvm->slots_lock);
3616         return r;
3617 }
3618
3619 int allocate_vpid(void)
3620 {
3621         int vpid;
3622
3623         if (!enable_vpid)
3624                 return 0;
3625         spin_lock(&vmx_vpid_lock);
3626         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3627         if (vpid < VMX_NR_VPIDS)
3628                 __set_bit(vpid, vmx_vpid_bitmap);
3629         else
3630                 vpid = 0;
3631         spin_unlock(&vmx_vpid_lock);
3632         return vpid;
3633 }
3634
3635 void free_vpid(int vpid)
3636 {
3637         if (!enable_vpid || vpid == 0)
3638                 return;
3639         spin_lock(&vmx_vpid_lock);
3640         __clear_bit(vpid, vmx_vpid_bitmap);
3641         spin_unlock(&vmx_vpid_lock);
3642 }
3643
3644 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3645                                                           u32 msr, int type)
3646 {
3647         int f = sizeof(unsigned long);
3648
3649         if (!cpu_has_vmx_msr_bitmap())
3650                 return;
3651
3652         if (static_branch_unlikely(&enable_evmcs))
3653                 evmcs_touch_msr_bitmap();
3654
3655         /*
3656          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3657          * have the write-low and read-high bitmap offsets the wrong way round.
3658          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3659          */
3660         if (msr <= 0x1fff) {
3661                 if (type & MSR_TYPE_R)
3662                         /* read-low */
3663                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3664
3665                 if (type & MSR_TYPE_W)
3666                         /* write-low */
3667                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3668
3669         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3670                 msr &= 0x1fff;
3671                 if (type & MSR_TYPE_R)
3672                         /* read-high */
3673                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3674
3675                 if (type & MSR_TYPE_W)
3676                         /* write-high */
3677                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3678
3679         }
3680 }
3681
3682 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3683                                                          u32 msr, int type)
3684 {
3685         int f = sizeof(unsigned long);
3686
3687         if (!cpu_has_vmx_msr_bitmap())
3688                 return;
3689
3690         if (static_branch_unlikely(&enable_evmcs))
3691                 evmcs_touch_msr_bitmap();
3692
3693         /*
3694          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3695          * have the write-low and read-high bitmap offsets the wrong way round.
3696          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3697          */
3698         if (msr <= 0x1fff) {
3699                 if (type & MSR_TYPE_R)
3700                         /* read-low */
3701                         __set_bit(msr, msr_bitmap + 0x000 / f);
3702
3703                 if (type & MSR_TYPE_W)
3704                         /* write-low */
3705                         __set_bit(msr, msr_bitmap + 0x800 / f);
3706
3707         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3708                 msr &= 0x1fff;
3709                 if (type & MSR_TYPE_R)
3710                         /* read-high */
3711                         __set_bit(msr, msr_bitmap + 0x400 / f);
3712
3713                 if (type & MSR_TYPE_W)
3714                         /* write-high */
3715                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3716
3717         }
3718 }
3719
3720 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3721                                                       u32 msr, int type, bool value)
3722 {
3723         if (value)
3724                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3725         else
3726                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3727 }
3728
3729 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3730 {
3731         u8 mode = 0;
3732
3733         if (cpu_has_secondary_exec_ctrls() &&
3734             (secondary_exec_controls_get(to_vmx(vcpu)) &
3735              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3736                 mode |= MSR_BITMAP_MODE_X2APIC;
3737                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3738                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3739         }
3740
3741         return mode;
3742 }
3743
3744 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3745                                          u8 mode)
3746 {
3747         int msr;
3748
3749         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3750                 unsigned word = msr / BITS_PER_LONG;
3751                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3752                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3753         }
3754
3755         if (mode & MSR_BITMAP_MODE_X2APIC) {
3756                 /*
3757                  * TPR reads and writes can be virtualized even if virtual interrupt
3758                  * delivery is not in use.
3759                  */
3760                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3761                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3762                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3763                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3764                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3765                 }
3766         }
3767 }
3768
3769 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3770 {
3771         struct vcpu_vmx *vmx = to_vmx(vcpu);
3772         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3773         u8 mode = vmx_msr_bitmap_mode(vcpu);
3774         u8 changed = mode ^ vmx->msr_bitmap_mode;
3775
3776         if (!changed)
3777                 return;
3778
3779         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3780                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3781
3782         vmx->msr_bitmap_mode = mode;
3783 }
3784
3785 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3786 {
3787         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3788         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3789         u32 i;
3790
3791         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3792                                                         MSR_TYPE_RW, flag);
3793         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3794                                                         MSR_TYPE_RW, flag);
3795         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3796                                                         MSR_TYPE_RW, flag);
3797         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3798                                                         MSR_TYPE_RW, flag);
3799         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3800                 vmx_set_intercept_for_msr(msr_bitmap,
3801                         MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3802                 vmx_set_intercept_for_msr(msr_bitmap,
3803                         MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3804         }
3805 }
3806
3807 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3808 {
3809         struct vcpu_vmx *vmx = to_vmx(vcpu);
3810         void *vapic_page;
3811         u32 vppr;
3812         int rvi;
3813
3814         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3815                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3816                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3817                 return false;
3818
3819         rvi = vmx_get_rvi();
3820
3821         vapic_page = vmx->nested.virtual_apic_map.hva;
3822         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3823
3824         return ((rvi & 0xf0) > (vppr & 0xf0));
3825 }
3826
3827 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3828                                                      bool nested)
3829 {
3830 #ifdef CONFIG_SMP
3831         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3832
3833         if (vcpu->mode == IN_GUEST_MODE) {
3834                 /*
3835                  * The vector of interrupt to be delivered to vcpu had
3836                  * been set in PIR before this function.
3837                  *
3838                  * Following cases will be reached in this block, and
3839                  * we always send a notification event in all cases as
3840                  * explained below.
3841                  *
3842                  * Case 1: vcpu keeps in non-root mode. Sending a
3843                  * notification event posts the interrupt to vcpu.
3844                  *
3845                  * Case 2: vcpu exits to root mode and is still
3846                  * runnable. PIR will be synced to vIRR before the
3847                  * next vcpu entry. Sending a notification event in
3848                  * this case has no effect, as vcpu is not in root
3849                  * mode.
3850                  *
3851                  * Case 3: vcpu exits to root mode and is blocked.
3852                  * vcpu_block() has already synced PIR to vIRR and
3853                  * never blocks vcpu if vIRR is not cleared. Therefore,
3854                  * a blocked vcpu here does not wait for any requested
3855                  * interrupts in PIR, and sending a notification event
3856                  * which has no effect is safe here.
3857                  */
3858
3859                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3860                 return true;
3861         }
3862 #endif
3863         return false;
3864 }
3865
3866 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3867                                                 int vector)
3868 {
3869         struct vcpu_vmx *vmx = to_vmx(vcpu);
3870
3871         if (is_guest_mode(vcpu) &&
3872             vector == vmx->nested.posted_intr_nv) {
3873                 /*
3874                  * If a posted intr is not recognized by hardware,
3875                  * we will accomplish it in the next vmentry.
3876                  */
3877                 vmx->nested.pi_pending = true;
3878                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3879                 /* the PIR and ON have been set by L1. */
3880                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3881                         kvm_vcpu_kick(vcpu);
3882                 return 0;
3883         }
3884         return -1;
3885 }
3886 /*
3887  * Send interrupt to vcpu via posted interrupt way.
3888  * 1. If target vcpu is running(non-root mode), send posted interrupt
3889  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3890  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3891  * interrupt from PIR in next vmentry.
3892  */
3893 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3894 {
3895         struct vcpu_vmx *vmx = to_vmx(vcpu);
3896         int r;
3897
3898         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3899         if (!r)
3900                 return 0;
3901
3902         if (!vcpu->arch.apicv_active)
3903                 return -1;
3904
3905         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3906                 return 0;
3907
3908         /* If a previous notification has sent the IPI, nothing to do.  */
3909         if (pi_test_and_set_on(&vmx->pi_desc))
3910                 return 0;
3911
3912         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3913                 kvm_vcpu_kick(vcpu);
3914
3915         return 0;
3916 }
3917
3918 /*
3919  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3920  * will not change in the lifetime of the guest.
3921  * Note that host-state that does change is set elsewhere. E.g., host-state
3922  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3923  */
3924 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3925 {
3926         u32 low32, high32;
3927         unsigned long tmpl;
3928         unsigned long cr0, cr3, cr4;
3929
3930         cr0 = read_cr0();
3931         WARN_ON(cr0 & X86_CR0_TS);
3932         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3933
3934         /*
3935          * Save the most likely value for this task's CR3 in the VMCS.
3936          * We can't use __get_current_cr3_fast() because we're not atomic.
3937          */
3938         cr3 = __read_cr3();
3939         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
3940         vmx->loaded_vmcs->host_state.cr3 = cr3;
3941
3942         /* Save the most likely value for this task's CR4 in the VMCS. */
3943         cr4 = cr4_read_shadow();
3944         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
3945         vmx->loaded_vmcs->host_state.cr4 = cr4;
3946
3947         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3948 #ifdef CONFIG_X86_64
3949         /*
3950          * Load null selectors, so we can avoid reloading them in
3951          * vmx_prepare_switch_to_host(), in case userspace uses
3952          * the null selectors too (the expected case).
3953          */
3954         vmcs_write16(HOST_DS_SELECTOR, 0);
3955         vmcs_write16(HOST_ES_SELECTOR, 0);
3956 #else
3957         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3958         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3959 #endif
3960         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3961         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3962
3963         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
3964
3965         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3966
3967         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3968         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3969         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3970         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3971
3972         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3973                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3974                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3975         }
3976
3977         if (cpu_has_load_ia32_efer())
3978                 vmcs_write64(HOST_IA32_EFER, host_efer);
3979 }
3980
3981 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3982 {
3983         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3984         if (enable_ept)
3985                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3986         if (is_guest_mode(&vmx->vcpu))
3987                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3988                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3989         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3990 }
3991
3992 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3993 {
3994         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3995
3996         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3997                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3998
3999         if (!enable_vnmi)
4000                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4001
4002         if (!enable_preemption_timer)
4003                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4004
4005         return pin_based_exec_ctrl;
4006 }
4007
4008 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4009 {
4010         struct vcpu_vmx *vmx = to_vmx(vcpu);
4011
4012         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4013         if (cpu_has_secondary_exec_ctrls()) {
4014                 if (kvm_vcpu_apicv_active(vcpu))
4015                         secondary_exec_controls_setbit(vmx,
4016                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4017                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4018                 else
4019                         secondary_exec_controls_clearbit(vmx,
4020                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4021                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4022         }
4023
4024         if (cpu_has_vmx_msr_bitmap())
4025                 vmx_update_msr_bitmap(vcpu);
4026 }
4027
4028 u32 vmx_exec_control(struct vcpu_vmx *vmx)
4029 {
4030         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4031
4032         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4033                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4034
4035         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4036                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4037 #ifdef CONFIG_X86_64
4038                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4039                                 CPU_BASED_CR8_LOAD_EXITING;
4040 #endif
4041         }
4042         if (!enable_ept)
4043                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4044                                 CPU_BASED_CR3_LOAD_EXITING  |
4045                                 CPU_BASED_INVLPG_EXITING;
4046         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4047                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4048                                 CPU_BASED_MONITOR_EXITING);
4049         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4050                 exec_control &= ~CPU_BASED_HLT_EXITING;
4051         return exec_control;
4052 }
4053
4054
4055 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4056 {
4057         struct kvm_vcpu *vcpu = &vmx->vcpu;
4058
4059         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4060
4061         if (vmx_pt_mode_is_system())
4062                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4063         if (!cpu_need_virtualize_apic_accesses(vcpu))
4064                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4065         if (vmx->vpid == 0)
4066                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4067         if (!enable_ept) {
4068                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4069                 enable_unrestricted_guest = 0;
4070         }
4071         if (!enable_unrestricted_guest)
4072                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4073         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4074                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4075         if (!kvm_vcpu_apicv_active(vcpu))
4076                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4077                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4078         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4079
4080         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4081          * in vmx_set_cr4.  */
4082         exec_control &= ~SECONDARY_EXEC_DESC;
4083
4084         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4085            (handle_vmptrld).
4086            We can NOT enable shadow_vmcs here because we don't have yet
4087            a current VMCS12
4088         */
4089         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4090
4091         if (!enable_pml)
4092                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4093
4094         if (vmx_xsaves_supported()) {
4095                 /* Exposing XSAVES only when XSAVE is exposed */
4096                 bool xsaves_enabled =
4097                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4098                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4099                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4100
4101                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4102
4103                 if (!xsaves_enabled)
4104                         exec_control &= ~SECONDARY_EXEC_XSAVES;
4105
4106                 if (nested) {
4107                         if (xsaves_enabled)
4108                                 vmx->nested.msrs.secondary_ctls_high |=
4109                                         SECONDARY_EXEC_XSAVES;
4110                         else
4111                                 vmx->nested.msrs.secondary_ctls_high &=
4112                                         ~SECONDARY_EXEC_XSAVES;
4113                 }
4114         }
4115
4116         if (cpu_has_vmx_rdtscp()) {
4117                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4118                 if (!rdtscp_enabled)
4119                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
4120
4121                 if (nested) {
4122                         if (rdtscp_enabled)
4123                                 vmx->nested.msrs.secondary_ctls_high |=
4124                                         SECONDARY_EXEC_RDTSCP;
4125                         else
4126                                 vmx->nested.msrs.secondary_ctls_high &=
4127                                         ~SECONDARY_EXEC_RDTSCP;
4128                 }
4129         }
4130
4131         if (cpu_has_vmx_invpcid()) {
4132                 /* Exposing INVPCID only when PCID is exposed */
4133                 bool invpcid_enabled =
4134                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4135                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4136
4137                 if (!invpcid_enabled) {
4138                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4139                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4140                 }
4141
4142                 if (nested) {
4143                         if (invpcid_enabled)
4144                                 vmx->nested.msrs.secondary_ctls_high |=
4145                                         SECONDARY_EXEC_ENABLE_INVPCID;
4146                         else
4147                                 vmx->nested.msrs.secondary_ctls_high &=
4148                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
4149                 }
4150         }
4151
4152         if (vmx_rdrand_supported()) {
4153                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4154                 if (rdrand_enabled)
4155                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4156
4157                 if (nested) {
4158                         if (rdrand_enabled)
4159                                 vmx->nested.msrs.secondary_ctls_high |=
4160                                         SECONDARY_EXEC_RDRAND_EXITING;
4161                         else
4162                                 vmx->nested.msrs.secondary_ctls_high &=
4163                                         ~SECONDARY_EXEC_RDRAND_EXITING;
4164                 }
4165         }
4166
4167         if (vmx_rdseed_supported()) {
4168                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4169                 if (rdseed_enabled)
4170                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4171
4172                 if (nested) {
4173                         if (rdseed_enabled)
4174                                 vmx->nested.msrs.secondary_ctls_high |=
4175                                         SECONDARY_EXEC_RDSEED_EXITING;
4176                         else
4177                                 vmx->nested.msrs.secondary_ctls_high &=
4178                                         ~SECONDARY_EXEC_RDSEED_EXITING;
4179                 }
4180         }
4181
4182         if (vmx_waitpkg_supported()) {
4183                 bool waitpkg_enabled =
4184                         guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4185
4186                 if (!waitpkg_enabled)
4187                         exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4188
4189                 if (nested) {
4190                         if (waitpkg_enabled)
4191                                 vmx->nested.msrs.secondary_ctls_high |=
4192                                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4193                         else
4194                                 vmx->nested.msrs.secondary_ctls_high &=
4195                                         ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4196                 }
4197         }
4198
4199         vmx->secondary_exec_control = exec_control;
4200 }
4201
4202 static void ept_set_mmio_spte_mask(void)
4203 {
4204         /*
4205          * EPT Misconfigurations can be generated if the value of bits 2:0
4206          * of an EPT paging-structure entry is 110b (write/execute).
4207          */
4208         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4209                                    VMX_EPT_MISCONFIG_WX_VALUE, 0);
4210 }
4211
4212 #define VMX_XSS_EXIT_BITMAP 0
4213
4214 /*
4215  * Noting that the initialization of Guest-state Area of VMCS is in
4216  * vmx_vcpu_reset().
4217  */
4218 static void init_vmcs(struct vcpu_vmx *vmx)
4219 {
4220         if (nested)
4221                 nested_vmx_set_vmcs_shadowing_bitmap();
4222
4223         if (cpu_has_vmx_msr_bitmap())
4224                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4225
4226         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4227
4228         /* Control */
4229         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4230
4231         exec_controls_set(vmx, vmx_exec_control(vmx));
4232
4233         if (cpu_has_secondary_exec_ctrls()) {
4234                 vmx_compute_secondary_exec_control(vmx);
4235                 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4236         }
4237
4238         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4239                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4240                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4241                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4242                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4243
4244                 vmcs_write16(GUEST_INTR_STATUS, 0);
4245
4246                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4247                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4248         }
4249
4250         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4251                 vmcs_write32(PLE_GAP, ple_gap);
4252                 vmx->ple_window = ple_window;
4253                 vmx->ple_window_dirty = true;
4254         }
4255
4256         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4257         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4258         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4259
4260         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4261         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4262         vmx_set_constant_host_state(vmx);
4263         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4264         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4265
4266         if (cpu_has_vmx_vmfunc())
4267                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4268
4269         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4270         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4271         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4272         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4273         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4274
4275         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4276                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4277
4278         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4279
4280         /* 22.2.1, 20.8.1 */
4281         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4282
4283         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4284         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4285
4286         set_cr4_guest_host_mask(vmx);
4287
4288         if (vmx->vpid != 0)
4289                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4290
4291         if (vmx_xsaves_supported())
4292                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4293
4294         if (enable_pml) {
4295                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4296                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4297         }
4298
4299         if (cpu_has_vmx_encls_vmexit())
4300                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4301
4302         if (vmx_pt_mode_is_host_guest()) {
4303                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4304                 /* Bit[6~0] are forced to 1, writes are ignored. */
4305                 vmx->pt_desc.guest.output_mask = 0x7F;
4306                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4307         }
4308 }
4309
4310 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4311 {
4312         struct vcpu_vmx *vmx = to_vmx(vcpu);
4313         struct msr_data apic_base_msr;
4314         u64 cr0;
4315
4316         vmx->rmode.vm86_active = 0;
4317         vmx->spec_ctrl = 0;
4318
4319         vmx->msr_ia32_umwait_control = 0;
4320
4321         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4322         vmx->hv_deadline_tsc = -1;
4323         kvm_set_cr8(vcpu, 0);
4324
4325         if (!init_event) {
4326                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4327                                      MSR_IA32_APICBASE_ENABLE;
4328                 if (kvm_vcpu_is_reset_bsp(vcpu))
4329                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4330                 apic_base_msr.host_initiated = true;
4331                 kvm_set_apic_base(vcpu, &apic_base_msr);
4332         }
4333
4334         vmx_segment_cache_clear(vmx);
4335
4336         seg_setup(VCPU_SREG_CS);
4337         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4338         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4339
4340         seg_setup(VCPU_SREG_DS);
4341         seg_setup(VCPU_SREG_ES);
4342         seg_setup(VCPU_SREG_FS);
4343         seg_setup(VCPU_SREG_GS);
4344         seg_setup(VCPU_SREG_SS);
4345
4346         vmcs_write16(GUEST_TR_SELECTOR, 0);
4347         vmcs_writel(GUEST_TR_BASE, 0);
4348         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4349         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4350
4351         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4352         vmcs_writel(GUEST_LDTR_BASE, 0);
4353         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4354         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4355
4356         if (!init_event) {
4357                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4358                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4359                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4360                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4361         }
4362
4363         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4364         kvm_rip_write(vcpu, 0xfff0);
4365
4366         vmcs_writel(GUEST_GDTR_BASE, 0);
4367         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4368
4369         vmcs_writel(GUEST_IDTR_BASE, 0);
4370         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4371
4372         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4373         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4374         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4375         if (kvm_mpx_supported())
4376                 vmcs_write64(GUEST_BNDCFGS, 0);
4377
4378         setup_msrs(vmx);
4379
4380         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4381
4382         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4383                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4384                 if (cpu_need_tpr_shadow(vcpu))
4385                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4386                                      __pa(vcpu->arch.apic->regs));
4387                 vmcs_write32(TPR_THRESHOLD, 0);
4388         }
4389
4390         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4391
4392         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4393         vmx->vcpu.arch.cr0 = cr0;
4394         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4395         vmx_set_cr4(vcpu, 0);
4396         vmx_set_efer(vcpu, 0);
4397
4398         update_exception_bitmap(vcpu);
4399
4400         vpid_sync_context(vmx->vpid);
4401         if (init_event)
4402                 vmx_clear_hlt(vcpu);
4403 }
4404
4405 static void enable_irq_window(struct kvm_vcpu *vcpu)
4406 {
4407         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4408 }
4409
4410 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4411 {
4412         if (!enable_vnmi ||
4413             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4414                 enable_irq_window(vcpu);
4415                 return;
4416         }
4417
4418         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4419 }
4420
4421 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4422 {
4423         struct vcpu_vmx *vmx = to_vmx(vcpu);
4424         uint32_t intr;
4425         int irq = vcpu->arch.interrupt.nr;
4426
4427         trace_kvm_inj_virq(irq);
4428
4429         ++vcpu->stat.irq_injections;
4430         if (vmx->rmode.vm86_active) {
4431                 int inc_eip = 0;
4432                 if (vcpu->arch.interrupt.soft)
4433                         inc_eip = vcpu->arch.event_exit_inst_len;
4434                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4435                 return;
4436         }
4437         intr = irq | INTR_INFO_VALID_MASK;
4438         if (vcpu->arch.interrupt.soft) {
4439                 intr |= INTR_TYPE_SOFT_INTR;
4440                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4441                              vmx->vcpu.arch.event_exit_inst_len);
4442         } else
4443                 intr |= INTR_TYPE_EXT_INTR;
4444         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4445
4446         vmx_clear_hlt(vcpu);
4447 }
4448
4449 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4450 {
4451         struct vcpu_vmx *vmx = to_vmx(vcpu);
4452
4453         if (!enable_vnmi) {
4454                 /*
4455                  * Tracking the NMI-blocked state in software is built upon
4456                  * finding the next open IRQ window. This, in turn, depends on
4457                  * well-behaving guests: They have to keep IRQs disabled at
4458                  * least as long as the NMI handler runs. Otherwise we may
4459                  * cause NMI nesting, maybe breaking the guest. But as this is
4460                  * highly unlikely, we can live with the residual risk.
4461                  */
4462                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4463                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4464         }
4465
4466         ++vcpu->stat.nmi_injections;
4467         vmx->loaded_vmcs->nmi_known_unmasked = false;
4468
4469         if (vmx->rmode.vm86_active) {
4470                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4471                 return;
4472         }
4473
4474         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4475                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4476
4477         vmx_clear_hlt(vcpu);
4478 }
4479
4480 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4481 {
4482         struct vcpu_vmx *vmx = to_vmx(vcpu);
4483         bool masked;
4484
4485         if (!enable_vnmi)
4486                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4487         if (vmx->loaded_vmcs->nmi_known_unmasked)
4488                 return false;
4489         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4490         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4491         return masked;
4492 }
4493
4494 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4495 {
4496         struct vcpu_vmx *vmx = to_vmx(vcpu);
4497
4498         if (!enable_vnmi) {
4499                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4500                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4501                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4502                 }
4503         } else {
4504                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4505                 if (masked)
4506                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4507                                       GUEST_INTR_STATE_NMI);
4508                 else
4509                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4510                                         GUEST_INTR_STATE_NMI);
4511         }
4512 }
4513
4514 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4515 {
4516         if (to_vmx(vcpu)->nested.nested_run_pending)
4517                 return 0;
4518
4519         if (!enable_vnmi &&
4520             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4521                 return 0;
4522
4523         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4524                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4525                    | GUEST_INTR_STATE_NMI));
4526 }
4527
4528 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4529 {
4530         if (to_vmx(vcpu)->nested.nested_run_pending)
4531                 return false;
4532
4533         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4534                 return true;
4535
4536         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4537                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4538                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4539 }
4540
4541 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4542 {
4543         int ret;
4544
4545         if (enable_unrestricted_guest)
4546                 return 0;
4547
4548         mutex_lock(&kvm->slots_lock);
4549         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4550                                       PAGE_SIZE * 3);
4551         mutex_unlock(&kvm->slots_lock);
4552
4553         if (ret)
4554                 return ret;
4555         to_kvm_vmx(kvm)->tss_addr = addr;
4556         return init_rmode_tss(kvm);
4557 }
4558
4559 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4560 {
4561         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4562         return 0;
4563 }
4564
4565 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4566 {
4567         switch (vec) {
4568         case BP_VECTOR:
4569                 /*
4570                  * Update instruction length as we may reinject the exception
4571                  * from user space while in guest debugging mode.
4572                  */
4573                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4574                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4575                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4576                         return false;
4577                 /* fall through */
4578         case DB_VECTOR:
4579                 if (vcpu->guest_debug &
4580                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4581                         return false;
4582                 /* fall through */
4583         case DE_VECTOR:
4584         case OF_VECTOR:
4585         case BR_VECTOR:
4586         case UD_VECTOR:
4587         case DF_VECTOR:
4588         case SS_VECTOR:
4589         case GP_VECTOR:
4590         case MF_VECTOR:
4591                 return true;
4592         }
4593         return false;
4594 }
4595
4596 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4597                                   int vec, u32 err_code)
4598 {
4599         /*
4600          * Instruction with address size override prefix opcode 0x67
4601          * Cause the #SS fault with 0 error code in VM86 mode.
4602          */
4603         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4604                 if (kvm_emulate_instruction(vcpu, 0)) {
4605                         if (vcpu->arch.halt_request) {
4606                                 vcpu->arch.halt_request = 0;
4607                                 return kvm_vcpu_halt(vcpu);
4608                         }
4609                         return 1;
4610                 }
4611                 return 0;
4612         }
4613
4614         /*
4615          * Forward all other exceptions that are valid in real mode.
4616          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4617          *        the required debugging infrastructure rework.
4618          */
4619         kvm_queue_exception(vcpu, vec);
4620         return 1;
4621 }
4622
4623 /*
4624  * Trigger machine check on the host. We assume all the MSRs are already set up
4625  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4626  * We pass a fake environment to the machine check handler because we want
4627  * the guest to be always treated like user space, no matter what context
4628  * it used internally.
4629  */
4630 static void kvm_machine_check(void)
4631 {
4632 #if defined(CONFIG_X86_MCE)
4633         struct pt_regs regs = {
4634                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4635                 .flags = X86_EFLAGS_IF,
4636         };
4637
4638         do_machine_check(&regs, 0);
4639 #endif
4640 }
4641
4642 static int handle_machine_check(struct kvm_vcpu *vcpu)
4643 {
4644         /* handled by vmx_vcpu_run() */
4645         return 1;
4646 }
4647
4648 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4649 {
4650         struct vcpu_vmx *vmx = to_vmx(vcpu);
4651         struct kvm_run *kvm_run = vcpu->run;
4652         u32 intr_info, ex_no, error_code;
4653         unsigned long cr2, rip, dr6;
4654         u32 vect_info;
4655
4656         vect_info = vmx->idt_vectoring_info;
4657         intr_info = vmx->exit_intr_info;
4658
4659         if (is_machine_check(intr_info) || is_nmi(intr_info))
4660                 return 1; /* handled by handle_exception_nmi_irqoff() */
4661
4662         if (is_invalid_opcode(intr_info))
4663                 return handle_ud(vcpu);
4664
4665         error_code = 0;
4666         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4667                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4668
4669         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4670                 WARN_ON_ONCE(!enable_vmware_backdoor);
4671
4672                 /*
4673                  * VMware backdoor emulation on #GP interception only handles
4674                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4675                  * error code on #GP.
4676                  */
4677                 if (error_code) {
4678                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4679                         return 1;
4680                 }
4681                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4682         }
4683
4684         /*
4685          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4686          * MMIO, it is better to report an internal error.
4687          * See the comments in vmx_handle_exit.
4688          */
4689         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4690             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4691                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4692                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4693                 vcpu->run->internal.ndata = 3;
4694                 vcpu->run->internal.data[0] = vect_info;
4695                 vcpu->run->internal.data[1] = intr_info;
4696                 vcpu->run->internal.data[2] = error_code;
4697                 return 0;
4698         }
4699
4700         if (is_page_fault(intr_info)) {
4701                 cr2 = vmx_get_exit_qual(vcpu);
4702                 /* EPT won't cause page fault directly */
4703                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4704                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4705         }
4706
4707         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4708
4709         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4710                 return handle_rmode_exception(vcpu, ex_no, error_code);
4711
4712         switch (ex_no) {
4713         case AC_VECTOR:
4714                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4715                 return 1;
4716         case DB_VECTOR:
4717                 dr6 = vmx_get_exit_qual(vcpu);
4718                 if (!(vcpu->guest_debug &
4719                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4720                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4721                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4722                         if (is_icebp(intr_info))
4723                                 WARN_ON(!skip_emulated_instruction(vcpu));
4724
4725                         kvm_queue_exception(vcpu, DB_VECTOR);
4726                         return 1;
4727                 }
4728                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4729                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4730                 /* fall through */
4731         case BP_VECTOR:
4732                 /*
4733                  * Update instruction length as we may reinject #BP from
4734                  * user space while in guest debugging mode. Reading it for
4735                  * #DB as well causes no harm, it is not used in that case.
4736                  */
4737                 vmx->vcpu.arch.event_exit_inst_len =
4738                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4739                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4740                 rip = kvm_rip_read(vcpu);
4741                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4742                 kvm_run->debug.arch.exception = ex_no;
4743                 break;
4744         default:
4745                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4746                 kvm_run->ex.exception = ex_no;
4747                 kvm_run->ex.error_code = error_code;
4748                 break;
4749         }
4750         return 0;
4751 }
4752
4753 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4754 {
4755         ++vcpu->stat.irq_exits;
4756         return 1;
4757 }
4758
4759 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4760 {
4761         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4762         vcpu->mmio_needed = 0;
4763         return 0;
4764 }
4765
4766 static int handle_io(struct kvm_vcpu *vcpu)
4767 {
4768         unsigned long exit_qualification;
4769         int size, in, string;
4770         unsigned port;
4771
4772         exit_qualification = vmx_get_exit_qual(vcpu);
4773         string = (exit_qualification & 16) != 0;
4774
4775         ++vcpu->stat.io_exits;
4776
4777         if (string)
4778                 return kvm_emulate_instruction(vcpu, 0);
4779
4780         port = exit_qualification >> 16;
4781         size = (exit_qualification & 7) + 1;
4782         in = (exit_qualification & 8) != 0;
4783
4784         return kvm_fast_pio(vcpu, size, port, in);
4785 }
4786
4787 static void
4788 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4789 {
4790         /*
4791          * Patch in the VMCALL instruction:
4792          */
4793         hypercall[0] = 0x0f;
4794         hypercall[1] = 0x01;
4795         hypercall[2] = 0xc1;
4796 }
4797
4798 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4799 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4800 {
4801         if (is_guest_mode(vcpu)) {
4802                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4803                 unsigned long orig_val = val;
4804
4805                 /*
4806                  * We get here when L2 changed cr0 in a way that did not change
4807                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4808                  * but did change L0 shadowed bits. So we first calculate the
4809                  * effective cr0 value that L1 would like to write into the
4810                  * hardware. It consists of the L2-owned bits from the new
4811                  * value combined with the L1-owned bits from L1's guest_cr0.
4812                  */
4813                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4814                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4815
4816                 if (!nested_guest_cr0_valid(vcpu, val))
4817                         return 1;
4818
4819                 if (kvm_set_cr0(vcpu, val))
4820                         return 1;
4821                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4822                 return 0;
4823         } else {
4824                 if (to_vmx(vcpu)->nested.vmxon &&
4825                     !nested_host_cr0_valid(vcpu, val))
4826                         return 1;
4827
4828                 return kvm_set_cr0(vcpu, val);
4829         }
4830 }
4831
4832 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4833 {
4834         if (is_guest_mode(vcpu)) {
4835                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4836                 unsigned long orig_val = val;
4837
4838                 /* analogously to handle_set_cr0 */
4839                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4840                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4841                 if (kvm_set_cr4(vcpu, val))
4842                         return 1;
4843                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4844                 return 0;
4845         } else
4846                 return kvm_set_cr4(vcpu, val);
4847 }
4848
4849 static int handle_desc(struct kvm_vcpu *vcpu)
4850 {
4851         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4852         return kvm_emulate_instruction(vcpu, 0);
4853 }
4854
4855 static int handle_cr(struct kvm_vcpu *vcpu)
4856 {
4857         unsigned long exit_qualification, val;
4858         int cr;
4859         int reg;
4860         int err;
4861         int ret;
4862
4863         exit_qualification = vmx_get_exit_qual(vcpu);
4864         cr = exit_qualification & 15;
4865         reg = (exit_qualification >> 8) & 15;
4866         switch ((exit_qualification >> 4) & 3) {
4867         case 0: /* mov to cr */
4868                 val = kvm_register_readl(vcpu, reg);
4869                 trace_kvm_cr_write(cr, val);
4870                 switch (cr) {
4871                 case 0:
4872                         err = handle_set_cr0(vcpu, val);
4873                         return kvm_complete_insn_gp(vcpu, err);
4874                 case 3:
4875                         WARN_ON_ONCE(enable_unrestricted_guest);
4876                         err = kvm_set_cr3(vcpu, val);
4877                         return kvm_complete_insn_gp(vcpu, err);
4878                 case 4:
4879                         err = handle_set_cr4(vcpu, val);
4880                         return kvm_complete_insn_gp(vcpu, err);
4881                 case 8: {
4882                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4883                                 u8 cr8 = (u8)val;
4884                                 err = kvm_set_cr8(vcpu, cr8);
4885                                 ret = kvm_complete_insn_gp(vcpu, err);
4886                                 if (lapic_in_kernel(vcpu))
4887                                         return ret;
4888                                 if (cr8_prev <= cr8)
4889                                         return ret;
4890                                 /*
4891                                  * TODO: we might be squashing a
4892                                  * KVM_GUESTDBG_SINGLESTEP-triggered
4893                                  * KVM_EXIT_DEBUG here.
4894                                  */
4895                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4896                                 return 0;
4897                         }
4898                 }
4899                 break;
4900         case 2: /* clts */
4901                 WARN_ONCE(1, "Guest should always own CR0.TS");
4902                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4903                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4904                 return kvm_skip_emulated_instruction(vcpu);
4905         case 1: /*mov from cr*/
4906                 switch (cr) {
4907                 case 3:
4908                         WARN_ON_ONCE(enable_unrestricted_guest);
4909                         val = kvm_read_cr3(vcpu);
4910                         kvm_register_write(vcpu, reg, val);
4911                         trace_kvm_cr_read(cr, val);
4912                         return kvm_skip_emulated_instruction(vcpu);
4913                 case 8:
4914                         val = kvm_get_cr8(vcpu);
4915                         kvm_register_write(vcpu, reg, val);
4916                         trace_kvm_cr_read(cr, val);
4917                         return kvm_skip_emulated_instruction(vcpu);
4918                 }
4919                 break;
4920         case 3: /* lmsw */
4921                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4922                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4923                 kvm_lmsw(vcpu, val);
4924
4925                 return kvm_skip_emulated_instruction(vcpu);
4926         default:
4927                 break;
4928         }
4929         vcpu->run->exit_reason = 0;
4930         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4931                (int)(exit_qualification >> 4) & 3, cr);
4932         return 0;
4933 }
4934
4935 static int handle_dr(struct kvm_vcpu *vcpu)
4936 {
4937         unsigned long exit_qualification;
4938         int dr, dr7, reg;
4939
4940         exit_qualification = vmx_get_exit_qual(vcpu);
4941         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4942
4943         /* First, if DR does not exist, trigger UD */
4944         if (!kvm_require_dr(vcpu, dr))
4945                 return 1;
4946
4947         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4948         if (!kvm_require_cpl(vcpu, 0))
4949                 return 1;
4950         dr7 = vmcs_readl(GUEST_DR7);
4951         if (dr7 & DR7_GD) {
4952                 /*
4953                  * As the vm-exit takes precedence over the debug trap, we
4954                  * need to emulate the latter, either for the host or the
4955                  * guest debugging itself.
4956                  */
4957                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4958                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4959                         vcpu->run->debug.arch.dr7 = dr7;
4960                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4961                         vcpu->run->debug.arch.exception = DB_VECTOR;
4962                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4963                         return 0;
4964                 } else {
4965                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4966                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4967                         kvm_queue_exception(vcpu, DB_VECTOR);
4968                         return 1;
4969                 }
4970         }
4971
4972         if (vcpu->guest_debug == 0) {
4973                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4974
4975                 /*
4976                  * No more DR vmexits; force a reload of the debug registers
4977                  * and reenter on this instruction.  The next vmexit will
4978                  * retrieve the full state of the debug registers.
4979                  */
4980                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4981                 return 1;
4982         }
4983
4984         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4985         if (exit_qualification & TYPE_MOV_FROM_DR) {
4986                 unsigned long val;
4987
4988                 if (kvm_get_dr(vcpu, dr, &val))
4989                         return 1;
4990                 kvm_register_write(vcpu, reg, val);
4991         } else
4992                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4993                         return 1;
4994
4995         return kvm_skip_emulated_instruction(vcpu);
4996 }
4997
4998 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4999 {
5000         return vcpu->arch.dr6;
5001 }
5002
5003 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5004 {
5005 }
5006
5007 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5008 {
5009         get_debugreg(vcpu->arch.db[0], 0);
5010         get_debugreg(vcpu->arch.db[1], 1);
5011         get_debugreg(vcpu->arch.db[2], 2);
5012         get_debugreg(vcpu->arch.db[3], 3);
5013         get_debugreg(vcpu->arch.dr6, 6);
5014         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5015
5016         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5017         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5018 }
5019
5020 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5021 {
5022         vmcs_writel(GUEST_DR7, val);
5023 }
5024
5025 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5026 {
5027         kvm_apic_update_ppr(vcpu);
5028         return 1;
5029 }
5030
5031 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5032 {
5033         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5034
5035         kvm_make_request(KVM_REQ_EVENT, vcpu);
5036
5037         ++vcpu->stat.irq_window_exits;
5038         return 1;
5039 }
5040
5041 static int handle_vmcall(struct kvm_vcpu *vcpu)
5042 {
5043         return kvm_emulate_hypercall(vcpu);
5044 }
5045
5046 static int handle_invd(struct kvm_vcpu *vcpu)
5047 {
5048         return kvm_emulate_instruction(vcpu, 0);
5049 }
5050
5051 static int handle_invlpg(struct kvm_vcpu *vcpu)
5052 {
5053         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5054
5055         kvm_mmu_invlpg(vcpu, exit_qualification);
5056         return kvm_skip_emulated_instruction(vcpu);
5057 }
5058
5059 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5060 {
5061         int err;
5062
5063         err = kvm_rdpmc(vcpu);
5064         return kvm_complete_insn_gp(vcpu, err);
5065 }
5066
5067 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5068 {
5069         return kvm_emulate_wbinvd(vcpu);
5070 }
5071
5072 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5073 {
5074         u64 new_bv = kvm_read_edx_eax(vcpu);
5075         u32 index = kvm_rcx_read(vcpu);
5076
5077         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5078                 return kvm_skip_emulated_instruction(vcpu);
5079         return 1;
5080 }
5081
5082 static int handle_apic_access(struct kvm_vcpu *vcpu)
5083 {
5084         if (likely(fasteoi)) {
5085                 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5086                 int access_type, offset;
5087
5088                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5089                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5090                 /*
5091                  * Sane guest uses MOV to write EOI, with written value
5092                  * not cared. So make a short-circuit here by avoiding
5093                  * heavy instruction emulation.
5094                  */
5095                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5096                     (offset == APIC_EOI)) {
5097                         kvm_lapic_set_eoi(vcpu);
5098                         return kvm_skip_emulated_instruction(vcpu);
5099                 }
5100         }
5101         return kvm_emulate_instruction(vcpu, 0);
5102 }
5103
5104 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5105 {
5106         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5107         int vector = exit_qualification & 0xff;
5108
5109         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5110         kvm_apic_set_eoi_accelerated(vcpu, vector);
5111         return 1;
5112 }
5113
5114 static int handle_apic_write(struct kvm_vcpu *vcpu)
5115 {
5116         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5117         u32 offset = exit_qualification & 0xfff;
5118
5119         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5120         kvm_apic_write_nodecode(vcpu, offset);
5121         return 1;
5122 }
5123
5124 static int handle_task_switch(struct kvm_vcpu *vcpu)
5125 {
5126         struct vcpu_vmx *vmx = to_vmx(vcpu);
5127         unsigned long exit_qualification;
5128         bool has_error_code = false;
5129         u32 error_code = 0;
5130         u16 tss_selector;
5131         int reason, type, idt_v, idt_index;
5132
5133         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5134         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5135         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5136
5137         exit_qualification = vmx_get_exit_qual(vcpu);
5138
5139         reason = (u32)exit_qualification >> 30;
5140         if (reason == TASK_SWITCH_GATE && idt_v) {
5141                 switch (type) {
5142                 case INTR_TYPE_NMI_INTR:
5143                         vcpu->arch.nmi_injected = false;
5144                         vmx_set_nmi_mask(vcpu, true);
5145                         break;
5146                 case INTR_TYPE_EXT_INTR:
5147                 case INTR_TYPE_SOFT_INTR:
5148                         kvm_clear_interrupt_queue(vcpu);
5149                         break;
5150                 case INTR_TYPE_HARD_EXCEPTION:
5151                         if (vmx->idt_vectoring_info &
5152                             VECTORING_INFO_DELIVER_CODE_MASK) {
5153                                 has_error_code = true;
5154                                 error_code =
5155                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5156                         }
5157                         /* fall through */
5158                 case INTR_TYPE_SOFT_EXCEPTION:
5159                         kvm_clear_exception_queue(vcpu);
5160                         break;
5161                 default:
5162                         break;
5163                 }
5164         }
5165         tss_selector = exit_qualification;
5166
5167         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5168                        type != INTR_TYPE_EXT_INTR &&
5169                        type != INTR_TYPE_NMI_INTR))
5170                 WARN_ON(!skip_emulated_instruction(vcpu));
5171
5172         /*
5173          * TODO: What about debug traps on tss switch?
5174          *       Are we supposed to inject them and update dr6?
5175          */
5176         return kvm_task_switch(vcpu, tss_selector,
5177                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5178                                reason, has_error_code, error_code);
5179 }
5180
5181 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5182 {
5183         unsigned long exit_qualification;
5184         gpa_t gpa;
5185         u64 error_code;
5186
5187         exit_qualification = vmx_get_exit_qual(vcpu);
5188
5189         /*
5190          * EPT violation happened while executing iret from NMI,
5191          * "blocked by NMI" bit has to be set before next VM entry.
5192          * There are errata that may cause this bit to not be set:
5193          * AAK134, BY25.
5194          */
5195         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5196                         enable_vnmi &&
5197                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5198                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5199
5200         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5201         trace_kvm_page_fault(gpa, exit_qualification);
5202
5203         /* Is it a read fault? */
5204         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5205                      ? PFERR_USER_MASK : 0;
5206         /* Is it a write fault? */
5207         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5208                       ? PFERR_WRITE_MASK : 0;
5209         /* Is it a fetch fault? */
5210         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5211                       ? PFERR_FETCH_MASK : 0;
5212         /* ept page table entry is present? */
5213         error_code |= (exit_qualification &
5214                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5215                         EPT_VIOLATION_EXECUTABLE))
5216                       ? PFERR_PRESENT_MASK : 0;
5217
5218         error_code |= (exit_qualification & 0x100) != 0 ?
5219                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5220
5221         vcpu->arch.exit_qualification = exit_qualification;
5222         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5223 }
5224
5225 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5226 {
5227         gpa_t gpa;
5228
5229         /*
5230          * A nested guest cannot optimize MMIO vmexits, because we have an
5231          * nGPA here instead of the required GPA.
5232          */
5233         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5234         if (!is_guest_mode(vcpu) &&
5235             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5236                 trace_kvm_fast_mmio(gpa);
5237                 return kvm_skip_emulated_instruction(vcpu);
5238         }
5239
5240         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5241 }
5242
5243 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5244 {
5245         WARN_ON_ONCE(!enable_vnmi);
5246         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5247         ++vcpu->stat.nmi_window_exits;
5248         kvm_make_request(KVM_REQ_EVENT, vcpu);
5249
5250         return 1;
5251 }
5252
5253 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5254 {
5255         struct vcpu_vmx *vmx = to_vmx(vcpu);
5256         bool intr_window_requested;
5257         unsigned count = 130;
5258
5259         /*
5260          * We should never reach the point where we are emulating L2
5261          * due to invalid guest state as that means we incorrectly
5262          * allowed a nested VMEntry with an invalid vmcs12.
5263          */
5264         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5265
5266         intr_window_requested = exec_controls_get(vmx) &
5267                                 CPU_BASED_INTR_WINDOW_EXITING;
5268
5269         while (vmx->emulation_required && count-- != 0) {
5270                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5271                         return handle_interrupt_window(&vmx->vcpu);
5272
5273                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5274                         return 1;
5275
5276                 if (!kvm_emulate_instruction(vcpu, 0))
5277                         return 0;
5278
5279                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5280                     vcpu->arch.exception.pending) {
5281                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5282                         vcpu->run->internal.suberror =
5283                                                 KVM_INTERNAL_ERROR_EMULATION;
5284                         vcpu->run->internal.ndata = 0;
5285                         return 0;
5286                 }
5287
5288                 if (vcpu->arch.halt_request) {
5289                         vcpu->arch.halt_request = 0;
5290                         return kvm_vcpu_halt(vcpu);
5291                 }
5292
5293                 /*
5294                  * Note, return 1 and not 0, vcpu_run() is responsible for
5295                  * morphing the pending signal into the proper return code.
5296                  */
5297                 if (signal_pending(current))
5298                         return 1;
5299
5300                 if (need_resched())
5301                         schedule();
5302         }
5303
5304         return 1;
5305 }
5306
5307 static void grow_ple_window(struct kvm_vcpu *vcpu)
5308 {
5309         struct vcpu_vmx *vmx = to_vmx(vcpu);
5310         unsigned int old = vmx->ple_window;
5311
5312         vmx->ple_window = __grow_ple_window(old, ple_window,
5313                                             ple_window_grow,
5314                                             ple_window_max);
5315
5316         if (vmx->ple_window != old) {
5317                 vmx->ple_window_dirty = true;
5318                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5319                                             vmx->ple_window, old);
5320         }
5321 }
5322
5323 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5324 {
5325         struct vcpu_vmx *vmx = to_vmx(vcpu);
5326         unsigned int old = vmx->ple_window;
5327
5328         vmx->ple_window = __shrink_ple_window(old, ple_window,
5329                                               ple_window_shrink,
5330                                               ple_window);
5331
5332         if (vmx->ple_window != old) {
5333                 vmx->ple_window_dirty = true;
5334                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5335                                             vmx->ple_window, old);
5336         }
5337 }
5338
5339 /*
5340  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5341  */
5342 static void wakeup_handler(void)
5343 {
5344         struct kvm_vcpu *vcpu;
5345         int cpu = smp_processor_id();
5346
5347         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5348         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5349                         blocked_vcpu_list) {
5350                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5351
5352                 if (pi_test_on(pi_desc) == 1)
5353                         kvm_vcpu_kick(vcpu);
5354         }
5355         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5356 }
5357
5358 static void vmx_enable_tdp(void)
5359 {
5360         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5361                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5362                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5363                 0ull, VMX_EPT_EXECUTABLE_MASK,
5364                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5365                 VMX_EPT_RWX_MASK, 0ull);
5366
5367         ept_set_mmio_spte_mask();
5368 }
5369
5370 /*
5371  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5372  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5373  */
5374 static int handle_pause(struct kvm_vcpu *vcpu)
5375 {
5376         if (!kvm_pause_in_guest(vcpu->kvm))
5377                 grow_ple_window(vcpu);
5378
5379         /*
5380          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5381          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5382          * never set PAUSE_EXITING and just set PLE if supported,
5383          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5384          */
5385         kvm_vcpu_on_spin(vcpu, true);
5386         return kvm_skip_emulated_instruction(vcpu);
5387 }
5388
5389 static int handle_nop(struct kvm_vcpu *vcpu)
5390 {
5391         return kvm_skip_emulated_instruction(vcpu);
5392 }
5393
5394 static int handle_mwait(struct kvm_vcpu *vcpu)
5395 {
5396         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5397         return handle_nop(vcpu);
5398 }
5399
5400 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5401 {
5402         kvm_queue_exception(vcpu, UD_VECTOR);
5403         return 1;
5404 }
5405
5406 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5407 {
5408         return 1;
5409 }
5410
5411 static int handle_monitor(struct kvm_vcpu *vcpu)
5412 {
5413         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5414         return handle_nop(vcpu);
5415 }
5416
5417 static int handle_invpcid(struct kvm_vcpu *vcpu)
5418 {
5419         u32 vmx_instruction_info;
5420         unsigned long type;
5421         bool pcid_enabled;
5422         gva_t gva;
5423         struct x86_exception e;
5424         unsigned i;
5425         unsigned long roots_to_free = 0;
5426         struct {
5427                 u64 pcid;
5428                 u64 gla;
5429         } operand;
5430
5431         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5432                 kvm_queue_exception(vcpu, UD_VECTOR);
5433                 return 1;
5434         }
5435
5436         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5437         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5438
5439         if (type > 3) {
5440                 kvm_inject_gp(vcpu, 0);
5441                 return 1;
5442         }
5443
5444         /* According to the Intel instruction reference, the memory operand
5445          * is read even if it isn't needed (e.g., for type==all)
5446          */
5447         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5448                                 vmx_instruction_info, false,
5449                                 sizeof(operand), &gva))
5450                 return 1;
5451
5452         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5453                 kvm_inject_emulated_page_fault(vcpu, &e);
5454                 return 1;
5455         }
5456
5457         if (operand.pcid >> 12 != 0) {
5458                 kvm_inject_gp(vcpu, 0);
5459                 return 1;
5460         }
5461
5462         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5463
5464         switch (type) {
5465         case INVPCID_TYPE_INDIV_ADDR:
5466                 if ((!pcid_enabled && (operand.pcid != 0)) ||
5467                     is_noncanonical_address(operand.gla, vcpu)) {
5468                         kvm_inject_gp(vcpu, 0);
5469                         return 1;
5470                 }
5471                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5472                 return kvm_skip_emulated_instruction(vcpu);
5473
5474         case INVPCID_TYPE_SINGLE_CTXT:
5475                 if (!pcid_enabled && (operand.pcid != 0)) {
5476                         kvm_inject_gp(vcpu, 0);
5477                         return 1;
5478                 }
5479
5480                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5481                         kvm_mmu_sync_roots(vcpu);
5482                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
5483                 }
5484
5485                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5486                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
5487                             == operand.pcid)
5488                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5489
5490                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5491                 /*
5492                  * If neither the current cr3 nor any of the prev_roots use the
5493                  * given PCID, then nothing needs to be done here because a
5494                  * resync will happen anyway before switching to any other CR3.
5495                  */
5496
5497                 return kvm_skip_emulated_instruction(vcpu);
5498
5499         case INVPCID_TYPE_ALL_NON_GLOBAL:
5500                 /*
5501                  * Currently, KVM doesn't mark global entries in the shadow
5502                  * page tables, so a non-global flush just degenerates to a
5503                  * global flush. If needed, we could optimize this later by
5504                  * keeping track of global entries in shadow page tables.
5505                  */
5506
5507                 /* fall-through */
5508         case INVPCID_TYPE_ALL_INCL_GLOBAL:
5509                 kvm_mmu_unload(vcpu);
5510                 return kvm_skip_emulated_instruction(vcpu);
5511
5512         default:
5513                 BUG(); /* We have already checked above that type <= 3 */
5514         }
5515 }
5516
5517 static int handle_pml_full(struct kvm_vcpu *vcpu)
5518 {
5519         unsigned long exit_qualification;
5520
5521         trace_kvm_pml_full(vcpu->vcpu_id);
5522
5523         exit_qualification = vmx_get_exit_qual(vcpu);
5524
5525         /*
5526          * PML buffer FULL happened while executing iret from NMI,
5527          * "blocked by NMI" bit has to be set before next VM entry.
5528          */
5529         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5530                         enable_vnmi &&
5531                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5532                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5533                                 GUEST_INTR_STATE_NMI);
5534
5535         /*
5536          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5537          * here.., and there's no userspace involvement needed for PML.
5538          */
5539         return 1;
5540 }
5541
5542 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5543 {
5544         struct vcpu_vmx *vmx = to_vmx(vcpu);
5545
5546         if (!vmx->req_immediate_exit &&
5547             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5548                 kvm_lapic_expired_hv_timer(vcpu);
5549
5550         return 1;
5551 }
5552
5553 /*
5554  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5555  * are overwritten by nested_vmx_setup() when nested=1.
5556  */
5557 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5558 {
5559         kvm_queue_exception(vcpu, UD_VECTOR);
5560         return 1;
5561 }
5562
5563 static int handle_encls(struct kvm_vcpu *vcpu)
5564 {
5565         /*
5566          * SGX virtualization is not yet supported.  There is no software
5567          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5568          * to prevent the guest from executing ENCLS.
5569          */
5570         kvm_queue_exception(vcpu, UD_VECTOR);
5571         return 1;
5572 }
5573
5574 /*
5575  * The exit handlers return 1 if the exit was handled fully and guest execution
5576  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5577  * to be done to userspace and return 0.
5578  */
5579 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5580         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5581         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5582         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5583         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5584         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5585         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5586         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5587         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5588         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5589         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5590         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5591         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5592         [EXIT_REASON_INVD]                    = handle_invd,
5593         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5594         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5595         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5596         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5597         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5598         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5599         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5600         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5601         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5602         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5603         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5604         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5605         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5606         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5607         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5608         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5609         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5610         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5611         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5612         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5613         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5614         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5615         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5616         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5617         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5618         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
5619         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5620         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
5621         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5622         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5623         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
5624         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
5625         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5626         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5627         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5628         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5629         [EXIT_REASON_ENCLS]                   = handle_encls,
5630 };
5631
5632 static const int kvm_vmx_max_exit_handlers =
5633         ARRAY_SIZE(kvm_vmx_exit_handlers);
5634
5635 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5636 {
5637         *info1 = vmx_get_exit_qual(vcpu);
5638         *info2 = vmx_get_intr_info(vcpu);
5639 }
5640
5641 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5642 {
5643         if (vmx->pml_pg) {
5644                 __free_page(vmx->pml_pg);
5645                 vmx->pml_pg = NULL;
5646         }
5647 }
5648
5649 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5650 {
5651         struct vcpu_vmx *vmx = to_vmx(vcpu);
5652         u64 *pml_buf;
5653         u16 pml_idx;
5654
5655         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5656
5657         /* Do nothing if PML buffer is empty */
5658         if (pml_idx == (PML_ENTITY_NUM - 1))
5659                 return;
5660
5661         /* PML index always points to next available PML buffer entity */
5662         if (pml_idx >= PML_ENTITY_NUM)
5663                 pml_idx = 0;
5664         else
5665                 pml_idx++;
5666
5667         pml_buf = page_address(vmx->pml_pg);
5668         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5669                 u64 gpa;
5670
5671                 gpa = pml_buf[pml_idx];
5672                 WARN_ON(gpa & (PAGE_SIZE - 1));
5673                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5674         }
5675
5676         /* reset PML index */
5677         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5678 }
5679
5680 /*
5681  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5682  * Called before reporting dirty_bitmap to userspace.
5683  */
5684 static void kvm_flush_pml_buffers(struct kvm *kvm)
5685 {
5686         int i;
5687         struct kvm_vcpu *vcpu;
5688         /*
5689          * We only need to kick vcpu out of guest mode here, as PML buffer
5690          * is flushed at beginning of all VMEXITs, and it's obvious that only
5691          * vcpus running in guest are possible to have unflushed GPAs in PML
5692          * buffer.
5693          */
5694         kvm_for_each_vcpu(i, vcpu, kvm)
5695                 kvm_vcpu_kick(vcpu);
5696 }
5697
5698 static void vmx_dump_sel(char *name, uint32_t sel)
5699 {
5700         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5701                name, vmcs_read16(sel),
5702                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5703                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5704                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5705 }
5706
5707 static void vmx_dump_dtsel(char *name, uint32_t limit)
5708 {
5709         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5710                name, vmcs_read32(limit),
5711                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5712 }
5713
5714 void dump_vmcs(void)
5715 {
5716         u32 vmentry_ctl, vmexit_ctl;
5717         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5718         unsigned long cr4;
5719         u64 efer;
5720         int i, n;
5721
5722         if (!dump_invalid_vmcs) {
5723                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5724                 return;
5725         }
5726
5727         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5728         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5729         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5730         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5731         cr4 = vmcs_readl(GUEST_CR4);
5732         efer = vmcs_read64(GUEST_IA32_EFER);
5733         secondary_exec_control = 0;
5734         if (cpu_has_secondary_exec_ctrls())
5735                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5736
5737         pr_err("*** Guest State ***\n");
5738         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5739                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5740                vmcs_readl(CR0_GUEST_HOST_MASK));
5741         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5742                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5743         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5744         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5745             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5746         {
5747                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5748                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5749                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5750                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5751         }
5752         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5753                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5754         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5755                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5756         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5757                vmcs_readl(GUEST_SYSENTER_ESP),
5758                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5759         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5760         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5761         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5762         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5763         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5764         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5765         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5766         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5767         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5768         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5769         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5770             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5771                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
5772                        efer, vmcs_read64(GUEST_IA32_PAT));
5773         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5774                vmcs_read64(GUEST_IA32_DEBUGCTL),
5775                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5776         if (cpu_has_load_perf_global_ctrl() &&
5777             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5778                 pr_err("PerfGlobCtl = 0x%016llx\n",
5779                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5780         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5781                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5782         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5783                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5784                vmcs_read32(GUEST_ACTIVITY_STATE));
5785         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5786                 pr_err("InterruptStatus = %04x\n",
5787                        vmcs_read16(GUEST_INTR_STATUS));
5788
5789         pr_err("*** Host State ***\n");
5790         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5791                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5792         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5793                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5794                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5795                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5796                vmcs_read16(HOST_TR_SELECTOR));
5797         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5798                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5799                vmcs_readl(HOST_TR_BASE));
5800         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5801                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5802         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5803                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5804                vmcs_readl(HOST_CR4));
5805         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5806                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5807                vmcs_read32(HOST_IA32_SYSENTER_CS),
5808                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5809         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5810                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
5811                        vmcs_read64(HOST_IA32_EFER),
5812                        vmcs_read64(HOST_IA32_PAT));
5813         if (cpu_has_load_perf_global_ctrl() &&
5814             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5815                 pr_err("PerfGlobCtl = 0x%016llx\n",
5816                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5817
5818         pr_err("*** Control State ***\n");
5819         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5820                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5821         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5822         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5823                vmcs_read32(EXCEPTION_BITMAP),
5824                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5825                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5826         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5827                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5828                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5829                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5830         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5831                vmcs_read32(VM_EXIT_INTR_INFO),
5832                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5833                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5834         pr_err("        reason=%08x qualification=%016lx\n",
5835                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5836         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5837                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5838                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5839         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5840         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5841                 pr_err("TSC Multiplier = 0x%016llx\n",
5842                        vmcs_read64(TSC_MULTIPLIER));
5843         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5844                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5845                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5846                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5847                 }
5848                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5849                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5850                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5851                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5852         }
5853         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5854                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5855         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5856                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5857         n = vmcs_read32(CR3_TARGET_COUNT);
5858         for (i = 0; i + 1 < n; i += 4)
5859                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5860                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5861                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5862         if (i < n)
5863                 pr_err("CR3 target%u=%016lx\n",
5864                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5865         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5866                 pr_err("PLE Gap=%08x Window=%08x\n",
5867                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5868         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5869                 pr_err("Virtual processor ID = 0x%04x\n",
5870                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5871 }
5872
5873 /*
5874  * The guest has exited.  See if we can fix it or if we need userspace
5875  * assistance.
5876  */
5877 static int vmx_handle_exit(struct kvm_vcpu *vcpu,
5878         enum exit_fastpath_completion exit_fastpath)
5879 {
5880         struct vcpu_vmx *vmx = to_vmx(vcpu);
5881         u32 exit_reason = vmx->exit_reason;
5882         u32 vectoring_info = vmx->idt_vectoring_info;
5883
5884         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5885
5886         /*
5887          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5888          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5889          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5890          * mode as if vcpus is in root mode, the PML buffer must has been
5891          * flushed already.
5892          */
5893         if (enable_pml)
5894                 vmx_flush_pml_buffer(vcpu);
5895
5896         /* If guest state is invalid, start emulating */
5897         if (vmx->emulation_required)
5898                 return handle_invalid_guest_state(vcpu);
5899
5900         if (is_guest_mode(vcpu)) {
5901                 /*
5902                  * The host physical addresses of some pages of guest memory
5903                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5904                  * Page). The CPU may write to these pages via their host
5905                  * physical address while L2 is running, bypassing any
5906                  * address-translation-based dirty tracking (e.g. EPT write
5907                  * protection).
5908                  *
5909                  * Mark them dirty on every exit from L2 to prevent them from
5910                  * getting out of sync with dirty tracking.
5911                  */
5912                 nested_mark_vmcs12_pages_dirty(vcpu);
5913
5914                 if (nested_vmx_reflect_vmexit(vcpu))
5915                         return 1;
5916         }
5917
5918         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5919                 dump_vmcs();
5920                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5921                 vcpu->run->fail_entry.hardware_entry_failure_reason
5922                         = exit_reason;
5923                 return 0;
5924         }
5925
5926         if (unlikely(vmx->fail)) {
5927                 dump_vmcs();
5928                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5929                 vcpu->run->fail_entry.hardware_entry_failure_reason
5930                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5931                 return 0;
5932         }
5933
5934         /*
5935          * Note:
5936          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5937          * delivery event since it indicates guest is accessing MMIO.
5938          * The vm-exit can be triggered again after return to guest that
5939          * will cause infinite loop.
5940          */
5941         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5942                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5943                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5944                         exit_reason != EXIT_REASON_PML_FULL &&
5945                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
5946                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5947                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5948                 vcpu->run->internal.ndata = 3;
5949                 vcpu->run->internal.data[0] = vectoring_info;
5950                 vcpu->run->internal.data[1] = exit_reason;
5951                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5952                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5953                         vcpu->run->internal.ndata++;
5954                         vcpu->run->internal.data[3] =
5955                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5956                 }
5957                 return 0;
5958         }
5959
5960         if (unlikely(!enable_vnmi &&
5961                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5962                 if (vmx_interrupt_allowed(vcpu)) {
5963                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5964                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5965                            vcpu->arch.nmi_pending) {
5966                         /*
5967                          * This CPU don't support us in finding the end of an
5968                          * NMI-blocked window if the guest runs with IRQs
5969                          * disabled. So we pull the trigger after 1 s of
5970                          * futile waiting, but inform the user about this.
5971                          */
5972                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5973                                "state on VCPU %d after 1 s timeout\n",
5974                                __func__, vcpu->vcpu_id);
5975                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5976                 }
5977         }
5978
5979         if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5980                 kvm_skip_emulated_instruction(vcpu);
5981                 return 1;
5982         }
5983
5984         if (exit_reason >= kvm_vmx_max_exit_handlers)
5985                 goto unexpected_vmexit;
5986 #ifdef CONFIG_RETPOLINE
5987         if (exit_reason == EXIT_REASON_MSR_WRITE)
5988                 return kvm_emulate_wrmsr(vcpu);
5989         else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
5990                 return handle_preemption_timer(vcpu);
5991         else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
5992                 return handle_interrupt_window(vcpu);
5993         else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
5994                 return handle_external_interrupt(vcpu);
5995         else if (exit_reason == EXIT_REASON_HLT)
5996                 return kvm_emulate_halt(vcpu);
5997         else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
5998                 return handle_ept_misconfig(vcpu);
5999 #endif
6000
6001         exit_reason = array_index_nospec(exit_reason,
6002                                          kvm_vmx_max_exit_handlers);
6003         if (!kvm_vmx_exit_handlers[exit_reason])
6004                 goto unexpected_vmexit;
6005
6006         return kvm_vmx_exit_handlers[exit_reason](vcpu);
6007
6008 unexpected_vmexit:
6009         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
6010         dump_vmcs();
6011         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6012         vcpu->run->internal.suberror =
6013                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6014         vcpu->run->internal.ndata = 1;
6015         vcpu->run->internal.data[0] = exit_reason;
6016         return 0;
6017 }
6018
6019 /*
6020  * Software based L1D cache flush which is used when microcode providing
6021  * the cache control MSR is not loaded.
6022  *
6023  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6024  * flush it is required to read in 64 KiB because the replacement algorithm
6025  * is not exactly LRU. This could be sized at runtime via topology
6026  * information but as all relevant affected CPUs have 32KiB L1D cache size
6027  * there is no point in doing so.
6028  */
6029 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6030 {
6031         int size = PAGE_SIZE << L1D_CACHE_ORDER;
6032
6033         /*
6034          * This code is only executed when the the flush mode is 'cond' or
6035          * 'always'
6036          */
6037         if (static_branch_likely(&vmx_l1d_flush_cond)) {
6038                 bool flush_l1d;
6039
6040                 /*
6041                  * Clear the per-vcpu flush bit, it gets set again
6042                  * either from vcpu_run() or from one of the unsafe
6043                  * VMEXIT handlers.
6044                  */
6045                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6046                 vcpu->arch.l1tf_flush_l1d = false;
6047
6048                 /*
6049                  * Clear the per-cpu flush bit, it gets set again from
6050                  * the interrupt handlers.
6051                  */
6052                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6053                 kvm_clear_cpu_l1tf_flush_l1d();
6054
6055                 if (!flush_l1d)
6056                         return;
6057         }
6058
6059         vcpu->stat.l1d_flush++;
6060
6061         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6062                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6063                 return;
6064         }
6065
6066         asm volatile(
6067                 /* First ensure the pages are in the TLB */
6068                 "xorl   %%eax, %%eax\n"
6069                 ".Lpopulate_tlb:\n\t"
6070                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6071                 "addl   $4096, %%eax\n\t"
6072                 "cmpl   %%eax, %[size]\n\t"
6073                 "jne    .Lpopulate_tlb\n\t"
6074                 "xorl   %%eax, %%eax\n\t"
6075                 "cpuid\n\t"
6076                 /* Now fill the cache */
6077                 "xorl   %%eax, %%eax\n"
6078                 ".Lfill_cache:\n"
6079                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6080                 "addl   $64, %%eax\n\t"
6081                 "cmpl   %%eax, %[size]\n\t"
6082                 "jne    .Lfill_cache\n\t"
6083                 "lfence\n"
6084                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6085                     [size] "r" (size)
6086                 : "eax", "ebx", "ecx", "edx");
6087 }
6088
6089 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6090 {
6091         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6092         int tpr_threshold;
6093
6094         if (is_guest_mode(vcpu) &&
6095                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6096                 return;
6097
6098         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6099         if (is_guest_mode(vcpu))
6100                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6101         else
6102                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6103 }
6104
6105 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6106 {
6107         struct vcpu_vmx *vmx = to_vmx(vcpu);
6108         u32 sec_exec_control;
6109
6110         if (!lapic_in_kernel(vcpu))
6111                 return;
6112
6113         if (!flexpriority_enabled &&
6114             !cpu_has_vmx_virtualize_x2apic_mode())
6115                 return;
6116
6117         /* Postpone execution until vmcs01 is the current VMCS. */
6118         if (is_guest_mode(vcpu)) {
6119                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6120                 return;
6121         }
6122
6123         sec_exec_control = secondary_exec_controls_get(vmx);
6124         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6125                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6126
6127         switch (kvm_get_apic_mode(vcpu)) {
6128         case LAPIC_MODE_INVALID:
6129                 WARN_ONCE(true, "Invalid local APIC state");
6130         case LAPIC_MODE_DISABLED:
6131                 break;
6132         case LAPIC_MODE_XAPIC:
6133                 if (flexpriority_enabled) {
6134                         sec_exec_control |=
6135                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6136                         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6137
6138                         /*
6139                          * Flush the TLB, reloading the APIC access page will
6140                          * only do so if its physical address has changed, but
6141                          * the guest may have inserted a non-APIC mapping into
6142                          * the TLB while the APIC access page was disabled.
6143                          */
6144                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6145                 }
6146                 break;
6147         case LAPIC_MODE_X2APIC:
6148                 if (cpu_has_vmx_virtualize_x2apic_mode())
6149                         sec_exec_control |=
6150                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6151                 break;
6152         }
6153         secondary_exec_controls_set(vmx, sec_exec_control);
6154
6155         vmx_update_msr_bitmap(vcpu);
6156 }
6157
6158 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6159 {
6160         struct page *page;
6161
6162         /* Defer reload until vmcs01 is the current VMCS. */
6163         if (is_guest_mode(vcpu)) {
6164                 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6165                 return;
6166         }
6167
6168         if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6169             SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6170                 return;
6171
6172         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6173         if (is_error_page(page))
6174                 return;
6175
6176         vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6177         vmx_flush_tlb_current(vcpu);
6178
6179         /*
6180          * Do not pin apic access page in memory, the MMU notifier
6181          * will call us again if it is migrated or swapped out.
6182          */
6183         put_page(page);
6184 }
6185
6186 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6187 {
6188         u16 status;
6189         u8 old;
6190
6191         if (max_isr == -1)
6192                 max_isr = 0;
6193
6194         status = vmcs_read16(GUEST_INTR_STATUS);
6195         old = status >> 8;
6196         if (max_isr != old) {
6197                 status &= 0xff;
6198                 status |= max_isr << 8;
6199                 vmcs_write16(GUEST_INTR_STATUS, status);
6200         }
6201 }
6202
6203 static void vmx_set_rvi(int vector)
6204 {
6205         u16 status;
6206         u8 old;
6207
6208         if (vector == -1)
6209                 vector = 0;
6210
6211         status = vmcs_read16(GUEST_INTR_STATUS);
6212         old = (u8)status & 0xff;
6213         if ((u8)vector != old) {
6214                 status &= ~0xff;
6215                 status |= (u8)vector;
6216                 vmcs_write16(GUEST_INTR_STATUS, status);
6217         }
6218 }
6219
6220 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6221 {
6222         /*
6223          * When running L2, updating RVI is only relevant when
6224          * vmcs12 virtual-interrupt-delivery enabled.
6225          * However, it can be enabled only when L1 also
6226          * intercepts external-interrupts and in that case
6227          * we should not update vmcs02 RVI but instead intercept
6228          * interrupt. Therefore, do nothing when running L2.
6229          */
6230         if (!is_guest_mode(vcpu))
6231                 vmx_set_rvi(max_irr);
6232 }
6233
6234 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6235 {
6236         struct vcpu_vmx *vmx = to_vmx(vcpu);
6237         int max_irr;
6238         bool max_irr_updated;
6239
6240         WARN_ON(!vcpu->arch.apicv_active);
6241         if (pi_test_on(&vmx->pi_desc)) {
6242                 pi_clear_on(&vmx->pi_desc);
6243                 /*
6244                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6245                  * But on x86 this is just a compiler barrier anyway.
6246                  */
6247                 smp_mb__after_atomic();
6248                 max_irr_updated =
6249                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6250
6251                 /*
6252                  * If we are running L2 and L1 has a new pending interrupt
6253                  * which can be injected, we should re-evaluate
6254                  * what should be done with this new L1 interrupt.
6255                  * If L1 intercepts external-interrupts, we should
6256                  * exit from L2 to L1. Otherwise, interrupt should be
6257                  * delivered directly to L2.
6258                  */
6259                 if (is_guest_mode(vcpu) && max_irr_updated) {
6260                         if (nested_exit_on_intr(vcpu))
6261                                 kvm_vcpu_exiting_guest_mode(vcpu);
6262                         else
6263                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6264                 }
6265         } else {
6266                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6267         }
6268         vmx_hwapic_irr_update(vcpu, max_irr);
6269         return max_irr;
6270 }
6271
6272 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6273 {
6274         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6275
6276         return pi_test_on(pi_desc) ||
6277                 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6278 }
6279
6280 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6281 {
6282         if (!kvm_vcpu_apicv_active(vcpu))
6283                 return;
6284
6285         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6286         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6287         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6288         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6289 }
6290
6291 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6292 {
6293         struct vcpu_vmx *vmx = to_vmx(vcpu);
6294
6295         pi_clear_on(&vmx->pi_desc);
6296         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6297 }
6298
6299 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6300 {
6301         u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6302
6303         /* if exit due to PF check for async PF */
6304         if (is_page_fault(intr_info)) {
6305                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6306         /* Handle machine checks before interrupts are enabled */
6307         } else if (is_machine_check(intr_info)) {
6308                 kvm_machine_check();
6309         /* We need to handle NMIs before interrupts are enabled */
6310         } else if (is_nmi(intr_info)) {
6311                 kvm_before_interrupt(&vmx->vcpu);
6312                 asm("int $2");
6313                 kvm_after_interrupt(&vmx->vcpu);
6314         }
6315 }
6316
6317 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6318 {
6319         unsigned int vector;
6320         unsigned long entry;
6321 #ifdef CONFIG_X86_64
6322         unsigned long tmp;
6323 #endif
6324         gate_desc *desc;
6325         u32 intr_info = vmx_get_intr_info(vcpu);
6326
6327         if (WARN_ONCE(!is_external_intr(intr_info),
6328             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6329                 return;
6330
6331         vector = intr_info & INTR_INFO_VECTOR_MASK;
6332         desc = (gate_desc *)host_idt_base + vector;
6333         entry = gate_offset(desc);
6334
6335         kvm_before_interrupt(vcpu);
6336
6337         asm volatile(
6338 #ifdef CONFIG_X86_64
6339                 "mov %%" _ASM_SP ", %[sp]\n\t"
6340                 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6341                 "push $%c[ss]\n\t"
6342                 "push %[sp]\n\t"
6343 #endif
6344                 "pushf\n\t"
6345                 __ASM_SIZE(push) " $%c[cs]\n\t"
6346                 CALL_NOSPEC
6347                 :
6348 #ifdef CONFIG_X86_64
6349                 [sp]"=&r"(tmp),
6350 #endif
6351                 ASM_CALL_CONSTRAINT
6352                 :
6353                 [thunk_target]"r"(entry),
6354                 [ss]"i"(__KERNEL_DS),
6355                 [cs]"i"(__KERNEL_CS)
6356         );
6357
6358         kvm_after_interrupt(vcpu);
6359 }
6360 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6361
6362 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6363         enum exit_fastpath_completion *exit_fastpath)
6364 {
6365         struct vcpu_vmx *vmx = to_vmx(vcpu);
6366
6367         if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6368                 handle_external_interrupt_irqoff(vcpu);
6369         else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6370                 handle_exception_nmi_irqoff(vmx);
6371         else if (!is_guest_mode(vcpu) &&
6372                 vmx->exit_reason == EXIT_REASON_MSR_WRITE)
6373                 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
6374 }
6375
6376 static bool vmx_has_emulated_msr(int index)
6377 {
6378         switch (index) {
6379         case MSR_IA32_SMBASE:
6380                 /*
6381                  * We cannot do SMM unless we can run the guest in big
6382                  * real mode.
6383                  */
6384                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6385         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6386                 return nested;
6387         case MSR_AMD64_VIRT_SPEC_CTRL:
6388                 /* This is AMD only.  */
6389                 return false;
6390         default:
6391                 return true;
6392         }
6393 }
6394
6395 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6396 {
6397         u32 exit_intr_info;
6398         bool unblock_nmi;
6399         u8 vector;
6400         bool idtv_info_valid;
6401
6402         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6403
6404         if (enable_vnmi) {
6405                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6406                         return;
6407
6408                 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6409                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6410                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6411                 /*
6412                  * SDM 3: 27.7.1.2 (September 2008)
6413                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6414                  * a guest IRET fault.
6415                  * SDM 3: 23.2.2 (September 2008)
6416                  * Bit 12 is undefined in any of the following cases:
6417                  *  If the VM exit sets the valid bit in the IDT-vectoring
6418                  *   information field.
6419                  *  If the VM exit is due to a double fault.
6420                  */
6421                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6422                     vector != DF_VECTOR && !idtv_info_valid)
6423                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6424                                       GUEST_INTR_STATE_NMI);
6425                 else
6426                         vmx->loaded_vmcs->nmi_known_unmasked =
6427                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6428                                   & GUEST_INTR_STATE_NMI);
6429         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6430                 vmx->loaded_vmcs->vnmi_blocked_time +=
6431                         ktime_to_ns(ktime_sub(ktime_get(),
6432                                               vmx->loaded_vmcs->entry_time));
6433 }
6434
6435 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6436                                       u32 idt_vectoring_info,
6437                                       int instr_len_field,
6438                                       int error_code_field)
6439 {
6440         u8 vector;
6441         int type;
6442         bool idtv_info_valid;
6443
6444         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6445
6446         vcpu->arch.nmi_injected = false;
6447         kvm_clear_exception_queue(vcpu);
6448         kvm_clear_interrupt_queue(vcpu);
6449
6450         if (!idtv_info_valid)
6451                 return;
6452
6453         kvm_make_request(KVM_REQ_EVENT, vcpu);
6454
6455         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6456         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6457
6458         switch (type) {
6459         case INTR_TYPE_NMI_INTR:
6460                 vcpu->arch.nmi_injected = true;
6461                 /*
6462                  * SDM 3: 27.7.1.2 (September 2008)
6463                  * Clear bit "block by NMI" before VM entry if a NMI
6464                  * delivery faulted.
6465                  */
6466                 vmx_set_nmi_mask(vcpu, false);
6467                 break;
6468         case INTR_TYPE_SOFT_EXCEPTION:
6469                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6470                 /* fall through */
6471         case INTR_TYPE_HARD_EXCEPTION:
6472                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6473                         u32 err = vmcs_read32(error_code_field);
6474                         kvm_requeue_exception_e(vcpu, vector, err);
6475                 } else
6476                         kvm_requeue_exception(vcpu, vector);
6477                 break;
6478         case INTR_TYPE_SOFT_INTR:
6479                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6480                 /* fall through */
6481         case INTR_TYPE_EXT_INTR:
6482                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6483                 break;
6484         default:
6485                 break;
6486         }
6487 }
6488
6489 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6490 {
6491         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6492                                   VM_EXIT_INSTRUCTION_LEN,
6493                                   IDT_VECTORING_ERROR_CODE);
6494 }
6495
6496 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6497 {
6498         __vmx_complete_interrupts(vcpu,
6499                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6500                                   VM_ENTRY_INSTRUCTION_LEN,
6501                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6502
6503         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6504 }
6505
6506 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6507 {
6508         int i, nr_msrs;
6509         struct perf_guest_switch_msr *msrs;
6510
6511         msrs = perf_guest_get_msrs(&nr_msrs);
6512
6513         if (!msrs)
6514                 return;
6515
6516         for (i = 0; i < nr_msrs; i++)
6517                 if (msrs[i].host == msrs[i].guest)
6518                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6519                 else
6520                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6521                                         msrs[i].host, false);
6522 }
6523
6524 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6525 {
6526         u32 host_umwait_control;
6527
6528         if (!vmx_has_waitpkg(vmx))
6529                 return;
6530
6531         host_umwait_control = get_umwait_control_msr();
6532
6533         if (vmx->msr_ia32_umwait_control != host_umwait_control)
6534                 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6535                         vmx->msr_ia32_umwait_control,
6536                         host_umwait_control, false);
6537         else
6538                 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6539 }
6540
6541 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6542 {
6543         struct vcpu_vmx *vmx = to_vmx(vcpu);
6544         u64 tscl;
6545         u32 delta_tsc;
6546
6547         if (vmx->req_immediate_exit) {
6548                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6549                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6550         } else if (vmx->hv_deadline_tsc != -1) {
6551                 tscl = rdtsc();
6552                 if (vmx->hv_deadline_tsc > tscl)
6553                         /* set_hv_timer ensures the delta fits in 32-bits */
6554                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6555                                 cpu_preemption_timer_multi);
6556                 else
6557                         delta_tsc = 0;
6558
6559                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6560                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6561         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6562                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6563                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6564         }
6565 }
6566
6567 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6568 {
6569         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6570                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6571                 vmcs_writel(HOST_RSP, host_rsp);
6572         }
6573 }
6574
6575 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6576
6577 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6578 {
6579         struct vcpu_vmx *vmx = to_vmx(vcpu);
6580         unsigned long cr3, cr4;
6581
6582         /* Record the guest's net vcpu time for enforced NMI injections. */
6583         if (unlikely(!enable_vnmi &&
6584                      vmx->loaded_vmcs->soft_vnmi_blocked))
6585                 vmx->loaded_vmcs->entry_time = ktime_get();
6586
6587         /* Don't enter VMX if guest state is invalid, let the exit handler
6588            start emulation until we arrive back to a valid state */
6589         if (vmx->emulation_required)
6590                 return;
6591
6592         if (vmx->ple_window_dirty) {
6593                 vmx->ple_window_dirty = false;
6594                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6595         }
6596
6597         /*
6598          * We did this in prepare_switch_to_guest, because it needs to
6599          * be within srcu_read_lock.
6600          */
6601         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6602
6603         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6604                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6605         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6606                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6607
6608         cr3 = __get_current_cr3_fast();
6609         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6610                 vmcs_writel(HOST_CR3, cr3);
6611                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6612         }
6613
6614         cr4 = cr4_read_shadow();
6615         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6616                 vmcs_writel(HOST_CR4, cr4);
6617                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6618         }
6619
6620         /* When single-stepping over STI and MOV SS, we must clear the
6621          * corresponding interruptibility bits in the guest state. Otherwise
6622          * vmentry fails as it then expects bit 14 (BS) in pending debug
6623          * exceptions being set, but that's not correct for the guest debugging
6624          * case. */
6625         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6626                 vmx_set_interrupt_shadow(vcpu, 0);
6627
6628         kvm_load_guest_xsave_state(vcpu);
6629
6630         if (static_cpu_has(X86_FEATURE_PKU) &&
6631             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6632             vcpu->arch.pkru != vmx->host_pkru)
6633                 __write_pkru(vcpu->arch.pkru);
6634
6635         pt_guest_enter(vmx);
6636
6637         if (vcpu_to_pmu(vcpu)->version)
6638                 atomic_switch_perf_msrs(vmx);
6639         atomic_switch_umwait_control_msr(vmx);
6640
6641         if (enable_preemption_timer)
6642                 vmx_update_hv_timer(vcpu);
6643
6644         if (lapic_in_kernel(vcpu) &&
6645                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6646                 kvm_wait_lapic_expire(vcpu);
6647
6648         /*
6649          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6650          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6651          * is no need to worry about the conditional branch over the wrmsr
6652          * being speculatively taken.
6653          */
6654         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6655
6656         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6657         if (static_branch_unlikely(&vmx_l1d_should_flush))
6658                 vmx_l1d_flush(vcpu);
6659         else if (static_branch_unlikely(&mds_user_clear))
6660                 mds_clear_cpu_buffers();
6661
6662         if (vcpu->arch.cr2 != read_cr2())
6663                 write_cr2(vcpu->arch.cr2);
6664
6665         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6666                                    vmx->loaded_vmcs->launched);
6667
6668         vcpu->arch.cr2 = read_cr2();
6669
6670         /*
6671          * We do not use IBRS in the kernel. If this vCPU has used the
6672          * SPEC_CTRL MSR it may have left it on; save the value and
6673          * turn it off. This is much more efficient than blindly adding
6674          * it to the atomic save/restore list. Especially as the former
6675          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6676          *
6677          * For non-nested case:
6678          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6679          * save it.
6680          *
6681          * For nested case:
6682          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6683          * save it.
6684          */
6685         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6686                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6687
6688         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6689
6690         /* All fields are clean at this point */
6691         if (static_branch_unlikely(&enable_evmcs))
6692                 current_evmcs->hv_clean_fields |=
6693                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6694
6695         if (static_branch_unlikely(&enable_evmcs))
6696                 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6697
6698         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6699         if (vmx->host_debugctlmsr)
6700                 update_debugctlmsr(vmx->host_debugctlmsr);
6701
6702 #ifndef CONFIG_X86_64
6703         /*
6704          * The sysexit path does not restore ds/es, so we must set them to
6705          * a reasonable value ourselves.
6706          *
6707          * We can't defer this to vmx_prepare_switch_to_host() since that
6708          * function may be executed in interrupt context, which saves and
6709          * restore segments around it, nullifying its effect.
6710          */
6711         loadsegment(ds, __USER_DS);
6712         loadsegment(es, __USER_DS);
6713 #endif
6714
6715         vmx_register_cache_reset(vcpu);
6716
6717         pt_guest_exit(vmx);
6718
6719         /*
6720          * eager fpu is enabled if PKEY is supported and CR4 is switched
6721          * back on host, so it is safe to read guest PKRU from current
6722          * XSAVE.
6723          */
6724         if (static_cpu_has(X86_FEATURE_PKU) &&
6725             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6726                 vcpu->arch.pkru = rdpkru();
6727                 if (vcpu->arch.pkru != vmx->host_pkru)
6728                         __write_pkru(vmx->host_pkru);
6729         }
6730
6731         kvm_load_host_xsave_state(vcpu);
6732
6733         vmx->nested.nested_run_pending = 0;
6734         vmx->idt_vectoring_info = 0;
6735
6736         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6737         if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6738                 kvm_machine_check();
6739
6740         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6741                 return;
6742
6743         vmx->loaded_vmcs->launched = 1;
6744         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6745
6746         vmx_recover_nmi_blocking(vmx);
6747         vmx_complete_interrupts(vmx);
6748 }
6749
6750 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6751 {
6752         struct vcpu_vmx *vmx = to_vmx(vcpu);
6753
6754         if (enable_pml)
6755                 vmx_destroy_pml_buffer(vmx);
6756         free_vpid(vmx->vpid);
6757         nested_vmx_free_vcpu(vcpu);
6758         free_loaded_vmcs(vmx->loaded_vmcs);
6759 }
6760
6761 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6762 {
6763         struct vcpu_vmx *vmx;
6764         unsigned long *msr_bitmap;
6765         int i, cpu, err;
6766
6767         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6768         vmx = to_vmx(vcpu);
6769
6770         err = -ENOMEM;
6771
6772         vmx->vpid = allocate_vpid();
6773
6774         /*
6775          * If PML is turned on, failure on enabling PML just results in failure
6776          * of creating the vcpu, therefore we can simplify PML logic (by
6777          * avoiding dealing with cases, such as enabling PML partially on vcpus
6778          * for the guest), etc.
6779          */
6780         if (enable_pml) {
6781                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6782                 if (!vmx->pml_pg)
6783                         goto free_vpid;
6784         }
6785
6786         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
6787
6788         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6789                 u32 index = vmx_msr_index[i];
6790                 u32 data_low, data_high;
6791                 int j = vmx->nmsrs;
6792
6793                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6794                         continue;
6795                 if (wrmsr_safe(index, data_low, data_high) < 0)
6796                         continue;
6797
6798                 vmx->guest_msrs[j].index = i;
6799                 vmx->guest_msrs[j].data = 0;
6800                 switch (index) {
6801                 case MSR_IA32_TSX_CTRL:
6802                         /*
6803                          * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6804                          * let's avoid changing CPUID bits under the host
6805                          * kernel's feet.
6806                          */
6807                         vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6808                         break;
6809                 default:
6810                         vmx->guest_msrs[j].mask = -1ull;
6811                         break;
6812                 }
6813                 ++vmx->nmsrs;
6814         }
6815
6816         err = alloc_loaded_vmcs(&vmx->vmcs01);
6817         if (err < 0)
6818                 goto free_pml;
6819
6820         msr_bitmap = vmx->vmcs01.msr_bitmap;
6821         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6822         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6823         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6824         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6825         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6826         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6827         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6828         if (kvm_cstate_in_guest(vcpu->kvm)) {
6829                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6830                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6831                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6832                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6833         }
6834         vmx->msr_bitmap_mode = 0;
6835
6836         vmx->loaded_vmcs = &vmx->vmcs01;
6837         cpu = get_cpu();
6838         vmx_vcpu_load(vcpu, cpu);
6839         vcpu->cpu = cpu;
6840         init_vmcs(vmx);
6841         vmx_vcpu_put(vcpu);
6842         put_cpu();
6843         if (cpu_need_virtualize_apic_accesses(vcpu)) {
6844                 err = alloc_apic_access_page(vcpu->kvm);
6845                 if (err)
6846                         goto free_vmcs;
6847         }
6848
6849         if (enable_ept && !enable_unrestricted_guest) {
6850                 err = init_rmode_identity_map(vcpu->kvm);
6851                 if (err)
6852                         goto free_vmcs;
6853         }
6854
6855         if (nested)
6856                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6857                                            vmx_capability.ept);
6858         else
6859                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6860
6861         vmx->nested.posted_intr_nv = -1;
6862         vmx->nested.current_vmptr = -1ull;
6863
6864         vcpu->arch.microcode_version = 0x100000000ULL;
6865         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6866
6867         /*
6868          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6869          * or POSTED_INTR_WAKEUP_VECTOR.
6870          */
6871         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6872         vmx->pi_desc.sn = 1;
6873
6874         vmx->ept_pointer = INVALID_PAGE;
6875
6876         return 0;
6877
6878 free_vmcs:
6879         free_loaded_vmcs(vmx->loaded_vmcs);
6880 free_pml:
6881         vmx_destroy_pml_buffer(vmx);
6882 free_vpid:
6883         free_vpid(vmx->vpid);
6884         return err;
6885 }
6886
6887 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6888 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6889
6890 static int vmx_vm_init(struct kvm *kvm)
6891 {
6892         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6893
6894         if (!ple_gap)
6895                 kvm->arch.pause_in_guest = true;
6896
6897         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6898                 switch (l1tf_mitigation) {
6899                 case L1TF_MITIGATION_OFF:
6900                 case L1TF_MITIGATION_FLUSH_NOWARN:
6901                         /* 'I explicitly don't care' is set */
6902                         break;
6903                 case L1TF_MITIGATION_FLUSH:
6904                 case L1TF_MITIGATION_FLUSH_NOSMT:
6905                 case L1TF_MITIGATION_FULL:
6906                         /*
6907                          * Warn upon starting the first VM in a potentially
6908                          * insecure environment.
6909                          */
6910                         if (sched_smt_active())
6911                                 pr_warn_once(L1TF_MSG_SMT);
6912                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6913                                 pr_warn_once(L1TF_MSG_L1D);
6914                         break;
6915                 case L1TF_MITIGATION_FULL_FORCE:
6916                         /* Flush is enforced */
6917                         break;
6918                 }
6919         }
6920         kvm_apicv_init(kvm, enable_apicv);
6921         return 0;
6922 }
6923
6924 static int __init vmx_check_processor_compat(void)
6925 {
6926         struct vmcs_config vmcs_conf;
6927         struct vmx_capability vmx_cap;
6928
6929         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6930             !this_cpu_has(X86_FEATURE_VMX)) {
6931                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6932                 return -EIO;
6933         }
6934
6935         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6936                 return -EIO;
6937         if (nested)
6938                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6939         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6940                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6941                                 smp_processor_id());
6942                 return -EIO;
6943         }
6944         return 0;
6945 }
6946
6947 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6948 {
6949         u8 cache;
6950         u64 ipat = 0;
6951
6952         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
6953          * memory aliases with conflicting memory types and sometimes MCEs.
6954          * We have to be careful as to what are honored and when.
6955          *
6956          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
6957          * UC.  The effective memory type is UC or WC depending on guest PAT.
6958          * This was historically the source of MCEs and we want to be
6959          * conservative.
6960          *
6961          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
6962          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
6963          * EPT memory type is set to WB.  The effective memory type is forced
6964          * WB.
6965          *
6966          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
6967          * EPT memory type is used to emulate guest CD/MTRR.
6968          */
6969
6970         if (is_mmio) {
6971                 cache = MTRR_TYPE_UNCACHABLE;
6972                 goto exit;
6973         }
6974
6975         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6976                 ipat = VMX_EPT_IPAT_BIT;
6977                 cache = MTRR_TYPE_WRBACK;
6978                 goto exit;
6979         }
6980
6981         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6982                 ipat = VMX_EPT_IPAT_BIT;
6983                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6984                         cache = MTRR_TYPE_WRBACK;
6985                 else
6986                         cache = MTRR_TYPE_UNCACHABLE;
6987                 goto exit;
6988         }
6989
6990         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6991
6992 exit:
6993         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6994 }
6995
6996 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6997 {
6998         /*
6999          * These bits in the secondary execution controls field
7000          * are dynamic, the others are mostly based on the hypervisor
7001          * architecture and the guest's CPUID.  Do not touch the
7002          * dynamic bits.
7003          */
7004         u32 mask =
7005                 SECONDARY_EXEC_SHADOW_VMCS |
7006                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7007                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7008                 SECONDARY_EXEC_DESC;
7009
7010         u32 new_ctl = vmx->secondary_exec_control;
7011         u32 cur_ctl = secondary_exec_controls_get(vmx);
7012
7013         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7014 }
7015
7016 /*
7017  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7018  * (indicating "allowed-1") if they are supported in the guest's CPUID.
7019  */
7020 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7021 {
7022         struct vcpu_vmx *vmx = to_vmx(vcpu);
7023         struct kvm_cpuid_entry2 *entry;
7024
7025         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7026         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7027
7028 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
7029         if (entry && (entry->_reg & (_cpuid_mask)))                     \
7030                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
7031 } while (0)
7032
7033         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7034         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
7035         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
7036         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
7037         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
7038         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
7039         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
7040         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
7041         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
7042         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
7043         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7044         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
7045         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
7046         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
7047         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
7048
7049         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7050         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
7051         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
7052         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
7053         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
7054         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
7055         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
7056
7057 #undef cr4_fixed1_update
7058 }
7059
7060 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7061 {
7062         struct vcpu_vmx *vmx = to_vmx(vcpu);
7063
7064         if (kvm_mpx_supported()) {
7065                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7066
7067                 if (mpx_enabled) {
7068                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7069                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7070                 } else {
7071                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7072                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7073                 }
7074         }
7075 }
7076
7077 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7078 {
7079         struct vcpu_vmx *vmx = to_vmx(vcpu);
7080         struct kvm_cpuid_entry2 *best = NULL;
7081         int i;
7082
7083         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7084                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7085                 if (!best)
7086                         return;
7087                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7088                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7089                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7090                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7091         }
7092
7093         /* Get the number of configurable Address Ranges for filtering */
7094         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7095                                                 PT_CAP_num_address_ranges);
7096
7097         /* Initialize and clear the no dependency bits */
7098         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7099                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7100
7101         /*
7102          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7103          * will inject an #GP
7104          */
7105         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7106                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7107
7108         /*
7109          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7110          * PSBFreq can be set
7111          */
7112         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7113                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7114                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7115
7116         /*
7117          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7118          * MTCFreq can be set
7119          */
7120         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7121                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7122                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7123
7124         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7125         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7126                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7127                                                         RTIT_CTL_PTW_EN);
7128
7129         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7130         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7131                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7132
7133         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7134         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7135                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7136
7137         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7138         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7139                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7140
7141         /* unmask address range configure area */
7142         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7143                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7144 }
7145
7146 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7147 {
7148         struct vcpu_vmx *vmx = to_vmx(vcpu);
7149
7150         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7151         vcpu->arch.xsaves_enabled = false;
7152
7153         if (cpu_has_secondary_exec_ctrls()) {
7154                 vmx_compute_secondary_exec_control(vmx);
7155                 vmcs_set_secondary_exec_control(vmx);
7156         }
7157
7158         if (nested_vmx_allowed(vcpu))
7159                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7160                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7161                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7162         else
7163                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7164                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7165                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7166
7167         if (nested_vmx_allowed(vcpu)) {
7168                 nested_vmx_cr_fixed1_bits_update(vcpu);
7169                 nested_vmx_entry_exit_ctls_update(vcpu);
7170         }
7171
7172         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7173                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7174                 update_intel_pt_cfg(vcpu);
7175
7176         if (boot_cpu_has(X86_FEATURE_RTM)) {
7177                 struct shared_msr_entry *msr;
7178                 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7179                 if (msr) {
7180                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7181                         vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7182                 }
7183         }
7184 }
7185
7186 static __init void vmx_set_cpu_caps(void)
7187 {
7188         kvm_set_cpu_caps();
7189
7190         /* CPUID 0x1 */
7191         if (nested)
7192                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7193
7194         /* CPUID 0x7 */
7195         if (kvm_mpx_supported())
7196                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7197         if (cpu_has_vmx_invpcid())
7198                 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
7199         if (vmx_pt_mode_is_host_guest())
7200                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7201
7202         /* PKU is not yet implemented for shadow paging. */
7203         if (enable_ept && boot_cpu_has(X86_FEATURE_OSPKE))
7204                 kvm_cpu_cap_check_and_set(X86_FEATURE_PKU);
7205
7206         if (vmx_umip_emulated())
7207                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7208
7209         /* CPUID 0xD.1 */
7210         supported_xss = 0;
7211         if (!vmx_xsaves_supported())
7212                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7213
7214         /* CPUID 0x80000001 */
7215         if (!cpu_has_vmx_rdtscp())
7216                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7217 }
7218
7219 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7220 {
7221         to_vmx(vcpu)->req_immediate_exit = true;
7222 }
7223
7224 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7225                                   struct x86_instruction_info *info)
7226 {
7227         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7228         unsigned short port;
7229         bool intercept;
7230         int size;
7231
7232         if (info->intercept == x86_intercept_in ||
7233             info->intercept == x86_intercept_ins) {
7234                 port = info->src_val;
7235                 size = info->dst_bytes;
7236         } else {
7237                 port = info->dst_val;
7238                 size = info->src_bytes;
7239         }
7240
7241         /*
7242          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7243          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7244          * control.
7245          *
7246          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7247          */
7248         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7249                 intercept = nested_cpu_has(vmcs12,
7250                                            CPU_BASED_UNCOND_IO_EXITING);
7251         else
7252                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7253
7254         /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7255         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7256 }
7257
7258 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7259                                struct x86_instruction_info *info,
7260                                enum x86_intercept_stage stage,
7261                                struct x86_exception *exception)
7262 {
7263         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7264
7265         switch (info->intercept) {
7266         /*
7267          * RDPID causes #UD if disabled through secondary execution controls.
7268          * Because it is marked as EmulateOnUD, we need to intercept it here.
7269          */
7270         case x86_intercept_rdtscp:
7271                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7272                         exception->vector = UD_VECTOR;
7273                         exception->error_code_valid = false;
7274                         return X86EMUL_PROPAGATE_FAULT;
7275                 }
7276                 break;
7277
7278         case x86_intercept_in:
7279         case x86_intercept_ins:
7280         case x86_intercept_out:
7281         case x86_intercept_outs:
7282                 return vmx_check_intercept_io(vcpu, info);
7283
7284         case x86_intercept_lgdt:
7285         case x86_intercept_lidt:
7286         case x86_intercept_lldt:
7287         case x86_intercept_ltr:
7288         case x86_intercept_sgdt:
7289         case x86_intercept_sidt:
7290         case x86_intercept_sldt:
7291         case x86_intercept_str:
7292                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7293                         return X86EMUL_CONTINUE;
7294
7295                 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7296                 break;
7297
7298         /* TODO: check more intercepts... */
7299         default:
7300                 break;
7301         }
7302
7303         return X86EMUL_UNHANDLEABLE;
7304 }
7305
7306 #ifdef CONFIG_X86_64
7307 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7308 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7309                                   u64 divisor, u64 *result)
7310 {
7311         u64 low = a << shift, high = a >> (64 - shift);
7312
7313         /* To avoid the overflow on divq */
7314         if (high >= divisor)
7315                 return 1;
7316
7317         /* Low hold the result, high hold rem which is discarded */
7318         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7319             "rm" (divisor), "0" (low), "1" (high));
7320         *result = low;
7321
7322         return 0;
7323 }
7324
7325 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7326                             bool *expired)
7327 {
7328         struct vcpu_vmx *vmx;
7329         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7330         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7331
7332         if (kvm_mwait_in_guest(vcpu->kvm) ||
7333                 kvm_can_post_timer_interrupt(vcpu))
7334                 return -EOPNOTSUPP;
7335
7336         vmx = to_vmx(vcpu);
7337         tscl = rdtsc();
7338         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7339         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7340         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7341                                                     ktimer->timer_advance_ns);
7342
7343         if (delta_tsc > lapic_timer_advance_cycles)
7344                 delta_tsc -= lapic_timer_advance_cycles;
7345         else
7346                 delta_tsc = 0;
7347
7348         /* Convert to host delta tsc if tsc scaling is enabled */
7349         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7350             delta_tsc && u64_shl_div_u64(delta_tsc,
7351                                 kvm_tsc_scaling_ratio_frac_bits,
7352                                 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7353                 return -ERANGE;
7354
7355         /*
7356          * If the delta tsc can't fit in the 32 bit after the multi shift,
7357          * we can't use the preemption timer.
7358          * It's possible that it fits on later vmentries, but checking
7359          * on every vmentry is costly so we just use an hrtimer.
7360          */
7361         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7362                 return -ERANGE;
7363
7364         vmx->hv_deadline_tsc = tscl + delta_tsc;
7365         *expired = !delta_tsc;
7366         return 0;
7367 }
7368
7369 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7370 {
7371         to_vmx(vcpu)->hv_deadline_tsc = -1;
7372 }
7373 #endif
7374
7375 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7376 {
7377         if (!kvm_pause_in_guest(vcpu->kvm))
7378                 shrink_ple_window(vcpu);
7379 }
7380
7381 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7382                                      struct kvm_memory_slot *slot)
7383 {
7384         if (!kvm_dirty_log_manual_protect_and_init_set(kvm))
7385                 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7386         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7387 }
7388
7389 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7390                                        struct kvm_memory_slot *slot)
7391 {
7392         kvm_mmu_slot_set_dirty(kvm, slot);
7393 }
7394
7395 static void vmx_flush_log_dirty(struct kvm *kvm)
7396 {
7397         kvm_flush_pml_buffers(kvm);
7398 }
7399
7400 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7401 {
7402         struct vmcs12 *vmcs12;
7403         struct vcpu_vmx *vmx = to_vmx(vcpu);
7404         gpa_t gpa, dst;
7405
7406         if (is_guest_mode(vcpu)) {
7407                 WARN_ON_ONCE(vmx->nested.pml_full);
7408
7409                 /*
7410                  * Check if PML is enabled for the nested guest.
7411                  * Whether eptp bit 6 is set is already checked
7412                  * as part of A/D emulation.
7413                  */
7414                 vmcs12 = get_vmcs12(vcpu);
7415                 if (!nested_cpu_has_pml(vmcs12))
7416                         return 0;
7417
7418                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7419                         vmx->nested.pml_full = true;
7420                         return 1;
7421                 }
7422
7423                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7424                 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7425
7426                 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7427                                          offset_in_page(dst), sizeof(gpa)))
7428                         return 0;
7429
7430                 vmcs12->guest_pml_index--;
7431         }
7432
7433         return 0;
7434 }
7435
7436 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7437                                            struct kvm_memory_slot *memslot,
7438                                            gfn_t offset, unsigned long mask)
7439 {
7440         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7441 }
7442
7443 static void __pi_post_block(struct kvm_vcpu *vcpu)
7444 {
7445         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7446         struct pi_desc old, new;
7447         unsigned int dest;
7448
7449         do {
7450                 old.control = new.control = pi_desc->control;
7451                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7452                      "Wakeup handler not enabled while the VCPU is blocked\n");
7453
7454                 dest = cpu_physical_id(vcpu->cpu);
7455
7456                 if (x2apic_enabled())
7457                         new.ndst = dest;
7458                 else
7459                         new.ndst = (dest << 8) & 0xFF00;
7460
7461                 /* set 'NV' to 'notification vector' */
7462                 new.nv = POSTED_INTR_VECTOR;
7463         } while (cmpxchg64(&pi_desc->control, old.control,
7464                            new.control) != old.control);
7465
7466         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7467                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7468                 list_del(&vcpu->blocked_vcpu_list);
7469                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7470                 vcpu->pre_pcpu = -1;
7471         }
7472 }
7473
7474 /*
7475  * This routine does the following things for vCPU which is going
7476  * to be blocked if VT-d PI is enabled.
7477  * - Store the vCPU to the wakeup list, so when interrupts happen
7478  *   we can find the right vCPU to wake up.
7479  * - Change the Posted-interrupt descriptor as below:
7480  *      'NDST' <-- vcpu->pre_pcpu
7481  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7482  * - If 'ON' is set during this process, which means at least one
7483  *   interrupt is posted for this vCPU, we cannot block it, in
7484  *   this case, return 1, otherwise, return 0.
7485  *
7486  */
7487 static int pi_pre_block(struct kvm_vcpu *vcpu)
7488 {
7489         unsigned int dest;
7490         struct pi_desc old, new;
7491         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7492
7493         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7494                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
7495                 !kvm_vcpu_apicv_active(vcpu))
7496                 return 0;
7497
7498         WARN_ON(irqs_disabled());
7499         local_irq_disable();
7500         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7501                 vcpu->pre_pcpu = vcpu->cpu;
7502                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7503                 list_add_tail(&vcpu->blocked_vcpu_list,
7504                               &per_cpu(blocked_vcpu_on_cpu,
7505                                        vcpu->pre_pcpu));
7506                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7507         }
7508
7509         do {
7510                 old.control = new.control = pi_desc->control;
7511
7512                 WARN((pi_desc->sn == 1),
7513                      "Warning: SN field of posted-interrupts "
7514                      "is set before blocking\n");
7515
7516                 /*
7517                  * Since vCPU can be preempted during this process,
7518                  * vcpu->cpu could be different with pre_pcpu, we
7519                  * need to set pre_pcpu as the destination of wakeup
7520                  * notification event, then we can find the right vCPU
7521                  * to wakeup in wakeup handler if interrupts happen
7522                  * when the vCPU is in blocked state.
7523                  */
7524                 dest = cpu_physical_id(vcpu->pre_pcpu);
7525
7526                 if (x2apic_enabled())
7527                         new.ndst = dest;
7528                 else
7529                         new.ndst = (dest << 8) & 0xFF00;
7530
7531                 /* set 'NV' to 'wakeup vector' */
7532                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7533         } while (cmpxchg64(&pi_desc->control, old.control,
7534                            new.control) != old.control);
7535
7536         /* We should not block the vCPU if an interrupt is posted for it.  */
7537         if (pi_test_on(pi_desc) == 1)
7538                 __pi_post_block(vcpu);
7539
7540         local_irq_enable();
7541         return (vcpu->pre_pcpu == -1);
7542 }
7543
7544 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7545 {
7546         if (pi_pre_block(vcpu))
7547                 return 1;
7548
7549         if (kvm_lapic_hv_timer_in_use(vcpu))
7550                 kvm_lapic_switch_to_sw_timer(vcpu);
7551
7552         return 0;
7553 }
7554
7555 static void pi_post_block(struct kvm_vcpu *vcpu)
7556 {
7557         if (vcpu->pre_pcpu == -1)
7558                 return;
7559
7560         WARN_ON(irqs_disabled());
7561         local_irq_disable();
7562         __pi_post_block(vcpu);
7563         local_irq_enable();
7564 }
7565
7566 static void vmx_post_block(struct kvm_vcpu *vcpu)
7567 {
7568         if (kvm_x86_ops.set_hv_timer)
7569                 kvm_lapic_switch_to_hv_timer(vcpu);
7570
7571         pi_post_block(vcpu);
7572 }
7573
7574 /*
7575  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7576  *
7577  * @kvm: kvm
7578  * @host_irq: host irq of the interrupt
7579  * @guest_irq: gsi of the interrupt
7580  * @set: set or unset PI
7581  * returns 0 on success, < 0 on failure
7582  */
7583 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7584                               uint32_t guest_irq, bool set)
7585 {
7586         struct kvm_kernel_irq_routing_entry *e;
7587         struct kvm_irq_routing_table *irq_rt;
7588         struct kvm_lapic_irq irq;
7589         struct kvm_vcpu *vcpu;
7590         struct vcpu_data vcpu_info;
7591         int idx, ret = 0;
7592
7593         if (!kvm_arch_has_assigned_device(kvm) ||
7594                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7595                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7596                 return 0;
7597
7598         idx = srcu_read_lock(&kvm->irq_srcu);
7599         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7600         if (guest_irq >= irq_rt->nr_rt_entries ||
7601             hlist_empty(&irq_rt->map[guest_irq])) {
7602                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7603                              guest_irq, irq_rt->nr_rt_entries);
7604                 goto out;
7605         }
7606
7607         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7608                 if (e->type != KVM_IRQ_ROUTING_MSI)
7609                         continue;
7610                 /*
7611                  * VT-d PI cannot support posting multicast/broadcast
7612                  * interrupts to a vCPU, we still use interrupt remapping
7613                  * for these kind of interrupts.
7614                  *
7615                  * For lowest-priority interrupts, we only support
7616                  * those with single CPU as the destination, e.g. user
7617                  * configures the interrupts via /proc/irq or uses
7618                  * irqbalance to make the interrupts single-CPU.
7619                  *
7620                  * We will support full lowest-priority interrupt later.
7621                  *
7622                  * In addition, we can only inject generic interrupts using
7623                  * the PI mechanism, refuse to route others through it.
7624                  */
7625
7626                 kvm_set_msi_irq(kvm, e, &irq);
7627                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7628                     !kvm_irq_is_postable(&irq)) {
7629                         /*
7630                          * Make sure the IRTE is in remapped mode if
7631                          * we don't handle it in posted mode.
7632                          */
7633                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7634                         if (ret < 0) {
7635                                 printk(KERN_INFO
7636                                    "failed to back to remapped mode, irq: %u\n",
7637                                    host_irq);
7638                                 goto out;
7639                         }
7640
7641                         continue;
7642                 }
7643
7644                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7645                 vcpu_info.vector = irq.vector;
7646
7647                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7648                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7649
7650                 if (set)
7651                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7652                 else
7653                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7654
7655                 if (ret < 0) {
7656                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
7657                                         __func__);
7658                         goto out;
7659                 }
7660         }
7661
7662         ret = 0;
7663 out:
7664         srcu_read_unlock(&kvm->irq_srcu, idx);
7665         return ret;
7666 }
7667
7668 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7669 {
7670         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7671                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7672                         FEAT_CTL_LMCE_ENABLED;
7673         else
7674                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7675                         ~FEAT_CTL_LMCE_ENABLED;
7676 }
7677
7678 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7679 {
7680         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7681         if (to_vmx(vcpu)->nested.nested_run_pending)
7682                 return 0;
7683         return 1;
7684 }
7685
7686 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7687 {
7688         struct vcpu_vmx *vmx = to_vmx(vcpu);
7689
7690         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7691         if (vmx->nested.smm.guest_mode)
7692                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7693
7694         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7695         vmx->nested.vmxon = false;
7696         vmx_clear_hlt(vcpu);
7697         return 0;
7698 }
7699
7700 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7701 {
7702         struct vcpu_vmx *vmx = to_vmx(vcpu);
7703         int ret;
7704
7705         if (vmx->nested.smm.vmxon) {
7706                 vmx->nested.vmxon = true;
7707                 vmx->nested.smm.vmxon = false;
7708         }
7709
7710         if (vmx->nested.smm.guest_mode) {
7711                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7712                 if (ret)
7713                         return ret;
7714
7715                 vmx->nested.smm.guest_mode = false;
7716         }
7717         return 0;
7718 }
7719
7720 static int enable_smi_window(struct kvm_vcpu *vcpu)
7721 {
7722         return 0;
7723 }
7724
7725 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7726 {
7727         return false;
7728 }
7729
7730 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7731 {
7732         return to_vmx(vcpu)->nested.vmxon;
7733 }
7734
7735 static void hardware_unsetup(void)
7736 {
7737         if (nested)
7738                 nested_vmx_hardware_unsetup();
7739
7740         free_kvm_area();
7741 }
7742
7743 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7744 {
7745         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7746                           BIT(APICV_INHIBIT_REASON_HYPERV);
7747
7748         return supported & BIT(bit);
7749 }
7750
7751 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7752         .hardware_unsetup = hardware_unsetup,
7753
7754         .hardware_enable = hardware_enable,
7755         .hardware_disable = hardware_disable,
7756         .cpu_has_accelerated_tpr = report_flexpriority,
7757         .has_emulated_msr = vmx_has_emulated_msr,
7758
7759         .vm_size = sizeof(struct kvm_vmx),
7760         .vm_init = vmx_vm_init,
7761
7762         .vcpu_create = vmx_create_vcpu,
7763         .vcpu_free = vmx_free_vcpu,
7764         .vcpu_reset = vmx_vcpu_reset,
7765
7766         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7767         .vcpu_load = vmx_vcpu_load,
7768         .vcpu_put = vmx_vcpu_put,
7769
7770         .update_bp_intercept = update_exception_bitmap,
7771         .get_msr_feature = vmx_get_msr_feature,
7772         .get_msr = vmx_get_msr,
7773         .set_msr = vmx_set_msr,
7774         .get_segment_base = vmx_get_segment_base,
7775         .get_segment = vmx_get_segment,
7776         .set_segment = vmx_set_segment,
7777         .get_cpl = vmx_get_cpl,
7778         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7779         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7780         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7781         .set_cr0 = vmx_set_cr0,
7782         .set_cr4 = vmx_set_cr4,
7783         .set_efer = vmx_set_efer,
7784         .get_idt = vmx_get_idt,
7785         .set_idt = vmx_set_idt,
7786         .get_gdt = vmx_get_gdt,
7787         .set_gdt = vmx_set_gdt,
7788         .get_dr6 = vmx_get_dr6,
7789         .set_dr6 = vmx_set_dr6,
7790         .set_dr7 = vmx_set_dr7,
7791         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7792         .cache_reg = vmx_cache_reg,
7793         .get_rflags = vmx_get_rflags,
7794         .set_rflags = vmx_set_rflags,
7795
7796         .tlb_flush_all = vmx_flush_tlb_all,
7797         .tlb_flush_current = vmx_flush_tlb_current,
7798         .tlb_flush_gva = vmx_flush_tlb_gva,
7799         .tlb_flush_guest = vmx_flush_tlb_guest,
7800
7801         .run = vmx_vcpu_run,
7802         .handle_exit = vmx_handle_exit,
7803         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7804         .update_emulated_instruction = vmx_update_emulated_instruction,
7805         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7806         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7807         .patch_hypercall = vmx_patch_hypercall,
7808         .set_irq = vmx_inject_irq,
7809         .set_nmi = vmx_inject_nmi,
7810         .queue_exception = vmx_queue_exception,
7811         .cancel_injection = vmx_cancel_injection,
7812         .interrupt_allowed = vmx_interrupt_allowed,
7813         .nmi_allowed = vmx_nmi_allowed,
7814         .get_nmi_mask = vmx_get_nmi_mask,
7815         .set_nmi_mask = vmx_set_nmi_mask,
7816         .enable_nmi_window = enable_nmi_window,
7817         .enable_irq_window = enable_irq_window,
7818         .update_cr8_intercept = update_cr8_intercept,
7819         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7820         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7821         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7822         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7823         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7824         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7825         .hwapic_irr_update = vmx_hwapic_irr_update,
7826         .hwapic_isr_update = vmx_hwapic_isr_update,
7827         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7828         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7829         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7830         .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7831
7832         .set_tss_addr = vmx_set_tss_addr,
7833         .set_identity_map_addr = vmx_set_identity_map_addr,
7834         .get_tdp_level = get_ept_level,
7835         .get_mt_mask = vmx_get_mt_mask,
7836
7837         .get_exit_info = vmx_get_exit_info,
7838
7839         .cpuid_update = vmx_cpuid_update,
7840
7841         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7842
7843         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7844         .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7845
7846         .load_mmu_pgd = vmx_load_mmu_pgd,
7847
7848         .check_intercept = vmx_check_intercept,
7849         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7850
7851         .request_immediate_exit = vmx_request_immediate_exit,
7852
7853         .sched_in = vmx_sched_in,
7854
7855         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7856         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7857         .flush_log_dirty = vmx_flush_log_dirty,
7858         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7859         .write_log_dirty = vmx_write_pml_buffer,
7860
7861         .pre_block = vmx_pre_block,
7862         .post_block = vmx_post_block,
7863
7864         .pmu_ops = &intel_pmu_ops,
7865
7866         .update_pi_irte = vmx_update_pi_irte,
7867
7868 #ifdef CONFIG_X86_64
7869         .set_hv_timer = vmx_set_hv_timer,
7870         .cancel_hv_timer = vmx_cancel_hv_timer,
7871 #endif
7872
7873         .setup_mce = vmx_setup_mce,
7874
7875         .smi_allowed = vmx_smi_allowed,
7876         .pre_enter_smm = vmx_pre_enter_smm,
7877         .pre_leave_smm = vmx_pre_leave_smm,
7878         .enable_smi_window = enable_smi_window,
7879
7880         .check_nested_events = NULL,
7881         .get_nested_state = NULL,
7882         .set_nested_state = NULL,
7883         .get_vmcs12_pages = NULL,
7884         .nested_enable_evmcs = NULL,
7885         .nested_get_evmcs_version = NULL,
7886         .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7887         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7888 };
7889
7890 static __init int hardware_setup(void)
7891 {
7892         unsigned long host_bndcfgs;
7893         struct desc_ptr dt;
7894         int r, i, ept_lpage_level;
7895
7896         store_idt(&dt);
7897         host_idt_base = dt.address;
7898
7899         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7900                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7901
7902         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7903                 return -EIO;
7904
7905         if (boot_cpu_has(X86_FEATURE_NX))
7906                 kvm_enable_efer_bits(EFER_NX);
7907
7908         if (boot_cpu_has(X86_FEATURE_MPX)) {
7909                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7910                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7911         }
7912
7913         if (!cpu_has_vmx_mpx())
7914                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7915                                     XFEATURE_MASK_BNDCSR);
7916
7917         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7918             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7919                 enable_vpid = 0;
7920
7921         if (!cpu_has_vmx_ept() ||
7922             !cpu_has_vmx_ept_4levels() ||
7923             !cpu_has_vmx_ept_mt_wb() ||
7924             !cpu_has_vmx_invept_global())
7925                 enable_ept = 0;
7926
7927         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7928                 enable_ept_ad_bits = 0;
7929
7930         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7931                 enable_unrestricted_guest = 0;
7932
7933         if (!cpu_has_vmx_flexpriority())
7934                 flexpriority_enabled = 0;
7935
7936         if (!cpu_has_virtual_nmis())
7937                 enable_vnmi = 0;
7938
7939         /*
7940          * set_apic_access_page_addr() is used to reload apic access
7941          * page upon invalidation.  No need to do anything if not
7942          * using the APIC_ACCESS_ADDR VMCS field.
7943          */
7944         if (!flexpriority_enabled)
7945                 vmx_x86_ops.set_apic_access_page_addr = NULL;
7946
7947         if (!cpu_has_vmx_tpr_shadow())
7948                 vmx_x86_ops.update_cr8_intercept = NULL;
7949
7950 #if IS_ENABLED(CONFIG_HYPERV)
7951         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7952             && enable_ept) {
7953                 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7954                 vmx_x86_ops.tlb_remote_flush_with_range =
7955                                 hv_remote_flush_tlb_with_range;
7956         }
7957 #endif
7958
7959         if (!cpu_has_vmx_ple()) {
7960                 ple_gap = 0;
7961                 ple_window = 0;
7962                 ple_window_grow = 0;
7963                 ple_window_max = 0;
7964                 ple_window_shrink = 0;
7965         }
7966
7967         if (!cpu_has_vmx_apicv()) {
7968                 enable_apicv = 0;
7969                 vmx_x86_ops.sync_pir_to_irr = NULL;
7970         }
7971
7972         if (cpu_has_vmx_tsc_scaling()) {
7973                 kvm_has_tsc_control = true;
7974                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7975                 kvm_tsc_scaling_ratio_frac_bits = 48;
7976         }
7977
7978         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7979
7980         if (enable_ept)
7981                 vmx_enable_tdp();
7982
7983         if (!enable_ept)
7984                 ept_lpage_level = 0;
7985         else if (cpu_has_vmx_ept_1g_page())
7986                 ept_lpage_level = PT_PDPE_LEVEL;
7987         else if (cpu_has_vmx_ept_2m_page())
7988                 ept_lpage_level = PT_DIRECTORY_LEVEL;
7989         else
7990                 ept_lpage_level = PT_PAGE_TABLE_LEVEL;
7991         kvm_configure_mmu(enable_ept, ept_lpage_level);
7992
7993         /*
7994          * Only enable PML when hardware supports PML feature, and both EPT
7995          * and EPT A/D bit features are enabled -- PML depends on them to work.
7996          */
7997         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7998                 enable_pml = 0;
7999
8000         if (!enable_pml) {
8001                 vmx_x86_ops.slot_enable_log_dirty = NULL;
8002                 vmx_x86_ops.slot_disable_log_dirty = NULL;
8003                 vmx_x86_ops.flush_log_dirty = NULL;
8004                 vmx_x86_ops.enable_log_dirty_pt_masked = NULL;
8005         }
8006
8007         if (!cpu_has_vmx_preemption_timer())
8008                 enable_preemption_timer = false;
8009
8010         if (enable_preemption_timer) {
8011                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
8012                 u64 vmx_msr;
8013
8014                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
8015                 cpu_preemption_timer_multi =
8016                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
8017
8018                 if (tsc_khz)
8019                         use_timer_freq = (u64)tsc_khz * 1000;
8020                 use_timer_freq >>= cpu_preemption_timer_multi;
8021
8022                 /*
8023                  * KVM "disables" the preemption timer by setting it to its max
8024                  * value.  Don't use the timer if it might cause spurious exits
8025                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
8026                  */
8027                 if (use_timer_freq > 0xffffffffu / 10)
8028                         enable_preemption_timer = false;
8029         }
8030
8031         if (!enable_preemption_timer) {
8032                 vmx_x86_ops.set_hv_timer = NULL;
8033                 vmx_x86_ops.cancel_hv_timer = NULL;
8034                 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
8035         }
8036
8037         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
8038
8039         kvm_mce_cap_supported |= MCG_LMCE_P;
8040
8041         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
8042                 return -EINVAL;
8043         if (!enable_ept || !cpu_has_vmx_intel_pt())
8044                 pt_mode = PT_MODE_SYSTEM;
8045
8046         if (nested) {
8047                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
8048                                            vmx_capability.ept);
8049
8050                 r = nested_vmx_hardware_setup(&vmx_x86_ops,
8051                                               kvm_vmx_exit_handlers);
8052                 if (r)
8053                         return r;
8054         }
8055
8056         vmx_set_cpu_caps();
8057
8058         r = alloc_kvm_area();
8059         if (r)
8060                 nested_vmx_hardware_unsetup();
8061         return r;
8062 }
8063
8064 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
8065         .cpu_has_kvm_support = cpu_has_kvm_support,
8066         .disabled_by_bios = vmx_disabled_by_bios,
8067         .check_processor_compatibility = vmx_check_processor_compat,
8068         .hardware_setup = hardware_setup,
8069
8070         .runtime_ops = &vmx_x86_ops,
8071 };
8072
8073 static void vmx_cleanup_l1d_flush(void)
8074 {
8075         if (vmx_l1d_flush_pages) {
8076                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
8077                 vmx_l1d_flush_pages = NULL;
8078         }
8079         /* Restore state so sysfs ignores VMX */
8080         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
8081 }
8082
8083 static void vmx_exit(void)
8084 {
8085 #ifdef CONFIG_KEXEC_CORE
8086         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8087         synchronize_rcu();
8088 #endif
8089
8090         kvm_exit();
8091
8092 #if IS_ENABLED(CONFIG_HYPERV)
8093         if (static_branch_unlikely(&enable_evmcs)) {
8094                 int cpu;
8095                 struct hv_vp_assist_page *vp_ap;
8096                 /*
8097                  * Reset everything to support using non-enlightened VMCS
8098                  * access later (e.g. when we reload the module with
8099                  * enlightened_vmcs=0)
8100                  */
8101                 for_each_online_cpu(cpu) {
8102                         vp_ap = hv_get_vp_assist_page(cpu);
8103
8104                         if (!vp_ap)
8105                                 continue;
8106
8107                         vp_ap->nested_control.features.directhypercall = 0;
8108                         vp_ap->current_nested_vmcs = 0;
8109                         vp_ap->enlighten_vmentry = 0;
8110                 }
8111
8112                 static_branch_disable(&enable_evmcs);
8113         }
8114 #endif
8115         vmx_cleanup_l1d_flush();
8116 }
8117 module_exit(vmx_exit);
8118
8119 static int __init vmx_init(void)
8120 {
8121         int r, cpu;
8122
8123 #if IS_ENABLED(CONFIG_HYPERV)
8124         /*
8125          * Enlightened VMCS usage should be recommended and the host needs
8126          * to support eVMCS v1 or above. We can also disable eVMCS support
8127          * with module parameter.
8128          */
8129         if (enlightened_vmcs &&
8130             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8131             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8132             KVM_EVMCS_VERSION) {
8133                 int cpu;
8134
8135                 /* Check that we have assist pages on all online CPUs */
8136                 for_each_online_cpu(cpu) {
8137                         if (!hv_get_vp_assist_page(cpu)) {
8138                                 enlightened_vmcs = false;
8139                                 break;
8140                         }
8141                 }
8142
8143                 if (enlightened_vmcs) {
8144                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8145                         static_branch_enable(&enable_evmcs);
8146                 }
8147
8148                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8149                         vmx_x86_ops.enable_direct_tlbflush
8150                                 = hv_enable_direct_tlbflush;
8151
8152         } else {
8153                 enlightened_vmcs = false;
8154         }
8155 #endif
8156
8157         r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
8158                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8159         if (r)
8160                 return r;
8161
8162         /*
8163          * Must be called after kvm_init() so enable_ept is properly set
8164          * up. Hand the parameter mitigation value in which was stored in
8165          * the pre module init parser. If no parameter was given, it will
8166          * contain 'auto' which will be turned into the default 'cond'
8167          * mitigation mode.
8168          */
8169         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8170         if (r) {
8171                 vmx_exit();
8172                 return r;
8173         }
8174
8175         for_each_possible_cpu(cpu) {
8176                 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8177                 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
8178                 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8179         }
8180
8181 #ifdef CONFIG_KEXEC_CORE
8182         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8183                            crash_vmclear_local_loaded_vmcss);
8184 #endif
8185         vmx_check_vmcs12_offsets();
8186
8187         return 0;
8188 }
8189 module_init(vmx_init);