arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/frame.h>
  17 #include <linux/highmem.h>
  18 #include <linux/hrtimer.h>
  19 #include <linux/kernel.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/mm.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30 #include <linux/entry-kvm.h>
  31
  32 #include <asm/apic.h>
  33 #include <asm/asm.h>
  34 #include <asm/cpu.h>
  35 #include <asm/cpu_device_id.h>
  36 #include <asm/debugreg.h>
  37 #include <asm/desc.h>
  38 #include <asm/fpu/internal.h>
  39 #include <asm/io.h>
  40 #include <asm/irq_remapping.h>
  41 #include <asm/kexec.h>
  42 #include <asm/perf_event.h>
  43 #include <asm/mce.h>
  44 #include <asm/mmu_context.h>
  45 #include <asm/mshyperv.h>
  46 #include <asm/mwait.h>
  47 #include <asm/spec-ctrl.h>
  48 #include <asm/virtext.h>
  49 #include <asm/vmx.h>
  50
  51 #include "capabilities.h"
  52 #include "cpuid.h"
  53 #include "evmcs.h"
  54 #include "irq.h"
  55 #include "kvm_cache_regs.h"
  56 #include "lapic.h"
  57 #include "mmu.h"
  58 #include "nested.h"
  59 #include "ops.h"
  60 #include "pmu.h"
  61 #include "trace.h"
  62 #include "vmcs.h"
  63 #include "vmcs12.h"
  64 #include "vmx.h"
  65 #include "x86.h"
  66
  67 MODULE_AUTHOR("Qumranet");
  68 MODULE_LICENSE("GPL");
  69
  70 #ifdef MODULE
  71 static const struct x86_cpu_id vmx_cpu_id[] = {
  72         X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
  73         {}
  74 };
  75 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  76 #endif
  77
  78 bool __read_mostly enable_vpid = 1;
  79 module_param_named(vpid, enable_vpid, bool, 0444);
  80
  81 static bool __read_mostly enable_vnmi = 1;
  82 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  83
  84 bool __read_mostly flexpriority_enabled = 1;
  85 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  86
  87 bool __read_mostly enable_ept = 1;
  88 module_param_named(ept, enable_ept, bool, S_IRUGO);
  89
  90 bool __read_mostly enable_unrestricted_guest = 1;
  91 module_param_named(unrestricted_guest,
  92                         enable_unrestricted_guest, bool, S_IRUGO);
  93
  94 bool __read_mostly enable_ept_ad_bits = 1;
  95 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  96
  97 static bool __read_mostly emulate_invalid_guest_state = true;
  98 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  99
 100 static bool __read_mostly fasteoi = 1;
 101 module_param(fasteoi, bool, S_IRUGO);
 102
 103 bool __read_mostly enable_apicv = 1;
 104 module_param(enable_apicv, bool, S_IRUGO);
 105
 106 /*
 107  * If nested=1, nested virtualization is supported, i.e., guests may use
 108  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 109  * use VMX instructions.
 110  */
 111 static bool __read_mostly nested = 1;
 112 module_param(nested, bool, S_IRUGO);
 113
 114 bool __read_mostly enable_pml = 1;
 115 module_param_named(pml, enable_pml, bool, S_IRUGO);
 116
 117 static bool __read_mostly dump_invalid_vmcs = 0;
 118 module_param(dump_invalid_vmcs, bool, 0644);
 119
 120 #define MSR_BITMAP_MODE_X2APIC          1
 121 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 122
 123 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 124
 125 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 126 static int __read_mostly cpu_preemption_timer_multi;
 127 static bool __read_mostly enable_preemption_timer = 1;
 128 #ifdef CONFIG_X86_64
 129 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 130 #endif
 131
 132 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 133 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 134 #define KVM_VM_CR0_ALWAYS_ON                            \
 135         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 136          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 137
 138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 141
 142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 143
 144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 145         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 146         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 147         RTIT_STATUS_BYTECNT))
 148
 149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
 150         (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
 151
 152 /*
 153  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 154  * ple_gap:    upper bound on the amount of time between two successive
 155  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 156  *             According to test, this time is usually smaller than 128 cycles.
 157  * ple_window: upper bound on the amount of time a guest is allowed to execute
 158  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 159  *             less than 2^12 cycles
 160  * Time is measured based on a counter that runs at the same rate as the TSC,
 161  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 162  */
 163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, uint, 0444);
 165
 166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, uint, 0444);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, uint, 0444);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, uint, 0444);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, uint, 0444);
 180
 181 /* Default is SYSTEM mode, 1 for host-guest mode */
 182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 183 module_param(pt_mode, int, S_IRUGO);
 184
 185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 188
 189 /* Storage for pre module init parameter parsing */
 190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 191
 192 static const struct {
 193         const char *option;
 194         bool for_parse;
 195 } vmentry_l1d_param[] = {
 196         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 197         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 198         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 199         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 200         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 201         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 202 };
 203
 204 #define L1D_CACHE_ORDER 4
 205 static void *vmx_l1d_flush_pages;
 206
 207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 208 {
 209         struct page *page;
 210         unsigned int i;
 211
 212         if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
 213                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 214                 return 0;
 215         }
 216
 217         if (!enable_ept) {
 218                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 219                 return 0;
 220         }
 221
 222         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 223                 u64 msr;
 224
 225                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 226                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 227                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 228                         return 0;
 229                 }
 230         }
 231
 232         /* If set to auto use the default l1tf mitigation method */
 233         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 234                 switch (l1tf_mitigation) {
 235                 case L1TF_MITIGATION_OFF:
 236                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 237                         break;
 238                 case L1TF_MITIGATION_FLUSH_NOWARN:
 239                 case L1TF_MITIGATION_FLUSH:
 240                 case L1TF_MITIGATION_FLUSH_NOSMT:
 241                         l1tf = VMENTER_L1D_FLUSH_COND;
 242                         break;
 243                 case L1TF_MITIGATION_FULL:
 244                 case L1TF_MITIGATION_FULL_FORCE:
 245                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 246                         break;
 247                 }
 248         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 249                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 250         }
 251
 252         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 253             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 254                 /*
 255                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 256                  * lifetime and so should not be charged to a memcg.
 257                  */
 258                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 259                 if (!page)
 260                         return -ENOMEM;
 261                 vmx_l1d_flush_pages = page_address(page);
 262
 263                 /*
 264                  * Initialize each page with a different pattern in
 265                  * order to protect against KSM in the nested
 266                  * virtualization case.
 267                  */
 268                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 269                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 270                                PAGE_SIZE);
 271                 }
 272         }
 273
 274         l1tf_vmx_mitigation = l1tf;
 275
 276         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 277                 static_branch_enable(&vmx_l1d_should_flush);
 278         else
 279                 static_branch_disable(&vmx_l1d_should_flush);
 280
 281         if (l1tf == VMENTER_L1D_FLUSH_COND)
 282                 static_branch_enable(&vmx_l1d_flush_cond);
 283         else
 284                 static_branch_disable(&vmx_l1d_flush_cond);
 285         return 0;
 286 }
 287
 288 static int vmentry_l1d_flush_parse(const char *s)
 289 {
 290         unsigned int i;
 291
 292         if (s) {
 293                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 294                         if (vmentry_l1d_param[i].for_parse &&
 295                             sysfs_streq(s, vmentry_l1d_param[i].option))
 296                                 return i;
 297                 }
 298         }
 299         return -EINVAL;
 300 }
 301
 302 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 303 {
 304         int l1tf, ret;
 305
 306         l1tf = vmentry_l1d_flush_parse(s);
 307         if (l1tf < 0)
 308                 return l1tf;
 309
 310         if (!boot_cpu_has(X86_BUG_L1TF))
 311                 return 0;
 312
 313         /*
 314          * Has vmx_init() run already? If not then this is the pre init
 315          * parameter parsing. In that case just store the value and let
 316          * vmx_init() do the proper setup after enable_ept has been
 317          * established.
 318          */
 319         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 320                 vmentry_l1d_flush_param = l1tf;
 321                 return 0;
 322         }
 323
 324         mutex_lock(&vmx_l1d_flush_mutex);
 325         ret = vmx_setup_l1d_flush(l1tf);
 326         mutex_unlock(&vmx_l1d_flush_mutex);
 327         return ret;
 328 }
 329
 330 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 331 {
 332         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 333                 return sprintf(s, "???\n");
 334
 335         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 336 }
 337
 338 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 339         .set = vmentry_l1d_flush_set,
 340         .get = vmentry_l1d_flush_get,
 341 };
 342 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 343
 344 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 345 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 346 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 347                                                           u32 msr, int type);
 348
 349 void vmx_vmexit(void);
 350
 351 #define vmx_insn_failed(fmt...)         \
 352 do {                                    \
 353         WARN_ONCE(1, fmt);              \
 354         pr_warn_ratelimited(fmt);       \
 355 } while (0)
 356
 357 asmlinkage void vmread_error(unsigned long field, bool fault)
 358 {
 359         if (fault)
 360                 kvm_spurious_fault();
 361         else
 362                 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
 363 }
 364
 365 noinline void vmwrite_error(unsigned long field, unsigned long value)
 366 {
 367         vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
 368                         field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 369 }
 370
 371 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 372 {
 373         vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
 374 }
 375
 376 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 377 {
 378         vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
 379 }
 380
 381 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
 382 {
 383         vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
 384                         ext, vpid, gva);
 385 }
 386
 387 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
 388 {
 389         vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
 390                         ext, eptp, gpa);
 391 }
 392
 393 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 394 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 395 /*
 396  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 397  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 398  */
 399 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 400
 401 /*
 402  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 403  * can find which vCPU should be waken up.
 404  */
 405 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 406 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 407
 408 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 409 static DEFINE_SPINLOCK(vmx_vpid_lock);
 410
 411 struct vmcs_config vmcs_config;
 412 struct vmx_capability vmx_capability;
 413
 414 #define VMX_SEGMENT_FIELD(seg)                                  \
 415         [VCPU_SREG_##seg] = {                                   \
 416                 .selector = GUEST_##seg##_SELECTOR,             \
 417                 .base = GUEST_##seg##_BASE,                     \
 418                 .limit = GUEST_##seg##_LIMIT,                   \
 419                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 420         }
 421
 422 static const struct kvm_vmx_segment_field {
 423         unsigned selector;
 424         unsigned base;
 425         unsigned limit;
 426         unsigned ar_bytes;
 427 } kvm_vmx_segment_fields[] = {
 428         VMX_SEGMENT_FIELD(CS),
 429         VMX_SEGMENT_FIELD(DS),
 430         VMX_SEGMENT_FIELD(ES),
 431         VMX_SEGMENT_FIELD(FS),
 432         VMX_SEGMENT_FIELD(GS),
 433         VMX_SEGMENT_FIELD(SS),
 434         VMX_SEGMENT_FIELD(TR),
 435         VMX_SEGMENT_FIELD(LDTR),
 436 };
 437
 438 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
 439 {
 440         vmx->segment_cache.bitmask = 0;
 441 }
 442
 443 static unsigned long host_idt_base;
 444
 445 /*
 446  * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
 447  * will emulate SYSCALL in legacy mode if the vendor string in guest
 448  * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
 449  * support this emulation, IA32_STAR must always be included in
 450  * vmx_msr_index[], even in i386 builds.
 451  */
 452 const u32 vmx_msr_index[] = {
 453 #ifdef CONFIG_X86_64
 454         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 455 #endif
 456         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 457         MSR_IA32_TSX_CTRL,
 458 };
 459
 460 #if IS_ENABLED(CONFIG_HYPERV)
 461 static bool __read_mostly enlightened_vmcs = true;
 462 module_param(enlightened_vmcs, bool, 0444);
 463
 464 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
 465 static void check_ept_pointer_match(struct kvm *kvm)
 466 {
 467         struct kvm_vcpu *vcpu;
 468         u64 tmp_eptp = INVALID_PAGE;
 469         int i;
 470
 471         kvm_for_each_vcpu(i, vcpu, kvm) {
 472                 if (!VALID_PAGE(tmp_eptp)) {
 473                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
 474                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
 475                         to_kvm_vmx(kvm)->ept_pointers_match
 476                                 = EPT_POINTERS_MISMATCH;
 477                         return;
 478                 }
 479         }
 480
 481         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
 482 }
 483
 484 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
 485                 void *data)
 486 {
 487         struct kvm_tlb_range *range = data;
 488
 489         return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
 490                         range->pages);
 491 }
 492
 493 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
 494                 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
 495 {
 496         u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
 497
 498         /*
 499          * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
 500          * of the base of EPT PML4 table, strip off EPT configuration
 501          * information.
 502          */
 503         if (range)
 504                 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
 505                                 kvm_fill_hv_flush_list_func, (void *)range);
 506         else
 507                 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
 508 }
 509
 510 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
 511                 struct kvm_tlb_range *range)
 512 {
 513         struct kvm_vcpu *vcpu;
 514         int ret = 0, i;
 515
 516         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 517
 518         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
 519                 check_ept_pointer_match(kvm);
 520
 521         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
 522                 kvm_for_each_vcpu(i, vcpu, kvm) {
 523                         /* If ept_pointer is invalid pointer, bypass flush request. */
 524                         if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
 525                                 ret |= __hv_remote_flush_tlb_with_range(
 526                                         kvm, vcpu, range);
 527                 }
 528         } else {
 529                 ret = __hv_remote_flush_tlb_with_range(kvm,
 530                                 kvm_get_vcpu(kvm, 0), range);
 531         }
 532
 533         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 534         return ret;
 535 }
 536 static int hv_remote_flush_tlb(struct kvm *kvm)
 537 {
 538         return hv_remote_flush_tlb_with_range(kvm, NULL);
 539 }
 540
 541 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 542 {
 543         struct hv_enlightened_vmcs *evmcs;
 544         struct hv_partition_assist_pg **p_hv_pa_pg =
 545                         &vcpu->kvm->arch.hyperv.hv_pa_pg;
 546         /*
 547          * Synthetic VM-Exit is not enabled in current code and so All
 548          * evmcs in singe VM shares same assist page.
 549          */
 550         if (!*p_hv_pa_pg)
 551                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
 552
 553         if (!*p_hv_pa_pg)
 554                 return -ENOMEM;
 555
 556         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 557
 558         evmcs->partition_assist_page =
 559                 __pa(*p_hv_pa_pg);
 560         evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
 561         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 562
 563         return 0;
 564 }
 565
 566 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 567
 568 /*
 569  * Comment's format: document - errata name - stepping - processor name.
 570  * Refer from
 571  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 572  */
 573 static u32 vmx_preemption_cpu_tfms[] = {
 574 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 575 0x000206E6,
 576 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 577 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 578 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 579 0x00020652,
 580 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 581 0x00020655,
 582 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 583 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 584 /*
 585  * 320767.pdf - AAP86  - B1 -
 586  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 587  */
 588 0x000106E5,
 589 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 590 0x000106A0,
 591 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 592 0x000106A1,
 593 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 594 0x000106A4,
 595  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 596  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 597  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 598 0x000106A5,
 599  /* Xeon E3-1220 V2 */
 600 0x000306A8,
 601 };
 602
 603 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 604 {
 605         u32 eax = cpuid_eax(0x00000001), i;
 606
 607         /* Clear the reserved bits */
 608         eax &= ~(0x3U << 14 | 0xfU << 28);
 609         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 610                 if (eax == vmx_preemption_cpu_tfms[i])
 611                         return true;
 612
 613         return false;
 614 }
 615
 616 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 617 {
 618         return flexpriority_enabled && lapic_in_kernel(vcpu);
 619 }
 620
 621 static inline bool report_flexpriority(void)
 622 {
 623         return flexpriority_enabled;
 624 }
 625
 626 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 627 {
 628         int i;
 629
 630         for (i = 0; i < vmx->nmsrs; ++i)
 631                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 632                         return i;
 633         return -1;
 634 }
 635
 636 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 637 {
 638         int i;
 639
 640         i = __find_msr_index(vmx, msr);
 641         if (i >= 0)
 642                 return &vmx->guest_msrs[i];
 643         return NULL;
 644 }
 645
 646 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data)
 647 {
 648         int ret = 0;
 649
 650         u64 old_msr_data = msr->data;
 651         msr->data = data;
 652         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
 653                 preempt_disable();
 654                 ret = kvm_set_shared_msr(msr->index, msr->data,
 655                                          msr->mask);
 656                 preempt_enable();
 657                 if (ret)
 658                         msr->data = old_msr_data;
 659         }
 660         return ret;
 661 }
 662
 663 #ifdef CONFIG_KEXEC_CORE
 664 static void crash_vmclear_local_loaded_vmcss(void)
 665 {
 666         int cpu = raw_smp_processor_id();
 667         struct loaded_vmcs *v;
 668
 669         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 670                             loaded_vmcss_on_cpu_link)
 671                 vmcs_clear(v->vmcs);
 672 }
 673 #endif /* CONFIG_KEXEC_CORE */
 674
 675 static void __loaded_vmcs_clear(void *arg)
 676 {
 677         struct loaded_vmcs *loaded_vmcs = arg;
 678         int cpu = raw_smp_processor_id();
 679
 680         if (loaded_vmcs->cpu != cpu)
 681                 return; /* vcpu migration can race with cpu offline */
 682         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 683                 per_cpu(current_vmcs, cpu) = NULL;
 684
 685         vmcs_clear(loaded_vmcs->vmcs);
 686         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 687                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 688
 689         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 690
 691         /*
 692          * Ensure all writes to loaded_vmcs, including deleting it from its
 693          * current percpu list, complete before setting loaded_vmcs->vcpu to
 694          * -1, otherwise a different cpu can see vcpu == -1 first and add
 695          * loaded_vmcs to its percpu list before it's deleted from this cpu's
 696          * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
 697          */
 698         smp_wmb();
 699
 700         loaded_vmcs->cpu = -1;
 701         loaded_vmcs->launched = 0;
 702 }
 703
 704 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 705 {
 706         int cpu = loaded_vmcs->cpu;
 707
 708         if (cpu != -1)
 709                 smp_call_function_single(cpu,
 710                          __loaded_vmcs_clear, loaded_vmcs, 1);
 711 }
 712
 713 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 714                                        unsigned field)
 715 {
 716         bool ret;
 717         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 718
 719         if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
 720                 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
 721                 vmx->segment_cache.bitmask = 0;
 722         }
 723         ret = vmx->segment_cache.bitmask & mask;
 724         vmx->segment_cache.bitmask |= mask;
 725         return ret;
 726 }
 727
 728 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 729 {
 730         u16 *p = &vmx->segment_cache.seg[seg].selector;
 731
 732         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 733                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 734         return *p;
 735 }
 736
 737 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 738 {
 739         ulong *p = &vmx->segment_cache.seg[seg].base;
 740
 741         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 742                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 743         return *p;
 744 }
 745
 746 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 747 {
 748         u32 *p = &vmx->segment_cache.seg[seg].limit;
 749
 750         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 751                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 752         return *p;
 753 }
 754
 755 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 756 {
 757         u32 *p = &vmx->segment_cache.seg[seg].ar;
 758
 759         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 760                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 761         return *p;
 762 }
 763
 764 void update_exception_bitmap(struct kvm_vcpu *vcpu)
 765 {
 766         u32 eb;
 767
 768         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 769              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 770         /*
 771          * Guest access to VMware backdoor ports could legitimately
 772          * trigger #GP because of TSS I/O permission bitmap.
 773          * We intercept those #GP and allow access to them anyway
 774          * as VMware does.
 775          */
 776         if (enable_vmware_backdoor)
 777                 eb |= (1u << GP_VECTOR);
 778         if ((vcpu->guest_debug &
 779              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 780             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 781                 eb |= 1u << BP_VECTOR;
 782         if (to_vmx(vcpu)->rmode.vm86_active)
 783                 eb = ~0;
 784         if (!vmx_need_pf_intercept(vcpu))
 785                 eb &= ~(1u << PF_VECTOR);
 786
 787         /* When we are running a nested L2 guest and L1 specified for it a
 788          * certain exception bitmap, we must trap the same exceptions and pass
 789          * them to L1. When running L2, we will only handle the exceptions
 790          * specified above if L1 did not want them.
 791          */
 792         if (is_guest_mode(vcpu))
 793                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 794
 795         vmcs_write32(EXCEPTION_BITMAP, eb);
 796 }
 797
 798 /*
 799  * Check if MSR is intercepted for currently loaded MSR bitmap.
 800  */
 801 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 802 {
 803         unsigned long *msr_bitmap;
 804         int f = sizeof(unsigned long);
 805
 806         if (!cpu_has_vmx_msr_bitmap())
 807                 return true;
 808
 809         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 810
 811         if (msr <= 0x1fff) {
 812                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 813         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 814                 msr &= 0x1fff;
 815                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 816         }
 817
 818         return true;
 819 }
 820
 821 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 822                 unsigned long entry, unsigned long exit)
 823 {
 824         vm_entry_controls_clearbit(vmx, entry);
 825         vm_exit_controls_clearbit(vmx, exit);
 826 }
 827
 828 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr)
 829 {
 830         unsigned int i;
 831
 832         for (i = 0; i < m->nr; ++i) {
 833                 if (m->val[i].index == msr)
 834                         return i;
 835         }
 836         return -ENOENT;
 837 }
 838
 839 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 840 {
 841         int i;
 842         struct msr_autoload *m = &vmx->msr_autoload;
 843
 844         switch (msr) {
 845         case MSR_EFER:
 846                 if (cpu_has_load_ia32_efer()) {
 847                         clear_atomic_switch_msr_special(vmx,
 848                                         VM_ENTRY_LOAD_IA32_EFER,
 849                                         VM_EXIT_LOAD_IA32_EFER);
 850                         return;
 851                 }
 852                 break;
 853         case MSR_CORE_PERF_GLOBAL_CTRL:
 854                 if (cpu_has_load_perf_global_ctrl()) {
 855                         clear_atomic_switch_msr_special(vmx,
 856                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 857                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 858                         return;
 859                 }
 860                 break;
 861         }
 862         i = vmx_find_msr_index(&m->guest, msr);
 863         if (i < 0)
 864                 goto skip_guest;
 865         --m->guest.nr;
 866         m->guest.val[i] = m->guest.val[m->guest.nr];
 867         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 868
 869 skip_guest:
 870         i = vmx_find_msr_index(&m->host, msr);
 871         if (i < 0)
 872                 return;
 873
 874         --m->host.nr;
 875         m->host.val[i] = m->host.val[m->host.nr];
 876         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 877 }
 878
 879 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 880                 unsigned long entry, unsigned long exit,
 881                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 882                 u64 guest_val, u64 host_val)
 883 {
 884         vmcs_write64(guest_val_vmcs, guest_val);
 885         if (host_val_vmcs != HOST_IA32_EFER)
 886                 vmcs_write64(host_val_vmcs, host_val);
 887         vm_entry_controls_setbit(vmx, entry);
 888         vm_exit_controls_setbit(vmx, exit);
 889 }
 890
 891 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 892                                   u64 guest_val, u64 host_val, bool entry_only)
 893 {
 894         int i, j = 0;
 895         struct msr_autoload *m = &vmx->msr_autoload;
 896
 897         switch (msr) {
 898         case MSR_EFER:
 899                 if (cpu_has_load_ia32_efer()) {
 900                         add_atomic_switch_msr_special(vmx,
 901                                         VM_ENTRY_LOAD_IA32_EFER,
 902                                         VM_EXIT_LOAD_IA32_EFER,
 903                                         GUEST_IA32_EFER,
 904                                         HOST_IA32_EFER,
 905                                         guest_val, host_val);
 906                         return;
 907                 }
 908                 break;
 909         case MSR_CORE_PERF_GLOBAL_CTRL:
 910                 if (cpu_has_load_perf_global_ctrl()) {
 911                         add_atomic_switch_msr_special(vmx,
 912                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 913                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 914                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 915                                         HOST_IA32_PERF_GLOBAL_CTRL,
 916                                         guest_val, host_val);
 917                         return;
 918                 }
 919                 break;
 920         case MSR_IA32_PEBS_ENABLE:
 921                 /* PEBS needs a quiescent period after being disabled (to write
 922                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 923                  * provide that period, so a CPU could write host's record into
 924                  * guest's memory.
 925                  */
 926                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 927         }
 928
 929         i = vmx_find_msr_index(&m->guest, msr);
 930         if (!entry_only)
 931                 j = vmx_find_msr_index(&m->host, msr);
 932
 933         if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) ||
 934                 (j < 0 &&  m->host.nr == NR_LOADSTORE_MSRS)) {
 935                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 936                                 "Can't add msr %x\n", msr);
 937                 return;
 938         }
 939         if (i < 0) {
 940                 i = m->guest.nr++;
 941                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 942         }
 943         m->guest.val[i].index = msr;
 944         m->guest.val[i].value = guest_val;
 945
 946         if (entry_only)
 947                 return;
 948
 949         if (j < 0) {
 950                 j = m->host.nr++;
 951                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 952         }
 953         m->host.val[j].index = msr;
 954         m->host.val[j].value = host_val;
 955 }
 956
 957 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 958 {
 959         u64 guest_efer = vmx->vcpu.arch.efer;
 960         u64 ignore_bits = 0;
 961
 962         /* Shadow paging assumes NX to be available.  */
 963         if (!enable_ept)
 964                 guest_efer |= EFER_NX;
 965
 966         /*
 967          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 968          */
 969         ignore_bits |= EFER_SCE;
 970 #ifdef CONFIG_X86_64
 971         ignore_bits |= EFER_LMA | EFER_LME;
 972         /* SCE is meaningful only in long mode on Intel */
 973         if (guest_efer & EFER_LMA)
 974                 ignore_bits &= ~(u64)EFER_SCE;
 975 #endif
 976
 977         /*
 978          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 979          * On CPUs that support "load IA32_EFER", always switch EFER
 980          * atomically, since it's faster than switching it manually.
 981          */
 982         if (cpu_has_load_ia32_efer() ||
 983             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 984                 if (!(guest_efer & EFER_LMA))
 985                         guest_efer &= ~EFER_LME;
 986                 if (guest_efer != host_efer)
 987                         add_atomic_switch_msr(vmx, MSR_EFER,
 988                                               guest_efer, host_efer, false);
 989                 else
 990                         clear_atomic_switch_msr(vmx, MSR_EFER);
 991                 return false;
 992         } else {
 993                 clear_atomic_switch_msr(vmx, MSR_EFER);
 994
 995                 guest_efer &= ~ignore_bits;
 996                 guest_efer |= host_efer & ignore_bits;
 997
 998                 vmx->guest_msrs[efer_offset].data = guest_efer;
 999                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1000
1001                 return true;
1002         }
1003 }
1004
1005 #ifdef CONFIG_X86_32
1006 /*
1007  * On 32-bit kernels, VM exits still load the FS and GS bases from the
1008  * VMCS rather than the segment table.  KVM uses this helper to figure
1009  * out the current bases to poke them into the VMCS before entry.
1010  */
1011 static unsigned long segment_base(u16 selector)
1012 {
1013         struct desc_struct *table;
1014         unsigned long v;
1015
1016         if (!(selector & ~SEGMENT_RPL_MASK))
1017                 return 0;
1018
1019         table = get_current_gdt_ro();
1020
1021         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1022                 u16 ldt_selector = kvm_read_ldt();
1023
1024                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1025                         return 0;
1026
1027                 table = (struct desc_struct *)segment_base(ldt_selector);
1028         }
1029         v = get_desc_base(&table[selector >> 3]);
1030         return v;
1031 }
1032 #endif
1033
1034 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1035 {
1036         return vmx_pt_mode_is_host_guest() &&
1037                !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1038 }
1039
1040 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1041 {
1042         u32 i;
1043
1044         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1045         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1046         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1047         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1048         for (i = 0; i < addr_range; i++) {
1049                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1050                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1051         }
1052 }
1053
1054 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1055 {
1056         u32 i;
1057
1058         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1059         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1060         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1061         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1062         for (i = 0; i < addr_range; i++) {
1063                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1064                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1065         }
1066 }
1067
1068 static void pt_guest_enter(struct vcpu_vmx *vmx)
1069 {
1070         if (vmx_pt_mode_is_system())
1071                 return;
1072
1073         /*
1074          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1075          * Save host state before VM entry.
1076          */
1077         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1078         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1079                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1080                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1081                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1082         }
1083 }
1084
1085 static void pt_guest_exit(struct vcpu_vmx *vmx)
1086 {
1087         if (vmx_pt_mode_is_system())
1088                 return;
1089
1090         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1091                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1092                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1093         }
1094
1095         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1096         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1097 }
1098
1099 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1100                         unsigned long fs_base, unsigned long gs_base)
1101 {
1102         if (unlikely(fs_sel != host->fs_sel)) {
1103                 if (!(fs_sel & 7))
1104                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1105                 else
1106                         vmcs_write16(HOST_FS_SELECTOR, 0);
1107                 host->fs_sel = fs_sel;
1108         }
1109         if (unlikely(gs_sel != host->gs_sel)) {
1110                 if (!(gs_sel & 7))
1111                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1112                 else
1113                         vmcs_write16(HOST_GS_SELECTOR, 0);
1114                 host->gs_sel = gs_sel;
1115         }
1116         if (unlikely(fs_base != host->fs_base)) {
1117                 vmcs_writel(HOST_FS_BASE, fs_base);
1118                 host->fs_base = fs_base;
1119         }
1120         if (unlikely(gs_base != host->gs_base)) {
1121                 vmcs_writel(HOST_GS_BASE, gs_base);
1122                 host->gs_base = gs_base;
1123         }
1124 }
1125
1126 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1127 {
1128         struct vcpu_vmx *vmx = to_vmx(vcpu);
1129         struct vmcs_host_state *host_state;
1130 #ifdef CONFIG_X86_64
1131         int cpu = raw_smp_processor_id();
1132 #endif
1133         unsigned long fs_base, gs_base;
1134         u16 fs_sel, gs_sel;
1135         int i;
1136
1137         vmx->req_immediate_exit = false;
1138
1139         /*
1140          * Note that guest MSRs to be saved/restored can also be changed
1141          * when guest state is loaded. This happens when guest transitions
1142          * to/from long-mode by setting MSR_EFER.LMA.
1143          */
1144         if (!vmx->guest_msrs_ready) {
1145                 vmx->guest_msrs_ready = true;
1146                 for (i = 0; i < vmx->save_nmsrs; ++i)
1147                         kvm_set_shared_msr(vmx->guest_msrs[i].index,
1148                                            vmx->guest_msrs[i].data,
1149                                            vmx->guest_msrs[i].mask);
1150
1151         }
1152
1153         if (vmx->nested.need_vmcs12_to_shadow_sync)
1154                 nested_sync_vmcs12_to_shadow(vcpu);
1155
1156         if (vmx->guest_state_loaded)
1157                 return;
1158
1159         host_state = &vmx->loaded_vmcs->host_state;
1160
1161         /*
1162          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1163          * allow segment selectors with cpl > 0 or ti == 1.
1164          */
1165         host_state->ldt_sel = kvm_read_ldt();
1166
1167 #ifdef CONFIG_X86_64
1168         savesegment(ds, host_state->ds_sel);
1169         savesegment(es, host_state->es_sel);
1170
1171         gs_base = cpu_kernelmode_gs_base(cpu);
1172         if (likely(is_64bit_mm(current->mm))) {
1173                 current_save_fsgs();
1174                 fs_sel = current->thread.fsindex;
1175                 gs_sel = current->thread.gsindex;
1176                 fs_base = current->thread.fsbase;
1177                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1178         } else {
1179                 savesegment(fs, fs_sel);
1180                 savesegment(gs, gs_sel);
1181                 fs_base = read_msr(MSR_FS_BASE);
1182                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1183         }
1184
1185         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1186 #else
1187         savesegment(fs, fs_sel);
1188         savesegment(gs, gs_sel);
1189         fs_base = segment_base(fs_sel);
1190         gs_base = segment_base(gs_sel);
1191 #endif
1192
1193         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1194         vmx->guest_state_loaded = true;
1195 }
1196
1197 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1198 {
1199         struct vmcs_host_state *host_state;
1200
1201         if (!vmx->guest_state_loaded)
1202                 return;
1203
1204         host_state = &vmx->loaded_vmcs->host_state;
1205
1206         ++vmx->vcpu.stat.host_state_reload;
1207
1208 #ifdef CONFIG_X86_64
1209         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1210 #endif
1211         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1212                 kvm_load_ldt(host_state->ldt_sel);
1213 #ifdef CONFIG_X86_64
1214                 load_gs_index(host_state->gs_sel);
1215 #else
1216                 loadsegment(gs, host_state->gs_sel);
1217 #endif
1218         }
1219         if (host_state->fs_sel & 7)
1220                 loadsegment(fs, host_state->fs_sel);
1221 #ifdef CONFIG_X86_64
1222         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1223                 loadsegment(ds, host_state->ds_sel);
1224                 loadsegment(es, host_state->es_sel);
1225         }
1226 #endif
1227         invalidate_tss_limit();
1228 #ifdef CONFIG_X86_64
1229         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1230 #endif
1231         load_fixmap_gdt(raw_smp_processor_id());
1232         vmx->guest_state_loaded = false;
1233         vmx->guest_msrs_ready = false;
1234 }
1235
1236 #ifdef CONFIG_X86_64
1237 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1238 {
1239         preempt_disable();
1240         if (vmx->guest_state_loaded)
1241                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1242         preempt_enable();
1243         return vmx->msr_guest_kernel_gs_base;
1244 }
1245
1246 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1247 {
1248         preempt_disable();
1249         if (vmx->guest_state_loaded)
1250                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1251         preempt_enable();
1252         vmx->msr_guest_kernel_gs_base = data;
1253 }
1254 #endif
1255
1256 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1257 {
1258         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1259         struct pi_desc old, new;
1260         unsigned int dest;
1261
1262         /*
1263          * In case of hot-plug or hot-unplug, we may have to undo
1264          * vmx_vcpu_pi_put even if there is no assigned device.  And we
1265          * always keep PI.NDST up to date for simplicity: it makes the
1266          * code easier, and CPU migration is not a fast path.
1267          */
1268         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1269                 return;
1270
1271         /*
1272          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1273          * PI.NDST: pi_post_block is the one expected to change PID.NDST and the
1274          * wakeup handler expects the vCPU to be on the blocked_vcpu_list that
1275          * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up
1276          * correctly.
1277          */
1278         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) {
1279                 pi_clear_sn(pi_desc);
1280                 goto after_clear_sn;
1281         }
1282
1283         /* The full case.  */
1284         do {
1285                 old.control = new.control = pi_desc->control;
1286
1287                 dest = cpu_physical_id(cpu);
1288
1289                 if (x2apic_enabled())
1290                         new.ndst = dest;
1291                 else
1292                         new.ndst = (dest << 8) & 0xFF00;
1293
1294                 new.sn = 0;
1295         } while (cmpxchg64(&pi_desc->control, old.control,
1296                            new.control) != old.control);
1297
1298 after_clear_sn:
1299
1300         /*
1301          * Clear SN before reading the bitmap.  The VT-d firmware
1302          * writes the bitmap and reads SN atomically (5.2.3 in the
1303          * spec), so it doesn't really have a memory barrier that
1304          * pairs with this, but we cannot do that and we need one.
1305          */
1306         smp_mb__after_atomic();
1307
1308         if (!pi_is_pir_empty(pi_desc))
1309                 pi_set_on(pi_desc);
1310 }
1311
1312 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1313                         struct loaded_vmcs *buddy)
1314 {
1315         struct vcpu_vmx *vmx = to_vmx(vcpu);
1316         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1317         struct vmcs *prev;
1318
1319         if (!already_loaded) {
1320                 loaded_vmcs_clear(vmx->loaded_vmcs);
1321                 local_irq_disable();
1322
1323                 /*
1324                  * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1325                  * this cpu's percpu list, otherwise it may not yet be deleted
1326                  * from its previous cpu's percpu list.  Pairs with the
1327                  * smb_wmb() in __loaded_vmcs_clear().
1328                  */
1329                 smp_rmb();
1330
1331                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1332                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1333                 local_irq_enable();
1334         }
1335
1336         prev = per_cpu(current_vmcs, cpu);
1337         if (prev != vmx->loaded_vmcs->vmcs) {
1338                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1339                 vmcs_load(vmx->loaded_vmcs->vmcs);
1340
1341                 /*
1342                  * No indirect branch prediction barrier needed when switching
1343                  * the active VMCS within a guest, e.g. on nested VM-Enter.
1344                  * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1345                  */
1346                 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1347                         indirect_branch_prediction_barrier();
1348         }
1349
1350         if (!already_loaded) {
1351                 void *gdt = get_current_gdt_ro();
1352                 unsigned long sysenter_esp;
1353
1354                 /*
1355                  * Flush all EPTP/VPID contexts, the new pCPU may have stale
1356                  * TLB entries from its previous association with the vCPU.
1357                  */
1358                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1359
1360                 /*
1361                  * Linux uses per-cpu TSS and GDT, so set these when switching
1362                  * processors.  See 22.2.4.
1363                  */
1364                 vmcs_writel(HOST_TR_BASE,
1365                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1366                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1367
1368                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1369                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1370
1371                 vmx->loaded_vmcs->cpu = cpu;
1372         }
1373
1374         /* Setup TSC multiplier */
1375         if (kvm_has_tsc_control &&
1376             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1377                 decache_tsc_multiplier(vmx);
1378 }
1379
1380 /*
1381  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1382  * vcpu mutex is already taken.
1383  */
1384 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1385 {
1386         struct vcpu_vmx *vmx = to_vmx(vcpu);
1387
1388         vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1389
1390         vmx_vcpu_pi_load(vcpu, cpu);
1391
1392         vmx->host_debugctlmsr = get_debugctlmsr();
1393 }
1394
1395 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1396 {
1397         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1398
1399         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1400                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
1401                 !kvm_vcpu_apicv_active(vcpu))
1402                 return;
1403
1404         /* Set SN when the vCPU is preempted */
1405         if (vcpu->preempted)
1406                 pi_set_sn(pi_desc);
1407 }
1408
1409 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1410 {
1411         vmx_vcpu_pi_put(vcpu);
1412
1413         vmx_prepare_switch_to_host(to_vmx(vcpu));
1414 }
1415
1416 static bool emulation_required(struct kvm_vcpu *vcpu)
1417 {
1418         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1419 }
1420
1421 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1422 {
1423         struct vcpu_vmx *vmx = to_vmx(vcpu);
1424         unsigned long rflags, save_rflags;
1425
1426         if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1427                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1428                 rflags = vmcs_readl(GUEST_RFLAGS);
1429                 if (vmx->rmode.vm86_active) {
1430                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1431                         save_rflags = vmx->rmode.save_rflags;
1432                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1433                 }
1434                 vmx->rflags = rflags;
1435         }
1436         return vmx->rflags;
1437 }
1438
1439 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1440 {
1441         struct vcpu_vmx *vmx = to_vmx(vcpu);
1442         unsigned long old_rflags;
1443
1444         if (enable_unrestricted_guest) {
1445                 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1446                 vmx->rflags = rflags;
1447                 vmcs_writel(GUEST_RFLAGS, rflags);
1448                 return;
1449         }
1450
1451         old_rflags = vmx_get_rflags(vcpu);
1452         vmx->rflags = rflags;
1453         if (vmx->rmode.vm86_active) {
1454                 vmx->rmode.save_rflags = rflags;
1455                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1456         }
1457         vmcs_writel(GUEST_RFLAGS, rflags);
1458
1459         if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1460                 vmx->emulation_required = emulation_required(vcpu);
1461 }
1462
1463 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1464 {
1465         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1466         int ret = 0;
1467
1468         if (interruptibility & GUEST_INTR_STATE_STI)
1469                 ret |= KVM_X86_SHADOW_INT_STI;
1470         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1471                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1472
1473         return ret;
1474 }
1475
1476 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1477 {
1478         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1479         u32 interruptibility = interruptibility_old;
1480
1481         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1482
1483         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1484                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1485         else if (mask & KVM_X86_SHADOW_INT_STI)
1486                 interruptibility |= GUEST_INTR_STATE_STI;
1487
1488         if ((interruptibility != interruptibility_old))
1489                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1490 }
1491
1492 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1493 {
1494         struct vcpu_vmx *vmx = to_vmx(vcpu);
1495         unsigned long value;
1496
1497         /*
1498          * Any MSR write that attempts to change bits marked reserved will
1499          * case a #GP fault.
1500          */
1501         if (data & vmx->pt_desc.ctl_bitmask)
1502                 return 1;
1503
1504         /*
1505          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1506          * result in a #GP unless the same write also clears TraceEn.
1507          */
1508         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1509                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1510                 return 1;
1511
1512         /*
1513          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1514          * and FabricEn would cause #GP, if
1515          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1516          */
1517         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1518                 !(data & RTIT_CTL_FABRIC_EN) &&
1519                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1520                                         PT_CAP_single_range_output))
1521                 return 1;
1522
1523         /*
1524          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1525          * utilize encodings marked reserved will casue a #GP fault.
1526          */
1527         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1528         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1529                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1530                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1531                 return 1;
1532         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1533                                                 PT_CAP_cycle_thresholds);
1534         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1535                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1536                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1537                 return 1;
1538         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1539         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1540                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1541                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1542                 return 1;
1543
1544         /*
1545          * If ADDRx_CFG is reserved or the encodings is >2 will
1546          * cause a #GP fault.
1547          */
1548         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1549         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1550                 return 1;
1551         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1552         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1553                 return 1;
1554         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1555         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1556                 return 1;
1557         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1558         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1559                 return 1;
1560
1561         return 0;
1562 }
1563
1564 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1565 {
1566         unsigned long rip, orig_rip;
1567
1568         /*
1569          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1570          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1571          * set when EPT misconfig occurs.  In practice, real hardware updates
1572          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1573          * (namely Hyper-V) don't set it due to it being undefined behavior,
1574          * i.e. we end up advancing IP with some random value.
1575          */
1576         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1577             to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1578                 orig_rip = kvm_rip_read(vcpu);
1579                 rip = orig_rip + vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1580 #ifdef CONFIG_X86_64
1581                 /*
1582                  * We need to mask out the high 32 bits of RIP if not in 64-bit
1583                  * mode, but just finding out that we are in 64-bit mode is
1584                  * quite expensive.  Only do it if there was a carry.
1585                  */
1586                 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1587                         rip = (u32)rip;
1588 #endif
1589                 kvm_rip_write(vcpu, rip);
1590         } else {
1591                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1592                         return 0;
1593         }
1594
1595         /* skipping an emulated instruction also counts */
1596         vmx_set_interrupt_shadow(vcpu, 0);
1597
1598         return 1;
1599 }
1600
1601 /*
1602  * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
1603  * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
1604  * indicates whether exit to userspace is needed.
1605  */
1606 int vmx_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
1607                               struct x86_exception *e)
1608 {
1609         if (r == X86EMUL_PROPAGATE_FAULT) {
1610                 kvm_inject_emulated_page_fault(vcpu, e);
1611                 return 1;
1612         }
1613
1614         /*
1615          * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
1616          * while handling a VMX instruction KVM could've handled the request
1617          * correctly by exiting to userspace and performing I/O but there
1618          * doesn't seem to be a real use-case behind such requests, just return
1619          * KVM_EXIT_INTERNAL_ERROR for now.
1620          */
1621         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1622         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
1623         vcpu->run->internal.ndata = 0;
1624
1625         return 0;
1626 }
1627
1628 /*
1629  * Recognizes a pending MTF VM-exit and records the nested state for later
1630  * delivery.
1631  */
1632 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1633 {
1634         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1635         struct vcpu_vmx *vmx = to_vmx(vcpu);
1636
1637         if (!is_guest_mode(vcpu))
1638                 return;
1639
1640         /*
1641          * Per the SDM, MTF takes priority over debug-trap exceptions besides
1642          * T-bit traps. As instruction emulation is completed (i.e. at the
1643          * instruction boundary), any #DB exception pending delivery must be a
1644          * debug-trap. Record the pending MTF state to be delivered in
1645          * vmx_check_nested_events().
1646          */
1647         if (nested_cpu_has_mtf(vmcs12) &&
1648             (!vcpu->arch.exception.pending ||
1649              vcpu->arch.exception.nr == DB_VECTOR))
1650                 vmx->nested.mtf_pending = true;
1651         else
1652                 vmx->nested.mtf_pending = false;
1653 }
1654
1655 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1656 {
1657         vmx_update_emulated_instruction(vcpu);
1658         return skip_emulated_instruction(vcpu);
1659 }
1660
1661 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1662 {
1663         /*
1664          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1665          * explicitly skip the instruction because if the HLT state is set,
1666          * then the instruction is already executing and RIP has already been
1667          * advanced.
1668          */
1669         if (kvm_hlt_in_guest(vcpu->kvm) &&
1670                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1671                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1672 }
1673
1674 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1675 {
1676         struct vcpu_vmx *vmx = to_vmx(vcpu);
1677         unsigned nr = vcpu->arch.exception.nr;
1678         bool has_error_code = vcpu->arch.exception.has_error_code;
1679         u32 error_code = vcpu->arch.exception.error_code;
1680         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1681
1682         kvm_deliver_exception_payload(vcpu);
1683
1684         if (has_error_code) {
1685                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1686                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1687         }
1688
1689         if (vmx->rmode.vm86_active) {
1690                 int inc_eip = 0;
1691                 if (kvm_exception_is_soft(nr))
1692                         inc_eip = vcpu->arch.event_exit_inst_len;
1693                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1694                 return;
1695         }
1696
1697         WARN_ON_ONCE(vmx->emulation_required);
1698
1699         if (kvm_exception_is_soft(nr)) {
1700                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1701                              vmx->vcpu.arch.event_exit_inst_len);
1702                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1703         } else
1704                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1705
1706         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1707
1708         vmx_clear_hlt(vcpu);
1709 }
1710
1711 /*
1712  * Swap MSR entry in host/guest MSR entry array.
1713  */
1714 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1715 {
1716         struct shared_msr_entry tmp;
1717
1718         tmp = vmx->guest_msrs[to];
1719         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1720         vmx->guest_msrs[from] = tmp;
1721 }
1722
1723 /*
1724  * Set up the vmcs to automatically save and restore system
1725  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1726  * mode, as fiddling with msrs is very expensive.
1727  */
1728 static void setup_msrs(struct vcpu_vmx *vmx)
1729 {
1730         int save_nmsrs, index;
1731
1732         save_nmsrs = 0;
1733 #ifdef CONFIG_X86_64
1734         /*
1735          * The SYSCALL MSRs are only needed on long mode guests, and only
1736          * when EFER.SCE is set.
1737          */
1738         if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1739                 index = __find_msr_index(vmx, MSR_STAR);
1740                 if (index >= 0)
1741                         move_msr_up(vmx, index, save_nmsrs++);
1742                 index = __find_msr_index(vmx, MSR_LSTAR);
1743                 if (index >= 0)
1744                         move_msr_up(vmx, index, save_nmsrs++);
1745                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1746                 if (index >= 0)
1747                         move_msr_up(vmx, index, save_nmsrs++);
1748         }
1749 #endif
1750         index = __find_msr_index(vmx, MSR_EFER);
1751         if (index >= 0 && update_transition_efer(vmx, index))
1752                 move_msr_up(vmx, index, save_nmsrs++);
1753         index = __find_msr_index(vmx, MSR_TSC_AUX);
1754         if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1755                 move_msr_up(vmx, index, save_nmsrs++);
1756         index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL);
1757         if (index >= 0)
1758                 move_msr_up(vmx, index, save_nmsrs++);
1759
1760         vmx->save_nmsrs = save_nmsrs;
1761         vmx->guest_msrs_ready = false;
1762
1763         if (cpu_has_vmx_msr_bitmap())
1764                 vmx_update_msr_bitmap(&vmx->vcpu);
1765 }
1766
1767 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1768 {
1769         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1770         u64 g_tsc_offset = 0;
1771
1772         /*
1773          * We're here if L1 chose not to trap WRMSR to TSC. According
1774          * to the spec, this should set L1's TSC; The offset that L1
1775          * set for L2 remains unchanged, and still needs to be added
1776          * to the newly set TSC to get L2's TSC.
1777          */
1778         if (is_guest_mode(vcpu) &&
1779             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1780                 g_tsc_offset = vmcs12->tsc_offset;
1781
1782         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1783                                    vcpu->arch.tsc_offset - g_tsc_offset,
1784                                    offset);
1785         vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1786         return offset + g_tsc_offset;
1787 }
1788
1789 /*
1790  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1791  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1792  * all guests if the "nested" module option is off, and can also be disabled
1793  * for a single guest by disabling its VMX cpuid bit.
1794  */
1795 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1796 {
1797         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1798 }
1799
1800 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1801                                                  uint64_t val)
1802 {
1803         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1804
1805         return !(val & ~valid_bits);
1806 }
1807
1808 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1809 {
1810         switch (msr->index) {
1811         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1812                 if (!nested)
1813                         return 1;
1814                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1815         case MSR_IA32_PERF_CAPABILITIES:
1816                 msr->data = vmx_get_perf_capabilities();
1817                 return 0;
1818         default:
1819                 return KVM_MSR_RET_INVALID;
1820         }
1821 }
1822
1823 /*
1824  * Reads an msr value (of 'msr_index') into 'pdata'.
1825  * Returns 0 on success, non-0 otherwise.
1826  * Assumes vcpu_load() was already called.
1827  */
1828 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1829 {
1830         struct vcpu_vmx *vmx = to_vmx(vcpu);
1831         struct shared_msr_entry *msr;
1832         u32 index;
1833
1834         switch (msr_info->index) {
1835 #ifdef CONFIG_X86_64
1836         case MSR_FS_BASE:
1837                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1838                 break;
1839         case MSR_GS_BASE:
1840                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1841                 break;
1842         case MSR_KERNEL_GS_BASE:
1843                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1844                 break;
1845 #endif
1846         case MSR_EFER:
1847                 return kvm_get_msr_common(vcpu, msr_info);
1848         case MSR_IA32_TSX_CTRL:
1849                 if (!msr_info->host_initiated &&
1850                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1851                         return 1;
1852                 goto find_shared_msr;
1853         case MSR_IA32_UMWAIT_CONTROL:
1854                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1855                         return 1;
1856
1857                 msr_info->data = vmx->msr_ia32_umwait_control;
1858                 break;
1859         case MSR_IA32_SPEC_CTRL:
1860                 if (!msr_info->host_initiated &&
1861                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1862                         return 1;
1863
1864                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1865                 break;
1866         case MSR_IA32_SYSENTER_CS:
1867                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1868                 break;
1869         case MSR_IA32_SYSENTER_EIP:
1870                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1871                 break;
1872         case MSR_IA32_SYSENTER_ESP:
1873                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1874                 break;
1875         case MSR_IA32_BNDCFGS:
1876                 if (!kvm_mpx_supported() ||
1877                     (!msr_info->host_initiated &&
1878                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1879                         return 1;
1880                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1881                 break;
1882         case MSR_IA32_MCG_EXT_CTL:
1883                 if (!msr_info->host_initiated &&
1884                     !(vmx->msr_ia32_feature_control &
1885                       FEAT_CTL_LMCE_ENABLED))
1886                         return 1;
1887                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1888                 break;
1889         case MSR_IA32_FEAT_CTL:
1890                 msr_info->data = vmx->msr_ia32_feature_control;
1891                 break;
1892         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1893                 if (!nested_vmx_allowed(vcpu))
1894                         return 1;
1895                 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1896                                     &msr_info->data))
1897                         return 1;
1898                 /*
1899                  * Enlightened VMCS v1 doesn't have certain fields, but buggy
1900                  * Hyper-V versions are still trying to use corresponding
1901                  * features when they are exposed. Filter out the essential
1902                  * minimum.
1903                  */
1904                 if (!msr_info->host_initiated &&
1905                     vmx->nested.enlightened_vmcs_enabled)
1906                         nested_evmcs_filter_control_msr(msr_info->index,
1907                                                         &msr_info->data);
1908                 break;
1909         case MSR_IA32_RTIT_CTL:
1910                 if (!vmx_pt_mode_is_host_guest())
1911                         return 1;
1912                 msr_info->data = vmx->pt_desc.guest.ctl;
1913                 break;
1914         case MSR_IA32_RTIT_STATUS:
1915                 if (!vmx_pt_mode_is_host_guest())
1916                         return 1;
1917                 msr_info->data = vmx->pt_desc.guest.status;
1918                 break;
1919         case MSR_IA32_RTIT_CR3_MATCH:
1920                 if (!vmx_pt_mode_is_host_guest() ||
1921                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1922                                                 PT_CAP_cr3_filtering))
1923                         return 1;
1924                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1925                 break;
1926         case MSR_IA32_RTIT_OUTPUT_BASE:
1927                 if (!vmx_pt_mode_is_host_guest() ||
1928                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1929                                         PT_CAP_topa_output) &&
1930                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1931                                         PT_CAP_single_range_output)))
1932                         return 1;
1933                 msr_info->data = vmx->pt_desc.guest.output_base;
1934                 break;
1935         case MSR_IA32_RTIT_OUTPUT_MASK:
1936                 if (!vmx_pt_mode_is_host_guest() ||
1937                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1938                                         PT_CAP_topa_output) &&
1939                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1940                                         PT_CAP_single_range_output)))
1941                         return 1;
1942                 msr_info->data = vmx->pt_desc.guest.output_mask;
1943                 break;
1944         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1945                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1946                 if (!vmx_pt_mode_is_host_guest() ||
1947                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1948                                         PT_CAP_num_address_ranges)))
1949                         return 1;
1950                 if (index % 2)
1951                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1952                 else
1953                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1954                 break;
1955         case MSR_TSC_AUX:
1956                 if (!msr_info->host_initiated &&
1957                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1958                         return 1;
1959                 goto find_shared_msr;
1960         default:
1961         find_shared_msr:
1962                 msr = find_msr_entry(vmx, msr_info->index);
1963                 if (msr) {
1964                         msr_info->data = msr->data;
1965                         break;
1966                 }
1967                 return kvm_get_msr_common(vcpu, msr_info);
1968         }
1969
1970         return 0;
1971 }
1972
1973 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1974                                                     u64 data)
1975 {
1976 #ifdef CONFIG_X86_64
1977         if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1978                 return (u32)data;
1979 #endif
1980         return (unsigned long)data;
1981 }
1982
1983 /*
1984  * Writes msr value into the appropriate "register".
1985  * Returns 0 on success, non-0 otherwise.
1986  * Assumes vcpu_load() was already called.
1987  */
1988 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1989 {
1990         struct vcpu_vmx *vmx = to_vmx(vcpu);
1991         struct shared_msr_entry *msr;
1992         int ret = 0;
1993         u32 msr_index = msr_info->index;
1994         u64 data = msr_info->data;
1995         u32 index;
1996
1997         switch (msr_index) {
1998         case MSR_EFER:
1999                 ret = kvm_set_msr_common(vcpu, msr_info);
2000                 break;
2001 #ifdef CONFIG_X86_64
2002         case MSR_FS_BASE:
2003                 vmx_segment_cache_clear(vmx);
2004                 vmcs_writel(GUEST_FS_BASE, data);
2005                 break;
2006         case MSR_GS_BASE:
2007                 vmx_segment_cache_clear(vmx);
2008                 vmcs_writel(GUEST_GS_BASE, data);
2009                 break;
2010         case MSR_KERNEL_GS_BASE:
2011                 vmx_write_guest_kernel_gs_base(vmx, data);
2012                 break;
2013 #endif
2014         case MSR_IA32_SYSENTER_CS:
2015                 if (is_guest_mode(vcpu))
2016                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
2017                 vmcs_write32(GUEST_SYSENTER_CS, data);
2018                 break;
2019         case MSR_IA32_SYSENTER_EIP:
2020                 if (is_guest_mode(vcpu)) {
2021                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
2022                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
2023                 }
2024                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2025                 break;
2026         case MSR_IA32_SYSENTER_ESP:
2027                 if (is_guest_mode(vcpu)) {
2028                         data = nested_vmx_truncate_sysenter_addr(vcpu, data);
2029                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
2030                 }
2031                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2032                 break;
2033         case MSR_IA32_DEBUGCTLMSR:
2034                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
2035                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
2036                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2037
2038                 ret = kvm_set_msr_common(vcpu, msr_info);
2039                 break;
2040
2041         case MSR_IA32_BNDCFGS:
2042                 if (!kvm_mpx_supported() ||
2043                     (!msr_info->host_initiated &&
2044                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2045                         return 1;
2046                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2047                     (data & MSR_IA32_BNDCFGS_RSVD))
2048                         return 1;
2049                 vmcs_write64(GUEST_BNDCFGS, data);
2050                 break;
2051         case MSR_IA32_UMWAIT_CONTROL:
2052                 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2053                         return 1;
2054
2055                 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2056                 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2057                         return 1;
2058
2059                 vmx->msr_ia32_umwait_control = data;
2060                 break;
2061         case MSR_IA32_SPEC_CTRL:
2062                 if (!msr_info->host_initiated &&
2063                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2064                         return 1;
2065
2066                 if (kvm_spec_ctrl_test_value(data))
2067                         return 1;
2068
2069                 vmx->spec_ctrl = data;
2070                 if (!data)
2071                         break;
2072
2073                 /*
2074                  * For non-nested:
2075                  * When it's written (to non-zero) for the first time, pass
2076                  * it through.
2077                  *
2078                  * For nested:
2079                  * The handling of the MSR bitmap for L2 guests is done in
2080                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2081                  * vmcs02.msr_bitmap here since it gets completely overwritten
2082                  * in the merging. We update the vmcs01 here for L1 as well
2083                  * since it will end up touching the MSR anyway now.
2084                  */
2085                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
2086                                               MSR_IA32_SPEC_CTRL,
2087                                               MSR_TYPE_RW);
2088                 break;
2089         case MSR_IA32_TSX_CTRL:
2090                 if (!msr_info->host_initiated &&
2091                     !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2092                         return 1;
2093                 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2094                         return 1;
2095                 goto find_shared_msr;
2096         case MSR_IA32_PRED_CMD:
2097                 if (!msr_info->host_initiated &&
2098                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
2099                         return 1;
2100
2101                 if (data & ~PRED_CMD_IBPB)
2102                         return 1;
2103                 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL))
2104                         return 1;
2105                 if (!data)
2106                         break;
2107
2108                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2109
2110                 /*
2111                  * For non-nested:
2112                  * When it's written (to non-zero) for the first time, pass
2113                  * it through.
2114                  *
2115                  * For nested:
2116                  * The handling of the MSR bitmap for L2 guests is done in
2117                  * nested_vmx_prepare_msr_bitmap. We should not touch the
2118                  * vmcs02.msr_bitmap here since it gets completely overwritten
2119                  * in the merging.
2120                  */
2121                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
2122                                               MSR_TYPE_W);
2123                 break;
2124         case MSR_IA32_CR_PAT:
2125                 if (!kvm_pat_valid(data))
2126                         return 1;
2127
2128                 if (is_guest_mode(vcpu) &&
2129                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2130                         get_vmcs12(vcpu)->guest_ia32_pat = data;
2131
2132                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2133                         vmcs_write64(GUEST_IA32_PAT, data);
2134                         vcpu->arch.pat = data;
2135                         break;
2136                 }
2137                 ret = kvm_set_msr_common(vcpu, msr_info);
2138                 break;
2139         case MSR_IA32_TSC_ADJUST:
2140                 ret = kvm_set_msr_common(vcpu, msr_info);
2141                 break;
2142         case MSR_IA32_MCG_EXT_CTL:
2143                 if ((!msr_info->host_initiated &&
2144                      !(to_vmx(vcpu)->msr_ia32_feature_control &
2145                        FEAT_CTL_LMCE_ENABLED)) ||
2146                     (data & ~MCG_EXT_CTL_LMCE_EN))
2147                         return 1;
2148                 vcpu->arch.mcg_ext_ctl = data;
2149                 break;
2150         case MSR_IA32_FEAT_CTL:
2151                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2152                     (to_vmx(vcpu)->msr_ia32_feature_control &
2153                      FEAT_CTL_LOCKED && !msr_info->host_initiated))
2154                         return 1;
2155                 vmx->msr_ia32_feature_control = data;
2156                 if (msr_info->host_initiated && data == 0)
2157                         vmx_leave_nested(vcpu);
2158                 break;
2159         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2160                 if (!msr_info->host_initiated)
2161                         return 1; /* they are read-only */
2162                 if (!nested_vmx_allowed(vcpu))
2163                         return 1;
2164                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2165         case MSR_IA32_RTIT_CTL:
2166                 if (!vmx_pt_mode_is_host_guest() ||
2167                         vmx_rtit_ctl_check(vcpu, data) ||
2168                         vmx->nested.vmxon)
2169                         return 1;
2170                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2171                 vmx->pt_desc.guest.ctl = data;
2172                 pt_update_intercept_for_msr(vmx);
2173                 break;
2174         case MSR_IA32_RTIT_STATUS:
2175                 if (!pt_can_write_msr(vmx))
2176                         return 1;
2177                 if (data & MSR_IA32_RTIT_STATUS_MASK)
2178                         return 1;
2179                 vmx->pt_desc.guest.status = data;
2180                 break;
2181         case MSR_IA32_RTIT_CR3_MATCH:
2182                 if (!pt_can_write_msr(vmx))
2183                         return 1;
2184                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2185                                            PT_CAP_cr3_filtering))
2186                         return 1;
2187                 vmx->pt_desc.guest.cr3_match = data;
2188                 break;
2189         case MSR_IA32_RTIT_OUTPUT_BASE:
2190                 if (!pt_can_write_msr(vmx))
2191                         return 1;
2192                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2193                                            PT_CAP_topa_output) &&
2194                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2195                                            PT_CAP_single_range_output))
2196                         return 1;
2197                 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)
2198                         return 1;
2199                 vmx->pt_desc.guest.output_base = data;
2200                 break;
2201         case MSR_IA32_RTIT_OUTPUT_MASK:
2202                 if (!pt_can_write_msr(vmx))
2203                         return 1;
2204                 if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2205                                            PT_CAP_topa_output) &&
2206                     !intel_pt_validate_cap(vmx->pt_desc.caps,
2207                                            PT_CAP_single_range_output))
2208                         return 1;
2209                 vmx->pt_desc.guest.output_mask = data;
2210                 break;
2211         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2212                 if (!pt_can_write_msr(vmx))
2213                         return 1;
2214                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2215                 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2216                                                        PT_CAP_num_address_ranges))
2217                         return 1;
2218                 if (is_noncanonical_address(data, vcpu))
2219                         return 1;
2220                 if (index % 2)
2221                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2222                 else
2223                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2224                 break;
2225         case MSR_TSC_AUX:
2226                 if (!msr_info->host_initiated &&
2227                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2228                         return 1;
2229                 /* Check reserved bit, higher 32 bits should be zero */
2230                 if ((data >> 32) != 0)
2231                         return 1;
2232                 goto find_shared_msr;
2233
2234         default:
2235         find_shared_msr:
2236                 msr = find_msr_entry(vmx, msr_index);
2237                 if (msr)
2238                         ret = vmx_set_guest_msr(vmx, msr, data);
2239                 else
2240                         ret = kvm_set_msr_common(vcpu, msr_info);
2241         }
2242
2243         return ret;
2244 }
2245
2246 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2247 {
2248         unsigned long guest_owned_bits;
2249
2250         kvm_register_mark_available(vcpu, reg);
2251
2252         switch (reg) {
2253         case VCPU_REGS_RSP:
2254                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2255                 break;
2256         case VCPU_REGS_RIP:
2257                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2258                 break;
2259         case VCPU_EXREG_PDPTR:
2260                 if (enable_ept)
2261                         ept_save_pdptrs(vcpu);
2262                 break;
2263         case VCPU_EXREG_CR0:
2264                 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2265
2266                 vcpu->arch.cr0 &= ~guest_owned_bits;
2267                 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2268                 break;
2269         case VCPU_EXREG_CR3:
2270                 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2271                         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2272                 break;
2273         case VCPU_EXREG_CR4:
2274                 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2275
2276                 vcpu->arch.cr4 &= ~guest_owned_bits;
2277                 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2278                 break;
2279         default:
2280                 WARN_ON_ONCE(1);
2281                 break;
2282         }
2283 }
2284
2285 static __init int cpu_has_kvm_support(void)
2286 {
2287         return cpu_has_vmx();
2288 }
2289
2290 static __init int vmx_disabled_by_bios(void)
2291 {
2292         return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2293                !boot_cpu_has(X86_FEATURE_VMX);
2294 }
2295
2296 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2297 {
2298         u64 msr;
2299
2300         cr4_set_bits(X86_CR4_VMXE);
2301         intel_pt_handle_vmx(1);
2302
2303         asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2304                           _ASM_EXTABLE(1b, %l[fault])
2305                           : : [vmxon_pointer] "m"(vmxon_pointer)
2306                           : : fault);
2307         return 0;
2308
2309 fault:
2310         WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2311                   rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2312         intel_pt_handle_vmx(0);
2313         cr4_clear_bits(X86_CR4_VMXE);
2314
2315         return -EFAULT;
2316 }
2317
2318 static int hardware_enable(void)
2319 {
2320         int cpu = raw_smp_processor_id();
2321         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2322         int r;
2323
2324         if (cr4_read_shadow() & X86_CR4_VMXE)
2325                 return -EBUSY;
2326
2327         /*
2328          * This can happen if we hot-added a CPU but failed to allocate
2329          * VP assist page for it.
2330          */
2331         if (static_branch_unlikely(&enable_evmcs) &&
2332             !hv_get_vp_assist_page(cpu))
2333                 return -EFAULT;
2334
2335         r = kvm_cpu_vmxon(phys_addr);
2336         if (r)
2337                 return r;
2338
2339         if (enable_ept)
2340                 ept_sync_global();
2341
2342         return 0;
2343 }
2344
2345 static void vmclear_local_loaded_vmcss(void)
2346 {
2347         int cpu = raw_smp_processor_id();
2348         struct loaded_vmcs *v, *n;
2349
2350         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2351                                  loaded_vmcss_on_cpu_link)
2352                 __loaded_vmcs_clear(v);
2353 }
2354
2355
2356 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2357  * tricks.
2358  */
2359 static void kvm_cpu_vmxoff(void)
2360 {
2361         asm volatile (__ex("vmxoff"));
2362
2363         intel_pt_handle_vmx(0);
2364         cr4_clear_bits(X86_CR4_VMXE);
2365 }
2366
2367 static void hardware_disable(void)
2368 {
2369         vmclear_local_loaded_vmcss();
2370         kvm_cpu_vmxoff();
2371 }
2372
2373 /*
2374  * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2375  * directly instead of going through cpu_has(), to ensure KVM is trapping
2376  * ENCLS whenever it's supported in hardware.  It does not matter whether
2377  * the host OS supports or has enabled SGX.
2378  */
2379 static bool cpu_has_sgx(void)
2380 {
2381         return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2382 }
2383
2384 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2385                                       u32 msr, u32 *result)
2386 {
2387         u32 vmx_msr_low, vmx_msr_high;
2388         u32 ctl = ctl_min | ctl_opt;
2389
2390         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2391
2392         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2393         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2394
2395         /* Ensure minimum (required) set of control bits are supported. */
2396         if (ctl_min & ~ctl)
2397                 return -EIO;
2398
2399         *result = ctl;
2400         return 0;
2401 }
2402
2403 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2404                                     struct vmx_capability *vmx_cap)
2405 {
2406         u32 vmx_msr_low, vmx_msr_high;
2407         u32 min, opt, min2, opt2;
2408         u32 _pin_based_exec_control = 0;
2409         u32 _cpu_based_exec_control = 0;
2410         u32 _cpu_based_2nd_exec_control = 0;
2411         u32 _vmexit_control = 0;
2412         u32 _vmentry_control = 0;
2413
2414         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2415         min = CPU_BASED_HLT_EXITING |
2416 #ifdef CONFIG_X86_64
2417               CPU_BASED_CR8_LOAD_EXITING |
2418               CPU_BASED_CR8_STORE_EXITING |
2419 #endif
2420               CPU_BASED_CR3_LOAD_EXITING |
2421               CPU_BASED_CR3_STORE_EXITING |
2422               CPU_BASED_UNCOND_IO_EXITING |
2423               CPU_BASED_MOV_DR_EXITING |
2424               CPU_BASED_USE_TSC_OFFSETTING |
2425               CPU_BASED_MWAIT_EXITING |
2426               CPU_BASED_MONITOR_EXITING |
2427               CPU_BASED_INVLPG_EXITING |
2428               CPU_BASED_RDPMC_EXITING;
2429
2430         opt = CPU_BASED_TPR_SHADOW |
2431               CPU_BASED_USE_MSR_BITMAPS |
2432               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2433         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2434                                 &_cpu_based_exec_control) < 0)
2435                 return -EIO;
2436 #ifdef CONFIG_X86_64
2437         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2438                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2439                                            ~CPU_BASED_CR8_STORE_EXITING;
2440 #endif
2441         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2442                 min2 = 0;
2443                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2444                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2445                         SECONDARY_EXEC_WBINVD_EXITING |
2446                         SECONDARY_EXEC_ENABLE_VPID |
2447                         SECONDARY_EXEC_ENABLE_EPT |
2448                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2449                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2450                         SECONDARY_EXEC_DESC |
2451                         SECONDARY_EXEC_RDTSCP |
2452                         SECONDARY_EXEC_ENABLE_INVPCID |
2453                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2454                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2455                         SECONDARY_EXEC_SHADOW_VMCS |
2456                         SECONDARY_EXEC_XSAVES |
2457                         SECONDARY_EXEC_RDSEED_EXITING |
2458                         SECONDARY_EXEC_RDRAND_EXITING |
2459                         SECONDARY_EXEC_ENABLE_PML |
2460                         SECONDARY_EXEC_TSC_SCALING |
2461                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2462                         SECONDARY_EXEC_PT_USE_GPA |
2463                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2464                         SECONDARY_EXEC_ENABLE_VMFUNC;
2465                 if (cpu_has_sgx())
2466                         opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2467                 if (adjust_vmx_controls(min2, opt2,
2468                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2469                                         &_cpu_based_2nd_exec_control) < 0)
2470                         return -EIO;
2471         }
2472 #ifndef CONFIG_X86_64
2473         if (!(_cpu_based_2nd_exec_control &
2474                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2475                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2476 #endif
2477
2478         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2479                 _cpu_based_2nd_exec_control &= ~(
2480                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2481                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2482                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2483
2484         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2485                 &vmx_cap->ept, &vmx_cap->vpid);
2486
2487         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2488                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2489                    enabled */
2490                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2491                                              CPU_BASED_CR3_STORE_EXITING |
2492                                              CPU_BASED_INVLPG_EXITING);
2493         } else if (vmx_cap->ept) {
2494                 vmx_cap->ept = 0;
2495                 pr_warn_once("EPT CAP should not exist if not support "
2496                                 "1-setting enable EPT VM-execution control\n");
2497         }
2498         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2499                 vmx_cap->vpid) {
2500                 vmx_cap->vpid = 0;
2501                 pr_warn_once("VPID CAP should not exist if not support "
2502                                 "1-setting enable VPID VM-execution control\n");
2503         }
2504
2505         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2506 #ifdef CONFIG_X86_64
2507         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2508 #endif
2509         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2510               VM_EXIT_LOAD_IA32_PAT |
2511               VM_EXIT_LOAD_IA32_EFER |
2512               VM_EXIT_CLEAR_BNDCFGS |
2513               VM_EXIT_PT_CONCEAL_PIP |
2514               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2515         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2516                                 &_vmexit_control) < 0)
2517                 return -EIO;
2518
2519         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2520         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2521                  PIN_BASED_VMX_PREEMPTION_TIMER;
2522         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2523                                 &_pin_based_exec_control) < 0)
2524                 return -EIO;
2525
2526         if (cpu_has_broken_vmx_preemption_timer())
2527                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2528         if (!(_cpu_based_2nd_exec_control &
2529                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2530                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2531
2532         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2533         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2534               VM_ENTRY_LOAD_IA32_PAT |
2535               VM_ENTRY_LOAD_IA32_EFER |
2536               VM_ENTRY_LOAD_BNDCFGS |
2537               VM_ENTRY_PT_CONCEAL_PIP |
2538               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2539         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2540                                 &_vmentry_control) < 0)
2541                 return -EIO;
2542
2543         /*
2544          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2545          * can't be used due to an errata where VM Exit may incorrectly clear
2546          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2547          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2548          */
2549         if (boot_cpu_data.x86 == 0x6) {
2550                 switch (boot_cpu_data.x86_model) {
2551                 case 26: /* AAK155 */
2552                 case 30: /* AAP115 */
2553                 case 37: /* AAT100 */
2554                 case 44: /* BC86,AAY89,BD102 */
2555                 case 46: /* BA97 */
2556                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2557                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2558                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2559                                         "does not work properly. Using workaround\n");
2560                         break;
2561                 default:
2562                         break;
2563                 }
2564         }
2565
2566
2567         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2568
2569         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2570         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2571                 return -EIO;
2572
2573 #ifdef CONFIG_X86_64
2574         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2575         if (vmx_msr_high & (1u<<16))
2576                 return -EIO;
2577 #endif
2578
2579         /* Require Write-Back (WB) memory type for VMCS accesses. */
2580         if (((vmx_msr_high >> 18) & 15) != 6)
2581                 return -EIO;
2582
2583         vmcs_conf->size = vmx_msr_high & 0x1fff;
2584         vmcs_conf->order = get_order(vmcs_conf->size);
2585         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2586
2587         vmcs_conf->revision_id = vmx_msr_low;
2588
2589         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2590         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2591         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2592         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2593         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2594
2595         if (static_branch_unlikely(&enable_evmcs))
2596                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2597
2598         return 0;
2599 }
2600
2601 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2602 {
2603         int node = cpu_to_node(cpu);
2604         struct page *pages;
2605         struct vmcs *vmcs;
2606
2607         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2608         if (!pages)
2609                 return NULL;
2610         vmcs = page_address(pages);
2611         memset(vmcs, 0, vmcs_config.size);
2612
2613         /* KVM supports Enlightened VMCS v1 only */
2614         if (static_branch_unlikely(&enable_evmcs))
2615                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2616         else
2617                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2618
2619         if (shadow)
2620                 vmcs->hdr.shadow_vmcs = 1;
2621         return vmcs;
2622 }
2623
2624 void free_vmcs(struct vmcs *vmcs)
2625 {
2626         free_pages((unsigned long)vmcs, vmcs_config.order);
2627 }
2628
2629 /*
2630  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2631  */
2632 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2633 {
2634         if (!loaded_vmcs->vmcs)
2635                 return;
2636         loaded_vmcs_clear(loaded_vmcs);
2637         free_vmcs(loaded_vmcs->vmcs);
2638         loaded_vmcs->vmcs = NULL;
2639         if (loaded_vmcs->msr_bitmap)
2640                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2641         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2642 }
2643
2644 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2645 {
2646         loaded_vmcs->vmcs = alloc_vmcs(false);
2647         if (!loaded_vmcs->vmcs)
2648                 return -ENOMEM;
2649
2650         vmcs_clear(loaded_vmcs->vmcs);
2651
2652         loaded_vmcs->shadow_vmcs = NULL;
2653         loaded_vmcs->hv_timer_soft_disabled = false;
2654         loaded_vmcs->cpu = -1;
2655         loaded_vmcs->launched = 0;
2656
2657         if (cpu_has_vmx_msr_bitmap()) {
2658                 loaded_vmcs->msr_bitmap = (unsigned long *)
2659                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2660                 if (!loaded_vmcs->msr_bitmap)
2661                         goto out_vmcs;
2662                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2663
2664                 if (IS_ENABLED(CONFIG_HYPERV) &&
2665                     static_branch_unlikely(&enable_evmcs) &&
2666                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2667                         struct hv_enlightened_vmcs *evmcs =
2668                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2669
2670                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2671                 }
2672         }
2673
2674         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2675         memset(&loaded_vmcs->controls_shadow, 0,
2676                 sizeof(struct vmcs_controls_shadow));
2677
2678         return 0;
2679
2680 out_vmcs:
2681         free_loaded_vmcs(loaded_vmcs);
2682         return -ENOMEM;
2683 }
2684
2685 static void free_kvm_area(void)
2686 {
2687         int cpu;
2688
2689         for_each_possible_cpu(cpu) {
2690                 free_vmcs(per_cpu(vmxarea, cpu));
2691                 per_cpu(vmxarea, cpu) = NULL;
2692         }
2693 }
2694
2695 static __init int alloc_kvm_area(void)
2696 {
2697         int cpu;
2698
2699         for_each_possible_cpu(cpu) {
2700                 struct vmcs *vmcs;
2701
2702                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2703                 if (!vmcs) {
2704                         free_kvm_area();
2705                         return -ENOMEM;
2706                 }
2707
2708                 /*
2709                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2710                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2711                  * revision_id reported by MSR_IA32_VMX_BASIC.
2712                  *
2713                  * However, even though not explicitly documented by
2714                  * TLFS, VMXArea passed as VMXON argument should
2715                  * still be marked with revision_id reported by
2716                  * physical CPU.
2717                  */
2718                 if (static_branch_unlikely(&enable_evmcs))
2719                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2720
2721                 per_cpu(vmxarea, cpu) = vmcs;
2722         }
2723         return 0;
2724 }
2725
2726 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2727                 struct kvm_segment *save)
2728 {
2729         if (!emulate_invalid_guest_state) {
2730                 /*
2731                  * CS and SS RPL should be equal during guest entry according
2732                  * to VMX spec, but in reality it is not always so. Since vcpu
2733                  * is in the middle of the transition from real mode to
2734                  * protected mode it is safe to assume that RPL 0 is a good
2735                  * default value.
2736                  */
2737                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2738                         save->selector &= ~SEGMENT_RPL_MASK;
2739                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2740                 save->s = 1;
2741         }
2742         vmx_set_segment(vcpu, save, seg);
2743 }
2744
2745 static void enter_pmode(struct kvm_vcpu *vcpu)
2746 {
2747         unsigned long flags;
2748         struct vcpu_vmx *vmx = to_vmx(vcpu);
2749
2750         /*
2751          * Update real mode segment cache. It may be not up-to-date if sement
2752          * register was written while vcpu was in a guest mode.
2753          */
2754         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2755         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2756         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2757         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2758         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2759         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2760
2761         vmx->rmode.vm86_active = 0;
2762
2763         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2764
2765         flags = vmcs_readl(GUEST_RFLAGS);
2766         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2767         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2768         vmcs_writel(GUEST_RFLAGS, flags);
2769
2770         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2771                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2772
2773         update_exception_bitmap(vcpu);
2774
2775         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2776         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2777         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2778         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2779         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2780         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2781 }
2782
2783 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2784 {
2785         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2786         struct kvm_segment var = *save;
2787
2788         var.dpl = 0x3;
2789         if (seg == VCPU_SREG_CS)
2790                 var.type = 0x3;
2791
2792         if (!emulate_invalid_guest_state) {
2793                 var.selector = var.base >> 4;
2794                 var.base = var.base & 0xffff0;
2795                 var.limit = 0xffff;
2796                 var.g = 0;
2797                 var.db = 0;
2798                 var.present = 1;
2799                 var.s = 1;
2800                 var.l = 0;
2801                 var.unusable = 0;
2802                 var.type = 0x3;
2803                 var.avl = 0;
2804                 if (save->base & 0xf)
2805                         printk_once(KERN_WARNING "kvm: segment base is not "
2806                                         "paragraph aligned when entering "
2807                                         "protected mode (seg=%d)", seg);
2808         }
2809
2810         vmcs_write16(sf->selector, var.selector);
2811         vmcs_writel(sf->base, var.base);
2812         vmcs_write32(sf->limit, var.limit);
2813         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2814 }
2815
2816 static void enter_rmode(struct kvm_vcpu *vcpu)
2817 {
2818         unsigned long flags;
2819         struct vcpu_vmx *vmx = to_vmx(vcpu);
2820         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2821
2822         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2823         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2824         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2825         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2826         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2827         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2828         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2829
2830         vmx->rmode.vm86_active = 1;
2831
2832         /*
2833          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2834          * vcpu. Warn the user that an update is overdue.
2835          */
2836         if (!kvm_vmx->tss_addr)
2837                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2838                              "called before entering vcpu\n");
2839
2840         vmx_segment_cache_clear(vmx);
2841
2842         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2843         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2844         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2845
2846         flags = vmcs_readl(GUEST_RFLAGS);
2847         vmx->rmode.save_rflags = flags;
2848
2849         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2850
2851         vmcs_writel(GUEST_RFLAGS, flags);
2852         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2853         update_exception_bitmap(vcpu);
2854
2855         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2856         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2857         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2858         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2859         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2860         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2861
2862         kvm_mmu_reset_context(vcpu);
2863 }
2864
2865 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2866 {
2867         struct vcpu_vmx *vmx = to_vmx(vcpu);
2868         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2869
2870         if (!msr)
2871                 return;
2872
2873         vcpu->arch.efer = efer;
2874         if (efer & EFER_LMA) {
2875                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2876                 msr->data = efer;
2877         } else {
2878                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2879
2880                 msr->data = efer & ~EFER_LME;
2881         }
2882         setup_msrs(vmx);
2883 }
2884
2885 #ifdef CONFIG_X86_64
2886
2887 static void enter_lmode(struct kvm_vcpu *vcpu)
2888 {
2889         u32 guest_tr_ar;
2890
2891         vmx_segment_cache_clear(to_vmx(vcpu));
2892
2893         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2894         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2895                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2896                                      __func__);
2897                 vmcs_write32(GUEST_TR_AR_BYTES,
2898                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2899                              | VMX_AR_TYPE_BUSY_64_TSS);
2900         }
2901         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2902 }
2903
2904 static void exit_lmode(struct kvm_vcpu *vcpu)
2905 {
2906         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2907         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2908 }
2909
2910 #endif
2911
2912 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2913 {
2914         struct vcpu_vmx *vmx = to_vmx(vcpu);
2915
2916         /*
2917          * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2918          * the CPU is not required to invalidate guest-physical mappings on
2919          * VM-Entry, even if VPID is disabled.  Guest-physical mappings are
2920          * associated with the root EPT structure and not any particular VPID
2921          * (INVVPID also isn't required to invalidate guest-physical mappings).
2922          */
2923         if (enable_ept) {
2924                 ept_sync_global();
2925         } else if (enable_vpid) {
2926                 if (cpu_has_vmx_invvpid_global()) {
2927                         vpid_sync_vcpu_global();
2928                 } else {
2929                         vpid_sync_vcpu_single(vmx->vpid);
2930                         vpid_sync_vcpu_single(vmx->nested.vpid02);
2931                 }
2932         }
2933 }
2934
2935 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2936 {
2937         struct kvm_mmu *mmu = vcpu->arch.mmu;
2938         u64 root_hpa = mmu->root_hpa;
2939
2940         /* No flush required if the current context is invalid. */
2941         if (!VALID_PAGE(root_hpa))
2942                 return;
2943
2944         if (enable_ept)
2945                 ept_sync_context(construct_eptp(vcpu, root_hpa,
2946                                                 mmu->shadow_root_level));
2947         else if (!is_guest_mode(vcpu))
2948                 vpid_sync_context(to_vmx(vcpu)->vpid);
2949         else
2950                 vpid_sync_context(nested_get_vpid02(vcpu));
2951 }
2952
2953 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2954 {
2955         /*
2956          * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2957          * vmx_flush_tlb_guest() for an explanation of why this is ok.
2958          */
2959         vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2960 }
2961
2962 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2963 {
2964         /*
2965          * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2966          * or a vpid couldn't be allocated for this vCPU.  VM-Enter and VM-Exit
2967          * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2968          * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2969          * i.e. no explicit INVVPID is necessary.
2970          */
2971         vpid_sync_context(to_vmx(vcpu)->vpid);
2972 }
2973
2974 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2975 {
2976         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2977
2978         if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2979                 return;
2980
2981         if (is_pae_paging(vcpu)) {
2982                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2983                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2984                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2985                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2986         }
2987 }
2988
2989 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2990 {
2991         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2992
2993         if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2994                 return;
2995
2996         mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2997         mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2998         mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2999         mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3000
3001         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
3002 }
3003
3004 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3005                                         unsigned long cr0,
3006                                         struct kvm_vcpu *vcpu)
3007 {
3008         struct vcpu_vmx *vmx = to_vmx(vcpu);
3009
3010         if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
3011                 vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
3012         if (!(cr0 & X86_CR0_PG)) {
3013                 /* From paging/starting to nonpaging */
3014                 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
3015                                           CPU_BASED_CR3_STORE_EXITING);
3016                 vcpu->arch.cr0 = cr0;
3017                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3018         } else if (!is_paging(vcpu)) {
3019                 /* From nonpaging to paging */
3020                 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
3021                                             CPU_BASED_CR3_STORE_EXITING);
3022                 vcpu->arch.cr0 = cr0;
3023                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3024         }
3025
3026         if (!(cr0 & X86_CR0_WP))
3027                 *hw_cr0 &= ~X86_CR0_WP;
3028 }
3029
3030 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3031 {
3032         struct vcpu_vmx *vmx = to_vmx(vcpu);
3033         unsigned long hw_cr0;
3034
3035         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3036         if (enable_unrestricted_guest)
3037                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3038         else {
3039                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3040
3041                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3042                         enter_pmode(vcpu);
3043
3044                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3045                         enter_rmode(vcpu);
3046         }
3047
3048 #ifdef CONFIG_X86_64
3049         if (vcpu->arch.efer & EFER_LME) {
3050                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3051                         enter_lmode(vcpu);
3052                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3053                         exit_lmode(vcpu);
3054         }
3055 #endif
3056
3057         if (enable_ept && !enable_unrestricted_guest)
3058                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3059
3060         vmcs_writel(CR0_READ_SHADOW, cr0);
3061         vmcs_writel(GUEST_CR0, hw_cr0);
3062         vcpu->arch.cr0 = cr0;
3063         kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3064
3065         /* depends on vcpu->arch.cr0 to be set to a new value */
3066         vmx->emulation_required = emulation_required(vcpu);
3067 }
3068
3069 static int vmx_get_max_tdp_level(void)
3070 {
3071         if (cpu_has_vmx_ept_5levels())
3072                 return 5;
3073         return 4;
3074 }
3075
3076 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa,
3077                    int root_level)
3078 {
3079         u64 eptp = VMX_EPTP_MT_WB;
3080
3081         eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3082
3083         if (enable_ept_ad_bits &&
3084             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3085                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
3086         eptp |= (root_hpa & PAGE_MASK);
3087
3088         return eptp;
3089 }
3090
3091 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long pgd,
3092                              int pgd_level)
3093 {
3094         struct kvm *kvm = vcpu->kvm;
3095         bool update_guest_cr3 = true;
3096         unsigned long guest_cr3;
3097         u64 eptp;
3098
3099         if (enable_ept) {
3100                 eptp = construct_eptp(vcpu, pgd, pgd_level);
3101                 vmcs_write64(EPT_POINTER, eptp);
3102
3103                 if (kvm_x86_ops.tlb_remote_flush) {
3104                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3105                         to_vmx(vcpu)->ept_pointer = eptp;
3106                         to_kvm_vmx(kvm)->ept_pointers_match
3107                                 = EPT_POINTERS_CHECK;
3108                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3109                 }
3110
3111                 if (!enable_unrestricted_guest && !is_paging(vcpu))
3112                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3113                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3114                         guest_cr3 = vcpu->arch.cr3;
3115                 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3116                         update_guest_cr3 = false;
3117                 ept_load_pdptrs(vcpu);
3118         } else {
3119                 guest_cr3 = pgd;
3120         }
3121
3122         if (update_guest_cr3)
3123                 vmcs_writel(GUEST_CR3, guest_cr3);
3124 }
3125
3126 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3127 {
3128         struct vcpu_vmx *vmx = to_vmx(vcpu);
3129         /*
3130          * Pass through host's Machine Check Enable value to hw_cr4, which
3131          * is in force while we are in guest mode.  Do not let guests control
3132          * this bit, even if host CR4.MCE == 0.
3133          */
3134         unsigned long hw_cr4;
3135
3136         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3137         if (enable_unrestricted_guest)
3138                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3139         else if (vmx->rmode.vm86_active)
3140                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3141         else
3142                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3143
3144         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3145                 if (cr4 & X86_CR4_UMIP) {
3146                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3147                         hw_cr4 &= ~X86_CR4_UMIP;
3148                 } else if (!is_guest_mode(vcpu) ||
3149                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3150                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3151                 }
3152         }
3153
3154         if (cr4 & X86_CR4_VMXE) {
3155                 /*
3156                  * To use VMXON (and later other VMX instructions), a guest
3157                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3158                  * So basically the check on whether to allow nested VMX
3159                  * is here.  We operate under the default treatment of SMM,
3160                  * so VMX cannot be enabled under SMM.
3161                  */
3162                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3163                         return 1;
3164         }
3165
3166         if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3167                 return 1;
3168
3169         vcpu->arch.cr4 = cr4;
3170         kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3171
3172         if (!enable_unrestricted_guest) {
3173                 if (enable_ept) {
3174                         if (!is_paging(vcpu)) {
3175                                 hw_cr4 &= ~X86_CR4_PAE;
3176                                 hw_cr4 |= X86_CR4_PSE;
3177                         } else if (!(cr4 & X86_CR4_PAE)) {
3178                                 hw_cr4 &= ~X86_CR4_PAE;
3179                         }
3180                 }
3181
3182                 /*
3183                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3184                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3185                  * to be manually disabled when guest switches to non-paging
3186                  * mode.
3187                  *
3188                  * If !enable_unrestricted_guest, the CPU is always running
3189                  * with CR0.PG=1 and CR4 needs to be modified.
3190                  * If enable_unrestricted_guest, the CPU automatically
3191                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3192                  */
3193                 if (!is_paging(vcpu))
3194                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3195         }
3196
3197         vmcs_writel(CR4_READ_SHADOW, cr4);
3198         vmcs_writel(GUEST_CR4, hw_cr4);
3199         return 0;
3200 }
3201
3202 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3203 {
3204         struct vcpu_vmx *vmx = to_vmx(vcpu);
3205         u32 ar;
3206
3207         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3208                 *var = vmx->rmode.segs[seg];
3209                 if (seg == VCPU_SREG_TR
3210                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3211                         return;
3212                 var->base = vmx_read_guest_seg_base(vmx, seg);
3213                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3214                 return;
3215         }
3216         var->base = vmx_read_guest_seg_base(vmx, seg);
3217         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3218         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3219         ar = vmx_read_guest_seg_ar(vmx, seg);
3220         var->unusable = (ar >> 16) & 1;
3221         var->type = ar & 15;
3222         var->s = (ar >> 4) & 1;
3223         var->dpl = (ar >> 5) & 3;
3224         /*
3225          * Some userspaces do not preserve unusable property. Since usable
3226          * segment has to be present according to VMX spec we can use present
3227          * property to amend userspace bug by making unusable segment always
3228          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3229          * segment as unusable.
3230          */
3231         var->present = !var->unusable;
3232         var->avl = (ar >> 12) & 1;
3233         var->l = (ar >> 13) & 1;
3234         var->db = (ar >> 14) & 1;
3235         var->g = (ar >> 15) & 1;
3236 }
3237
3238 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3239 {
3240         struct kvm_segment s;
3241
3242         if (to_vmx(vcpu)->rmode.vm86_active) {
3243                 vmx_get_segment(vcpu, &s, seg);
3244                 return s.base;
3245         }
3246         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3247 }
3248
3249 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3250 {
3251         struct vcpu_vmx *vmx = to_vmx(vcpu);
3252
3253         if (unlikely(vmx->rmode.vm86_active))
3254                 return 0;
3255         else {
3256                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3257                 return VMX_AR_DPL(ar);
3258         }
3259 }
3260
3261 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3262 {
3263         u32 ar;
3264
3265         if (var->unusable || !var->present)
3266                 ar = 1 << 16;
3267         else {
3268                 ar = var->type & 15;
3269                 ar |= (var->s & 1) << 4;
3270                 ar |= (var->dpl & 3) << 5;
3271                 ar |= (var->present & 1) << 7;
3272                 ar |= (var->avl & 1) << 12;
3273                 ar |= (var->l & 1) << 13;
3274                 ar |= (var->db & 1) << 14;
3275                 ar |= (var->g & 1) << 15;
3276         }
3277
3278         return ar;
3279 }
3280
3281 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3282 {
3283         struct vcpu_vmx *vmx = to_vmx(vcpu);
3284         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3285
3286         vmx_segment_cache_clear(vmx);
3287
3288         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3289                 vmx->rmode.segs[seg] = *var;
3290                 if (seg == VCPU_SREG_TR)
3291                         vmcs_write16(sf->selector, var->selector);
3292                 else if (var->s)
3293                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3294                 goto out;
3295         }
3296
3297         vmcs_writel(sf->base, var->base);
3298         vmcs_write32(sf->limit, var->limit);
3299         vmcs_write16(sf->selector, var->selector);
3300
3301         /*
3302          *   Fix the "Accessed" bit in AR field of segment registers for older
3303          * qemu binaries.
3304          *   IA32 arch specifies that at the time of processor reset the
3305          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3306          * is setting it to 0 in the userland code. This causes invalid guest
3307          * state vmexit when "unrestricted guest" mode is turned on.
3308          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3309          * tree. Newer qemu binaries with that qemu fix would not need this
3310          * kvm hack.
3311          */
3312         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3313                 var->type |= 0x1; /* Accessed */
3314
3315         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3316
3317 out:
3318         vmx->emulation_required = emulation_required(vcpu);
3319 }
3320
3321 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3322 {
3323         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3324
3325         *db = (ar >> 14) & 1;
3326         *l = (ar >> 13) & 1;
3327 }
3328
3329 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3330 {
3331         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3332         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3333 }
3334
3335 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3336 {
3337         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3338         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3339 }
3340
3341 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3342 {
3343         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3344         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3345 }
3346
3347 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3348 {
3349         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3350         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3351 }
3352
3353 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3354 {
3355         struct kvm_segment var;
3356         u32 ar;
3357
3358         vmx_get_segment(vcpu, &var, seg);
3359         var.dpl = 0x3;
3360         if (seg == VCPU_SREG_CS)
3361                 var.type = 0x3;
3362         ar = vmx_segment_access_rights(&var);
3363
3364         if (var.base != (var.selector << 4))
3365                 return false;
3366         if (var.limit != 0xffff)
3367                 return false;
3368         if (ar != 0xf3)
3369                 return false;
3370
3371         return true;
3372 }
3373
3374 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3375 {
3376         struct kvm_segment cs;
3377         unsigned int cs_rpl;
3378
3379         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3380         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3381
3382         if (cs.unusable)
3383                 return false;
3384         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3385                 return false;
3386         if (!cs.s)
3387                 return false;
3388         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3389                 if (cs.dpl > cs_rpl)
3390                         return false;
3391         } else {
3392                 if (cs.dpl != cs_rpl)
3393                         return false;
3394         }
3395         if (!cs.present)
3396                 return false;
3397
3398         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3399         return true;
3400 }
3401
3402 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3403 {
3404         struct kvm_segment ss;
3405         unsigned int ss_rpl;
3406
3407         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3408         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3409
3410         if (ss.unusable)
3411                 return true;
3412         if (ss.type != 3 && ss.type != 7)
3413                 return false;
3414         if (!ss.s)
3415                 return false;
3416         if (ss.dpl != ss_rpl) /* DPL != RPL */
3417                 return false;
3418         if (!ss.present)
3419                 return false;
3420
3421         return true;
3422 }
3423
3424 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3425 {
3426         struct kvm_segment var;
3427         unsigned int rpl;
3428
3429         vmx_get_segment(vcpu, &var, seg);
3430         rpl = var.selector & SEGMENT_RPL_MASK;
3431
3432         if (var.unusable)
3433                 return true;
3434         if (!var.s)
3435                 return false;
3436         if (!var.present)
3437                 return false;
3438         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3439                 if (var.dpl < rpl) /* DPL < RPL */
3440                         return false;
3441         }
3442
3443         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3444          * rights flags
3445          */
3446         return true;
3447 }
3448
3449 static bool tr_valid(struct kvm_vcpu *vcpu)
3450 {
3451         struct kvm_segment tr;
3452
3453         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3454
3455         if (tr.unusable)
3456                 return false;
3457         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3458                 return false;
3459         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3460                 return false;
3461         if (!tr.present)
3462                 return false;
3463
3464         return true;
3465 }
3466
3467 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3468 {
3469         struct kvm_segment ldtr;
3470
3471         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3472
3473         if (ldtr.unusable)
3474                 return true;
3475         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3476                 return false;
3477         if (ldtr.type != 2)
3478                 return false;
3479         if (!ldtr.present)
3480                 return false;
3481
3482         return true;
3483 }
3484
3485 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3486 {
3487         struct kvm_segment cs, ss;
3488
3489         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3490         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3491
3492         return ((cs.selector & SEGMENT_RPL_MASK) ==
3493                  (ss.selector & SEGMENT_RPL_MASK));
3494 }
3495
3496 /*
3497  * Check if guest state is valid. Returns true if valid, false if
3498  * not.
3499  * We assume that registers are always usable
3500  */
3501 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3502 {
3503         if (enable_unrestricted_guest)
3504                 return true;
3505
3506         /* real mode guest state checks */
3507         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3508                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3509                         return false;
3510                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3511                         return false;
3512                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3513                         return false;
3514                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3515                         return false;
3516                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3517                         return false;
3518                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3519                         return false;
3520         } else {
3521         /* protected mode guest state checks */
3522                 if (!cs_ss_rpl_check(vcpu))
3523                         return false;
3524                 if (!code_segment_valid(vcpu))
3525                         return false;
3526                 if (!stack_segment_valid(vcpu))
3527                         return false;
3528                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3529                         return false;
3530                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3531                         return false;
3532                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3533                         return false;
3534                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3535                         return false;
3536                 if (!tr_valid(vcpu))
3537                         return false;
3538                 if (!ldtr_valid(vcpu))
3539                         return false;
3540         }
3541         /* TODO:
3542          * - Add checks on RIP
3543          * - Add checks on RFLAGS
3544          */
3545
3546         return true;
3547 }
3548
3549 static int init_rmode_tss(struct kvm *kvm)
3550 {
3551         gfn_t fn;
3552         u16 data = 0;
3553         int idx, r;
3554
3555         idx = srcu_read_lock(&kvm->srcu);
3556         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3557         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3558         if (r < 0)
3559                 goto out;
3560         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3561         r = kvm_write_guest_page(kvm, fn++, &data,
3562                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3563         if (r < 0)
3564                 goto out;
3565         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3566         if (r < 0)
3567                 goto out;
3568         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3569         if (r < 0)
3570                 goto out;
3571         data = ~0;
3572         r = kvm_write_guest_page(kvm, fn, &data,
3573                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3574                                  sizeof(u8));
3575 out:
3576         srcu_read_unlock(&kvm->srcu, idx);
3577         return r;
3578 }
3579
3580 static int init_rmode_identity_map(struct kvm *kvm)
3581 {
3582         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3583         int i, r = 0;
3584         kvm_pfn_t identity_map_pfn;
3585         u32 tmp;
3586
3587         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3588         mutex_lock(&kvm->slots_lock);
3589
3590         if (likely(kvm_vmx->ept_identity_pagetable_done))
3591                 goto out;
3592
3593         if (!kvm_vmx->ept_identity_map_addr)
3594                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3595         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3596
3597         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3598                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3599         if (r < 0)
3600                 goto out;
3601
3602         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3603         if (r < 0)
3604                 goto out;
3605         /* Set up identity-mapping pagetable for EPT in real mode */
3606         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3607                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3608                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3609                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3610                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3611                 if (r < 0)
3612                         goto out;
3613         }
3614         kvm_vmx->ept_identity_pagetable_done = true;
3615
3616 out:
3617         mutex_unlock(&kvm->slots_lock);
3618         return r;
3619 }
3620
3621 static void seg_setup(int seg)
3622 {
3623         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3624         unsigned int ar;
3625
3626         vmcs_write16(sf->selector, 0);
3627         vmcs_writel(sf->base, 0);
3628         vmcs_write32(sf->limit, 0xffff);
3629         ar = 0x93;
3630         if (seg == VCPU_SREG_CS)
3631                 ar |= 0x08; /* code segment */
3632
3633         vmcs_write32(sf->ar_bytes, ar);
3634 }
3635
3636 static int alloc_apic_access_page(struct kvm *kvm)
3637 {
3638         struct page *page;
3639         int r = 0;
3640
3641         mutex_lock(&kvm->slots_lock);
3642         if (kvm->arch.apic_access_page_done)
3643                 goto out;
3644         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3645                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3646         if (r)
3647                 goto out;
3648
3649         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3650         if (is_error_page(page)) {
3651                 r = -EFAULT;
3652                 goto out;
3653         }
3654
3655         /*
3656          * Do not pin the page in memory, so that memory hot-unplug
3657          * is able to migrate it.
3658          */
3659         put_page(page);
3660         kvm->arch.apic_access_page_done = true;
3661 out:
3662         mutex_unlock(&kvm->slots_lock);
3663         return r;
3664 }
3665
3666 int allocate_vpid(void)
3667 {
3668         int vpid;
3669
3670         if (!enable_vpid)
3671                 return 0;
3672         spin_lock(&vmx_vpid_lock);
3673         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3674         if (vpid < VMX_NR_VPIDS)
3675                 __set_bit(vpid, vmx_vpid_bitmap);
3676         else
3677                 vpid = 0;
3678         spin_unlock(&vmx_vpid_lock);
3679         return vpid;
3680 }
3681
3682 void free_vpid(int vpid)
3683 {
3684         if (!enable_vpid || vpid == 0)
3685                 return;
3686         spin_lock(&vmx_vpid_lock);
3687         __clear_bit(vpid, vmx_vpid_bitmap);
3688         spin_unlock(&vmx_vpid_lock);
3689 }
3690
3691 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3692                                                           u32 msr, int type)
3693 {
3694         int f = sizeof(unsigned long);
3695
3696         if (!cpu_has_vmx_msr_bitmap())
3697                 return;
3698
3699         if (static_branch_unlikely(&enable_evmcs))
3700                 evmcs_touch_msr_bitmap();
3701
3702         /*
3703          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3704          * have the write-low and read-high bitmap offsets the wrong way round.
3705          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3706          */
3707         if (msr <= 0x1fff) {
3708                 if (type & MSR_TYPE_R)
3709                         /* read-low */
3710                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3711
3712                 if (type & MSR_TYPE_W)
3713                         /* write-low */
3714                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3715
3716         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3717                 msr &= 0x1fff;
3718                 if (type & MSR_TYPE_R)
3719                         /* read-high */
3720                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3721
3722                 if (type & MSR_TYPE_W)
3723                         /* write-high */
3724                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3725
3726         }
3727 }
3728
3729 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3730                                                          u32 msr, int type)
3731 {
3732         int f = sizeof(unsigned long);
3733
3734         if (!cpu_has_vmx_msr_bitmap())
3735                 return;
3736
3737         if (static_branch_unlikely(&enable_evmcs))
3738                 evmcs_touch_msr_bitmap();
3739
3740         /*
3741          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3742          * have the write-low and read-high bitmap offsets the wrong way round.
3743          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3744          */
3745         if (msr <= 0x1fff) {
3746                 if (type & MSR_TYPE_R)
3747                         /* read-low */
3748                         __set_bit(msr, msr_bitmap + 0x000 / f);
3749
3750                 if (type & MSR_TYPE_W)
3751                         /* write-low */
3752                         __set_bit(msr, msr_bitmap + 0x800 / f);
3753
3754         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3755                 msr &= 0x1fff;
3756                 if (type & MSR_TYPE_R)
3757                         /* read-high */
3758                         __set_bit(msr, msr_bitmap + 0x400 / f);
3759
3760                 if (type & MSR_TYPE_W)
3761                         /* write-high */
3762                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3763
3764         }
3765 }
3766
3767 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3768                                                       u32 msr, int type, bool value)
3769 {
3770         if (value)
3771                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3772         else
3773                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3774 }
3775
3776 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3777 {
3778         u8 mode = 0;
3779
3780         if (cpu_has_secondary_exec_ctrls() &&
3781             (secondary_exec_controls_get(to_vmx(vcpu)) &
3782              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3783                 mode |= MSR_BITMAP_MODE_X2APIC;
3784                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3785                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3786         }
3787
3788         return mode;
3789 }
3790
3791 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3792                                          u8 mode)
3793 {
3794         int msr;
3795
3796         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3797                 unsigned word = msr / BITS_PER_LONG;
3798                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3799                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3800         }
3801
3802         if (mode & MSR_BITMAP_MODE_X2APIC) {
3803                 /*
3804                  * TPR reads and writes can be virtualized even if virtual interrupt
3805                  * delivery is not in use.
3806                  */
3807                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3808                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3809                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3810                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3811                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3812                 }
3813         }
3814 }
3815
3816 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3817 {
3818         struct vcpu_vmx *vmx = to_vmx(vcpu);
3819         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3820         u8 mode = vmx_msr_bitmap_mode(vcpu);
3821         u8 changed = mode ^ vmx->msr_bitmap_mode;
3822
3823         if (!changed)
3824                 return;
3825
3826         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3827                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3828
3829         vmx->msr_bitmap_mode = mode;
3830 }
3831
3832 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3833 {
3834         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3835         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3836         u32 i;
3837
3838         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3839                                                         MSR_TYPE_RW, flag);
3840         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3841                                                         MSR_TYPE_RW, flag);
3842         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3843                                                         MSR_TYPE_RW, flag);
3844         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3845                                                         MSR_TYPE_RW, flag);
3846         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3847                 vmx_set_intercept_for_msr(msr_bitmap,
3848                         MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3849                 vmx_set_intercept_for_msr(msr_bitmap,
3850                         MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3851         }
3852 }
3853
3854 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3855 {
3856         struct vcpu_vmx *vmx = to_vmx(vcpu);
3857         void *vapic_page;
3858         u32 vppr;
3859         int rvi;
3860
3861         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3862                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3863                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3864                 return false;
3865
3866         rvi = vmx_get_rvi();
3867
3868         vapic_page = vmx->nested.virtual_apic_map.hva;
3869         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3870
3871         return ((rvi & 0xf0) > (vppr & 0xf0));
3872 }
3873
3874 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3875                                                      bool nested)
3876 {
3877 #ifdef CONFIG_SMP
3878         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3879
3880         if (vcpu->mode == IN_GUEST_MODE) {
3881                 /*
3882                  * The vector of interrupt to be delivered to vcpu had
3883                  * been set in PIR before this function.
3884                  *
3885                  * Following cases will be reached in this block, and
3886                  * we always send a notification event in all cases as
3887                  * explained below.
3888                  *
3889                  * Case 1: vcpu keeps in non-root mode. Sending a
3890                  * notification event posts the interrupt to vcpu.
3891                  *
3892                  * Case 2: vcpu exits to root mode and is still
3893                  * runnable. PIR will be synced to vIRR before the
3894                  * next vcpu entry. Sending a notification event in
3895                  * this case has no effect, as vcpu is not in root
3896                  * mode.
3897                  *
3898                  * Case 3: vcpu exits to root mode and is blocked.
3899                  * vcpu_block() has already synced PIR to vIRR and
3900                  * never blocks vcpu if vIRR is not cleared. Therefore,
3901                  * a blocked vcpu here does not wait for any requested
3902                  * interrupts in PIR, and sending a notification event
3903                  * which has no effect is safe here.
3904                  */
3905
3906                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3907                 return true;
3908         }
3909 #endif
3910         return false;
3911 }
3912
3913 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3914                                                 int vector)
3915 {
3916         struct vcpu_vmx *vmx = to_vmx(vcpu);
3917
3918         if (is_guest_mode(vcpu) &&
3919             vector == vmx->nested.posted_intr_nv) {
3920                 /*
3921                  * If a posted intr is not recognized by hardware,
3922                  * we will accomplish it in the next vmentry.
3923                  */
3924                 vmx->nested.pi_pending = true;
3925                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3926                 /* the PIR and ON have been set by L1. */
3927                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3928                         kvm_vcpu_kick(vcpu);
3929                 return 0;
3930         }
3931         return -1;
3932 }
3933 /*
3934  * Send interrupt to vcpu via posted interrupt way.
3935  * 1. If target vcpu is running(non-root mode), send posted interrupt
3936  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3937  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3938  * interrupt from PIR in next vmentry.
3939  */
3940 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3941 {
3942         struct vcpu_vmx *vmx = to_vmx(vcpu);
3943         int r;
3944
3945         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3946         if (!r)
3947                 return 0;
3948
3949         if (!vcpu->arch.apicv_active)
3950                 return -1;
3951
3952         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3953                 return 0;
3954
3955         /* If a previous notification has sent the IPI, nothing to do.  */
3956         if (pi_test_and_set_on(&vmx->pi_desc))
3957                 return 0;
3958
3959         if (vcpu != kvm_get_running_vcpu() &&
3960             !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3961                 kvm_vcpu_kick(vcpu);
3962
3963         return 0;
3964 }
3965
3966 /*
3967  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3968  * will not change in the lifetime of the guest.
3969  * Note that host-state that does change is set elsewhere. E.g., host-state
3970  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3971  */
3972 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3973 {
3974         u32 low32, high32;
3975         unsigned long tmpl;
3976         unsigned long cr0, cr3, cr4;
3977
3978         cr0 = read_cr0();
3979         WARN_ON(cr0 & X86_CR0_TS);
3980         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3981
3982         /*
3983          * Save the most likely value for this task's CR3 in the VMCS.
3984          * We can't use __get_current_cr3_fast() because we're not atomic.
3985          */
3986         cr3 = __read_cr3();
3987         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
3988         vmx->loaded_vmcs->host_state.cr3 = cr3;
3989
3990         /* Save the most likely value for this task's CR4 in the VMCS. */
3991         cr4 = cr4_read_shadow();
3992         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
3993         vmx->loaded_vmcs->host_state.cr4 = cr4;
3994
3995         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3996 #ifdef CONFIG_X86_64
3997         /*
3998          * Load null selectors, so we can avoid reloading them in
3999          * vmx_prepare_switch_to_host(), in case userspace uses
4000          * the null selectors too (the expected case).
4001          */
4002         vmcs_write16(HOST_DS_SELECTOR, 0);
4003         vmcs_write16(HOST_ES_SELECTOR, 0);
4004 #else
4005         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4006         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4007 #endif
4008         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4009         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4010
4011         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
4012
4013         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4014
4015         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4016         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4017         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4018         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4019
4020         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4021                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4022                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4023         }
4024
4025         if (cpu_has_load_ia32_efer())
4026                 vmcs_write64(HOST_IA32_EFER, host_efer);
4027 }
4028
4029 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4030 {
4031         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS;
4032         if (!enable_ept)
4033                 vmx->vcpu.arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4034         if (is_guest_mode(&vmx->vcpu))
4035                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4036                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4037         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4038 }
4039
4040 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4041 {
4042         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4043
4044         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4045                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4046
4047         if (!enable_vnmi)
4048                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4049
4050         if (!enable_preemption_timer)
4051                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4052
4053         return pin_based_exec_ctrl;
4054 }
4055
4056 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4057 {
4058         struct vcpu_vmx *vmx = to_vmx(vcpu);
4059
4060         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4061         if (cpu_has_secondary_exec_ctrls()) {
4062                 if (kvm_vcpu_apicv_active(vcpu))
4063                         secondary_exec_controls_setbit(vmx,
4064                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4065                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4066                 else
4067                         secondary_exec_controls_clearbit(vmx,
4068                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4069                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4070         }
4071
4072         if (cpu_has_vmx_msr_bitmap())
4073                 vmx_update_msr_bitmap(vcpu);
4074 }
4075
4076 u32 vmx_exec_control(struct vcpu_vmx *vmx)
4077 {
4078         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4079
4080         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4081                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4082
4083         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4084                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4085 #ifdef CONFIG_X86_64
4086                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4087                                 CPU_BASED_CR8_LOAD_EXITING;
4088 #endif
4089         }
4090         if (!enable_ept)
4091                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4092                                 CPU_BASED_CR3_LOAD_EXITING  |
4093                                 CPU_BASED_INVLPG_EXITING;
4094         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4095                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4096                                 CPU_BASED_MONITOR_EXITING);
4097         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4098                 exec_control &= ~CPU_BASED_HLT_EXITING;
4099         return exec_control;
4100 }
4101
4102
4103 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4104 {
4105         struct kvm_vcpu *vcpu = &vmx->vcpu;
4106
4107         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4108
4109         if (vmx_pt_mode_is_system())
4110                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4111         if (!cpu_need_virtualize_apic_accesses(vcpu))
4112                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4113         if (vmx->vpid == 0)
4114                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4115         if (!enable_ept) {
4116                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4117                 enable_unrestricted_guest = 0;
4118         }
4119         if (!enable_unrestricted_guest)
4120                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4121         if (kvm_pause_in_guest(vmx->vcpu.kvm))
4122                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4123         if (!kvm_vcpu_apicv_active(vcpu))
4124                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4125                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4126         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4127
4128         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4129          * in vmx_set_cr4.  */
4130         exec_control &= ~SECONDARY_EXEC_DESC;
4131
4132         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4133            (handle_vmptrld).
4134            We can NOT enable shadow_vmcs here because we don't have yet
4135            a current VMCS12
4136         */
4137         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4138
4139         if (!enable_pml)
4140                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4141
4142         if (vmx_xsaves_supported()) {
4143                 /* Exposing XSAVES only when XSAVE is exposed */
4144                 bool xsaves_enabled =
4145                         boot_cpu_has(X86_FEATURE_XSAVE) &&
4146                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4147                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4148
4149                 vcpu->arch.xsaves_enabled = xsaves_enabled;
4150
4151                 if (!xsaves_enabled)
4152                         exec_control &= ~SECONDARY_EXEC_XSAVES;
4153
4154                 if (nested) {
4155                         if (xsaves_enabled)
4156                                 vmx->nested.msrs.secondary_ctls_high |=
4157                                         SECONDARY_EXEC_XSAVES;
4158                         else
4159                                 vmx->nested.msrs.secondary_ctls_high &=
4160                                         ~SECONDARY_EXEC_XSAVES;
4161                 }
4162         }
4163
4164         if (cpu_has_vmx_rdtscp()) {
4165                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4166                 if (!rdtscp_enabled)
4167                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
4168
4169                 if (nested) {
4170                         if (rdtscp_enabled)
4171                                 vmx->nested.msrs.secondary_ctls_high |=
4172                                         SECONDARY_EXEC_RDTSCP;
4173                         else
4174                                 vmx->nested.msrs.secondary_ctls_high &=
4175                                         ~SECONDARY_EXEC_RDTSCP;
4176                 }
4177         }
4178
4179         if (cpu_has_vmx_invpcid()) {
4180                 /* Exposing INVPCID only when PCID is exposed */
4181                 bool invpcid_enabled =
4182                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4183                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4184
4185                 if (!invpcid_enabled) {
4186                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4187                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4188                 }
4189
4190                 if (nested) {
4191                         if (invpcid_enabled)
4192                                 vmx->nested.msrs.secondary_ctls_high |=
4193                                         SECONDARY_EXEC_ENABLE_INVPCID;
4194                         else
4195                                 vmx->nested.msrs.secondary_ctls_high &=
4196                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
4197                 }
4198         }
4199
4200         if (vmx_rdrand_supported()) {
4201                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4202                 if (rdrand_enabled)
4203                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4204
4205                 if (nested) {
4206                         if (rdrand_enabled)
4207                                 vmx->nested.msrs.secondary_ctls_high |=
4208                                         SECONDARY_EXEC_RDRAND_EXITING;
4209                         else
4210                                 vmx->nested.msrs.secondary_ctls_high &=
4211                                         ~SECONDARY_EXEC_RDRAND_EXITING;
4212                 }
4213         }
4214
4215         if (vmx_rdseed_supported()) {
4216                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4217                 if (rdseed_enabled)
4218                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4219
4220                 if (nested) {
4221                         if (rdseed_enabled)
4222                                 vmx->nested.msrs.secondary_ctls_high |=
4223                                         SECONDARY_EXEC_RDSEED_EXITING;
4224                         else
4225                                 vmx->nested.msrs.secondary_ctls_high &=
4226                                         ~SECONDARY_EXEC_RDSEED_EXITING;
4227                 }
4228         }
4229
4230         if (vmx_waitpkg_supported()) {
4231                 bool waitpkg_enabled =
4232                         guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4233
4234                 if (!waitpkg_enabled)
4235                         exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4236
4237                 if (nested) {
4238                         if (waitpkg_enabled)
4239                                 vmx->nested.msrs.secondary_ctls_high |=
4240                                         SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4241                         else
4242                                 vmx->nested.msrs.secondary_ctls_high &=
4243                                         ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4244                 }
4245         }
4246
4247         vmx->secondary_exec_control = exec_control;
4248 }
4249
4250 static void ept_set_mmio_spte_mask(void)
4251 {
4252         /*
4253          * EPT Misconfigurations can be generated if the value of bits 2:0
4254          * of an EPT paging-structure entry is 110b (write/execute).
4255          */
4256         kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE, 0);
4257 }
4258
4259 #define VMX_XSS_EXIT_BITMAP 0
4260
4261 /*
4262  * Noting that the initialization of Guest-state Area of VMCS is in
4263  * vmx_vcpu_reset().
4264  */
4265 static void init_vmcs(struct vcpu_vmx *vmx)
4266 {
4267         if (nested)
4268                 nested_vmx_set_vmcs_shadowing_bitmap();
4269
4270         if (cpu_has_vmx_msr_bitmap())
4271                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4272
4273         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4274
4275         /* Control */
4276         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4277
4278         exec_controls_set(vmx, vmx_exec_control(vmx));
4279
4280         if (cpu_has_secondary_exec_ctrls()) {
4281                 vmx_compute_secondary_exec_control(vmx);
4282                 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4283         }
4284
4285         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4286                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4287                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4288                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4289                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4290
4291                 vmcs_write16(GUEST_INTR_STATUS, 0);
4292
4293                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4294                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4295         }
4296
4297         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4298                 vmcs_write32(PLE_GAP, ple_gap);
4299                 vmx->ple_window = ple_window;
4300                 vmx->ple_window_dirty = true;
4301         }
4302
4303         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4304         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4305         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4306
4307         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4308         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4309         vmx_set_constant_host_state(vmx);
4310         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4311         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4312
4313         if (cpu_has_vmx_vmfunc())
4314                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4315
4316         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4317         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4318         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4319         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4320         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4321
4322         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4323                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4324
4325         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4326
4327         /* 22.2.1, 20.8.1 */
4328         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4329
4330         vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4331         vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4332
4333         set_cr4_guest_host_mask(vmx);
4334
4335         if (vmx->vpid != 0)
4336                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4337
4338         if (vmx_xsaves_supported())
4339                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4340
4341         if (enable_pml) {
4342                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4343                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4344         }
4345
4346         if (cpu_has_vmx_encls_vmexit())
4347                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4348
4349         if (vmx_pt_mode_is_host_guest()) {
4350                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4351                 /* Bit[6~0] are forced to 1, writes are ignored. */
4352                 vmx->pt_desc.guest.output_mask = 0x7F;
4353                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4354         }
4355
4356         /*
4357          * If EPT is enabled, #PF is only trapped if MAXPHYADDR is mismatched
4358          * between guest and host.  In that case we only care about present
4359          * faults.
4360          */
4361         if (enable_ept) {
4362                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, PFERR_PRESENT_MASK);
4363                 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, PFERR_PRESENT_MASK);
4364         }
4365 }
4366
4367 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4368 {
4369         struct vcpu_vmx *vmx = to_vmx(vcpu);
4370         struct msr_data apic_base_msr;
4371         u64 cr0;
4372
4373         vmx->rmode.vm86_active = 0;
4374         vmx->spec_ctrl = 0;
4375
4376         vmx->msr_ia32_umwait_control = 0;
4377
4378         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4379         vmx->hv_deadline_tsc = -1;
4380         kvm_set_cr8(vcpu, 0);
4381
4382         if (!init_event) {
4383                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4384                                      MSR_IA32_APICBASE_ENABLE;
4385                 if (kvm_vcpu_is_reset_bsp(vcpu))
4386                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4387                 apic_base_msr.host_initiated = true;
4388                 kvm_set_apic_base(vcpu, &apic_base_msr);
4389         }
4390
4391         vmx_segment_cache_clear(vmx);
4392
4393         seg_setup(VCPU_SREG_CS);
4394         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4395         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4396
4397         seg_setup(VCPU_SREG_DS);
4398         seg_setup(VCPU_SREG_ES);
4399         seg_setup(VCPU_SREG_FS);
4400         seg_setup(VCPU_SREG_GS);
4401         seg_setup(VCPU_SREG_SS);
4402
4403         vmcs_write16(GUEST_TR_SELECTOR, 0);
4404         vmcs_writel(GUEST_TR_BASE, 0);
4405         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4406         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4407
4408         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4409         vmcs_writel(GUEST_LDTR_BASE, 0);
4410         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4411         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4412
4413         if (!init_event) {
4414                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4415                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4416                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4417                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4418         }
4419
4420         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4421         kvm_rip_write(vcpu, 0xfff0);
4422
4423         vmcs_writel(GUEST_GDTR_BASE, 0);
4424         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4425
4426         vmcs_writel(GUEST_IDTR_BASE, 0);
4427         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4428
4429         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4430         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4431         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4432         if (kvm_mpx_supported())
4433                 vmcs_write64(GUEST_BNDCFGS, 0);
4434
4435         setup_msrs(vmx);
4436
4437         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4438
4439         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4440                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4441                 if (cpu_need_tpr_shadow(vcpu))
4442                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4443                                      __pa(vcpu->arch.apic->regs));
4444                 vmcs_write32(TPR_THRESHOLD, 0);
4445         }
4446
4447         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4448
4449         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4450         vmx->vcpu.arch.cr0 = cr0;
4451         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4452         vmx_set_cr4(vcpu, 0);
4453         vmx_set_efer(vcpu, 0);
4454
4455         update_exception_bitmap(vcpu);
4456
4457         vpid_sync_context(vmx->vpid);
4458         if (init_event)
4459                 vmx_clear_hlt(vcpu);
4460 }
4461
4462 static void enable_irq_window(struct kvm_vcpu *vcpu)
4463 {
4464         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4465 }
4466
4467 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4468 {
4469         if (!enable_vnmi ||
4470             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4471                 enable_irq_window(vcpu);
4472                 return;
4473         }
4474
4475         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4476 }
4477
4478 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4479 {
4480         struct vcpu_vmx *vmx = to_vmx(vcpu);
4481         uint32_t intr;
4482         int irq = vcpu->arch.interrupt.nr;
4483
4484         trace_kvm_inj_virq(irq);
4485
4486         ++vcpu->stat.irq_injections;
4487         if (vmx->rmode.vm86_active) {
4488                 int inc_eip = 0;
4489                 if (vcpu->arch.interrupt.soft)
4490                         inc_eip = vcpu->arch.event_exit_inst_len;
4491                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4492                 return;
4493         }
4494         intr = irq | INTR_INFO_VALID_MASK;
4495         if (vcpu->arch.interrupt.soft) {
4496                 intr |= INTR_TYPE_SOFT_INTR;
4497                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4498                              vmx->vcpu.arch.event_exit_inst_len);
4499         } else
4500                 intr |= INTR_TYPE_EXT_INTR;
4501         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4502
4503         vmx_clear_hlt(vcpu);
4504 }
4505
4506 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4507 {
4508         struct vcpu_vmx *vmx = to_vmx(vcpu);
4509
4510         if (!enable_vnmi) {
4511                 /*
4512                  * Tracking the NMI-blocked state in software is built upon
4513                  * finding the next open IRQ window. This, in turn, depends on
4514                  * well-behaving guests: They have to keep IRQs disabled at
4515                  * least as long as the NMI handler runs. Otherwise we may
4516                  * cause NMI nesting, maybe breaking the guest. But as this is
4517                  * highly unlikely, we can live with the residual risk.
4518                  */
4519                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4520                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4521         }
4522
4523         ++vcpu->stat.nmi_injections;
4524         vmx->loaded_vmcs->nmi_known_unmasked = false;
4525
4526         if (vmx->rmode.vm86_active) {
4527                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4528                 return;
4529         }
4530
4531         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4532                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4533
4534         vmx_clear_hlt(vcpu);
4535 }
4536
4537 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4538 {
4539         struct vcpu_vmx *vmx = to_vmx(vcpu);
4540         bool masked;
4541
4542         if (!enable_vnmi)
4543                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4544         if (vmx->loaded_vmcs->nmi_known_unmasked)
4545                 return false;
4546         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4547         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4548         return masked;
4549 }
4550
4551 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4552 {
4553         struct vcpu_vmx *vmx = to_vmx(vcpu);
4554
4555         if (!enable_vnmi) {
4556                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4557                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4558                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4559                 }
4560         } else {
4561                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4562                 if (masked)
4563                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4564                                       GUEST_INTR_STATE_NMI);
4565                 else
4566                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4567                                         GUEST_INTR_STATE_NMI);
4568         }
4569 }
4570
4571 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4572 {
4573         if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4574                 return false;
4575
4576         if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4577                 return true;
4578
4579         return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4580                 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4581                  GUEST_INTR_STATE_NMI));
4582 }
4583
4584 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4585 {
4586         if (to_vmx(vcpu)->nested.nested_run_pending)
4587                 return -EBUSY;
4588
4589         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
4590         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4591                 return -EBUSY;
4592
4593         return !vmx_nmi_blocked(vcpu);
4594 }
4595
4596 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4597 {
4598         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4599                 return false;
4600
4601         return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4602                (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4603                 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4604 }
4605
4606 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4607 {
4608         if (to_vmx(vcpu)->nested.nested_run_pending)
4609                 return -EBUSY;
4610
4611        /*
4612         * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4613         * e.g. if the IRQ arrived asynchronously after checking nested events.
4614         */
4615         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4616                 return -EBUSY;
4617
4618         return !vmx_interrupt_blocked(vcpu);
4619 }
4620
4621 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4622 {
4623         int ret;
4624
4625         if (enable_unrestricted_guest)
4626                 return 0;
4627
4628         mutex_lock(&kvm->slots_lock);
4629         ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4630                                       PAGE_SIZE * 3);
4631         mutex_unlock(&kvm->slots_lock);
4632
4633         if (ret)
4634                 return ret;
4635         to_kvm_vmx(kvm)->tss_addr = addr;
4636         return init_rmode_tss(kvm);
4637 }
4638
4639 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4640 {
4641         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4642         return 0;
4643 }
4644
4645 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4646 {
4647         switch (vec) {
4648         case BP_VECTOR:
4649                 /*
4650                  * Update instruction length as we may reinject the exception
4651                  * from user space while in guest debugging mode.
4652                  */
4653                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4654                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4655                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4656                         return false;
4657                 fallthrough;
4658         case DB_VECTOR:
4659                 return !(vcpu->guest_debug &
4660                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4661         case DE_VECTOR:
4662         case OF_VECTOR:
4663         case BR_VECTOR:
4664         case UD_VECTOR:
4665         case DF_VECTOR:
4666         case SS_VECTOR:
4667         case GP_VECTOR:
4668         case MF_VECTOR:
4669                 return true;
4670         }
4671         return false;
4672 }
4673
4674 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4675                                   int vec, u32 err_code)
4676 {
4677         /*
4678          * Instruction with address size override prefix opcode 0x67
4679          * Cause the #SS fault with 0 error code in VM86 mode.
4680          */
4681         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4682                 if (kvm_emulate_instruction(vcpu, 0)) {
4683                         if (vcpu->arch.halt_request) {
4684                                 vcpu->arch.halt_request = 0;
4685                                 return kvm_vcpu_halt(vcpu);
4686                         }
4687                         return 1;
4688                 }
4689                 return 0;
4690         }
4691
4692         /*
4693          * Forward all other exceptions that are valid in real mode.
4694          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4695          *        the required debugging infrastructure rework.
4696          */
4697         kvm_queue_exception(vcpu, vec);
4698         return 1;
4699 }
4700
4701 /*
4702  * Trigger machine check on the host. We assume all the MSRs are already set up
4703  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4704  * We pass a fake environment to the machine check handler because we want
4705  * the guest to be always treated like user space, no matter what context
4706  * it used internally.
4707  */
4708 static void kvm_machine_check(void)
4709 {
4710 #if defined(CONFIG_X86_MCE)
4711         struct pt_regs regs = {
4712                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4713                 .flags = X86_EFLAGS_IF,
4714         };
4715
4716         do_machine_check(&regs);
4717 #endif
4718 }
4719
4720 static int handle_machine_check(struct kvm_vcpu *vcpu)
4721 {
4722         /* handled by vmx_vcpu_run() */
4723         return 1;
4724 }
4725
4726 /*
4727  * If the host has split lock detection disabled, then #AC is
4728  * unconditionally injected into the guest, which is the pre split lock
4729  * detection behaviour.
4730  *
4731  * If the host has split lock detection enabled then #AC is
4732  * only injected into the guest when:
4733  *  - Guest CPL == 3 (user mode)
4734  *  - Guest has #AC detection enabled in CR0
4735  *  - Guest EFLAGS has AC bit set
4736  */
4737 static inline bool guest_inject_ac(struct kvm_vcpu *vcpu)
4738 {
4739         if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4740                 return true;
4741
4742         return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4743                (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4744 }
4745
4746 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4747 {
4748         struct vcpu_vmx *vmx = to_vmx(vcpu);
4749         struct kvm_run *kvm_run = vcpu->run;
4750         u32 intr_info, ex_no, error_code;
4751         unsigned long cr2, rip, dr6;
4752         u32 vect_info;
4753
4754         vect_info = vmx->idt_vectoring_info;
4755         intr_info = vmx_get_intr_info(vcpu);
4756
4757         if (is_machine_check(intr_info) || is_nmi(intr_info))
4758                 return 1; /* handled by handle_exception_nmi_irqoff() */
4759
4760         if (is_invalid_opcode(intr_info))
4761                 return handle_ud(vcpu);
4762
4763         error_code = 0;
4764         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4765                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4766
4767         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4768                 WARN_ON_ONCE(!enable_vmware_backdoor);
4769
4770                 /*
4771                  * VMware backdoor emulation on #GP interception only handles
4772                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4773                  * error code on #GP.
4774                  */
4775                 if (error_code) {
4776                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4777                         return 1;
4778                 }
4779                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4780         }
4781
4782         /*
4783          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4784          * MMIO, it is better to report an internal error.
4785          * See the comments in vmx_handle_exit.
4786          */
4787         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4788             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4789                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4790                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4791                 vcpu->run->internal.ndata = 4;
4792                 vcpu->run->internal.data[0] = vect_info;
4793                 vcpu->run->internal.data[1] = intr_info;
4794                 vcpu->run->internal.data[2] = error_code;
4795                 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4796                 return 0;
4797         }
4798
4799         if (is_page_fault(intr_info)) {
4800                 cr2 = vmx_get_exit_qual(vcpu);
4801                 if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4802                         /*
4803                          * EPT will cause page fault only if we need to
4804                          * detect illegal GPAs.
4805                          */
4806                         kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4807                         return 1;
4808                 } else
4809                         return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4810         }
4811
4812         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4813
4814         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4815                 return handle_rmode_exception(vcpu, ex_no, error_code);
4816
4817         switch (ex_no) {
4818         case DB_VECTOR:
4819                 dr6 = vmx_get_exit_qual(vcpu);
4820                 if (!(vcpu->guest_debug &
4821                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4822                         if (is_icebp(intr_info))
4823                                 WARN_ON(!skip_emulated_instruction(vcpu));
4824
4825                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4826                         return 1;
4827                 }
4828                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4829                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4830                 fallthrough;
4831         case BP_VECTOR:
4832                 /*
4833                  * Update instruction length as we may reinject #BP from
4834                  * user space while in guest debugging mode. Reading it for
4835                  * #DB as well causes no harm, it is not used in that case.
4836                  */
4837                 vmx->vcpu.arch.event_exit_inst_len =
4838                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4839                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4840                 rip = kvm_rip_read(vcpu);
4841                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4842                 kvm_run->debug.arch.exception = ex_no;
4843                 break;
4844         case AC_VECTOR:
4845                 if (guest_inject_ac(vcpu)) {
4846                         kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4847                         return 1;
4848                 }
4849
4850                 /*
4851                  * Handle split lock. Depending on detection mode this will
4852                  * either warn and disable split lock detection for this
4853                  * task or force SIGBUS on it.
4854                  */
4855                 if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4856                         return 1;
4857                 fallthrough;
4858         default:
4859                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4860                 kvm_run->ex.exception = ex_no;
4861                 kvm_run->ex.error_code = error_code;
4862                 break;
4863         }
4864         return 0;
4865 }
4866
4867 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4868 {
4869         ++vcpu->stat.irq_exits;
4870         return 1;
4871 }
4872
4873 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4874 {
4875         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4876         vcpu->mmio_needed = 0;
4877         return 0;
4878 }
4879
4880 static int handle_io(struct kvm_vcpu *vcpu)
4881 {
4882         unsigned long exit_qualification;
4883         int size, in, string;
4884         unsigned port;
4885
4886         exit_qualification = vmx_get_exit_qual(vcpu);
4887         string = (exit_qualification & 16) != 0;
4888
4889         ++vcpu->stat.io_exits;
4890
4891         if (string)
4892                 return kvm_emulate_instruction(vcpu, 0);
4893
4894         port = exit_qualification >> 16;
4895         size = (exit_qualification & 7) + 1;
4896         in = (exit_qualification & 8) != 0;
4897
4898         return kvm_fast_pio(vcpu, size, port, in);
4899 }
4900
4901 static void
4902 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4903 {
4904         /*
4905          * Patch in the VMCALL instruction:
4906          */
4907         hypercall[0] = 0x0f;
4908         hypercall[1] = 0x01;
4909         hypercall[2] = 0xc1;
4910 }
4911
4912 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4913 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4914 {
4915         if (is_guest_mode(vcpu)) {
4916                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4917                 unsigned long orig_val = val;
4918
4919                 /*
4920                  * We get here when L2 changed cr0 in a way that did not change
4921                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4922                  * but did change L0 shadowed bits. So we first calculate the
4923                  * effective cr0 value that L1 would like to write into the
4924                  * hardware. It consists of the L2-owned bits from the new
4925                  * value combined with the L1-owned bits from L1's guest_cr0.
4926                  */
4927                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4928                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4929
4930                 if (!nested_guest_cr0_valid(vcpu, val))
4931                         return 1;
4932
4933                 if (kvm_set_cr0(vcpu, val))
4934                         return 1;
4935                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4936                 return 0;
4937         } else {
4938                 if (to_vmx(vcpu)->nested.vmxon &&
4939                     !nested_host_cr0_valid(vcpu, val))
4940                         return 1;
4941
4942                 return kvm_set_cr0(vcpu, val);
4943         }
4944 }
4945
4946 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4947 {
4948         if (is_guest_mode(vcpu)) {
4949                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4950                 unsigned long orig_val = val;
4951
4952                 /* analogously to handle_set_cr0 */
4953                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4954                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4955                 if (kvm_set_cr4(vcpu, val))
4956                         return 1;
4957                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4958                 return 0;
4959         } else
4960                 return kvm_set_cr4(vcpu, val);
4961 }
4962
4963 static int handle_desc(struct kvm_vcpu *vcpu)
4964 {
4965         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4966         return kvm_emulate_instruction(vcpu, 0);
4967 }
4968
4969 static int handle_cr(struct kvm_vcpu *vcpu)
4970 {
4971         unsigned long exit_qualification, val;
4972         int cr;
4973         int reg;
4974         int err;
4975         int ret;
4976
4977         exit_qualification = vmx_get_exit_qual(vcpu);
4978         cr = exit_qualification & 15;
4979         reg = (exit_qualification >> 8) & 15;
4980         switch ((exit_qualification >> 4) & 3) {
4981         case 0: /* mov to cr */
4982                 val = kvm_register_readl(vcpu, reg);
4983                 trace_kvm_cr_write(cr, val);
4984                 switch (cr) {
4985                 case 0:
4986                         err = handle_set_cr0(vcpu, val);
4987                         return kvm_complete_insn_gp(vcpu, err);
4988                 case 3:
4989                         WARN_ON_ONCE(enable_unrestricted_guest);
4990                         err = kvm_set_cr3(vcpu, val);
4991                         return kvm_complete_insn_gp(vcpu, err);
4992                 case 4:
4993                         err = handle_set_cr4(vcpu, val);
4994                         return kvm_complete_insn_gp(vcpu, err);
4995                 case 8: {
4996                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4997                                 u8 cr8 = (u8)val;
4998                                 err = kvm_set_cr8(vcpu, cr8);
4999                                 ret = kvm_complete_insn_gp(vcpu, err);
5000                                 if (lapic_in_kernel(vcpu))
5001                                         return ret;
5002                                 if (cr8_prev <= cr8)
5003                                         return ret;
5004                                 /*
5005                                  * TODO: we might be squashing a
5006                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5007                                  * KVM_EXIT_DEBUG here.
5008                                  */
5009                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5010                                 return 0;
5011                         }
5012                 }
5013                 break;
5014         case 2: /* clts */
5015                 WARN_ONCE(1, "Guest should always own CR0.TS");
5016                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5017                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5018                 return kvm_skip_emulated_instruction(vcpu);
5019         case 1: /*mov from cr*/
5020                 switch (cr) {
5021                 case 3:
5022                         WARN_ON_ONCE(enable_unrestricted_guest);
5023                         val = kvm_read_cr3(vcpu);
5024                         kvm_register_write(vcpu, reg, val);
5025                         trace_kvm_cr_read(cr, val);
5026                         return kvm_skip_emulated_instruction(vcpu);
5027                 case 8:
5028                         val = kvm_get_cr8(vcpu);
5029                         kvm_register_write(vcpu, reg, val);
5030                         trace_kvm_cr_read(cr, val);
5031                         return kvm_skip_emulated_instruction(vcpu);
5032                 }
5033                 break;
5034         case 3: /* lmsw */
5035                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5036                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5037                 kvm_lmsw(vcpu, val);
5038
5039                 return kvm_skip_emulated_instruction(vcpu);
5040         default:
5041                 break;
5042         }
5043         vcpu->run->exit_reason = 0;
5044         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5045                (int)(exit_qualification >> 4) & 3, cr);
5046         return 0;
5047 }
5048
5049 static int handle_dr(struct kvm_vcpu *vcpu)
5050 {
5051         unsigned long exit_qualification;
5052         int dr, dr7, reg;
5053
5054         exit_qualification = vmx_get_exit_qual(vcpu);
5055         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5056
5057         /* First, if DR does not exist, trigger UD */
5058         if (!kvm_require_dr(vcpu, dr))
5059                 return 1;
5060
5061         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5062         if (!kvm_require_cpl(vcpu, 0))
5063                 return 1;
5064         dr7 = vmcs_readl(GUEST_DR7);
5065         if (dr7 & DR7_GD) {
5066                 /*
5067                  * As the vm-exit takes precedence over the debug trap, we
5068                  * need to emulate the latter, either for the host or the
5069                  * guest debugging itself.
5070                  */
5071                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5072                         vcpu->run->debug.arch.dr6 = DR6_BD | DR6_RTM | DR6_FIXED_1;
5073                         vcpu->run->debug.arch.dr7 = dr7;
5074                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5075                         vcpu->run->debug.arch.exception = DB_VECTOR;
5076                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5077                         return 0;
5078                 } else {
5079                         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5080                         return 1;
5081                 }
5082         }
5083
5084         if (vcpu->guest_debug == 0) {
5085                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5086
5087                 /*
5088                  * No more DR vmexits; force a reload of the debug registers
5089                  * and reenter on this instruction.  The next vmexit will
5090                  * retrieve the full state of the debug registers.
5091                  */
5092                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5093                 return 1;
5094         }
5095
5096         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5097         if (exit_qualification & TYPE_MOV_FROM_DR) {
5098                 unsigned long val;
5099
5100                 if (kvm_get_dr(vcpu, dr, &val))
5101                         return 1;
5102                 kvm_register_write(vcpu, reg, val);
5103         } else
5104                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5105                         return 1;
5106
5107         return kvm_skip_emulated_instruction(vcpu);
5108 }
5109
5110 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5111 {
5112         get_debugreg(vcpu->arch.db[0], 0);
5113         get_debugreg(vcpu->arch.db[1], 1);
5114         get_debugreg(vcpu->arch.db[2], 2);
5115         get_debugreg(vcpu->arch.db[3], 3);
5116         get_debugreg(vcpu->arch.dr6, 6);
5117         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5118
5119         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5120         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5121 }
5122
5123 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5124 {
5125         vmcs_writel(GUEST_DR7, val);
5126 }
5127
5128 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5129 {
5130         kvm_apic_update_ppr(vcpu);
5131         return 1;
5132 }
5133
5134 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5135 {
5136         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5137
5138         kvm_make_request(KVM_REQ_EVENT, vcpu);
5139
5140         ++vcpu->stat.irq_window_exits;
5141         return 1;
5142 }
5143
5144 static int handle_vmcall(struct kvm_vcpu *vcpu)
5145 {
5146         return kvm_emulate_hypercall(vcpu);
5147 }
5148
5149 static int handle_invd(struct kvm_vcpu *vcpu)
5150 {
5151         return kvm_emulate_instruction(vcpu, 0);
5152 }
5153
5154 static int handle_invlpg(struct kvm_vcpu *vcpu)
5155 {
5156         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5157
5158         kvm_mmu_invlpg(vcpu, exit_qualification);
5159         return kvm_skip_emulated_instruction(vcpu);
5160 }
5161
5162 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5163 {
5164         int err;
5165
5166         err = kvm_rdpmc(vcpu);
5167         return kvm_complete_insn_gp(vcpu, err);
5168 }
5169
5170 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5171 {
5172         return kvm_emulate_wbinvd(vcpu);
5173 }
5174
5175 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5176 {
5177         u64 new_bv = kvm_read_edx_eax(vcpu);
5178         u32 index = kvm_rcx_read(vcpu);
5179
5180         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5181                 return kvm_skip_emulated_instruction(vcpu);
5182         return 1;
5183 }
5184
5185 static int handle_apic_access(struct kvm_vcpu *vcpu)
5186 {
5187         if (likely(fasteoi)) {
5188                 unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5189                 int access_type, offset;
5190
5191                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5192                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5193                 /*
5194                  * Sane guest uses MOV to write EOI, with written value
5195                  * not cared. So make a short-circuit here by avoiding
5196                  * heavy instruction emulation.
5197                  */
5198                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5199                     (offset == APIC_EOI)) {
5200                         kvm_lapic_set_eoi(vcpu);
5201                         return kvm_skip_emulated_instruction(vcpu);
5202                 }
5203         }
5204         return kvm_emulate_instruction(vcpu, 0);
5205 }
5206
5207 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5208 {
5209         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5210         int vector = exit_qualification & 0xff;
5211
5212         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5213         kvm_apic_set_eoi_accelerated(vcpu, vector);
5214         return 1;
5215 }
5216
5217 static int handle_apic_write(struct kvm_vcpu *vcpu)
5218 {
5219         unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5220         u32 offset = exit_qualification & 0xfff;
5221
5222         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5223         kvm_apic_write_nodecode(vcpu, offset);
5224         return 1;
5225 }
5226
5227 static int handle_task_switch(struct kvm_vcpu *vcpu)
5228 {
5229         struct vcpu_vmx *vmx = to_vmx(vcpu);
5230         unsigned long exit_qualification;
5231         bool has_error_code = false;
5232         u32 error_code = 0;
5233         u16 tss_selector;
5234         int reason, type, idt_v, idt_index;
5235
5236         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5237         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5238         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5239
5240         exit_qualification = vmx_get_exit_qual(vcpu);
5241
5242         reason = (u32)exit_qualification >> 30;
5243         if (reason == TASK_SWITCH_GATE && idt_v) {
5244                 switch (type) {
5245                 case INTR_TYPE_NMI_INTR:
5246                         vcpu->arch.nmi_injected = false;
5247                         vmx_set_nmi_mask(vcpu, true);
5248                         break;
5249                 case INTR_TYPE_EXT_INTR:
5250                 case INTR_TYPE_SOFT_INTR:
5251                         kvm_clear_interrupt_queue(vcpu);
5252                         break;
5253                 case INTR_TYPE_HARD_EXCEPTION:
5254                         if (vmx->idt_vectoring_info &
5255                             VECTORING_INFO_DELIVER_CODE_MASK) {
5256                                 has_error_code = true;
5257                                 error_code =
5258                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5259                         }
5260                         fallthrough;
5261                 case INTR_TYPE_SOFT_EXCEPTION:
5262                         kvm_clear_exception_queue(vcpu);
5263                         break;
5264                 default:
5265                         break;
5266                 }
5267         }
5268         tss_selector = exit_qualification;
5269
5270         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5271                        type != INTR_TYPE_EXT_INTR &&
5272                        type != INTR_TYPE_NMI_INTR))
5273                 WARN_ON(!skip_emulated_instruction(vcpu));
5274
5275         /*
5276          * TODO: What about debug traps on tss switch?
5277          *       Are we supposed to inject them and update dr6?
5278          */
5279         return kvm_task_switch(vcpu, tss_selector,
5280                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5281                                reason, has_error_code, error_code);
5282 }
5283
5284 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5285 {
5286         unsigned long exit_qualification;
5287         gpa_t gpa;
5288         u64 error_code;
5289
5290         exit_qualification = vmx_get_exit_qual(vcpu);
5291
5292         /*
5293          * EPT violation happened while executing iret from NMI,
5294          * "blocked by NMI" bit has to be set before next VM entry.
5295          * There are errata that may cause this bit to not be set:
5296          * AAK134, BY25.
5297          */
5298         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5299                         enable_vnmi &&
5300                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5301                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5302
5303         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5304         trace_kvm_page_fault(gpa, exit_qualification);
5305
5306         /* Is it a read fault? */
5307         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5308                      ? PFERR_USER_MASK : 0;
5309         /* Is it a write fault? */
5310         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5311                       ? PFERR_WRITE_MASK : 0;
5312         /* Is it a fetch fault? */
5313         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5314                       ? PFERR_FETCH_MASK : 0;
5315         /* ept page table entry is present? */
5316         error_code |= (exit_qualification &
5317                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5318                         EPT_VIOLATION_EXECUTABLE))
5319                       ? PFERR_PRESENT_MASK : 0;
5320
5321         error_code |= (exit_qualification & 0x100) != 0 ?
5322                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5323
5324         vcpu->arch.exit_qualification = exit_qualification;
5325
5326         /*
5327          * Check that the GPA doesn't exceed physical memory limits, as that is
5328          * a guest page fault.  We have to emulate the instruction here, because
5329          * if the illegal address is that of a paging structure, then
5330          * EPT_VIOLATION_ACC_WRITE bit is set.  Alternatively, if supported we
5331          * would also use advanced VM-exit information for EPT violations to
5332          * reconstruct the page fault error code.
5333          */
5334         if (unlikely(kvm_mmu_is_illegal_gpa(vcpu, gpa)))
5335                 return kvm_emulate_instruction(vcpu, 0);
5336
5337         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5338 }
5339
5340 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5341 {
5342         gpa_t gpa;
5343
5344         /*
5345          * A nested guest cannot optimize MMIO vmexits, because we have an
5346          * nGPA here instead of the required GPA.
5347          */
5348         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5349         if (!is_guest_mode(vcpu) &&
5350             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5351                 trace_kvm_fast_mmio(gpa);
5352                 return kvm_skip_emulated_instruction(vcpu);
5353         }
5354
5355         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5356 }
5357
5358 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5359 {
5360         WARN_ON_ONCE(!enable_vnmi);
5361         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5362         ++vcpu->stat.nmi_window_exits;
5363         kvm_make_request(KVM_REQ_EVENT, vcpu);
5364
5365         return 1;
5366 }
5367
5368 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5369 {
5370         struct vcpu_vmx *vmx = to_vmx(vcpu);
5371         bool intr_window_requested;
5372         unsigned count = 130;
5373
5374         intr_window_requested = exec_controls_get(vmx) &
5375                                 CPU_BASED_INTR_WINDOW_EXITING;
5376
5377         while (vmx->emulation_required && count-- != 0) {
5378                 if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5379                         return handle_interrupt_window(&vmx->vcpu);
5380
5381                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5382                         return 1;
5383
5384                 if (!kvm_emulate_instruction(vcpu, 0))
5385                         return 0;
5386
5387                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5388                     vcpu->arch.exception.pending) {
5389                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5390                         vcpu->run->internal.suberror =
5391                                                 KVM_INTERNAL_ERROR_EMULATION;
5392                         vcpu->run->internal.ndata = 0;
5393                         return 0;
5394                 }
5395
5396                 if (vcpu->arch.halt_request) {
5397                         vcpu->arch.halt_request = 0;
5398                         return kvm_vcpu_halt(vcpu);
5399                 }
5400
5401                 /*
5402                  * Note, return 1 and not 0, vcpu_run() will invoke
5403                  * xfer_to_guest_mode() which will create a proper return
5404                  * code.
5405                  */
5406                 if (__xfer_to_guest_mode_work_pending())
5407                         return 1;
5408         }
5409
5410         return 1;
5411 }
5412
5413 static void grow_ple_window(struct kvm_vcpu *vcpu)
5414 {
5415         struct vcpu_vmx *vmx = to_vmx(vcpu);
5416         unsigned int old = vmx->ple_window;
5417
5418         vmx->ple_window = __grow_ple_window(old, ple_window,
5419                                             ple_window_grow,
5420                                             ple_window_max);
5421
5422         if (vmx->ple_window != old) {
5423                 vmx->ple_window_dirty = true;
5424                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5425                                             vmx->ple_window, old);
5426         }
5427 }
5428
5429 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5430 {
5431         struct vcpu_vmx *vmx = to_vmx(vcpu);
5432         unsigned int old = vmx->ple_window;
5433
5434         vmx->ple_window = __shrink_ple_window(old, ple_window,
5435                                               ple_window_shrink,
5436                                               ple_window);
5437
5438         if (vmx->ple_window != old) {
5439                 vmx->ple_window_dirty = true;
5440                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5441                                             vmx->ple_window, old);
5442         }
5443 }
5444
5445 /*
5446  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5447  */
5448 static void wakeup_handler(void)
5449 {
5450         struct kvm_vcpu *vcpu;
5451         int cpu = smp_processor_id();
5452
5453         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5454         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5455                         blocked_vcpu_list) {
5456                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5457
5458                 if (pi_test_on(pi_desc) == 1)
5459                         kvm_vcpu_kick(vcpu);
5460         }
5461         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5462 }
5463
5464 static void vmx_enable_tdp(void)
5465 {
5466         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5467                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5468                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5469                 0ull, VMX_EPT_EXECUTABLE_MASK,
5470                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5471                 VMX_EPT_RWX_MASK, 0ull);
5472
5473         ept_set_mmio_spte_mask();
5474 }
5475
5476 /*
5477  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5478  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5479  */
5480 static int handle_pause(struct kvm_vcpu *vcpu)
5481 {
5482         if (!kvm_pause_in_guest(vcpu->kvm))
5483                 grow_ple_window(vcpu);
5484
5485         /*
5486          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5487          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5488          * never set PAUSE_EXITING and just set PLE if supported,
5489          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5490          */
5491         kvm_vcpu_on_spin(vcpu, true);
5492         return kvm_skip_emulated_instruction(vcpu);
5493 }
5494
5495 static int handle_nop(struct kvm_vcpu *vcpu)
5496 {
5497         return kvm_skip_emulated_instruction(vcpu);
5498 }
5499
5500 static int handle_mwait(struct kvm_vcpu *vcpu)
5501 {
5502         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5503         return handle_nop(vcpu);
5504 }
5505
5506 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5507 {
5508         kvm_queue_exception(vcpu, UD_VECTOR);
5509         return 1;
5510 }
5511
5512 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5513 {
5514         return 1;
5515 }
5516
5517 static int handle_monitor(struct kvm_vcpu *vcpu)
5518 {
5519         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5520         return handle_nop(vcpu);
5521 }
5522
5523 static int handle_invpcid(struct kvm_vcpu *vcpu)
5524 {
5525         u32 vmx_instruction_info;
5526         unsigned long type;
5527         bool pcid_enabled;
5528         gva_t gva;
5529         struct x86_exception e;
5530         unsigned i;
5531         unsigned long roots_to_free = 0;
5532         struct {
5533                 u64 pcid;
5534                 u64 gla;
5535         } operand;
5536         int r;
5537
5538         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5539                 kvm_queue_exception(vcpu, UD_VECTOR);
5540                 return 1;
5541         }
5542
5543         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5544         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5545
5546         if (type > 3) {
5547                 kvm_inject_gp(vcpu, 0);
5548                 return 1;
5549         }
5550
5551         /* According to the Intel instruction reference, the memory operand
5552          * is read even if it isn't needed (e.g., for type==all)
5553          */
5554         if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5555                                 vmx_instruction_info, false,
5556                                 sizeof(operand), &gva))
5557                 return 1;
5558
5559         r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
5560         if (r != X86EMUL_CONTINUE)
5561                 return vmx_handle_memory_failure(vcpu, r, &e);
5562
5563         if (operand.pcid >> 12 != 0) {
5564                 kvm_inject_gp(vcpu, 0);
5565                 return 1;
5566         }
5567
5568         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5569
5570         switch (type) {
5571         case INVPCID_TYPE_INDIV_ADDR:
5572                 if ((!pcid_enabled && (operand.pcid != 0)) ||
5573                     is_noncanonical_address(operand.gla, vcpu)) {
5574                         kvm_inject_gp(vcpu, 0);
5575                         return 1;
5576                 }
5577                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5578                 return kvm_skip_emulated_instruction(vcpu);
5579
5580         case INVPCID_TYPE_SINGLE_CTXT:
5581                 if (!pcid_enabled && (operand.pcid != 0)) {
5582                         kvm_inject_gp(vcpu, 0);
5583                         return 1;
5584                 }
5585
5586                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5587                         kvm_mmu_sync_roots(vcpu);
5588                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
5589                 }
5590
5591                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5592                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
5593                             == operand.pcid)
5594                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5595
5596                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5597                 /*
5598                  * If neither the current cr3 nor any of the prev_roots use the
5599                  * given PCID, then nothing needs to be done here because a
5600                  * resync will happen anyway before switching to any other CR3.
5601                  */
5602
5603                 return kvm_skip_emulated_instruction(vcpu);
5604
5605         case INVPCID_TYPE_ALL_NON_GLOBAL:
5606                 /*
5607                  * Currently, KVM doesn't mark global entries in the shadow
5608                  * page tables, so a non-global flush just degenerates to a
5609                  * global flush. If needed, we could optimize this later by
5610                  * keeping track of global entries in shadow page tables.
5611                  */
5612
5613                 fallthrough;
5614         case INVPCID_TYPE_ALL_INCL_GLOBAL:
5615                 kvm_mmu_unload(vcpu);
5616                 return kvm_skip_emulated_instruction(vcpu);
5617
5618         default:
5619                 BUG(); /* We have already checked above that type <= 3 */
5620         }
5621 }
5622
5623 static int handle_pml_full(struct kvm_vcpu *vcpu)
5624 {
5625         unsigned long exit_qualification;
5626
5627         trace_kvm_pml_full(vcpu->vcpu_id);
5628
5629         exit_qualification = vmx_get_exit_qual(vcpu);
5630
5631         /*
5632          * PML buffer FULL happened while executing iret from NMI,
5633          * "blocked by NMI" bit has to be set before next VM entry.
5634          */
5635         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5636                         enable_vnmi &&
5637                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5638                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5639                                 GUEST_INTR_STATE_NMI);
5640
5641         /*
5642          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5643          * here.., and there's no userspace involvement needed for PML.
5644          */
5645         return 1;
5646 }
5647
5648 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5649 {
5650         struct vcpu_vmx *vmx = to_vmx(vcpu);
5651
5652         if (!vmx->req_immediate_exit &&
5653             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5654                 kvm_lapic_expired_hv_timer(vcpu);
5655                 return EXIT_FASTPATH_REENTER_GUEST;
5656         }
5657
5658         return EXIT_FASTPATH_NONE;
5659 }
5660
5661 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5662 {
5663         handle_fastpath_preemption_timer(vcpu);
5664         return 1;
5665 }
5666
5667 /*
5668  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5669  * are overwritten by nested_vmx_setup() when nested=1.
5670  */
5671 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5672 {
5673         kvm_queue_exception(vcpu, UD_VECTOR);
5674         return 1;
5675 }
5676
5677 static int handle_encls(struct kvm_vcpu *vcpu)
5678 {
5679         /*
5680          * SGX virtualization is not yet supported.  There is no software
5681          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5682          * to prevent the guest from executing ENCLS.
5683          */
5684         kvm_queue_exception(vcpu, UD_VECTOR);
5685         return 1;
5686 }
5687
5688 /*
5689  * The exit handlers return 1 if the exit was handled fully and guest execution
5690  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5691  * to be done to userspace and return 0.
5692  */
5693 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5694         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5695         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5696         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5697         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5698         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5699         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5700         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5701         [EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5702         [EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5703         [EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5704         [EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5705         [EXIT_REASON_HLT]                     = kvm_emulate_halt,
5706         [EXIT_REASON_INVD]                    = handle_invd,
5707         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5708         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5709         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5710         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5711         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5712         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5713         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5714         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5715         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5716         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5717         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5718         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5719         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5720         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5721         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5722         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5723         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5724         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5725         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5726         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5727         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5728         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5729         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5730         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5731         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5732         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
5733         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5734         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
5735         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5736         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5737         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
5738         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
5739         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5740         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5741         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5742         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5743         [EXIT_REASON_ENCLS]                   = handle_encls,
5744 };
5745
5746 static const int kvm_vmx_max_exit_handlers =
5747         ARRAY_SIZE(kvm_vmx_exit_handlers);
5748
5749 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5750 {
5751         *info1 = vmx_get_exit_qual(vcpu);
5752         *info2 = vmx_get_intr_info(vcpu);
5753 }
5754
5755 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5756 {
5757         if (vmx->pml_pg) {
5758                 __free_page(vmx->pml_pg);
5759                 vmx->pml_pg = NULL;
5760         }
5761 }
5762
5763 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5764 {
5765         struct vcpu_vmx *vmx = to_vmx(vcpu);
5766         u64 *pml_buf;
5767         u16 pml_idx;
5768
5769         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5770
5771         /* Do nothing if PML buffer is empty */
5772         if (pml_idx == (PML_ENTITY_NUM - 1))
5773                 return;
5774
5775         /* PML index always points to next available PML buffer entity */
5776         if (pml_idx >= PML_ENTITY_NUM)
5777                 pml_idx = 0;
5778         else
5779                 pml_idx++;
5780
5781         pml_buf = page_address(vmx->pml_pg);
5782         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5783                 u64 gpa;
5784
5785                 gpa = pml_buf[pml_idx];
5786                 WARN_ON(gpa & (PAGE_SIZE - 1));
5787                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5788         }
5789
5790         /* reset PML index */
5791         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5792 }
5793
5794 /*
5795  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5796  * Called before reporting dirty_bitmap to userspace.
5797  */
5798 static void kvm_flush_pml_buffers(struct kvm *kvm)
5799 {
5800         int i;
5801         struct kvm_vcpu *vcpu;
5802         /*
5803          * We only need to kick vcpu out of guest mode here, as PML buffer
5804          * is flushed at beginning of all VMEXITs, and it's obvious that only
5805          * vcpus running in guest are possible to have unflushed GPAs in PML
5806          * buffer.
5807          */
5808         kvm_for_each_vcpu(i, vcpu, kvm)
5809                 kvm_vcpu_kick(vcpu);
5810 }
5811
5812 static void vmx_dump_sel(char *name, uint32_t sel)
5813 {
5814         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5815                name, vmcs_read16(sel),
5816                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5817                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5818                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5819 }
5820
5821 static void vmx_dump_dtsel(char *name, uint32_t limit)
5822 {
5823         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5824                name, vmcs_read32(limit),
5825                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5826 }
5827
5828 void dump_vmcs(void)
5829 {
5830         u32 vmentry_ctl, vmexit_ctl;
5831         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5832         unsigned long cr4;
5833         u64 efer;
5834
5835         if (!dump_invalid_vmcs) {
5836                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5837                 return;
5838         }
5839
5840         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5841         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5842         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5843         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5844         cr4 = vmcs_readl(GUEST_CR4);
5845         efer = vmcs_read64(GUEST_IA32_EFER);
5846         secondary_exec_control = 0;
5847         if (cpu_has_secondary_exec_ctrls())
5848                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5849
5850         pr_err("*** Guest State ***\n");
5851         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5852                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5853                vmcs_readl(CR0_GUEST_HOST_MASK));
5854         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5855                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5856         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5857         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5858             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5859         {
5860                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5861                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5862                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5863                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5864         }
5865         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5866                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5867         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5868                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5869         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5870                vmcs_readl(GUEST_SYSENTER_ESP),
5871                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5872         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5873         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5874         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5875         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5876         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5877         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5878         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5879         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5880         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5881         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5882         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5883             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5884                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
5885                        efer, vmcs_read64(GUEST_IA32_PAT));
5886         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5887                vmcs_read64(GUEST_IA32_DEBUGCTL),
5888                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5889         if (cpu_has_load_perf_global_ctrl() &&
5890             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5891                 pr_err("PerfGlobCtl = 0x%016llx\n",
5892                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5893         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5894                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5895         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5896                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5897                vmcs_read32(GUEST_ACTIVITY_STATE));
5898         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5899                 pr_err("InterruptStatus = %04x\n",
5900                        vmcs_read16(GUEST_INTR_STATUS));
5901
5902         pr_err("*** Host State ***\n");
5903         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5904                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5905         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5906                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5907                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5908                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5909                vmcs_read16(HOST_TR_SELECTOR));
5910         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5911                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5912                vmcs_readl(HOST_TR_BASE));
5913         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5914                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5915         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5916                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5917                vmcs_readl(HOST_CR4));
5918         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5919                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5920                vmcs_read32(HOST_IA32_SYSENTER_CS),
5921                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5922         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5923                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
5924                        vmcs_read64(HOST_IA32_EFER),
5925                        vmcs_read64(HOST_IA32_PAT));
5926         if (cpu_has_load_perf_global_ctrl() &&
5927             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5928                 pr_err("PerfGlobCtl = 0x%016llx\n",
5929                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5930
5931         pr_err("*** Control State ***\n");
5932         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5933                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5934         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5935         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5936                vmcs_read32(EXCEPTION_BITMAP),
5937                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5938                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5939         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5940                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5941                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5942                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5943         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5944                vmcs_read32(VM_EXIT_INTR_INFO),
5945                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5946                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5947         pr_err("        reason=%08x qualification=%016lx\n",
5948                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5949         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5950                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5951                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5952         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5953         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5954                 pr_err("TSC Multiplier = 0x%016llx\n",
5955                        vmcs_read64(TSC_MULTIPLIER));
5956         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5957                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5958                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5959                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5960                 }
5961                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5962                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5963                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5964                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5965         }
5966         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5967                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5968         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5969                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5970         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5971                 pr_err("PLE Gap=%08x Window=%08x\n",
5972                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5973         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5974                 pr_err("Virtual processor ID = 0x%04x\n",
5975                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5976 }
5977
5978 /*
5979  * The guest has exited.  See if we can fix it or if we need userspace
5980  * assistance.
5981  */
5982 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5983 {
5984         struct vcpu_vmx *vmx = to_vmx(vcpu);
5985         u32 exit_reason = vmx->exit_reason;
5986         u32 vectoring_info = vmx->idt_vectoring_info;
5987
5988         /*
5989          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5990          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5991          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5992          * mode as if vcpus is in root mode, the PML buffer must has been
5993          * flushed already.
5994          */
5995         if (enable_pml)
5996                 vmx_flush_pml_buffer(vcpu);
5997
5998         /*
5999          * We should never reach this point with a pending nested VM-Enter, and
6000          * more specifically emulation of L2 due to invalid guest state (see
6001          * below) should never happen as that means we incorrectly allowed a
6002          * nested VM-Enter with an invalid vmcs12.
6003          */
6004         WARN_ON_ONCE(vmx->nested.nested_run_pending);
6005
6006         /* If guest state is invalid, start emulating */
6007         if (vmx->emulation_required)
6008                 return handle_invalid_guest_state(vcpu);
6009
6010         if (is_guest_mode(vcpu)) {
6011                 /*
6012                  * The host physical addresses of some pages of guest memory
6013                  * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
6014                  * Page). The CPU may write to these pages via their host
6015                  * physical address while L2 is running, bypassing any
6016                  * address-translation-based dirty tracking (e.g. EPT write
6017                  * protection).
6018                  *
6019                  * Mark them dirty on every exit from L2 to prevent them from
6020                  * getting out of sync with dirty tracking.
6021                  */
6022                 nested_mark_vmcs12_pages_dirty(vcpu);
6023
6024                 if (nested_vmx_reflect_vmexit(vcpu))
6025                         return 1;
6026         }
6027
6028         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6029                 dump_vmcs();
6030                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6031                 vcpu->run->fail_entry.hardware_entry_failure_reason
6032                         = exit_reason;
6033                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
6034                 return 0;
6035         }
6036
6037         if (unlikely(vmx->fail)) {
6038                 dump_vmcs();
6039                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6040                 vcpu->run->fail_entry.hardware_entry_failure_reason
6041                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6042                 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
6043                 return 0;
6044         }
6045
6046         /*
6047          * Note:
6048          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6049          * delivery event since it indicates guest is accessing MMIO.
6050          * The vm-exit can be triggered again after return to guest that
6051          * will cause infinite loop.
6052          */
6053         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6054                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6055                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6056                         exit_reason != EXIT_REASON_PML_FULL &&
6057                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6058                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6059                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6060                 vcpu->run->internal.ndata = 3;
6061                 vcpu->run->internal.data[0] = vectoring_info;
6062                 vcpu->run->internal.data[1] = exit_reason;
6063                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
6064                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
6065                         vcpu->run->internal.ndata++;
6066                         vcpu->run->internal.data[3] =
6067                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6068                 }
6069                 vcpu->run->internal.data[vcpu->run->internal.ndata++] =
6070                         vcpu->arch.last_vmentry_cpu;
6071                 return 0;
6072         }
6073
6074         if (unlikely(!enable_vnmi &&
6075                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
6076                 if (!vmx_interrupt_blocked(vcpu)) {
6077                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6078                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
6079                            vcpu->arch.nmi_pending) {
6080                         /*
6081                          * This CPU don't support us in finding the end of an
6082                          * NMI-blocked window if the guest runs with IRQs
6083                          * disabled. So we pull the trigger after 1 s of
6084                          * futile waiting, but inform the user about this.
6085                          */
6086                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6087                                "state on VCPU %d after 1 s timeout\n",
6088                                __func__, vcpu->vcpu_id);
6089                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6090                 }
6091         }
6092
6093         if (exit_fastpath != EXIT_FASTPATH_NONE)
6094                 return 1;
6095
6096         if (exit_reason >= kvm_vmx_max_exit_handlers)
6097                 goto unexpected_vmexit;
6098 #ifdef CONFIG_RETPOLINE
6099         if (exit_reason == EXIT_REASON_MSR_WRITE)
6100                 return kvm_emulate_wrmsr(vcpu);
6101         else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
6102                 return handle_preemption_timer(vcpu);
6103         else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
6104                 return handle_interrupt_window(vcpu);
6105         else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6106                 return handle_external_interrupt(vcpu);
6107         else if (exit_reason == EXIT_REASON_HLT)
6108                 return kvm_emulate_halt(vcpu);
6109         else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
6110                 return handle_ept_misconfig(vcpu);
6111 #endif
6112
6113         exit_reason = array_index_nospec(exit_reason,
6114                                          kvm_vmx_max_exit_handlers);
6115         if (!kvm_vmx_exit_handlers[exit_reason])
6116                 goto unexpected_vmexit;
6117
6118         return kvm_vmx_exit_handlers[exit_reason](vcpu);
6119
6120 unexpected_vmexit:
6121         vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
6122         dump_vmcs();
6123         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6124         vcpu->run->internal.suberror =
6125                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6126         vcpu->run->internal.ndata = 2;
6127         vcpu->run->internal.data[0] = exit_reason;
6128         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6129         return 0;
6130 }
6131
6132 /*
6133  * Software based L1D cache flush which is used when microcode providing
6134  * the cache control MSR is not loaded.
6135  *
6136  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6137  * flush it is required to read in 64 KiB because the replacement algorithm
6138  * is not exactly LRU. This could be sized at runtime via topology
6139  * information but as all relevant affected CPUs have 32KiB L1D cache size
6140  * there is no point in doing so.
6141  */
6142 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6143 {
6144         int size = PAGE_SIZE << L1D_CACHE_ORDER;
6145
6146         /*
6147          * This code is only executed when the the flush mode is 'cond' or
6148          * 'always'
6149          */
6150         if (static_branch_likely(&vmx_l1d_flush_cond)) {
6151                 bool flush_l1d;
6152
6153                 /*
6154                  * Clear the per-vcpu flush bit, it gets set again
6155                  * either from vcpu_run() or from one of the unsafe
6156                  * VMEXIT handlers.
6157                  */
6158                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
6159                 vcpu->arch.l1tf_flush_l1d = false;
6160
6161                 /*
6162                  * Clear the per-cpu flush bit, it gets set again from
6163                  * the interrupt handlers.
6164                  */
6165                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6166                 kvm_clear_cpu_l1tf_flush_l1d();
6167
6168                 if (!flush_l1d)
6169                         return;
6170         }
6171
6172         vcpu->stat.l1d_flush++;
6173
6174         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6175                 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6176                 return;
6177         }
6178
6179         asm volatile(
6180                 /* First ensure the pages are in the TLB */
6181                 "xorl   %%eax, %%eax\n"
6182                 ".Lpopulate_tlb:\n\t"
6183                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6184                 "addl   $4096, %%eax\n\t"
6185                 "cmpl   %%eax, %[size]\n\t"
6186                 "jne    .Lpopulate_tlb\n\t"
6187                 "xorl   %%eax, %%eax\n\t"
6188                 "cpuid\n\t"
6189                 /* Now fill the cache */
6190                 "xorl   %%eax, %%eax\n"
6191                 ".Lfill_cache:\n"
6192                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6193                 "addl   $64, %%eax\n\t"
6194                 "cmpl   %%eax, %[size]\n\t"
6195                 "jne    .Lfill_cache\n\t"
6196                 "lfence\n"
6197                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
6198                     [size] "r" (size)
6199                 : "eax", "ebx", "ecx", "edx");
6200 }
6201
6202 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6203 {
6204         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6205         int tpr_threshold;
6206
6207         if (is_guest_mode(vcpu) &&
6208                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6209                 return;
6210
6211         tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6212         if (is_guest_mode(vcpu))
6213                 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6214         else
6215                 vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6216 }
6217
6218 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6219 {
6220         struct vcpu_vmx *vmx = to_vmx(vcpu);
6221         u32 sec_exec_control;
6222
6223         if (!lapic_in_kernel(vcpu))
6224                 return;
6225
6226         if (!flexpriority_enabled &&
6227             !cpu_has_vmx_virtualize_x2apic_mode())
6228                 return;
6229
6230         /* Postpone execution until vmcs01 is the current VMCS. */
6231         if (is_guest_mode(vcpu)) {
6232                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6233                 return;
6234         }
6235
6236         sec_exec_control = secondary_exec_controls_get(vmx);
6237         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6238                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6239
6240         switch (kvm_get_apic_mode(vcpu)) {
6241         case LAPIC_MODE_INVALID:
6242                 WARN_ONCE(true, "Invalid local APIC state");
6243         case LAPIC_MODE_DISABLED:
6244                 break;
6245         case LAPIC_MODE_XAPIC:
6246                 if (flexpriority_enabled) {
6247                         sec_exec_control |=
6248                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6249                         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6250
6251                         /*
6252                          * Flush the TLB, reloading the APIC access page will
6253                          * only do so if its physical address has changed, but
6254                          * the guest may have inserted a non-APIC mapping into
6255                          * the TLB while the APIC access page was disabled.
6256                          */
6257                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6258                 }
6259                 break;
6260         case LAPIC_MODE_X2APIC:
6261                 if (cpu_has_vmx_virtualize_x2apic_mode())
6262                         sec_exec_control |=
6263                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6264                 break;
6265         }
6266         secondary_exec_controls_set(vmx, sec_exec_control);
6267
6268         vmx_update_msr_bitmap(vcpu);
6269 }
6270
6271 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6272 {
6273         struct page *page;
6274
6275         /* Defer reload until vmcs01 is the current VMCS. */
6276         if (is_guest_mode(vcpu)) {
6277                 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6278                 return;
6279         }
6280
6281         if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6282             SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6283                 return;
6284
6285         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6286         if (is_error_page(page))
6287                 return;
6288
6289         vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6290         vmx_flush_tlb_current(vcpu);
6291
6292         /*
6293          * Do not pin apic access page in memory, the MMU notifier
6294          * will call us again if it is migrated or swapped out.
6295          */
6296         put_page(page);
6297 }
6298
6299 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6300 {
6301         u16 status;
6302         u8 old;
6303
6304         if (max_isr == -1)
6305                 max_isr = 0;
6306
6307         status = vmcs_read16(GUEST_INTR_STATUS);
6308         old = status >> 8;
6309         if (max_isr != old) {
6310                 status &= 0xff;
6311                 status |= max_isr << 8;
6312                 vmcs_write16(GUEST_INTR_STATUS, status);
6313         }
6314 }
6315
6316 static void vmx_set_rvi(int vector)
6317 {
6318         u16 status;
6319         u8 old;
6320
6321         if (vector == -1)
6322                 vector = 0;
6323
6324         status = vmcs_read16(GUEST_INTR_STATUS);
6325         old = (u8)status & 0xff;
6326         if ((u8)vector != old) {
6327                 status &= ~0xff;
6328                 status |= (u8)vector;
6329                 vmcs_write16(GUEST_INTR_STATUS, status);
6330         }
6331 }
6332
6333 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6334 {
6335         /*
6336          * When running L2, updating RVI is only relevant when
6337          * vmcs12 virtual-interrupt-delivery enabled.
6338          * However, it can be enabled only when L1 also
6339          * intercepts external-interrupts and in that case
6340          * we should not update vmcs02 RVI but instead intercept
6341          * interrupt. Therefore, do nothing when running L2.
6342          */
6343         if (!is_guest_mode(vcpu))
6344                 vmx_set_rvi(max_irr);
6345 }
6346
6347 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6348 {
6349         struct vcpu_vmx *vmx = to_vmx(vcpu);
6350         int max_irr;
6351         bool max_irr_updated;
6352
6353         WARN_ON(!vcpu->arch.apicv_active);
6354         if (pi_test_on(&vmx->pi_desc)) {
6355                 pi_clear_on(&vmx->pi_desc);
6356                 /*
6357                  * IOMMU can write to PID.ON, so the barrier matters even on UP.
6358                  * But on x86 this is just a compiler barrier anyway.
6359                  */
6360                 smp_mb__after_atomic();
6361                 max_irr_updated =
6362                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6363
6364                 /*
6365                  * If we are running L2 and L1 has a new pending interrupt
6366                  * which can be injected, we should re-evaluate
6367                  * what should be done with this new L1 interrupt.
6368                  * If L1 intercepts external-interrupts, we should
6369                  * exit from L2 to L1. Otherwise, interrupt should be
6370                  * delivered directly to L2.
6371                  */
6372                 if (is_guest_mode(vcpu) && max_irr_updated) {
6373                         if (nested_exit_on_intr(vcpu))
6374                                 kvm_vcpu_exiting_guest_mode(vcpu);
6375                         else
6376                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6377                 }
6378         } else {
6379                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6380         }
6381         vmx_hwapic_irr_update(vcpu, max_irr);
6382         return max_irr;
6383 }
6384
6385 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6386 {
6387         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6388
6389         return pi_test_on(pi_desc) ||
6390                 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc));
6391 }
6392
6393 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6394 {
6395         if (!kvm_vcpu_apicv_active(vcpu))
6396                 return;
6397
6398         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6399         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6400         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6401         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6402 }
6403
6404 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6405 {
6406         struct vcpu_vmx *vmx = to_vmx(vcpu);
6407
6408         pi_clear_on(&vmx->pi_desc);
6409         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6410 }
6411
6412 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6413 {
6414         u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6415
6416         /* if exit due to PF check for async PF */
6417         if (is_page_fault(intr_info)) {
6418                 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6419         /* Handle machine checks before interrupts are enabled */
6420         } else if (is_machine_check(intr_info)) {
6421                 kvm_machine_check();
6422         /* We need to handle NMIs before interrupts are enabled */
6423         } else if (is_nmi(intr_info)) {
6424                 kvm_before_interrupt(&vmx->vcpu);
6425                 asm("int $2");
6426                 kvm_after_interrupt(&vmx->vcpu);
6427         }
6428 }
6429
6430 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6431 {
6432         unsigned int vector;
6433         unsigned long entry;
6434 #ifdef CONFIG_X86_64
6435         unsigned long tmp;
6436 #endif
6437         gate_desc *desc;
6438         u32 intr_info = vmx_get_intr_info(vcpu);
6439
6440         if (WARN_ONCE(!is_external_intr(intr_info),
6441             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6442                 return;
6443
6444         vector = intr_info & INTR_INFO_VECTOR_MASK;
6445         desc = (gate_desc *)host_idt_base + vector;
6446         entry = gate_offset(desc);
6447
6448         kvm_before_interrupt(vcpu);
6449
6450         asm volatile(
6451 #ifdef CONFIG_X86_64
6452                 "mov %%rsp, %[sp]\n\t"
6453                 "and $-16, %%rsp\n\t"
6454                 "push %[ss]\n\t"
6455                 "push %[sp]\n\t"
6456 #endif
6457                 "pushf\n\t"
6458                 "push %[cs]\n\t"
6459                 CALL_NOSPEC
6460                 :
6461 #ifdef CONFIG_X86_64
6462                 [sp]"=&r"(tmp),
6463 #endif
6464                 ASM_CALL_CONSTRAINT
6465                 :
6466                 [thunk_target]"r"(entry),
6467 #ifdef CONFIG_X86_64
6468                 [ss]"i"(__KERNEL_DS),
6469 #endif
6470                 [cs]"i"(__KERNEL_CS)
6471         );
6472
6473         kvm_after_interrupt(vcpu);
6474 }
6475 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6476
6477 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6478 {
6479         struct vcpu_vmx *vmx = to_vmx(vcpu);
6480
6481         if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6482                 handle_external_interrupt_irqoff(vcpu);
6483         else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6484                 handle_exception_nmi_irqoff(vmx);
6485 }
6486
6487 static bool vmx_has_emulated_msr(u32 index)
6488 {
6489         switch (index) {
6490         case MSR_IA32_SMBASE:
6491                 /*
6492                  * We cannot do SMM unless we can run the guest in big
6493                  * real mode.
6494                  */
6495                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6496         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6497                 return nested;
6498         case MSR_AMD64_VIRT_SPEC_CTRL:
6499                 /* This is AMD only.  */
6500                 return false;
6501         default:
6502                 return true;
6503         }
6504 }
6505
6506 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6507 {
6508         u32 exit_intr_info;
6509         bool unblock_nmi;
6510         u8 vector;
6511         bool idtv_info_valid;
6512
6513         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6514
6515         if (enable_vnmi) {
6516                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6517                         return;
6518
6519                 exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6520                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6521                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6522                 /*
6523                  * SDM 3: 27.7.1.2 (September 2008)
6524                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6525                  * a guest IRET fault.
6526                  * SDM 3: 23.2.2 (September 2008)
6527                  * Bit 12 is undefined in any of the following cases:
6528                  *  If the VM exit sets the valid bit in the IDT-vectoring
6529                  *   information field.
6530                  *  If the VM exit is due to a double fault.
6531                  */
6532                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6533                     vector != DF_VECTOR && !idtv_info_valid)
6534                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6535                                       GUEST_INTR_STATE_NMI);
6536                 else
6537                         vmx->loaded_vmcs->nmi_known_unmasked =
6538                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6539                                   & GUEST_INTR_STATE_NMI);
6540         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6541                 vmx->loaded_vmcs->vnmi_blocked_time +=
6542                         ktime_to_ns(ktime_sub(ktime_get(),
6543                                               vmx->loaded_vmcs->entry_time));
6544 }
6545
6546 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6547                                       u32 idt_vectoring_info,
6548                                       int instr_len_field,
6549                                       int error_code_field)
6550 {
6551         u8 vector;
6552         int type;
6553         bool idtv_info_valid;
6554
6555         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6556
6557         vcpu->arch.nmi_injected = false;
6558         kvm_clear_exception_queue(vcpu);
6559         kvm_clear_interrupt_queue(vcpu);
6560
6561         if (!idtv_info_valid)
6562                 return;
6563
6564         kvm_make_request(KVM_REQ_EVENT, vcpu);
6565
6566         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6567         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6568
6569         switch (type) {
6570         case INTR_TYPE_NMI_INTR:
6571                 vcpu->arch.nmi_injected = true;
6572                 /*
6573                  * SDM 3: 27.7.1.2 (September 2008)
6574                  * Clear bit "block by NMI" before VM entry if a NMI
6575                  * delivery faulted.
6576                  */
6577                 vmx_set_nmi_mask(vcpu, false);
6578                 break;
6579         case INTR_TYPE_SOFT_EXCEPTION:
6580                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6581                 fallthrough;
6582         case INTR_TYPE_HARD_EXCEPTION:
6583                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6584                         u32 err = vmcs_read32(error_code_field);
6585                         kvm_requeue_exception_e(vcpu, vector, err);
6586                 } else
6587                         kvm_requeue_exception(vcpu, vector);
6588                 break;
6589         case INTR_TYPE_SOFT_INTR:
6590                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6591                 fallthrough;
6592         case INTR_TYPE_EXT_INTR:
6593                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6594                 break;
6595         default:
6596                 break;
6597         }
6598 }
6599
6600 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6601 {
6602         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6603                                   VM_EXIT_INSTRUCTION_LEN,
6604                                   IDT_VECTORING_ERROR_CODE);
6605 }
6606
6607 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6608 {
6609         __vmx_complete_interrupts(vcpu,
6610                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6611                                   VM_ENTRY_INSTRUCTION_LEN,
6612                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6613
6614         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6615 }
6616
6617 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6618 {
6619         int i, nr_msrs;
6620         struct perf_guest_switch_msr *msrs;
6621
6622         msrs = perf_guest_get_msrs(&nr_msrs);
6623
6624         if (!msrs)
6625                 return;
6626
6627         for (i = 0; i < nr_msrs; i++)
6628                 if (msrs[i].host == msrs[i].guest)
6629                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6630                 else
6631                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6632                                         msrs[i].host, false);
6633 }
6634
6635 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6636 {
6637         struct vcpu_vmx *vmx = to_vmx(vcpu);
6638         u64 tscl;
6639         u32 delta_tsc;
6640
6641         if (vmx->req_immediate_exit) {
6642                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6643                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6644         } else if (vmx->hv_deadline_tsc != -1) {
6645                 tscl = rdtsc();
6646                 if (vmx->hv_deadline_tsc > tscl)
6647                         /* set_hv_timer ensures the delta fits in 32-bits */
6648                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6649                                 cpu_preemption_timer_multi);
6650                 else
6651                         delta_tsc = 0;
6652
6653                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6654                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6655         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6656                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6657                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6658         }
6659 }
6660
6661 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6662 {
6663         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6664                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6665                 vmcs_writel(HOST_RSP, host_rsp);
6666         }
6667 }
6668
6669 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6670 {
6671         switch (to_vmx(vcpu)->exit_reason) {
6672         case EXIT_REASON_MSR_WRITE:
6673                 return handle_fastpath_set_msr_irqoff(vcpu);
6674         case EXIT_REASON_PREEMPTION_TIMER:
6675                 return handle_fastpath_preemption_timer(vcpu);
6676         default:
6677                 return EXIT_FASTPATH_NONE;
6678         }
6679 }
6680
6681 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6682
6683 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6684                                         struct vcpu_vmx *vmx)
6685 {
6686         /*
6687          * VMENTER enables interrupts (host state), but the kernel state is
6688          * interrupts disabled when this is invoked. Also tell RCU about
6689          * it. This is the same logic as for exit_to_user_mode().
6690          *
6691          * This ensures that e.g. latency analysis on the host observes
6692          * guest mode as interrupt enabled.
6693          *
6694          * guest_enter_irqoff() informs context tracking about the
6695          * transition to guest mode and if enabled adjusts RCU state
6696          * accordingly.
6697          */
6698         instrumentation_begin();
6699         trace_hardirqs_on_prepare();
6700         lockdep_hardirqs_on_prepare(CALLER_ADDR0);
6701         instrumentation_end();
6702
6703         guest_enter_irqoff();
6704         lockdep_hardirqs_on(CALLER_ADDR0);
6705
6706         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6707         if (static_branch_unlikely(&vmx_l1d_should_flush))
6708                 vmx_l1d_flush(vcpu);
6709         else if (static_branch_unlikely(&mds_user_clear))
6710                 mds_clear_cpu_buffers();
6711
6712         if (vcpu->arch.cr2 != native_read_cr2())
6713                 native_write_cr2(vcpu->arch.cr2);
6714
6715         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6716                                    vmx->loaded_vmcs->launched);
6717
6718         vcpu->arch.cr2 = native_read_cr2();
6719
6720         /*
6721          * VMEXIT disables interrupts (host state), but tracing and lockdep
6722          * have them in state 'on' as recorded before entering guest mode.
6723          * Same as enter_from_user_mode().
6724          *
6725          * guest_exit_irqoff() restores host context and reinstates RCU if
6726          * enabled and required.
6727          *
6728          * This needs to be done before the below as native_read_msr()
6729          * contains a tracepoint and x86_spec_ctrl_restore_host() calls
6730          * into world and some more.
6731          */
6732         lockdep_hardirqs_off(CALLER_ADDR0);
6733         guest_exit_irqoff();
6734
6735         instrumentation_begin();
6736         trace_hardirqs_off_finish();
6737         instrumentation_end();
6738 }
6739
6740 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6741 {
6742         fastpath_t exit_fastpath;
6743         struct vcpu_vmx *vmx = to_vmx(vcpu);
6744         unsigned long cr3, cr4;
6745
6746 reenter_guest:
6747         /* Record the guest's net vcpu time for enforced NMI injections. */
6748         if (unlikely(!enable_vnmi &&
6749                      vmx->loaded_vmcs->soft_vnmi_blocked))
6750                 vmx->loaded_vmcs->entry_time = ktime_get();
6751
6752         /* Don't enter VMX if guest state is invalid, let the exit handler
6753            start emulation until we arrive back to a valid state */
6754         if (vmx->emulation_required)
6755                 return EXIT_FASTPATH_NONE;
6756
6757         if (vmx->ple_window_dirty) {
6758                 vmx->ple_window_dirty = false;
6759                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6760         }
6761
6762         /*
6763          * We did this in prepare_switch_to_guest, because it needs to
6764          * be within srcu_read_lock.
6765          */
6766         WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6767
6768         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6769                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6770         if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6771                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6772
6773         cr3 = __get_current_cr3_fast();
6774         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6775                 vmcs_writel(HOST_CR3, cr3);
6776                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6777         }
6778
6779         cr4 = cr4_read_shadow();
6780         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6781                 vmcs_writel(HOST_CR4, cr4);
6782                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6783         }
6784
6785         /* When single-stepping over STI and MOV SS, we must clear the
6786          * corresponding interruptibility bits in the guest state. Otherwise
6787          * vmentry fails as it then expects bit 14 (BS) in pending debug
6788          * exceptions being set, but that's not correct for the guest debugging
6789          * case. */
6790         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6791                 vmx_set_interrupt_shadow(vcpu, 0);
6792
6793         kvm_load_guest_xsave_state(vcpu);
6794
6795         pt_guest_enter(vmx);
6796
6797         atomic_switch_perf_msrs(vmx);
6798
6799         if (enable_preemption_timer)
6800                 vmx_update_hv_timer(vcpu);
6801
6802         if (lapic_in_kernel(vcpu) &&
6803                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6804                 kvm_wait_lapic_expire(vcpu);
6805
6806         /*
6807          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6808          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6809          * is no need to worry about the conditional branch over the wrmsr
6810          * being speculatively taken.
6811          */
6812         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6813
6814         /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6815         vmx_vcpu_enter_exit(vcpu, vmx);
6816
6817         /*
6818          * We do not use IBRS in the kernel. If this vCPU has used the
6819          * SPEC_CTRL MSR it may have left it on; save the value and
6820          * turn it off. This is much more efficient than blindly adding
6821          * it to the atomic save/restore list. Especially as the former
6822          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6823          *
6824          * For non-nested case:
6825          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6826          * save it.
6827          *
6828          * For nested case:
6829          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6830          * save it.
6831          */
6832         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6833                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6834
6835         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6836
6837         /* All fields are clean at this point */
6838         if (static_branch_unlikely(&enable_evmcs))
6839                 current_evmcs->hv_clean_fields |=
6840                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6841
6842         if (static_branch_unlikely(&enable_evmcs))
6843                 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6844
6845         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6846         if (vmx->host_debugctlmsr)
6847                 update_debugctlmsr(vmx->host_debugctlmsr);
6848
6849 #ifndef CONFIG_X86_64
6850         /*
6851          * The sysexit path does not restore ds/es, so we must set them to
6852          * a reasonable value ourselves.
6853          *
6854          * We can't defer this to vmx_prepare_switch_to_host() since that
6855          * function may be executed in interrupt context, which saves and
6856          * restore segments around it, nullifying its effect.
6857          */
6858         loadsegment(ds, __USER_DS);
6859         loadsegment(es, __USER_DS);
6860 #endif
6861
6862         vmx_register_cache_reset(vcpu);
6863
6864         pt_guest_exit(vmx);
6865
6866         kvm_load_host_xsave_state(vcpu);
6867
6868         vmx->nested.nested_run_pending = 0;
6869         vmx->idt_vectoring_info = 0;
6870
6871         if (unlikely(vmx->fail)) {
6872                 vmx->exit_reason = 0xdead;
6873                 return EXIT_FASTPATH_NONE;
6874         }
6875
6876         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6877         if (unlikely((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY))
6878                 kvm_machine_check();
6879
6880         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6881
6882         if (unlikely(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6883                 return EXIT_FASTPATH_NONE;
6884
6885         vmx->loaded_vmcs->launched = 1;
6886         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6887
6888         vmx_recover_nmi_blocking(vmx);
6889         vmx_complete_interrupts(vmx);
6890
6891         if (is_guest_mode(vcpu))
6892                 return EXIT_FASTPATH_NONE;
6893
6894         exit_fastpath = vmx_exit_handlers_fastpath(vcpu);
6895         if (exit_fastpath == EXIT_FASTPATH_REENTER_GUEST) {
6896                 if (!kvm_vcpu_exit_request(vcpu)) {
6897                         /*
6898                          * FIXME: this goto should be a loop in vcpu_enter_guest,
6899                          * but it would incur the cost of a retpoline for now.
6900                          * Revisit once static calls are available.
6901                          */
6902                         if (vcpu->arch.apicv_active)
6903                                 vmx_sync_pir_to_irr(vcpu);
6904                         goto reenter_guest;
6905                 }
6906                 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
6907         }
6908
6909         return exit_fastpath;
6910 }
6911
6912 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6913 {
6914         struct vcpu_vmx *vmx = to_vmx(vcpu);
6915
6916         if (enable_pml)
6917                 vmx_destroy_pml_buffer(vmx);
6918         free_vpid(vmx->vpid);
6919         nested_vmx_free_vcpu(vcpu);
6920         free_loaded_vmcs(vmx->loaded_vmcs);
6921 }
6922
6923 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6924 {
6925         struct vcpu_vmx *vmx;
6926         unsigned long *msr_bitmap;
6927         int i, cpu, err;
6928
6929         BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6930         vmx = to_vmx(vcpu);
6931
6932         err = -ENOMEM;
6933
6934         vmx->vpid = allocate_vpid();
6935
6936         /*
6937          * If PML is turned on, failure on enabling PML just results in failure
6938          * of creating the vcpu, therefore we can simplify PML logic (by
6939          * avoiding dealing with cases, such as enabling PML partially on vcpus
6940          * for the guest), etc.
6941          */
6942         if (enable_pml) {
6943                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6944                 if (!vmx->pml_pg)
6945                         goto free_vpid;
6946         }
6947
6948         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS);
6949
6950         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6951                 u32 index = vmx_msr_index[i];
6952                 u32 data_low, data_high;
6953                 int j = vmx->nmsrs;
6954
6955                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6956                         continue;
6957                 if (wrmsr_safe(index, data_low, data_high) < 0)
6958                         continue;
6959
6960                 vmx->guest_msrs[j].index = i;
6961                 vmx->guest_msrs[j].data = 0;
6962                 switch (index) {
6963                 case MSR_IA32_TSX_CTRL:
6964                         /*
6965                          * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6966                          * let's avoid changing CPUID bits under the host
6967                          * kernel's feet.
6968                          */
6969                         vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6970                         break;
6971                 default:
6972                         vmx->guest_msrs[j].mask = -1ull;
6973                         break;
6974                 }
6975                 ++vmx->nmsrs;
6976         }
6977
6978         err = alloc_loaded_vmcs(&vmx->vmcs01);
6979         if (err < 0)
6980                 goto free_pml;
6981
6982         msr_bitmap = vmx->vmcs01.msr_bitmap;
6983         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6984         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6985         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6986         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6987         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6988         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6989         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6990         if (kvm_cstate_in_guest(vcpu->kvm)) {
6991                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6992                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6993                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6994                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6995         }
6996         vmx->msr_bitmap_mode = 0;
6997
6998         vmx->loaded_vmcs = &vmx->vmcs01;
6999         cpu = get_cpu();
7000         vmx_vcpu_load(vcpu, cpu);
7001         vcpu->cpu = cpu;
7002         init_vmcs(vmx);
7003         vmx_vcpu_put(vcpu);
7004         put_cpu();
7005         if (cpu_need_virtualize_apic_accesses(vcpu)) {
7006                 err = alloc_apic_access_page(vcpu->kvm);
7007                 if (err)
7008                         goto free_vmcs;
7009         }
7010
7011         if (enable_ept && !enable_unrestricted_guest) {
7012                 err = init_rmode_identity_map(vcpu->kvm);
7013                 if (err)
7014                         goto free_vmcs;
7015         }
7016
7017         if (nested)
7018                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
7019                                            vmx_capability.ept);
7020         else
7021                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
7022
7023         vmx->nested.posted_intr_nv = -1;
7024         vmx->nested.current_vmptr = -1ull;
7025
7026         vcpu->arch.microcode_version = 0x100000000ULL;
7027         vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
7028
7029         /*
7030          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
7031          * or POSTED_INTR_WAKEUP_VECTOR.
7032          */
7033         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
7034         vmx->pi_desc.sn = 1;
7035
7036         vmx->ept_pointer = INVALID_PAGE;
7037
7038         return 0;
7039
7040 free_vmcs:
7041         free_loaded_vmcs(vmx->loaded_vmcs);
7042 free_pml:
7043         vmx_destroy_pml_buffer(vmx);
7044 free_vpid:
7045         free_vpid(vmx->vpid);
7046         return err;
7047 }
7048
7049 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
7050 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
7051
7052 static int vmx_vm_init(struct kvm *kvm)
7053 {
7054         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
7055
7056         if (!ple_gap)
7057                 kvm->arch.pause_in_guest = true;
7058
7059         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
7060                 switch (l1tf_mitigation) {
7061                 case L1TF_MITIGATION_OFF:
7062                 case L1TF_MITIGATION_FLUSH_NOWARN:
7063                         /* 'I explicitly don't care' is set */
7064                         break;
7065                 case L1TF_MITIGATION_FLUSH:
7066                 case L1TF_MITIGATION_FLUSH_NOSMT:
7067                 case L1TF_MITIGATION_FULL:
7068                         /*
7069                          * Warn upon starting the first VM in a potentially
7070                          * insecure environment.
7071                          */
7072                         if (sched_smt_active())
7073                                 pr_warn_once(L1TF_MSG_SMT);
7074                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
7075                                 pr_warn_once(L1TF_MSG_L1D);
7076                         break;
7077                 case L1TF_MITIGATION_FULL_FORCE:
7078                         /* Flush is enforced */
7079                         break;
7080                 }
7081         }
7082         kvm_apicv_init(kvm, enable_apicv);
7083         return 0;
7084 }
7085
7086 static int __init vmx_check_processor_compat(void)
7087 {
7088         struct vmcs_config vmcs_conf;
7089         struct vmx_capability vmx_cap;
7090
7091         if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
7092             !this_cpu_has(X86_FEATURE_VMX)) {
7093                 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
7094                 return -EIO;
7095         }
7096
7097         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
7098                 return -EIO;
7099         if (nested)
7100                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
7101         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7102                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7103                                 smp_processor_id());
7104                 return -EIO;
7105         }
7106         return 0;
7107 }
7108
7109 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7110 {
7111         u8 cache;
7112         u64 ipat = 0;
7113
7114         /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
7115          * memory aliases with conflicting memory types and sometimes MCEs.
7116          * We have to be careful as to what are honored and when.
7117          *
7118          * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
7119          * UC.  The effective memory type is UC or WC depending on guest PAT.
7120          * This was historically the source of MCEs and we want to be
7121          * conservative.
7122          *
7123          * When there is no need to deal with noncoherent DMA (e.g., no VT-d
7124          * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
7125          * EPT memory type is set to WB.  The effective memory type is forced
7126          * WB.
7127          *
7128          * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
7129          * EPT memory type is used to emulate guest CD/MTRR.
7130          */
7131
7132         if (is_mmio) {
7133                 cache = MTRR_TYPE_UNCACHABLE;
7134                 goto exit;
7135         }
7136
7137         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
7138                 ipat = VMX_EPT_IPAT_BIT;
7139                 cache = MTRR_TYPE_WRBACK;
7140                 goto exit;
7141         }
7142
7143         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
7144                 ipat = VMX_EPT_IPAT_BIT;
7145                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
7146                         cache = MTRR_TYPE_WRBACK;
7147                 else
7148                         cache = MTRR_TYPE_UNCACHABLE;
7149                 goto exit;
7150         }
7151
7152         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
7153
7154 exit:
7155         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
7156 }
7157
7158 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
7159 {
7160         /*
7161          * These bits in the secondary execution controls field
7162          * are dynamic, the others are mostly based on the hypervisor
7163          * architecture and the guest's CPUID.  Do not touch the
7164          * dynamic bits.
7165          */
7166         u32 mask =
7167                 SECONDARY_EXEC_SHADOW_VMCS |
7168                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7169                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7170                 SECONDARY_EXEC_DESC;
7171
7172         u32 new_ctl = vmx->secondary_exec_control;
7173         u32 cur_ctl = secondary_exec_controls_get(vmx);
7174
7175         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7176 }
7177
7178 /*
7179  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7180  * (indicating "allowed-1") if they are supported in the guest's CPUID.
7181  */
7182 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7183 {
7184         struct vcpu_vmx *vmx = to_vmx(vcpu);
7185         struct kvm_cpuid_entry2 *entry;
7186
7187         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7188         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7189
7190 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
7191         if (entry && (entry->_reg & (_cpuid_mask)))                     \
7192                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
7193 } while (0)
7194
7195         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7196         cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
7197         cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
7198         cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
7199         cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
7200         cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
7201         cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
7202         cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
7203         cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
7204         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
7205         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7206         cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
7207         cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
7208         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
7209         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
7210
7211         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7212         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
7213         cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
7214         cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
7215         cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
7216         cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
7217         cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
7218
7219 #undef cr4_fixed1_update
7220 }
7221
7222 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7223 {
7224         struct vcpu_vmx *vmx = to_vmx(vcpu);
7225
7226         if (kvm_mpx_supported()) {
7227                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7228
7229                 if (mpx_enabled) {
7230                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7231                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7232                 } else {
7233                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7234                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7235                 }
7236         }
7237 }
7238
7239 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7240 {
7241         struct vcpu_vmx *vmx = to_vmx(vcpu);
7242         struct kvm_cpuid_entry2 *best = NULL;
7243         int i;
7244
7245         for (i = 0; i < PT_CPUID_LEAVES; i++) {
7246                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7247                 if (!best)
7248                         return;
7249                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7250                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7251                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7252                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7253         }
7254
7255         /* Get the number of configurable Address Ranges for filtering */
7256         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7257                                                 PT_CAP_num_address_ranges);
7258
7259         /* Initialize and clear the no dependency bits */
7260         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7261                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7262
7263         /*
7264          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7265          * will inject an #GP
7266          */
7267         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7268                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7269
7270         /*
7271          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7272          * PSBFreq can be set
7273          */
7274         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7275                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7276                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7277
7278         /*
7279          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7280          * MTCFreq can be set
7281          */
7282         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7283                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7284                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7285
7286         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7287         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7288                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7289                                                         RTIT_CTL_PTW_EN);
7290
7291         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7292         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7293                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7294
7295         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7296         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7297                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7298
7299         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7300         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7301                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7302
7303         /* unmask address range configure area */
7304         for (i = 0; i < vmx->pt_desc.addr_range; i++)
7305                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7306 }
7307
7308 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7309 {
7310         struct vcpu_vmx *vmx = to_vmx(vcpu);
7311
7312         /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7313         vcpu->arch.xsaves_enabled = false;
7314
7315         if (cpu_has_secondary_exec_ctrls()) {
7316                 vmx_compute_secondary_exec_control(vmx);
7317                 vmcs_set_secondary_exec_control(vmx);
7318         }
7319
7320         if (nested_vmx_allowed(vcpu))
7321                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7322                         FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7323                         FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7324         else
7325                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7326                         ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7327                           FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7328
7329         if (nested_vmx_allowed(vcpu)) {
7330                 nested_vmx_cr_fixed1_bits_update(vcpu);
7331                 nested_vmx_entry_exit_ctls_update(vcpu);
7332         }
7333
7334         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7335                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7336                 update_intel_pt_cfg(vcpu);
7337
7338         if (boot_cpu_has(X86_FEATURE_RTM)) {
7339                 struct shared_msr_entry *msr;
7340                 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL);
7341                 if (msr) {
7342                         bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7343                         vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7344                 }
7345         }
7346 }
7347
7348 static __init void vmx_set_cpu_caps(void)
7349 {
7350         kvm_set_cpu_caps();
7351
7352         /* CPUID 0x1 */
7353         if (nested)
7354                 kvm_cpu_cap_set(X86_FEATURE_VMX);
7355
7356         /* CPUID 0x7 */
7357         if (kvm_mpx_supported())
7358                 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7359         if (cpu_has_vmx_invpcid())
7360                 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
7361         if (vmx_pt_mode_is_host_guest())
7362                 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7363
7364         if (vmx_umip_emulated())
7365                 kvm_cpu_cap_set(X86_FEATURE_UMIP);
7366
7367         /* CPUID 0xD.1 */
7368         supported_xss = 0;
7369         if (!vmx_xsaves_supported())
7370                 kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7371
7372         /* CPUID 0x80000001 */
7373         if (!cpu_has_vmx_rdtscp())
7374                 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7375
7376         if (vmx_waitpkg_supported())
7377                 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7378 }
7379
7380 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7381 {
7382         to_vmx(vcpu)->req_immediate_exit = true;
7383 }
7384
7385 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7386                                   struct x86_instruction_info *info)
7387 {
7388         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7389         unsigned short port;
7390         bool intercept;
7391         int size;
7392
7393         if (info->intercept == x86_intercept_in ||
7394             info->intercept == x86_intercept_ins) {
7395                 port = info->src_val;
7396                 size = info->dst_bytes;
7397         } else {
7398                 port = info->dst_val;
7399                 size = info->src_bytes;
7400         }
7401
7402         /*
7403          * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7404          * VM-exits depend on the 'unconditional IO exiting' VM-execution
7405          * control.
7406          *
7407          * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7408          */
7409         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7410                 intercept = nested_cpu_has(vmcs12,
7411                                            CPU_BASED_UNCOND_IO_EXITING);
7412         else
7413                 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7414
7415         /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7416         return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7417 }
7418
7419 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7420                                struct x86_instruction_info *info,
7421                                enum x86_intercept_stage stage,
7422                                struct x86_exception *exception)
7423 {
7424         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7425
7426         switch (info->intercept) {
7427         /*
7428          * RDPID causes #UD if disabled through secondary execution controls.
7429          * Because it is marked as EmulateOnUD, we need to intercept it here.
7430          */
7431         case x86_intercept_rdtscp:
7432                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7433                         exception->vector = UD_VECTOR;
7434                         exception->error_code_valid = false;
7435                         return X86EMUL_PROPAGATE_FAULT;
7436                 }
7437                 break;
7438
7439         case x86_intercept_in:
7440         case x86_intercept_ins:
7441         case x86_intercept_out:
7442         case x86_intercept_outs:
7443                 return vmx_check_intercept_io(vcpu, info);
7444
7445         case x86_intercept_lgdt:
7446         case x86_intercept_lidt:
7447         case x86_intercept_lldt:
7448         case x86_intercept_ltr:
7449         case x86_intercept_sgdt:
7450         case x86_intercept_sidt:
7451         case x86_intercept_sldt:
7452         case x86_intercept_str:
7453                 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7454                         return X86EMUL_CONTINUE;
7455
7456                 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7457                 break;
7458
7459         /* TODO: check more intercepts... */
7460         default:
7461                 break;
7462         }
7463
7464         return X86EMUL_UNHANDLEABLE;
7465 }
7466
7467 #ifdef CONFIG_X86_64
7468 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7469 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7470                                   u64 divisor, u64 *result)
7471 {
7472         u64 low = a << shift, high = a >> (64 - shift);
7473
7474         /* To avoid the overflow on divq */
7475         if (high >= divisor)
7476                 return 1;
7477
7478         /* Low hold the result, high hold rem which is discarded */
7479         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7480             "rm" (divisor), "0" (low), "1" (high));
7481         *result = low;
7482
7483         return 0;
7484 }
7485
7486 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7487                             bool *expired)
7488 {
7489         struct vcpu_vmx *vmx;
7490         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7491         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7492
7493         vmx = to_vmx(vcpu);
7494         tscl = rdtsc();
7495         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7496         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7497         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7498                                                     ktimer->timer_advance_ns);
7499
7500         if (delta_tsc > lapic_timer_advance_cycles)
7501                 delta_tsc -= lapic_timer_advance_cycles;
7502         else
7503                 delta_tsc = 0;
7504
7505         /* Convert to host delta tsc if tsc scaling is enabled */
7506         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7507             delta_tsc && u64_shl_div_u64(delta_tsc,
7508                                 kvm_tsc_scaling_ratio_frac_bits,
7509                                 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7510                 return -ERANGE;
7511
7512         /*
7513          * If the delta tsc can't fit in the 32 bit after the multi shift,
7514          * we can't use the preemption timer.
7515          * It's possible that it fits on later vmentries, but checking
7516          * on every vmentry is costly so we just use an hrtimer.
7517          */
7518         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7519                 return -ERANGE;
7520
7521         vmx->hv_deadline_tsc = tscl + delta_tsc;
7522         *expired = !delta_tsc;
7523         return 0;
7524 }
7525
7526 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7527 {
7528         to_vmx(vcpu)->hv_deadline_tsc = -1;
7529 }
7530 #endif
7531
7532 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7533 {
7534         if (!kvm_pause_in_guest(vcpu->kvm))
7535                 shrink_ple_window(vcpu);
7536 }
7537
7538 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7539                                      struct kvm_memory_slot *slot)
7540 {
7541         if (!kvm_dirty_log_manual_protect_and_init_set(kvm))
7542                 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7543         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7544 }
7545
7546 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7547                                        struct kvm_memory_slot *slot)
7548 {
7549         kvm_mmu_slot_set_dirty(kvm, slot);
7550 }
7551
7552 static void vmx_flush_log_dirty(struct kvm *kvm)
7553 {
7554         kvm_flush_pml_buffers(kvm);
7555 }
7556
7557 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7558                                            struct kvm_memory_slot *memslot,
7559                                            gfn_t offset, unsigned long mask)
7560 {
7561         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7562 }
7563
7564 static void __pi_post_block(struct kvm_vcpu *vcpu)
7565 {
7566         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7567         struct pi_desc old, new;
7568         unsigned int dest;
7569
7570         do {
7571                 old.control = new.control = pi_desc->control;
7572                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7573                      "Wakeup handler not enabled while the VCPU is blocked\n");
7574
7575                 dest = cpu_physical_id(vcpu->cpu);
7576
7577                 if (x2apic_enabled())
7578                         new.ndst = dest;
7579                 else
7580                         new.ndst = (dest << 8) & 0xFF00;
7581
7582                 /* set 'NV' to 'notification vector' */
7583                 new.nv = POSTED_INTR_VECTOR;
7584         } while (cmpxchg64(&pi_desc->control, old.control,
7585                            new.control) != old.control);
7586
7587         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7588                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7589                 list_del(&vcpu->blocked_vcpu_list);
7590                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7591                 vcpu->pre_pcpu = -1;
7592         }
7593 }
7594
7595 /*
7596  * This routine does the following things for vCPU which is going
7597  * to be blocked if VT-d PI is enabled.
7598  * - Store the vCPU to the wakeup list, so when interrupts happen
7599  *   we can find the right vCPU to wake up.
7600  * - Change the Posted-interrupt descriptor as below:
7601  *      'NDST' <-- vcpu->pre_pcpu
7602  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7603  * - If 'ON' is set during this process, which means at least one
7604  *   interrupt is posted for this vCPU, we cannot block it, in
7605  *   this case, return 1, otherwise, return 0.
7606  *
7607  */
7608 static int pi_pre_block(struct kvm_vcpu *vcpu)
7609 {
7610         unsigned int dest;
7611         struct pi_desc old, new;
7612         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7613
7614         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7615                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
7616                 !kvm_vcpu_apicv_active(vcpu))
7617                 return 0;
7618
7619         WARN_ON(irqs_disabled());
7620         local_irq_disable();
7621         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7622                 vcpu->pre_pcpu = vcpu->cpu;
7623                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7624                 list_add_tail(&vcpu->blocked_vcpu_list,
7625                               &per_cpu(blocked_vcpu_on_cpu,
7626                                        vcpu->pre_pcpu));
7627                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7628         }
7629
7630         do {
7631                 old.control = new.control = pi_desc->control;
7632
7633                 WARN((pi_desc->sn == 1),
7634                      "Warning: SN field of posted-interrupts "
7635                      "is set before blocking\n");
7636
7637                 /*
7638                  * Since vCPU can be preempted during this process,
7639                  * vcpu->cpu could be different with pre_pcpu, we
7640                  * need to set pre_pcpu as the destination of wakeup
7641                  * notification event, then we can find the right vCPU
7642                  * to wakeup in wakeup handler if interrupts happen
7643                  * when the vCPU is in blocked state.
7644                  */
7645                 dest = cpu_physical_id(vcpu->pre_pcpu);
7646
7647                 if (x2apic_enabled())
7648                         new.ndst = dest;
7649                 else
7650                         new.ndst = (dest << 8) & 0xFF00;
7651
7652                 /* set 'NV' to 'wakeup vector' */
7653                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7654         } while (cmpxchg64(&pi_desc->control, old.control,
7655                            new.control) != old.control);
7656
7657         /* We should not block the vCPU if an interrupt is posted for it.  */
7658         if (pi_test_on(pi_desc) == 1)
7659                 __pi_post_block(vcpu);
7660
7661         local_irq_enable();
7662         return (vcpu->pre_pcpu == -1);
7663 }
7664
7665 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7666 {
7667         if (pi_pre_block(vcpu))
7668                 return 1;
7669
7670         if (kvm_lapic_hv_timer_in_use(vcpu))
7671                 kvm_lapic_switch_to_sw_timer(vcpu);
7672
7673         return 0;
7674 }
7675
7676 static void pi_post_block(struct kvm_vcpu *vcpu)
7677 {
7678         if (vcpu->pre_pcpu == -1)
7679                 return;
7680
7681         WARN_ON(irqs_disabled());
7682         local_irq_disable();
7683         __pi_post_block(vcpu);
7684         local_irq_enable();
7685 }
7686
7687 static void vmx_post_block(struct kvm_vcpu *vcpu)
7688 {
7689         if (kvm_x86_ops.set_hv_timer)
7690                 kvm_lapic_switch_to_hv_timer(vcpu);
7691
7692         pi_post_block(vcpu);
7693 }
7694
7695 /*
7696  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7697  *
7698  * @kvm: kvm
7699  * @host_irq: host irq of the interrupt
7700  * @guest_irq: gsi of the interrupt
7701  * @set: set or unset PI
7702  * returns 0 on success, < 0 on failure
7703  */
7704 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7705                               uint32_t guest_irq, bool set)
7706 {
7707         struct kvm_kernel_irq_routing_entry *e;
7708         struct kvm_irq_routing_table *irq_rt;
7709         struct kvm_lapic_irq irq;
7710         struct kvm_vcpu *vcpu;
7711         struct vcpu_data vcpu_info;
7712         int idx, ret = 0;
7713
7714         if (!kvm_arch_has_assigned_device(kvm) ||
7715                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7716                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7717                 return 0;
7718
7719         idx = srcu_read_lock(&kvm->irq_srcu);
7720         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7721         if (guest_irq >= irq_rt->nr_rt_entries ||
7722             hlist_empty(&irq_rt->map[guest_irq])) {
7723                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7724                              guest_irq, irq_rt->nr_rt_entries);
7725                 goto out;
7726         }
7727
7728         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7729                 if (e->type != KVM_IRQ_ROUTING_MSI)
7730                         continue;
7731                 /*
7732                  * VT-d PI cannot support posting multicast/broadcast
7733                  * interrupts to a vCPU, we still use interrupt remapping
7734                  * for these kind of interrupts.
7735                  *
7736                  * For lowest-priority interrupts, we only support
7737                  * those with single CPU as the destination, e.g. user
7738                  * configures the interrupts via /proc/irq or uses
7739                  * irqbalance to make the interrupts single-CPU.
7740                  *
7741                  * We will support full lowest-priority interrupt later.
7742                  *
7743                  * In addition, we can only inject generic interrupts using
7744                  * the PI mechanism, refuse to route others through it.
7745                  */
7746
7747                 kvm_set_msi_irq(kvm, e, &irq);
7748                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7749                     !kvm_irq_is_postable(&irq)) {
7750                         /*
7751                          * Make sure the IRTE is in remapped mode if
7752                          * we don't handle it in posted mode.
7753                          */
7754                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7755                         if (ret < 0) {
7756                                 printk(KERN_INFO
7757                                    "failed to back to remapped mode, irq: %u\n",
7758                                    host_irq);
7759                                 goto out;
7760                         }
7761
7762                         continue;
7763                 }
7764
7765                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7766                 vcpu_info.vector = irq.vector;
7767
7768                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7769                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7770
7771                 if (set)
7772                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7773                 else
7774                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7775
7776                 if (ret < 0) {
7777                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
7778                                         __func__);
7779                         goto out;
7780                 }
7781         }
7782
7783         ret = 0;
7784 out:
7785         srcu_read_unlock(&kvm->irq_srcu, idx);
7786         return ret;
7787 }
7788
7789 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7790 {
7791         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7792                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7793                         FEAT_CTL_LMCE_ENABLED;
7794         else
7795                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7796                         ~FEAT_CTL_LMCE_ENABLED;
7797 }
7798
7799 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7800 {
7801         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7802         if (to_vmx(vcpu)->nested.nested_run_pending)
7803                 return -EBUSY;
7804         return !is_smm(vcpu);
7805 }
7806
7807 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7808 {
7809         struct vcpu_vmx *vmx = to_vmx(vcpu);
7810
7811         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7812         if (vmx->nested.smm.guest_mode)
7813                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7814
7815         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7816         vmx->nested.vmxon = false;
7817         vmx_clear_hlt(vcpu);
7818         return 0;
7819 }
7820
7821 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7822 {
7823         struct vcpu_vmx *vmx = to_vmx(vcpu);
7824         int ret;
7825
7826         if (vmx->nested.smm.vmxon) {
7827                 vmx->nested.vmxon = true;
7828                 vmx->nested.smm.vmxon = false;
7829         }
7830
7831         if (vmx->nested.smm.guest_mode) {
7832                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7833                 if (ret)
7834                         return ret;
7835
7836                 vmx->nested.smm.guest_mode = false;
7837         }
7838         return 0;
7839 }
7840
7841 static void enable_smi_window(struct kvm_vcpu *vcpu)
7842 {
7843         /* RSM will cause a vmexit anyway.  */
7844 }
7845
7846 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7847 {
7848         return false;
7849 }
7850
7851 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7852 {
7853         return to_vmx(vcpu)->nested.vmxon;
7854 }
7855
7856 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7857 {
7858         if (is_guest_mode(vcpu)) {
7859                 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7860
7861                 if (hrtimer_try_to_cancel(timer) == 1)
7862                         hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7863         }
7864 }
7865
7866 static void hardware_unsetup(void)
7867 {
7868         if (nested)
7869                 nested_vmx_hardware_unsetup();
7870
7871         free_kvm_area();
7872 }
7873
7874 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7875 {
7876         ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7877                           BIT(APICV_INHIBIT_REASON_HYPERV);
7878
7879         return supported & BIT(bit);
7880 }
7881
7882 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7883         .hardware_unsetup = hardware_unsetup,
7884
7885         .hardware_enable = hardware_enable,
7886         .hardware_disable = hardware_disable,
7887         .cpu_has_accelerated_tpr = report_flexpriority,
7888         .has_emulated_msr = vmx_has_emulated_msr,
7889
7890         .vm_size = sizeof(struct kvm_vmx),
7891         .vm_init = vmx_vm_init,
7892
7893         .vcpu_create = vmx_create_vcpu,
7894         .vcpu_free = vmx_free_vcpu,
7895         .vcpu_reset = vmx_vcpu_reset,
7896
7897         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7898         .vcpu_load = vmx_vcpu_load,
7899         .vcpu_put = vmx_vcpu_put,
7900
7901         .update_exception_bitmap = update_exception_bitmap,
7902         .get_msr_feature = vmx_get_msr_feature,
7903         .get_msr = vmx_get_msr,
7904         .set_msr = vmx_set_msr,
7905         .get_segment_base = vmx_get_segment_base,
7906         .get_segment = vmx_get_segment,
7907         .set_segment = vmx_set_segment,
7908         .get_cpl = vmx_get_cpl,
7909         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7910         .set_cr0 = vmx_set_cr0,
7911         .set_cr4 = vmx_set_cr4,
7912         .set_efer = vmx_set_efer,
7913         .get_idt = vmx_get_idt,
7914         .set_idt = vmx_set_idt,
7915         .get_gdt = vmx_get_gdt,
7916         .set_gdt = vmx_set_gdt,
7917         .set_dr7 = vmx_set_dr7,
7918         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7919         .cache_reg = vmx_cache_reg,
7920         .get_rflags = vmx_get_rflags,
7921         .set_rflags = vmx_set_rflags,
7922
7923         .tlb_flush_all = vmx_flush_tlb_all,
7924         .tlb_flush_current = vmx_flush_tlb_current,
7925         .tlb_flush_gva = vmx_flush_tlb_gva,
7926         .tlb_flush_guest = vmx_flush_tlb_guest,
7927
7928         .run = vmx_vcpu_run,
7929         .handle_exit = vmx_handle_exit,
7930         .skip_emulated_instruction = vmx_skip_emulated_instruction,
7931         .update_emulated_instruction = vmx_update_emulated_instruction,
7932         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7933         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7934         .patch_hypercall = vmx_patch_hypercall,
7935         .set_irq = vmx_inject_irq,
7936         .set_nmi = vmx_inject_nmi,
7937         .queue_exception = vmx_queue_exception,
7938         .cancel_injection = vmx_cancel_injection,
7939         .interrupt_allowed = vmx_interrupt_allowed,
7940         .nmi_allowed = vmx_nmi_allowed,
7941         .get_nmi_mask = vmx_get_nmi_mask,
7942         .set_nmi_mask = vmx_set_nmi_mask,
7943         .enable_nmi_window = enable_nmi_window,
7944         .enable_irq_window = enable_irq_window,
7945         .update_cr8_intercept = update_cr8_intercept,
7946         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7947         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7948         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7949         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7950         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7951         .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7952         .hwapic_irr_update = vmx_hwapic_irr_update,
7953         .hwapic_isr_update = vmx_hwapic_isr_update,
7954         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7955         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7956         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7957         .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7958
7959         .set_tss_addr = vmx_set_tss_addr,
7960         .set_identity_map_addr = vmx_set_identity_map_addr,
7961         .get_mt_mask = vmx_get_mt_mask,
7962
7963         .get_exit_info = vmx_get_exit_info,
7964
7965         .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7966
7967         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7968
7969         .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7970
7971         .load_mmu_pgd = vmx_load_mmu_pgd,
7972
7973         .check_intercept = vmx_check_intercept,
7974         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7975
7976         .request_immediate_exit = vmx_request_immediate_exit,
7977
7978         .sched_in = vmx_sched_in,
7979
7980         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7981         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7982         .flush_log_dirty = vmx_flush_log_dirty,
7983         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7984
7985         .pre_block = vmx_pre_block,
7986         .post_block = vmx_post_block,
7987
7988         .pmu_ops = &intel_pmu_ops,
7989         .nested_ops = &vmx_nested_ops,
7990
7991         .update_pi_irte = vmx_update_pi_irte,
7992
7993 #ifdef CONFIG_X86_64
7994         .set_hv_timer = vmx_set_hv_timer,
7995         .cancel_hv_timer = vmx_cancel_hv_timer,
7996 #endif
7997
7998         .setup_mce = vmx_setup_mce,
7999
8000         .smi_allowed = vmx_smi_allowed,
8001         .pre_enter_smm = vmx_pre_enter_smm,
8002         .pre_leave_smm = vmx_pre_leave_smm,
8003         .enable_smi_window = enable_smi_window,
8004
8005         .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
8006         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
8007         .migrate_timers = vmx_migrate_timers,
8008 };
8009
8010 static __init int hardware_setup(void)
8011 {
8012         unsigned long host_bndcfgs;
8013         struct desc_ptr dt;
8014         int r, i, ept_lpage_level;
8015
8016         store_idt(&dt);
8017         host_idt_base = dt.address;
8018
8019         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
8020                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8021
8022         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
8023                 return -EIO;
8024
8025         if (boot_cpu_has(X86_FEATURE_NX))
8026                 kvm_enable_efer_bits(EFER_NX);
8027
8028         if (boot_cpu_has(X86_FEATURE_MPX)) {
8029                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
8030                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
8031         }
8032
8033         if (!cpu_has_vmx_mpx())
8034                 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
8035                                     XFEATURE_MASK_BNDCSR);
8036
8037         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
8038             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
8039                 enable_vpid = 0;
8040
8041         if (!cpu_has_vmx_ept() ||
8042             !cpu_has_vmx_ept_4levels() ||
8043             !cpu_has_vmx_ept_mt_wb() ||
8044             !cpu_has_vmx_invept_global())
8045                 enable_ept = 0;
8046
8047         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
8048                 enable_ept_ad_bits = 0;
8049
8050         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
8051                 enable_unrestricted_guest = 0;
8052
8053         if (!cpu_has_vmx_flexpriority())
8054                 flexpriority_enabled = 0;
8055
8056         if (!cpu_has_virtual_nmis())
8057                 enable_vnmi = 0;
8058
8059         /*
8060          * set_apic_access_page_addr() is used to reload apic access
8061          * page upon invalidation.  No need to do anything if not
8062          * using the APIC_ACCESS_ADDR VMCS field.
8063          */
8064         if (!flexpriority_enabled)
8065                 vmx_x86_ops.set_apic_access_page_addr = NULL;
8066
8067         if (!cpu_has_vmx_tpr_shadow())
8068                 vmx_x86_ops.update_cr8_intercept = NULL;
8069
8070 #if IS_ENABLED(CONFIG_HYPERV)
8071         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
8072             && enable_ept) {
8073                 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
8074                 vmx_x86_ops.tlb_remote_flush_with_range =
8075                                 hv_remote_flush_tlb_with_range;
8076         }
8077 #endif
8078
8079         if (!cpu_has_vmx_ple()) {
8080                 ple_gap = 0;
8081                 ple_window = 0;
8082                 ple_window_grow = 0;
8083                 ple_window_max = 0;
8084                 ple_window_shrink = 0;
8085         }
8086
8087         if (!cpu_has_vmx_apicv()) {
8088                 enable_apicv = 0;
8089                 vmx_x86_ops.sync_pir_to_irr = NULL;
8090         }
8091
8092         if (cpu_has_vmx_tsc_scaling()) {
8093                 kvm_has_tsc_control = true;
8094                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
8095                 kvm_tsc_scaling_ratio_frac_bits = 48;
8096         }
8097
8098         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8099
8100         if (enable_ept)
8101                 vmx_enable_tdp();
8102
8103         if (!enable_ept)
8104                 ept_lpage_level = 0;
8105         else if (cpu_has_vmx_ept_1g_page())
8106                 ept_lpage_level = PG_LEVEL_1G;
8107         else if (cpu_has_vmx_ept_2m_page())
8108                 ept_lpage_level = PG_LEVEL_2M;
8109         else
8110                 ept_lpage_level = PG_LEVEL_4K;
8111         kvm_configure_mmu(enable_ept, vmx_get_max_tdp_level(), ept_lpage_level);
8112
8113         /*
8114          * Only enable PML when hardware supports PML feature, and both EPT
8115          * and EPT A/D bit features are enabled -- PML depends on them to work.
8116          */
8117         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
8118                 enable_pml = 0;
8119
8120         if (!enable_pml) {
8121                 vmx_x86_ops.slot_enable_log_dirty = NULL;
8122                 vmx_x86_ops.slot_disable_log_dirty = NULL;
8123                 vmx_x86_ops.flush_log_dirty = NULL;
8124                 vmx_x86_ops.enable_log_dirty_pt_masked = NULL;
8125         }
8126
8127         if (!cpu_has_vmx_preemption_timer())
8128                 enable_preemption_timer = false;
8129
8130         if (enable_preemption_timer) {
8131                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
8132                 u64 vmx_msr;
8133
8134                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
8135                 cpu_preemption_timer_multi =
8136                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
8137
8138                 if (tsc_khz)
8139                         use_timer_freq = (u64)tsc_khz * 1000;
8140                 use_timer_freq >>= cpu_preemption_timer_multi;
8141
8142                 /*
8143                  * KVM "disables" the preemption timer by setting it to its max
8144                  * value.  Don't use the timer if it might cause spurious exits
8145                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
8146                  */
8147                 if (use_timer_freq > 0xffffffffu / 10)
8148                         enable_preemption_timer = false;
8149         }
8150
8151         if (!enable_preemption_timer) {
8152                 vmx_x86_ops.set_hv_timer = NULL;
8153                 vmx_x86_ops.cancel_hv_timer = NULL;
8154                 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
8155         }
8156
8157         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
8158
8159         kvm_mce_cap_supported |= MCG_LMCE_P;
8160
8161         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
8162                 return -EINVAL;
8163         if (!enable_ept || !cpu_has_vmx_intel_pt())
8164                 pt_mode = PT_MODE_SYSTEM;
8165
8166         if (nested) {
8167                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
8168                                            vmx_capability.ept);
8169
8170                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
8171                 if (r)
8172                         return r;
8173         }
8174
8175         vmx_set_cpu_caps();
8176
8177         r = alloc_kvm_area();
8178         if (r)
8179                 nested_vmx_hardware_unsetup();
8180         return r;
8181 }
8182
8183 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
8184         .cpu_has_kvm_support = cpu_has_kvm_support,
8185         .disabled_by_bios = vmx_disabled_by_bios,
8186         .check_processor_compatibility = vmx_check_processor_compat,
8187         .hardware_setup = hardware_setup,
8188
8189         .runtime_ops = &vmx_x86_ops,
8190 };
8191
8192 static void vmx_cleanup_l1d_flush(void)
8193 {
8194         if (vmx_l1d_flush_pages) {
8195                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
8196                 vmx_l1d_flush_pages = NULL;
8197         }
8198         /* Restore state so sysfs ignores VMX */
8199         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
8200 }
8201
8202 static void vmx_exit(void)
8203 {
8204 #ifdef CONFIG_KEXEC_CORE
8205         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8206         synchronize_rcu();
8207 #endif
8208
8209         kvm_exit();
8210
8211 #if IS_ENABLED(CONFIG_HYPERV)
8212         if (static_branch_unlikely(&enable_evmcs)) {
8213                 int cpu;
8214                 struct hv_vp_assist_page *vp_ap;
8215                 /*
8216                  * Reset everything to support using non-enlightened VMCS
8217                  * access later (e.g. when we reload the module with
8218                  * enlightened_vmcs=0)
8219                  */
8220                 for_each_online_cpu(cpu) {
8221                         vp_ap = hv_get_vp_assist_page(cpu);
8222
8223                         if (!vp_ap)
8224                                 continue;
8225
8226                         vp_ap->nested_control.features.directhypercall = 0;
8227                         vp_ap->current_nested_vmcs = 0;
8228                         vp_ap->enlighten_vmentry = 0;
8229                 }
8230
8231                 static_branch_disable(&enable_evmcs);
8232         }
8233 #endif
8234         vmx_cleanup_l1d_flush();
8235 }
8236 module_exit(vmx_exit);
8237
8238 static int __init vmx_init(void)
8239 {
8240         int r, cpu;
8241
8242 #if IS_ENABLED(CONFIG_HYPERV)
8243         /*
8244          * Enlightened VMCS usage should be recommended and the host needs
8245          * to support eVMCS v1 or above. We can also disable eVMCS support
8246          * with module parameter.
8247          */
8248         if (enlightened_vmcs &&
8249             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
8250             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
8251             KVM_EVMCS_VERSION) {
8252                 int cpu;
8253
8254                 /* Check that we have assist pages on all online CPUs */
8255                 for_each_online_cpu(cpu) {
8256                         if (!hv_get_vp_assist_page(cpu)) {
8257                                 enlightened_vmcs = false;
8258                                 break;
8259                         }
8260                 }
8261
8262                 if (enlightened_vmcs) {
8263                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8264                         static_branch_enable(&enable_evmcs);
8265                 }
8266
8267                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
8268                         vmx_x86_ops.enable_direct_tlbflush
8269                                 = hv_enable_direct_tlbflush;
8270
8271         } else {
8272                 enlightened_vmcs = false;
8273         }
8274 #endif
8275
8276         r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
8277                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8278         if (r)
8279                 return r;
8280
8281         /*
8282          * Must be called after kvm_init() so enable_ept is properly set
8283          * up. Hand the parameter mitigation value in which was stored in
8284          * the pre module init parser. If no parameter was given, it will
8285          * contain 'auto' which will be turned into the default 'cond'
8286          * mitigation mode.
8287          */
8288         r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
8289         if (r) {
8290                 vmx_exit();
8291                 return r;
8292         }
8293
8294         for_each_possible_cpu(cpu) {
8295                 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8296                 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
8297                 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8298         }
8299
8300 #ifdef CONFIG_KEXEC_CORE
8301         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8302                            crash_vmclear_local_loaded_vmcss);
8303 #endif
8304         vmx_check_vmcs12_offsets();
8305
8306         /*
8307          * Intel processors don't have problems with
8308          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable
8309          * it for VMX by default
8310          */
8311         allow_smaller_maxphyaddr = true;
8312
8313         return 0;
8314 }
8315 module_init(vmx_init);