arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39 #include <linux/frame.h>
  40
  41 #include <asm/apic.h>
  42 #include <asm/perf_event.h>
  43 #include <asm/tlbflush.h>
  44 #include <asm/desc.h>
  45 #include <asm/debugreg.h>
  46 #include <asm/kvm_para.h>
  47 #include <asm/irq_remapping.h>
  48
  49 #include <asm/virtext.h>
  50 #include "trace.h"
  51
  52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  53
  54 MODULE_AUTHOR("Qumranet");
  55 MODULE_LICENSE("GPL");
  56
  57 static const struct x86_cpu_id svm_cpu_id[] = {
  58         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  59         {}
  60 };
  61 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  62
  63 #define IOPM_ALLOC_ORDER 2
  64 #define MSRPM_ALLOC_ORDER 1
  65
  66 #define SEG_TYPE_LDT 2
  67 #define SEG_TYPE_BUSY_TSS16 3
  68
  69 #define SVM_FEATURE_NPT            (1 <<  0)
  70 #define SVM_FEATURE_LBRV           (1 <<  1)
  71 #define SVM_FEATURE_SVML           (1 <<  2)
  72 #define SVM_FEATURE_NRIP           (1 <<  3)
  73 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  74 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  75 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  76 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  77 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  78
  79 #define SVM_AVIC_DOORBELL       0xc001011b
  80
  81 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  82 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  83 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  84
  85 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  86
  87 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  88 #define TSC_RATIO_MIN           0x0000000000000001ULL
  89 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  90
  91 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  92
  93 /*
  94  * 0xff is broadcast, so the max index allowed for physical APIC ID
  95  * table is 0xfe.  APIC IDs above 0xff are reserved.
  96  */
  97 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
  98
  99 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
 100 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 101 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 102
 103 /* AVIC GATAG is encoded using VM and VCPU IDs */
 104 #define AVIC_VCPU_ID_BITS               8
 105 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 106
 107 #define AVIC_VM_ID_BITS                 24
 108 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 109 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 110
 111 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 112                                                 (y & AVIC_VCPU_ID_MASK))
 113 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 114 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 115
 116 static bool erratum_383_found __read_mostly;
 117
 118 static const u32 host_save_user_msrs[] = {
 119 #ifdef CONFIG_X86_64
 120         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 121         MSR_FS_BASE,
 122 #endif
 123         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 124         MSR_TSC_AUX,
 125 };
 126
 127 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 128
 129 struct kvm_vcpu;
 130
 131 struct nested_state {
 132         struct vmcb *hsave;
 133         u64 hsave_msr;
 134         u64 vm_cr_msr;
 135         u64 vmcb;
 136
 137         /* These are the merged vectors */
 138         u32 *msrpm;
 139
 140         /* gpa pointers to the real vectors */
 141         u64 vmcb_msrpm;
 142         u64 vmcb_iopm;
 143
 144         /* A VMEXIT is required but not yet emulated */
 145         bool exit_required;
 146
 147         /* cache for intercepts of the guest */
 148         u32 intercept_cr;
 149         u32 intercept_dr;
 150         u32 intercept_exceptions;
 151         u64 intercept;
 152
 153         /* Nested Paging related state */
 154         u64 nested_cr3;
 155 };
 156
 157 #define MSRPM_OFFSETS   16
 158 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 159
 160 /*
 161  * Set osvw_len to higher value when updated Revision Guides
 162  * are published and we know what the new status bits are
 163  */
 164 static uint64_t osvw_len = 4, osvw_status;
 165
 166 struct vcpu_svm {
 167         struct kvm_vcpu vcpu;
 168         struct vmcb *vmcb;
 169         unsigned long vmcb_pa;
 170         struct svm_cpu_data *svm_data;
 171         uint64_t asid_generation;
 172         uint64_t sysenter_esp;
 173         uint64_t sysenter_eip;
 174         uint64_t tsc_aux;
 175
 176         u64 next_rip;
 177
 178         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 179         struct {
 180                 u16 fs;
 181                 u16 gs;
 182                 u16 ldt;
 183                 u64 gs_base;
 184         } host;
 185
 186         u32 *msrpm;
 187
 188         ulong nmi_iret_rip;
 189
 190         struct nested_state nested;
 191
 192         bool nmi_singlestep;
 193         u64 nmi_singlestep_guest_rflags;
 194
 195         unsigned int3_injected;
 196         unsigned long int3_rip;
 197
 198         /* cached guest cpuid flags for faster access */
 199         bool nrips_enabled      : 1;
 200
 201         u32 ldr_reg;
 202         struct page *avic_backing_page;
 203         u64 *avic_physical_id_cache;
 204         bool avic_is_running;
 205
 206         /*
 207          * Per-vcpu list of struct amd_svm_iommu_ir:
 208          * This is used mainly to store interrupt remapping information used
 209          * when update the vcpu affinity. This avoids the need to scan for
 210          * IRTE and try to match ga_tag in the IOMMU driver.
 211          */
 212         struct list_head ir_list;
 213         spinlock_t ir_list_lock;
 214 };
 215
 216 /*
 217  * This is a wrapper of struct amd_iommu_ir_data.
 218  */
 219 struct amd_svm_iommu_ir {
 220         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 221         void *data;             /* Storing pointer to struct amd_ir_data */
 222 };
 223
 224 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 225 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 226
 227 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 228 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 229 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 230 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 231
 232 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 233 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 234
 235 #define MSR_INVALID                     0xffffffffU
 236
 237 static const struct svm_direct_access_msrs {
 238         u32 index;   /* Index of the MSR */
 239         bool always; /* True if intercept is always on */
 240 } direct_access_msrs[] = {
 241         { .index = MSR_STAR,                            .always = true  },
 242         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 243 #ifdef CONFIG_X86_64
 244         { .index = MSR_GS_BASE,                         .always = true  },
 245         { .index = MSR_FS_BASE,                         .always = true  },
 246         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 247         { .index = MSR_LSTAR,                           .always = true  },
 248         { .index = MSR_CSTAR,                           .always = true  },
 249         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 250 #endif
 251         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 252         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 253         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 254         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 255         { .index = MSR_INVALID,                         .always = false },
 256 };
 257
 258 /* enable NPT for AMD64 and X86 with PAE */
 259 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 260 static bool npt_enabled = true;
 261 #else
 262 static bool npt_enabled;
 263 #endif
 264
 265 /* allow nested paging (virtualized MMU) for all guests */
 266 static int npt = true;
 267 module_param(npt, int, S_IRUGO);
 268
 269 /* allow nested virtualization in KVM/SVM */
 270 static int nested = true;
 271 module_param(nested, int, S_IRUGO);
 272
 273 /* enable / disable AVIC */
 274 static int avic;
 275 #ifdef CONFIG_X86_LOCAL_APIC
 276 module_param(avic, int, S_IRUGO);
 277 #endif
 278
 279 /* enable/disable Virtual VMLOAD VMSAVE */
 280 static int vls = true;
 281 module_param(vls, int, 0444);
 282
 283 /* enable/disable Virtual GIF */
 284 static int vgif = true;
 285 module_param(vgif, int, 0444);
 286
 287 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 288 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 289 static void svm_complete_interrupts(struct vcpu_svm *svm);
 290
 291 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 292 static int nested_svm_intercept(struct vcpu_svm *svm);
 293 static int nested_svm_vmexit(struct vcpu_svm *svm);
 294 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 295                                       bool has_error_code, u32 error_code);
 296
 297 enum {
 298         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 299                             pause filter count */
 300         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 301         VMCB_ASID,       /* ASID */
 302         VMCB_INTR,       /* int_ctl, int_vector */
 303         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 304         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 305         VMCB_DR,         /* DR6, DR7 */
 306         VMCB_DT,         /* GDT, IDT */
 307         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 308         VMCB_CR2,        /* CR2 only */
 309         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 310         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 311                           * AVIC PHYSICAL_TABLE pointer,
 312                           * AVIC LOGICAL_TABLE pointer
 313                           */
 314         VMCB_DIRTY_MAX,
 315 };
 316
 317 /* TPR and CR2 are always written before VMRUN */
 318 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 319
 320 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 321
 322 static inline void mark_all_dirty(struct vmcb *vmcb)
 323 {
 324         vmcb->control.clean = 0;
 325 }
 326
 327 static inline void mark_all_clean(struct vmcb *vmcb)
 328 {
 329         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 330                                & ~VMCB_ALWAYS_DIRTY_MASK;
 331 }
 332
 333 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 334 {
 335         vmcb->control.clean &= ~(1 << bit);
 336 }
 337
 338 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 339 {
 340         return container_of(vcpu, struct vcpu_svm, vcpu);
 341 }
 342
 343 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 344 {
 345         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 346         mark_dirty(svm->vmcb, VMCB_AVIC);
 347 }
 348
 349 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 350 {
 351         struct vcpu_svm *svm = to_svm(vcpu);
 352         u64 *entry = svm->avic_physical_id_cache;
 353
 354         if (!entry)
 355                 return false;
 356
 357         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 358 }
 359
 360 static void recalc_intercepts(struct vcpu_svm *svm)
 361 {
 362         struct vmcb_control_area *c, *h;
 363         struct nested_state *g;
 364
 365         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 366
 367         if (!is_guest_mode(&svm->vcpu))
 368                 return;
 369
 370         c = &svm->vmcb->control;
 371         h = &svm->nested.hsave->control;
 372         g = &svm->nested;
 373
 374         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 375         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 376         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 377         c->intercept = h->intercept | g->intercept;
 378 }
 379
 380 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 381 {
 382         if (is_guest_mode(&svm->vcpu))
 383                 return svm->nested.hsave;
 384         else
 385                 return svm->vmcb;
 386 }
 387
 388 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 389 {
 390         struct vmcb *vmcb = get_host_vmcb(svm);
 391
 392         vmcb->control.intercept_cr |= (1U << bit);
 393
 394         recalc_intercepts(svm);
 395 }
 396
 397 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 398 {
 399         struct vmcb *vmcb = get_host_vmcb(svm);
 400
 401         vmcb->control.intercept_cr &= ~(1U << bit);
 402
 403         recalc_intercepts(svm);
 404 }
 405
 406 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 407 {
 408         struct vmcb *vmcb = get_host_vmcb(svm);
 409
 410         return vmcb->control.intercept_cr & (1U << bit);
 411 }
 412
 413 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 414 {
 415         struct vmcb *vmcb = get_host_vmcb(svm);
 416
 417         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 418                 | (1 << INTERCEPT_DR1_READ)
 419                 | (1 << INTERCEPT_DR2_READ)
 420                 | (1 << INTERCEPT_DR3_READ)
 421                 | (1 << INTERCEPT_DR4_READ)
 422                 | (1 << INTERCEPT_DR5_READ)
 423                 | (1 << INTERCEPT_DR6_READ)
 424                 | (1 << INTERCEPT_DR7_READ)
 425                 | (1 << INTERCEPT_DR0_WRITE)
 426                 | (1 << INTERCEPT_DR1_WRITE)
 427                 | (1 << INTERCEPT_DR2_WRITE)
 428                 | (1 << INTERCEPT_DR3_WRITE)
 429                 | (1 << INTERCEPT_DR4_WRITE)
 430                 | (1 << INTERCEPT_DR5_WRITE)
 431                 | (1 << INTERCEPT_DR6_WRITE)
 432                 | (1 << INTERCEPT_DR7_WRITE);
 433
 434         recalc_intercepts(svm);
 435 }
 436
 437 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 438 {
 439         struct vmcb *vmcb = get_host_vmcb(svm);
 440
 441         vmcb->control.intercept_dr = 0;
 442
 443         recalc_intercepts(svm);
 444 }
 445
 446 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 447 {
 448         struct vmcb *vmcb = get_host_vmcb(svm);
 449
 450         vmcb->control.intercept_exceptions |= (1U << bit);
 451
 452         recalc_intercepts(svm);
 453 }
 454
 455 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 456 {
 457         struct vmcb *vmcb = get_host_vmcb(svm);
 458
 459         vmcb->control.intercept_exceptions &= ~(1U << bit);
 460
 461         recalc_intercepts(svm);
 462 }
 463
 464 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 465 {
 466         struct vmcb *vmcb = get_host_vmcb(svm);
 467
 468         vmcb->control.intercept |= (1ULL << bit);
 469
 470         recalc_intercepts(svm);
 471 }
 472
 473 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 474 {
 475         struct vmcb *vmcb = get_host_vmcb(svm);
 476
 477         vmcb->control.intercept &= ~(1ULL << bit);
 478
 479         recalc_intercepts(svm);
 480 }
 481
 482 static inline bool vgif_enabled(struct vcpu_svm *svm)
 483 {
 484         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 485 }
 486
 487 static inline void enable_gif(struct vcpu_svm *svm)
 488 {
 489         if (vgif_enabled(svm))
 490                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 491         else
 492                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 493 }
 494
 495 static inline void disable_gif(struct vcpu_svm *svm)
 496 {
 497         if (vgif_enabled(svm))
 498                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 499         else
 500                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 501 }
 502
 503 static inline bool gif_set(struct vcpu_svm *svm)
 504 {
 505         if (vgif_enabled(svm))
 506                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 507         else
 508                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 509 }
 510
 511 static unsigned long iopm_base;
 512
 513 struct kvm_ldttss_desc {
 514         u16 limit0;
 515         u16 base0;
 516         unsigned base1:8, type:5, dpl:2, p:1;
 517         unsigned limit1:4, zero0:3, g:1, base2:8;
 518         u32 base3;
 519         u32 zero1;
 520 } __attribute__((packed));
 521
 522 struct svm_cpu_data {
 523         int cpu;
 524
 525         u64 asid_generation;
 526         u32 max_asid;
 527         u32 next_asid;
 528         struct kvm_ldttss_desc *tss_desc;
 529
 530         struct page *save_area;
 531 };
 532
 533 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 534
 535 struct svm_init_data {
 536         int cpu;
 537         int r;
 538 };
 539
 540 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 541
 542 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 543 #define MSRS_RANGE_SIZE 2048
 544 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 545
 546 static u32 svm_msrpm_offset(u32 msr)
 547 {
 548         u32 offset;
 549         int i;
 550
 551         for (i = 0; i < NUM_MSR_MAPS; i++) {
 552                 if (msr < msrpm_ranges[i] ||
 553                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 554                         continue;
 555
 556                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 557                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 558
 559                 /* Now we have the u8 offset - but need the u32 offset */
 560                 return offset / 4;
 561         }
 562
 563         /* MSR not in any range */
 564         return MSR_INVALID;
 565 }
 566
 567 #define MAX_INST_SIZE 15
 568
 569 static inline void clgi(void)
 570 {
 571         asm volatile (__ex(SVM_CLGI));
 572 }
 573
 574 static inline void stgi(void)
 575 {
 576         asm volatile (__ex(SVM_STGI));
 577 }
 578
 579 static inline void invlpga(unsigned long addr, u32 asid)
 580 {
 581         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 582 }
 583
 584 static int get_npt_level(struct kvm_vcpu *vcpu)
 585 {
 586 #ifdef CONFIG_X86_64
 587         return PT64_ROOT_4LEVEL;
 588 #else
 589         return PT32E_ROOT_LEVEL;
 590 #endif
 591 }
 592
 593 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 594 {
 595         vcpu->arch.efer = efer;
 596         if (!npt_enabled && !(efer & EFER_LMA))
 597                 efer &= ~EFER_LME;
 598
 599         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 600         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 601 }
 602
 603 static int is_external_interrupt(u32 info)
 604 {
 605         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 606         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 607 }
 608
 609 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 610 {
 611         struct vcpu_svm *svm = to_svm(vcpu);
 612         u32 ret = 0;
 613
 614         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 615                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 616         return ret;
 617 }
 618
 619 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 620 {
 621         struct vcpu_svm *svm = to_svm(vcpu);
 622
 623         if (mask == 0)
 624                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 625         else
 626                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 627
 628 }
 629
 630 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 631 {
 632         struct vcpu_svm *svm = to_svm(vcpu);
 633
 634         if (svm->vmcb->control.next_rip != 0) {
 635                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 636                 svm->next_rip = svm->vmcb->control.next_rip;
 637         }
 638
 639         if (!svm->next_rip) {
 640                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 641                                 EMULATE_DONE)
 642                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 643                 return;
 644         }
 645         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 646                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 647                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 648
 649         kvm_rip_write(vcpu, svm->next_rip);
 650         svm_set_interrupt_shadow(vcpu, 0);
 651 }
 652
 653 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 654 {
 655         struct vcpu_svm *svm = to_svm(vcpu);
 656         unsigned nr = vcpu->arch.exception.nr;
 657         bool has_error_code = vcpu->arch.exception.has_error_code;
 658         bool reinject = vcpu->arch.exception.injected;
 659         u32 error_code = vcpu->arch.exception.error_code;
 660
 661         /*
 662          * If we are within a nested VM we'd better #VMEXIT and let the guest
 663          * handle the exception
 664          */
 665         if (!reinject &&
 666             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 667                 return;
 668
 669         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 670                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 671
 672                 /*
 673                  * For guest debugging where we have to reinject #BP if some
 674                  * INT3 is guest-owned:
 675                  * Emulate nRIP by moving RIP forward. Will fail if injection
 676                  * raises a fault that is not intercepted. Still better than
 677                  * failing in all cases.
 678                  */
 679                 skip_emulated_instruction(&svm->vcpu);
 680                 rip = kvm_rip_read(&svm->vcpu);
 681                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 682                 svm->int3_injected = rip - old_rip;
 683         }
 684
 685         svm->vmcb->control.event_inj = nr
 686                 | SVM_EVTINJ_VALID
 687                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 688                 | SVM_EVTINJ_TYPE_EXEPT;
 689         svm->vmcb->control.event_inj_err = error_code;
 690 }
 691
 692 static void svm_init_erratum_383(void)
 693 {
 694         u32 low, high;
 695         int err;
 696         u64 val;
 697
 698         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 699                 return;
 700
 701         /* Use _safe variants to not break nested virtualization */
 702         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 703         if (err)
 704                 return;
 705
 706         val |= (1ULL << 47);
 707
 708         low  = lower_32_bits(val);
 709         high = upper_32_bits(val);
 710
 711         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 712
 713         erratum_383_found = true;
 714 }
 715
 716 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 717 {
 718         /*
 719          * Guests should see errata 400 and 415 as fixed (assuming that
 720          * HLT and IO instructions are intercepted).
 721          */
 722         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 723         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 724
 725         /*
 726          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 727          * all osvw.status bits inside that length, including bit 0 (which is
 728          * reserved for erratum 298), are valid. However, if host processor's
 729          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 730          * be conservative here and therefore we tell the guest that erratum 298
 731          * is present (because we really don't know).
 732          */
 733         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 734                 vcpu->arch.osvw.status |= 1;
 735 }
 736
 737 static int has_svm(void)
 738 {
 739         const char *msg;
 740
 741         if (!cpu_has_svm(&msg)) {
 742                 printk(KERN_INFO "has_svm: %s\n", msg);
 743                 return 0;
 744         }
 745
 746         return 1;
 747 }
 748
 749 static void svm_hardware_disable(void)
 750 {
 751         /* Make sure we clean up behind us */
 752         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 753                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 754
 755         cpu_svm_disable();
 756
 757         amd_pmu_disable_virt();
 758 }
 759
 760 static int svm_hardware_enable(void)
 761 {
 762
 763         struct svm_cpu_data *sd;
 764         uint64_t efer;
 765         struct desc_struct *gdt;
 766         int me = raw_smp_processor_id();
 767
 768         rdmsrl(MSR_EFER, efer);
 769         if (efer & EFER_SVME)
 770                 return -EBUSY;
 771
 772         if (!has_svm()) {
 773                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 774                 return -EINVAL;
 775         }
 776         sd = per_cpu(svm_data, me);
 777         if (!sd) {
 778                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 779                 return -EINVAL;
 780         }
 781
 782         sd->asid_generation = 1;
 783         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 784         sd->next_asid = sd->max_asid + 1;
 785
 786         gdt = get_current_gdt_rw();
 787         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 788
 789         wrmsrl(MSR_EFER, efer | EFER_SVME);
 790
 791         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 792
 793         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 794                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 795                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 796         }
 797
 798
 799         /*
 800          * Get OSVW bits.
 801          *
 802          * Note that it is possible to have a system with mixed processor
 803          * revisions and therefore different OSVW bits. If bits are not the same
 804          * on different processors then choose the worst case (i.e. if erratum
 805          * is present on one processor and not on another then assume that the
 806          * erratum is present everywhere).
 807          */
 808         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 809                 uint64_t len, status = 0;
 810                 int err;
 811
 812                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 813                 if (!err)
 814                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 815                                                       &err);
 816
 817                 if (err)
 818                         osvw_status = osvw_len = 0;
 819                 else {
 820                         if (len < osvw_len)
 821                                 osvw_len = len;
 822                         osvw_status |= status;
 823                         osvw_status &= (1ULL << osvw_len) - 1;
 824                 }
 825         } else
 826                 osvw_status = osvw_len = 0;
 827
 828         svm_init_erratum_383();
 829
 830         amd_pmu_enable_virt();
 831
 832         return 0;
 833 }
 834
 835 static void svm_cpu_uninit(int cpu)
 836 {
 837         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 838
 839         if (!sd)
 840                 return;
 841
 842         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 843         __free_page(sd->save_area);
 844         kfree(sd);
 845 }
 846
 847 static int svm_cpu_init(int cpu)
 848 {
 849         struct svm_cpu_data *sd;
 850         int r;
 851
 852         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 853         if (!sd)
 854                 return -ENOMEM;
 855         sd->cpu = cpu;
 856         sd->save_area = alloc_page(GFP_KERNEL);
 857         r = -ENOMEM;
 858         if (!sd->save_area)
 859                 goto err_1;
 860
 861         per_cpu(svm_data, cpu) = sd;
 862
 863         return 0;
 864
 865 err_1:
 866         kfree(sd);
 867         return r;
 868
 869 }
 870
 871 static bool valid_msr_intercept(u32 index)
 872 {
 873         int i;
 874
 875         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 876                 if (direct_access_msrs[i].index == index)
 877                         return true;
 878
 879         return false;
 880 }
 881
 882 static void set_msr_interception(u32 *msrpm, unsigned msr,
 883                                  int read, int write)
 884 {
 885         u8 bit_read, bit_write;
 886         unsigned long tmp;
 887         u32 offset;
 888
 889         /*
 890          * If this warning triggers extend the direct_access_msrs list at the
 891          * beginning of the file
 892          */
 893         WARN_ON(!valid_msr_intercept(msr));
 894
 895         offset    = svm_msrpm_offset(msr);
 896         bit_read  = 2 * (msr & 0x0f);
 897         bit_write = 2 * (msr & 0x0f) + 1;
 898         tmp       = msrpm[offset];
 899
 900         BUG_ON(offset == MSR_INVALID);
 901
 902         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 903         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 904
 905         msrpm[offset] = tmp;
 906 }
 907
 908 static void svm_vcpu_init_msrpm(u32 *msrpm)
 909 {
 910         int i;
 911
 912         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 913
 914         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 915                 if (!direct_access_msrs[i].always)
 916                         continue;
 917
 918                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 919         }
 920 }
 921
 922 static void add_msr_offset(u32 offset)
 923 {
 924         int i;
 925
 926         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 927
 928                 /* Offset already in list? */
 929                 if (msrpm_offsets[i] == offset)
 930                         return;
 931
 932                 /* Slot used by another offset? */
 933                 if (msrpm_offsets[i] != MSR_INVALID)
 934                         continue;
 935
 936                 /* Add offset to list */
 937                 msrpm_offsets[i] = offset;
 938
 939                 return;
 940         }
 941
 942         /*
 943          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 944          * increase MSRPM_OFFSETS in this case.
 945          */
 946         BUG();
 947 }
 948
 949 static void init_msrpm_offsets(void)
 950 {
 951         int i;
 952
 953         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 954
 955         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 956                 u32 offset;
 957
 958                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 959                 BUG_ON(offset == MSR_INVALID);
 960
 961                 add_msr_offset(offset);
 962         }
 963 }
 964
 965 static void svm_enable_lbrv(struct vcpu_svm *svm)
 966 {
 967         u32 *msrpm = svm->msrpm;
 968
 969         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 970         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 971         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 972         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 973         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 974 }
 975
 976 static void svm_disable_lbrv(struct vcpu_svm *svm)
 977 {
 978         u32 *msrpm = svm->msrpm;
 979
 980         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 981         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 982         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 983         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 984         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 985 }
 986
 987 static void disable_nmi_singlestep(struct vcpu_svm *svm)
 988 {
 989         svm->nmi_singlestep = false;
 990
 991         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 992                 /* Clear our flags if they were not set by the guest */
 993                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 994                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 995                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 996                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 997         }
 998 }
 999
1000 /* Note:
1001  * This hash table is used to map VM_ID to a struct kvm_arch,
1002  * when handling AMD IOMMU GALOG notification to schedule in
1003  * a particular vCPU.
1004  */
1005 #define SVM_VM_DATA_HASH_BITS   8
1006 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1007 static u32 next_vm_id = 0;
1008 static bool next_vm_id_wrapped = 0;
1009 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1010
1011 /* Note:
1012  * This function is called from IOMMU driver to notify
1013  * SVM to schedule in a particular vCPU of a particular VM.
1014  */
1015 static int avic_ga_log_notifier(u32 ga_tag)
1016 {
1017         unsigned long flags;
1018         struct kvm_arch *ka = NULL;
1019         struct kvm_vcpu *vcpu = NULL;
1020         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1021         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1022
1023         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1024
1025         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1026         hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
1027                 struct kvm *kvm = container_of(ka, struct kvm, arch);
1028                 struct kvm_arch *vm_data = &kvm->arch;
1029
1030                 if (vm_data->avic_vm_id != vm_id)
1031                         continue;
1032                 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
1033                 break;
1034         }
1035         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1036
1037         /* Note:
1038          * At this point, the IOMMU should have already set the pending
1039          * bit in the vAPIC backing page. So, we just need to schedule
1040          * in the vcpu.
1041          */
1042         if (vcpu)
1043                 kvm_vcpu_wake_up(vcpu);
1044
1045         return 0;
1046 }
1047
1048 static __init int svm_hardware_setup(void)
1049 {
1050         int cpu;
1051         struct page *iopm_pages;
1052         void *iopm_va;
1053         int r;
1054
1055         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1056
1057         if (!iopm_pages)
1058                 return -ENOMEM;
1059
1060         iopm_va = page_address(iopm_pages);
1061         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1062         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1063
1064         init_msrpm_offsets();
1065
1066         if (boot_cpu_has(X86_FEATURE_NX))
1067                 kvm_enable_efer_bits(EFER_NX);
1068
1069         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1070                 kvm_enable_efer_bits(EFER_FFXSR);
1071
1072         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1073                 kvm_has_tsc_control = true;
1074                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1075                 kvm_tsc_scaling_ratio_frac_bits = 32;
1076         }
1077
1078         if (nested) {
1079                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1080                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1081         }
1082
1083         for_each_possible_cpu(cpu) {
1084                 r = svm_cpu_init(cpu);
1085                 if (r)
1086                         goto err;
1087         }
1088
1089         if (!boot_cpu_has(X86_FEATURE_NPT))
1090                 npt_enabled = false;
1091
1092         if (npt_enabled && !npt) {
1093                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1094                 npt_enabled = false;
1095         }
1096
1097         if (npt_enabled) {
1098                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1099                 kvm_enable_tdp();
1100         } else
1101                 kvm_disable_tdp();
1102
1103         if (avic) {
1104                 if (!npt_enabled ||
1105                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1106                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1107                         avic = false;
1108                 } else {
1109                         pr_info("AVIC enabled\n");
1110
1111                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1112                 }
1113         }
1114
1115         if (vls) {
1116                 if (!npt_enabled ||
1117                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1118                     !IS_ENABLED(CONFIG_X86_64)) {
1119                         vls = false;
1120                 } else {
1121                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1122                 }
1123         }
1124
1125         if (vgif) {
1126                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1127                         vgif = false;
1128                 else
1129                         pr_info("Virtual GIF supported\n");
1130         }
1131
1132         return 0;
1133
1134 err:
1135         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1136         iopm_base = 0;
1137         return r;
1138 }
1139
1140 static __exit void svm_hardware_unsetup(void)
1141 {
1142         int cpu;
1143
1144         for_each_possible_cpu(cpu)
1145                 svm_cpu_uninit(cpu);
1146
1147         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1148         iopm_base = 0;
1149 }
1150
1151 static void init_seg(struct vmcb_seg *seg)
1152 {
1153         seg->selector = 0;
1154         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1155                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1156         seg->limit = 0xffff;
1157         seg->base = 0;
1158 }
1159
1160 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1161 {
1162         seg->selector = 0;
1163         seg->attrib = SVM_SELECTOR_P_MASK | type;
1164         seg->limit = 0xffff;
1165         seg->base = 0;
1166 }
1167
1168 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1169 {
1170         struct vcpu_svm *svm = to_svm(vcpu);
1171         u64 g_tsc_offset = 0;
1172
1173         if (is_guest_mode(vcpu)) {
1174                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1175                                svm->nested.hsave->control.tsc_offset;
1176                 svm->nested.hsave->control.tsc_offset = offset;
1177         } else
1178                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1179                                            svm->vmcb->control.tsc_offset,
1180                                            offset);
1181
1182         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1183
1184         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1185 }
1186
1187 static void avic_init_vmcb(struct vcpu_svm *svm)
1188 {
1189         struct vmcb *vmcb = svm->vmcb;
1190         struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1191         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1192         phys_addr_t lpa = __sme_set(page_to_phys(vm_data->avic_logical_id_table_page));
1193         phys_addr_t ppa = __sme_set(page_to_phys(vm_data->avic_physical_id_table_page));
1194
1195         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1196         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1197         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1198         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1199         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1200 }
1201
1202 static void init_vmcb(struct vcpu_svm *svm)
1203 {
1204         struct vmcb_control_area *control = &svm->vmcb->control;
1205         struct vmcb_save_area *save = &svm->vmcb->save;
1206
1207         svm->vcpu.arch.hflags = 0;
1208
1209         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1210         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1211         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1212         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1213         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1214         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1215         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1216                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1217
1218         set_dr_intercepts(svm);
1219
1220         set_exception_intercept(svm, PF_VECTOR);
1221         set_exception_intercept(svm, UD_VECTOR);
1222         set_exception_intercept(svm, MC_VECTOR);
1223         set_exception_intercept(svm, AC_VECTOR);
1224         set_exception_intercept(svm, DB_VECTOR);
1225
1226         set_intercept(svm, INTERCEPT_INTR);
1227         set_intercept(svm, INTERCEPT_NMI);
1228         set_intercept(svm, INTERCEPT_SMI);
1229         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1230         set_intercept(svm, INTERCEPT_RDPMC);
1231         set_intercept(svm, INTERCEPT_CPUID);
1232         set_intercept(svm, INTERCEPT_INVD);
1233         set_intercept(svm, INTERCEPT_HLT);
1234         set_intercept(svm, INTERCEPT_INVLPG);
1235         set_intercept(svm, INTERCEPT_INVLPGA);
1236         set_intercept(svm, INTERCEPT_IOIO_PROT);
1237         set_intercept(svm, INTERCEPT_MSR_PROT);
1238         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1239         set_intercept(svm, INTERCEPT_SHUTDOWN);
1240         set_intercept(svm, INTERCEPT_VMRUN);
1241         set_intercept(svm, INTERCEPT_VMMCALL);
1242         set_intercept(svm, INTERCEPT_VMLOAD);
1243         set_intercept(svm, INTERCEPT_VMSAVE);
1244         set_intercept(svm, INTERCEPT_STGI);
1245         set_intercept(svm, INTERCEPT_CLGI);
1246         set_intercept(svm, INTERCEPT_SKINIT);
1247         set_intercept(svm, INTERCEPT_WBINVD);
1248         set_intercept(svm, INTERCEPT_XSETBV);
1249
1250         if (!kvm_mwait_in_guest()) {
1251                 set_intercept(svm, INTERCEPT_MONITOR);
1252                 set_intercept(svm, INTERCEPT_MWAIT);
1253         }
1254
1255         control->iopm_base_pa = __sme_set(iopm_base);
1256         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1257         control->int_ctl = V_INTR_MASKING_MASK;
1258
1259         init_seg(&save->es);
1260         init_seg(&save->ss);
1261         init_seg(&save->ds);
1262         init_seg(&save->fs);
1263         init_seg(&save->gs);
1264
1265         save->cs.selector = 0xf000;
1266         save->cs.base = 0xffff0000;
1267         /* Executable/Readable Code Segment */
1268         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1269                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1270         save->cs.limit = 0xffff;
1271
1272         save->gdtr.limit = 0xffff;
1273         save->idtr.limit = 0xffff;
1274
1275         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1276         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1277
1278         svm_set_efer(&svm->vcpu, 0);
1279         save->dr6 = 0xffff0ff0;
1280         kvm_set_rflags(&svm->vcpu, 2);
1281         save->rip = 0x0000fff0;
1282         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1283
1284         /*
1285          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1286          * It also updates the guest-visible cr0 value.
1287          */
1288         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1289         kvm_mmu_reset_context(&svm->vcpu);
1290
1291         save->cr4 = X86_CR4_PAE;
1292         /* rdx = ?? */
1293
1294         if (npt_enabled) {
1295                 /* Setup VMCB for Nested Paging */
1296                 control->nested_ctl = 1;
1297                 clr_intercept(svm, INTERCEPT_INVLPG);
1298                 clr_exception_intercept(svm, PF_VECTOR);
1299                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1300                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1301                 save->g_pat = svm->vcpu.arch.pat;
1302                 save->cr3 = 0;
1303                 save->cr4 = 0;
1304         }
1305         svm->asid_generation = 0;
1306
1307         svm->nested.vmcb = 0;
1308         svm->vcpu.arch.hflags = 0;
1309
1310         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1311                 control->pause_filter_count = 3000;
1312                 set_intercept(svm, INTERCEPT_PAUSE);
1313         }
1314
1315         if (kvm_vcpu_apicv_active(&svm->vcpu))
1316                 avic_init_vmcb(svm);
1317
1318         /*
1319          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1320          * in VMCB and clear intercepts to avoid #VMEXIT.
1321          */
1322         if (vls) {
1323                 clr_intercept(svm, INTERCEPT_VMLOAD);
1324                 clr_intercept(svm, INTERCEPT_VMSAVE);
1325                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1326         }
1327
1328         if (vgif) {
1329                 clr_intercept(svm, INTERCEPT_STGI);
1330                 clr_intercept(svm, INTERCEPT_CLGI);
1331                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1332         }
1333
1334         mark_all_dirty(svm->vmcb);
1335
1336         enable_gif(svm);
1337
1338 }
1339
1340 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1341                                        unsigned int index)
1342 {
1343         u64 *avic_physical_id_table;
1344         struct kvm_arch *vm_data = &vcpu->kvm->arch;
1345
1346         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1347                 return NULL;
1348
1349         avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1350
1351         return &avic_physical_id_table[index];
1352 }
1353
1354 /**
1355  * Note:
1356  * AVIC hardware walks the nested page table to check permissions,
1357  * but does not use the SPA address specified in the leaf page
1358  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1359  * field of the VMCB. Therefore, we set up the
1360  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1361  */
1362 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1363 {
1364         struct kvm *kvm = vcpu->kvm;
1365         int ret;
1366
1367         if (kvm->arch.apic_access_page_done)
1368                 return 0;
1369
1370         ret = x86_set_memory_region(kvm,
1371                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1372                                     APIC_DEFAULT_PHYS_BASE,
1373                                     PAGE_SIZE);
1374         if (ret)
1375                 return ret;
1376
1377         kvm->arch.apic_access_page_done = true;
1378         return 0;
1379 }
1380
1381 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1382 {
1383         int ret;
1384         u64 *entry, new_entry;
1385         int id = vcpu->vcpu_id;
1386         struct vcpu_svm *svm = to_svm(vcpu);
1387
1388         ret = avic_init_access_page(vcpu);
1389         if (ret)
1390                 return ret;
1391
1392         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1393                 return -EINVAL;
1394
1395         if (!svm->vcpu.arch.apic->regs)
1396                 return -EINVAL;
1397
1398         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1399
1400         /* Setting AVIC backing page address in the phy APIC ID table */
1401         entry = avic_get_physical_id_entry(vcpu, id);
1402         if (!entry)
1403                 return -EINVAL;
1404
1405         new_entry = READ_ONCE(*entry);
1406         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1407                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1408                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1409         WRITE_ONCE(*entry, new_entry);
1410
1411         svm->avic_physical_id_cache = entry;
1412
1413         return 0;
1414 }
1415
1416 static void avic_vm_destroy(struct kvm *kvm)
1417 {
1418         unsigned long flags;
1419         struct kvm_arch *vm_data = &kvm->arch;
1420
1421         if (!avic)
1422                 return;
1423
1424         if (vm_data->avic_logical_id_table_page)
1425                 __free_page(vm_data->avic_logical_id_table_page);
1426         if (vm_data->avic_physical_id_table_page)
1427                 __free_page(vm_data->avic_physical_id_table_page);
1428
1429         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1430         hash_del(&vm_data->hnode);
1431         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1432 }
1433
1434 static int avic_vm_init(struct kvm *kvm)
1435 {
1436         unsigned long flags;
1437         int err = -ENOMEM;
1438         struct kvm_arch *vm_data = &kvm->arch;
1439         struct page *p_page;
1440         struct page *l_page;
1441         struct kvm_arch *ka;
1442         u32 vm_id;
1443
1444         if (!avic)
1445                 return 0;
1446
1447         /* Allocating physical APIC ID table (4KB) */
1448         p_page = alloc_page(GFP_KERNEL);
1449         if (!p_page)
1450                 goto free_avic;
1451
1452         vm_data->avic_physical_id_table_page = p_page;
1453         clear_page(page_address(p_page));
1454
1455         /* Allocating logical APIC ID table (4KB) */
1456         l_page = alloc_page(GFP_KERNEL);
1457         if (!l_page)
1458                 goto free_avic;
1459
1460         vm_data->avic_logical_id_table_page = l_page;
1461         clear_page(page_address(l_page));
1462
1463         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1464  again:
1465         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1466         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1467                 next_vm_id_wrapped = 1;
1468                 goto again;
1469         }
1470         /* Is it still in use? Only possible if wrapped at least once */
1471         if (next_vm_id_wrapped) {
1472                 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
1473                         struct kvm *k2 = container_of(ka, struct kvm, arch);
1474                         struct kvm_arch *vd2 = &k2->arch;
1475                         if (vd2->avic_vm_id == vm_id)
1476                                 goto again;
1477                 }
1478         }
1479         vm_data->avic_vm_id = vm_id;
1480         hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1481         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1482
1483         return 0;
1484
1485 free_avic:
1486         avic_vm_destroy(kvm);
1487         return err;
1488 }
1489
1490 static inline int
1491 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1492 {
1493         int ret = 0;
1494         unsigned long flags;
1495         struct amd_svm_iommu_ir *ir;
1496         struct vcpu_svm *svm = to_svm(vcpu);
1497
1498         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1499                 return 0;
1500
1501         /*
1502          * Here, we go through the per-vcpu ir_list to update all existing
1503          * interrupt remapping table entry targeting this vcpu.
1504          */
1505         spin_lock_irqsave(&svm->ir_list_lock, flags);
1506
1507         if (list_empty(&svm->ir_list))
1508                 goto out;
1509
1510         list_for_each_entry(ir, &svm->ir_list, node) {
1511                 ret = amd_iommu_update_ga(cpu, r, ir->data);
1512                 if (ret)
1513                         break;
1514         }
1515 out:
1516         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1517         return ret;
1518 }
1519
1520 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1521 {
1522         u64 entry;
1523         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1524         int h_physical_id = kvm_cpu_get_apicid(cpu);
1525         struct vcpu_svm *svm = to_svm(vcpu);
1526
1527         if (!kvm_vcpu_apicv_active(vcpu))
1528                 return;
1529
1530         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1531                 return;
1532
1533         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1534         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1535
1536         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1537         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1538
1539         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1540         if (svm->avic_is_running)
1541                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1542
1543         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1544         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1545                                         svm->avic_is_running);
1546 }
1547
1548 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1549 {
1550         u64 entry;
1551         struct vcpu_svm *svm = to_svm(vcpu);
1552
1553         if (!kvm_vcpu_apicv_active(vcpu))
1554                 return;
1555
1556         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1557         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1558                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1559
1560         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1561         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1562 }
1563
1564 /**
1565  * This function is called during VCPU halt/unhalt.
1566  */
1567 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1568 {
1569         struct vcpu_svm *svm = to_svm(vcpu);
1570
1571         svm->avic_is_running = is_run;
1572         if (is_run)
1573                 avic_vcpu_load(vcpu, vcpu->cpu);
1574         else
1575                 avic_vcpu_put(vcpu);
1576 }
1577
1578 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1579 {
1580         struct vcpu_svm *svm = to_svm(vcpu);
1581         u32 dummy;
1582         u32 eax = 1;
1583
1584         if (!init_event) {
1585                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1586                                            MSR_IA32_APICBASE_ENABLE;
1587                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1588                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1589         }
1590         init_vmcb(svm);
1591
1592         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
1593         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1594
1595         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1596                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1597 }
1598
1599 static int avic_init_vcpu(struct vcpu_svm *svm)
1600 {
1601         int ret;
1602
1603         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1604                 return 0;
1605
1606         ret = avic_init_backing_page(&svm->vcpu);
1607         if (ret)
1608                 return ret;
1609
1610         INIT_LIST_HEAD(&svm->ir_list);
1611         spin_lock_init(&svm->ir_list_lock);
1612
1613         return ret;
1614 }
1615
1616 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1617 {
1618         struct vcpu_svm *svm;
1619         struct page *page;
1620         struct page *msrpm_pages;
1621         struct page *hsave_page;
1622         struct page *nested_msrpm_pages;
1623         int err;
1624
1625         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1626         if (!svm) {
1627                 err = -ENOMEM;
1628                 goto out;
1629         }
1630
1631         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1632         if (err)
1633                 goto free_svm;
1634
1635         err = -ENOMEM;
1636         page = alloc_page(GFP_KERNEL);
1637         if (!page)
1638                 goto uninit;
1639
1640         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1641         if (!msrpm_pages)
1642                 goto free_page1;
1643
1644         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1645         if (!nested_msrpm_pages)
1646                 goto free_page2;
1647
1648         hsave_page = alloc_page(GFP_KERNEL);
1649         if (!hsave_page)
1650                 goto free_page3;
1651
1652         err = avic_init_vcpu(svm);
1653         if (err)
1654                 goto free_page4;
1655
1656         /* We initialize this flag to true to make sure that the is_running
1657          * bit would be set the first time the vcpu is loaded.
1658          */
1659         svm->avic_is_running = true;
1660
1661         svm->nested.hsave = page_address(hsave_page);
1662
1663         svm->msrpm = page_address(msrpm_pages);
1664         svm_vcpu_init_msrpm(svm->msrpm);
1665
1666         svm->nested.msrpm = page_address(nested_msrpm_pages);
1667         svm_vcpu_init_msrpm(svm->nested.msrpm);
1668
1669         svm->vmcb = page_address(page);
1670         clear_page(svm->vmcb);
1671         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
1672         svm->asid_generation = 0;
1673         init_vmcb(svm);
1674
1675         svm_init_osvw(&svm->vcpu);
1676
1677         return &svm->vcpu;
1678
1679 free_page4:
1680         __free_page(hsave_page);
1681 free_page3:
1682         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1683 free_page2:
1684         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1685 free_page1:
1686         __free_page(page);
1687 uninit:
1688         kvm_vcpu_uninit(&svm->vcpu);
1689 free_svm:
1690         kmem_cache_free(kvm_vcpu_cache, svm);
1691 out:
1692         return ERR_PTR(err);
1693 }
1694
1695 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1696 {
1697         struct vcpu_svm *svm = to_svm(vcpu);
1698
1699         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1700         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1701         __free_page(virt_to_page(svm->nested.hsave));
1702         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1703         kvm_vcpu_uninit(vcpu);
1704         kmem_cache_free(kvm_vcpu_cache, svm);
1705 }
1706
1707 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1708 {
1709         struct vcpu_svm *svm = to_svm(vcpu);
1710         int i;
1711
1712         if (unlikely(cpu != vcpu->cpu)) {
1713                 svm->asid_generation = 0;
1714                 mark_all_dirty(svm->vmcb);
1715         }
1716
1717 #ifdef CONFIG_X86_64
1718         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1719 #endif
1720         savesegment(fs, svm->host.fs);
1721         savesegment(gs, svm->host.gs);
1722         svm->host.ldt = kvm_read_ldt();
1723
1724         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1725                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1726
1727         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1728                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1729                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1730                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1731                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1732                 }
1733         }
1734         /* This assumes that the kernel never uses MSR_TSC_AUX */
1735         if (static_cpu_has(X86_FEATURE_RDTSCP))
1736                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1737
1738         avic_vcpu_load(vcpu, cpu);
1739 }
1740
1741 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1742 {
1743         struct vcpu_svm *svm = to_svm(vcpu);
1744         int i;
1745
1746         avic_vcpu_put(vcpu);
1747
1748         ++vcpu->stat.host_state_reload;
1749         kvm_load_ldt(svm->host.ldt);
1750 #ifdef CONFIG_X86_64
1751         loadsegment(fs, svm->host.fs);
1752         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1753         load_gs_index(svm->host.gs);
1754 #else
1755 #ifdef CONFIG_X86_32_LAZY_GS
1756         loadsegment(gs, svm->host.gs);
1757 #endif
1758 #endif
1759         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1760                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1761 }
1762
1763 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1764 {
1765         avic_set_running(vcpu, false);
1766 }
1767
1768 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1769 {
1770         avic_set_running(vcpu, true);
1771 }
1772
1773 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1774 {
1775         struct vcpu_svm *svm = to_svm(vcpu);
1776         unsigned long rflags = svm->vmcb->save.rflags;
1777
1778         if (svm->nmi_singlestep) {
1779                 /* Hide our flags if they were not set by the guest */
1780                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1781                         rflags &= ~X86_EFLAGS_TF;
1782                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1783                         rflags &= ~X86_EFLAGS_RF;
1784         }
1785         return rflags;
1786 }
1787
1788 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1789 {
1790         if (to_svm(vcpu)->nmi_singlestep)
1791                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1792
1793        /*
1794         * Any change of EFLAGS.VM is accompanied by a reload of SS
1795         * (caused by either a task switch or an inter-privilege IRET),
1796         * so we do not need to update the CPL here.
1797         */
1798         to_svm(vcpu)->vmcb->save.rflags = rflags;
1799 }
1800
1801 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1802 {
1803         switch (reg) {
1804         case VCPU_EXREG_PDPTR:
1805                 BUG_ON(!npt_enabled);
1806                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1807                 break;
1808         default:
1809                 BUG();
1810         }
1811 }
1812
1813 static void svm_set_vintr(struct vcpu_svm *svm)
1814 {
1815         set_intercept(svm, INTERCEPT_VINTR);
1816 }
1817
1818 static void svm_clear_vintr(struct vcpu_svm *svm)
1819 {
1820         clr_intercept(svm, INTERCEPT_VINTR);
1821 }
1822
1823 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1824 {
1825         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1826
1827         switch (seg) {
1828         case VCPU_SREG_CS: return &save->cs;
1829         case VCPU_SREG_DS: return &save->ds;
1830         case VCPU_SREG_ES: return &save->es;
1831         case VCPU_SREG_FS: return &save->fs;
1832         case VCPU_SREG_GS: return &save->gs;
1833         case VCPU_SREG_SS: return &save->ss;
1834         case VCPU_SREG_TR: return &save->tr;
1835         case VCPU_SREG_LDTR: return &save->ldtr;
1836         }
1837         BUG();
1838         return NULL;
1839 }
1840
1841 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1842 {
1843         struct vmcb_seg *s = svm_seg(vcpu, seg);
1844
1845         return s->base;
1846 }
1847
1848 static void svm_get_segment(struct kvm_vcpu *vcpu,
1849                             struct kvm_segment *var, int seg)
1850 {
1851         struct vmcb_seg *s = svm_seg(vcpu, seg);
1852
1853         var->base = s->base;
1854         var->limit = s->limit;
1855         var->selector = s->selector;
1856         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1857         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1858         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1859         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1860         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1861         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1862         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1863
1864         /*
1865          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1866          * However, the SVM spec states that the G bit is not observed by the
1867          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1868          * So let's synthesize a legal G bit for all segments, this helps
1869          * running KVM nested. It also helps cross-vendor migration, because
1870          * Intel's vmentry has a check on the 'G' bit.
1871          */
1872         var->g = s->limit > 0xfffff;
1873
1874         /*
1875          * AMD's VMCB does not have an explicit unusable field, so emulate it
1876          * for cross vendor migration purposes by "not present"
1877          */
1878         var->unusable = !var->present;
1879
1880         switch (seg) {
1881         case VCPU_SREG_TR:
1882                 /*
1883                  * Work around a bug where the busy flag in the tr selector
1884                  * isn't exposed
1885                  */
1886                 var->type |= 0x2;
1887                 break;
1888         case VCPU_SREG_DS:
1889         case VCPU_SREG_ES:
1890         case VCPU_SREG_FS:
1891         case VCPU_SREG_GS:
1892                 /*
1893                  * The accessed bit must always be set in the segment
1894                  * descriptor cache, although it can be cleared in the
1895                  * descriptor, the cached bit always remains at 1. Since
1896                  * Intel has a check on this, set it here to support
1897                  * cross-vendor migration.
1898                  */
1899                 if (!var->unusable)
1900                         var->type |= 0x1;
1901                 break;
1902         case VCPU_SREG_SS:
1903                 /*
1904                  * On AMD CPUs sometimes the DB bit in the segment
1905                  * descriptor is left as 1, although the whole segment has
1906                  * been made unusable. Clear it here to pass an Intel VMX
1907                  * entry check when cross vendor migrating.
1908                  */
1909                 if (var->unusable)
1910                         var->db = 0;
1911                 /* This is symmetric with svm_set_segment() */
1912                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1913                 break;
1914         }
1915 }
1916
1917 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1918 {
1919         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1920
1921         return save->cpl;
1922 }
1923
1924 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1925 {
1926         struct vcpu_svm *svm = to_svm(vcpu);
1927
1928         dt->size = svm->vmcb->save.idtr.limit;
1929         dt->address = svm->vmcb->save.idtr.base;
1930 }
1931
1932 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1933 {
1934         struct vcpu_svm *svm = to_svm(vcpu);
1935
1936         svm->vmcb->save.idtr.limit = dt->size;
1937         svm->vmcb->save.idtr.base = dt->address ;
1938         mark_dirty(svm->vmcb, VMCB_DT);
1939 }
1940
1941 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1942 {
1943         struct vcpu_svm *svm = to_svm(vcpu);
1944
1945         dt->size = svm->vmcb->save.gdtr.limit;
1946         dt->address = svm->vmcb->save.gdtr.base;
1947 }
1948
1949 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1950 {
1951         struct vcpu_svm *svm = to_svm(vcpu);
1952
1953         svm->vmcb->save.gdtr.limit = dt->size;
1954         svm->vmcb->save.gdtr.base = dt->address ;
1955         mark_dirty(svm->vmcb, VMCB_DT);
1956 }
1957
1958 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1959 {
1960 }
1961
1962 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1963 {
1964 }
1965
1966 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1967 {
1968 }
1969
1970 static void update_cr0_intercept(struct vcpu_svm *svm)
1971 {
1972         ulong gcr0 = svm->vcpu.arch.cr0;
1973         u64 *hcr0 = &svm->vmcb->save.cr0;
1974
1975         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1976                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1977
1978         mark_dirty(svm->vmcb, VMCB_CR);
1979
1980         if (gcr0 == *hcr0) {
1981                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1982                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1983         } else {
1984                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1985                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1986         }
1987 }
1988
1989 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1990 {
1991         struct vcpu_svm *svm = to_svm(vcpu);
1992
1993 #ifdef CONFIG_X86_64
1994         if (vcpu->arch.efer & EFER_LME) {
1995                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1996                         vcpu->arch.efer |= EFER_LMA;
1997                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1998                 }
1999
2000                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2001                         vcpu->arch.efer &= ~EFER_LMA;
2002                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2003                 }
2004         }
2005 #endif
2006         vcpu->arch.cr0 = cr0;
2007
2008         if (!npt_enabled)
2009                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2010
2011         /*
2012          * re-enable caching here because the QEMU bios
2013          * does not do it - this results in some delay at
2014          * reboot
2015          */
2016         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2017                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2018         svm->vmcb->save.cr0 = cr0;
2019         mark_dirty(svm->vmcb, VMCB_CR);
2020         update_cr0_intercept(svm);
2021 }
2022
2023 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2024 {
2025         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2026         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2027
2028         if (cr4 & X86_CR4_VMXE)
2029                 return 1;
2030
2031         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2032                 svm_flush_tlb(vcpu);
2033
2034         vcpu->arch.cr4 = cr4;
2035         if (!npt_enabled)
2036                 cr4 |= X86_CR4_PAE;
2037         cr4 |= host_cr4_mce;
2038         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2039         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2040         return 0;
2041 }
2042
2043 static void svm_set_segment(struct kvm_vcpu *vcpu,
2044                             struct kvm_segment *var, int seg)
2045 {
2046         struct vcpu_svm *svm = to_svm(vcpu);
2047         struct vmcb_seg *s = svm_seg(vcpu, seg);
2048
2049         s->base = var->base;
2050         s->limit = var->limit;
2051         s->selector = var->selector;
2052         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2053         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2054         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2055         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2056         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2057         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2058         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2059         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2060
2061         /*
2062          * This is always accurate, except if SYSRET returned to a segment
2063          * with SS.DPL != 3.  Intel does not have this quirk, and always
2064          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2065          * would entail passing the CPL to userspace and back.
2066          */
2067         if (seg == VCPU_SREG_SS)
2068                 /* This is symmetric with svm_get_segment() */
2069                 svm->vmcb->save.cpl = (var->dpl & 3);
2070
2071         mark_dirty(svm->vmcb, VMCB_SEG);
2072 }
2073
2074 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2075 {
2076         struct vcpu_svm *svm = to_svm(vcpu);
2077
2078         clr_exception_intercept(svm, BP_VECTOR);
2079
2080         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2081                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2082                         set_exception_intercept(svm, BP_VECTOR);
2083         } else
2084                 vcpu->guest_debug = 0;
2085 }
2086
2087 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2088 {
2089         if (sd->next_asid > sd->max_asid) {
2090                 ++sd->asid_generation;
2091                 sd->next_asid = 1;
2092                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2093         }
2094
2095         svm->asid_generation = sd->asid_generation;
2096         svm->vmcb->control.asid = sd->next_asid++;
2097
2098         mark_dirty(svm->vmcb, VMCB_ASID);
2099 }
2100
2101 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2102 {
2103         return to_svm(vcpu)->vmcb->save.dr6;
2104 }
2105
2106 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2107 {
2108         struct vcpu_svm *svm = to_svm(vcpu);
2109
2110         svm->vmcb->save.dr6 = value;
2111         mark_dirty(svm->vmcb, VMCB_DR);
2112 }
2113
2114 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2115 {
2116         struct vcpu_svm *svm = to_svm(vcpu);
2117
2118         get_debugreg(vcpu->arch.db[0], 0);
2119         get_debugreg(vcpu->arch.db[1], 1);
2120         get_debugreg(vcpu->arch.db[2], 2);
2121         get_debugreg(vcpu->arch.db[3], 3);
2122         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2123         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2124
2125         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2126         set_dr_intercepts(svm);
2127 }
2128
2129 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2130 {
2131         struct vcpu_svm *svm = to_svm(vcpu);
2132
2133         svm->vmcb->save.dr7 = value;
2134         mark_dirty(svm->vmcb, VMCB_DR);
2135 }
2136
2137 static int pf_interception(struct vcpu_svm *svm)
2138 {
2139         u64 fault_address = svm->vmcb->control.exit_info_2;
2140         u64 error_code = svm->vmcb->control.exit_info_1;
2141
2142         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2143                         svm->vmcb->control.insn_bytes,
2144                         svm->vmcb->control.insn_len);
2145 }
2146
2147 static int npf_interception(struct vcpu_svm *svm)
2148 {
2149         u64 fault_address = svm->vmcb->control.exit_info_2;
2150         u64 error_code = svm->vmcb->control.exit_info_1;
2151
2152         trace_kvm_page_fault(fault_address, error_code);
2153         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2154                         svm->vmcb->control.insn_bytes,
2155                         svm->vmcb->control.insn_len);
2156 }
2157
2158 static int db_interception(struct vcpu_svm *svm)
2159 {
2160         struct kvm_run *kvm_run = svm->vcpu.run;
2161
2162         if (!(svm->vcpu.guest_debug &
2163               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2164                 !svm->nmi_singlestep) {
2165                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2166                 return 1;
2167         }
2168
2169         if (svm->nmi_singlestep) {
2170                 disable_nmi_singlestep(svm);
2171         }
2172
2173         if (svm->vcpu.guest_debug &
2174             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2175                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2176                 kvm_run->debug.arch.pc =
2177                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2178                 kvm_run->debug.arch.exception = DB_VECTOR;
2179                 return 0;
2180         }
2181
2182         return 1;
2183 }
2184
2185 static int bp_interception(struct vcpu_svm *svm)
2186 {
2187         struct kvm_run *kvm_run = svm->vcpu.run;
2188
2189         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2190         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2191         kvm_run->debug.arch.exception = BP_VECTOR;
2192         return 0;
2193 }
2194
2195 static int ud_interception(struct vcpu_svm *svm)
2196 {
2197         int er;
2198
2199         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2200         if (er == EMULATE_USER_EXIT)
2201                 return 0;
2202         if (er != EMULATE_DONE)
2203                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2204         return 1;
2205 }
2206
2207 static int ac_interception(struct vcpu_svm *svm)
2208 {
2209         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2210         return 1;
2211 }
2212
2213 static bool is_erratum_383(void)
2214 {
2215         int err, i;
2216         u64 value;
2217
2218         if (!erratum_383_found)
2219                 return false;
2220
2221         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2222         if (err)
2223                 return false;
2224
2225         /* Bit 62 may or may not be set for this mce */
2226         value &= ~(1ULL << 62);
2227
2228         if (value != 0xb600000000010015ULL)
2229                 return false;
2230
2231         /* Clear MCi_STATUS registers */
2232         for (i = 0; i < 6; ++i)
2233                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2234
2235         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2236         if (!err) {
2237                 u32 low, high;
2238
2239                 value &= ~(1ULL << 2);
2240                 low    = lower_32_bits(value);
2241                 high   = upper_32_bits(value);
2242
2243                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2244         }
2245
2246         /* Flush tlb to evict multi-match entries */
2247         __flush_tlb_all();
2248
2249         return true;
2250 }
2251
2252 static void svm_handle_mce(struct vcpu_svm *svm)
2253 {
2254         if (is_erratum_383()) {
2255                 /*
2256                  * Erratum 383 triggered. Guest state is corrupt so kill the
2257                  * guest.
2258                  */
2259                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2260
2261                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2262
2263                 return;
2264         }
2265
2266         /*
2267          * On an #MC intercept the MCE handler is not called automatically in
2268          * the host. So do it by hand here.
2269          */
2270         asm volatile (
2271                 "int $0x12\n");
2272         /* not sure if we ever come back to this point */
2273
2274         return;
2275 }
2276
2277 static int mc_interception(struct vcpu_svm *svm)
2278 {
2279         return 1;
2280 }
2281
2282 static int shutdown_interception(struct vcpu_svm *svm)
2283 {
2284         struct kvm_run *kvm_run = svm->vcpu.run;
2285
2286         /*
2287          * VMCB is undefined after a SHUTDOWN intercept
2288          * so reinitialize it.
2289          */
2290         clear_page(svm->vmcb);
2291         init_vmcb(svm);
2292
2293         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2294         return 0;
2295 }
2296
2297 static int io_interception(struct vcpu_svm *svm)
2298 {
2299         struct kvm_vcpu *vcpu = &svm->vcpu;
2300         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2301         int size, in, string, ret;
2302         unsigned port;
2303
2304         ++svm->vcpu.stat.io_exits;
2305         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2306         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2307         if (string)
2308                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2309
2310         port = io_info >> 16;
2311         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2312         svm->next_rip = svm->vmcb->control.exit_info_2;
2313         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2314
2315         /*
2316          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
2317          * KVM_EXIT_DEBUG here.
2318          */
2319         if (in)
2320                 return kvm_fast_pio_in(vcpu, size, port) && ret;
2321         else
2322                 return kvm_fast_pio_out(vcpu, size, port) && ret;
2323 }
2324
2325 static int nmi_interception(struct vcpu_svm *svm)
2326 {
2327         return 1;
2328 }
2329
2330 static int intr_interception(struct vcpu_svm *svm)
2331 {
2332         ++svm->vcpu.stat.irq_exits;
2333         return 1;
2334 }
2335
2336 static int nop_on_interception(struct vcpu_svm *svm)
2337 {
2338         return 1;
2339 }
2340
2341 static int halt_interception(struct vcpu_svm *svm)
2342 {
2343         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2344         return kvm_emulate_halt(&svm->vcpu);
2345 }
2346
2347 static int vmmcall_interception(struct vcpu_svm *svm)
2348 {
2349         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2350         return kvm_emulate_hypercall(&svm->vcpu);
2351 }
2352
2353 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2354 {
2355         struct vcpu_svm *svm = to_svm(vcpu);
2356
2357         return svm->nested.nested_cr3;
2358 }
2359
2360 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2361 {
2362         struct vcpu_svm *svm = to_svm(vcpu);
2363         u64 cr3 = svm->nested.nested_cr3;
2364         u64 pdpte;
2365         int ret;
2366
2367         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2368                                        offset_in_page(cr3) + index * 8, 8);
2369         if (ret)
2370                 return 0;
2371         return pdpte;
2372 }
2373
2374 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2375                                    unsigned long root)
2376 {
2377         struct vcpu_svm *svm = to_svm(vcpu);
2378
2379         svm->vmcb->control.nested_cr3 = __sme_set(root);
2380         mark_dirty(svm->vmcb, VMCB_NPT);
2381         svm_flush_tlb(vcpu);
2382 }
2383
2384 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2385                                        struct x86_exception *fault)
2386 {
2387         struct vcpu_svm *svm = to_svm(vcpu);
2388
2389         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2390                 /*
2391                  * TODO: track the cause of the nested page fault, and
2392                  * correctly fill in the high bits of exit_info_1.
2393                  */
2394                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2395                 svm->vmcb->control.exit_code_hi = 0;
2396                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2397                 svm->vmcb->control.exit_info_2 = fault->address;
2398         }
2399
2400         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2401         svm->vmcb->control.exit_info_1 |= fault->error_code;
2402
2403         /*
2404          * The present bit is always zero for page structure faults on real
2405          * hardware.
2406          */
2407         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2408                 svm->vmcb->control.exit_info_1 &= ~1;
2409
2410         nested_svm_vmexit(svm);
2411 }
2412
2413 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2414 {
2415         WARN_ON(mmu_is_nested(vcpu));
2416         kvm_init_shadow_mmu(vcpu);
2417         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2418         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2419         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2420         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2421         vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu);
2422         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2423         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2424 }
2425
2426 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2427 {
2428         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2429 }
2430
2431 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2432 {
2433         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2434             !is_paging(&svm->vcpu)) {
2435                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2436                 return 1;
2437         }
2438
2439         if (svm->vmcb->save.cpl) {
2440                 kvm_inject_gp(&svm->vcpu, 0);
2441                 return 1;
2442         }
2443
2444         return 0;
2445 }
2446
2447 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2448                                       bool has_error_code, u32 error_code)
2449 {
2450         int vmexit;
2451
2452         if (!is_guest_mode(&svm->vcpu))
2453                 return 0;
2454
2455         vmexit = nested_svm_intercept(svm);
2456         if (vmexit != NESTED_EXIT_DONE)
2457                 return 0;
2458
2459         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2460         svm->vmcb->control.exit_code_hi = 0;
2461         svm->vmcb->control.exit_info_1 = error_code;
2462
2463         /*
2464          * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2465          * The fix is to add the ancillary datum (CR2 or DR6) to structs
2466          * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2467          * written only when inject_pending_event runs (DR6 would written here
2468          * too).  This should be conditional on a new capability---if the
2469          * capability is disabled, kvm_multiple_exception would write the
2470          * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2471          */
2472         if (svm->vcpu.arch.exception.nested_apf)
2473                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2474         else
2475                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2476
2477         svm->nested.exit_required = true;
2478         return vmexit;
2479 }
2480
2481 /* This function returns true if it is save to enable the irq window */
2482 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2483 {
2484         if (!is_guest_mode(&svm->vcpu))
2485                 return true;
2486
2487         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2488                 return true;
2489
2490         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2491                 return false;
2492
2493         /*
2494          * if vmexit was already requested (by intercepted exception
2495          * for instance) do not overwrite it with "external interrupt"
2496          * vmexit.
2497          */
2498         if (svm->nested.exit_required)
2499                 return false;
2500
2501         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2502         svm->vmcb->control.exit_info_1 = 0;
2503         svm->vmcb->control.exit_info_2 = 0;
2504
2505         if (svm->nested.intercept & 1ULL) {
2506                 /*
2507                  * The #vmexit can't be emulated here directly because this
2508                  * code path runs with irqs and preemption disabled. A
2509                  * #vmexit emulation might sleep. Only signal request for
2510                  * the #vmexit here.
2511                  */
2512                 svm->nested.exit_required = true;
2513                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2514                 return false;
2515         }
2516
2517         return true;
2518 }
2519
2520 /* This function returns true if it is save to enable the nmi window */
2521 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2522 {
2523         if (!is_guest_mode(&svm->vcpu))
2524                 return true;
2525
2526         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2527                 return true;
2528
2529         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2530         svm->nested.exit_required = true;
2531
2532         return false;
2533 }
2534
2535 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2536 {
2537         struct page *page;
2538
2539         might_sleep();
2540
2541         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2542         if (is_error_page(page))
2543                 goto error;
2544
2545         *_page = page;
2546
2547         return kmap(page);
2548
2549 error:
2550         kvm_inject_gp(&svm->vcpu, 0);
2551
2552         return NULL;
2553 }
2554
2555 static void nested_svm_unmap(struct page *page)
2556 {
2557         kunmap(page);
2558         kvm_release_page_dirty(page);
2559 }
2560
2561 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2562 {
2563         unsigned port, size, iopm_len;
2564         u16 val, mask;
2565         u8 start_bit;
2566         u64 gpa;
2567
2568         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2569                 return NESTED_EXIT_HOST;
2570
2571         port = svm->vmcb->control.exit_info_1 >> 16;
2572         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2573                 SVM_IOIO_SIZE_SHIFT;
2574         gpa  = svm->nested.vmcb_iopm + (port / 8);
2575         start_bit = port % 8;
2576         iopm_len = (start_bit + size > 8) ? 2 : 1;
2577         mask = (0xf >> (4 - size)) << start_bit;
2578         val = 0;
2579
2580         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2581                 return NESTED_EXIT_DONE;
2582
2583         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2584 }
2585
2586 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2587 {
2588         u32 offset, msr, value;
2589         int write, mask;
2590
2591         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2592                 return NESTED_EXIT_HOST;
2593
2594         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2595         offset = svm_msrpm_offset(msr);
2596         write  = svm->vmcb->control.exit_info_1 & 1;
2597         mask   = 1 << ((2 * (msr & 0xf)) + write);
2598
2599         if (offset == MSR_INVALID)
2600                 return NESTED_EXIT_DONE;
2601
2602         /* Offset is in 32 bit units but need in 8 bit units */
2603         offset *= 4;
2604
2605         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2606                 return NESTED_EXIT_DONE;
2607
2608         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2609 }
2610
2611 /* DB exceptions for our internal use must not cause vmexit */
2612 static int nested_svm_intercept_db(struct vcpu_svm *svm)
2613 {
2614         unsigned long dr6;
2615
2616         /* if we're not singlestepping, it's not ours */
2617         if (!svm->nmi_singlestep)
2618                 return NESTED_EXIT_DONE;
2619
2620         /* if it's not a singlestep exception, it's not ours */
2621         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
2622                 return NESTED_EXIT_DONE;
2623         if (!(dr6 & DR6_BS))
2624                 return NESTED_EXIT_DONE;
2625
2626         /* if the guest is singlestepping, it should get the vmexit */
2627         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
2628                 disable_nmi_singlestep(svm);
2629                 return NESTED_EXIT_DONE;
2630         }
2631
2632         /* it's ours, the nested hypervisor must not see this one */
2633         return NESTED_EXIT_HOST;
2634 }
2635
2636 static int nested_svm_exit_special(struct vcpu_svm *svm)
2637 {
2638         u32 exit_code = svm->vmcb->control.exit_code;
2639
2640         switch (exit_code) {
2641         case SVM_EXIT_INTR:
2642         case SVM_EXIT_NMI:
2643         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2644                 return NESTED_EXIT_HOST;
2645         case SVM_EXIT_NPF:
2646                 /* For now we are always handling NPFs when using them */
2647                 if (npt_enabled)
2648                         return NESTED_EXIT_HOST;
2649                 break;
2650         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2651                 /* When we're shadowing, trap PFs, but not async PF */
2652                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
2653                         return NESTED_EXIT_HOST;
2654                 break;
2655         default:
2656                 break;
2657         }
2658
2659         return NESTED_EXIT_CONTINUE;
2660 }
2661
2662 /*
2663  * If this function returns true, this #vmexit was already handled
2664  */
2665 static int nested_svm_intercept(struct vcpu_svm *svm)
2666 {
2667         u32 exit_code = svm->vmcb->control.exit_code;
2668         int vmexit = NESTED_EXIT_HOST;
2669
2670         switch (exit_code) {
2671         case SVM_EXIT_MSR:
2672                 vmexit = nested_svm_exit_handled_msr(svm);
2673                 break;
2674         case SVM_EXIT_IOIO:
2675                 vmexit = nested_svm_intercept_ioio(svm);
2676                 break;
2677         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2678                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2679                 if (svm->nested.intercept_cr & bit)
2680                         vmexit = NESTED_EXIT_DONE;
2681                 break;
2682         }
2683         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2684                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2685                 if (svm->nested.intercept_dr & bit)
2686                         vmexit = NESTED_EXIT_DONE;
2687                 break;
2688         }
2689         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2690                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2691                 if (svm->nested.intercept_exceptions & excp_bits) {
2692                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
2693                                 vmexit = nested_svm_intercept_db(svm);
2694                         else
2695                                 vmexit = NESTED_EXIT_DONE;
2696                 }
2697                 /* async page fault always cause vmexit */
2698                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2699                          svm->vcpu.arch.exception.nested_apf != 0)
2700                         vmexit = NESTED_EXIT_DONE;
2701                 break;
2702         }
2703         case SVM_EXIT_ERR: {
2704                 vmexit = NESTED_EXIT_DONE;
2705                 break;
2706         }
2707         default: {
2708                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2709                 if (svm->nested.intercept & exit_bits)
2710                         vmexit = NESTED_EXIT_DONE;
2711         }
2712         }
2713
2714         return vmexit;
2715 }
2716
2717 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2718 {
2719         int vmexit;
2720
2721         vmexit = nested_svm_intercept(svm);
2722
2723         if (vmexit == NESTED_EXIT_DONE)
2724                 nested_svm_vmexit(svm);
2725
2726         return vmexit;
2727 }
2728
2729 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2730 {
2731         struct vmcb_control_area *dst  = &dst_vmcb->control;
2732         struct vmcb_control_area *from = &from_vmcb->control;
2733
2734         dst->intercept_cr         = from->intercept_cr;
2735         dst->intercept_dr         = from->intercept_dr;
2736         dst->intercept_exceptions = from->intercept_exceptions;
2737         dst->intercept            = from->intercept;
2738         dst->iopm_base_pa         = from->iopm_base_pa;
2739         dst->msrpm_base_pa        = from->msrpm_base_pa;
2740         dst->tsc_offset           = from->tsc_offset;
2741         dst->asid                 = from->asid;
2742         dst->tlb_ctl              = from->tlb_ctl;
2743         dst->int_ctl              = from->int_ctl;
2744         dst->int_vector           = from->int_vector;
2745         dst->int_state            = from->int_state;
2746         dst->exit_code            = from->exit_code;
2747         dst->exit_code_hi         = from->exit_code_hi;
2748         dst->exit_info_1          = from->exit_info_1;
2749         dst->exit_info_2          = from->exit_info_2;
2750         dst->exit_int_info        = from->exit_int_info;
2751         dst->exit_int_info_err    = from->exit_int_info_err;
2752         dst->nested_ctl           = from->nested_ctl;
2753         dst->event_inj            = from->event_inj;
2754         dst->event_inj_err        = from->event_inj_err;
2755         dst->nested_cr3           = from->nested_cr3;
2756         dst->virt_ext              = from->virt_ext;
2757 }
2758
2759 static int nested_svm_vmexit(struct vcpu_svm *svm)
2760 {
2761         struct vmcb *nested_vmcb;
2762         struct vmcb *hsave = svm->nested.hsave;
2763         struct vmcb *vmcb = svm->vmcb;
2764         struct page *page;
2765
2766         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2767                                        vmcb->control.exit_info_1,
2768                                        vmcb->control.exit_info_2,
2769                                        vmcb->control.exit_int_info,
2770                                        vmcb->control.exit_int_info_err,
2771                                        KVM_ISA_SVM);
2772
2773         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2774         if (!nested_vmcb)
2775                 return 1;
2776
2777         /* Exit Guest-Mode */
2778         leave_guest_mode(&svm->vcpu);
2779         svm->nested.vmcb = 0;
2780
2781         /* Give the current vmcb to the guest */
2782         disable_gif(svm);
2783
2784         nested_vmcb->save.es     = vmcb->save.es;
2785         nested_vmcb->save.cs     = vmcb->save.cs;
2786         nested_vmcb->save.ss     = vmcb->save.ss;
2787         nested_vmcb->save.ds     = vmcb->save.ds;
2788         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2789         nested_vmcb->save.idtr   = vmcb->save.idtr;
2790         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2791         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2792         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2793         nested_vmcb->save.cr2    = vmcb->save.cr2;
2794         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2795         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2796         nested_vmcb->save.rip    = vmcb->save.rip;
2797         nested_vmcb->save.rsp    = vmcb->save.rsp;
2798         nested_vmcb->save.rax    = vmcb->save.rax;
2799         nested_vmcb->save.dr7    = vmcb->save.dr7;
2800         nested_vmcb->save.dr6    = vmcb->save.dr6;
2801         nested_vmcb->save.cpl    = vmcb->save.cpl;
2802
2803         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2804         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2805         nested_vmcb->control.int_state         = vmcb->control.int_state;
2806         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2807         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2808         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2809         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2810         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2811         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2812
2813         if (svm->nrips_enabled)
2814                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
2815
2816         /*
2817          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2818          * to make sure that we do not lose injected events. So check event_inj
2819          * here and copy it to exit_int_info if it is valid.
2820          * Exit_int_info and event_inj can't be both valid because the case
2821          * below only happens on a VMRUN instruction intercept which has
2822          * no valid exit_int_info set.
2823          */
2824         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2825                 struct vmcb_control_area *nc = &nested_vmcb->control;
2826
2827                 nc->exit_int_info     = vmcb->control.event_inj;
2828                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2829         }
2830
2831         nested_vmcb->control.tlb_ctl           = 0;
2832         nested_vmcb->control.event_inj         = 0;
2833         nested_vmcb->control.event_inj_err     = 0;
2834
2835         /* We always set V_INTR_MASKING and remember the old value in hflags */
2836         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2837                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2838
2839         /* Restore the original control entries */
2840         copy_vmcb_control_area(vmcb, hsave);
2841
2842         kvm_clear_exception_queue(&svm->vcpu);
2843         kvm_clear_interrupt_queue(&svm->vcpu);
2844
2845         svm->nested.nested_cr3 = 0;
2846
2847         /* Restore selected save entries */
2848         svm->vmcb->save.es = hsave->save.es;
2849         svm->vmcb->save.cs = hsave->save.cs;
2850         svm->vmcb->save.ss = hsave->save.ss;
2851         svm->vmcb->save.ds = hsave->save.ds;
2852         svm->vmcb->save.gdtr = hsave->save.gdtr;
2853         svm->vmcb->save.idtr = hsave->save.idtr;
2854         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2855         svm_set_efer(&svm->vcpu, hsave->save.efer);
2856         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2857         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2858         if (npt_enabled) {
2859                 svm->vmcb->save.cr3 = hsave->save.cr3;
2860                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2861         } else {
2862                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2863         }
2864         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2865         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2866         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2867         svm->vmcb->save.dr7 = 0;
2868         svm->vmcb->save.cpl = 0;
2869         svm->vmcb->control.exit_int_info = 0;
2870
2871         mark_all_dirty(svm->vmcb);
2872
2873         nested_svm_unmap(page);
2874
2875         nested_svm_uninit_mmu_context(&svm->vcpu);
2876         kvm_mmu_reset_context(&svm->vcpu);
2877         kvm_mmu_load(&svm->vcpu);
2878
2879         return 0;
2880 }
2881
2882 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2883 {
2884         /*
2885          * This function merges the msr permission bitmaps of kvm and the
2886          * nested vmcb. It is optimized in that it only merges the parts where
2887          * the kvm msr permission bitmap may contain zero bits
2888          */
2889         int i;
2890
2891         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2892                 return true;
2893
2894         for (i = 0; i < MSRPM_OFFSETS; i++) {
2895                 u32 value, p;
2896                 u64 offset;
2897
2898                 if (msrpm_offsets[i] == 0xffffffff)
2899                         break;
2900
2901                 p      = msrpm_offsets[i];
2902                 offset = svm->nested.vmcb_msrpm + (p * 4);
2903
2904                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2905                         return false;
2906
2907                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2908         }
2909
2910         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
2911
2912         return true;
2913 }
2914
2915 static bool nested_vmcb_checks(struct vmcb *vmcb)
2916 {
2917         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2918                 return false;
2919
2920         if (vmcb->control.asid == 0)
2921                 return false;
2922
2923         if (vmcb->control.nested_ctl && !npt_enabled)
2924                 return false;
2925
2926         return true;
2927 }
2928
2929 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
2930                                  struct vmcb *nested_vmcb, struct page *page)
2931 {
2932         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2933                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2934         else
2935                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2936
2937         if (nested_vmcb->control.nested_ctl) {
2938                 kvm_mmu_unload(&svm->vcpu);
2939                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2940                 nested_svm_init_mmu_context(&svm->vcpu);
2941         }
2942
2943         /* Load the nested guest state */
2944         svm->vmcb->save.es = nested_vmcb->save.es;
2945         svm->vmcb->save.cs = nested_vmcb->save.cs;
2946         svm->vmcb->save.ss = nested_vmcb->save.ss;
2947         svm->vmcb->save.ds = nested_vmcb->save.ds;
2948         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2949         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2950         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2951         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2952         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2953         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2954         if (npt_enabled) {
2955                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2956                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2957         } else
2958                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2959
2960         /* Guest paging mode is active - reset mmu */
2961         kvm_mmu_reset_context(&svm->vcpu);
2962
2963         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2964         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2965         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2966         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2967
2968         /* In case we don't even reach vcpu_run, the fields are not updated */
2969         svm->vmcb->save.rax = nested_vmcb->save.rax;
2970         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2971         svm->vmcb->save.rip = nested_vmcb->save.rip;
2972         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2973         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2974         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2975
2976         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2977         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2978
2979         /* cache intercepts */
2980         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2981         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2982         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2983         svm->nested.intercept            = nested_vmcb->control.intercept;
2984
2985         svm_flush_tlb(&svm->vcpu);
2986         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2987         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2988                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2989         else
2990                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2991
2992         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2993                 /* We only want the cr8 intercept bits of the guest */
2994                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2995                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2996         }
2997
2998         /* We don't want to see VMMCALLs from a nested guest */
2999         clr_intercept(svm, INTERCEPT_VMMCALL);
3000
3001         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3002         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3003         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3004         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3005         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3006         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3007
3008         nested_svm_unmap(page);
3009
3010         /* Enter Guest-Mode */
3011         enter_guest_mode(&svm->vcpu);
3012
3013         /*
3014          * Merge guest and host intercepts - must be called  with vcpu in
3015          * guest-mode to take affect here
3016          */
3017         recalc_intercepts(svm);
3018
3019         svm->nested.vmcb = vmcb_gpa;
3020
3021         enable_gif(svm);
3022
3023         mark_all_dirty(svm->vmcb);
3024 }
3025
3026 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3027 {
3028         struct vmcb *nested_vmcb;
3029         struct vmcb *hsave = svm->nested.hsave;
3030         struct vmcb *vmcb = svm->vmcb;
3031         struct page *page;
3032         u64 vmcb_gpa;
3033
3034         vmcb_gpa = svm->vmcb->save.rax;
3035
3036         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3037         if (!nested_vmcb)
3038                 return false;
3039
3040         if (!nested_vmcb_checks(nested_vmcb)) {
3041                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3042                 nested_vmcb->control.exit_code_hi = 0;
3043                 nested_vmcb->control.exit_info_1  = 0;
3044                 nested_vmcb->control.exit_info_2  = 0;
3045
3046                 nested_svm_unmap(page);
3047
3048                 return false;
3049         }
3050
3051         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3052                                nested_vmcb->save.rip,
3053                                nested_vmcb->control.int_ctl,
3054                                nested_vmcb->control.event_inj,
3055                                nested_vmcb->control.nested_ctl);
3056
3057         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3058                                     nested_vmcb->control.intercept_cr >> 16,
3059                                     nested_vmcb->control.intercept_exceptions,
3060                                     nested_vmcb->control.intercept);
3061
3062         /* Clear internal status */
3063         kvm_clear_exception_queue(&svm->vcpu);
3064         kvm_clear_interrupt_queue(&svm->vcpu);
3065
3066         /*
3067          * Save the old vmcb, so we don't need to pick what we save, but can
3068          * restore everything when a VMEXIT occurs
3069          */
3070         hsave->save.es     = vmcb->save.es;
3071         hsave->save.cs     = vmcb->save.cs;
3072         hsave->save.ss     = vmcb->save.ss;
3073         hsave->save.ds     = vmcb->save.ds;
3074         hsave->save.gdtr   = vmcb->save.gdtr;
3075         hsave->save.idtr   = vmcb->save.idtr;
3076         hsave->save.efer   = svm->vcpu.arch.efer;
3077         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3078         hsave->save.cr4    = svm->vcpu.arch.cr4;
3079         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3080         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3081         hsave->save.rsp    = vmcb->save.rsp;
3082         hsave->save.rax    = vmcb->save.rax;
3083         if (npt_enabled)
3084                 hsave->save.cr3    = vmcb->save.cr3;
3085         else
3086                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3087
3088         copy_vmcb_control_area(hsave, vmcb);
3089
3090         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3091
3092         return true;
3093 }
3094
3095 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3096 {
3097         to_vmcb->save.fs = from_vmcb->save.fs;
3098         to_vmcb->save.gs = from_vmcb->save.gs;
3099         to_vmcb->save.tr = from_vmcb->save.tr;
3100         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3101         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3102         to_vmcb->save.star = from_vmcb->save.star;
3103         to_vmcb->save.lstar = from_vmcb->save.lstar;
3104         to_vmcb->save.cstar = from_vmcb->save.cstar;
3105         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3106         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3107         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3108         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3109 }
3110
3111 static int vmload_interception(struct vcpu_svm *svm)
3112 {
3113         struct vmcb *nested_vmcb;
3114         struct page *page;
3115         int ret;
3116
3117         if (nested_svm_check_permissions(svm))
3118                 return 1;
3119
3120         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3121         if (!nested_vmcb)
3122                 return 1;
3123
3124         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3125         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3126
3127         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3128         nested_svm_unmap(page);
3129
3130         return ret;
3131 }
3132
3133 static int vmsave_interception(struct vcpu_svm *svm)
3134 {
3135         struct vmcb *nested_vmcb;
3136         struct page *page;
3137         int ret;
3138
3139         if (nested_svm_check_permissions(svm))
3140                 return 1;
3141
3142         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3143         if (!nested_vmcb)
3144                 return 1;
3145
3146         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3147         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3148
3149         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3150         nested_svm_unmap(page);
3151
3152         return ret;
3153 }
3154
3155 static int vmrun_interception(struct vcpu_svm *svm)
3156 {
3157         if (nested_svm_check_permissions(svm))
3158                 return 1;
3159
3160         /* Save rip after vmrun instruction */
3161         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3162
3163         if (!nested_svm_vmrun(svm))
3164                 return 1;
3165
3166         if (!nested_svm_vmrun_msrpm(svm))
3167                 goto failed;
3168
3169         return 1;
3170
3171 failed:
3172
3173         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3174         svm->vmcb->control.exit_code_hi = 0;
3175         svm->vmcb->control.exit_info_1  = 0;
3176         svm->vmcb->control.exit_info_2  = 0;
3177
3178         nested_svm_vmexit(svm);
3179
3180         return 1;
3181 }
3182
3183 static int stgi_interception(struct vcpu_svm *svm)
3184 {
3185         int ret;
3186
3187         if (nested_svm_check_permissions(svm))
3188                 return 1;
3189
3190         /*
3191          * If VGIF is enabled, the STGI intercept is only added to
3192          * detect the opening of the SMI/NMI window; remove it now.
3193          */
3194         if (vgif_enabled(svm))
3195                 clr_intercept(svm, INTERCEPT_STGI);
3196
3197         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3198         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3199         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3200
3201         enable_gif(svm);
3202
3203         return ret;
3204 }
3205
3206 static int clgi_interception(struct vcpu_svm *svm)
3207 {
3208         int ret;
3209
3210         if (nested_svm_check_permissions(svm))
3211                 return 1;
3212
3213         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3214         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3215
3216         disable_gif(svm);
3217
3218         /* After a CLGI no interrupts should come */
3219         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3220                 svm_clear_vintr(svm);
3221                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3222                 mark_dirty(svm->vmcb, VMCB_INTR);
3223         }
3224
3225         return ret;
3226 }
3227
3228 static int invlpga_interception(struct vcpu_svm *svm)
3229 {
3230         struct kvm_vcpu *vcpu = &svm->vcpu;
3231
3232         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3233                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3234
3235         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3236         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3237
3238         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3239         return kvm_skip_emulated_instruction(&svm->vcpu);
3240 }
3241
3242 static int skinit_interception(struct vcpu_svm *svm)
3243 {
3244         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3245
3246         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3247         return 1;
3248 }
3249
3250 static int wbinvd_interception(struct vcpu_svm *svm)
3251 {
3252         return kvm_emulate_wbinvd(&svm->vcpu);
3253 }
3254
3255 static int xsetbv_interception(struct vcpu_svm *svm)
3256 {
3257         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3258         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3259
3260         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3261                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3262                 return kvm_skip_emulated_instruction(&svm->vcpu);
3263         }
3264
3265         return 1;
3266 }
3267
3268 static int task_switch_interception(struct vcpu_svm *svm)
3269 {
3270         u16 tss_selector;
3271         int reason;
3272         int int_type = svm->vmcb->control.exit_int_info &
3273                 SVM_EXITINTINFO_TYPE_MASK;
3274         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3275         uint32_t type =
3276                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3277         uint32_t idt_v =
3278                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3279         bool has_error_code = false;
3280         u32 error_code = 0;
3281
3282         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3283
3284         if (svm->vmcb->control.exit_info_2 &
3285             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3286                 reason = TASK_SWITCH_IRET;
3287         else if (svm->vmcb->control.exit_info_2 &
3288                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3289                 reason = TASK_SWITCH_JMP;
3290         else if (idt_v)
3291                 reason = TASK_SWITCH_GATE;
3292         else
3293                 reason = TASK_SWITCH_CALL;
3294
3295         if (reason == TASK_SWITCH_GATE) {
3296                 switch (type) {
3297                 case SVM_EXITINTINFO_TYPE_NMI:
3298                         svm->vcpu.arch.nmi_injected = false;
3299                         break;
3300                 case SVM_EXITINTINFO_TYPE_EXEPT:
3301                         if (svm->vmcb->control.exit_info_2 &
3302                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3303                                 has_error_code = true;
3304                                 error_code =
3305                                         (u32)svm->vmcb->control.exit_info_2;
3306                         }
3307                         kvm_clear_exception_queue(&svm->vcpu);
3308                         break;
3309                 case SVM_EXITINTINFO_TYPE_INTR:
3310                         kvm_clear_interrupt_queue(&svm->vcpu);
3311                         break;
3312                 default:
3313                         break;
3314                 }
3315         }
3316
3317         if (reason != TASK_SWITCH_GATE ||
3318             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3319             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3320              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3321                 skip_emulated_instruction(&svm->vcpu);
3322
3323         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3324                 int_vec = -1;
3325
3326         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3327                                 has_error_code, error_code) == EMULATE_FAIL) {
3328                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3329                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3330                 svm->vcpu.run->internal.ndata = 0;
3331                 return 0;
3332         }
3333         return 1;
3334 }
3335
3336 static int cpuid_interception(struct vcpu_svm *svm)
3337 {
3338         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3339         return kvm_emulate_cpuid(&svm->vcpu);
3340 }
3341
3342 static int iret_interception(struct vcpu_svm *svm)
3343 {
3344         ++svm->vcpu.stat.nmi_window_exits;
3345         clr_intercept(svm, INTERCEPT_IRET);
3346         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3347         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3348         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3349         return 1;
3350 }
3351
3352 static int invlpg_interception(struct vcpu_svm *svm)
3353 {
3354         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3355                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3356
3357         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3358         return kvm_skip_emulated_instruction(&svm->vcpu);
3359 }
3360
3361 static int emulate_on_interception(struct vcpu_svm *svm)
3362 {
3363         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3364 }
3365
3366 static int rdpmc_interception(struct vcpu_svm *svm)
3367 {
3368         int err;
3369
3370         if (!static_cpu_has(X86_FEATURE_NRIPS))
3371                 return emulate_on_interception(svm);
3372
3373         err = kvm_rdpmc(&svm->vcpu);
3374         return kvm_complete_insn_gp(&svm->vcpu, err);
3375 }
3376
3377 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3378                                             unsigned long val)
3379 {
3380         unsigned long cr0 = svm->vcpu.arch.cr0;
3381         bool ret = false;
3382         u64 intercept;
3383
3384         intercept = svm->nested.intercept;
3385
3386         if (!is_guest_mode(&svm->vcpu) ||
3387             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3388                 return false;
3389
3390         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3391         val &= ~SVM_CR0_SELECTIVE_MASK;
3392
3393         if (cr0 ^ val) {
3394                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3395                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3396         }
3397
3398         return ret;
3399 }
3400
3401 #define CR_VALID (1ULL << 63)
3402
3403 static int cr_interception(struct vcpu_svm *svm)
3404 {
3405         int reg, cr;
3406         unsigned long val;
3407         int err;
3408
3409         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3410                 return emulate_on_interception(svm);
3411
3412         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3413                 return emulate_on_interception(svm);
3414
3415         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3416         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3417                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3418         else
3419                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3420
3421         err = 0;
3422         if (cr >= 16) { /* mov to cr */
3423                 cr -= 16;
3424                 val = kvm_register_read(&svm->vcpu, reg);
3425                 switch (cr) {
3426                 case 0:
3427                         if (!check_selective_cr0_intercepted(svm, val))
3428                                 err = kvm_set_cr0(&svm->vcpu, val);
3429                         else
3430                                 return 1;
3431
3432                         break;
3433                 case 3:
3434                         err = kvm_set_cr3(&svm->vcpu, val);
3435                         break;
3436                 case 4:
3437                         err = kvm_set_cr4(&svm->vcpu, val);
3438                         break;
3439                 case 8:
3440                         err = kvm_set_cr8(&svm->vcpu, val);
3441                         break;
3442                 default:
3443                         WARN(1, "unhandled write to CR%d", cr);
3444                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3445                         return 1;
3446                 }
3447         } else { /* mov from cr */
3448                 switch (cr) {
3449                 case 0:
3450                         val = kvm_read_cr0(&svm->vcpu);
3451                         break;
3452                 case 2:
3453                         val = svm->vcpu.arch.cr2;
3454                         break;
3455                 case 3:
3456                         val = kvm_read_cr3(&svm->vcpu);
3457                         break;
3458                 case 4:
3459                         val = kvm_read_cr4(&svm->vcpu);
3460                         break;
3461                 case 8:
3462                         val = kvm_get_cr8(&svm->vcpu);
3463                         break;
3464                 default:
3465                         WARN(1, "unhandled read from CR%d", cr);
3466                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3467                         return 1;
3468                 }
3469                 kvm_register_write(&svm->vcpu, reg, val);
3470         }
3471         return kvm_complete_insn_gp(&svm->vcpu, err);
3472 }
3473
3474 static int dr_interception(struct vcpu_svm *svm)
3475 {
3476         int reg, dr;
3477         unsigned long val;
3478
3479         if (svm->vcpu.guest_debug == 0) {
3480                 /*
3481                  * No more DR vmexits; force a reload of the debug registers
3482                  * and reenter on this instruction.  The next vmexit will
3483                  * retrieve the full state of the debug registers.
3484                  */
3485                 clr_dr_intercepts(svm);
3486                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3487                 return 1;
3488         }
3489
3490         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3491                 return emulate_on_interception(svm);
3492
3493         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3494         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3495
3496         if (dr >= 16) { /* mov to DRn */
3497                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3498                         return 1;
3499                 val = kvm_register_read(&svm->vcpu, reg);
3500                 kvm_set_dr(&svm->vcpu, dr - 16, val);
3501         } else {
3502                 if (!kvm_require_dr(&svm->vcpu, dr))
3503                         return 1;
3504                 kvm_get_dr(&svm->vcpu, dr, &val);
3505                 kvm_register_write(&svm->vcpu, reg, val);
3506         }
3507
3508         return kvm_skip_emulated_instruction(&svm->vcpu);
3509 }
3510
3511 static int cr8_write_interception(struct vcpu_svm *svm)
3512 {
3513         struct kvm_run *kvm_run = svm->vcpu.run;
3514         int r;
3515
3516         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3517         /* instruction emulation calls kvm_set_cr8() */
3518         r = cr_interception(svm);
3519         if (lapic_in_kernel(&svm->vcpu))
3520                 return r;
3521         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3522                 return r;
3523         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3524         return 0;
3525 }
3526
3527 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3528 {
3529         struct vcpu_svm *svm = to_svm(vcpu);
3530
3531         switch (msr_info->index) {
3532         case MSR_IA32_TSC: {
3533                 msr_info->data = svm->vmcb->control.tsc_offset +
3534                         kvm_scale_tsc(vcpu, rdtsc());
3535
3536                 break;
3537         }
3538         case MSR_STAR:
3539                 msr_info->data = svm->vmcb->save.star;
3540                 break;
3541 #ifdef CONFIG_X86_64
3542         case MSR_LSTAR:
3543                 msr_info->data = svm->vmcb->save.lstar;
3544                 break;
3545         case MSR_CSTAR:
3546                 msr_info->data = svm->vmcb->save.cstar;
3547                 break;
3548         case MSR_KERNEL_GS_BASE:
3549                 msr_info->data = svm->vmcb->save.kernel_gs_base;
3550                 break;
3551         case MSR_SYSCALL_MASK:
3552                 msr_info->data = svm->vmcb->save.sfmask;
3553                 break;
3554 #endif
3555         case MSR_IA32_SYSENTER_CS:
3556                 msr_info->data = svm->vmcb->save.sysenter_cs;
3557                 break;
3558         case MSR_IA32_SYSENTER_EIP:
3559                 msr_info->data = svm->sysenter_eip;
3560                 break;
3561         case MSR_IA32_SYSENTER_ESP:
3562                 msr_info->data = svm->sysenter_esp;
3563                 break;
3564         case MSR_TSC_AUX:
3565                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3566                         return 1;
3567                 msr_info->data = svm->tsc_aux;
3568                 break;
3569         /*
3570          * Nobody will change the following 5 values in the VMCB so we can
3571          * safely return them on rdmsr. They will always be 0 until LBRV is
3572          * implemented.
3573          */
3574         case MSR_IA32_DEBUGCTLMSR:
3575                 msr_info->data = svm->vmcb->save.dbgctl;
3576                 break;
3577         case MSR_IA32_LASTBRANCHFROMIP:
3578                 msr_info->data = svm->vmcb->save.br_from;
3579                 break;
3580         case MSR_IA32_LASTBRANCHTOIP:
3581                 msr_info->data = svm->vmcb->save.br_to;
3582                 break;
3583         case MSR_IA32_LASTINTFROMIP:
3584                 msr_info->data = svm->vmcb->save.last_excp_from;
3585                 break;
3586         case MSR_IA32_LASTINTTOIP:
3587                 msr_info->data = svm->vmcb->save.last_excp_to;
3588                 break;
3589         case MSR_VM_HSAVE_PA:
3590                 msr_info->data = svm->nested.hsave_msr;
3591                 break;
3592         case MSR_VM_CR:
3593                 msr_info->data = svm->nested.vm_cr_msr;
3594                 break;
3595         case MSR_IA32_UCODE_REV:
3596                 msr_info->data = 0x01000065;
3597                 break;
3598         case MSR_F15H_IC_CFG: {
3599
3600                 int family, model;
3601
3602                 family = guest_cpuid_family(vcpu);
3603                 model  = guest_cpuid_model(vcpu);
3604
3605                 if (family < 0 || model < 0)
3606                         return kvm_get_msr_common(vcpu, msr_info);
3607
3608                 msr_info->data = 0;
3609
3610                 if (family == 0x15 &&
3611                     (model >= 0x2 && model < 0x20))
3612                         msr_info->data = 0x1E;
3613                 }
3614                 break;
3615         default:
3616                 return kvm_get_msr_common(vcpu, msr_info);
3617         }
3618         return 0;
3619 }
3620
3621 static int rdmsr_interception(struct vcpu_svm *svm)
3622 {
3623         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3624         struct msr_data msr_info;
3625
3626         msr_info.index = ecx;
3627         msr_info.host_initiated = false;
3628         if (svm_get_msr(&svm->vcpu, &msr_info)) {
3629                 trace_kvm_msr_read_ex(ecx);
3630                 kvm_inject_gp(&svm->vcpu, 0);
3631                 return 1;
3632         } else {
3633                 trace_kvm_msr_read(ecx, msr_info.data);
3634
3635                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3636                                    msr_info.data & 0xffffffff);
3637                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3638                                    msr_info.data >> 32);
3639                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3640                 return kvm_skip_emulated_instruction(&svm->vcpu);
3641         }
3642 }
3643
3644 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3645 {
3646         struct vcpu_svm *svm = to_svm(vcpu);
3647         int svm_dis, chg_mask;
3648
3649         if (data & ~SVM_VM_CR_VALID_MASK)
3650                 return 1;
3651
3652         chg_mask = SVM_VM_CR_VALID_MASK;
3653
3654         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3655                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3656
3657         svm->nested.vm_cr_msr &= ~chg_mask;
3658         svm->nested.vm_cr_msr |= (data & chg_mask);
3659
3660         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3661
3662         /* check for svm_disable while efer.svme is set */
3663         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3664                 return 1;
3665
3666         return 0;
3667 }
3668
3669 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3670 {
3671         struct vcpu_svm *svm = to_svm(vcpu);
3672
3673         u32 ecx = msr->index;
3674         u64 data = msr->data;
3675         switch (ecx) {
3676         case MSR_IA32_CR_PAT:
3677                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3678                         return 1;
3679                 vcpu->arch.pat = data;
3680                 svm->vmcb->save.g_pat = data;
3681                 mark_dirty(svm->vmcb, VMCB_NPT);
3682                 break;
3683         case MSR_IA32_TSC:
3684                 kvm_write_tsc(vcpu, msr);
3685                 break;
3686         case MSR_STAR:
3687                 svm->vmcb->save.star = data;
3688                 break;
3689 #ifdef CONFIG_X86_64
3690         case MSR_LSTAR:
3691                 svm->vmcb->save.lstar = data;
3692                 break;
3693         case MSR_CSTAR:
3694                 svm->vmcb->save.cstar = data;
3695                 break;
3696         case MSR_KERNEL_GS_BASE:
3697                 svm->vmcb->save.kernel_gs_base = data;
3698                 break;
3699         case MSR_SYSCALL_MASK:
3700                 svm->vmcb->save.sfmask = data;
3701                 break;
3702 #endif
3703         case MSR_IA32_SYSENTER_CS:
3704                 svm->vmcb->save.sysenter_cs = data;
3705                 break;
3706         case MSR_IA32_SYSENTER_EIP:
3707                 svm->sysenter_eip = data;
3708                 svm->vmcb->save.sysenter_eip = data;
3709                 break;
3710         case MSR_IA32_SYSENTER_ESP:
3711                 svm->sysenter_esp = data;
3712                 svm->vmcb->save.sysenter_esp = data;
3713                 break;
3714         case MSR_TSC_AUX:
3715                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3716                         return 1;
3717
3718                 /*
3719                  * This is rare, so we update the MSR here instead of using
3720                  * direct_access_msrs.  Doing that would require a rdmsr in
3721                  * svm_vcpu_put.
3722                  */
3723                 svm->tsc_aux = data;
3724                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3725                 break;
3726         case MSR_IA32_DEBUGCTLMSR:
3727                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3728                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3729                                     __func__, data);
3730                         break;
3731                 }
3732                 if (data & DEBUGCTL_RESERVED_BITS)
3733                         return 1;
3734
3735                 svm->vmcb->save.dbgctl = data;
3736                 mark_dirty(svm->vmcb, VMCB_LBR);
3737                 if (data & (1ULL<<0))
3738                         svm_enable_lbrv(svm);
3739                 else
3740                         svm_disable_lbrv(svm);
3741                 break;
3742         case MSR_VM_HSAVE_PA:
3743                 svm->nested.hsave_msr = data;
3744                 break;
3745         case MSR_VM_CR:
3746                 return svm_set_vm_cr(vcpu, data);
3747         case MSR_VM_IGNNE:
3748                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3749                 break;
3750         case MSR_IA32_APICBASE:
3751                 if (kvm_vcpu_apicv_active(vcpu))
3752                         avic_update_vapic_bar(to_svm(vcpu), data);
3753                 /* Follow through */
3754         default:
3755                 return kvm_set_msr_common(vcpu, msr);
3756         }
3757         return 0;
3758 }
3759
3760 static int wrmsr_interception(struct vcpu_svm *svm)
3761 {
3762         struct msr_data msr;
3763         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3764         u64 data = kvm_read_edx_eax(&svm->vcpu);
3765
3766         msr.data = data;
3767         msr.index = ecx;
3768         msr.host_initiated = false;
3769
3770         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3771         if (kvm_set_msr(&svm->vcpu, &msr)) {
3772                 trace_kvm_msr_write_ex(ecx, data);
3773                 kvm_inject_gp(&svm->vcpu, 0);
3774                 return 1;
3775         } else {
3776                 trace_kvm_msr_write(ecx, data);
3777                 return kvm_skip_emulated_instruction(&svm->vcpu);
3778         }
3779 }
3780
3781 static int msr_interception(struct vcpu_svm *svm)
3782 {
3783         if (svm->vmcb->control.exit_info_1)
3784                 return wrmsr_interception(svm);
3785         else
3786                 return rdmsr_interception(svm);
3787 }
3788
3789 static int interrupt_window_interception(struct vcpu_svm *svm)
3790 {
3791         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3792         svm_clear_vintr(svm);
3793         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3794         mark_dirty(svm->vmcb, VMCB_INTR);
3795         ++svm->vcpu.stat.irq_window_exits;
3796         return 1;
3797 }
3798
3799 static int pause_interception(struct vcpu_svm *svm)
3800 {
3801         struct kvm_vcpu *vcpu = &svm->vcpu;
3802         bool in_kernel = (svm_get_cpl(vcpu) == 0);
3803
3804         kvm_vcpu_on_spin(vcpu, in_kernel);
3805         return 1;
3806 }
3807
3808 static int nop_interception(struct vcpu_svm *svm)
3809 {
3810         return kvm_skip_emulated_instruction(&(svm->vcpu));
3811 }
3812
3813 static int monitor_interception(struct vcpu_svm *svm)
3814 {
3815         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3816         return nop_interception(svm);
3817 }
3818
3819 static int mwait_interception(struct vcpu_svm *svm)
3820 {
3821         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3822         return nop_interception(svm);
3823 }
3824
3825 enum avic_ipi_failure_cause {
3826         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3827         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3828         AVIC_IPI_FAILURE_INVALID_TARGET,
3829         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3830 };
3831
3832 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3833 {
3834         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3835         u32 icrl = svm->vmcb->control.exit_info_1;
3836         u32 id = svm->vmcb->control.exit_info_2 >> 32;
3837         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3838         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3839
3840         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3841
3842         switch (id) {
3843         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3844                 /*
3845                  * AVIC hardware handles the generation of
3846                  * IPIs when the specified Message Type is Fixed
3847                  * (also known as fixed delivery mode) and
3848                  * the Trigger Mode is edge-triggered. The hardware
3849                  * also supports self and broadcast delivery modes
3850                  * specified via the Destination Shorthand(DSH)
3851                  * field of the ICRL. Logical and physical APIC ID
3852                  * formats are supported. All other IPI types cause
3853                  * a #VMEXIT, which needs to emulated.
3854                  */
3855                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3856                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3857                 break;
3858         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3859                 int i;
3860                 struct kvm_vcpu *vcpu;
3861                 struct kvm *kvm = svm->vcpu.kvm;
3862                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3863
3864                 /*
3865                  * At this point, we expect that the AVIC HW has already
3866                  * set the appropriate IRR bits on the valid target
3867                  * vcpus. So, we just need to kick the appropriate vcpu.
3868                  */
3869                 kvm_for_each_vcpu(i, vcpu, kvm) {
3870                         bool m = kvm_apic_match_dest(vcpu, apic,
3871                                                      icrl & KVM_APIC_SHORT_MASK,
3872                                                      GET_APIC_DEST_FIELD(icrh),
3873                                                      icrl & KVM_APIC_DEST_MASK);
3874
3875                         if (m && !avic_vcpu_is_running(vcpu))
3876                                 kvm_vcpu_wake_up(vcpu);
3877                 }
3878                 break;
3879         }
3880         case AVIC_IPI_FAILURE_INVALID_TARGET:
3881                 break;
3882         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3883                 WARN_ONCE(1, "Invalid backing page\n");
3884                 break;
3885         default:
3886                 pr_err("Unknown IPI interception\n");
3887         }
3888
3889         return 1;
3890 }
3891
3892 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3893 {
3894         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3895         int index;
3896         u32 *logical_apic_id_table;
3897         int dlid = GET_APIC_LOGICAL_ID(ldr);
3898
3899         if (!dlid)
3900                 return NULL;
3901
3902         if (flat) { /* flat */
3903                 index = ffs(dlid) - 1;
3904                 if (index > 7)
3905                         return NULL;
3906         } else { /* cluster */
3907                 int cluster = (dlid & 0xf0) >> 4;
3908                 int apic = ffs(dlid & 0x0f) - 1;
3909
3910                 if ((apic < 0) || (apic > 7) ||
3911                     (cluster >= 0xf))
3912                         return NULL;
3913                 index = (cluster << 2) + apic;
3914         }
3915
3916         logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3917
3918         return &logical_apic_id_table[index];
3919 }
3920
3921 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3922                           bool valid)
3923 {
3924         bool flat;
3925         u32 *entry, new_entry;
3926
3927         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3928         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3929         if (!entry)
3930                 return -EINVAL;
3931
3932         new_entry = READ_ONCE(*entry);
3933         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3934         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3935         if (valid)
3936                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3937         else
3938                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3939         WRITE_ONCE(*entry, new_entry);
3940
3941         return 0;
3942 }
3943
3944 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3945 {
3946         int ret;
3947         struct vcpu_svm *svm = to_svm(vcpu);
3948         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3949
3950         if (!ldr)
3951                 return 1;
3952
3953         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3954         if (ret && svm->ldr_reg) {
3955                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3956                 svm->ldr_reg = 0;
3957         } else {
3958                 svm->ldr_reg = ldr;
3959         }
3960         return ret;
3961 }
3962
3963 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3964 {
3965         u64 *old, *new;
3966         struct vcpu_svm *svm = to_svm(vcpu);
3967         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3968         u32 id = (apic_id_reg >> 24) & 0xff;
3969
3970         if (vcpu->vcpu_id == id)
3971                 return 0;
3972
3973         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3974         new = avic_get_physical_id_entry(vcpu, id);
3975         if (!new || !old)
3976                 return 1;
3977
3978         /* We need to move physical_id_entry to new offset */
3979         *new = *old;
3980         *old = 0ULL;
3981         to_svm(vcpu)->avic_physical_id_cache = new;
3982
3983         /*
3984          * Also update the guest physical APIC ID in the logical
3985          * APIC ID table entry if already setup the LDR.
3986          */
3987         if (svm->ldr_reg)
3988                 avic_handle_ldr_update(vcpu);
3989
3990         return 0;
3991 }
3992
3993 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3994 {
3995         struct vcpu_svm *svm = to_svm(vcpu);
3996         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3997         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3998         u32 mod = (dfr >> 28) & 0xf;
3999
4000         /*
4001          * We assume that all local APICs are using the same type.
4002          * If this changes, we need to flush the AVIC logical
4003          * APID id table.
4004          */
4005         if (vm_data->ldr_mode == mod)
4006                 return 0;
4007
4008         clear_page(page_address(vm_data->avic_logical_id_table_page));
4009         vm_data->ldr_mode = mod;
4010
4011         if (svm->ldr_reg)
4012                 avic_handle_ldr_update(vcpu);
4013         return 0;
4014 }
4015
4016 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4017 {
4018         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4019         u32 offset = svm->vmcb->control.exit_info_1 &
4020                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4021
4022         switch (offset) {
4023         case APIC_ID:
4024                 if (avic_handle_apic_id_update(&svm->vcpu))
4025                         return 0;
4026                 break;
4027         case APIC_LDR:
4028                 if (avic_handle_ldr_update(&svm->vcpu))
4029                         return 0;
4030                 break;
4031         case APIC_DFR:
4032                 avic_handle_dfr_update(&svm->vcpu);
4033                 break;
4034         default:
4035                 break;
4036         }
4037
4038         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4039
4040         return 1;
4041 }
4042
4043 static bool is_avic_unaccelerated_access_trap(u32 offset)
4044 {
4045         bool ret = false;
4046
4047         switch (offset) {
4048         case APIC_ID:
4049         case APIC_EOI:
4050         case APIC_RRR:
4051         case APIC_LDR:
4052         case APIC_DFR:
4053         case APIC_SPIV:
4054         case APIC_ESR:
4055         case APIC_ICR:
4056         case APIC_LVTT:
4057         case APIC_LVTTHMR:
4058         case APIC_LVTPC:
4059         case APIC_LVT0:
4060         case APIC_LVT1:
4061         case APIC_LVTERR:
4062         case APIC_TMICT:
4063         case APIC_TDCR:
4064                 ret = true;
4065                 break;
4066         default:
4067                 break;
4068         }
4069         return ret;
4070 }
4071
4072 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4073 {
4074         int ret = 0;
4075         u32 offset = svm->vmcb->control.exit_info_1 &
4076                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4077         u32 vector = svm->vmcb->control.exit_info_2 &
4078                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4079         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4080                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4081         bool trap = is_avic_unaccelerated_access_trap(offset);
4082
4083         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4084                                             trap, write, vector);
4085         if (trap) {
4086                 /* Handling Trap */
4087                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4088                 ret = avic_unaccel_trap_write(svm);
4089         } else {
4090                 /* Handling Fault */
4091                 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4092         }
4093
4094         return ret;
4095 }
4096
4097 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4098         [SVM_EXIT_READ_CR0]                     = cr_interception,
4099         [SVM_EXIT_READ_CR3]                     = cr_interception,
4100         [SVM_EXIT_READ_CR4]                     = cr_interception,
4101         [SVM_EXIT_READ_CR8]                     = cr_interception,
4102         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4103         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4104         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4105         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4106         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4107         [SVM_EXIT_READ_DR0]                     = dr_interception,
4108         [SVM_EXIT_READ_DR1]                     = dr_interception,
4109         [SVM_EXIT_READ_DR2]                     = dr_interception,
4110         [SVM_EXIT_READ_DR3]                     = dr_interception,
4111         [SVM_EXIT_READ_DR4]                     = dr_interception,
4112         [SVM_EXIT_READ_DR5]                     = dr_interception,
4113         [SVM_EXIT_READ_DR6]                     = dr_interception,
4114         [SVM_EXIT_READ_DR7]                     = dr_interception,
4115         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4116         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4117         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4118         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4119         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4120         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4121         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4122         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4123         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4124         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4125         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4126         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4127         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4128         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4129         [SVM_EXIT_INTR]                         = intr_interception,
4130         [SVM_EXIT_NMI]                          = nmi_interception,
4131         [SVM_EXIT_SMI]                          = nop_on_interception,
4132         [SVM_EXIT_INIT]                         = nop_on_interception,
4133         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4134         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4135         [SVM_EXIT_CPUID]                        = cpuid_interception,
4136         [SVM_EXIT_IRET]                         = iret_interception,
4137         [SVM_EXIT_INVD]                         = emulate_on_interception,
4138         [SVM_EXIT_PAUSE]                        = pause_interception,
4139         [SVM_EXIT_HLT]                          = halt_interception,
4140         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4141         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4142         [SVM_EXIT_IOIO]                         = io_interception,
4143         [SVM_EXIT_MSR]                          = msr_interception,
4144         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4145         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4146         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4147         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4148         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4149         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4150         [SVM_EXIT_STGI]                         = stgi_interception,
4151         [SVM_EXIT_CLGI]                         = clgi_interception,
4152         [SVM_EXIT_SKINIT]                       = skinit_interception,
4153         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4154         [SVM_EXIT_MONITOR]                      = monitor_interception,
4155         [SVM_EXIT_MWAIT]                        = mwait_interception,
4156         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4157         [SVM_EXIT_NPF]                          = npf_interception,
4158         [SVM_EXIT_RSM]                          = emulate_on_interception,
4159         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4160         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4161 };
4162
4163 static void dump_vmcb(struct kvm_vcpu *vcpu)
4164 {
4165         struct vcpu_svm *svm = to_svm(vcpu);
4166         struct vmcb_control_area *control = &svm->vmcb->control;
4167         struct vmcb_save_area *save = &svm->vmcb->save;
4168
4169         pr_err("VMCB Control Area:\n");
4170         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4171         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4172         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4173         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4174         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4175         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4176         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4177         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4178         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4179         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4180         pr_err("%-20s%d\n", "asid:", control->asid);
4181         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4182         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4183         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4184         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4185         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4186         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4187         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4188         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4189         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4190         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4191         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4192         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4193         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4194         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4195         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4196         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4197         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4198         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4199         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4200         pr_err("VMCB State Save Area:\n");
4201         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4202                "es:",
4203                save->es.selector, save->es.attrib,
4204                save->es.limit, save->es.base);
4205         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4206                "cs:",
4207                save->cs.selector, save->cs.attrib,
4208                save->cs.limit, save->cs.base);
4209         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4210                "ss:",
4211                save->ss.selector, save->ss.attrib,
4212                save->ss.limit, save->ss.base);
4213         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4214                "ds:",
4215                save->ds.selector, save->ds.attrib,
4216                save->ds.limit, save->ds.base);
4217         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4218                "fs:",
4219                save->fs.selector, save->fs.attrib,
4220                save->fs.limit, save->fs.base);
4221         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4222                "gs:",
4223                save->gs.selector, save->gs.attrib,
4224                save->gs.limit, save->gs.base);
4225         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4226                "gdtr:",
4227                save->gdtr.selector, save->gdtr.attrib,
4228                save->gdtr.limit, save->gdtr.base);
4229         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4230                "ldtr:",
4231                save->ldtr.selector, save->ldtr.attrib,
4232                save->ldtr.limit, save->ldtr.base);
4233         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4234                "idtr:",
4235                save->idtr.selector, save->idtr.attrib,
4236                save->idtr.limit, save->idtr.base);
4237         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4238                "tr:",
4239                save->tr.selector, save->tr.attrib,
4240                save->tr.limit, save->tr.base);
4241         pr_err("cpl:            %d                efer:         %016llx\n",
4242                 save->cpl, save->efer);
4243         pr_err("%-15s %016llx %-13s %016llx\n",
4244                "cr0:", save->cr0, "cr2:", save->cr2);
4245         pr_err("%-15s %016llx %-13s %016llx\n",
4246                "cr3:", save->cr3, "cr4:", save->cr4);
4247         pr_err("%-15s %016llx %-13s %016llx\n",
4248                "dr6:", save->dr6, "dr7:", save->dr7);
4249         pr_err("%-15s %016llx %-13s %016llx\n",
4250                "rip:", save->rip, "rflags:", save->rflags);
4251         pr_err("%-15s %016llx %-13s %016llx\n",
4252                "rsp:", save->rsp, "rax:", save->rax);
4253         pr_err("%-15s %016llx %-13s %016llx\n",
4254                "star:", save->star, "lstar:", save->lstar);
4255         pr_err("%-15s %016llx %-13s %016llx\n",
4256                "cstar:", save->cstar, "sfmask:", save->sfmask);
4257         pr_err("%-15s %016llx %-13s %016llx\n",
4258                "kernel_gs_base:", save->kernel_gs_base,
4259                "sysenter_cs:", save->sysenter_cs);
4260         pr_err("%-15s %016llx %-13s %016llx\n",
4261                "sysenter_esp:", save->sysenter_esp,
4262                "sysenter_eip:", save->sysenter_eip);
4263         pr_err("%-15s %016llx %-13s %016llx\n",
4264                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4265         pr_err("%-15s %016llx %-13s %016llx\n",
4266                "br_from:", save->br_from, "br_to:", save->br_to);
4267         pr_err("%-15s %016llx %-13s %016llx\n",
4268                "excp_from:", save->last_excp_from,
4269                "excp_to:", save->last_excp_to);
4270 }
4271
4272 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4273 {
4274         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4275
4276         *info1 = control->exit_info_1;
4277         *info2 = control->exit_info_2;
4278 }
4279
4280 static int handle_exit(struct kvm_vcpu *vcpu)
4281 {
4282         struct vcpu_svm *svm = to_svm(vcpu);
4283         struct kvm_run *kvm_run = vcpu->run;
4284         u32 exit_code = svm->vmcb->control.exit_code;
4285
4286         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4287
4288         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4289                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4290         if (npt_enabled)
4291                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4292
4293         if (unlikely(svm->nested.exit_required)) {
4294                 nested_svm_vmexit(svm);
4295                 svm->nested.exit_required = false;
4296
4297                 return 1;
4298         }
4299
4300         if (is_guest_mode(vcpu)) {
4301                 int vmexit;
4302
4303                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4304                                         svm->vmcb->control.exit_info_1,
4305                                         svm->vmcb->control.exit_info_2,
4306                                         svm->vmcb->control.exit_int_info,
4307                                         svm->vmcb->control.exit_int_info_err,
4308                                         KVM_ISA_SVM);
4309
4310                 vmexit = nested_svm_exit_special(svm);
4311
4312                 if (vmexit == NESTED_EXIT_CONTINUE)
4313                         vmexit = nested_svm_exit_handled(svm);
4314
4315                 if (vmexit == NESTED_EXIT_DONE)
4316                         return 1;
4317         }
4318
4319         svm_complete_interrupts(svm);
4320
4321         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4322                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4323                 kvm_run->fail_entry.hardware_entry_failure_reason
4324                         = svm->vmcb->control.exit_code;
4325                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4326                 dump_vmcb(vcpu);
4327                 return 0;
4328         }
4329
4330         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4331             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4332             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4333             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4334                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4335                        "exit_code 0x%x\n",
4336                        __func__, svm->vmcb->control.exit_int_info,
4337                        exit_code);
4338
4339         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4340             || !svm_exit_handlers[exit_code]) {
4341                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4342                 kvm_queue_exception(vcpu, UD_VECTOR);
4343                 return 1;
4344         }
4345
4346         return svm_exit_handlers[exit_code](svm);
4347 }
4348
4349 static void reload_tss(struct kvm_vcpu *vcpu)
4350 {
4351         int cpu = raw_smp_processor_id();
4352
4353         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4354         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4355         load_TR_desc();
4356 }
4357
4358 static void pre_svm_run(struct vcpu_svm *svm)
4359 {
4360         int cpu = raw_smp_processor_id();
4361
4362         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4363
4364         /* FIXME: handle wraparound of asid_generation */
4365         if (svm->asid_generation != sd->asid_generation)
4366                 new_asid(svm, sd);
4367 }
4368
4369 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4370 {
4371         struct vcpu_svm *svm = to_svm(vcpu);
4372
4373         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4374         vcpu->arch.hflags |= HF_NMI_MASK;
4375         set_intercept(svm, INTERCEPT_IRET);
4376         ++vcpu->stat.nmi_injections;
4377 }
4378
4379 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4380 {
4381         struct vmcb_control_area *control;
4382
4383         /* The following fields are ignored when AVIC is enabled */
4384         control = &svm->vmcb->control;
4385         control->int_vector = irq;
4386         control->int_ctl &= ~V_INTR_PRIO_MASK;
4387         control->int_ctl |= V_IRQ_MASK |
4388                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4389         mark_dirty(svm->vmcb, VMCB_INTR);
4390 }
4391
4392 static void svm_set_irq(struct kvm_vcpu *vcpu)
4393 {
4394         struct vcpu_svm *svm = to_svm(vcpu);
4395
4396         BUG_ON(!(gif_set(svm)));
4397
4398         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4399         ++vcpu->stat.irq_injections;
4400
4401         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4402                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4403 }
4404
4405 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4406 {
4407         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4408 }
4409
4410 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4411 {
4412         struct vcpu_svm *svm = to_svm(vcpu);
4413
4414         if (svm_nested_virtualize_tpr(vcpu) ||
4415             kvm_vcpu_apicv_active(vcpu))
4416                 return;
4417
4418         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4419
4420         if (irr == -1)
4421                 return;
4422
4423         if (tpr >= irr)
4424                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4425 }
4426
4427 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4428 {
4429         return;
4430 }
4431
4432 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
4433 {
4434         return avic && irqchip_split(vcpu->kvm);
4435 }
4436
4437 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4438 {
4439 }
4440
4441 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4442 {
4443 }
4444
4445 /* Note: Currently only used by Hyper-V. */
4446 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4447 {
4448         struct vcpu_svm *svm = to_svm(vcpu);
4449         struct vmcb *vmcb = svm->vmcb;
4450
4451         if (!kvm_vcpu_apicv_active(&svm->vcpu))
4452                 return;
4453
4454         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4455         mark_dirty(vmcb, VMCB_INTR);
4456 }
4457
4458 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4459 {
4460         return;
4461 }
4462
4463 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4464 {
4465         kvm_lapic_set_irr(vec, vcpu->arch.apic);
4466         smp_mb__after_atomic();
4467
4468         if (avic_vcpu_is_running(vcpu))
4469                 wrmsrl(SVM_AVIC_DOORBELL,
4470                        kvm_cpu_get_apicid(vcpu->cpu));
4471         else
4472                 kvm_vcpu_wake_up(vcpu);
4473 }
4474
4475 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4476 {
4477         unsigned long flags;
4478         struct amd_svm_iommu_ir *cur;
4479
4480         spin_lock_irqsave(&svm->ir_list_lock, flags);
4481         list_for_each_entry(cur, &svm->ir_list, node) {
4482                 if (cur->data != pi->ir_data)
4483                         continue;
4484                 list_del(&cur->node);
4485                 kfree(cur);
4486                 break;
4487         }
4488         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4489 }
4490
4491 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4492 {
4493         int ret = 0;
4494         unsigned long flags;
4495         struct amd_svm_iommu_ir *ir;
4496
4497         /**
4498          * In some cases, the existing irte is updaed and re-set,
4499          * so we need to check here if it's already been * added
4500          * to the ir_list.
4501          */
4502         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4503                 struct kvm *kvm = svm->vcpu.kvm;
4504                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4505                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4506                 struct vcpu_svm *prev_svm;
4507
4508                 if (!prev_vcpu) {
4509                         ret = -EINVAL;
4510                         goto out;
4511                 }
4512
4513                 prev_svm = to_svm(prev_vcpu);
4514                 svm_ir_list_del(prev_svm, pi);
4515         }
4516
4517         /**
4518          * Allocating new amd_iommu_pi_data, which will get
4519          * add to the per-vcpu ir_list.
4520          */
4521         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4522         if (!ir) {
4523                 ret = -ENOMEM;
4524                 goto out;
4525         }
4526         ir->data = pi->ir_data;
4527
4528         spin_lock_irqsave(&svm->ir_list_lock, flags);
4529         list_add(&ir->node, &svm->ir_list);
4530         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4531 out:
4532         return ret;
4533 }
4534
4535 /**
4536  * Note:
4537  * The HW cannot support posting multicast/broadcast
4538  * interrupts to a vCPU. So, we still use legacy interrupt
4539  * remapping for these kind of interrupts.
4540  *
4541  * For lowest-priority interrupts, we only support
4542  * those with single CPU as the destination, e.g. user
4543  * configures the interrupts via /proc/irq or uses
4544  * irqbalance to make the interrupts single-CPU.
4545  */
4546 static int
4547 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4548                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4549 {
4550         struct kvm_lapic_irq irq;
4551         struct kvm_vcpu *vcpu = NULL;
4552
4553         kvm_set_msi_irq(kvm, e, &irq);
4554
4555         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4556                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4557                          __func__, irq.vector);
4558                 return -1;
4559         }
4560
4561         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4562                  irq.vector);
4563         *svm = to_svm(vcpu);
4564         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
4565         vcpu_info->vector = irq.vector;
4566
4567         return 0;
4568 }
4569
4570 /*
4571  * svm_update_pi_irte - set IRTE for Posted-Interrupts
4572  *
4573  * @kvm: kvm
4574  * @host_irq: host irq of the interrupt
4575  * @guest_irq: gsi of the interrupt
4576  * @set: set or unset PI
4577  * returns 0 on success, < 0 on failure
4578  */
4579 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4580                               uint32_t guest_irq, bool set)
4581 {
4582         struct kvm_kernel_irq_routing_entry *e;
4583         struct kvm_irq_routing_table *irq_rt;
4584         int idx, ret = -EINVAL;
4585
4586         if (!kvm_arch_has_assigned_device(kvm) ||
4587             !irq_remapping_cap(IRQ_POSTING_CAP))
4588                 return 0;
4589
4590         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4591                  __func__, host_irq, guest_irq, set);
4592
4593         idx = srcu_read_lock(&kvm->irq_srcu);
4594         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4595         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4596
4597         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4598                 struct vcpu_data vcpu_info;
4599                 struct vcpu_svm *svm = NULL;
4600
4601                 if (e->type != KVM_IRQ_ROUTING_MSI)
4602                         continue;
4603
4604                 /**
4605                  * Here, we setup with legacy mode in the following cases:
4606                  * 1. When cannot target interrupt to a specific vcpu.
4607                  * 2. Unsetting posted interrupt.
4608                  * 3. APIC virtialization is disabled for the vcpu.
4609                  */
4610                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4611                     kvm_vcpu_apicv_active(&svm->vcpu)) {
4612                         struct amd_iommu_pi_data pi;
4613
4614                         /* Try to enable guest_mode in IRTE */
4615                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
4616                                             AVIC_HPA_MASK);
4617                         pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4618                                                      svm->vcpu.vcpu_id);
4619                         pi.is_guest_mode = true;
4620                         pi.vcpu_data = &vcpu_info;
4621                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4622
4623                         /**
4624                          * Here, we successfully setting up vcpu affinity in
4625                          * IOMMU guest mode. Now, we need to store the posted
4626                          * interrupt information in a per-vcpu ir_list so that
4627                          * we can reference to them directly when we update vcpu
4628                          * scheduling information in IOMMU irte.
4629                          */
4630                         if (!ret && pi.is_guest_mode)
4631                                 svm_ir_list_add(svm, &pi);
4632                 } else {
4633                         /* Use legacy mode in IRTE */
4634                         struct amd_iommu_pi_data pi;
4635
4636                         /**
4637                          * Here, pi is used to:
4638                          * - Tell IOMMU to use legacy mode for this interrupt.
4639                          * - Retrieve ga_tag of prior interrupt remapping data.
4640                          */
4641                         pi.is_guest_mode = false;
4642                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4643
4644                         /**
4645                          * Check if the posted interrupt was previously
4646                          * setup with the guest_mode by checking if the ga_tag
4647                          * was cached. If so, we need to clean up the per-vcpu
4648                          * ir_list.
4649                          */
4650                         if (!ret && pi.prev_ga_tag) {
4651                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4652                                 struct kvm_vcpu *vcpu;
4653
4654                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
4655                                 if (vcpu)
4656                                         svm_ir_list_del(to_svm(vcpu), &pi);
4657                         }
4658                 }
4659
4660                 if (!ret && svm) {
4661                         trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4662                                                  host_irq, e->gsi,
4663                                                  vcpu_info.vector,
4664                                                  vcpu_info.pi_desc_addr, set);
4665                 }
4666
4667                 if (ret < 0) {
4668                         pr_err("%s: failed to update PI IRTE\n", __func__);
4669                         goto out;
4670                 }
4671         }
4672
4673         ret = 0;
4674 out:
4675         srcu_read_unlock(&kvm->irq_srcu, idx);
4676         return ret;
4677 }
4678
4679 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4680 {
4681         struct vcpu_svm *svm = to_svm(vcpu);
4682         struct vmcb *vmcb = svm->vmcb;
4683         int ret;
4684         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4685               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4686         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4687
4688         return ret;
4689 }
4690
4691 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4692 {
4693         struct vcpu_svm *svm = to_svm(vcpu);
4694
4695         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4696 }
4697
4698 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4699 {
4700         struct vcpu_svm *svm = to_svm(vcpu);
4701
4702         if (masked) {
4703                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4704                 set_intercept(svm, INTERCEPT_IRET);
4705         } else {
4706                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4707                 clr_intercept(svm, INTERCEPT_IRET);
4708         }
4709 }
4710
4711 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4712 {
4713         struct vcpu_svm *svm = to_svm(vcpu);
4714         struct vmcb *vmcb = svm->vmcb;
4715         int ret;
4716
4717         if (!gif_set(svm) ||
4718              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4719                 return 0;
4720
4721         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4722
4723         if (is_guest_mode(vcpu))
4724                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4725
4726         return ret;
4727 }
4728
4729 static void enable_irq_window(struct kvm_vcpu *vcpu)
4730 {
4731         struct vcpu_svm *svm = to_svm(vcpu);
4732
4733         if (kvm_vcpu_apicv_active(vcpu))
4734                 return;
4735
4736         /*
4737          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4738          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
4739          * get that intercept, this function will be called again though and
4740          * we'll get the vintr intercept. However, if the vGIF feature is
4741          * enabled, the STGI interception will not occur. Enable the irq
4742          * window under the assumption that the hardware will set the GIF.
4743          */
4744         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
4745                 svm_set_vintr(svm);
4746                 svm_inject_irq(svm, 0x0);
4747         }
4748 }
4749
4750 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4751 {
4752         struct vcpu_svm *svm = to_svm(vcpu);
4753
4754         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4755             == HF_NMI_MASK)
4756                 return; /* IRET will cause a vm exit */
4757
4758         if (!gif_set(svm)) {
4759                 if (vgif_enabled(svm))
4760                         set_intercept(svm, INTERCEPT_STGI);
4761                 return; /* STGI will cause a vm exit */
4762         }
4763
4764         if (svm->nested.exit_required)
4765                 return; /* we're not going to run the guest yet */
4766
4767         /*
4768          * Something prevents NMI from been injected. Single step over possible
4769          * problem (IRET or exception injection or interrupt shadow)
4770          */
4771         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
4772         svm->nmi_singlestep = true;
4773         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4774 }
4775
4776 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4777 {
4778         return 0;
4779 }
4780
4781 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4782 {
4783         struct vcpu_svm *svm = to_svm(vcpu);
4784
4785         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4786                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4787         else
4788                 svm->asid_generation--;
4789 }
4790
4791 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4792 {
4793 }
4794
4795 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4796 {
4797         struct vcpu_svm *svm = to_svm(vcpu);
4798
4799         if (svm_nested_virtualize_tpr(vcpu))
4800                 return;
4801
4802         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4803                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4804                 kvm_set_cr8(vcpu, cr8);
4805         }
4806 }
4807
4808 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4809 {
4810         struct vcpu_svm *svm = to_svm(vcpu);
4811         u64 cr8;
4812
4813         if (svm_nested_virtualize_tpr(vcpu) ||
4814             kvm_vcpu_apicv_active(vcpu))
4815                 return;
4816
4817         cr8 = kvm_get_cr8(vcpu);
4818         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4819         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4820 }
4821
4822 static void svm_complete_interrupts(struct vcpu_svm *svm)
4823 {
4824         u8 vector;
4825         int type;
4826         u32 exitintinfo = svm->vmcb->control.exit_int_info;
4827         unsigned int3_injected = svm->int3_injected;
4828
4829         svm->int3_injected = 0;
4830
4831         /*
4832          * If we've made progress since setting HF_IRET_MASK, we've
4833          * executed an IRET and can allow NMI injection.
4834          */
4835         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4836             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4837                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4838                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4839         }
4840
4841         svm->vcpu.arch.nmi_injected = false;
4842         kvm_clear_exception_queue(&svm->vcpu);
4843         kvm_clear_interrupt_queue(&svm->vcpu);
4844
4845         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4846                 return;
4847
4848         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4849
4850         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4851         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4852
4853         switch (type) {
4854         case SVM_EXITINTINFO_TYPE_NMI:
4855                 svm->vcpu.arch.nmi_injected = true;
4856                 break;
4857         case SVM_EXITINTINFO_TYPE_EXEPT:
4858                 /*
4859                  * In case of software exceptions, do not reinject the vector,
4860                  * but re-execute the instruction instead. Rewind RIP first
4861                  * if we emulated INT3 before.
4862                  */
4863                 if (kvm_exception_is_soft(vector)) {
4864                         if (vector == BP_VECTOR && int3_injected &&
4865                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4866                                 kvm_rip_write(&svm->vcpu,
4867                                               kvm_rip_read(&svm->vcpu) -
4868                                               int3_injected);
4869                         break;
4870                 }
4871                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4872                         u32 err = svm->vmcb->control.exit_int_info_err;
4873                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
4874
4875                 } else
4876                         kvm_requeue_exception(&svm->vcpu, vector);
4877                 break;
4878         case SVM_EXITINTINFO_TYPE_INTR:
4879                 kvm_queue_interrupt(&svm->vcpu, vector, false);
4880                 break;
4881         default:
4882                 break;
4883         }
4884 }
4885
4886 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4887 {
4888         struct vcpu_svm *svm = to_svm(vcpu);
4889         struct vmcb_control_area *control = &svm->vmcb->control;
4890
4891         control->exit_int_info = control->event_inj;
4892         control->exit_int_info_err = control->event_inj_err;
4893         control->event_inj = 0;
4894         svm_complete_interrupts(svm);
4895 }
4896
4897 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4898 {
4899         struct vcpu_svm *svm = to_svm(vcpu);
4900
4901         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4902         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4903         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4904
4905         /*
4906          * A vmexit emulation is required before the vcpu can be executed
4907          * again.
4908          */
4909         if (unlikely(svm->nested.exit_required))
4910                 return;
4911
4912         /*
4913          * Disable singlestep if we're injecting an interrupt/exception.
4914          * We don't want our modified rflags to be pushed on the stack where
4915          * we might not be able to easily reset them if we disabled NMI
4916          * singlestep later.
4917          */
4918         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
4919                 /*
4920                  * Event injection happens before external interrupts cause a
4921                  * vmexit and interrupts are disabled here, so smp_send_reschedule
4922                  * is enough to force an immediate vmexit.
4923                  */
4924                 disable_nmi_singlestep(svm);
4925                 smp_send_reschedule(vcpu->cpu);
4926         }
4927
4928         pre_svm_run(svm);
4929
4930         sync_lapic_to_cr8(vcpu);
4931
4932         svm->vmcb->save.cr2 = vcpu->arch.cr2;
4933
4934         clgi();
4935
4936         local_irq_enable();
4937
4938         asm volatile (
4939                 "push %%" _ASM_BP "; \n\t"
4940                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4941                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4942                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4943                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4944                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4945                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4946 #ifdef CONFIG_X86_64
4947                 "mov %c[r8](%[svm]),  %%r8  \n\t"
4948                 "mov %c[r9](%[svm]),  %%r9  \n\t"
4949                 "mov %c[r10](%[svm]), %%r10 \n\t"
4950                 "mov %c[r11](%[svm]), %%r11 \n\t"
4951                 "mov %c[r12](%[svm]), %%r12 \n\t"
4952                 "mov %c[r13](%[svm]), %%r13 \n\t"
4953                 "mov %c[r14](%[svm]), %%r14 \n\t"
4954                 "mov %c[r15](%[svm]), %%r15 \n\t"
4955 #endif
4956
4957                 /* Enter guest mode */
4958                 "push %%" _ASM_AX " \n\t"
4959                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4960                 __ex(SVM_VMLOAD) "\n\t"
4961                 __ex(SVM_VMRUN) "\n\t"
4962                 __ex(SVM_VMSAVE) "\n\t"
4963                 "pop %%" _ASM_AX " \n\t"
4964
4965                 /* Save guest registers, load host registers */
4966                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4967                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4968                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4969                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4970                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4971                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4972 #ifdef CONFIG_X86_64
4973                 "mov %%r8,  %c[r8](%[svm]) \n\t"
4974                 "mov %%r9,  %c[r9](%[svm]) \n\t"
4975                 "mov %%r10, %c[r10](%[svm]) \n\t"
4976                 "mov %%r11, %c[r11](%[svm]) \n\t"
4977                 "mov %%r12, %c[r12](%[svm]) \n\t"
4978                 "mov %%r13, %c[r13](%[svm]) \n\t"
4979                 "mov %%r14, %c[r14](%[svm]) \n\t"
4980                 "mov %%r15, %c[r15](%[svm]) \n\t"
4981 #endif
4982                 /*
4983                 * Clear host registers marked as clobbered to prevent
4984                 * speculative use.
4985                 */
4986                 "xor %%" _ASM_BX ", %%" _ASM_BX " \n\t"
4987                 "xor %%" _ASM_CX ", %%" _ASM_CX " \n\t"
4988                 "xor %%" _ASM_DX ", %%" _ASM_DX " \n\t"
4989                 "xor %%" _ASM_SI ", %%" _ASM_SI " \n\t"
4990                 "xor %%" _ASM_DI ", %%" _ASM_DI " \n\t"
4991 #ifdef CONFIG_X86_64
4992                 "xor %%r8, %%r8 \n\t"
4993                 "xor %%r9, %%r9 \n\t"
4994                 "xor %%r10, %%r10 \n\t"
4995                 "xor %%r11, %%r11 \n\t"
4996                 "xor %%r12, %%r12 \n\t"
4997                 "xor %%r13, %%r13 \n\t"
4998                 "xor %%r14, %%r14 \n\t"
4999                 "xor %%r15, %%r15 \n\t"
5000 #endif
5001                 "pop %%" _ASM_BP
5002                 :
5003                 : [svm]"a"(svm),
5004                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5005                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5006                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5007                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5008                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5009                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5010                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5011 #ifdef CONFIG_X86_64
5012                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5013                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5014                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5015                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5016                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5017                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5018                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5019                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5020 #endif
5021                 : "cc", "memory"
5022 #ifdef CONFIG_X86_64
5023                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5024                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5025 #else
5026                 , "ebx", "ecx", "edx", "esi", "edi"
5027 #endif
5028                 );
5029
5030 #ifdef CONFIG_X86_64
5031         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5032 #else
5033         loadsegment(fs, svm->host.fs);
5034 #ifndef CONFIG_X86_32_LAZY_GS
5035         loadsegment(gs, svm->host.gs);
5036 #endif
5037 #endif
5038
5039         reload_tss(vcpu);
5040
5041         local_irq_disable();
5042
5043         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5044         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5045         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5046         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5047
5048         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5049                 kvm_before_handle_nmi(&svm->vcpu);
5050
5051         stgi();
5052
5053         /* Any pending NMI will happen here */
5054
5055         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5056                 kvm_after_handle_nmi(&svm->vcpu);
5057
5058         sync_cr8_to_lapic(vcpu);
5059
5060         svm->next_rip = 0;
5061
5062         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5063
5064         /* if exit due to PF check for async PF */
5065         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5066                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5067
5068         if (npt_enabled) {
5069                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5070                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5071         }
5072
5073         /*
5074          * We need to handle MC intercepts here before the vcpu has a chance to
5075          * change the physical cpu
5076          */
5077         if (unlikely(svm->vmcb->control.exit_code ==
5078                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5079                 svm_handle_mce(svm);
5080
5081         mark_all_clean(svm->vmcb);
5082 }
5083 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5084
5085 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5086 {
5087         struct vcpu_svm *svm = to_svm(vcpu);
5088
5089         svm->vmcb->save.cr3 = __sme_set(root);
5090         mark_dirty(svm->vmcb, VMCB_CR);
5091         svm_flush_tlb(vcpu);
5092 }
5093
5094 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5095 {
5096         struct vcpu_svm *svm = to_svm(vcpu);
5097
5098         svm->vmcb->control.nested_cr3 = __sme_set(root);
5099         mark_dirty(svm->vmcb, VMCB_NPT);
5100
5101         /* Also sync guest cr3 here in case we live migrate */
5102         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5103         mark_dirty(svm->vmcb, VMCB_CR);
5104
5105         svm_flush_tlb(vcpu);
5106 }
5107
5108 static int is_disabled(void)
5109 {
5110         u64 vm_cr;
5111
5112         rdmsrl(MSR_VM_CR, vm_cr);
5113         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5114                 return 1;
5115
5116         return 0;
5117 }
5118
5119 static void
5120 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5121 {
5122         /*
5123          * Patch in the VMMCALL instruction:
5124          */
5125         hypercall[0] = 0x0f;
5126         hypercall[1] = 0x01;
5127         hypercall[2] = 0xd9;
5128 }
5129
5130 static void svm_check_processor_compat(void *rtn)
5131 {
5132         *(int *)rtn = 0;
5133 }
5134
5135 static bool svm_cpu_has_accelerated_tpr(void)
5136 {
5137         return false;
5138 }
5139
5140 static bool svm_has_high_real_mode_segbase(void)
5141 {
5142         return true;
5143 }
5144
5145 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5146 {
5147         return 0;
5148 }
5149
5150 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5151 {
5152         struct vcpu_svm *svm = to_svm(vcpu);
5153
5154         /* Update nrips enabled cache */
5155         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5156
5157         if (!kvm_vcpu_apicv_active(vcpu))
5158                 return;
5159
5160         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5161 }
5162
5163 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5164 {
5165         switch (func) {
5166         case 0x1:
5167                 if (avic)
5168                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5169                 break;
5170         case 0x80000001:
5171                 if (nested)
5172                         entry->ecx |= (1 << 2); /* Set SVM bit */
5173                 break;
5174         case 0x8000000A:
5175                 entry->eax = 1; /* SVM revision 1 */
5176                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5177                                    ASID emulation to nested SVM */
5178                 entry->ecx = 0; /* Reserved */
5179                 entry->edx = 0; /* Per default do not support any
5180                                    additional features */
5181
5182                 /* Support next_rip if host supports it */
5183                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5184                         entry->edx |= SVM_FEATURE_NRIP;
5185
5186                 /* Support NPT for the guest if enabled */
5187                 if (npt_enabled)
5188                         entry->edx |= SVM_FEATURE_NPT;
5189
5190                 break;
5191         }
5192 }
5193
5194 static int svm_get_lpage_level(void)
5195 {
5196         return PT_PDPE_LEVEL;
5197 }
5198
5199 static bool svm_rdtscp_supported(void)
5200 {
5201         return boot_cpu_has(X86_FEATURE_RDTSCP);
5202 }
5203
5204 static bool svm_invpcid_supported(void)
5205 {
5206         return false;
5207 }
5208
5209 static bool svm_mpx_supported(void)
5210 {
5211         return false;
5212 }
5213
5214 static bool svm_xsaves_supported(void)
5215 {
5216         return false;
5217 }
5218
5219 static bool svm_has_wbinvd_exit(void)
5220 {
5221         return true;
5222 }
5223
5224 #define PRE_EX(exit)  { .exit_code = (exit), \
5225                         .stage = X86_ICPT_PRE_EXCEPT, }
5226 #define POST_EX(exit) { .exit_code = (exit), \
5227                         .stage = X86_ICPT_POST_EXCEPT, }
5228 #define POST_MEM(exit) { .exit_code = (exit), \
5229                         .stage = X86_ICPT_POST_MEMACCESS, }
5230
5231 static const struct __x86_intercept {
5232         u32 exit_code;
5233         enum x86_intercept_stage stage;
5234 } x86_intercept_map[] = {
5235         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5236         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5237         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5238         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5239         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5240         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5241         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5242         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5243         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5244         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5245         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5246         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5247         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5248         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5249         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5250         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5251         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5252         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5253         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5254         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5255         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5256         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5257         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5258         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5259         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5260         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5261         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5262         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5263         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5264         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5265         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5266         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5267         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5268         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5269         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5270         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5271         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5272         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5273         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5274         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5275         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5276         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5277         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5278         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5279         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5280         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5281 };
5282
5283 #undef PRE_EX
5284 #undef POST_EX
5285 #undef POST_MEM
5286
5287 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5288                                struct x86_instruction_info *info,
5289                                enum x86_intercept_stage stage)
5290 {
5291         struct vcpu_svm *svm = to_svm(vcpu);
5292         int vmexit, ret = X86EMUL_CONTINUE;
5293         struct __x86_intercept icpt_info;
5294         struct vmcb *vmcb = svm->vmcb;
5295
5296         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5297                 goto out;
5298
5299         icpt_info = x86_intercept_map[info->intercept];
5300
5301         if (stage != icpt_info.stage)
5302                 goto out;
5303
5304         switch (icpt_info.exit_code) {
5305         case SVM_EXIT_READ_CR0:
5306                 if (info->intercept == x86_intercept_cr_read)
5307                         icpt_info.exit_code += info->modrm_reg;
5308                 break;
5309         case SVM_EXIT_WRITE_CR0: {
5310                 unsigned long cr0, val;
5311                 u64 intercept;
5312
5313                 if (info->intercept == x86_intercept_cr_write)
5314                         icpt_info.exit_code += info->modrm_reg;
5315
5316                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5317                     info->intercept == x86_intercept_clts)
5318                         break;
5319
5320                 intercept = svm->nested.intercept;
5321
5322                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5323                         break;
5324
5325                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5326                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
5327
5328                 if (info->intercept == x86_intercept_lmsw) {
5329                         cr0 &= 0xfUL;
5330                         val &= 0xfUL;
5331                         /* lmsw can't clear PE - catch this here */
5332                         if (cr0 & X86_CR0_PE)
5333                                 val |= X86_CR0_PE;
5334                 }
5335
5336                 if (cr0 ^ val)
5337                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5338
5339                 break;
5340         }
5341         case SVM_EXIT_READ_DR0:
5342         case SVM_EXIT_WRITE_DR0:
5343                 icpt_info.exit_code += info->modrm_reg;
5344                 break;
5345         case SVM_EXIT_MSR:
5346                 if (info->intercept == x86_intercept_wrmsr)
5347                         vmcb->control.exit_info_1 = 1;
5348                 else
5349                         vmcb->control.exit_info_1 = 0;
5350                 break;
5351         case SVM_EXIT_PAUSE:
5352                 /*
5353                  * We get this for NOP only, but pause
5354                  * is rep not, check this here
5355                  */
5356                 if (info->rep_prefix != REPE_PREFIX)
5357                         goto out;
5358                 break;
5359         case SVM_EXIT_IOIO: {
5360                 u64 exit_info;
5361                 u32 bytes;
5362
5363                 if (info->intercept == x86_intercept_in ||
5364                     info->intercept == x86_intercept_ins) {
5365                         exit_info = ((info->src_val & 0xffff) << 16) |
5366                                 SVM_IOIO_TYPE_MASK;
5367                         bytes = info->dst_bytes;
5368                 } else {
5369                         exit_info = (info->dst_val & 0xffff) << 16;
5370                         bytes = info->src_bytes;
5371                 }
5372
5373                 if (info->intercept == x86_intercept_outs ||
5374                     info->intercept == x86_intercept_ins)
5375                         exit_info |= SVM_IOIO_STR_MASK;
5376
5377                 if (info->rep_prefix)
5378                         exit_info |= SVM_IOIO_REP_MASK;
5379
5380                 bytes = min(bytes, 4u);
5381
5382                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5383
5384                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5385
5386                 vmcb->control.exit_info_1 = exit_info;
5387                 vmcb->control.exit_info_2 = info->next_rip;
5388
5389                 break;
5390         }
5391         default:
5392                 break;
5393         }
5394
5395         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5396         if (static_cpu_has(X86_FEATURE_NRIPS))
5397                 vmcb->control.next_rip  = info->next_rip;
5398         vmcb->control.exit_code = icpt_info.exit_code;
5399         vmexit = nested_svm_exit_handled(svm);
5400
5401         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5402                                            : X86EMUL_CONTINUE;
5403
5404 out:
5405         return ret;
5406 }
5407
5408 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5409 {
5410         local_irq_enable();
5411         /*
5412          * We must have an instruction with interrupts enabled, so
5413          * the timer interrupt isn't delayed by the interrupt shadow.
5414          */
5415         asm("nop");
5416         local_irq_disable();
5417 }
5418
5419 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5420 {
5421 }
5422
5423 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5424 {
5425         if (avic_handle_apic_id_update(vcpu) != 0)
5426                 return;
5427         if (avic_handle_dfr_update(vcpu) != 0)
5428                 return;
5429         avic_handle_ldr_update(vcpu);
5430 }
5431
5432 static void svm_setup_mce(struct kvm_vcpu *vcpu)
5433 {
5434         /* [63:9] are reserved. */
5435         vcpu->arch.mcg_cap &= 0x1ff;
5436 }
5437
5438 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
5439 {
5440         struct vcpu_svm *svm = to_svm(vcpu);
5441
5442         /* Per APM Vol.2 15.22.2 "Response to SMI" */
5443         if (!gif_set(svm))
5444                 return 0;
5445
5446         if (is_guest_mode(&svm->vcpu) &&
5447             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
5448                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
5449                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
5450                 svm->nested.exit_required = true;
5451                 return 0;
5452         }
5453
5454         return 1;
5455 }
5456
5457 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
5458 {
5459         struct vcpu_svm *svm = to_svm(vcpu);
5460         int ret;
5461
5462         if (is_guest_mode(vcpu)) {
5463                 /* FED8h - SVM Guest */
5464                 put_smstate(u64, smstate, 0x7ed8, 1);
5465                 /* FEE0h - SVM Guest VMCB Physical Address */
5466                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
5467
5468                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5469                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5470                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5471
5472                 ret = nested_svm_vmexit(svm);
5473                 if (ret)
5474                         return ret;
5475         }
5476         return 0;
5477 }
5478
5479 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
5480 {
5481         struct vcpu_svm *svm = to_svm(vcpu);
5482         struct vmcb *nested_vmcb;
5483         struct page *page;
5484         struct {
5485                 u64 guest;
5486                 u64 vmcb;
5487         } svm_state_save;
5488         int ret;
5489
5490         ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
5491                                   sizeof(svm_state_save));
5492         if (ret)
5493                 return ret;
5494
5495         if (svm_state_save.guest) {
5496                 vcpu->arch.hflags &= ~HF_SMM_MASK;
5497                 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
5498                 if (nested_vmcb)
5499                         enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
5500                 else
5501                         ret = 1;
5502                 vcpu->arch.hflags |= HF_SMM_MASK;
5503         }
5504         return ret;
5505 }
5506
5507 static int enable_smi_window(struct kvm_vcpu *vcpu)
5508 {
5509         struct vcpu_svm *svm = to_svm(vcpu);
5510
5511         if (!gif_set(svm)) {
5512                 if (vgif_enabled(svm))
5513                         set_intercept(svm, INTERCEPT_STGI);
5514                 /* STGI will cause a vm exit */
5515                 return 1;
5516         }
5517         return 0;
5518 }
5519
5520 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5521         .cpu_has_kvm_support = has_svm,
5522         .disabled_by_bios = is_disabled,
5523         .hardware_setup = svm_hardware_setup,
5524         .hardware_unsetup = svm_hardware_unsetup,
5525         .check_processor_compatibility = svm_check_processor_compat,
5526         .hardware_enable = svm_hardware_enable,
5527         .hardware_disable = svm_hardware_disable,
5528         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5529         .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5530
5531         .vcpu_create = svm_create_vcpu,
5532         .vcpu_free = svm_free_vcpu,
5533         .vcpu_reset = svm_vcpu_reset,
5534
5535         .vm_init = avic_vm_init,
5536         .vm_destroy = avic_vm_destroy,
5537
5538         .prepare_guest_switch = svm_prepare_guest_switch,
5539         .vcpu_load = svm_vcpu_load,
5540         .vcpu_put = svm_vcpu_put,
5541         .vcpu_blocking = svm_vcpu_blocking,
5542         .vcpu_unblocking = svm_vcpu_unblocking,
5543
5544         .update_bp_intercept = update_bp_intercept,
5545         .get_msr = svm_get_msr,
5546         .set_msr = svm_set_msr,
5547         .get_segment_base = svm_get_segment_base,
5548         .get_segment = svm_get_segment,
5549         .set_segment = svm_set_segment,
5550         .get_cpl = svm_get_cpl,
5551         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5552         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5553         .decache_cr3 = svm_decache_cr3,
5554         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5555         .set_cr0 = svm_set_cr0,
5556         .set_cr3 = svm_set_cr3,
5557         .set_cr4 = svm_set_cr4,
5558         .set_efer = svm_set_efer,
5559         .get_idt = svm_get_idt,
5560         .set_idt = svm_set_idt,
5561         .get_gdt = svm_get_gdt,
5562         .set_gdt = svm_set_gdt,
5563         .get_dr6 = svm_get_dr6,
5564         .set_dr6 = svm_set_dr6,
5565         .set_dr7 = svm_set_dr7,
5566         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5567         .cache_reg = svm_cache_reg,
5568         .get_rflags = svm_get_rflags,
5569         .set_rflags = svm_set_rflags,
5570
5571         .tlb_flush = svm_flush_tlb,
5572
5573         .run = svm_vcpu_run,
5574         .handle_exit = handle_exit,
5575         .skip_emulated_instruction = skip_emulated_instruction,
5576         .set_interrupt_shadow = svm_set_interrupt_shadow,
5577         .get_interrupt_shadow = svm_get_interrupt_shadow,
5578         .patch_hypercall = svm_patch_hypercall,
5579         .set_irq = svm_set_irq,
5580         .set_nmi = svm_inject_nmi,
5581         .queue_exception = svm_queue_exception,
5582         .cancel_injection = svm_cancel_injection,
5583         .interrupt_allowed = svm_interrupt_allowed,
5584         .nmi_allowed = svm_nmi_allowed,
5585         .get_nmi_mask = svm_get_nmi_mask,
5586         .set_nmi_mask = svm_set_nmi_mask,
5587         .enable_nmi_window = enable_nmi_window,
5588         .enable_irq_window = enable_irq_window,
5589         .update_cr8_intercept = update_cr8_intercept,
5590         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5591         .get_enable_apicv = svm_get_enable_apicv,
5592         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5593         .load_eoi_exitmap = svm_load_eoi_exitmap,
5594         .hwapic_irr_update = svm_hwapic_irr_update,
5595         .hwapic_isr_update = svm_hwapic_isr_update,
5596         .apicv_post_state_restore = avic_post_state_restore,
5597
5598         .set_tss_addr = svm_set_tss_addr,
5599         .get_tdp_level = get_npt_level,
5600         .get_mt_mask = svm_get_mt_mask,
5601
5602         .get_exit_info = svm_get_exit_info,
5603
5604         .get_lpage_level = svm_get_lpage_level,
5605
5606         .cpuid_update = svm_cpuid_update,
5607
5608         .rdtscp_supported = svm_rdtscp_supported,
5609         .invpcid_supported = svm_invpcid_supported,
5610         .mpx_supported = svm_mpx_supported,
5611         .xsaves_supported = svm_xsaves_supported,
5612
5613         .set_supported_cpuid = svm_set_supported_cpuid,
5614
5615         .has_wbinvd_exit = svm_has_wbinvd_exit,
5616
5617         .write_tsc_offset = svm_write_tsc_offset,
5618
5619         .set_tdp_cr3 = set_tdp_cr3,
5620
5621         .check_intercept = svm_check_intercept,
5622         .handle_external_intr = svm_handle_external_intr,
5623
5624         .sched_in = svm_sched_in,
5625
5626         .pmu_ops = &amd_pmu_ops,
5627         .deliver_posted_interrupt = svm_deliver_avic_intr,
5628         .update_pi_irte = svm_update_pi_irte,
5629         .setup_mce = svm_setup_mce,
5630
5631         .smi_allowed = svm_smi_allowed,
5632         .pre_enter_smm = svm_pre_enter_smm,
5633         .pre_leave_smm = svm_pre_leave_smm,
5634         .enable_smi_window = enable_smi_window,
5635 };
5636
5637 static int __init svm_init(void)
5638 {
5639         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5640                         __alignof__(struct vcpu_svm), THIS_MODULE);
5641 }
5642
5643 static void __exit svm_exit(void)
5644 {
5645         kvm_exit();
5646 }
5647
5648 module_init(svm_init)
5649 module_exit(svm_exit)